Mercurial > mplayer.hg
annotate cpudetect.c @ 28402:c884d17bd005
Convert HAVE_WINSOCK2_H into a 0/1 definition.
author | diego |
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date | Sun, 01 Feb 2009 13:42:27 +0000 |
parents | 3e3bd9da4c7e |
children | 6629e391d52d |
rev | line source |
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1 #include "config.h" |
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2 #include "cpudetect.h" |
5937 | 3 #include "mp_msg.h" |
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4 |
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5 CpuCaps gCpuCaps; |
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6 |
3837 | 7 #ifdef HAVE_MALLOC_H |
8 #include <malloc.h> | |
9 #endif | |
10 #include <stdlib.h> | |
11 | |
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12 #if ARCH_X86 |
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13 |
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14 #include <stdio.h> |
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15 #include <string.h> |
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16 |
12143 | 17 #if defined (__NetBSD__) || defined(__OpenBSD__) |
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18 #include <sys/param.h> |
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19 #include <sys/sysctl.h> |
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20 #include <machine/cpu.h> |
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21 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__) |
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22 #include <sys/types.h> |
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23 #include <sys/sysctl.h> |
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24 #elif defined(__linux__) |
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25 #include <signal.h> |
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26 #elif defined(__MINGW32__) || defined(__CYGWIN__) |
10440 | 27 #include <windows.h> |
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28 #elif defined(__OS2__) |
26061 | 29 #define INCL_DOS |
30 #include <os2.h> | |
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31 #elif defined(__AMIGAOS4__) |
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32 #include <proto/exec.h> |
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33 #endif |
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34 |
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35 /* Thanks to the FreeBSD project for some of this cpuid code, and |
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36 * help understanding how to use it. Thanks to the Mesa |
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37 * team for SSE support detection and more cpu detect code. |
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38 */ |
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39 |
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40 /* I believe this code works. However, it has only been used on a PII and PIII */ |
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41 |
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42 static void check_os_katmai_support( void ); |
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43 |
2272 | 44 // return TRUE if cpuid supported |
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45 static int has_cpuid(void) |
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46 { |
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47 long a, c; |
2272 | 48 |
49 // code from libavcodec: | |
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50 #if ARCH_X86_64 |
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51 #define PUSHF "pushfq\n\t" |
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52 #define POPF "popfq\n\t" |
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53 #else |
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54 #define PUSHF "pushfl\n\t" |
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55 #define POPF "popfl\n\t" |
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56 #endif |
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57 __asm__ volatile ( |
2272 | 58 /* See if CPUID instruction is supported ... */ |
59 /* ... Get copies of EFLAGS into eax and ecx */ | |
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60 PUSHF |
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61 "pop %0\n\t" |
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62 "mov %0, %1\n\t" |
2272 | 63 |
64 /* ... Toggle the ID bit in one copy and store */ | |
65 /* to the EFLAGS reg */ | |
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66 "xor $0x200000, %0\n\t" |
2272 | 67 "push %0\n\t" |
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68 POPF |
2272 | 69 |
70 /* ... Get the (hopefully modified) EFLAGS */ | |
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71 PUSHF |
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72 "pop %0\n\t" |
2272 | 73 : "=a" (a), "=c" (c) |
74 : | |
75 : "cc" | |
76 ); | |
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77 #undef PUSHF |
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78 #undef POPF |
2272 | 79 |
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80 return a != c; |
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81 } |
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82 |
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83 static void |
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84 do_cpuid(unsigned int ax, unsigned int *p) |
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85 { |
2272 | 86 #if 0 |
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87 __asm__ volatile( |
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88 "cpuid;" |
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89 : "=a" (p[0]), "=b" (p[1]), "=c" (p[2]), "=d" (p[3]) |
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90 : "0" (ax) |
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91 ); |
2272 | 92 #else |
93 // code from libavcodec: | |
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94 __asm__ volatile |
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95 ("mov %%"REG_b", %%"REG_S"\n\t" |
2272 | 96 "cpuid\n\t" |
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97 "xchg %%"REG_b", %%"REG_S |
3403 | 98 : "=a" (p[0]), "=S" (p[1]), |
2272 | 99 "=c" (p[2]), "=d" (p[3]) |
100 : "0" (ax)); | |
101 #endif | |
102 | |
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103 } |
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104 |
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105 void GetCpuCaps( CpuCaps *caps) |
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106 { |
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107 unsigned int regs[4]; |
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108 unsigned int regs2[4]; |
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109 |
8860 | 110 memset(caps, 0, sizeof(*caps)); |
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111 caps->isX86=1; |
8860 | 112 caps->cl_size=32; /* default */ |
2288 | 113 if (!has_cpuid()) { |
6134 | 114 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"CPUID not supported!??? (maybe an old 486?)\n"); |
2288 | 115 return; |
116 } | |
117 do_cpuid(0x00000000, regs); // get _max_ cpuid level and vendor name | |
6134 | 118 mp_msg(MSGT_CPUDETECT,MSGL_V,"CPU vendor name: %.4s%.4s%.4s max cpuid level: %d\n", |
3837 | 119 (char*) (regs+1),(char*) (regs+3),(char*) (regs+2), regs[0]); |
2288 | 120 if (regs[0]>=0x00000001) |
2280 | 121 { |
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122 char *tmpstr, *ptmpstr; |
8860 | 123 unsigned cl_size; |
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124 |
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125 do_cpuid(0x00000001, regs2); |
2301 | 126 |
2288 | 127 caps->cpuType=(regs2[0] >> 8)&0xf; |
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128 caps->cpuModel=(regs2[0] >> 4)&0xf; |
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129 |
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130 // see AMD64 Architecture Programmer's Manual, Volume 3: General-purpose and |
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131 // System Instructions, Table 3-2: Effective family computation, page 120. |
2288 | 132 if(caps->cpuType==0xf){ |
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133 // use extended family (P4, IA64, K8) |
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134 caps->cpuType=0xf+((regs2[0]>>20)&255); |
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135 } |
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136 if(caps->cpuType==0xf || caps->cpuType==6) |
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137 caps->cpuModel |= ((regs2[0]>>16)&0xf) << 4; |
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138 |
3403 | 139 caps->cpuStepping=regs2[0] & 0xf; |
2288 | 140 |
141 // general feature flags: | |
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142 caps->hasTSC = (regs2[3] & (1 << 8 )) >> 8; // 0x0000010 |
2272 | 143 caps->hasMMX = (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 |
144 caps->hasSSE = (regs2[3] & (1 << 25 )) >> 25; // 0x2000000 | |
145 caps->hasSSE2 = (regs2[3] & (1 << 26 )) >> 26; // 0x4000000 | |
28015 | 146 caps->hasSSSE3 = (regs2[2] & (1 << 9 )) >> 9; // 0x0000200 |
2288 | 147 caps->hasMMX2 = caps->hasSSE; // SSE cpus supports mmxext too |
8860 | 148 cl_size = ((regs2[1] >> 8) & 0xFF)*8; |
149 if(cl_size) caps->cl_size = cl_size; | |
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150 |
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151 ptmpstr=tmpstr=GetCpuFriendlyName(regs, regs2); |
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152 while(*ptmpstr == ' ') // strip leading spaces |
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153 ptmpstr++; |
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154 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: %s ", ptmpstr); |
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155 free(tmpstr); |
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156 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"(Family: %d, Model: %d, Stepping: %d)\n", |
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157 caps->cpuType, caps->cpuModel, caps->cpuStepping); |
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158 |
2288 | 159 } |
160 do_cpuid(0x80000000, regs); | |
161 if (regs[0]>=0x80000001) { | |
6134 | 162 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cpuid-level: %d\n",regs[0]&0x7FFFFFFF); |
2288 | 163 do_cpuid(0x80000001, regs2); |
3840 | 164 caps->hasMMX |= (regs2[3] & (1 << 23 )) >> 23; // 0x0800000 |
165 caps->hasMMX2 |= (regs2[3] & (1 << 22 )) >> 22; // 0x400000 | |
2288 | 166 caps->has3DNow = (regs2[3] & (1 << 31 )) >> 31; //0x80000000 |
167 caps->has3DNowExt = (regs2[3] & (1 << 30 )) >> 30; | |
28015 | 168 caps->hasSSE4a = (regs2[2] & (1 << 6 )) >> 6; // 0x0000040 |
2288 | 169 } |
8860 | 170 if(regs[0]>=0x80000006) |
171 { | |
172 do_cpuid(0x80000006, regs2); | |
173 mp_msg(MSGT_CPUDETECT,MSGL_V,"extended cache-info: %d\n",regs2[2]&0x7FFFFFFF); | |
174 caps->cl_size = regs2[2] & 0xFF; | |
175 } | |
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176 mp_msg(MSGT_CPUDETECT,MSGL_V,"Detected cache-line size is %u bytes\n",caps->cl_size); |
2288 | 177 #if 0 |
5937 | 178 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"cpudetect: MMX=%d MMX2=%d SSE=%d SSE2=%d 3DNow=%d 3DNowExt=%d\n", |
2288 | 179 gCpuCaps.hasMMX, |
180 gCpuCaps.hasMMX2, | |
181 gCpuCaps.hasSSE, | |
182 gCpuCaps.hasSSE2, | |
183 gCpuCaps.has3DNow, | |
184 gCpuCaps.has3DNowExt ); | |
185 #endif | |
186 | |
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187 /* FIXME: Does SSE2 need more OS support, too? */ |
26060 | 188 #if defined(__linux__) || defined(__FreeBSD__) || defined(__FreeBSD_kernel__) \ |
189 || defined(__NetBSD__) || defined(__OpenBSD__) || defined(__DragonFly__) \ | |
26061 | 190 || defined(__APPLE__) || defined(__CYGWIN__) || defined(__MINGW32__) \ |
191 || defined(__OS2__) | |
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192 if (caps->hasSSE) |
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193 check_os_katmai_support(); |
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194 if (!caps->hasSSE) |
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195 caps->hasSSE2 = 0; |
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196 #else |
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197 caps->hasSSE=0; |
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198 caps->hasSSE2 = 0; |
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199 #endif |
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200 // caps->has3DNow=1; |
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201 // caps->hasMMX2 = 0; |
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202 // caps->hasMMX = 0; |
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203 |
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204 #ifndef RUNTIME_CPUDETECT |
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205 #if !HAVE_MMX |
6134 | 206 if(caps->hasMMX) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX supported but disabled\n"); |
4829 | 207 caps->hasMMX=0; |
208 #endif | |
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209 #if !HAVE_MMX2 |
6134 | 210 if(caps->hasMMX2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"MMX2 supported but disabled\n"); |
4829 | 211 caps->hasMMX2=0; |
212 #endif | |
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213 #if !HAVE_SSE |
6134 | 214 if(caps->hasSSE) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE supported but disabled\n"); |
4829 | 215 caps->hasSSE=0; |
216 #endif | |
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217 #if !HAVE_SSE2 |
6134 | 218 if(caps->hasSSE2) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"SSE2 supported but disabled\n"); |
4829 | 219 caps->hasSSE2=0; |
220 #endif | |
28335 | 221 #if !HAVE_AMD3DNOW |
6134 | 222 if(caps->has3DNow) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNow supported but disabled\n"); |
4829 | 223 caps->has3DNow=0; |
224 #endif | |
28335 | 225 #if !HAVE_AMD3DNOWEXT |
6134 | 226 if(caps->has3DNowExt) mp_msg(MSGT_CPUDETECT,MSGL_WARN,"3DNowExt supported but disabled\n"); |
4829 | 227 caps->has3DNowExt=0; |
228 #endif | |
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229 #endif // RUNTIME_CPUDETECT |
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230 } |
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231 |
2301 | 232 |
233 #define CPUID_EXTFAMILY ((regs2[0] >> 20)&0xFF) /* 27..20 */ | |
234 #define CPUID_EXTMODEL ((regs2[0] >> 16)&0x0F) /* 19..16 */ | |
235 #define CPUID_TYPE ((regs2[0] >> 12)&0x04) /* 13..12 */ | |
236 #define CPUID_FAMILY ((regs2[0] >> 8)&0x0F) /* 11..08 */ | |
237 #define CPUID_MODEL ((regs2[0] >> 4)&0x0F) /* 07..04 */ | |
238 #define CPUID_STEPPING ((regs2[0] >> 0)&0x0F) /* 03..00 */ | |
239 | |
240 char *GetCpuFriendlyName(unsigned int regs[], unsigned int regs2[]){ | |
241 #include "cputable.h" /* get cpuname and cpuvendors */ | |
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242 char vendor[13]; |
2303 | 243 char *retname; |
13628 | 244 int i; |
2301 | 245 |
18869 | 246 if (NULL==(retname=malloc(256))) { |
5937 | 247 mp_msg(MSGT_CPUDETECT,MSGL_FATAL,"Error: GetCpuFriendlyName() not enough memory\n"); |
2303 | 248 exit(1); |
249 } | |
250 | |
3837 | 251 sprintf(vendor,"%.4s%.4s%.4s",(char*)(regs+1),(char*)(regs+3),(char*)(regs+2)); |
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252 |
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253 do_cpuid(0x80000000,regs); |
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254 if (regs[0] >= 0x80000004) |
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255 { |
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256 // CPU has built-in namestring |
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257 retname[0] = '\0'; |
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258 for (i = 0x80000002; i <= 0x80000004; i++) |
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259 { |
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260 do_cpuid(i, regs); |
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261 strncat(retname, (char*)regs, 16); |
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262 } |
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263 return retname; |
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264 } |
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265 |
2301 | 266 for(i=0; i<MAX_VENDORS; i++){ |
267 if(!strcmp(cpuvendors[i].string,vendor)){ | |
268 if(cpuname[i][CPUID_FAMILY][CPUID_MODEL]){ | |
13628 | 269 snprintf(retname,255,"%s %s",cpuvendors[i].name,cpuname[i][CPUID_FAMILY][CPUID_MODEL]); |
2301 | 270 } else { |
13628 | 271 snprintf(retname,255,"unknown %s %d. Generation CPU",cpuvendors[i].name,CPUID_FAMILY); |
5937 | 272 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"unknown %s CPU:\n",cpuvendors[i].name); |
273 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Vendor: %s\n",cpuvendors[i].string); | |
274 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Type: %d\n",CPUID_TYPE); | |
275 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Family: %d (ext: %d)\n",CPUID_FAMILY,CPUID_EXTFAMILY); | |
276 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Model: %d (ext: %d)\n",CPUID_MODEL,CPUID_EXTMODEL); | |
277 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Stepping: %d\n",CPUID_STEPPING); | |
278 mp_msg(MSGT_CPUDETECT,MSGL_WARN,"Please send the above info along with the exact CPU name" | |
2301 | 279 "to the MPlayer-Developers, so we can add it to the list!\n"); |
280 } | |
281 } | |
282 } | |
14478 | 283 retname[255] = 0; |
2301 | 284 |
285 //printf("Detected CPU: %s\n", retname); | |
286 return retname; | |
287 } | |
288 | |
289 #undef CPUID_EXTFAMILY | |
290 #undef CPUID_EXTMODEL | |
291 #undef CPUID_TYPE | |
292 #undef CPUID_FAMILY | |
293 #undef CPUID_MODEL | |
294 #undef CPUID_STEPPING | |
295 | |
296 | |
28295 | 297 #if defined(__linux__) && defined(_POSIX_SOURCE) && !ARCH_X86_64 |
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298 static void sigill_handler_sse( int signal, struct sigcontext sc ) |
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299 { |
6134 | 300 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); |
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301 |
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302 /* Both the "xorps %%xmm0,%%xmm0" and "divps %xmm0,%%xmm1" |
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303 * instructions are 3 bytes long. We must increment the instruction |
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304 * pointer manually to avoid repeated execution of the offending |
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305 * instruction. |
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306 * |
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307 * If the SIGILL is caused by a divide-by-zero when unmasked |
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308 * exceptions aren't supported, the SIMD FPU status and control |
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309 * word will be restored at the end of the test, so we don't need |
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310 * to worry about doing it here. Besides, we may not be able to... |
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311 */ |
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312 sc.eip += 3; |
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313 |
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314 gCpuCaps.hasSSE=0; |
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315 } |
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316 #endif /* __linux__ && _POSIX_SOURCE */ |
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317 |
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318 #if defined(__MINGW32__) || defined(__CYGWIN__) |
10440 | 319 LONG CALLBACK win32_sig_handler_sse(EXCEPTION_POINTERS* ep) |
320 { | |
321 if(ep->ExceptionRecord->ExceptionCode==EXCEPTION_ILLEGAL_INSTRUCTION){ | |
322 mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGILL, " ); | |
323 ep->ContextRecord->Eip +=3; | |
324 gCpuCaps.hasSSE=0; | |
325 return EXCEPTION_CONTINUE_EXECUTION; | |
326 } | |
327 return EXCEPTION_CONTINUE_SEARCH; | |
328 } | |
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329 #endif /* defined(__MINGW32__) || defined(__CYGWIN__) */ |
10440 | 330 |
26061 | 331 #ifdef __OS2__ |
332 ULONG _System os2_sig_handler_sse( PEXCEPTIONREPORTRECORD p1, | |
333 PEXCEPTIONREGISTRATIONRECORD p2, | |
334 PCONTEXTRECORD p3, | |
335 PVOID p4 ) | |
336 { | |
337 if(p1->ExceptionNum == XCPT_ILLEGAL_INSTRUCTION){ | |
338 mp_msg(MSGT_CPUDETECT, MSGL_V, "SIGILL, "); | |
339 | |
340 p3->ctx_RegEip += 3; | |
341 gCpuCaps.hasSSE = 0; | |
342 | |
343 return XCPT_CONTINUE_EXECUTION; | |
344 } | |
345 return XCPT_CONTINUE_SEARCH; | |
346 } | |
347 #endif | |
348 | |
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349 /* If we're running on a processor that can do SSE, let's see if we |
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350 * are allowed to or not. This will catch 2.4.0 or later kernels that |
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351 * haven't been configured for a Pentium III but are running on one, |
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352 * and RedHat patched 2.2 kernels that have broken exception handling |
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353 * support for user space apps that do SSE. |
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354 */ |
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355 |
21848 | 356 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) |
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357 #define SSE_SYSCTL_NAME "hw.instruction_sse" |
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358 #elif defined(__APPLE__) |
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359 #define SSE_SYSCTL_NAME "hw.optional.sse" |
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360 #endif |
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361 |
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362 static void check_os_katmai_support( void ) |
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363 { |
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364 #if ARCH_X86_64 |
14455 | 365 gCpuCaps.hasSSE=1; |
366 gCpuCaps.hasSSE2=1; | |
21848 | 367 #elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__DragonFly__) || defined(__APPLE__) |
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368 int has_sse=0, ret; |
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369 size_t len=sizeof(has_sse); |
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370 |
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371 ret = sysctlbyname(SSE_SYSCTL_NAME, &has_sse, &len, NULL, 0); |
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372 if (ret || !has_sse) |
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373 gCpuCaps.hasSSE=0; |
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374 |
12143 | 375 #elif defined(__NetBSD__) || defined (__OpenBSD__) |
376 #if __NetBSD_Version__ >= 105250000 || (defined __OpenBSD__) | |
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377 int has_sse, has_sse2, ret, mib[2]; |
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378 size_t varlen; |
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379 |
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380 mib[0] = CTL_MACHDEP; |
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381 mib[1] = CPU_SSE; |
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382 varlen = sizeof(has_sse); |
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383 |
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384 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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385 ret = sysctl(mib, 2, &has_sse, &varlen, NULL, 0); |
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386 gCpuCaps.hasSSE = ret >= 0 && has_sse; |
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387 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
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388 |
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389 mib[1] = CPU_SSE2; |
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Ok, here is a better patch, which even adds a fix to compile it on older
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390 varlen = sizeof(has_sse2); |
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Ok, here is a better patch, which even adds a fix to compile it on older
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391 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE2... " ); |
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392 ret = sysctl(mib, 2, &has_sse2, &varlen, NULL, 0); |
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393 gCpuCaps.hasSSE2 = ret >= 0 && has_sse2; |
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394 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE2 ? "yes.\n" : "no!\n" ); |
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395 #else |
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396 gCpuCaps.hasSSE = 0; |
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397 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "No OS support for SSE, disabling to be safe.\n" ); |
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398 #endif |
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399 #elif defined(__MINGW32__) || defined(__CYGWIN__) |
10440 | 400 LPTOP_LEVEL_EXCEPTION_FILTER exc_fil; |
401 if ( gCpuCaps.hasSSE ) { | |
402 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); | |
403 exc_fil = SetUnhandledExceptionFilter(win32_sig_handler_sse); | |
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404 __asm__ volatile ("xorps %xmm0, %xmm0"); |
10440 | 405 SetUnhandledExceptionFilter(exc_fil); |
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406 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
10440 | 407 } |
26061 | 408 #elif defined(__OS2__) |
409 EXCEPTIONREGISTRATIONRECORD RegRec = { 0, &os2_sig_handler_sse }; | |
410 if ( gCpuCaps.hasSSE ) { | |
411 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); | |
412 DosSetExceptionHandler( &RegRec ); | |
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413 __asm__ volatile ("xorps %xmm0, %xmm0"); |
26061 | 414 DosUnsetExceptionHandler( &RegRec ); |
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415 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
26061 | 416 } |
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417 #elif defined(__linux__) |
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418 #if defined(_POSIX_SOURCE) |
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419 struct sigaction saved_sigill; |
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420 |
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421 /* Save the original signal handlers. |
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422 */ |
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423 sigaction( SIGILL, NULL, &saved_sigill ); |
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424 |
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425 signal( SIGILL, (void (*)(int))sigill_handler_sse ); |
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426 |
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427 /* Emulate test for OSFXSR in CR4. The OS will set this bit if it |
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428 * supports the extended FPU save and restore required for SSE. If |
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429 * we execute an SSE instruction on a PIII and get a SIGILL, the OS |
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430 * doesn't support Streaming SIMD Exceptions, even if the processor |
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431 * does. |
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432 */ |
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433 if ( gCpuCaps.hasSSE ) { |
6134 | 434 mp_msg(MSGT_CPUDETECT,MSGL_V, "Testing OS support for SSE... " ); |
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435 |
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436 // __asm__ volatile ("xorps %%xmm0, %%xmm0"); |
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437 __asm__ volatile ("xorps %xmm0, %xmm0"); |
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438 |
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439 mp_msg(MSGT_CPUDETECT,MSGL_V, gCpuCaps.hasSSE ? "yes.\n" : "no!\n" ); |
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440 } |
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441 |
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442 /* Restore the original signal handlers. |
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443 */ |
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444 sigaction( SIGILL, &saved_sigill, NULL ); |
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445 |
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446 /* If we've gotten to here and the XMM CPUID bit is still set, we're |
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447 * safe to go ahead and hook out the SSE code throughout Mesa. |
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448 */ |
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449 mp_msg(MSGT_CPUDETECT,MSGL_V, "Tests of OS support for SSE %s\n", gCpuCaps.hasSSE ? "passed." : "failed!" ); |
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450 #else |
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451 /* We can't use POSIX signal handling to test the availability of |
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452 * SSE, so we disable it by default. |
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453 */ |
5937 | 454 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, disabling to be safe.\n" ); |
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455 gCpuCaps.hasSSE=0; |
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456 #endif /* _POSIX_SOURCE */ |
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457 #else |
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458 /* Do nothing on other platforms for now. |
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arpi
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459 */ |
6134 | 460 mp_msg(MSGT_CPUDETECT,MSGL_WARN, "Cannot test OS support for SSE, leaving disabled.\n" ); |
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461 gCpuCaps.hasSSE=0; |
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462 #endif /* __linux__ */ |
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463 } |
20577 | 464 #else /* ARCH_X86 */ |
3146
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465 |
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466 #ifdef __APPLE__ |
9003 | 467 #include <sys/sysctl.h> |
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468 #elif defined(__AMIGAOS4__) |
25338
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469 /* nothing */ |
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470 #else |
9003 | 471 #include <signal.h> |
472 #include <setjmp.h> | |
473 | |
474 static sigjmp_buf jmpbuf; | |
475 static volatile sig_atomic_t canjump = 0; | |
476 | |
477 static void sigill_handler (int sig) | |
478 { | |
479 if (!canjump) { | |
480 signal (sig, SIG_DFL); | |
481 raise (sig); | |
482 } | |
483 | |
484 canjump = 0; | |
485 siglongjmp (jmpbuf, 1); | |
486 } | |
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487 #endif /* __APPLE__ */ |
9003 | 488 |
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489 void GetCpuCaps( CpuCaps *caps) |
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490 { |
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491 caps->cpuType=0; |
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Retrieve CPU built-in namestring, and if it exists, print it during cpu detection; t it doesn't exist, fallback to the cpu table. Patch by Zuxy Meng
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492 caps->cpuModel=0; |
3403 | 493 caps->cpuStepping=0; |
3146
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494 caps->hasMMX=0; |
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495 caps->hasMMX2=0; |
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496 caps->has3DNow=0; |
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497 caps->has3DNowExt=0; |
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498 caps->hasSSE=0; |
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499 caps->hasSSE2=0; |
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500 caps->hasSSSE3=0; |
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501 caps->hasSSE4a=0; |
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502 caps->isX86=0; |
9003 | 503 caps->hasAltiVec = 0; |
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504 #if HAVE_ALTIVEC |
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505 #ifdef __APPLE__ |
9003 | 506 /* |
507 rip-off from ffmpeg altivec detection code. | |
508 this code also appears on Apple's AltiVec pages. | |
509 */ | |
510 { | |
511 int sels[2] = {CTL_HW, HW_VECTORUNIT}; | |
512 int has_vu = 0; | |
513 size_t len = sizeof(has_vu); | |
514 int err; | |
515 | |
516 err = sysctl(sels, 2, &has_vu, &len, NULL, 0); | |
517 | |
518 if (err == 0) | |
519 if (has_vu != 0) | |
520 caps->hasAltiVec = 1; | |
521 } | |
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522 #elif defined(__AMIGAOS4__) |
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523 ULONG result = 0; |
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524 |
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525 GetCPUInfoTags(GCIT_VectorUnit, &result, TAG_DONE); |
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526 if (result == VECTORTYPE_ALTIVEC) |
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527 caps->hasAltiVec = 1; |
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528 #else |
9003 | 529 /* no Darwin, do it the brute-force way */ |
530 /* this is borrowed from the libmpeg2 library */ | |
531 { | |
532 signal (SIGILL, sigill_handler); | |
533 if (sigsetjmp (jmpbuf, 1)) { | |
534 signal (SIGILL, SIG_DFL); | |
535 } else { | |
536 canjump = 1; | |
537 | |
27754
08d18fe9da52
Change all occurrences of asm and __asm to __asm__, same as was done for FFmpeg.
diego
parents:
27727
diff
changeset
|
538 __asm__ volatile ("mtspr 256, %0\n\t" |
9122 | 539 "vand %%v0, %%v0, %%v0" |
9003 | 540 : |
541 : "r" (-1)); | |
542 | |
543 signal (SIGILL, SIG_DFL); | |
544 caps->hasAltiVec = 1; | |
545 } | |
546 } | |
25329
676e2ace8a46
Replace SYS_DARWIN conditional by the more correct __APPLE__.
diego
parents:
24664
diff
changeset
|
547 #endif /* __APPLE__ */ |
9324 | 548 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"AltiVec %sfound\n", (caps->hasAltiVec ? "" : "not ")); |
9003 | 549 #endif /* HAVE_ALTIVEC */ |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
550 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
parents:
28335
diff
changeset
|
551 if (ARCH_IA64) |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
552 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Intel Itanium\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
553 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
parents:
28335
diff
changeset
|
554 if (ARCH_SPARC) |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
555 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Sun Sparc\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
556 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
parents:
28335
diff
changeset
|
557 if (ARCH_ARM) |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
558 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: ARM\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
559 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
parents:
28335
diff
changeset
|
560 if (ARCH_PPC) |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
561 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: PowerPC\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
562 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
parents:
28335
diff
changeset
|
563 if (ARCH_ALPHA) |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
564 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Digital Alpha\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
565 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
parents:
28335
diff
changeset
|
566 if (ARCH_SGI_MIPS) |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
567 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: SGI MIPS\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
568 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
parents:
28335
diff
changeset
|
569 if (ARCH_PA_RISC) |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
570 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: Hewlett-Packard PA-RISC\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
571 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
parents:
28335
diff
changeset
|
572 if (ARCH_S390) |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
573 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
574 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
parents:
28335
diff
changeset
|
575 if (ARCH_S390X) |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
576 mp_msg(MSGT_CPUDETECT,MSGL_INFO,"CPU: IBM S/390X\n"); |
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
577 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
parents:
28335
diff
changeset
|
578 if (ARCH_VAX) |
11962
909093c314e9
architecture type reporting for non-x86 CPUs (try 2, tested on x86 and x86-64)
gabucino
parents:
10955
diff
changeset
|
579 mp_msg(MSGT_CPUDETECT,MSGL_INFO, "CPU: Digital VAX\n" ); |
25340 | 580 |
28342
457eb94aaf59
Replace another bunch of '#if HAVE_FOO' preprocessor checks by 'if (HAVE_FOO)'.
diego
parents:
28335
diff
changeset
|
581 if (ARCH_XTENSA) |
25340 | 582 mp_msg(MSGT_CPUDETECT,MSGL_INFO, "CPU: Tensilica Xtensa\n" ); |
3146
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
583 } |
3164eaa93396
non x86 fix (otherwise we would need #ifdef ARCH_X86 around every if(gCpuCaps.has...))
michael
parents:
2417
diff
changeset
|
584 #endif /* !ARCH_X86 */ |