annotate libmpeg2/motion_comp_arm_s.S @ 34798:e3ceb73d4152

Fix A-V desync with skipframe and H.264. This will however cause desync when skipframe is used on PAFF H.264 content without correct-pts.
author reimar
date Sun, 06 May 2012 08:44:28 +0000
parents da2271c341ee
children
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1 @ motion_comp_arm_s.S
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2 @ Copyright (C) 2004 AGAWA Koji <i (AT) atty (DOT) jp>
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3 @
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4 @ This file is part of mpeg2dec, a free MPEG-2 video stream decoder.
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5 @ See http://libmpeg2.sourceforge.net/ for updates.
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6 @
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7 @ mpeg2dec is free software; you can redistribute it and/or modify
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8 @ it under the terms of the GNU General Public License as published by
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9 @ the Free Software Foundation; either version 2 of the License, or
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10 @ (at your option) any later version.
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11 @
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12 @ mpeg2dec is distributed in the hope that it will be useful,
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13 @ but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 @ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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15 @ GNU General Public License for more details.
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16 @
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17 @ You should have received a copy of the GNU General Public License
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da2271c341ee Update internal libmpeg2 copy to version 0.5.1.
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18 @ along with mpeg2dec; if not, write to the Free Software
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19 @ Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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20
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da2271c341ee Update internal libmpeg2 copy to version 0.5.1.
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21
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22 .text
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62abac0c8637 cosmetics: Fix some typos and trailing whitespace in local changes.
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23
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24 @ ----------------------------------------------------------------
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25 .align
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26 .global MC_put_o_16_arm
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27 MC_put_o_16_arm:
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28 @@ void func(uint8_t * dest, const uint8_t * ref, int stride, int height)
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29 pld [r1]
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30 stmfd sp!, {r4-r11, lr} @ R14 is also called LR
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31 and r4, r1, #3
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32 adr r5, MC_put_o_16_arm_align_jt
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33 add r5, r5, r4, lsl #2
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34 ldr pc, [r5]
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35
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36 MC_put_o_16_arm_align0:
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37 ldmia r1, {r4-r7}
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38 add r1, r1, r2
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39 pld [r1]
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40 stmia r0, {r4-r7}
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41 subs r3, r3, #1
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42 add r0, r0, r2
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43 bne MC_put_o_16_arm_align0
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44 ldmfd sp!, {r4-r11, pc} @@ update PC with LR content.
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45
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46 .macro PROC shift
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47 ldmia r1, {r4-r8}
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48 add r1, r1, r2
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49 mov r9, r4, lsr #(\shift)
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50 pld [r1]
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51 mov r10, r5, lsr #(\shift)
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52 orr r9, r9, r5, lsl #(32-\shift)
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53 mov r11, r6, lsr #(\shift)
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54 orr r10, r10, r6, lsl #(32-\shift)
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55 mov r12, r7, lsr #(\shift)
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56 orr r11, r11, r7, lsl #(32-\shift)
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57 orr r12, r12, r8, lsl #(32-\shift)
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58 stmia r0, {r9-r12}
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59 subs r3, r3, #1
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60 add r0, r0, r2
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61 .endm
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62
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63 MC_put_o_16_arm_align1:
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64 and r1, r1, #0xFFFFFFFC
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65 1: PROC(8)
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66 bne 1b
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67 ldmfd sp!, {r4-r11, pc} @@ update PC with LR content.
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68 MC_put_o_16_arm_align2:
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69 and r1, r1, #0xFFFFFFFC
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70 1: PROC(16)
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71 bne 1b
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72 ldmfd sp!, {r4-r11, pc} @@ update PC with LR content.
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73 MC_put_o_16_arm_align3:
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74 and r1, r1, #0xFFFFFFFC
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75 1: PROC(24)
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76 bne 1b
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77 ldmfd sp!, {r4-r11, pc} @@ update PC with LR content.
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78 MC_put_o_16_arm_align_jt:
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79 .word MC_put_o_16_arm_align0
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80 .word MC_put_o_16_arm_align1
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81 .word MC_put_o_16_arm_align2
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82 .word MC_put_o_16_arm_align3
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83
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84 @ ----------------------------------------------------------------
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85 .align
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86 .global MC_put_o_8_arm
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87 MC_put_o_8_arm:
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88 @@ void func(uint8_t * dest, const uint8_t * ref, int stride, int height)
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89 pld [r1]
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90 stmfd sp!, {r4-r10, lr} @ R14 is also called LR
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91 and r4, r1, #3
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92 adr r5, MC_put_o_8_arm_align_jt
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93 add r5, r5, r4, lsl #2
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94 ldr pc, [r5]
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95 MC_put_o_8_arm_align0:
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96 ldmia r1, {r4-r5}
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97 add r1, r1, r2
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98 pld [r1]
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99 stmia r0, {r4-r5}
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100 add r0, r0, r2
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101 subs r3, r3, #1
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102 bne MC_put_o_8_arm_align0
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103 ldmfd sp!, {r4-r10, pc} @@ update PC with LR content.
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104
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105 .macro PROC8 shift
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106 ldmia r1, {r4-r6}
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107 add r1, r1, r2
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108 mov r9, r4, lsr #(\shift)
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109 pld [r1]
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110 mov r10, r5, lsr #(\shift)
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111 orr r9, r9, r5, lsl #(32-\shift)
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112 orr r10, r10, r6, lsl #(32-\shift)
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113 stmia r0, {r9-r10}
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114 subs r3, r3, #1
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115 add r0, r0, r2
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116 .endm
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117
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118 MC_put_o_8_arm_align1:
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119 and r1, r1, #0xFFFFFFFC
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120 1: PROC8(8)
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121 bne 1b
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122 ldmfd sp!, {r4-r10, pc} @@ update PC with LR content.
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123
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124 MC_put_o_8_arm_align2:
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125 and r1, r1, #0xFFFFFFFC
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126 1: PROC8(16)
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127 bne 1b
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128 ldmfd sp!, {r4-r10, pc} @@ update PC with LR content.
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129
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130 MC_put_o_8_arm_align3:
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131 and r1, r1, #0xFFFFFFFC
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132 1: PROC8(24)
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133 bne 1b
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134 ldmfd sp!, {r4-r10, pc} @@ update PC with LR content.
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135
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136 MC_put_o_8_arm_align_jt:
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137 .word MC_put_o_8_arm_align0
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138 .word MC_put_o_8_arm_align1
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139 .word MC_put_o_8_arm_align2
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140 .word MC_put_o_8_arm_align3
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141
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142 @ ----------------------------------------------------------------
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143 .macro AVG_PW rW1, rW2
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144 mov \rW2, \rW2, lsl #24
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145 orr \rW2, \rW2, \rW1, lsr #8
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146 eor r9, \rW1, \rW2
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147 and \rW2, \rW1, \rW2
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148 and r10, r9, r12
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149 add \rW2, \rW2, r10, lsr #1
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150 and r10, r9, r11
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151 add \rW2, \rW2, r10
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152 .endm
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153
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154 .align
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155 .global MC_put_x_16_arm
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156 MC_put_x_16_arm:
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157 @@ void func(uint8_t * dest, const uint8_t * ref, int stride, int height)
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158 pld [r1]
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159 stmfd sp!, {r4-r11,lr} @ R14 is also called LR
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160 and r4, r1, #3
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161 adr r5, MC_put_x_16_arm_align_jt
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162 ldr r11, [r5]
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163 mvn r12, r11
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164 add r5, r5, r4, lsl #2
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165 ldr pc, [r5, #4]
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166
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167 .macro ADJ_ALIGN_QW shift, R0, R1, R2, R3, R4
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168 mov \R0, \R0, lsr #(\shift)
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169 orr \R0, \R0, \R1, lsl #(32 - \shift)
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170 mov \R1, \R1, lsr #(\shift)
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171 orr \R1, \R1, \R2, lsl #(32 - \shift)
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172 mov \R2, \R2, lsr #(\shift)
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173 orr \R2, \R2, \R3, lsl #(32 - \shift)
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174 mov \R3, \R3, lsr #(\shift)
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175 orr \R3, \R3, \R4, lsl #(32 - \shift)
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176 mov \R4, \R4, lsr #(\shift)
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177 @ and \R4, \R4, #0xFF
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178 .endm
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179
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180 MC_put_x_16_arm_align0:
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181 ldmia r1, {r4-r8}
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182 add r1, r1, r2
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183 pld [r1]
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184 AVG_PW r7, r8
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185 AVG_PW r6, r7
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186 AVG_PW r5, r6
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187 AVG_PW r4, r5
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188 stmia r0, {r5-r8}
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189 subs r3, r3, #1
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190 add r0, r0, r2
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191 bne MC_put_x_16_arm_align0
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192 ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
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193 MC_put_x_16_arm_align1:
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194 and r1, r1, #0xFFFFFFFC
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195 1: ldmia r1, {r4-r8}
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196 add r1, r1, r2
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197 pld [r1]
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198 ADJ_ALIGN_QW 8, r4, r5, r6, r7, r8
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199 AVG_PW r7, r8
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200 AVG_PW r6, r7
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201 AVG_PW r5, r6
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202 AVG_PW r4, r5
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203 stmia r0, {r5-r8}
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204 subs r3, r3, #1
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205 add r0, r0, r2
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206 bne 1b
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207 ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
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208 MC_put_x_16_arm_align2:
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209 and r1, r1, #0xFFFFFFFC
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210 1: ldmia r1, {r4-r8}
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211 add r1, r1, r2
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212 pld [r1]
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213 ADJ_ALIGN_QW 16, r4, r5, r6, r7, r8
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214 AVG_PW r7, r8
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215 AVG_PW r6, r7
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216 AVG_PW r5, r6
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217 AVG_PW r4, r5
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218 stmia r0, {r5-r8}
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219 subs r3, r3, #1
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220 add r0, r0, r2
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221 bne 1b
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222 ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
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223 MC_put_x_16_arm_align3:
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224 and r1, r1, #0xFFFFFFFC
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225 1: ldmia r1, {r4-r8}
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226 add r1, r1, r2
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227 pld [r1]
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228 ADJ_ALIGN_QW 24, r4, r5, r6, r7, r8
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229 AVG_PW r7, r8
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230 AVG_PW r6, r7
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231 AVG_PW r5, r6
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232 AVG_PW r4, r5
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233 stmia r0, {r5-r8}
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234 subs r3, r3, #1
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235 add r0, r0, r2
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236 bne 1b
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237 ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
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238 MC_put_x_16_arm_align_jt:
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239 .word 0x01010101
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240 .word MC_put_x_16_arm_align0
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241 .word MC_put_x_16_arm_align1
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242 .word MC_put_x_16_arm_align2
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243 .word MC_put_x_16_arm_align3
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244
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245 @ ----------------------------------------------------------------
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246 .align
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247 .global MC_put_x_8_arm
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248 MC_put_x_8_arm:
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249 @@ void func(uint8_t * dest, const uint8_t * ref, int stride, int height)
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250 pld [r1]
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251 stmfd sp!, {r4-r11,lr} @ R14 is also called LR
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252 and r4, r1, #3
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253 adr r5, MC_put_x_8_arm_align_jt
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254 ldr r11, [r5]
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255 mvn r12, r11
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256 add r5, r5, r4, lsl #2
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257 ldr pc, [r5, #4]
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258
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259 .macro ADJ_ALIGN_DW shift, R0, R1, R2
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260 mov \R0, \R0, lsr #(\shift)
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261 orr \R0, \R0, \R1, lsl #(32 - \shift)
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262 mov \R1, \R1, lsr #(\shift)
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263 orr \R1, \R1, \R2, lsl #(32 - \shift)
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264 mov \R2, \R2, lsr #(\shift)
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265 @ and \R4, \R4, #0xFF
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266 .endm
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267
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268 MC_put_x_8_arm_align0:
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269 ldmia r1, {r4-r6}
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270 add r1, r1, r2
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271 pld [r1]
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272 AVG_PW r5, r6
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273 AVG_PW r4, r5
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274 stmia r0, {r5-r6}
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275 subs r3, r3, #1
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276 add r0, r0, r2
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277 bne MC_put_x_8_arm_align0
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278 ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
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279 MC_put_x_8_arm_align1:
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280 and r1, r1, #0xFFFFFFFC
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281 1: ldmia r1, {r4-r6}
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282 add r1, r1, r2
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283 pld [r1]
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284 ADJ_ALIGN_DW 8, r4, r5, r6
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285 AVG_PW r5, r6
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286 AVG_PW r4, r5
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287 stmia r0, {r5-r6}
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288 subs r3, r3, #1
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289 add r0, r0, r2
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290 bne 1b
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291 ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
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292 MC_put_x_8_arm_align2:
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293 and r1, r1, #0xFFFFFFFC
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294 1: ldmia r1, {r4-r6}
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295 add r1, r1, r2
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296 pld [r1]
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297 ADJ_ALIGN_DW 16, r4, r5, r6
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298 AVG_PW r5, r6
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299 AVG_PW r4, r5
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300 stmia r0, {r5-r6}
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301 subs r3, r3, #1
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302 add r0, r0, r2
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303 bne 1b
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304 ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
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305 MC_put_x_8_arm_align3:
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306 and r1, r1, #0xFFFFFFFC
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307 1: ldmia r1, {r4-r6}
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308 add r1, r1, r2
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309 pld [r1]
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310 ADJ_ALIGN_DW 24, r4, r5, r6
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311 AVG_PW r5, r6
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312 AVG_PW r4, r5
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313 stmia r0, {r5-r6}
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314 subs r3, r3, #1
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315 add r0, r0, r2
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316 bne 1b
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317 ldmfd sp!, {r4-r11,pc} @@ update PC with LR content.
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318 MC_put_x_8_arm_align_jt:
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319 .word 0x01010101
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320 .word MC_put_x_8_arm_align0
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321 .word MC_put_x_8_arm_align1
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322 .word MC_put_x_8_arm_align2
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323 .word MC_put_x_8_arm_align3