26096
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1 #ifndef _SAVAGE_REGS_H
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2 #define _SAVAGE_REGS_H
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3
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4 #define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX))
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5 #define S3_SAVAGE4_SERIES(chip) ((chip==S3_SAVAGE4) || (chip==S3_PROSAVAGE))
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6 #define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE))
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7 #define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000))
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8
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9 /*
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10 * Chip tags. These are used to group the adapters into
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11 * related families.
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12 */
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13 enum S3CHIPTAGS {
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14 S3_UNKNOWN = 0,
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15 S3_TRIO64V,
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16 S3_VIRGE,
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17 S3_SAVAGE3D,
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18 S3_SAVAGE_MX,
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19 S3_SAVAGE4,
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20 S3_PROSAVAGE,
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21 S3_SUPERSAVAGE,
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22 S3_SAVAGE2000,
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23 S3_LAST
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24 };
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25
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26 #define BIOS_BSIZE 1024
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27 #define BIOS_BASE 0xc0000
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28
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29 #define S3_NEWMMIO_REGBASE 0x1000000 /* 16MB */
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30 #define S3_NEWMMIO_REGSIZE 0x0010000 /* 64KB */
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31 #define S3_NEWMMIO_REGSIZE_SAVAGE 0x0080000 /* 512KB */
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32
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33 #define BASE_FREQ 14.31818
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34
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35 /*
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36 * There are two different streams engines used in the S3 line.
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37 * The old engine is in the Trio64, Virge,
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38 * Savage3D, Savage4, SavagePro, and SavageTwister.
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39 * The new engine is in the Savage2000, SavageMX,
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40 * SavageIX, and SuperSavage.
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41 */
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42
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43 /* Old engine registers */
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44 #define PSTREAM_CONTROL_REG 0x8180
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45 #define COL_CHROMA_KEY_CONTROL_REG 0x8184
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46 #define SSTREAM_CONTROL_REG 0x8190
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47 #define CHROMA_KEY_UPPER_BOUND_REG 0x8194
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48 #define SSTREAM_STRETCH_REG 0x8198
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49 #define COLOR_ADJUSTMENT_REG 0x819C
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50 #define BLEND_CONTROL_REG 0x81A0
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51 #define PSTREAM_FBADDR0_REG 0x81C0
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52 #define PSTREAM_FBADDR1_REG 0x81C4
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53 #define PSTREAM_STRIDE_REG 0x81C8
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54 #define DOUBLE_BUFFER_REG 0x81CC
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55 #define SSTREAM_FBADDR0_REG 0x81D0
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56 #define SSTREAM_FBADDR1_REG 0x81D4
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57 #define SSTREAM_STRIDE_REG 0x81D8
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58 #define OPAQUE_OVERLAY_CONTROL_REG 0x81DC
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59 #define K1_VSCALE_REG 0x81E0
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60 #define SSTREAM_VSCALE_REG 0x81E0
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61 #define K2_VSCALE_REG 0x81E4
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62 #define SSTREAM_VINITIAL_REG 0x81E4
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63 #define DDA_VERT_REG 0x81E8
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64 #define SSTREAM_LINES_REG 0x81E8
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65 #define STREAMS_FIFO_REG 0x81EC
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66 #define PSTREAM_WINDOW_START_REG 0x81F0
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67 #define PSTREAM_WINDOW_SIZE_REG 0x81F4
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68 #define SSTREAM_WINDOW_START_REG 0x81F8
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69 #define SSTREAM_WINDOW_SIZE_REG 0x81FC
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70 #define FIFO_CONTROL 0x8200
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71 #define PSTREAM_FBSIZE_REG 0x8300
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72 #define SSTREAM_FBSIZE_REG 0x8304
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73 #define SSTREAM_FBADDR2_REG 0x8308
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74
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75 /* New engine registers */
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76 #define PRI_STREAM_FBUF_ADDR0 0x81c0
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77 #define PRI_STREAM_FBUF_ADDR1 0x81c4
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78 #define PRI_STREAM_STRIDE 0x81c8
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79 #define PRI_STREAM_BUFFERSIZE 0x8214
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80 #define SEC_STREAM_CKEY_LOW 0x8184
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81 #define SEC_STREAM_CKEY_UPPER 0x8194
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82 #define BLEND_CONTROL 0x8190
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83 #define SEC_STREAM_COLOR_CONVERT1 0x8198
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84 #define SEC_STREAM_COLOR_CONVERT2 0x819c
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85 #define SEC_STREAM_COLOR_CONVERT3 0x81e4
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86 #define SEC_STREAM_HSCALING 0x81a0
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87 #define SEC_STREAM_BUFFERSIZE 0x81a8
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88 #define SEC_STREAM_HSCALE_NORMALIZE 0x81ac
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89 #define SEC_STREAM_VSCALING 0x81e8
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90 #define SEC_STREAM_FBUF_ADDR0 0x81d0
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91 #define SEC_STREAM_FBUF_ADDR1 0x81d4
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92 #define SEC_STREAM_FBUF_ADDR2 0x81ec
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93 #define SEC_STREAM_STRIDE 0x81d8
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94 #define SEC_STREAM_WINDOW_START 0x81f8
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95 #define SEC_STREAM_WINDOW_SZ 0x81fc
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96 #define SEC_STREAM_TILE_OFF 0x821c
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97 #define SEC_STREAM_OPAQUE_OVERLAY 0x81dc
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98
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99 /* Savage 2000 registers */
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100 #define SEC_STREAM_COLOR_CONVERT0_2000 0x8198
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101 #define SEC_STREAM_COLOR_CONVERT1_2000 0x819c
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102 #define SEC_STREAM_COLOR_CONVERT2_2000 0x81e0
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103 #define SEC_STREAM_COLOR_CONVERT3_2000 0x81e4
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104
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105 /* Virge+ registers */
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106 #define FIFO_CONTROL_REG 0x8200
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107 #define MIU_CONTROL_REG 0x8204
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108 #define STREAMS_TIMEOUT_REG 0x8208
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109 #define MISC_TIMEOUT_REG 0x820c
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110
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111 /* VGA stuff */
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112 #define vgaCRIndex 0x3d4
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113 #define vgaCRReg 0x3d5
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114
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115 /* CRT Control registers */
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116 #define EXT_MEM_CTRL1 0x53
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117 #define LIN_ADDR_CTRL 0x58
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118 #define EXT_MISC_CTRL2 0x67
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119
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120 /* Old engine constants */
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121 #define ENABLE_NEWMMIO 0x08
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122 #define ENABLE_LFB 0x10
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123 #define ENABLE_STREAMS_OLD 0x0c
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124 #define NO_STREAMS_OLD 0xf3
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125
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126 /* New engine constants */
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127 #define ENABLE_STREAM1 0x04
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128 #define NO_STREAMS 0xF9
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129
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130 #define VerticalRetraceWait() \
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131 do { \
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132 VGAIN8(0x3d4); \
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133 VGAOUT8(0x3d4, 0x17); \
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134 if (VGAIN8(0x3d5) & 0x80) { \
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135 int i = 0x10000; \
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136 while ((VGAIN8(0x3da) & 0x08) == 0x08 && i--) ; \
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137 i = 0x10000; \
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138 while ((VGAIN8(0x3da) & 0x08) == 0x00 && i--) ; \
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139 } \
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140 } while (0)
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141
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142 /* Scaling operations */
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143 #define HSCALING_Shift 0
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144 #define HSCALING_Mask (((1L << 16)-1) << HSCALING_Shift)
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145 #define HSCALING(w0,w1) ((((unsigned int)(((double)w0/(double)w1) * (1 << 15))) << HSCALING_Shift) & HSCALING_Mask)
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146
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147 #define VSCALING_Shift 0
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148 #define VSCALING_Mask (((1L << 20)-1) << VSCALING_Shift)
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149 #define VSCALING(h0,h1) ((((unsigned int) (((double)h0/(double)h1) * (1 << 15))) << VSCALING_Shift) & VSCALING_Mask)
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150
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151 /* Scaling factors */
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152 #define HDM_SHIFT 16
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153 #define HDSCALE_4 (2 << HDM_SHIFT)
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154 #define HDSCALE_8 (3 << HDM_SHIFT)
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155 #define HDSCALE_16 (4 << HDM_SHIFT)
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156 #define HDSCALE_32 (5 << HDM_SHIFT)
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157 #define HDSCALE_64 (6 << HDM_SHIFT)
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158
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159 /* Window parameters */
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160 #define OS_XY(x,y) (((x+1)<<16)|(y+1))
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161 #define OS_WH(x,y) (((x-1)<<16)|(y))
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162
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163 /* PCI stuff */
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164
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165 /* PCI-Memory IO access macros. */
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166 #define VID_WR08(p,i,val) (((uint8_t *)(p))[(i)]=(val))
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167 #define VID_RD08(p,i) (((uint8_t *)(p))[(i)])
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168
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169 #define VID_WR32(p,i,val) (((uint32_t *)(p))[(i)/4]=(val))
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170 #define VID_RD32(p,i) (((uint32_t *)(p))[(i)/4])
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171
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172 #ifndef USE_RMW_CYCLES
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173
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174 /* Can be used to inhibit READ-MODIFY-WRITE cycles. On by default. */
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175 #define MEM_BARRIER() __asm__ __volatile__ ("" : : : "memory")
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176
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177 #undef VID_WR08
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178 #define VID_WR08(p,i,val) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]=(val); })
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179 #undef VID_RD08
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180 #define VID_RD08(p,i) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]; })
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181
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182 #undef VID_WR16
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183 #define VID_WR16(p,i,val) ({ MEM_BARRIER(); ((uint16_t *)(p))[(i)/2]=(val); })
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184 #undef VID_RD16
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185 #define VID_RD16(p,i) ({ MEM_BARRIER(); ((uint16_t *)(p))[(i)/2]; })
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186
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187 #undef VID_WR32
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188 #define VID_WR32(p,i,val) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]=(val); })
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189 #undef VID_RD32
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190 #define VID_RD32(p,i) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]; })
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191 #endif /* USE_RMW_CYCLES */
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192
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193 #define VID_AND32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)&(val))
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194 #define VID_OR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)|(val))
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195 #define VID_XOR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)^(val))
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196
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197 #define VGAIN8(addr) VID_RD08(info->control_base+0x8000, addr)
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198 #define VGAIN16(addr) VID_RD16(info->control_base+0x8000, addr)
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199 #define VGAIN(addr) VID_RD32(info->control_base+0x8000, addr)
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200
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201 #define VGAOUT8(addr,val) VID_WR08(info->control_base+0x8000, addr, val)
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202 #define VGAOUT16(addr,val) VID_WR16(info->control_base+0x8000, addr, val)
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203 #define VGAOUT(addr,val) VID_WR32(info->control_base+0x8000, addr, val)
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204
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205 #define INREG(addr) VID_RD32(info->control_base, addr)
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206 #define OUTREG(addr,val) VID_WR32(info->control_base, addr, val)
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207 #define INREG8(addr) VID_RD08(info->control_base, addr)
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208 #define OUTREG8(addr,val) VID_WR08(info->control_base, addr, val)
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209 #define INREG16(addr) VID_RD16(info->control_base, addr)
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210 #define OUTREG16(addr,val) VID_WR16(info->control_base, addr, val)
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211
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212 #define ALIGN_TO(v, n) (((v) + (n-1)) & ~(n-1))
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213
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214 #endif /* _S3_REGS_H */
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