annotate cpuinfo.c @ 32264:f1884cb8d0ee

Remove __USE_UNIX98 from libdvdcss/libdvdnav/libdvdread CPPFLAGS. This is an internal glibc symbol that should not be used directly. Besides, other CPPFLAGS already take care of enabling single Unix v2.
author diego
date Sat, 25 Sep 2010 13:01:33 +0000
parents dd7f15a3fb1b
children 514016233368
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rev   line source
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1 /*
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2 * small utility to extract CPU information
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3 * Used by configure to set CPU optimization levels on some operating
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4 * systems where /proc/cpuinfo is non-existent or unreliable.
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5 *
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6 * This file is part of MPlayer.
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7 *
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8 * MPlayer is free software; you can redistribute it and/or modify
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9 * it under the terms of the GNU General Public License as published by
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10 * the Free Software Foundation; either version 2 of the License, or
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11 * (at your option) any later version.
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12 *
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13 * MPlayer is distributed in the hope that it will be useful,
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14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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16 * GNU General Public License for more details.
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17 *
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18 * You should have received a copy of the GNU General Public License along
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19 * with MPlayer; if not, write to the Free Software Foundation, Inc.,
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20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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21 */
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22
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23 #include <stdio.h>
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24 #include <sys/time.h>
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25 #include <stdlib.h>
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26 #include <string.h>
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27 #include <unistd.h>
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28
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29 #ifdef __MINGW32__
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30 #define MISSING_USLEEP
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31 #include <windows.h>
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32 #define sleep(t) Sleep(1000*t);
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33 #endif
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34
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35 #ifdef __BEOS__
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36 #define usleep(t) snooze(t)
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37 #endif
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38
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39 #ifdef M_UNIX
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40 typedef long long int64_t;
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41 #define MISSING_USLEEP
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42 #else
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43 #include <inttypes.h>
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44 #endif
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45
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46 #define CPUID_FEATURE_DEF(bit, desc, description) \
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47 { bit, desc }
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48
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49 typedef struct cpuid_regs {
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50 unsigned int eax;
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51 unsigned int ebx;
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52 unsigned int ecx;
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53 unsigned int edx;
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54 } cpuid_regs_t;
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55
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56 static cpuid_regs_t
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57 cpuid(int func) {
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58 cpuid_regs_t regs;
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59 #define CPUID ".byte 0x0f, 0xa2; "
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60 #ifdef __x86_64__
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61 __asm__("mov %%rbx, %%rsi\n\t"
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62 #else
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63 __asm__("mov %%ebx, %%esi\n\t"
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64 #endif
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65 CPUID"\n\t"
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66 #ifdef __x86_64__
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67 "xchg %%rsi, %%rbx\n\t"
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68 #else
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69 "xchg %%esi, %%ebx\n\t"
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70 #endif
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71 : "=a" (regs.eax), "=S" (regs.ebx), "=c" (regs.ecx), "=d" (regs.edx)
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72 : "0" (func));
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73 return regs;
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74 }
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75
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76
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77 static int64_t
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78 rdtsc(void)
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79 {
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80 uint32_t hi, lo;
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81 #define RDTSC ".byte 0x0f, 0x31; "
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82 __asm__ volatile (RDTSC : "=a"(lo), "=d"(hi) : );
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83 return (uint64_t) hi << 32 | lo;
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84 }
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85
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86 static const char*
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87 brandname(int i)
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88 {
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89 static const char* brandmap[] = {
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90 NULL,
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91 "Intel(R) Celeron(R) processor",
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92 "Intel(R) Pentium(R) III processor",
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93 "Intel(R) Pentium(R) III Xeon(tm) processor",
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94 "Intel(R) Pentium(R) III processor",
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95 NULL,
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96 "Mobile Intel(R) Pentium(R) III processor-M",
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97 "Mobile Intel(R) Celeron(R) processor"
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98 };
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99
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100 if (i >= sizeof(brandmap))
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101 return NULL;
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102 else
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103 return brandmap[i];
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104 }
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105
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106 static void
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107 store32(char *d, unsigned int v)
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108 {
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109 d[0] = v & 0xff;
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110 d[1] = (v >> 8) & 0xff;
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111 d[2] = (v >> 16) & 0xff;
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112 d[3] = (v >> 24) & 0xff;
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113 }
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114
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115
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116 int
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117 main(void)
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118 {
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119 cpuid_regs_t regs, regs_ext;
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120 char idstr[13];
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121 unsigned max_cpuid;
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122 unsigned max_ext_cpuid;
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123 unsigned int amd_flags;
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124 unsigned int amd_flags2;
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125 const char *model_name = NULL;
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126 int i;
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127 char processor_name[49];
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128
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129 regs = cpuid(0);
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130 max_cpuid = regs.eax;
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131 /* printf("%d CPUID function codes\n", max_cpuid+1); */
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132
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133 store32(idstr+0, regs.ebx);
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134 store32(idstr+4, regs.edx);
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135 store32(idstr+8, regs.ecx);
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136 idstr[12] = 0;
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137 printf("vendor_id\t: %s\n", idstr);
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138
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139 regs_ext = cpuid((1<<31) + 0);
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140 max_ext_cpuid = regs_ext.eax;
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141 if (max_ext_cpuid >= (1<<31) + 1) {
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142 regs_ext = cpuid((1<<31) + 1);
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143 amd_flags = regs_ext.edx;
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144 amd_flags2 = regs_ext.ecx;
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145
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146 if (max_ext_cpuid >= (1<<31) + 4) {
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147 for (i = 2; i <= 4; i++) {
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148 regs_ext = cpuid((1<<31) + i);
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149 store32(processor_name + (i-2)*16, regs_ext.eax);
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150 store32(processor_name + (i-2)*16 + 4, regs_ext.ebx);
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151 store32(processor_name + (i-2)*16 + 8, regs_ext.ecx);
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152 store32(processor_name + (i-2)*16 + 12, regs_ext.edx);
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153 }
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154 processor_name[48] = 0;
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155 model_name = processor_name;
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156 while (*model_name == ' ') {
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157 model_name++;
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158 }
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159 }
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160 } else {
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161 amd_flags = 0;
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162 amd_flags2 = 0;
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163 }
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164
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165 if (max_cpuid >= 1) {
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166 static struct {
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167 int bit;
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168 char *desc;
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169 } cap[] = {
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170 CPUID_FEATURE_DEF(0, "fpu", "Floating-point unit on-chip"),
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171 CPUID_FEATURE_DEF(1, "vme", "Virtual Mode Enhancements"),
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172 CPUID_FEATURE_DEF(2, "de", "Debugging Extension"),
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173 CPUID_FEATURE_DEF(3, "pse", "Page Size Extension"),
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174 CPUID_FEATURE_DEF(4, "tsc", "Time Stamp Counter"),
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175 CPUID_FEATURE_DEF(5, "msr", "Pentium Processor MSR"),
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176 CPUID_FEATURE_DEF(6, "pae", "Physical Address Extension"),
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177 CPUID_FEATURE_DEF(7, "mce", "Machine Check Exception"),
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178 CPUID_FEATURE_DEF(8, "cx8", "CMPXCHG8B Instruction Supported"),
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179 CPUID_FEATURE_DEF(9, "apic", "On-chip APIC Hardware Enabled"),
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180 CPUID_FEATURE_DEF(11, "sep", "SYSENTER and SYSEXIT"),
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181 CPUID_FEATURE_DEF(12, "mtrr", "Memory Type Range Registers"),
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182 CPUID_FEATURE_DEF(13, "pge", "PTE Global Bit"),
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183 CPUID_FEATURE_DEF(14, "mca", "Machine Check Architecture"),
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184 CPUID_FEATURE_DEF(15, "cmov", "Conditional Move/Compare Instruction"),
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185 CPUID_FEATURE_DEF(16, "pat", "Page Attribute Table"),
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186 CPUID_FEATURE_DEF(17, "pse36", "Page Size Extension 36-bit"),
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187 CPUID_FEATURE_DEF(18, "pn", "Processor Serial Number"),
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188 CPUID_FEATURE_DEF(19, "clflush", "CFLUSH instruction"),
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189 CPUID_FEATURE_DEF(21, "dts", "Debug Store"),
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190 CPUID_FEATURE_DEF(22, "acpi", "Thermal Monitor and Clock Ctrl"),
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191 CPUID_FEATURE_DEF(23, "mmx", "MMX Technology"),
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192 CPUID_FEATURE_DEF(24, "fxsr", "FXSAVE/FXRSTOR"),
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193 CPUID_FEATURE_DEF(25, "sse", "SSE Extensions"),
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194 CPUID_FEATURE_DEF(26, "sse2", "SSE2 Extensions"),
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195 CPUID_FEATURE_DEF(27, "ss", "Self Snoop"),
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196 CPUID_FEATURE_DEF(28, "ht", "Multi-threading"),
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197 CPUID_FEATURE_DEF(29, "tm", "Therm. Monitor"),
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198 CPUID_FEATURE_DEF(30, "ia64", "IA-64 Processor"),
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199 CPUID_FEATURE_DEF(31, "pbe", "Pend. Brk. EN."),
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200 { -1 }
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201 };
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202 static struct {
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203 int bit;
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204 char *desc;
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205 } cap2[] = {
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206 CPUID_FEATURE_DEF(0, "pni", "SSE3 Extensions"),
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207 CPUID_FEATURE_DEF(1, "pclmulqdq", "Carryless Multiplication"),
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208 CPUID_FEATURE_DEF(2, "dtes64", "64-bit Debug Store"),
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209 CPUID_FEATURE_DEF(3, "monitor", "MONITOR/MWAIT"),
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210 CPUID_FEATURE_DEF(4, "ds_cpl", "CPL Qualified Debug Store"),
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211 CPUID_FEATURE_DEF(5, "vmx", "Virtual Machine Extensions"),
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212 CPUID_FEATURE_DEF(6, "smx", "Safer Mode Extensions"),
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213 CPUID_FEATURE_DEF(7, "est", "Enhanced Intel SpeedStep Technology"),
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214 CPUID_FEATURE_DEF(8, "tm2", "Thermal Monitor 2"),
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215 CPUID_FEATURE_DEF(9, "ssse3", "Supplemental SSE3"),
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216 CPUID_FEATURE_DEF(10, "cid", "L1 Context ID"),
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217 CPUID_FEATURE_DEF(12, "fma", "Fused Multiply Add"),
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218 CPUID_FEATURE_DEF(13, "cx16", "CMPXCHG16B Available"),
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219 CPUID_FEATURE_DEF(14, "xtpr", "xTPR Disable"),
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220 CPUID_FEATURE_DEF(15, "pdcm", "Perf/Debug Capability MSR"),
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221 CPUID_FEATURE_DEF(18, "dca", "Direct Cache Access"),
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222 CPUID_FEATURE_DEF(19, "sse4_1", "SSE4.1 Extensions"),
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223 CPUID_FEATURE_DEF(20, "sse4_2", "SSE4.2 Extensions"),
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224 CPUID_FEATURE_DEF(21, "x2apic", "x2APIC Feature"),
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225 CPUID_FEATURE_DEF(22, "movbe", "MOVBE Instruction"),
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226 CPUID_FEATURE_DEF(23, "popcnt", "Pop Count Instruction"),
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227 CPUID_FEATURE_DEF(25, "aes", "AES Instruction"),
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228 CPUID_FEATURE_DEF(26, "xsave", "XSAVE/XRSTOR Extensions"),
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229 CPUID_FEATURE_DEF(27, "osxsave", "XSAVE/XRSTOR Enabled in the OS"),
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230 CPUID_FEATURE_DEF(28, "avx", "Advanced Vector Extension"),
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231 { -1 }
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232 };
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233 static struct {
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234 int bit;
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235 char *desc;
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236 } cap_amd[] = {
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237 CPUID_FEATURE_DEF(11, "syscall", "SYSCALL and SYSRET"),
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238 CPUID_FEATURE_DEF(19, "mp", "MP Capable"),
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239 CPUID_FEATURE_DEF(20, "nx", "No-Execute Page Protection"),
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240 CPUID_FEATURE_DEF(22, "mmxext", "MMX Technology (AMD Extensions)"),
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241 CPUID_FEATURE_DEF(25, "fxsr_opt", "Fast FXSAVE/FXRSTOR"),
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242 CPUID_FEATURE_DEF(26, "pdpe1gb", "PDP Entry for 1GiB Page"),
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243 CPUID_FEATURE_DEF(27, "rdtscp", "RDTSCP Instruction"),
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244 CPUID_FEATURE_DEF(29, "lm", "Long Mode Capable"),
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245 CPUID_FEATURE_DEF(30, "3dnowext", "3DNow! Extensions"),
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246 CPUID_FEATURE_DEF(31, "3dnow", "3DNow!"),
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247 { -1 }
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248 };
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249 static struct {
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250 int bit;
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251 char *desc;
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252 } cap_amd2[] = {
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253 CPUID_FEATURE_DEF(0, "lahf_lm", "LAHF/SAHF Supported in 64-bit Mode"),
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254 CPUID_FEATURE_DEF(1, "cmp_legacy", "Chip Multi-Core"),
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255 CPUID_FEATURE_DEF(2, "svm", "Secure Virtual Machine"),
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256 CPUID_FEATURE_DEF(3, "extapic", "Extended APIC Space"),
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257 CPUID_FEATURE_DEF(4, "cr8_legacy", "CR8 Available in Legacy Mode"),
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258 CPUID_FEATURE_DEF(5, "abm", "Advanced Bit Manipulation"),
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259 CPUID_FEATURE_DEF(6, "sse4a", "SSE4A Extensions"),
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260 CPUID_FEATURE_DEF(7, "misalignsse", "Misaligned SSE Mode"),
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261 CPUID_FEATURE_DEF(8, "3dnowprefetch", "3DNow! Prefetch/PrefetchW"),
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262 CPUID_FEATURE_DEF(9, "osvw", "OS Visible Workaround"),
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263 CPUID_FEATURE_DEF(10, "ibs", "Instruction Based Sampling"),
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264 CPUID_FEATURE_DEF(11, "sse5", "SSE5 Extensions"),
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265 CPUID_FEATURE_DEF(12, "skinit", "SKINIT, STGI, and DEV Support"),
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266 CPUID_FEATURE_DEF(13, "wdt", "Watchdog Timer Support"),
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267 { -1 }
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268 };
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269 unsigned int family, model, stepping;
23346
932c22238e5d 10l: cosmetic: more trailing whitespaces removed
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270
31077
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271 regs = cpuid(1);
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272 family = (regs.eax >> 8) & 0xf;
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273 model = (regs.eax >> 4) & 0xf;
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274 stepping = regs.eax & 0xf;
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275
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276 if (family == 0xf)
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277 family += (regs.eax >> 20) & 0xff;
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278 if (family == 0xf || family == 6)
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279 model += ((regs.eax >> 16) & 0xf) << 4;
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280
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281 printf("cpu family\t: %d\n"
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282 "model\t\t: %d\n"
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283 "stepping\t: %d\n" ,
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284 family,
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285 model,
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286 stepping);
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287
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288 if (strstr(idstr, "Intel") && !model_name) {
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289 if (family == 6 && model == 0xb && stepping == 1)
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290 model_name = "Intel (R) Celeron (R) processor";
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291 else
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292 model_name = brandname(regs.ebx & 0xf);
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293 }
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294
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295 printf("flags\t\t:");
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296 for (i = 0; cap[i].bit >= 0; i++) {
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297 if (regs.edx & (1 << cap[i].bit)) {
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298 printf(" %s", cap[i].desc);
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299 }
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300 }
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301 for (i = 0; cap2[i].bit >= 0; i++) {
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302 if (regs.ecx & (1 << cap2[i].bit)) {
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303 printf(" %s", cap2[i].desc);
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304 }
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305 }
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306 /* k6_mtrr is supported by some AMD K6-2/K6-III CPUs but
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307 it is not indicated by a CPUID feature bit, so we
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308 have to check the family, model and stepping instead. */
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309 if (strstr(idstr, "AMD") &&
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310 family == 5 &&
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311 (model >= 9 || (model == 8 && stepping >= 8)))
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312 printf(" %s", "k6_mtrr");
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313 /* similar for cyrix_arr. */
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314 if (strstr(idstr, "Cyrix") &&
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315 (family == 5 && (model < 4 || family == 6)))
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316 printf(" %s", "cyrix_arr");
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317 /* as well as centaur_mcr. */
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318 if (strstr(idstr, "Centaur") &&
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319 family == 5)
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320 printf(" %s", "centaur_mcr");
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321
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322 for (i = 0; cap_amd[i].bit >= 0; i++) {
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323 if (amd_flags & (1 << cap_amd[i].bit)) {
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324 printf(" %s", cap_amd[i].desc);
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325 }
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326 }
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327 for (i = 0; cap_amd2[i].bit >= 0; i++) {
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328 if (amd_flags2 & (1 << cap_amd2[i].bit)) {
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329 printf(" %s", cap_amd2[i].desc);
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330 }
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331 }
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332 printf("\n");
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333
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334 if (regs.edx & (1 << 4)) {
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335 int64_t tsc_start, tsc_end;
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336 struct timeval tv_start, tv_end;
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337 int usec_delay;
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338
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339 tsc_start = rdtsc();
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340 gettimeofday(&tv_start, NULL);
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341 #ifdef MISSING_USLEEP
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342 sleep(1);
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343 #else
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344 usleep(100000);
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345 #endif
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346 tsc_end = rdtsc();
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347 gettimeofday(&tv_end, NULL);
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348
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349 usec_delay = 1000000 * (tv_end.tv_sec - tv_start.tv_sec)
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350 + (tv_end.tv_usec - tv_start.tv_usec);
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351
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352 printf("cpu MHz\t\t: %.3f\n",
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353 (double)(tsc_end-tsc_start) / usec_delay);
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354 }
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355 }
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356
31077
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357 printf("model name\t: ");
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358 if (model_name)
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359 printf("%s\n", model_name);
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360 else
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361 printf("Unknown %s CPU\n", idstr);
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362 }