annotate TOOLS/cpuinfo.c @ 17670:f5f338e543b6

Fix rgb32tobgr16, rgb32to15, and rgb32tobgr15. All had the same problem that was fixed in rgb32to16 about a year ago: using only the first 8 bits of the 32-bit pixel.
author pacman
date Fri, 24 Feb 2006 09:52:59 +0000
parents 4471c5a962ec
children 744aa553e4a1
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rev   line source
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1 /* small utility to extract CPU information
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2 Used by configure to set CPU optimization levels on some operating
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3 systems where /proc/cpuinfo is non-existent or unreliable. */
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4
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5 #include <stdio.h>
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6 #include <sys/time.h>
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7 #include <stdlib.h>
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8 #include <string.h>
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9
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10 #ifdef __MINGW32__
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11 #include <sys/timeb.h>
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12 void gettimeofday(struct timeval* t,void* timezone) {
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13 struct timeb timebuffer;
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14 ftime( &timebuffer );
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15 t->tv_sec=timebuffer.time;
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16 t->tv_usec=1000*timebuffer.millitm;
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17 }
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18 #define MISSING_USLEEP
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19 #define sleep(t) _sleep(1000*t);
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20 #endif
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21
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22 #ifdef __BEOS__
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23 #define usleep(t) snooze(t)
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24 #endif
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25
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26 #ifdef M_UNIX
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27 typedef long long int64_t;
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28 #define MISSING_USLEEP
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29 #else
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30 #include <inttypes.h>
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31 #endif
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32
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33
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34 typedef struct cpuid_regs {
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35 unsigned int eax;
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36 unsigned int ebx;
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37 unsigned int ecx;
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38 unsigned int edx;
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39 } cpuid_regs_t;
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40
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41 static cpuid_regs_t
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42 cpuid(int func) {
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43 cpuid_regs_t regs;
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44 #define CPUID ".byte 0x0f, 0xa2; "
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45 asm("push %%ebx; "
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46 "movl %4,%%eax; " CPUID
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47 "movl %%eax,%0; movl %%ebx,%1; movl %%ecx,%2; movl %%edx,%3; "
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48 "pop %%ebx"
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49 : "=m" (regs.eax), "=m" (regs.ebx), "=m" (regs.ecx), "=m" (regs.edx)
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50 : "g" (func)
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51 : "%eax", "%ecx", "%edx");
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52 return regs;
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53 }
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54
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55
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56 static int64_t
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57 rdtsc(void)
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58 {
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59 unsigned int i, j;
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60 #define RDTSC ".byte 0x0f, 0x31; "
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61 asm(RDTSC : "=a"(i), "=d"(j) : );
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62 return ((int64_t)j<<32) + (int64_t)i;
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63 }
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64
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65
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66 static void
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67 store32(char *d, unsigned int v)
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68 {
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69 d[0] = v & 0xff;
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70 d[1] = (v >> 8) & 0xff;
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71 d[2] = (v >> 16) & 0xff;
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72 d[3] = (v >> 24) & 0xff;
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73 }
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74
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75
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76 int
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77 main(int argc, char **argv)
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78 {
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79 cpuid_regs_t regs, regs_ext;
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80 char idstr[13];
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81 unsigned max_cpuid;
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82 unsigned max_ext_cpuid;
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83 unsigned int amd_flags;
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84 unsigned int amd_flags2;
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85 char *model_name = "Unknown CPU";
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86 int i;
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87 char processor_name[49];
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88
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89 regs = cpuid(0);
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90 max_cpuid = regs.eax;
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91 /* printf("%d CPUID function codes\n", max_cpuid+1); */
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92
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93 store32(idstr+0, regs.ebx);
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94 store32(idstr+4, regs.edx);
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95 store32(idstr+8, regs.ecx);
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96 idstr[12] = 0;
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97 printf("vendor_id\t: %s\n", idstr);
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98
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99 if (strcmp(idstr, "GenuineIntel") == 0)
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100 model_name = "Unknown Intel CPU";
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101 else if (strcmp(idstr, "AuthenticAMD") == 0)
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102 model_name = "Unknown AMD CPU";
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103
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104 regs_ext = cpuid((1<<31) + 0);
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105 max_ext_cpuid = regs_ext.eax;
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106 if (max_ext_cpuid >= (1<<31) + 1) {
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107 regs_ext = cpuid((1<<31) + 1);
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108 amd_flags = regs_ext.edx;
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109 amd_flags2 = regs_ext.ecx;
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110
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111 if (max_ext_cpuid >= (1<<31) + 4) {
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112 for (i = 2; i <= 4; i++) {
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113 regs_ext = cpuid((1<<31) + i);
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114 store32(processor_name + (i-2)*16, regs_ext.eax);
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115 store32(processor_name + (i-2)*16 + 4, regs_ext.ebx);
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116 store32(processor_name + (i-2)*16 + 8, regs_ext.ecx);
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117 store32(processor_name + (i-2)*16 + 12, regs_ext.edx);
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118 }
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119 processor_name[48] = 0;
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120 model_name = processor_name;
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121 }
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122 } else {
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123 amd_flags = 0;
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124 amd_flags2 = 0;
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125 }
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126
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127 if (max_cpuid >= 1) {
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128 static struct {
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129 int bit;
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130 char *desc;;
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131 char *description;
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132 } cap[] = {
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133 { 0, "fpu", "Floating-point unit on-chip" },
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134 { 1, "vme", "Virtual Mode Enhancements" },
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135 { 2, "de", "Debugging Extension" },
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136 { 3, "pse", "Page Size Extension" },
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137 { 4, "tsc", "Time Stamp Counter" },
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138 { 5, "msr", "Pentium Processor MSR" },
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139 { 6, "pae", "Physical Address Extension" },
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140 { 7, "mce", "Machine Check Exception" },
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141 { 8, "cx8", "CMPXCHG8B Instruction Supported" },
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142 { 9, "apic", "On-chip CPIC Hardware Enabled" },
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143 { 11, "sep", "SYSENTER and SYSEXIT" },
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144 { 12, "mtrr", "Memory Type Range Registers" },
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145 { 13, "pge", "PTE Global Bit" },
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146 { 14, "mca", "Machine Check Architecture" },
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147 { 15, "cmov", "Conditional Move/Compare Instruction" },
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148 { 16, "pat", "Page Attribute Table" },
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149 { 17, "pse36", "Page Size Extension 36-bit" },
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150 { 18, "psn", "Processor Serial Number" },
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151 { 19, "cflsh", "CFLUSH instruction" },
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152 { 21, "ds", "Debug Store" },
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153 { 22, "acpi", "Thermal Monitor and Clock Ctrl" },
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154 { 23, "mmx", "MMX Technology" },
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155 { 24, "fxsr", "FXSAVE/FXRSTOR" },
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156 { 25, "sse", "SSE Extensions" },
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157 { 26, "sse2", "SSE2 Extensions" },
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158 { 27, "ss", "Self Snoop" },
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159 { 28, "htt", "Multi-threading" },
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160 { 29, "tm", "Therm. Monitor" },
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161 { 30, "ia64", "IA-64 Processor" },
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162 { 31, "pbe", "Pend. Brk. EN." },
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163 { -1 }
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164 };
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165 static struct {
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166 int bit;
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167 char *desc;
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168 char *description;
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169 } cap2[] = {
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170 { 0, "sse3", "SSE3 Extensions" },
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171 { 3, "monitor", "MONITOR/MWAIT" },
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172 { 4, "ds-cpl", "CPL Qualified Debug Store" },
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173 { 5, "vmx", "Virtual Machine Extensions" },
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174 { 7, "est", "Enhanced Intel SpeedStep Technology" },
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175 { 8, "tm2", "Thermal Monitor 2" },
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176 { 10, "cnxt-id", "L1 Context ID" },
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177 { 13, "cmpxchg16b", "CMPXCHG16B Available" },
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178 { -1 }
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179 };
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180 static struct {
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181 int bit;
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182 char *desc;;
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183 char *description;
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184 } cap_amd[] = {
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185 { 11, "syscall", "SYSCALL and SYSRET" },
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186 { 19, "mp", "MP Capable" },
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187 { 20, "nx", "No-Execute Page Protection" },
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188 { 22, "mmxext","MMX Technology (AMD Extensions)" },
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189 { 25, "fxsr_opt", "Fast FXSAVE/FXRSTOR" },
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190 { 27, "rdtscp", "RDTSCP Instruction" },
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191 { 30, "3dnowext","3Dnow! Extensions" },
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192 { 31, "3dnow", "3Dnow!" },
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193 { -1 }
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194 };
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195 static struct {
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196 int bit;
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197 char *desc;
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198 char *description;
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199 } cap_amd2[] = {
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200 { 0, "lahf_lm", "LAHF/SAHF Supported in 64-bit Mode" },
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201 { 1, "cmp_legacy", "Chip Multi-Core" },
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202 { 2, "svm", "Secure Virtual Machine" },
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203 { 4, "cr8", "CR8 Available in Legacy Mode" },
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204 { -1 }
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205 };
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206 unsigned int family, model, stepping;
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207
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208 regs = cpuid(1);
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209 printf("cpu family\t: %d\n"
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210 "model\t\t: %d\n"
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211 "stepping\t: %d\n" ,
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212 family = (regs.eax >> 8) & 0xf,
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213 model = (regs.eax >> 4) & 0xf,
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214 stepping = regs.eax & 0xf);
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215
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216 printf("flags\t\t:");
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217 for (i = 0; cap[i].bit >= 0; i++) {
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218 if (regs.edx & (1 << cap[i].bit)) {
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219 printf(" %s", cap[i].desc);
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220 }
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221 }
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222 for (i = 0; cap2[i].bit >= 0; i++) {
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223 if (regs.ecx & (1 << cap[i].bit)) {
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224 printf(" %s", cap2[i].desc);
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225 }
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226 }
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227 /* k6_mtrr is supported by some AMD K6-2/K6-III CPUs but
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228 it is not indicated by a CPUID feature bit, so we
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229 have to check the family, model and stepping instead. */
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230 if (strstr(idstr, "AMD") &&
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231 family == 5 &&
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232 (model >= 9 || model == 8 && stepping >= 8))
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233 printf(" %s", "k6_mtrr");
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234
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235 for (i = 0; cap_amd[i].bit >= 0; i++) {
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236 if (amd_flags & (1 << cap_amd[i].bit)) {
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237 printf(" %s", cap_amd[i].desc);
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238 }
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239 }
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240 for (i = 0; cap_amd2[i].bit >= 0; i++) {
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241 if (amd_flags2 & (1 << cap_amd2[i].bit)) {
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242 printf(" %s", cap_amd2[i].desc);
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243 }
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244 }
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245 printf("\n");
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246
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247 if (regs.edx & (1 << 4)) {
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248 int64_t tsc_start, tsc_end;
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249 struct timeval tv_start, tv_end;
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250 int usec_delay;
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251
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252 tsc_start = rdtsc();
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253 gettimeofday(&tv_start, NULL);
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254 #ifdef MISSING_USLEEP
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255 sleep(1);
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256 #else
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257 usleep(100000);
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258 #endif
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259 tsc_end = rdtsc();
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260 gettimeofday(&tv_end, NULL);
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261
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262 usec_delay = 1000000 * (tv_end.tv_sec - tv_start.tv_sec)
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263 + (tv_end.tv_usec - tv_start.tv_usec);
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264
17041
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265 printf("cpu MHz\t\t: %.3f\n",
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266 (double)(tsc_end-tsc_start) / usec_delay);
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267 }
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268 }
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269
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270 printf("model name\t: %s\n", model_name);
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271
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272 exit(0);
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273 }