comparison vidix/drivers/mach64_vid.c @ 4758:1d41ac612fb7

Fixes: - every line of movie is displayed instead of every odd before (v_inc: 11 -> 12; pitch -> pitch/2) - awful colored window on start (reset_regs: OUTREG(i,-1) -> OUTREG(i,0)) - YVYU fourcc displaying (SCALE_CNTL: 0xb0000 -> 0xc0000) - correct vertical scaling in double scan in interlaced modes (see y_x_start(end)) Note: tested 3DRage IIC doesn't support neihgter YV12 nor color correction so Michael should test and fix again these changes. Sorry!
author nick
date Tue, 19 Feb 2002 16:23:02 +0000
parents 412a67a4bf68
children d681c1b1c193
comparison
equal deleted inserted replaced
4757:4b794a67e9ca 4758:1d41ac612fb7
29 static uint32_t mach64_ram_size = 0; 29 static uint32_t mach64_ram_size = 0;
30 30
31 pciinfo_t pci_info; 31 pciinfo_t pci_info;
32 static int probed = 0; 32 static int probed = 0;
33 static int __verbose = 0; 33 static int __verbose = 0;
34
35 #define VERBOSE_LEVEL 1
34 36
35 typedef struct bes_registers_s 37 typedef struct bes_registers_s
36 { 38 {
37 /* base address of yuv framebuffer */ 39 /* base address of yuv framebuffer */
38 uint32_t yuv_base; 40 uint32_t yuv_base;
364 { 366 {
365 size_t i; 367 size_t i;
366 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) 368 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++)
367 { 369 {
368 mach64_fifo_wait(2); 370 mach64_fifo_wait(2);
369 OUTREG(vregs[i].name,-1); 371 OUTREG(vregs[i].name,0);
370 } 372 }
371 } 373 }
372 374
373 375
374 int vixInit(void) 376 int vixInit(void)
385 if (mach64_ram_size < 8) mach64_ram_size = (mach64_ram_size + 1) * 512; 387 if (mach64_ram_size < 8) mach64_ram_size = (mach64_ram_size + 1) * 512;
386 else if (mach64_ram_size < 12) mach64_ram_size = (mach64_ram_size - 3) * 1024; 388 else if (mach64_ram_size < 12) mach64_ram_size = (mach64_ram_size - 3) * 1024;
387 else mach64_ram_size = (mach64_ram_size - 7) * 2048; 389 else mach64_ram_size = (mach64_ram_size - 7) * 2048;
388 mach64_ram_size *= 0x400; /* KB -> bytes */ 390 mach64_ram_size *= 0x400; /* KB -> bytes */
389 if((mach64_mem_base = map_phys_mem(pci_info.base0,mach64_ram_size))==(void *)-1) return ENOMEM; 391 if((mach64_mem_base = map_phys_mem(pci_info.base0,mach64_ram_size))==(void *)-1) return ENOMEM;
390 // memset(&besr,0,sizeof(bes_registers_t)); 392 memset(&besr,0,sizeof(bes_registers_t));
391 mach64_vid_make_default(); 393 mach64_vid_make_default();
392 printf("[mach64] Video memory = %uMb\n",mach64_ram_size/0x100000); 394 printf("[mach64] Video memory = %uMb\n",mach64_ram_size/0x100000);
393 err = mtrr_set_type(pci_info.base0,mach64_ram_size,MTRR_TYPE_WRCOMB); 395 err = mtrr_set_type(pci_info.base0,mach64_ram_size,MTRR_TYPE_WRCOMB);
394 if(!err) printf("[mach64] Set write-combining type of video memory\n"); 396 if(!err) printf("[mach64] Set write-combining type of video memory\n");
395 reset_regs(); 397 reset_regs();
396 mach64_vid_dump_regs(); 398 if(__verbose > VERBOSE_LEVEL) mach64_vid_dump_regs();
397 return 0; 399 return 0;
398 } 400 }
399 401
400 void vixDestroy(void) 402 void vixDestroy(void)
401 { 403 {
514 OUTREG(SCALER_BUF0_OFFSET_U, besr.vid_buf1_base_adrs); 516 OUTREG(SCALER_BUF0_OFFSET_U, besr.vid_buf1_base_adrs);
515 OUTREG(SCALER_BUF0_OFFSET_V, besr.vid_buf2_base_adrs); 517 OUTREG(SCALER_BUF0_OFFSET_V, besr.vid_buf2_base_adrs);
516 OUTREG(SCALER_BUF1_OFFSET, besr.vid_buf3_base_adrs); 518 OUTREG(SCALER_BUF1_OFFSET, besr.vid_buf3_base_adrs);
517 OUTREG(SCALER_BUF1_OFFSET_U, besr.vid_buf4_base_adrs); 519 OUTREG(SCALER_BUF1_OFFSET_U, besr.vid_buf4_base_adrs);
518 OUTREG(SCALER_BUF1_OFFSET_V, besr.vid_buf5_base_adrs); 520 OUTREG(SCALER_BUF1_OFFSET_V, besr.vid_buf5_base_adrs);
519 OUTREG(OVERLAY_SCALE_CNTL, 0x04000001 | (3<<30)); 521 OUTREG(OVERLAY_SCALE_CNTL, 0xC4000003);
520 mach64_wait_for_idle(); 522 mach64_wait_for_idle();
521 vf = INREG(VIDEO_FORMAT); 523 vf = INREG(VIDEO_FORMAT);
522 524
523 // Bits 16-19 seem to select the format 525 // Bits 16-19 seem to select the format
524 // Bit 28 seems to toggle the chroma encoding 526 // Bit 28 seems to toggle the chroma encoding
530 case IMGFMT_IYUV: 532 case IMGFMT_IYUV:
531 case IMGFMT_I420: 533 case IMGFMT_I420:
532 case IMGFMT_YV12: OUTREG(VIDEO_FORMAT, (vf & ~0xF0000) | 0xA0000); break; 534 case IMGFMT_YV12: OUTREG(VIDEO_FORMAT, (vf & ~0xF0000) | 0xA0000); break;
533 /* 4:2:2 */ 535 /* 4:2:2 */
534 case IMGFMT_YVYU: 536 case IMGFMT_YVYU:
535 case IMGFMT_UYVY: OUTREG(VIDEO_FORMAT, (vf & ~0xF000) | 0xB000); break; 537 case IMGFMT_UYVY: OUTREG(VIDEO_FORMAT, (vf & ~0xF0000) | 0xC0000); break;
536 case IMGFMT_YUY2: 538 case IMGFMT_YUY2:
537 default: OUTREG(VIDEO_FORMAT, (vf & ~0xF0000) | 0xB0000); break; 539 default: OUTREG(VIDEO_FORMAT, (vf & ~0xF0000) | 0xB0000); break;
538 } 540 }
539 // OUTPLL(PLL_SCALER_LOCK_EN, 0); 541 if(__verbose > VERBOSE_LEVEL) mach64_vid_dump_regs();
540 if(__verbose > 1) mach64_vid_dump_regs();
541 } 542 }
542 543
543 static int mach64_vid_init_video( vidix_playback_t *config ) 544 static int mach64_vid_init_video( vidix_playback_t *config )
544 { 545 {
545 uint32_t src_w,src_h,dest_w,dest_h,pitch,h_inc,v_inc,left,leftUV,top,ecp; 546 uint32_t src_w,src_h,dest_w,dest_h,pitch,h_inc,v_inc,left,leftUV,top,ecp,y_pos;
546 int is_420,best_pitch,mpitch; 547 int is_420,best_pitch,mpitch;
547 mach64_vid_stop_video(); 548 mach64_vid_stop_video();
548 left = config->src.x << 16; 549 left = config->src.x << 16;
549 top = config->src.y << 16; 550 top = config->src.y << 16;
550 src_h = config->src.h; 551 src_h = config->src.h;
588 +(mach64_is_interlace()?1:0) 589 +(mach64_is_interlace()?1:0)
589 -(mach64_is_dbl_scan()?1:0) 590 -(mach64_is_dbl_scan()?1:0)
590 +(is_420?1:0) 591 +(is_420?1:0)
591 )) / dest_h; 592 )) / dest_h;
592 h_inc = (src_w << (12+ecp)) / dest_w; 593 h_inc = (src_w << (12+ecp)) / dest_w;
593 v_inc /= 2;
594 /* keep everything in 16.16 */ 594 /* keep everything in 16.16 */
595 config->offsets[0] = 0; 595 config->offsets[0] = 0;
596 config->offsets[1] = config->frame_size; 596 config->offsets[1] = config->frame_size;
597 if(is_420) 597 if(is_420)
598 { 598 {
636 } 636 }
637 637
638 leftUV = (left >> 17) & 15; 638 leftUV = (left >> 17) & 15;
639 left = (left >> 16) & 15; 639 left = (left >> 16) & 15;
640 besr.scale_inc = ( h_inc << 16 ) | v_inc; 640 besr.scale_inc = ( h_inc << 16 ) | v_inc;
641 besr.y_x_start = config->dest.y | (config->dest.x << 16); 641 y_pos = config->dest.y;
642 besr.y_x_end = (config->dest.y + dest_h) | ((config->dest.x + dest_w) << 16); 642 if(mach64_is_dbl_scan()) y_pos*=2;
643 else
644 if(mach64_is_interlace()) y_pos/=2;
645 besr.y_x_start = y_pos | (config->dest.x << 16);
646 y_pos =config->dest.y + dest_h;
647 if(mach64_is_dbl_scan()) y_pos*=2;
648 else
649 if(mach64_is_interlace()) y_pos/=2;
650 besr.y_x_end = y_pos | ((config->dest.x + dest_w) << 16);
643 besr.height_width = ((src_w - left)<<16) | (src_h - top); 651 besr.height_width = ((src_w - left)<<16) | (src_h - top);
644 besr.vid_buf_pitch = pitch; 652 besr.vid_buf_pitch = pitch/2;
645 return 0; 653 return 0;
646 } 654 }
647 655
648 656
649 uint32_t supported_fourcc[] = 657 uint32_t supported_fourcc[] =
744 OUTREG(SCALER_BUF0_OFFSET_U, off[1]); 752 OUTREG(SCALER_BUF0_OFFSET_U, off[1]);
745 OUTREG(SCALER_BUF0_OFFSET_V, off[2]); 753 OUTREG(SCALER_BUF0_OFFSET_V, off[2]);
746 OUTREG(SCALER_BUF1_OFFSET, off[3]); 754 OUTREG(SCALER_BUF1_OFFSET, off[3]);
747 OUTREG(SCALER_BUF1_OFFSET_U, off[4]); 755 OUTREG(SCALER_BUF1_OFFSET_U, off[4]);
748 OUTREG(SCALER_BUF1_OFFSET_V, off[5]); 756 OUTREG(SCALER_BUF1_OFFSET_V, off[5]);
749 if(__verbose > 1) mach64_vid_dump_regs(); 757 if(__verbose > VERBOSE_LEVEL) mach64_vid_dump_regs();
750 return 0; 758 return 0;
751 } 759 }
752 760
753 vidix_video_eq_t equal = 761 vidix_video_eq_t equal =
754 { 762 {