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SiS 650/651/740/etc driver by Jake Page <jake@CS.Stanford.EDU>
author alex
date Tue, 07 Oct 2003 23:12:16 +0000
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children e16982ed6708
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11037:77ed12a4f0b1 11038:3bac281db5a1
1 /**
2 VIDIX driver for SiS 300 and 310/325 series chips.
3
4 Copyright 2003 Jake Page, Sugar Media.
5
6 Based on SiS Xv driver:
7 Copyright 2002-2003 by Thomas Winischhofer, Vienna, Austria.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22
23 2003/10/08 integrated into mplayer/vidix architecture -- Alex Beregszaszi
24 **/
25
26 #include <errno.h>
27 #include <stdio.h>
28 #include <stdlib.h>
29 #include <string.h>
30 #include <inttypes.h>
31 #include <unistd.h>
32 #include <sys/io.h>
33
34 #include "../vidix.h"
35 #include "../fourcc.h"
36 #include "../../libdha/libdha.h"
37 #include "../../libdha/pci_ids.h"
38 #include "../../libdha/pci_names.h"
39 #include "../../config.h"
40
41 #include "sis_regs.h"
42 #include "sis_defs.h"
43
44
45 /** Random defines **/
46
47 #define WATCHDOG_DELAY 500000 /* Watchdog counter for retrace waiting */
48 #define IMAGE_MIN_WIDTH 32 /* Min and max source image sizes */
49 #define IMAGE_MIN_HEIGHT 24
50 #define IMAGE_MAX_WIDTH 720
51 #define IMAGE_MAX_HEIGHT 576
52 #define IMAGE_MAX_WIDTH_M650 1920
53 #define IMAGE_MAX_HEIGHT_M650 1080
54
55 #define OVERLAY_MIN_WIDTH 32 /* Minimum overlay sizes */
56 #define OVERLAY_MIN_HEIGHT 24
57
58 #define DISPMODE_SINGLE1 0x1 /* TW: CRT1 only */
59 #define DISPMODE_SINGLE2 0x2 /* TW: CRT2 only */
60 #define DISPMODE_MIRROR 0x4 /* TW: CRT1 + CRT2 MIRROR */
61
62 #define VMODE_INTERLACED 0x1
63 #define VMODE_DOUBLESCAN 0x2
64
65 typedef struct {
66 short x1, y1, x2, y2;
67 } BoxRec;
68
69 typedef struct {
70 int pixelFormat;
71
72 uint16_t pitch;
73 uint16_t origPitch;
74
75 uint8_t keyOP;
76 uint16_t HUSF;
77 uint16_t VUSF;
78 uint8_t IntBit;
79 uint8_t wHPre;
80
81 uint16_t srcW;
82 uint16_t srcH;
83
84 BoxRec dstBox;
85
86 uint32_t PSY;
87 uint32_t PSV;
88 uint32_t PSU;
89 uint8_t bobEnable;
90
91 uint8_t contrastCtrl;
92 uint8_t contrastFactor;
93
94 uint8_t lineBufSize;
95
96 uint8_t(*VBlankActiveFunc) ();
97
98 uint16_t SCREENheight;
99
100 } SISOverlayRec, *SISOverlayPtr;
101
102
103 /** static variable definitions **/
104 static int sis_probed = 0;
105 static pciinfo_t pci_info;
106 unsigned int sis_verbose = 0;
107
108 static void *sis_mem_base;
109 /* static void *sis_reg_base; */
110 unsigned short sis_iobase;
111
112 unsigned int sis_vga_engine = UNKNOWN_VGA;
113 static unsigned int sis_displaymode = DISPMODE_SINGLE1;
114 static unsigned int sis_has_two_overlays = 0;
115 static unsigned int sis_bridge_is_slave = 0;
116 static unsigned int sis_shift_value = 1;
117 static unsigned int sis_vmode = 0;
118 unsigned int sis_vbflags = DISPTYPE_DISP1;
119 unsigned int sis_overlay_on_crt1 = 1;
120 unsigned int sis_crt1_off = -1;
121 unsigned int sis_detected_crt2_devices;
122 unsigned int sis_force_crt2_type = CRT2_DEFAULT;
123 unsigned int sis_device_id = -1;
124
125 static int sis_format;
126 static int sis_Yoff = 0;
127 static int sis_Voff = 0;
128 static int sis_Uoff = 0;
129 static int sis_screen_width = 640;
130 static int sis_screen_height = 480;
131
132 static int sis_frames[VID_PLAY_MAXFRAMES];
133
134 static vidix_grkey_t sis_grkey;
135
136 static vidix_capability_t sis_cap = {
137 "SiS 300/310/325 Video Driver",
138 "Jake Page",
139 TYPE_OUTPUT,
140 {0, 0, 0, 0},
141 2048,
142 2048,
143 4,
144 4,
145 -1,
146 FLAG_UPSCALER | FLAG_DOWNSCALER | FLAG_EQUALIZER,
147 VENDOR_SIS,
148 -1,
149 {0, 0, 0, 0}
150 };
151
152 vidix_video_eq_t sis_equal = {
153 VEQ_CAP_BRIGHTNESS | VEQ_CAP_CONTRAST,
154 200, 0, 0, 0, 0, 0, 0, 0
155 };
156
157 static unsigned short sis_card_ids[] = {
158 DEVICE_SIS_300,
159 DEVICE_SIS_315H,
160 DEVICE_SIS_315,
161 DEVICE_SIS_315PRO,
162 DEVICE_SIS_330,
163 DEVICE_SIS_540_VGA,
164 DEVICE_SIS_550_VGA,
165 DEVICE_SIS_630_VGA,
166 DEVICE_SIS_650_VGA
167 };
168
169 /** function declarations **/
170
171 extern void sis_init_video_bridge();
172
173
174 static void set_overlay(SISOverlayPtr pOverlay, int index);
175 static void close_overlay();
176 static void calc_scale_factor(SISOverlayPtr pOverlay,
177 int index, int iscrt2);
178 static void set_line_buf_size(SISOverlayPtr pOverlay);
179 static void merge_line_buf(int enable);
180 static void set_format(SISOverlayPtr pOverlay);
181 static void set_colorkey();
182
183 static void set_brightness(uint8_t brightness);
184 static void set_contrast(uint8_t contrast);
185 static void set_saturation(char saturation);
186 static void set_hue(uint8_t hue);
187 #if 0
188 static void set_alpha(uint8_t alpha);
189 #endif
190
191 /* IO Port access functions */
192 static uint8_t getvideoreg(uint8_t reg)
193 {
194 uint8_t ret;
195 inSISIDXREG(SISVID, reg, ret);
196 return (ret);
197 }
198
199 static void setvideoreg(uint8_t reg, uint8_t data)
200 {
201 outSISIDXREG(SISVID, reg, data);
202 }
203
204 static void setvideoregmask(uint8_t reg, uint8_t data, uint8_t mask)
205 {
206 uint8_t old;
207
208 inSISIDXREG(SISVID, reg, old);
209 data = (data & mask) | (old & (~mask));
210 outSISIDXREG(SISVID, reg, data);
211 }
212
213 static void setsrregmask(uint8_t reg, uint8_t data, uint8_t mask)
214 {
215 uint8_t old;
216
217 inSISIDXREG(SISSR, reg, old);
218 data = (data & mask) | (old & (~mask));
219 outSISIDXREG(SISSR, reg, data);
220 }
221
222 /* vblank checking*/
223 static uint8_t vblank_active_CRT1()
224 {
225 /* this may be too simplistic? */
226 return (inSISREG(SISINPSTAT) & 0x08);
227 }
228
229 static uint8_t vblank_active_CRT2()
230 {
231 uint8_t ret;
232 if (sis_vga_engine == SIS_315_VGA) {
233 inSISIDXREG(SISPART1, Index_310_CRT2_FC_VR, ret);
234 } else {
235 inSISIDXREG(SISPART1, Index_CRT2_FC_VR, ret);
236 }
237 return ((ret & 0x02) ^ 0x02);
238 }
239
240
241 unsigned int vixGetVersion(void)
242 {
243 return (VIDIX_VERSION);
244 }
245
246 static int find_chip(unsigned chip_id)
247 {
248 unsigned i;
249 for (i = 0; i < sizeof(sis_card_ids) / sizeof(unsigned short); i++) {
250 if (chip_id == sis_card_ids[i])
251 return i;
252 }
253 return -1;
254 }
255
256 int vixProbe(int verbose, int force)
257 {
258 pciinfo_t lst[MAX_PCI_DEVICES];
259 unsigned i, num_pci;
260 int err;
261
262 sis_verbose = verbose;
263 force = force;
264 err = pci_scan(lst, &num_pci);
265 if (err) {
266 printf("[SiS] Error occured during pci scan: %s\n", strerror(err));
267 return err;
268 } else {
269 err = ENXIO;
270 for (i = 0; i < num_pci; i++) {
271 if (lst[i].vendor == VENDOR_SIS) {
272 int idx;
273 const char *dname;
274 idx = find_chip(lst[i].device);
275 if (idx == -1)
276 continue;
277 dname = pci_device_name(VENDOR_SIS, lst[i].device);
278 dname = dname ? dname : "Unknown chip";
279 if (sis_verbose > 0)
280 printf("[SiS] Found chip: %s (0x%X)\n",
281 dname, lst[i].device);
282 sis_device_id = sis_cap.device_id = lst[i].device;
283 err = 0;
284 memcpy(&pci_info, &lst[i], sizeof(pciinfo_t));
285
286 sis_has_two_overlays = 0;
287 switch (sis_cap.device_id) {
288 case DEVICE_SIS_300:
289 case DEVICE_SIS_630_VGA:
290 sis_has_two_overlays = 1;
291 case DEVICE_SIS_540_VGA:
292 sis_vga_engine = SIS_300_VGA;
293 break;
294 case DEVICE_SIS_330:
295 case DEVICE_SIS_550_VGA:
296 sis_has_two_overlays = 1;
297 case DEVICE_SIS_315H:
298 case DEVICE_SIS_315:
299 case DEVICE_SIS_315PRO:
300 case DEVICE_SIS_650_VGA:
301 /* M650 & 651 have 2 overlays */
302 /* JCP: I think this works, but not really tested yet */
303 {
304 unsigned char CR5F;
305 unsigned char tempreg1, tempreg2;
306
307 inSISIDXREG(SISCR, 0x5F, CR5F);
308 CR5F &= 0xf0;
309 andSISIDXREG(SISCR, 0x5c, 0x07);
310 inSISIDXREG(SISCR, 0x5c, tempreg1);
311 tempreg1 &= 0xf8;
312 setSISIDXREG(SISCR, 0x5c, 0x07, 0xf8);
313 inSISIDXREG(SISCR, 0x5c, tempreg2);
314 tempreg2 &= 0xf8;
315 if ((!tempreg1) || (tempreg2)) {
316 if (CR5F & 0x80) {
317 sis_has_two_overlays = 1;
318 }
319 } else {
320 sis_has_two_overlays = 1; /* ? */
321 }
322 if (sis_has_two_overlays) {
323 if (sis_verbose > 0)
324 printf
325 ("[SiS] detected M650/651 with 2 overlays\n");
326 }
327 }
328 sis_vga_engine = SIS_315_VGA;
329 break;
330 default:
331 /* should never get here */
332 sis_vga_engine = UNKNOWN_VGA;
333 break;
334 }
335 }
336 }
337 }
338 if (err && sis_verbose) {
339 printf("[SiS] Can't find chip\n");
340 } else {
341 sis_probed = 1;
342 }
343
344 return err;
345 }
346
347 int vixInit(void)
348 {
349 uint8_t sr_data, cr_data, cr_data2;
350 char *env_overlay_crt;
351
352 if (!sis_probed) {
353 printf("[SiS] driver was not probed but is being initialized\n");
354 return (EINTR);
355 }
356
357 /* JCP: this is WRONG. Need to coordinate w/ sisfb to use correct mem */
358 /* map 16MB scary hack for now. */
359 sis_mem_base = map_phys_mem(pci_info.base0, 0x1000000);
360 /* sis_reg_base = map_phys_mem(pci_info.base1, 0x20000); */
361 sis_iobase = pci_info.base2 & 0xFFFC;
362
363 /* would like to use fb ioctl - or some other method - here to get
364 current resolution. */
365 inSISIDXREG(SISCR, 0x12, cr_data);
366 inSISIDXREG(SISCR, 0x07, cr_data2);
367 sis_screen_height =
368 ((cr_data & 0xff) | ((uint16_t) (cr_data2 & 0x02) << 7) |
369 ((uint16_t) (cr_data2 & 0x40) << 3) | ((uint16_t) (sr_data & 0x02)
370 << 9)) + 1;
371
372 inSISIDXREG(SISSR, 0x0b, sr_data);
373 inSISIDXREG(SISCR, 0x01, cr_data);
374 sis_screen_width = (((cr_data & 0xff) |
375 ((uint16_t) (sr_data & 0x0C) << 6)) + 1) * 8;
376
377 inSISIDXREG(SISSR, Index_SR_Graphic_Mode, sr_data);
378 if (sr_data & 0x20) /* interlaced mode */
379 sis_vmode |= VMODE_INTERLACED;
380
381 #if 0 /* getting back false data here... */
382 /* CR9 bit 7 set = double scan active */
383 inSISIDXREG(SISCR, 0x09, cr_data);
384 if (cr_data & 0x40) {
385 sis_vmode |= VMODE_DOUBLESCAN;
386 }
387 #endif
388
389 /* JCP: eventually I'd like to replace this with a call to sisfb
390 SISFB_GET_INFO ioctl to get video bridge info. Not for now,
391 since it requires a very new and not widely distributed version. */
392 sis_init_video_bridge();
393
394 env_overlay_crt = getenv("VIDIX_CRT");
395 if (env_overlay_crt) {
396 int crt = atoi(env_overlay_crt);
397 if (crt == 1 || crt == 2) {
398 sis_overlay_on_crt1 = (crt == 1);
399 if (sis_verbose > 0) {
400 printf
401 ("[SiS] override: using overlay on CRT%d from VIDIX_CRT\n",
402 crt);
403 }
404 }
405 }
406
407 return 0;
408 }
409
410 void vixDestroy(void)
411 {
412 /* unmap_phys_mem(sis_reg_base, 0x20000); */
413 /* JCP: see above, hence also a hack. */
414 unmap_phys_mem(sis_mem_base, 0x1000000);
415 }
416
417 int vixGetCapability(vidix_capability_t * to)
418 {
419 memcpy(to, &sis_cap, sizeof(vidix_capability_t));
420 return 0;
421 }
422
423 static int is_supported_fourcc(uint32_t fourcc)
424 {
425 switch (fourcc) {
426 case IMGFMT_YV12:
427 case IMGFMT_I420:
428 case IMGFMT_UYVY:
429 case IMGFMT_YUY2:
430 case IMGFMT_RGB15:
431 case IMGFMT_RGB16:
432 return 1;
433 default:
434 return 0;
435 }
436 }
437
438 int vixQueryFourcc(vidix_fourcc_t * to)
439 {
440 if (is_supported_fourcc(to->fourcc)) {
441 to->depth = VID_DEPTH_8BPP | VID_DEPTH_16BPP | VID_DEPTH_32BPP;
442 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY;
443 return 0;
444 } else
445 to->depth = to->flags = 0;
446 return ENOSYS;
447 }
448
449 static int bridge_in_slave_mode()
450 {
451 unsigned char usScratchP1_00;
452
453 if (!(sis_vbflags & VB_VIDEOBRIDGE))
454 return 0;
455
456 inSISIDXREG(SISPART1, 0x00, usScratchP1_00);
457 if (((sis_vga_engine == SIS_300_VGA)
458 && (usScratchP1_00 & 0xa0) == 0x20)
459 || ((sis_vga_engine == SIS_315_VGA)
460 && (usScratchP1_00 & 0x50) == 0x10)) {
461 return 1;
462 } else {
463 return 0;
464 }
465 }
466
467 /* This does not handle X dual head mode, since 1) vidix doesn't support it
468 and 2) it doesn't make sense for other gfx drivers */
469 static void set_dispmode()
470 {
471 sis_bridge_is_slave = 0;
472
473 if (bridge_in_slave_mode())
474 sis_bridge_is_slave = 1;
475
476 if ((sis_vbflags & VB_DISPMODE_MIRROR) ||
477 (sis_bridge_is_slave && (sis_vbflags & DISPTYPE_DISP2))) {
478 if (sis_has_two_overlays)
479 sis_displaymode = DISPMODE_MIRROR; /* TW: CRT1+CRT2 (2 overlays) */
480 else if (!sis_overlay_on_crt1)
481 sis_displaymode = DISPMODE_SINGLE2;
482 else
483 sis_displaymode = DISPMODE_SINGLE1;
484 } else {
485 if (sis_vbflags & DISPTYPE_DISP1) {
486 sis_displaymode = DISPMODE_SINGLE1; /* TW: CRT1 only */
487 } else {
488 sis_displaymode = DISPMODE_SINGLE2; /* TW: CRT2 only */
489 }
490 }
491 }
492
493 static void set_disptype_regs()
494 {
495 switch (sis_displaymode) {
496 case DISPMODE_SINGLE1: /* TW: CRT1 only */
497 if (sis_verbose > 2) {
498 printf("[SiS] Setting up overlay on CRT1\n");
499 }
500 if (sis_has_two_overlays) {
501 setsrregmask(0x06, 0x00, 0xc0);
502 setsrregmask(0x32, 0x00, 0xc0);
503 } else {
504 setsrregmask(0x06, 0x00, 0xc0);
505 setsrregmask(0x32, 0x00, 0xc0);
506 }
507 break;
508 case DISPMODE_SINGLE2: /* TW: CRT2 only */
509 if (sis_verbose > 2) {
510 printf("[SiS] Setting up overlay on CRT2\n");
511 }
512 if (sis_has_two_overlays) {
513 setsrregmask(0x06, 0x80, 0xc0);
514 setsrregmask(0x32, 0x80, 0xc0);
515 } else {
516 setsrregmask(0x06, 0x40, 0xc0);
517 setsrregmask(0x32, 0x40, 0xc0);
518 }
519 break;
520 case DISPMODE_MIRROR: /* TW: CRT1 + CRT2 */
521 default:
522 if (sis_verbose > 2) {
523 printf("[SiS] Setting up overlay on CRT1 AND CRT2!\n");
524 }
525 setsrregmask(0x06, 0x80, 0xc0);
526 setsrregmask(0x32, 0x80, 0xc0);
527 break;
528 }
529 }
530
531 static void init_overlay()
532 {
533 /* Initialize first overlay (CRT1) */
534
535 /* Write-enable video registers */
536 setvideoregmask(Index_VI_Control_Misc2, 0x80, 0x81);
537
538 /* Disable overlay */
539 setvideoregmask(Index_VI_Control_Misc0, 0x00, 0x02);
540
541 /* Disable bobEnable */
542 setvideoregmask(Index_VI_Control_Misc1, 0x02, 0x02);
543
544 /* Reset scale control and contrast */
545 setvideoregmask(Index_VI_Scale_Control, 0x60, 0x60);
546 setvideoregmask(Index_VI_Contrast_Enh_Ctrl, 0x04, 0x1F);
547
548 setvideoreg(Index_VI_Disp_Y_Buf_Preset_Low, 0x00);
549 setvideoreg(Index_VI_Disp_Y_Buf_Preset_Middle, 0x00);
550 setvideoreg(Index_VI_UV_Buf_Preset_Low, 0x00);
551 setvideoreg(Index_VI_UV_Buf_Preset_Middle, 0x00);
552 setvideoreg(Index_VI_Disp_Y_UV_Buf_Preset_High, 0x00);
553 setvideoreg(Index_VI_Play_Threshold_Low, 0x00);
554 setvideoreg(Index_VI_Play_Threshold_High, 0x00);
555
556 /* may not want to init these here, could already be set to other
557 values by app? */
558 setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x01);
559 setvideoregmask(Index_VI_Contrast_Enh_Ctrl, 0x04, 0x07);
560 setvideoreg(Index_VI_Brightness, 0x20);
561 if (sis_vga_engine == SIS_315_VGA) {
562 setvideoreg(Index_VI_Hue, 0x00);
563 setvideoreg(Index_VI_Saturation, 0x00);
564 }
565
566 /* Initialize second overlay (CRT2) */
567 if (sis_has_two_overlays) {
568 /* Write-enable video registers */
569 setvideoregmask(Index_VI_Control_Misc2, 0x81, 0x81);
570
571 /* Disable overlay */
572 setvideoregmask(Index_VI_Control_Misc0, 0x00, 0x02);
573
574 /* Disable bobEnable */
575 setvideoregmask(Index_VI_Control_Misc1, 0x02, 0x02);
576
577 /* Reset scale control and contrast */
578 setvideoregmask(Index_VI_Scale_Control, 0x60, 0x60);
579 setvideoregmask(Index_VI_Contrast_Enh_Ctrl, 0x04, 0x1F);
580
581 setvideoreg(Index_VI_Disp_Y_Buf_Preset_Low, 0x00);
582 setvideoreg(Index_VI_Disp_Y_Buf_Preset_Middle, 0x00);
583 setvideoreg(Index_VI_UV_Buf_Preset_Low, 0x00);
584 setvideoreg(Index_VI_UV_Buf_Preset_Middle, 0x00);
585 setvideoreg(Index_VI_Disp_Y_UV_Buf_Preset_High, 0x00);
586 setvideoreg(Index_VI_Play_Threshold_Low, 0x00);
587 setvideoreg(Index_VI_Play_Threshold_High, 0x00);
588
589 setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x01);
590 setvideoregmask(Index_VI_Contrast_Enh_Ctrl, 0x04, 0x07);
591 setvideoreg(Index_VI_Brightness, 0x20);
592 if (sis_vga_engine == SIS_315_VGA) {
593 setvideoreg(Index_VI_Hue, 0x00);
594 setvideoreg(Index_VI_Saturation, 0x00);
595 }
596 }
597 }
598
599 int vixConfigPlayback(vidix_playback_t * info)
600 {
601 SISOverlayRec overlay;
602 int srcOffsetX = 0, srcOffsetY = 0;
603 int sx, sy;
604 int index = 0, iscrt2 = 0;
605 int total_size;
606
607 short src_w, drw_w;
608 short src_h, drw_h;
609 short src_x, drw_x;
610 short src_y, drw_y;
611 long dga_offset;
612 int pitch;
613 unsigned int i;
614
615 if (!is_supported_fourcc(info->fourcc))
616 return -1;
617
618 /* set chipset/engine.dependent config info */
619 /* which CRT to use, etc.? */
620 switch (sis_vga_engine) {
621 case SIS_315_VGA:
622 sis_shift_value = 1;
623 sis_equal.cap |= VEQ_CAP_SATURATION | VEQ_CAP_HUE;
624 break;
625 case SIS_300_VGA:
626 default:
627 sis_shift_value = 2;
628 break;
629 }
630
631 sis_displaymode = DISPMODE_SINGLE1; /* xV driver code in set_dispmode() */
632 set_dispmode();
633
634 set_disptype_regs();
635
636 init_overlay();
637
638 /* get basic dimension info */
639 src_x = info->src.x;
640 src_y = info->src.y;
641 src_w = info->src.w;
642 src_h = info->src.h;
643
644 drw_x = info->dest.x;
645 drw_y = info->dest.y;
646 drw_w = info->dest.w;
647 drw_h = info->dest.h;
648
649 switch (info->fourcc) {
650 case IMGFMT_YV12:
651 case IMGFMT_I420:
652 pitch = (src_w + 7) & ~7;
653 total_size = (pitch * src_h * 3) >> 1;
654 break;
655 case IMGFMT_YUY2:
656 case IMGFMT_UYVY:
657 case IMGFMT_RGB15:
658 case IMGFMT_RGB16:
659 pitch = ((src_w << 1) + 3) & ~3;
660 total_size = pitch * src_h;
661 break;
662 default:
663 return -1;
664 }
665
666 /* "allocate" memory for overlay! */
667 /* start at 8MB = sisfb's "dri reserved space" -
668 really shouldn't hardcode though */
669 /* XXX: JCP - this can use the sisfb FBIO_ALLOC ioctl to safely
670 allocate "video heap" memory... */
671 dga_offset = 0x800000;
672
673 /* use 7MB for now. need to calc/get real info from sisfb? */
674 /* this can result in a LOT of frames - probably not necessary */
675 info->num_frames = 0x700000 / (total_size * 2);
676 if (info->num_frames > VID_PLAY_MAXFRAMES)
677 info->num_frames = VID_PLAY_MAXFRAMES;
678
679 info->dga_addr = sis_mem_base + dga_offset;
680 info->dest.pitch.y = 16;
681 info->dest.pitch.u = 16;
682 info->dest.pitch.v = 16;
683 info->offset.y = 0;
684 info->offset.u = 0;
685 info->offset.v = 0;
686 info->frame_size = (total_size * 2); /* why times 2 ? */
687 for (i = 0; i < info->num_frames; i++) {
688 info->offsets[i] = info->frame_size * i;
689 /* save ptrs to mem buffers */
690 sis_frames[i] = (dga_offset + info->offsets[i]);
691 }
692
693 memset(&overlay, 0, sizeof(overlay));
694 overlay.pixelFormat = sis_format = info->fourcc;
695 overlay.pitch = overlay.origPitch = pitch;
696
697
698 overlay.keyOP = (sis_grkey.ckey.op == CKEY_TRUE ?
699 VI_ROP_DestKey : VI_ROP_Always);
700
701 overlay.bobEnable = 0x00;
702
703 overlay.SCREENheight = sis_screen_height;
704
705 /* probably will not support X virtual screen > phys very well? */
706 overlay.dstBox.x1 = drw_x; /* - pScrn->frameX0; */
707 overlay.dstBox.x2 = drw_x + drw_w; /* - pScrn->frameX0; ??? */
708 overlay.dstBox.y1 = drw_y; /* - pScrn->frameY0; */
709 overlay.dstBox.y2 = drw_y + drw_h; /* - pScrn->frameY0; ??? */
710
711 if ((overlay.dstBox.x1 > overlay.dstBox.x2) ||
712 (overlay.dstBox.y1 > overlay.dstBox.y2))
713 return -1;
714
715 if ((overlay.dstBox.x2 < 0) || (overlay.dstBox.y2 < 0))
716 return -1;
717
718 if (overlay.dstBox.x1 < 0) {
719 srcOffsetX = src_w * (-overlay.dstBox.x1) / drw_w;
720 overlay.dstBox.x1 = 0;
721 }
722 if (overlay.dstBox.y1 < 0) {
723 srcOffsetY = src_h * (-overlay.dstBox.y1) / drw_h;
724 overlay.dstBox.y1 = 0;
725 }
726
727 switch (info->fourcc) {
728 case IMGFMT_YV12:
729 info->dest.pitch.y = 16;
730 sx = (src_x + srcOffsetX) & ~7;
731 sy = (src_y + srcOffsetY) & ~1;
732 info->offset.y = sis_Yoff = sx + sy * pitch;
733 /* JCP: NOTE reversed u & v here! Not sure why this is needed.
734 maybe mplayer & sis define U & V differently?? */
735 info->offset.u = sis_Voff =
736 src_h * pitch + ((sx + sy * pitch / 2) >> 1);
737 info->offset.v = sis_Uoff =
738 src_h * pitch * 5 / 4 + ((sx + sy * pitch / 2) >> 1);
739
740 overlay.PSY = (sis_frames[0] + sis_Yoff) >> sis_shift_value;
741 overlay.PSV = (sis_frames[0] + sis_Voff) >> sis_shift_value;
742 overlay.PSU = (sis_frames[0] + sis_Uoff) >> sis_shift_value;
743 break;
744 case IMGFMT_I420:
745 sx = (src_x + srcOffsetX) & ~7;
746 sy = (src_y + srcOffsetY) & ~1;
747 info->offset.y = sis_Yoff = sx + sy * pitch;
748 /* JCP: see above... */
749 info->offset.u = sis_Voff =
750 src_h * pitch * 5 / 4 + ((sx + sy * pitch / 2) >> 1);
751 info->offset.v = sis_Uoff =
752 src_h * pitch + ((sx + sy * pitch / 2) >> 1);
753
754 overlay.PSY = (sis_frames[0] + sis_Yoff) >> sis_shift_value;
755 overlay.PSV = (sis_frames[0] + sis_Voff) >> sis_shift_value;
756 overlay.PSU = (sis_frames[0] + sis_Uoff) >> sis_shift_value;
757 break;
758 case IMGFMT_YUY2:
759 case IMGFMT_UYVY:
760 case IMGFMT_RGB16:
761 case IMGFMT_RGB15:
762 default:
763 sx = (src_x + srcOffsetX) & ~1;
764 sy = (src_y + srcOffsetY);
765 info->offset.y = sis_Yoff = sx * 2 + sy * pitch;
766
767 overlay.PSY = (sis_frames[0] + sis_Yoff) >> sis_shift_value;
768 break;
769 }
770
771 /* FIXME: is it possible that srcW < 0? */
772 overlay.srcW = src_w - (sx - src_x);
773 overlay.srcH = src_h - (sy - src_y);
774
775 /* JCP: what to do about this? */
776 #if 0
777 if ((pPriv->oldx1 != overlay.dstBox.x1) ||
778 (pPriv->oldx2 != overlay.dstBox.x2) ||
779 (pPriv->oldy1 != overlay.dstBox.y1) ||
780 (pPriv->oldy2 != overlay.dstBox.y2)) {
781 pPriv->mustwait = 1;
782 pPriv->oldx1 = overlay.dstBox.x1;
783 pPriv->oldx2 = overlay.dstBox.x2;
784 pPriv->oldy1 = overlay.dstBox.y1;
785 pPriv->oldy2 = overlay.dstBox.y2;
786 }
787 #endif
788
789 /* set merge line buffer */
790 merge_line_buf(overlay.srcW > 384);
791
792 /* calculate line buffer length */
793 set_line_buf_size(&overlay);
794
795 if (sis_displaymode == DISPMODE_SINGLE2) {
796 if (sis_has_two_overlays) {
797 /* TW: On chips with two overlays we use
798 * overlay 2 for CRT2 */
799 index = 1;
800 iscrt2 = 1;
801 } else {
802 /* TW: On chips with only one overlay we
803 * use that only overlay for CRT2 */
804 index = 0;
805 iscrt2 = 1;
806 }
807 overlay.VBlankActiveFunc = vblank_active_CRT2;
808 /* overlay.GetScanLineFunc = get_scanline_CRT2; */
809 } else {
810 index = 0;
811 iscrt2 = 0;
812 overlay.VBlankActiveFunc = vblank_active_CRT1;
813 /* overlay.GetScanLineFunc = get_scanline_CRT1; */
814 }
815
816 /* calc scale factor (to use below) */
817 calc_scale_factor(&overlay, index, iscrt2);
818
819 /* Select video1 (used for CRT1) or video2 (used for CRT2) */
820 setvideoregmask(Index_VI_Control_Misc2, index, 0x01);
821
822 set_format(&overlay);
823
824 set_colorkey();
825
826 vixPlaybackSetEq(&sis_equal);
827
828 /* set up video overlay registers */
829 set_overlay(&overlay, index);
830
831 /* prevent badness if bits are not at default setting */
832 setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x01);
833 setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x04);
834
835 /* JCP: Xv driver implementation loops back over above code to
836 setup mirror CRT2 */
837
838 return 0;
839 }
840
841 int vixPlaybackOn(void)
842 {
843 setvideoregmask(Index_VI_Control_Misc0, 0x02, 0x02);
844 return 0;
845 }
846
847 int vixPlaybackOff(void)
848 {
849 unsigned char sridx, cridx;
850 sridx = inSISREG(SISSR);
851 cridx = inSISREG(SISCR);
852 close_overlay();
853 outSISREG(SISSR, sridx);
854 outSISREG(SISCR, cridx);
855
856 return 0;
857 }
858
859 int vixPlaybackFrameSelect(unsigned int frame)
860 {
861 uint8_t data;
862 int index = 0;
863 uint32_t PSY;
864
865 if (sis_displaymode == DISPMODE_SINGLE2 && sis_has_two_overlays) {
866 index = 1;
867 }
868
869 PSY = (sis_frames[frame] + sis_Yoff) >> sis_shift_value;
870
871 /* Unlock address registers */
872 data = getvideoreg(Index_VI_Control_Misc1);
873 setvideoreg(Index_VI_Control_Misc1, data | 0x20);
874 /* TEST: Is this required? */
875 setvideoreg(Index_VI_Control_Misc1, data | 0x20);
876 /* TEST end */
877 /* TEST: Is this required? */
878 if (sis_vga_engine == SIS_315_VGA)
879 setvideoreg(Index_VI_Control_Misc3, 0x00);
880 /* TEST end */
881
882 /* set Y start address */
883 setvideoreg(Index_VI_Disp_Y_Buf_Start_Low, (uint8_t) (PSY));
884 setvideoreg(Index_VI_Disp_Y_Buf_Start_Middle, (uint8_t) ((PSY) >> 8));
885 setvideoreg(Index_VI_Disp_Y_Buf_Start_High, (uint8_t) ((PSY) >> 16));
886 /* set 310/325 series overflow bits for Y plane */
887 if (sis_vga_engine == SIS_315_VGA) {
888 setvideoreg(Index_VI_Y_Buf_Start_Over,
889 ((uint8_t) ((PSY) >> 24) & 0x01));
890 }
891
892 /* Set U/V data if using plane formats */
893 if ((sis_format == IMGFMT_YV12) || (sis_format == IMGFMT_I420)) {
894
895 uint32_t PSU, PSV;
896
897 PSU = (sis_frames[frame] + sis_Uoff) >> sis_shift_value;
898 PSV = (sis_frames[frame] + sis_Voff) >> sis_shift_value;
899
900 /* set U/V start address */
901 setvideoreg(Index_VI_U_Buf_Start_Low, (uint8_t) PSU);
902 setvideoreg(Index_VI_U_Buf_Start_Middle, (uint8_t) (PSU >> 8));
903 setvideoreg(Index_VI_U_Buf_Start_High, (uint8_t) (PSU >> 16));
904
905 setvideoreg(Index_VI_V_Buf_Start_Low, (uint8_t) PSV);
906 setvideoreg(Index_VI_V_Buf_Start_Middle, (uint8_t) (PSV >> 8));
907 setvideoreg(Index_VI_V_Buf_Start_High, (uint8_t) (PSV >> 16));
908
909 /* 310/325 series overflow bits */
910 if (sis_vga_engine == SIS_315_VGA) {
911 setvideoreg(Index_VI_U_Buf_Start_Over,
912 ((uint8_t) (PSU >> 24) & 0x01));
913 setvideoreg(Index_VI_V_Buf_Start_Over,
914 ((uint8_t) (PSV >> 24) & 0x01));
915 }
916 }
917
918 if (sis_vga_engine == SIS_315_VGA) {
919 /* Trigger register copy for 310 series */
920 setvideoreg(Index_VI_Control_Misc3, 1 << index);
921 }
922
923 /* Lock the address registers */
924 setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x20);
925
926 return 0;
927 }
928
929 int vixGetGrKeys(vidix_grkey_t * grkey)
930 {
931 memcpy(grkey, &sis_grkey, sizeof(vidix_grkey_t));
932 return 0;
933 }
934
935 int vixSetGrKeys(const vidix_grkey_t * grkey)
936 {
937 memcpy(&sis_grkey, grkey, sizeof(vidix_grkey_t));
938 set_colorkey();
939 return 0;
940 }
941
942 int vixPlaybackGetEq(vidix_video_eq_t * eq)
943 {
944 memcpy(eq, &sis_equal, sizeof(vidix_video_eq_t));
945 return 0;
946 }
947
948 int vixPlaybackSetEq(const vidix_video_eq_t * eq)
949 {
950 int br, sat, cr, hue;
951 if (eq->cap & VEQ_CAP_BRIGHTNESS)
952 sis_equal.brightness = eq->brightness;
953 if (eq->cap & VEQ_CAP_CONTRAST)
954 sis_equal.contrast = eq->contrast;
955 if (eq->cap & VEQ_CAP_SATURATION)
956 sis_equal.saturation = eq->saturation;
957 if (eq->cap & VEQ_CAP_HUE)
958 sis_equal.hue = eq->hue;
959 if (eq->cap & VEQ_CAP_RGB_INTENSITY) {
960 sis_equal.red_intensity = eq->red_intensity;
961 sis_equal.green_intensity = eq->green_intensity;
962 sis_equal.blue_intensity = eq->blue_intensity;
963 }
964 sis_equal.flags = eq->flags;
965
966 cr = (sis_equal.contrast + 1000) * 7 / 2000;
967 if (cr < 0)
968 cr = 0;
969 if (cr > 7)
970 cr = 7;
971
972 br = sis_equal.brightness * 127 / 1000;
973 if (br < -128)
974 br = -128;
975 if (br > 127)
976 br = 127;
977
978 sat = (sis_equal.saturation * 7) / 1000;
979 if (sat < -7)
980 sat = -7;
981 if (sat > 7)
982 sat = 7;
983
984 hue = sis_equal.hue * 7 / 1000;
985 if (hue < -8)
986 hue = -8;
987 if (hue > 7)
988 hue = 7;
989
990 set_brightness(br);
991 set_contrast(cr);
992 if (sis_vga_engine == SIS_315_VGA) {
993 set_saturation(sat);
994 set_hue(hue);
995 }
996
997 return 0;
998 }
999
1000 static void set_overlay(SISOverlayPtr pOverlay, int index)
1001 {
1002 uint16_t pitch = 0;
1003 uint8_t h_over = 0, v_over = 0;
1004 uint16_t top, bottom, left, right;
1005 uint16_t screenX = sis_screen_width;
1006 uint16_t screenY = sis_screen_height;
1007 uint8_t data;
1008 uint32_t watchdog;
1009
1010 top = pOverlay->dstBox.y1;
1011 bottom = pOverlay->dstBox.y2;
1012 if (bottom > screenY) {
1013 bottom = screenY;
1014 }
1015
1016 left = pOverlay->dstBox.x1;
1017 right = pOverlay->dstBox.x2;
1018 if (right > screenX) {
1019 right = screenX;
1020 }
1021
1022 /* JCP: these aren't really tested... */
1023 /* TW: DoubleScan modes require Y coordinates * 2 */
1024 if (sis_vmode & VMODE_DOUBLESCAN) {
1025 top <<= 1;
1026 bottom <<= 1;
1027 }
1028 /* TW: Interlace modes require Y coordinates / 2 */
1029 if (sis_vmode & VMODE_INTERLACED) {
1030 top >>= 1;
1031 bottom >>= 1;
1032 }
1033
1034 h_over = (((left >> 8) & 0x0f) | ((right >> 4) & 0xf0));
1035 v_over = (((top >> 8) & 0x0f) | ((bottom >> 4) & 0xf0));
1036
1037 pitch = pOverlay->pitch >> sis_shift_value;
1038
1039 /* set line buffer size */
1040 setvideoreg(Index_VI_Line_Buffer_Size, pOverlay->lineBufSize);
1041
1042 /* set color key mode */
1043 setvideoregmask(Index_VI_Key_Overlay_OP, pOverlay->keyOP, 0x0F);
1044
1045 /* TW: We don't have to wait for vertical retrace in all cases */
1046 /* JCP: be safe for now. */
1047 if (1 /*pPriv->mustwait */ ) {
1048 watchdog = WATCHDOG_DELAY;
1049 while (pOverlay->VBlankActiveFunc() && --watchdog);
1050 watchdog = WATCHDOG_DELAY;
1051 while ((!pOverlay->VBlankActiveFunc()) && --watchdog);
1052 if (!watchdog && sis_verbose > 0) {
1053 printf("[SiS]: timed out waiting for vertical retrace\n");
1054 }
1055 }
1056
1057 /* Unlock address registers */
1058 data = getvideoreg(Index_VI_Control_Misc1);
1059 setvideoreg(Index_VI_Control_Misc1, data | 0x20);
1060 /* TEST: Is this required? */
1061 setvideoreg(Index_VI_Control_Misc1, data | 0x20);
1062 /* TEST end */
1063
1064 /* TEST: Is this required? */
1065 if (sis_vga_engine == SIS_315_VGA)
1066 setvideoreg(Index_VI_Control_Misc3, 0x00);
1067 /* TEST end */
1068
1069 /* Set Y buf pitch */
1070 setvideoreg(Index_VI_Disp_Y_Buf_Pitch_Low, (uint8_t) (pitch));
1071 setvideoregmask(Index_VI_Disp_Y_UV_Buf_Pitch_Middle,
1072 (uint8_t) (pitch >> 8), 0x0f);
1073
1074 /* Set Y start address */
1075 setvideoreg(Index_VI_Disp_Y_Buf_Start_Low, (uint8_t) (pOverlay->PSY));
1076 setvideoreg(Index_VI_Disp_Y_Buf_Start_Middle,
1077 (uint8_t) ((pOverlay->PSY) >> 8));
1078 setvideoreg(Index_VI_Disp_Y_Buf_Start_High,
1079 (uint8_t) ((pOverlay->PSY) >> 16));
1080
1081 /* set 310/325 series overflow bits for Y plane */
1082 if (sis_vga_engine == SIS_315_VGA) {
1083 setvideoreg(Index_VI_Disp_Y_Buf_Pitch_High,
1084 (uint8_t) (pitch >> 12));
1085 setvideoreg(Index_VI_Y_Buf_Start_Over,
1086 ((uint8_t) ((pOverlay->PSY) >> 24) & 0x01));
1087 }
1088
1089 /* Set U/V data if using plane formats */
1090 if ((pOverlay->pixelFormat == IMGFMT_YV12) ||
1091 (pOverlay->pixelFormat == IMGFMT_I420)) {
1092
1093 uint32_t PSU, PSV;
1094
1095 PSU = pOverlay->PSU;
1096 PSV = pOverlay->PSV;
1097
1098 /* Set U/V pitch */
1099 setvideoreg(Index_VI_Disp_UV_Buf_Pitch_Low,
1100 (uint8_t) (pitch >> 1));
1101 setvideoregmask(Index_VI_Disp_Y_UV_Buf_Pitch_Middle,
1102 (uint8_t) (pitch >> 5), 0xf0);
1103
1104 /* set U/V start address */
1105 setvideoreg(Index_VI_U_Buf_Start_Low, (uint8_t) PSU);
1106 setvideoreg(Index_VI_U_Buf_Start_Middle, (uint8_t) (PSU >> 8));
1107 setvideoreg(Index_VI_U_Buf_Start_High, (uint8_t) (PSU >> 16));
1108
1109 setvideoreg(Index_VI_V_Buf_Start_Low, (uint8_t) PSV);
1110 setvideoreg(Index_VI_V_Buf_Start_Middle, (uint8_t) (PSV >> 8));
1111 setvideoreg(Index_VI_V_Buf_Start_High, (uint8_t) (PSV >> 16));
1112
1113 /* 310/325 series overflow bits */
1114 if (sis_vga_engine == SIS_315_VGA) {
1115 setvideoreg(Index_VI_Disp_UV_Buf_Pitch_High,
1116 (uint8_t) (pitch >> 13));
1117 setvideoreg(Index_VI_U_Buf_Start_Over,
1118 ((uint8_t) (PSU >> 24) & 0x01));
1119 setvideoreg(Index_VI_V_Buf_Start_Over,
1120 ((uint8_t) (PSV >> 24) & 0x01));
1121 }
1122 }
1123
1124 if (sis_vga_engine == SIS_315_VGA) {
1125 /* Trigger register copy for 310 series */
1126 setvideoreg(Index_VI_Control_Misc3, 1 << index);
1127 }
1128
1129 /* set scale factor */
1130 setvideoreg(Index_VI_Hor_Post_Up_Scale_Low,
1131 (uint8_t) (pOverlay->HUSF));
1132 setvideoreg(Index_VI_Hor_Post_Up_Scale_High,
1133 (uint8_t) ((pOverlay->HUSF) >> 8));
1134 setvideoreg(Index_VI_Ver_Up_Scale_Low, (uint8_t) (pOverlay->VUSF));
1135 setvideoreg(Index_VI_Ver_Up_Scale_High,
1136 (uint8_t) ((pOverlay->VUSF) >> 8));
1137
1138 setvideoregmask(Index_VI_Scale_Control, (pOverlay->IntBit << 3)
1139 | (pOverlay->wHPre), 0x7f);
1140
1141 /* set destination window position */
1142 setvideoreg(Index_VI_Win_Hor_Disp_Start_Low, (uint8_t) left);
1143 setvideoreg(Index_VI_Win_Hor_Disp_End_Low, (uint8_t) right);
1144 setvideoreg(Index_VI_Win_Hor_Over, (uint8_t) h_over);
1145
1146 setvideoreg(Index_VI_Win_Ver_Disp_Start_Low, (uint8_t) top);
1147 setvideoreg(Index_VI_Win_Ver_Disp_End_Low, (uint8_t) bottom);
1148 setvideoreg(Index_VI_Win_Ver_Over, (uint8_t) v_over);
1149
1150 setvideoregmask(Index_VI_Control_Misc1, pOverlay->bobEnable, 0x1a);
1151
1152 /* Lock the address registers */
1153 setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x20);
1154 }
1155
1156
1157 /* TW: Overlay MUST NOT be switched off while beam is over it */
1158 static void close_overlay()
1159 {
1160 uint32_t watchdog;
1161
1162 if ((sis_displaymode == DISPMODE_SINGLE2) ||
1163 (sis_displaymode == DISPMODE_MIRROR)) {
1164 if (sis_has_two_overlays) {
1165 setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x01);
1166 watchdog = WATCHDOG_DELAY;
1167 while (vblank_active_CRT2() && --watchdog);
1168 watchdog = WATCHDOG_DELAY;
1169 while ((!vblank_active_CRT2()) && --watchdog);
1170 setvideoregmask(Index_VI_Control_Misc0, 0x00, 0x02);
1171 watchdog = WATCHDOG_DELAY;
1172 while (vblank_active_CRT2() && --watchdog);
1173 watchdog = WATCHDOG_DELAY;
1174 while ((!vblank_active_CRT2()) && --watchdog);
1175 } else if (sis_displaymode == DISPMODE_SINGLE2) {
1176 setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x01);
1177 watchdog = WATCHDOG_DELAY;
1178 while (vblank_active_CRT1() && --watchdog);
1179 watchdog = WATCHDOG_DELAY;
1180 while ((!vblank_active_CRT1()) && --watchdog);
1181 setvideoregmask(Index_VI_Control_Misc0, 0x00, 0x02);
1182 watchdog = WATCHDOG_DELAY;
1183 while (vblank_active_CRT1() && --watchdog);
1184 watchdog = WATCHDOG_DELAY;
1185 while ((!vblank_active_CRT1()) && --watchdog);
1186 }
1187 }
1188 if ((sis_displaymode == DISPMODE_SINGLE1) ||
1189 (sis_displaymode == DISPMODE_MIRROR)) {
1190 setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x01);
1191 watchdog = WATCHDOG_DELAY;
1192 while (vblank_active_CRT1() && --watchdog);
1193 watchdog = WATCHDOG_DELAY;
1194 while ((!vblank_active_CRT1()) && --watchdog);
1195 setvideoregmask(Index_VI_Control_Misc0, 0x00, 0x02);
1196 watchdog = WATCHDOG_DELAY;
1197 while (vblank_active_CRT1() && --watchdog);
1198 watchdog = WATCHDOG_DELAY;
1199 while ((!vblank_active_CRT1()) && --watchdog);
1200 }
1201 }
1202
1203
1204 static void
1205 calc_scale_factor(SISOverlayPtr pOverlay, int index, int iscrt2)
1206 {
1207 uint32_t i = 0, mult = 0;
1208 int flag = 0;
1209
1210 int dstW = pOverlay->dstBox.x2 - pOverlay->dstBox.x1;
1211 int dstH = pOverlay->dstBox.y2 - pOverlay->dstBox.y1;
1212 int srcW = pOverlay->srcW;
1213 int srcH = pOverlay->srcH;
1214 /* uint16_t LCDheight = pSiS->LCDheight; */
1215 int srcPitch = pOverlay->origPitch;
1216 int origdstH = dstH;
1217
1218 /* get rid of warnings for now */
1219 index = index;
1220 iscrt2 = iscrt2;
1221
1222 #if 0 /* JCP: don't bother with this for now. */
1223 /* TW: Stretch image due to idiotic LCD "auto"-scaling on LVDS (and 630+301B) */
1224 if (pSiS->VBFlags & CRT2_LCD) {
1225 if (sis_bridge_is_slave) {
1226 if (pSiS->VBFlags & VB_LVDS) {
1227 dstH = (dstH * LCDheight) / pOverlay->SCREENheight;
1228 } else if ((sis_vga_engine == SIS_300_VGA) &&
1229 (pSiS->
1230 VBFlags & (VB_301B | VB_302B | VB_301LV |
1231 VB_302LV))) {
1232 dstH = (dstH * LCDheight) / pOverlay->SCREENheight;
1233 }
1234 } else if (iscrt2) {
1235 if (pSiS->VBFlags & VB_LVDS) {
1236 dstH = (dstH * LCDheight) / pOverlay->SCREENheight;
1237 if (sis_displaymode == DISPMODE_MIRROR)
1238 flag = 1;
1239 } else if ((sis_vga_engine == SIS_300_VGA) &&
1240 (pSiS->
1241 VBFlags & (VB_301B | VB_302B | VB_301LV |
1242 VB_302LV))) {
1243 dstH = (dstH * LCDheight) / pOverlay->SCREENheight;
1244 if (sis_displaymode == DISPMODE_MIRROR)
1245 flag = 1;
1246 }
1247 }
1248 }
1249 #endif
1250
1251 /* TW: For double scan modes, we need to double the height
1252 * (Perhaps we also need to scale LVDS, but I'm not sure.)
1253 * On 310/325 series, we need to double the width as well.
1254 * Interlace mode vice versa.
1255 */
1256 if (sis_vmode & VMODE_DOUBLESCAN) {
1257 dstH = origdstH << 1;
1258 flag = 0;
1259 if (sis_vga_engine == SIS_315_VGA) {
1260 dstW <<= 1;
1261 }
1262 }
1263 if (sis_vmode & VMODE_INTERLACED) {
1264 dstH = origdstH >> 1;
1265 flag = 0;
1266 }
1267
1268 if (dstW < OVERLAY_MIN_WIDTH)
1269 dstW = OVERLAY_MIN_WIDTH;
1270 if (dstW == srcW) {
1271 pOverlay->HUSF = 0x00;
1272 pOverlay->IntBit = 0x05;
1273 pOverlay->wHPre = 0;
1274 } else if (dstW > srcW) {
1275 dstW += 2;
1276 pOverlay->HUSF = (srcW << 16) / dstW;
1277 pOverlay->IntBit = 0x04;
1278 pOverlay->wHPre = 0;
1279 } else {
1280 int tmpW = dstW;
1281
1282 /* TW: It seems, the hardware can't scale below factor .125 (=1/8) if the
1283 pitch isn't a multiple of 256.
1284 TODO: Test this on the 310/325 series!
1285 */
1286 if ((srcPitch % 256) || (srcPitch < 256)) {
1287 if (((dstW * 1000) / srcW) < 125)
1288 dstW = tmpW = ((srcW * 125) / 1000) + 1;
1289 }
1290
1291 i = 0;
1292 pOverlay->IntBit = 0x01;
1293 while (srcW >= tmpW) {
1294 tmpW <<= 1;
1295 i++;
1296 }
1297 pOverlay->wHPre = (uint8_t) (i - 1);
1298 dstW <<= (i - 1);
1299 if ((srcW % dstW))
1300 pOverlay->HUSF = ((srcW - dstW) << 16) / dstW;
1301 else
1302 pOverlay->HUSF = 0x00;
1303 }
1304
1305 if (dstH < OVERLAY_MIN_HEIGHT)
1306 dstH = OVERLAY_MIN_HEIGHT;
1307 if (dstH == srcH) {
1308 pOverlay->VUSF = 0x00;
1309 pOverlay->IntBit |= 0x0A;
1310 } else if (dstH > srcH) {
1311 dstH += 0x02;
1312 pOverlay->VUSF = (srcH << 16) / dstH;
1313 pOverlay->IntBit |= 0x08;
1314 } else {
1315 uint32_t realI;
1316
1317 i = realI = srcH / dstH;
1318 pOverlay->IntBit |= 0x02;
1319
1320 if (i < 2) {
1321 pOverlay->VUSF = ((srcH - dstH) << 16) / dstH;
1322 /* TW: Needed for LCD-scaling modes */
1323 if ((flag) && (mult = (srcH / origdstH)) >= 2)
1324 pOverlay->pitch /= mult;
1325 } else {
1326 #if 0
1327 if (((pOverlay->bobEnable & 0x08) == 0x00) &&
1328 (((srcPitch * i) >> 2) > 0xFFF)) {
1329 pOverlay->bobEnable |= 0x08;
1330 srcPitch >>= 1;
1331 }
1332 #endif
1333 if (((srcPitch * i) >> 2) > 0xFFF) {
1334 i = (0xFFF * 2 / srcPitch);
1335 pOverlay->VUSF = 0xFFFF;
1336 } else {
1337 dstH = i * dstH;
1338 if (srcH % dstH)
1339 pOverlay->VUSF = ((srcH - dstH) << 16) / dstH;
1340 else
1341 pOverlay->VUSF = 0x00;
1342 }
1343 /* set video frame buffer offset */
1344 pOverlay->pitch = (uint16_t) (srcPitch * i);
1345 }
1346 }
1347 }
1348
1349 static void set_line_buf_size(SISOverlayPtr pOverlay)
1350 {
1351 uint8_t preHIDF;
1352 uint32_t i;
1353 uint32_t line = pOverlay->srcW;
1354
1355 if ((pOverlay->pixelFormat == IMGFMT_YV12) ||
1356 (pOverlay->pixelFormat == IMGFMT_I420)) {
1357 preHIDF = pOverlay->wHPre & 0x07;
1358 switch (preHIDF) {
1359 case 3:
1360 if ((line & 0xffffff00) == line)
1361 i = (line >> 8);
1362 else
1363 i = (line >> 8) + 1;
1364 pOverlay->lineBufSize = (uint8_t) (i * 32 - 1);
1365 break;
1366 case 4:
1367 if ((line & 0xfffffe00) == line)
1368 i = (line >> 9);
1369 else
1370 i = (line >> 9) + 1;
1371 pOverlay->lineBufSize = (uint8_t) (i * 64 - 1);
1372 break;
1373 case 5:
1374 if ((line & 0xfffffc00) == line)
1375 i = (line >> 10);
1376 else
1377 i = (line >> 10) + 1;
1378 pOverlay->lineBufSize = (uint8_t) (i * 128 - 1);
1379 break;
1380 case 6:
1381 if ((line & 0xfffff800) == line)
1382 i = (line >> 11);
1383 else
1384 i = (line >> 11) + 1;
1385 pOverlay->lineBufSize = (uint8_t) (i * 256 - 1);
1386 break;
1387 default:
1388 if ((line & 0xffffff80) == line)
1389 i = (line >> 7);
1390 else
1391 i = (line >> 7) + 1;
1392 pOverlay->lineBufSize = (uint8_t) (i * 16 - 1);
1393 break;
1394 }
1395 } else { /* YUV2, UYVY */
1396 if ((line & 0xffffff8) == line)
1397 i = (line >> 3);
1398 else
1399 i = (line >> 3) + 1;
1400 pOverlay->lineBufSize = (uint8_t) (i - 1);
1401 }
1402 }
1403
1404 static void merge_line_buf(int enable)
1405 {
1406 if (enable) {
1407 switch (sis_displaymode) {
1408 case DISPMODE_SINGLE1:
1409 if (sis_has_two_overlays) {
1410 /* dual line merge */
1411 setvideoregmask(Index_VI_Control_Misc2, 0x10, 0x11);
1412 setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04);
1413 } else {
1414 setvideoregmask(Index_VI_Control_Misc2, 0x10, 0x11);
1415 setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04);
1416 }
1417 break;
1418 case DISPMODE_SINGLE2:
1419 if (sis_has_two_overlays) {
1420 /* line merge */
1421 setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x11);
1422 setvideoregmask(Index_VI_Control_Misc1, 0x04, 0x04);
1423 } else {
1424 setvideoregmask(Index_VI_Control_Misc2, 0x10, 0x11);
1425 setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04);
1426 }
1427 break;
1428 case DISPMODE_MIRROR:
1429 default:
1430 /* line merge */
1431 setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x11);
1432 setvideoregmask(Index_VI_Control_Misc1, 0x04, 0x04);
1433 if (sis_has_two_overlays) {
1434 /* line merge */
1435 setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x11);
1436 setvideoregmask(Index_VI_Control_Misc1, 0x04, 0x04);
1437 }
1438 break;
1439 }
1440 } else {
1441 switch (sis_displaymode) {
1442 case DISPMODE_SINGLE1:
1443 setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x11);
1444 setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04);
1445 break;
1446 case DISPMODE_SINGLE2:
1447 if (sis_has_two_overlays) {
1448 setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x11);
1449 setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04);
1450 } else {
1451 setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x11);
1452 setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04);
1453 }
1454 break;
1455 case DISPMODE_MIRROR:
1456 default:
1457 setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x11);
1458 setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04);
1459 if (sis_has_two_overlays) {
1460 setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x11);
1461 setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04);
1462 }
1463 break;
1464 }
1465 }
1466 }
1467
1468
1469 static void set_format(SISOverlayPtr pOverlay)
1470 {
1471 uint8_t fmt;
1472
1473 switch (pOverlay->pixelFormat) {
1474 case IMGFMT_YV12:
1475 case IMGFMT_I420:
1476 fmt = 0x0c;
1477 break;
1478 case IMGFMT_YUY2:
1479 fmt = 0x28;
1480 break;
1481 case IMGFMT_UYVY:
1482 fmt = 0x08;
1483 break;
1484 case IMGFMT_RGB15: /* D[5:4] : 00 RGB555, 01 RGB 565 */
1485 fmt = 0x00;
1486 break;
1487 case IMGFMT_RGB16:
1488 fmt = 0x10;
1489 break;
1490 default:
1491 fmt = 0x00;
1492 break;
1493 }
1494 setvideoregmask(Index_VI_Control_Misc0, fmt, 0x7c);
1495 }
1496
1497 static void set_colorkey()
1498 {
1499 uint8_t r, g, b;
1500
1501 b = (uint8_t) sis_grkey.ckey.blue;
1502 g = (uint8_t) sis_grkey.ckey.green;
1503 r = (uint8_t) sis_grkey.ckey.red;
1504
1505 /* set color key mode */
1506 setvideoregmask(Index_VI_Key_Overlay_OP,
1507 sis_grkey.ckey.op == CKEY_TRUE ?
1508 VI_ROP_DestKey : VI_ROP_Always, 0x0F);
1509
1510 /* set colorkey values */
1511 setvideoreg(Index_VI_Overlay_ColorKey_Blue_Min, (uint8_t) b);
1512 setvideoreg(Index_VI_Overlay_ColorKey_Green_Min, (uint8_t) g);
1513 setvideoreg(Index_VI_Overlay_ColorKey_Red_Min, (uint8_t) r);
1514
1515 setvideoreg(Index_VI_Overlay_ColorKey_Blue_Max, (uint8_t) b);
1516 setvideoreg(Index_VI_Overlay_ColorKey_Green_Max, (uint8_t) g);
1517 setvideoreg(Index_VI_Overlay_ColorKey_Red_Max, (uint8_t) r);
1518 }
1519
1520 static void set_brightness(uint8_t brightness)
1521 {
1522 setvideoreg(Index_VI_Brightness, brightness);
1523 }
1524
1525 static void set_contrast(uint8_t contrast)
1526 {
1527 setvideoregmask(Index_VI_Contrast_Enh_Ctrl, contrast, 0x07);
1528 }
1529
1530 /* Next 3 functions are 310/325 series only */
1531
1532 static void set_saturation(char saturation)
1533 {
1534 uint8_t temp = 0;
1535
1536 if (saturation < 0) {
1537 temp |= 0x88;
1538 saturation = -saturation;
1539 }
1540 temp |= (saturation & 0x07);
1541 temp |= ((saturation & 0x07) << 4);
1542
1543 setvideoreg(Index_VI_Saturation, temp);
1544 }
1545
1546 static void set_hue(uint8_t hue)
1547 {
1548 setvideoreg(Index_VI_Hue, (hue & 0x08) ? (hue ^ 0x07) : hue);
1549 }
1550
1551 #if 0
1552 /* JCP: not used (I don't think it's correct anyway) */
1553 static void set_alpha(uint8_t alpha)
1554 {
1555 uint8_t data;
1556
1557 data = getvideoreg(Index_VI_Key_Overlay_OP);
1558 data &= 0x0F;
1559 setvideoreg(Index_VI_Key_Overlay_OP, data | (alpha << 4));
1560 }
1561 #endif