Mercurial > mplayer.hg

comparison vidix/drivers/nvidia_vid.c @ 10977:3da6b1de1c33

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
make it work in textmode again && support for nv03 with 4MB RAM
author faust3
date Thu, 02 Oct 2003 10:46:33 +0000
parents de7036f31e5a
children 0c633f49231d
comparison
equal deleted inserted replaced
10976:da5149d755c3 10977:3da6b1de1c33
407 VID_WR32 (info->chip.PVIDEO, 0x240, key); 407 VID_WR32 (info->chip.PVIDEO, 0x240, key);
408 break; 408 break;
409 } 409 }
410 } 410 }
411 411
412 static void nv_waitidle(struct rivatv_info *info ){
413 while (info->chip.PGRAPH[0x1C0] & 1) {}
414 }
415
412 416
413 /* Start overlay video. */ 417 /* Start overlay video. */
414 void rivatv_overlay_start (struct rivatv_info *info,int bufno){ 418 void rivatv_overlay_start (struct rivatv_info *info,int bufno){
415 uint32_t base, size, offset, xscale, yscale, pan,bpp, pitch0=0; 419 uint32_t base, size, offset, xscale, yscale, pan,bpp, pitch0=0;
416 int x, y; 420 int x=8, y=8;
417 int lwidth=info->d_width, lheight=info->d_height; 421 int lwidth=info->d_width, lheight=info->d_height;
418 int bps; 422 int bps;
419 423
424 size = info->buffer_size;
425 base = info->picture_offset;
426 offset = bufno*size;
420 /*update depth & dimensions here because it may change with vo vesa or vo fbdev*/ 427 /*update depth & dimensions here because it may change with vo vesa or vo fbdev*/
421 info->chip.lock (&info->chip, 0); 428 info->chip.lock (&info->chip, 0);
422 do { 429 nv_waitidle(info);
423 switch (info->chip.arch) { 430 switch (info->chip.arch) {
424 case NV_ARCH_03: 431 case NV_ARCH_03:
425 pitch0 = info->chip.PGRAPH[0x00000650/4]; 432 pitch0 = info->chip.PGRAPH[0x00000650/4];
426 break; 433 break;
427 case NV_ARCH_04: 434 case NV_ARCH_04:
428 case NV_ARCH_10: 435 case NV_ARCH_10:
429 case NV_ARCH_20: 436 case NV_ARCH_20:
430 case NV_ARCH_30: 437 case NV_ARCH_30:
431 pitch0 = info->chip.PGRAPH[0x00000670/4]; 438 pitch0 = info->chip.PGRAPH[0x00000670/4];
432 break; 439 break;
433 } 440 }
434 if (pitch0 == 0)
435 printf("[nvidia_vid]: pitch0 = 0!!! Rereading\n");
436 } while (pitch0 == 0);
437 VID_WR08(info->chip.PCIO, 0x03D4, 0x28); 441 VID_WR08(info->chip.PCIO, 0x03D4, 0x28);
438 bpp = VID_RD08(info->chip.PCIO,0x03D5); 442 bpp = VID_RD08(info->chip.PCIO,0x03D5);
439 if(bpp==3)bpp = 4; //fixme do nvidia cards support 24bpp? 443 if(bpp==3)bpp = 4; //fixme do nvidia cards support 24bpp?
440 if((bpp == 2) && (info->chip.PVIDEO[0x00000600/4] & 0x00001000) == 0x0)info->depth=15; //0x00101100 for BGR16 444 if((bpp == 2) && (info->chip.PVIDEO[0x00000600/4] & 0x00001000) == 0x0)info->depth=15; //0x00101100 for BGR16
441 else info->depth = bpp*8; 445 else info->depth = bpp*8;
442 if(!bpp)printf("[nvidia_vid] error invalid bpp\n"); 446 if(!bpp)printf("[nvidia_vid] error invalid bpp\n");
443 else 447 else
444 { 448 {
445 // printf("[nvidia_vid] video mode: %ux%u@%u\n",info->screen_x = pitch0/bpp,(pitch0/bpp*3)/4,info->depth); 449 // printf("[nvidia_vid] video mode: %ux%u@%u\n",info->screen_x = pitch0/bpp,(pitch0/bpp*3)/4,info->depth);
446 info->screen_x = pitch0/bpp; 450 info->screen_x = pitch0/bpp;
451 bps = info->screen_x * ((info->depth+1)/8);
452 /* get pan offset of the physical screen */
453 pan = rivatv_overlay_pan (info);
454 /* adjust window position depending on the pan offset */
455 x = info->wx - (pan % bps) * 8 / info->depth;
456 y = info->wy - (pan / bps);
457 /* adjust negative output window variables */
458 if (x < 0) {
459 lwidth = info->d_width + x;
460 offset += (-x * info->width / info->d_width) << 1;
461 // offset += (-window->x * port->vld_width / window->width) << 1;
462 x = 0;
463 }
464 if (y < 0) {
465 lheight = info->d_height + y;
466 offset += (-y * info->height / info->d_height * info->width) << 1;
467 // offset += (-window->y * port->vld_height / window->height * port->org_width) << 1;
468 y = 0;
469 }
470
471
472
473
474
475
447 } 476 }
448 477
449 bps = info->screen_x * ((info->depth+1)/8); 478
450 /* get pan offset of the physical screen */ 479
451 pan = rivatv_overlay_pan (info);
452 size = info->buffer_size;
453 /* adjust window position depending on the pan offset */
454 x = info->wx - (pan % bps) * 8 / info->depth;
455 y = info->wy - (pan / bps);
456
457 base = info->picture_offset;
458 offset = bufno*size;
459
460 /* adjust negative output window variables */
461 if (x < 0) {
462 lwidth = info->d_width + x;
463 offset += (-x * info->width / info->d_width) << 1;
464 // offset += (-window->x * port->vld_width / window->width) << 1;
465 x = 0;
466 }
467 if (y < 0) {
468 lheight = info->d_height + y;
469 offset += (-y * info->height / info->d_height * info->width) << 1;
470 // offset += (-window->y * port->vld_height / window->height * port->org_width) << 1;
471 y = 0;
472 }
473 480
474 switch (info->chip.arch) { 481 switch (info->chip.arch) {
475 case NV_ARCH_10: 482 case NV_ARCH_10:
476 case NV_ARCH_20: 483 case NV_ARCH_20:
477 case NV_ARCH_30: 484 case NV_ARCH_30:
597 } 604 }
598 /*set colorkey*/ 605 /*set colorkey*/
599 rivatv_overlay_colorkey(info,info->vidixcolorkey); 606 rivatv_overlay_colorkey(info,info->vidixcolorkey);
600 607
601 } 608 }
609
610
611
612
613
602 614
603 615
604 static rivatv_info* info; 616 static rivatv_info* info;
605 617
606 618
646 case NV_ARCH_03: 658 case NV_ARCH_03:
647 { 659 {
648 /* This maps framebuffer @6MB, thus 2MB are left for video. */ 660 /* This maps framebuffer @6MB, thus 2MB are left for video. */
649 info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize); 661 info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize);
650 /* This may trash your screen for resolutions greater than 1024x768, sorry. */ 662 /* This may trash your screen for resolutions greater than 1024x768, sorry. */
651 info->picture_offset = 2*1024*768*4 ; 663 info->picture_offset = 1024*768* 4 * ((info->chip.fbsize > 4194304)?2:1);
652 info->picture_base = (uint32_t) info->video_base + info->picture_offset; 664 info->picture_base = (uint32_t) info->video_base + info->picture_offset;
653 info->chip.PRAMIN = (uint32_t *) (info->video_base + 0x00C00000); 665 info->chip.PRAMIN = (uint32_t *) (info->video_base + 0x00C00000);
654 break; 666 break;
655 } 667 }
656 case NV_ARCH_04: 668 case NV_ARCH_04:
675 687
676 /*get some info about the screen dimension and depth*/ 688 /*get some info about the screen dimension and depth*/
677 { 689 {
678 uint32_t bpp=0,pitch0=0; 690 uint32_t bpp=0,pitch0=0;
679 info->chip.lock (&info->chip, 0); 691 info->chip.lock (&info->chip, 0);
680 do { 692 nv_waitidle(info);
681 switch (info->chip.arch) { 693 switch (info->chip.arch) {
682 case NV_ARCH_03: 694 case NV_ARCH_03:
683 pitch0 = info->chip.PGRAPH[0x00000650/4]; 695 pitch0 = info->chip.PGRAPH[0x00000650/4];
684 break; 696 break;
685 case NV_ARCH_04: 697 case NV_ARCH_04:
686 case NV_ARCH_10: 698 case NV_ARCH_10:
687 case NV_ARCH_20: 699 case NV_ARCH_20:
688 case NV_ARCH_30: 700 case NV_ARCH_30:
689 pitch0 = info->chip.PGRAPH[0x00000670/4]; 701 pitch0 = info->chip.PGRAPH[0x00000670/4];
690 break; 702 break;
691 } 703 }
692 if (pitch0 == 0)
693 printf("[nvidia_vid]: pitch0 = 0!!! Rereading\n");
694 } while (pitch0 == 0);
695 VID_WR08(info->chip.PCIO, 0x03D4, 0x28); 704 VID_WR08(info->chip.PCIO, 0x03D4, 0x28);
696 bpp = VID_RD08(info->chip.PCIO,0x03D5); 705 bpp = VID_RD08(info->chip.PCIO,0x03D5);
697 if(bpp==3)bpp = 4; //fixme do nvidia cards support 24bpp? 706 if(bpp==3)bpp = 4; //fixme do nvidia cards support 24bpp?
698 if((bpp == 2) && (info->chip.PVIDEO[0x00000600/4] & 0x00001000) == 0x0)info->depth=15; //0x00101100 for BGR16 707 if((bpp == 2) && (info->chip.PVIDEO[0x00000600/4] & 0x00001000) == 0x0)info->depth=15; //0x00101100 for BGR16
699 else info->depth = bpp*8; 708 else info->depth = bpp*8;