comparison cpuinfo.c @ 23344:57692910afd4

New tags introduced for AMD K10 and Intel Penryn

23343:a982544e5c08

      CPUID_FEATURE_DEF(8, "tm2", "Thermal Monitor 2"),
      CPUID_FEATURE_DEF(9, "ssse3", "Supplemental SSE3"),
      CPUID_FEATURE_DEF(10, "cid", "L1 Context ID"),
      CPUID_FEATURE_DEF(13, "cx16", "CMPXCHG16B Available"),
      CPUID_FEATURE_DEF(14, "xtpr", "xTPR Disable"), 
      CPUID_FEATURE_DEF(18, "dca", "Direct Cache Access"), 
      { -1 }
    };
    static struct {
      int bit;
      char *desc;

      CPUID_FEATURE_DEF(11, "syscall", "SYSCALL and SYSRET"),
      CPUID_FEATURE_DEF(19, "mp", "MP Capable"),
      CPUID_FEATURE_DEF(20, "nx", "No-Execute Page Protection"),
      CPUID_FEATURE_DEF(22, "mmxext", "MMX Technology (AMD Extensions)"),
      CPUID_FEATURE_DEF(25, "fxsr_opt", "Fast FXSAVE/FXRSTOR"),
      CPUID_FEATURE_DEF(27, "rdtscp", "RDTSCP Instruction"),
      CPUID_FEATURE_DEF(29, "lm", "Long Mode Capable"),
      CPUID_FEATURE_DEF(30, "3dnowext", "3DNow! Extensions"),
      CPUID_FEATURE_DEF(31, "3dnow", "3DNow!"),
      { -1 }

      char *desc;
    } cap_amd2[] = {
      CPUID_FEATURE_DEF(0, "lahf_lm", "LAHF/SAHF Supported in 64-bit Mode"),
      CPUID_FEATURE_DEF(1, "cmp_legacy", "Chip Multi-Core"),
      CPUID_FEATURE_DEF(2, "svm", "Secure Virtual Machine"),
      CPUID_FEATURE_DEF(4, "cr8legacy", "CR8 Available in Legacy Mode"),
      { -1 }
    };
    unsigned int family, model, stepping;

    regs = cpuid(1);

23344:57692910afd4

      CPUID_FEATURE_DEF(8, "tm2", "Thermal Monitor 2"),
      CPUID_FEATURE_DEF(9, "ssse3", "Supplemental SSE3"),
      CPUID_FEATURE_DEF(10, "cid", "L1 Context ID"),
      CPUID_FEATURE_DEF(13, "cx16", "CMPXCHG16B Available"),
      CPUID_FEATURE_DEF(14, "xtpr", "xTPR Disable"), 
      CPUID_FEATURE_DEF(15, "pdcm", "Perf/Debug Capability MSR"), 
      CPUID_FEATURE_DEF(18, "dca", "Direct Cache Access"), 
      CPUID_FEATURE_DEF(19, "sse41", "SSE4.1 Extensions"), 
      CPUID_FEATURE_DEF(20, "sse42", "SSE4.2 Extensions"), 
      CPUID_FEATURE_DEF(23, "popcnt", "Pop Count Instruction"), 
      { -1 }
    };
    static struct {
      int bit;
      char *desc;

      CPUID_FEATURE_DEF(11, "syscall", "SYSCALL and SYSRET"),
      CPUID_FEATURE_DEF(19, "mp", "MP Capable"),
      CPUID_FEATURE_DEF(20, "nx", "No-Execute Page Protection"),
      CPUID_FEATURE_DEF(22, "mmxext", "MMX Technology (AMD Extensions)"),
      CPUID_FEATURE_DEF(25, "fxsr_opt", "Fast FXSAVE/FXRSTOR"),
      CPUID_FEATURE_DEF(26, "pdpe1gb", "PDP Entry for 1GiB Page"),
      CPUID_FEATURE_DEF(27, "rdtscp", "RDTSCP Instruction"),
      CPUID_FEATURE_DEF(29, "lm", "Long Mode Capable"),
      CPUID_FEATURE_DEF(30, "3dnowext", "3DNow! Extensions"),
      CPUID_FEATURE_DEF(31, "3dnow", "3DNow!"),
      { -1 }

      char *desc;
    } cap_amd2[] = {
      CPUID_FEATURE_DEF(0, "lahf_lm", "LAHF/SAHF Supported in 64-bit Mode"),
      CPUID_FEATURE_DEF(1, "cmp_legacy", "Chip Multi-Core"),
      CPUID_FEATURE_DEF(2, "svm", "Secure Virtual Machine"),
      CPUID_FEATURE_DEF(3, "extapic", "Extended APIC Space"),
      CPUID_FEATURE_DEF(4, "cr8legacy", "CR8 Available in Legacy Mode"),
      CPUID_FEATURE_DEF(5, "abm", "Advanced Bit Manipulation"),
      CPUID_FEATURE_DEF(6, "sse4a", "SSE4A Extensions"),
      CPUID_FEATURE_DEF(7, "misalignsse", "Misaligned SSE Mode"),
      CPUID_FEATURE_DEF(8, "3dnowprefetch", "3DNow! Prefetch/PrefetchW"),
      CPUID_FEATURE_DEF(9, "osvw", "OS Visible Workaround"),
      CPUID_FEATURE_DEF(10, "ibs", ""),
      { -1 }
    };
    unsigned int family, model, stepping;

    regs = cpuid(1);