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comparison drivers/radeon/radeon_vid.c @ 3122:60c2510ab0ae

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Fixed bug of ram_size detection
author nick
date Sun, 25 Nov 2001 18:05:36 +0000
parents 7eba9b3ac5a7
children 3c5ad8d5ac00
comparison
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3121:fa5242f95187 3122:60c2510ab0ae
19 /* 19 /*
20 It's entirely possible this major conflicts with something else 20 It's entirely possible this major conflicts with something else
21 mknod /dev/radeon_vid c 178 0 21 mknod /dev/radeon_vid c 178 0
22 */ 22 */
23 23
24 /* TESTED and WORKING formats: YUY2 */
25
24 /* 26 /*
25 TODO: 27 TODO:
26 OV0_COLOUR_CNTL brightness saturation 28 Highest priority: fbvid.h compatibility and UYVY test
27 SCALER_GAMMA_SEL_BRIGHT gamma correction ??? 29 High priority: YV12, I420, IYUV support
28 OV0_GRAPHICS_KEY_CLR color key 30 Middle priority:
29 OV0_AUTO_FLIP_CNTL 31 OV0_COLOUR_CNTL brightness saturation
30 OV0_FILTER_CNTL 32 SCALER_GAMMA_SEL_BRIGHT gamma correction ???
31 OV0_VIDEO_KEY_CLR 33 OV0_GRAPHICS_KEY_CLR color key
32 OV0_KEY_CNTL 34 OV0_AUTO_FLIP_CNTL
33 35 OV0_FILTER_CNTL
34 BPP should be known 36 OV0_VIDEO_KEY_CLR
37 OV0_KEY_CNTL
38 Low priority: RGB/BGR 2-32, YVU9, IF09, CLPL, IYU1, IYU2, UYNV, CYUV
39 YUNV, YVYU, Y41P, Y211, Y41T, Y42T, V422, V655, CLJR
40 ^^^^
41 YUVP, UYVP, Mpeg PES (mpeg-1,2) support
35 */ 42 */
36 43
37 #include <linux/config.h> 44 #include <linux/config.h>
38 #include <linux/version.h> 45 #include <linux/version.h>
39 #include <linux/module.h> 46 #include <linux/module.h>
88 uint32_t vid_buf_pitch0_value; 95 uint32_t vid_buf_pitch0_value;
89 uint32_t vid_buf_pitch1_value; 96 uint32_t vid_buf_pitch1_value;
90 uint32_t p1_x_start_end; 97 uint32_t p1_x_start_end;
91 uint32_t p2_x_start_end; 98 uint32_t p2_x_start_end;
92 uint32_t p3_x_start_end; 99 uint32_t p3_x_start_end;
100 uint32_t base_addr;
93 uint32_t vid_buf0_base_adrs; 101 uint32_t vid_buf0_base_adrs;
94 /* These ones are for auto flip: maybe in the future */ 102 /* These ones are for auto flip: maybe in the future */
95 uint32_t vid_buf1_base_adrs; 103 uint32_t vid_buf1_base_adrs;
96 uint32_t vid_buf2_base_adrs; 104 uint32_t vid_buf2_base_adrs;
97 uint32_t vid_buf3_base_adrs; 105 uint32_t vid_buf3_base_adrs;
133 { OV0_VID_BUF_PITCH0_VALUE, 0 }, 141 { OV0_VID_BUF_PITCH0_VALUE, 0 },
134 { OV0_VID_BUF_PITCH1_VALUE, 0 }, 142 { OV0_VID_BUF_PITCH1_VALUE, 0 },
135 { OV0_P1_X_START_END, 0 }, 143 { OV0_P1_X_START_END, 0 },
136 { OV0_P2_X_START_END, 0 }, 144 { OV0_P2_X_START_END, 0 },
137 { OV0_P3_X_START_END, 0 }, 145 { OV0_P3_X_START_END, 0 },
146 { OV0_BASE_ADDR, 0 },
138 { OV0_VID_BUF0_BASE_ADRS, 0 }, 147 { OV0_VID_BUF0_BASE_ADRS, 0 },
139 { OV0_VID_BUF1_BASE_ADRS, 0 }, 148 { OV0_VID_BUF1_BASE_ADRS, 0 },
140 { OV0_VID_BUF2_BASE_ADRS, 0 }, 149 { OV0_VID_BUF2_BASE_ADRS, 0 },
141 { OV0_VID_BUF3_BASE_ADRS, 0 }, 150 { OV0_VID_BUF3_BASE_ADRS, 0 },
142 { OV0_VID_BUF4_BASE_ADRS, 0 }, 151 { OV0_VID_BUF4_BASE_ADRS, 0 },
172 #define RTRACE printk 181 #define RTRACE printk
173 #else 182 #else
174 #define RTRACE(...) ((void)0) 183 #define RTRACE(...) ((void)0)
175 #endif 184 #endif
176 185
186 static char *fourcc_format_name(int format)
187 {
188 switch(format)
189 {
190 case IMGFMT_RGB8: return("RGB 8-bit");
191 case IMGFMT_RGB15: return("RGB 15-bit");
192 case IMGFMT_RGB16: return("RGB 16-bit");
193 case IMGFMT_RGB24: return("RGB 24-bit");
194 case IMGFMT_RGB32: return("RGB 32-bit");
195 case IMGFMT_BGR8: return("BGR 8-bit");
196 case IMGFMT_BGR15: return("BGR 15-bit");
197 case IMGFMT_BGR16: return("BGR 16-bit");
198 case IMGFMT_BGR24: return("BGR 24-bit");
199 case IMGFMT_BGR32: return("BGR 32-bit");
200 case IMGFMT_YVU9: return("Planar YVU9");
201 case IMGFMT_IF09: return("Planar IF09");
202 case IMGFMT_YV12: return("Planar YV12");
203 case IMGFMT_I420: return("Planar I420");
204 case IMGFMT_IYUV: return("Planar IYUV");
205 case IMGFMT_CLPL: return("Planar CLPL");
206 case IMGFMT_IYU1: return("Packed IYU1");
207 case IMGFMT_IYU2: return("Packed IYU2");
208 case IMGFMT_UYVY: return("Packed UYVY");
209 case IMGFMT_UYNV: return("Packed UYNV");
210 case IMGFMT_cyuv: return("Packed CYUV");
211 case IMGFMT_YUY2: return("Packed YUY2");
212 case IMGFMT_YUNV: return("Packed YUNV");
213 case IMGFMT_YVYU: return("Packed YVYU");
214 case IMGFMT_Y41P: return("Packed Y41P");
215 case IMGFMT_Y211: return("Packed Y211");
216 case IMGFMT_Y41T: return("Packed Y41T");
217 case IMGFMT_Y42T: return("Packed Y42T");
218 case IMGFMT_V422: return("Packed V422");
219 case IMGFMT_V655: return("Packed V655");
220 case IMGFMT_CLJR: return("Packed CLJR");
221 case IMGFMT_YUVP: return("Packed YUVP");
222 case IMGFMT_UYVP: return("Packed UYVP");
223 /* case IMGFMT_MPEGPES: return("Mpeg PES");*/
224 }
225 return("Unknown");
226 }
227
177 228
178 /* 229 /*
179 * IO macros 230 * IO macros
180 */ 231 */
181 232
245 OUTREG(OV0_VID_BUF_PITCH0_VALUE, besr.vid_buf_pitch0_value); 296 OUTREG(OV0_VID_BUF_PITCH0_VALUE, besr.vid_buf_pitch0_value);
246 OUTREG(OV0_VID_BUF_PITCH1_VALUE, besr.vid_buf_pitch1_value); 297 OUTREG(OV0_VID_BUF_PITCH1_VALUE, besr.vid_buf_pitch1_value);
247 OUTREG(OV0_P1_X_START_END, besr.p1_x_start_end); 298 OUTREG(OV0_P1_X_START_END, besr.p1_x_start_end);
248 OUTREG(OV0_P2_X_START_END, besr.p2_x_start_end); 299 OUTREG(OV0_P2_X_START_END, besr.p2_x_start_end);
249 OUTREG(OV0_P3_X_START_END, besr.p3_x_start_end); 300 OUTREG(OV0_P3_X_START_END, besr.p3_x_start_end);
301 #if 0
302 OUTREG(OV0_BASE_ADDR, besr.base_addr);
303 #endif
250 OUTREG(OV0_VID_BUF0_BASE_ADRS, besr.vid_buf0_base_adrs); 304 OUTREG(OV0_VID_BUF0_BASE_ADRS, besr.vid_buf0_base_adrs);
251 OUTREG(OV0_VID_BUF1_BASE_ADRS, besr.vid_buf1_base_adrs); 305 OUTREG(OV0_VID_BUF1_BASE_ADRS, besr.vid_buf1_base_adrs);
252 OUTREG(OV0_VID_BUF2_BASE_ADRS, besr.vid_buf2_base_adrs); 306 OUTREG(OV0_VID_BUF2_BASE_ADRS, besr.vid_buf2_base_adrs);
253 OUTREG(OV0_VID_BUF3_BASE_ADRS, besr.vid_buf3_base_adrs); 307 OUTREG(OV0_VID_BUF3_BASE_ADRS, besr.vid_buf3_base_adrs);
254 OUTREG(OV0_VID_BUF4_BASE_ADRS, besr.vid_buf4_base_adrs); 308 OUTREG(OV0_VID_BUF4_BASE_ADRS, besr.vid_buf4_base_adrs);
273 case IMGFMT_RGB32: 327 case IMGFMT_RGB32:
274 case IMGFMT_BGR32: bes_flags |= SCALER_SOURCE_32BPP; break; 328 case IMGFMT_BGR32: bes_flags |= SCALER_SOURCE_32BPP; break;
275 329
276 case IMGFMT_UYVY: bes_flags |= SCALER_SOURCE_YVYU422; break; 330 case IMGFMT_UYVY: bes_flags |= SCALER_SOURCE_YVYU422; break;
277 case IMGFMT_YVU9: bes_flags |= SCALER_SOURCE_YUV9; break; 331 case IMGFMT_YVU9: bes_flags |= SCALER_SOURCE_YUV9; break;
278 case IMGFMT_IYUV: bes_flags |= SCALER_SOURCE_YUV12; break; 332
279 333 case IMGFMT_IYUV:
280 case IMGFMT_I420: 334 case IMGFMT_I420:
281 case IMGFMT_YV12: bes_flags |= SCALER_SOURCE_YUV12 | 335 case IMGFMT_YV12: bes_flags |= SCALER_SOURCE_YUV12;
282 SCALER_PIX_EXPAND |
283 SCALER_Y2R_TEMP;
284 break; 336 break;
285 case IMGFMT_YUY2: 337 case IMGFMT_YUY2:
286 default: bes_flags |= SCALER_SOURCE_VYUY422; break; 338 default: bes_flags |= SCALER_SOURCE_VYUY422; break;
287 } 339 }
288 RTRACE("radeon_vid: OV0: SCALER=%x\n",bes_flags); 340 RTRACE("radeon_vid: OV0: SCALER=%x\n",bes_flags);
358 default: 410 default:
359 printk( "radeon_vid: Unsupported pixel format: 0x%X\n",config->format); 411 printk( "radeon_vid: Unsupported pixel format: 0x%X\n",config->format);
360 return -1; 412 return -1;
361 } 413 }
362 is_420 = 0; 414 is_420 = 0;
363 if(config->format == IMGFMT_YV12 || config->format == IMGFMT_I420) is_420 = 1; 415 if(config->format == IMGFMT_YV12 ||
416 config->format == IMGFMT_I420 ||
417 config->format == IMGFMT_IYUV) is_420 = 1;
364 switch(config->format) 418 switch(config->format)
365 { 419 {
366 default: 420 default:
367 case IMGFMT_YVU9: 421 case IMGFMT_YVU9:
368 case IMGFMT_IYUV: 422 case IMGFMT_IYUV:
390 step_by++; 444 step_by++;
391 h_inc >>= 1; 445 h_inc >>= 1;
392 } 446 }
393 447
394 /* keep everything in 16.16 */ 448 /* keep everything in 16.16 */
395 449 besr.base_addr = radeon_overlay_off;
396 if(is_420) 450 if(is_420)
397 { 451 {
398 uint32_t dstPitch,d1line,d2line,d3line; 452 uint32_t dstPitch,d1line,d2line,d3line;
399 dstPitch = ((src_w + 15) & ~15); /* of luma */ 453 dstPitch = ((src_w + 15) & ~15); /* of luma */
400 d1line = top * dstPitch; 454 d1line = top*dstPitch;
401 d2line = (src_h * dstPitch) + ((top >> 1) * (dstPitch >> 1)); 455 d2line = src_h*dstPitch+(d1line>>1);
402 d3line = d2line + ((src_h >> 1) * (dstPitch >> 1)); 456 d3line = d2line+((src_h*dstPitch)>>2);
403 besr.vid_buf0_base_adrs = ((radeon_overlay_off + d1line) & VIF_BUF0_BASE_ADRS_MASK) | VIF_BUF0_PITCH_SEL; 457 besr.vid_buf0_base_adrs=((radeon_overlay_off+d1line)&VIF_BUF0_BASE_ADRS_MASK)|VIF_BUF0_PITCH_SEL;
404 besr.vid_buf1_base_adrs = ((radeon_overlay_off + d2line) & VIF_BUF1_BASE_ADRS_MASK) | VIF_BUF1_PITCH_SEL; 458 besr.vid_buf1_base_adrs=((radeon_overlay_off+d2line)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF0_PITCH_SEL;
405 besr.vid_buf2_base_adrs = ((radeon_overlay_off + d3line) & VIF_BUF2_BASE_ADRS_MASK) | VIF_BUF2_PITCH_SEL; 459 besr.vid_buf2_base_adrs=((radeon_overlay_off+d3line)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF0_PITCH_SEL;
406 } 460 }
407 else 461 else
408 { 462 {
409 besr.vid_buf0_base_adrs = radeon_overlay_off; 463 besr.vid_buf0_base_adrs = radeon_overlay_off;
410 besr.vid_buf0_base_adrs += ((left & ~7) << 1)&0xfffffff0; 464 besr.vid_buf0_base_adrs += ((left & ~7) << 1)&0xfffffff0;
422 tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc << 2); 476 tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc << 2);
423 besr.p23_h_accum_init = ((tmp << 4) & 0x000f8000) | 477 besr.p23_h_accum_init = ((tmp << 4) & 0x000f8000) |
424 ((tmp << 12) & 0x70000000); 478 ((tmp << 12) & 0x70000000);
425 479
426 tmp = (top & 0x0000ffff) + 0x00018000; 480 tmp = (top & 0x0000ffff) + 0x00018000;
427 besr.p1_v_accum_init = ((tmp << 4) & 0x03ff8000) | 0x00000001; 481 besr.p1_v_accum_init = ((tmp << 4) & OV0_P1_V_ACCUM_INIT_MASK)
428 482 |(OV0_P1_MAX_LN_IN_PER_LN_OUT & 1);
429 483
430 tmp = ((top >> 1) & 0x0000ffff) + 0x00018000; 484 tmp = ((top >> 1) & 0x0000ffff) + 0x00018000;
431 besr.p23_v_accum_init = is_420 ? ((tmp << 4) & 0x01ff8000) | 0x00000001 : 0; 485 besr.p23_v_accum_init = is_420 ? ((tmp << 4) & OV0_P23_V_ACCUM_INIT_MASK)
486 |(OV0_P23_MAX_LN_IN_PER_LN_OUT & 1) : 0;
432 487
433 leftUV = (left >> 17) & 15; 488 leftUV = (left >> 17) & 15;
434 left = (left >> 16) & 15; 489 left = (left >> 16) & 15;
435 besr.h_inc = h_inc | ((h_inc >> 1) << 16); 490 besr.h_inc = h_inc | ((h_inc >> 1) << 16);
436 besr.step_by = step_by | (step_by << 8); 491 besr.step_by = step_by | (step_by << 8);
437 besr.y_x_start = (config->x_org+8) | (config->y_org << 16); 492 besr.y_x_start = (config->x_org+8) | (config->y_org << 16);
438 besr.y_x_end = (config->x_org + config->dest_width+8) | ((config->y_org + config->dest_height) << 16); 493 besr.y_x_end = (config->x_org + config->dest_width+8) | ((config->y_org + config->dest_height) << 16);
439 besr.p1_blank_lines_at_top = P1_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); 494 besr.p1_blank_lines_at_top = P1_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16);
440 src_h = (src_h + 1) >> 1; 495 if(is_420)
441 besr.p23_blank_lines_at_top = is_420 ? P23_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16):0; 496 {
497 src_h = (src_h + 1) >> 1;
498 besr.p23_blank_lines_at_top = P23_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16);
499 }
500 else besr.p23_blank_lines_at_top = 0;
442 besr.vid_buf_pitch0_value = pitch; 501 besr.vid_buf_pitch0_value = pitch;
443 besr.vid_buf_pitch1_value = is_420 ? pitch>>1 : pitch; 502 besr.vid_buf_pitch1_value = is_420 ? pitch>>1 : pitch;
444 RTRACE("radeon_vid: BES: v_inc=%x h_inc=%x step_by=%x\n",besr.v_inc,besr.h_inc,besr.step_by); 503 RTRACE("radeon_vid: BES: v_inc=%x h_inc=%x step_by=%x\n",besr.v_inc,besr.h_inc,besr.step_by);
445 RTRACE("radeon_vid: BES: vid_buf0_basey=%x\n",besr.vid_buf0_base_adrs); 504 RTRACE("radeon_vid: BES: vid_buf0_basey=%x\n",besr.vid_buf0_base_adrs);
446 RTRACE("radeon_vid: BES: y_x_start=%x y_x_end=%x blank_at_top=%x pitch0_value=%x\n" 505 RTRACE("radeon_vid: BES: y_x_start=%x y_x_end=%x blank_at_top=%x pitch0_value=%x\n"
447 ,besr.y_x_start,besr.y_x_end,besr.p1_blank_lines_at_top,besr.vid_buf_pitch0_value); 506 ,besr.y_x_start,besr.y_x_end,besr.p1_blank_lines_at_top,besr.vid_buf_pitch0_value);
448 besr.p1_x_start_end = (src_w+left-1)|(left<<16); 507 besr.p1_x_start_end = (src_w+left-1)|(left<<16);
449 src_w>>=1; 508 if(is_420)
450 besr.p2_x_start_end = (src_w+left-1)|(leftUV<<16); 509 {
451 besr.p3_x_start_end = besr.p2_x_start_end; 510 if(config->format == IMGFMT_YV12)
511 {
512 besr.p3_x_start_end = ((src_w/2)+left-1)|((leftUV)<<16);
513 besr.p2_x_start_end = (src_w+left-1)|((src_w/2+leftUV)<<16);
514 }
515 else
516 {
517 besr.p2_x_start_end = ((src_w/2)+left-1)|((leftUV)<<16);
518 besr.p3_x_start_end = (src_w+left-1)|((src_w/2+leftUV)<<16);
519 }
520 }
521 else
522 {
523 src_w>>=1;
524 besr.p2_x_start_end = (src_w+left-1)|(leftUV<<16);
525 besr.p3_x_start_end = besr.p2_x_start_end;
526 }
452 return 0; 527 return 0;
453 } 528 }
454 529
455 static void radeon_vid_frame_sel(int frame) 530 static void radeon_vid_frame_sel(int frame)
456 { 531 {
521 if (copy_to_user((mga_vid_config_t *) arg, &radeon_config, sizeof(mga_vid_config_t))) 596 if (copy_to_user((mga_vid_config_t *) arg, &radeon_config, sizeof(mga_vid_config_t)))
522 { 597 {
523 printk( "radeon_vid: failed copy to userspace\n"); 598 printk( "radeon_vid: failed copy to userspace\n");
524 return -EFAULT; 599 return -EFAULT;
525 } 600 }
601 printk("radeon_vid: configuring for '%s' fourcc\n",fourcc_format_name(radeon_config.format));
526 return radeon_vid_init_video(&radeon_config); 602 return radeon_vid_init_video(&radeon_config);
527 break; 603 break;
528 604
529 case MGA_VID_ON: 605 case MGA_VID_ON:
530 RTRACE( "radeon_vid: Video ON (ioctl)\n"); 606 RTRACE( "radeon_vid: Video ON (ioctl)\n");
580 size_t i; 656 size_t i;
581 657
582 for(i=0;i<sizeof(ati_card_ids)/sizeof(struct ati_card_id_s);i++) 658 for(i=0;i<sizeof(ati_card_ids)/sizeof(struct ati_card_id_s);i++)
583 if((dev=pci_find_device(PCI_VENDOR_ID_ATI, ati_card_ids[i].id, NULL))) 659 if((dev=pci_find_device(PCI_VENDOR_ID_ATI, ati_card_ids[i].id, NULL)))
584 break; 660 break;
585 if(dev) 661 if(!dev)
586 printk("radeon_vid: Found %s\n",ati_card_ids[i].name);
587 else
588 { 662 {
589 printk("radeon_vid: No supported cards found\n"); 663 printk("radeon_vid: No supported cards found\n");
590 return FALSE; 664 return FALSE;
591 } 665 }
592 666
594 radeon_mem_base = dev->resource[0].start; 668 radeon_mem_base = dev->resource[0].start;
595 669
596 RTRACE( "radeon_vid: MMIO at 0x%p\n", radeon_mmio_base); 670 RTRACE( "radeon_vid: MMIO at 0x%p\n", radeon_mmio_base);
597 RTRACE( "radeon_vid: Frame Buffer at 0x%08x\n", radeon_mem_base); 671 RTRACE( "radeon_vid: Frame Buffer at 0x%08x\n", radeon_mem_base);
598 672
599 radeon_ram_size = pci_resource_len(dev, 0)/0x100000; 673 /* video memory size */
674 radeon_ram_size = INREG(CONFIG_MEMSIZE);
675
676 /* mem size is bits [28:0], mask off the rest */
677 radeon_ram_size &= CONFIG_MEMSIZE_MASK;
678 radeon_ram_size /= 0x100000;
679 printk("radeon_vid: Found %s (%uMb memory)\n",ati_card_ids[i].name,radeon_ram_size);
600 680
601 return TRUE; 681 return TRUE;
602 } 682 }
603 683
604 684