Mercurial > mplayer.hg
comparison drivers/radeon/radeon.h @ 1911:89313cfc8fec
Initial import of Ani Joshi's radeonfb-0.0.9
author | nick |
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date | Tue, 18 Sep 2001 16:12:34 +0000 |
parents | |
children | 33afcb62fc64 |
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1910:06fa415119bc | 1911:89313cfc8fec |
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1 #ifndef _RADEON_H | |
2 #define _RADEON_H | |
3 | |
4 | |
5 /* radeon PCI ids */ | |
6 #define PCI_DEVICE_ID_RADEON_QD 0x5144 | |
7 #define PCI_DEVICE_ID_RADEON_QE 0x5145 | |
8 #define PCI_DEVICE_ID_RADEON_QF 0x5146 | |
9 #define PCI_DEVICE_ID_RADEON_QG 0x5147 | |
10 | |
11 #define RADEON_REGSIZE 0x4000 | |
12 | |
13 | |
14 #define MM_INDEX 0x0000 | |
15 #define MM_DATA 0x0004 | |
16 #define BUS_CNTL 0x0030 | |
17 #define HI_STAT 0x004C | |
18 #define BUS_CNTL1 0x0034 | |
19 #define I2C_CNTL_1 0x0094 | |
20 #define CONFIG_CNTL 0x00E0 | |
21 #define CONFIG_MEMSIZE 0x00F8 | |
22 #define CONFIG_APER_0_BASE 0x0100 | |
23 #define CONFIG_APER_1_BASE 0x0104 | |
24 #define CONFIG_APER_SIZE 0x0108 | |
25 #define CONFIG_REG_1_BASE 0x010C | |
26 #define CONFIG_REG_APER_SIZE 0x0110 | |
27 #define PAD_AGPINPUT_DELAY 0x0164 | |
28 #define PAD_CTLR_STRENGTH 0x0168 | |
29 #define PAD_CTLR_UPDATE 0x016C | |
30 #define AGP_CNTL 0x0174 | |
31 #define BM_STATUS 0x0160 | |
32 #define CAP0_TRIG_CNTL 0x0950 | |
33 #define VIPH_CONTROL 0x0C40 | |
34 #define VENDOR_ID 0x0F00 | |
35 #define DEVICE_ID 0x0F02 | |
36 #define COMMAND 0x0F04 | |
37 #define STATUS 0x0F06 | |
38 #define REVISION_ID 0x0F08 | |
39 #define REGPROG_INF 0x0F09 | |
40 #define SUB_CLASS 0x0F0A | |
41 #define BASE_CODE 0x0F0B | |
42 #define CACHE_LINE 0x0F0C | |
43 #define LATENCY 0x0F0D | |
44 #define HEADER 0x0F0E | |
45 #define BIST 0x0F0F | |
46 #define REG_MEM_BASE 0x0F10 | |
47 #define REG_IO_BASE 0x0F14 | |
48 #define REG_REG_BASE 0x0F18 | |
49 #define ADAPTER_ID 0x0F2C | |
50 #define BIOS_ROM 0x0F30 | |
51 #define CAPABILITIES_PTR 0x0F34 | |
52 #define INTERRUPT_LINE 0x0F3C | |
53 #define INTERRUPT_PIN 0x0F3D | |
54 #define MIN_GRANT 0x0F3E | |
55 #define MAX_LATENCY 0x0F3F | |
56 #define ADAPTER_ID_W 0x0F4C | |
57 #define PMI_CAP_ID 0x0F50 | |
58 #define PMI_NXT_CAP_PTR 0x0F51 | |
59 #define PMI_PMC_REG 0x0F52 | |
60 #define PM_STATUS 0x0F54 | |
61 #define PMI_DATA 0x0F57 | |
62 #define AGP_CAP_ID 0x0F58 | |
63 #define AGP_STATUS 0x0F5C | |
64 #define AGP_COMMAND 0x0F60 | |
65 #define AIC_CTRL 0x01D0 | |
66 #define AIC_STAT 0x01D4 | |
67 #define AIC_PT_BASE 0x01D8 | |
68 #define AIC_LO_ADDR 0x01DC | |
69 #define AIC_HI_ADDR 0x01E0 | |
70 #define AIC_TLB_ADDR 0x01E4 | |
71 #define AIC_TLB_DATA 0x01E8 | |
72 #define DAC_CNTL 0x0058 | |
73 #define CRTC_GEN_CNTL 0x0050 | |
74 #define MEM_CNTL 0x0140 | |
75 #define EXT_MEM_CNTL 0x0144 | |
76 #define MC_AGP_LOCATION 0x014C | |
77 #define MEM_IO_CNTL_A0 0x0178 | |
78 #define MEM_INIT_LATENCY_TIMER 0x0154 | |
79 #define MEM_SDRAM_MODE_REG 0x0158 | |
80 #define AGP_BASE 0x0170 | |
81 #define MEM_IO_CNTL_A1 0x017C | |
82 #define MEM_IO_CNTL_B0 0x0180 | |
83 #define MEM_IO_CNTL_B1 0x0184 | |
84 #define MC_DEBUG 0x0188 | |
85 #define MC_STATUS 0x0150 | |
86 #define MEM_IO_OE_CNTL 0x018C | |
87 #define MC_FB_LOCATION 0x0148 | |
88 #define HOST_PATH_CNTL 0x0130 | |
89 #define MEM_VGA_WP_SEL 0x0038 | |
90 #define MEM_VGA_RP_SEL 0x003C | |
91 #define HDP_DEBUG 0x0138 | |
92 #define SW_SEMAPHORE 0x013C | |
93 #define SURFACE_CNTL 0x0B00 | |
94 #define SURFACE0_LOWER_BOUND 0x0B04 | |
95 #define SURFACE1_LOWER_BOUND 0x0B14 | |
96 #define SURFACE2_LOWER_BOUND 0x0B24 | |
97 #define SURFACE3_LOWER_BOUND 0x0B34 | |
98 #define SURFACE4_LOWER_BOUND 0x0B44 | |
99 #define SURFACE5_LOWER_BOUND 0x0B54 | |
100 #define SURFACE6_LOWER_BOUND 0x0B64 | |
101 #define SURFACE7_LOWER_BOUND 0x0B74 | |
102 #define SURFACE0_UPPER_BOUND 0x0B08 | |
103 #define SURFACE1_UPPER_BOUND 0x0B18 | |
104 #define SURFACE2_UPPER_BOUND 0x0B28 | |
105 #define SURFACE3_UPPER_BOUND 0x0B38 | |
106 #define SURFACE4_UPPER_BOUND 0x0B48 | |
107 #define SURFACE5_UPPER_BOUND 0x0B58 | |
108 #define SURFACE6_UPPER_BOUND 0x0B68 | |
109 #define SURFACE7_UPPER_BOUND 0x0B78 | |
110 #define SURFACE0_INFO 0x0B0C | |
111 #define SURFACE1_INFO 0x0B1C | |
112 #define SURFACE2_INFO 0x0B2C | |
113 #define SURFACE3_INFO 0x0B3C | |
114 #define SURFACE4_INFO 0x0B4C | |
115 #define SURFACE5_INFO 0x0B5C | |
116 #define SURFACE6_INFO 0x0B6C | |
117 #define SURFACE7_INFO 0x0B7C | |
118 #define SURFACE_ACCESS_FLAGS 0x0BF8 | |
119 #define SURFACE_ACCESS_CLR 0x0BFC | |
120 #define GEN_INT_CNTL 0x0040 | |
121 #define GEN_INT_STATUS 0x0044 | |
122 #define CRTC_EXT_CNTL 0x0054 | |
123 #define RB3D_CNTL 0x1C3C | |
124 #define WAIT_UNTIL 0x1720 | |
125 #define ISYNC_CNTL 0x1724 | |
126 #define RBBM_GUICNTL 0x172C | |
127 #define RBBM_STATUS 0x0E40 | |
128 #define RBBM_STATUS_alt_1 0x1740 | |
129 #define RBBM_CNTL 0x00EC | |
130 #define RBBM_CNTL_alt_1 0x0E44 | |
131 #define RBBM_SOFT_RESET 0x00F0 | |
132 #define RBBM_SOFT_RESET_alt_1 0x0E48 | |
133 #define NQWAIT_UNTIL 0x0E50 | |
134 #define RBBM_DEBUG 0x0E6C | |
135 #define RBBM_CMDFIFO_ADDR 0x0E70 | |
136 #define RBBM_CMDFIFO_DATAL 0x0E74 | |
137 #define RBBM_CMDFIFO_DATAH 0x0E78 | |
138 #define RBBM_CMDFIFO_STAT 0x0E7C | |
139 #define CRTC_STATUS 0x005C | |
140 #define GPIO_VGA_DDC 0x0060 | |
141 #define GPIO_DVI_DDC 0x0064 | |
142 #define GPIO_MONID 0x0068 | |
143 #define PALETTE_INDEX 0x00B0 | |
144 #define PALETTE_DATA 0x00B4 | |
145 #define PALETTE_30_DATA 0x00B8 | |
146 #define CRTC_H_TOTAL_DISP 0x0200 | |
147 #define CRTC_H_SYNC_STRT_WID 0x0204 | |
148 #define CRTC_V_TOTAL_DISP 0x0208 | |
149 #define CRTC_V_SYNC_STRT_WID 0x020C | |
150 #define CRTC_VLINE_CRNT_VLINE 0x0210 | |
151 #define CRTC_CRNT_FRAME 0x0214 | |
152 #define CRTC_GUI_TRIG_VLINE 0x0218 | |
153 #define CRTC_DEBUG 0x021C | |
154 #define CRTC_OFFSET_RIGHT 0x0220 | |
155 #define CRTC_OFFSET 0x0224 | |
156 #define CRTC_OFFSET_CNTL 0x0228 | |
157 #define CRTC_PITCH 0x022C | |
158 #define OVR_CLR 0x0230 | |
159 #define OVR_WID_LEFT_RIGHT 0x0234 | |
160 #define OVR_WID_TOP_BOTTOM 0x0238 | |
161 #define DISPLAY_BASE_ADDR 0x023C | |
162 #define SNAPSHOT_VH_COUNTS 0x0240 | |
163 #define SNAPSHOT_F_COUNT 0x0244 | |
164 #define N_VIF_COUNT 0x0248 | |
165 #define SNAPSHOT_VIF_COUNT 0x024C | |
166 #define FP_CRTC_H_TOTAL_DISP 0x0250 | |
167 #define FP_CRTC_V_TOTAL_DISP 0x0254 | |
168 #define CRT_CRTC_H_SYNC_STRT_WID 0x0258 | |
169 #define CRT_CRTC_V_SYNC_STRT_WID 0x025C | |
170 #define CUR_OFFSET 0x0260 | |
171 #define CUR_HORZ_VERT_POSN 0x0264 | |
172 #define CUR_HORZ_VERT_OFF 0x0268 | |
173 #define CUR_CLR0 0x026C | |
174 #define CUR_CLR1 0x0270 | |
175 #define FP_HORZ_VERT_ACTIVE 0x0278 | |
176 #define CRTC_MORE_CNTL 0x027C | |
177 #define DAC_EXT_CNTL 0x0280 | |
178 #define FP_GEN_CNTL 0x0284 | |
179 #define FP_HORZ_STRETCH 0x028C | |
180 #define FP_VERT_STRETCH 0x0290 | |
181 #define FP_H_SYNC_STRT_WID 0x02C4 | |
182 #define FP_V_SYNC_STRT_WID 0x02C8 | |
183 #define AUX_WINDOW_HORZ_CNTL 0x02D8 | |
184 #define AUX_WINDOW_VERT_CNTL 0x02DC | |
185 #define DDA_CONFIG 0x02e0 | |
186 #define DDA_ON_OFF 0x02e4 | |
187 #define GRPH_BUFFER_CNTL 0x02F0 | |
188 #define VGA_BUFFER_CNTL 0x02F4 | |
189 #define OV0_Y_X_START 0x0400 | |
190 #define OV0_Y_X_END 0x0404 | |
191 #define OV0_PIPELINE_CNTL 0x0408 | |
192 #define OV0_REG_LOAD_CNTL 0x0410 | |
193 #define OV0_SCALE_CNTL 0x0420 | |
194 #define OV0_V_INC 0x0424 | |
195 #define OV0_P1_V_ACCUM_INIT 0x0428 | |
196 #define OV0_P23_V_ACCUM_INIT 0x042C | |
197 #define OV0_P1_BLANK_LINES_AT_TOP 0x0430 | |
198 #define OV0_P23_BLANK_LINES_AT_TOP 0x0434 | |
199 #define OV0_BASE_ADDR 0x043C | |
200 #define OV0_VID_BUF0_BASE_ADRS 0x0440 | |
201 #define OV0_VID_BUF1_BASE_ADRS 0x0444 | |
202 #define OV0_VID_BUF2_BASE_ADRS 0x0448 | |
203 #define OV0_VID_BUF3_BASE_ADRS 0x044C | |
204 #define OV0_VID_BUF4_BASE_ADRS 0x0450 | |
205 #define OV0_VID_BUF5_BASE_ADRS 0x0454 | |
206 #define OV0_VID_BUF_PITCH0_VALUE 0x0460 | |
207 #define OV0_VID_BUF_PITCH1_VALUE 0x0464 | |
208 #define OV0_AUTO_FLIP_CNTRL 0x0470 | |
209 #define OV0_DEINTERLACE_PATTERN 0x0474 | |
210 #define OV0_SUBMIT_HISTORY 0x0478 | |
211 #define OV0_H_INC 0x0480 | |
212 #define OV0_STEP_BY 0x0484 | |
213 #define OV0_P1_H_ACCUM_INIT 0x0488 | |
214 #define OV0_P23_H_ACCUM_INIT 0x048C | |
215 #define OV0_P1_X_START_END 0x0494 | |
216 #define OV0_P2_X_START_END 0x0498 | |
217 #define OV0_P3_X_START_END 0x049C | |
218 #define OV0_FILTER_CNTL 0x04A0 | |
219 #define OV0_FOUR_TAP_COEF_0 0x04B0 | |
220 #define OV0_FOUR_TAP_COEF_1 0x04B4 | |
221 #define OV0_FOUR_TAP_COEF_2 0x04B8 | |
222 #define OV0_FOUR_TAP_COEF_3 0x04BC | |
223 #define OV0_FOUR_TAP_COEF_4 0x04C0 | |
224 #define OV0_FLAG_CNTRL 0x04DC | |
225 #define OV0_SLICE_CNTL 0x04E0 | |
226 #define OV0_VID_KEY_CLR_LOW 0x04E4 | |
227 #define OV0_VID_KEY_CLR_HIGH 0x04E8 | |
228 #define OV0_GRPH_KEY_CLR_LOW 0x04EC | |
229 #define OV0_GRPH_KEY_CLR_HIGH 0x04F0 | |
230 #define OV0_KEY_CNTL 0x04F4 | |
231 #define OV0_TEST 0x04F8 | |
232 #define SUBPIC_CNTL 0x0540 | |
233 #define SUBPIC_DEFCOLCON 0x0544 | |
234 #define SUBPIC_Y_X_START 0x054C | |
235 #define SUBPIC_Y_X_END 0x0550 | |
236 #define SUBPIC_V_INC 0x0554 | |
237 #define SUBPIC_H_INC 0x0558 | |
238 #define SUBPIC_BUF0_OFFSET 0x055C | |
239 #define SUBPIC_BUF1_OFFSET 0x0560 | |
240 #define SUBPIC_LC0_OFFSET 0x0564 | |
241 #define SUBPIC_LC1_OFFSET 0x0568 | |
242 #define SUBPIC_PITCH 0x056C | |
243 #define SUBPIC_BTN_HLI_COLCON 0x0570 | |
244 #define SUBPIC_BTN_HLI_Y_X_START 0x0574 | |
245 #define SUBPIC_BTN_HLI_Y_X_END 0x0578 | |
246 #define SUBPIC_PALETTE_INDEX 0x057C | |
247 #define SUBPIC_PALETTE_DATA 0x0580 | |
248 #define SUBPIC_H_ACCUM_INIT 0x0584 | |
249 #define SUBPIC_V_ACCUM_INIT 0x0588 | |
250 #define DISP_MISC_CNTL 0x0D00 | |
251 #define DAC_MACRO_CNTL 0x0D04 | |
252 #define DISP_PWR_MAN 0x0D08 | |
253 #define DISP_TEST_DEBUG_CNTL 0x0D10 | |
254 #define DISP_HW_DEBUG 0x0D14 | |
255 #define DAC_CRC_SIG1 0x0D18 | |
256 #define DAC_CRC_SIG2 0x0D1C | |
257 #define OV0_LIN_TRANS_A 0x0D20 | |
258 #define OV0_LIN_TRANS_B 0x0D24 | |
259 #define OV0_LIN_TRANS_C 0x0D28 | |
260 #define OV0_LIN_TRANS_D 0x0D2C | |
261 #define OV0_LIN_TRANS_E 0x0D30 | |
262 #define OV0_LIN_TRANS_F 0x0D34 | |
263 #define OV0_GAMMA_0_F 0x0D40 | |
264 #define OV0_GAMMA_10_1F 0x0D44 | |
265 #define OV0_GAMMA_20_3F 0x0D48 | |
266 #define OV0_GAMMA_40_7F 0x0D4C | |
267 #define OV0_GAMMA_380_3BF 0x0D50 | |
268 #define OV0_GAMMA_3C0_3FF 0x0D54 | |
269 #define DISP_MERGE_CNTL 0x0D60 | |
270 #define DISP_OUTPUT_CNTL 0x0D64 | |
271 #define DISP_LIN_TRANS_GRPH_A 0x0D80 | |
272 #define DISP_LIN_TRANS_GRPH_B 0x0D84 | |
273 #define DISP_LIN_TRANS_GRPH_C 0x0D88 | |
274 #define DISP_LIN_TRANS_GRPH_D 0x0D8C | |
275 #define DISP_LIN_TRANS_GRPH_E 0x0D90 | |
276 #define DISP_LIN_TRANS_GRPH_F 0x0D94 | |
277 #define DISP_LIN_TRANS_VID_A 0x0D98 | |
278 #define DISP_LIN_TRANS_VID_B 0x0D9C | |
279 #define DISP_LIN_TRANS_VID_C 0x0DA0 | |
280 #define DISP_LIN_TRANS_VID_D 0x0DA4 | |
281 #define DISP_LIN_TRANS_VID_E 0x0DA8 | |
282 #define DISP_LIN_TRANS_VID_F 0x0DAC | |
283 #define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0 | |
284 #define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4 | |
285 #define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8 | |
286 #define RMX_HORZ_PHASE 0x0DBC | |
287 #define DAC_EMBEDDED_SYNC_CNTL 0x0DC0 | |
288 #define DAC_BROAD_PULSE 0x0DC4 | |
289 #define DAC_SKEW_CLKS 0x0DC8 | |
290 #define DAC_INCR 0x0DCC | |
291 #define DAC_NEG_SYNC_LEVEL 0x0DD0 | |
292 #define DAC_POS_SYNC_LEVEL 0x0DD4 | |
293 #define DAC_BLANK_LEVEL 0x0DD8 | |
294 #define CLOCK_CNTL_INDEX 0x0008 | |
295 #define CLOCK_CNTL_DATA 0x000C | |
296 #define CP_RB_CNTL 0x0704 | |
297 #define CP_RB_BASE 0x0700 | |
298 #define CP_RB_RPTR_ADDR 0x070C | |
299 #define CP_RB_RPTR 0x0710 | |
300 #define CP_RB_WPTR 0x0714 | |
301 #define CP_RB_WPTR_DELAY 0x0718 | |
302 #define CP_IB_BASE 0x0738 | |
303 #define CP_IB_BUFSZ 0x073C | |
304 #define SCRATCH_REG0 0x15E0 | |
305 #define GUI_SCRATCH_REG0 0x15E0 | |
306 #define SCRATCH_REG1 0x15E4 | |
307 #define GUI_SCRATCH_REG1 0x15E4 | |
308 #define SCRATCH_REG2 0x15E8 | |
309 #define GUI_SCRATCH_REG2 0x15E8 | |
310 #define SCRATCH_REG3 0x15EC | |
311 #define GUI_SCRATCH_REG3 0x15EC | |
312 #define SCRATCH_REG4 0x15F0 | |
313 #define GUI_SCRATCH_REG4 0x15F0 | |
314 #define SCRATCH_REG5 0x15F4 | |
315 #define GUI_SCRATCH_REG5 0x15F4 | |
316 #define SCRATCH_UMSK 0x0770 | |
317 #define SCRATCH_ADDR 0x0774 | |
318 #define DP_BRUSH_FRGD_CLR 0x147C | |
319 #define DP_BRUSH_BKGD_CLR 0x1478 | |
320 #define DST_LINE_START 0x1600 | |
321 #define DST_LINE_END 0x1604 | |
322 #define SRC_OFFSET 0x15AC | |
323 #define SRC_PITCH 0x15B0 | |
324 #define SRC_TILE 0x1704 | |
325 #define SRC_PITCH_OFFSET 0x1428 | |
326 #define SRC_X 0x1414 | |
327 #define SRC_Y 0x1418 | |
328 #define SRC_X_Y 0x1590 | |
329 #define SRC_Y_X 0x1434 | |
330 #define DST_Y_X 0x1438 | |
331 #define DST_WIDTH_HEIGHT 0x1598 | |
332 #define DST_HEIGHT_WIDTH 0x143c | |
333 #define SRC_CLUT_ADDRESS 0x1780 | |
334 #define SRC_CLUT_DATA 0x1784 | |
335 #define SRC_CLUT_DATA_RD 0x1788 | |
336 #define HOST_DATA0 0x17C0 | |
337 #define HOST_DATA1 0x17C4 | |
338 #define HOST_DATA2 0x17C8 | |
339 #define HOST_DATA3 0x17CC | |
340 #define HOST_DATA4 0x17D0 | |
341 #define HOST_DATA5 0x17D4 | |
342 #define HOST_DATA6 0x17D8 | |
343 #define HOST_DATA7 0x17DC | |
344 #define HOST_DATA_LAST 0x17E0 | |
345 #define DP_SRC_ENDIAN 0x15D4 | |
346 #define DP_SRC_FRGD_CLR 0x15D8 | |
347 #define DP_SRC_BKGD_CLR 0x15DC | |
348 #define SC_LEFT 0x1640 | |
349 #define SC_RIGHT 0x1644 | |
350 #define SC_TOP 0x1648 | |
351 #define SC_BOTTOM 0x164C | |
352 #define SRC_SC_RIGHT 0x1654 | |
353 #define SRC_SC_BOTTOM 0x165C | |
354 #define DP_CNTL 0x16C0 | |
355 #define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0 | |
356 #define DP_DATATYPE 0x16C4 | |
357 #define DP_MIX 0x16C8 | |
358 #define DP_WRITE_MSK 0x16CC | |
359 #define DP_XOP 0x17F8 | |
360 #define CLR_CMP_CLR_SRC 0x15C4 | |
361 #define CLR_CMP_CLR_DST 0x15C8 | |
362 #define CLR_CMP_CNTL 0x15C0 | |
363 #define CLR_CMP_MSK 0x15CC | |
364 #define DSTCACHE_MODE 0x1710 | |
365 #define DSTCACHE_CTLSTAT 0x1714 | |
366 #define DEFAULT_PITCH_OFFSET 0x16E0 | |
367 #define DEFAULT_SC_BOTTOM_RIGHT 0x16E8 | |
368 #define DP_GUI_MASTER_CNTL 0x146C | |
369 #define SC_TOP_LEFT 0x16EC | |
370 #define SC_BOTTOM_RIGHT 0x16F0 | |
371 #define SRC_SC_BOTTOM_RIGHT 0x16F4 | |
372 #define RB2D_DSTCACHE_CTLSTAT 0x342C | |
373 | |
374 | |
375 #define CLK_PIN_CNTL 0x0001 | |
376 #define PPLL_CNTL 0x0002 | |
377 #define PPLL_REF_DIV 0x0003 | |
378 #define PPLL_DIV_0 0x0004 | |
379 #define PPLL_DIV_1 0x0005 | |
380 #define PPLL_DIV_2 0x0006 | |
381 #define PPLL_DIV_3 0x0007 | |
382 #define VCLK_ECP_CNTL 0x0008 | |
383 #define HTOTAL_CNTL 0x0009 | |
384 #define M_SPLL_REF_FB_DIV 0x000a | |
385 #define AGP_PLL_CNTL 0x000b | |
386 #define SPLL_CNTL 0x000c | |
387 #define SCLK_CNTL 0x000d | |
388 #define MPLL_CNTL 0x000e | |
389 #define MCLK_CNTL 0x0012 | |
390 #define AGP_PLL_CNTL 0x000b | |
391 #define PLL_TEST_CNTL 0x0013 | |
392 | |
393 | |
394 /* MCLK_CNTL bit constants */ | |
395 #define FORCEON_MCLKA (1 << 16) | |
396 #define FORCEON_MCLKB (1 << 17) | |
397 #define FORCEON_YCLKA (1 << 18) | |
398 #define FORCEON_YCLKB (1 << 19) | |
399 #define FORCEON_MC (1 << 20) | |
400 #define FORCEON_AIC (1 << 21) | |
401 | |
402 | |
403 /* BUS_CNTL bit constants */ | |
404 #define BUS_DBL_RESYNC 0x00000001 | |
405 #define BUS_MSTR_RESET 0x00000002 | |
406 #define BUS_FLUSH_BUF 0x00000004 | |
407 #define BUS_STOP_REQ_DIS 0x00000008 | |
408 #define BUS_ROTATION_DIS 0x00000010 | |
409 #define BUS_MASTER_DIS 0x00000040 | |
410 #define BUS_ROM_WRT_EN 0x00000080 | |
411 #define BUS_DIS_ROM 0x00001000 | |
412 #define BUS_PCI_READ_RETRY_EN 0x00002000 | |
413 #define BUS_AGP_AD_STEPPING_EN 0x00004000 | |
414 #define BUS_PCI_WRT_RETRY_EN 0x00008000 | |
415 #define BUS_MSTR_RD_MULT 0x00100000 | |
416 #define BUS_MSTR_RD_LINE 0x00200000 | |
417 #define BUS_SUSPEND 0x00400000 | |
418 #define LAT_16X 0x00800000 | |
419 #define BUS_RD_DISCARD_EN 0x01000000 | |
420 #define BUS_RD_ABORT_EN 0x02000000 | |
421 #define BUS_MSTR_WS 0x04000000 | |
422 #define BUS_PARKING_DIS 0x08000000 | |
423 #define BUS_MSTR_DISCONNECT_EN 0x10000000 | |
424 #define BUS_WRT_BURST 0x20000000 | |
425 #define BUS_READ_BURST 0x40000000 | |
426 #define BUS_RDY_READ_DLY 0x80000000 | |
427 | |
428 | |
429 /* CLOCK_CNTL_INDEX bit constants */ | |
430 #define PLL_WR_EN 0x00000080 | |
431 | |
432 /* CONFIG_CNTL bit constants */ | |
433 #define CFG_VGA_RAM_EN 0x00000100 | |
434 | |
435 /* CRTC_EXT_CNTL bit constants */ | |
436 #define VGA_ATI_LINEAR 0x00000008 | |
437 #define VGA_128KAP_PAGING 0x00000010 | |
438 #define XCRT_CNT_EN (1 << 6) | |
439 #define CRTC_HSYNC_DIS (1 << 8) | |
440 #define CRTC_VSYNC_DIS (1 << 9) | |
441 #define CRTC_DISPLAY_DIS (1 << 10) | |
442 | |
443 | |
444 /* DSTCACHE_CTLSTAT bit constants */ | |
445 #define RB2D_DC_FLUSH (3 << 0) | |
446 #define RB2D_DC_FLUSH_ALL 0xf | |
447 #define RB2D_DC_BUSY (1 << 31) | |
448 | |
449 | |
450 /* CRTC_GEN_CNTL bit constants */ | |
451 #define CRTC_DBL_SCAN_EN 0x00000001 | |
452 #define CRTC_CUR_EN 0x00010000 | |
453 #define CRTC_EXT_DISP_EN (1 << 24) | |
454 #define CRTC_EN (1 << 25) | |
455 | |
456 /* CRTC_STATUS bit constants */ | |
457 #define CRTC_VBLANK 0x00000001 | |
458 | |
459 /* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */ | |
460 #define CUR_LOCK 0x80000000 | |
461 | |
462 /* DAC_CNTL bit constants */ | |
463 #define DAC_8BIT_EN 0x00000100 | |
464 #define DAC_4BPP_PIX_ORDER 0x00000200 | |
465 #define DAC_CRC_EN 0x00080000 | |
466 #define DAC_MASK_ALL (0xff << 24) | |
467 #define DAC_VGA_ADR_EN (1 << 13) | |
468 #define DAC_RANGE_CNTL (3 << 0) | |
469 #define DAC_BLANKING (1 << 2) | |
470 | |
471 /* GEN_RESET_CNTL bit constants */ | |
472 #define SOFT_RESET_GUI 0x00000001 | |
473 #define SOFT_RESET_VCLK 0x00000100 | |
474 #define SOFT_RESET_PCLK 0x00000200 | |
475 #define SOFT_RESET_ECP 0x00000400 | |
476 #define SOFT_RESET_DISPENG_XCLK 0x00000800 | |
477 | |
478 /* MEM_CNTL bit constants */ | |
479 #define MEM_CTLR_STATUS_IDLE 0x00000000 | |
480 #define MEM_CTLR_STATUS_BUSY 0x00100000 | |
481 #define MEM_SEQNCR_STATUS_IDLE 0x00000000 | |
482 #define MEM_SEQNCR_STATUS_BUSY 0x00200000 | |
483 #define MEM_ARBITER_STATUS_IDLE 0x00000000 | |
484 #define MEM_ARBITER_STATUS_BUSY 0x00400000 | |
485 #define MEM_REQ_UNLOCK 0x00000000 | |
486 #define MEM_REQ_LOCK 0x00800000 | |
487 | |
488 | |
489 /* RBBM_SOFT_RESET bit constants */ | |
490 #define SOFT_RESET_CP (1 << 0) | |
491 #define SOFT_RESET_HI (1 << 1) | |
492 #define SOFT_RESET_SE (1 << 2) | |
493 #define SOFT_RESET_RE (1 << 3) | |
494 #define SOFT_RESET_PP (1 << 4) | |
495 #define SOFT_RESET_E2 (1 << 5) | |
496 #define SOFT_RESET_RB (1 << 6) | |
497 #define SOFT_RESET_HDP (1 << 7) | |
498 | |
499 | |
500 /* DEFAULT_SC_BOTTOM_RIGHT bit constants */ | |
501 #define DEFAULT_SC_RIGHT_MAX (0x1fff << 0) | |
502 #define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) | |
503 | |
504 /* MM_INDEX bit constants */ | |
505 #define MM_APER 0x80000000 | |
506 | |
507 /* CLR_CMP_CNTL bit constants */ | |
508 #define COMPARE_SRC_FALSE 0x00000000 | |
509 #define COMPARE_SRC_TRUE 0x00000001 | |
510 #define COMPARE_SRC_NOT_EQUAL 0x00000004 | |
511 #define COMPARE_SRC_EQUAL 0x00000005 | |
512 #define COMPARE_SRC_EQUAL_FLIP 0x00000007 | |
513 #define COMPARE_DST_FALSE 0x00000000 | |
514 #define COMPARE_DST_TRUE 0x00000100 | |
515 #define COMPARE_DST_NOT_EQUAL 0x00000400 | |
516 #define COMPARE_DST_EQUAL 0x00000500 | |
517 #define COMPARE_DESTINATION 0x00000000 | |
518 #define COMPARE_SOURCE 0x01000000 | |
519 #define COMPARE_SRC_AND_DST 0x02000000 | |
520 | |
521 | |
522 /* DP_CNTL bit constants */ | |
523 #define DST_X_RIGHT_TO_LEFT 0x00000000 | |
524 #define DST_X_LEFT_TO_RIGHT 0x00000001 | |
525 #define DST_Y_BOTTOM_TO_TOP 0x00000000 | |
526 #define DST_Y_TOP_TO_BOTTOM 0x00000002 | |
527 #define DST_X_MAJOR 0x00000000 | |
528 #define DST_Y_MAJOR 0x00000004 | |
529 #define DST_X_TILE 0x00000008 | |
530 #define DST_Y_TILE 0x00000010 | |
531 #define DST_LAST_PEL 0x00000020 | |
532 #define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000 | |
533 #define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040 | |
534 #define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000 | |
535 #define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080 | |
536 #define DST_BRES_SIGN 0x00000100 | |
537 #define DST_HOST_BIG_ENDIAN_EN 0x00000200 | |
538 #define DST_POLYLINE_NONLAST 0x00008000 | |
539 #define DST_RASTER_STALL 0x00010000 | |
540 #define DST_POLY_EDGE 0x00040000 | |
541 | |
542 | |
543 /* DP_CNTL_YDIR_XDIR_YMAJOR bit constants (short version of DP_CNTL) */ | |
544 #define DST_X_MAJOR_S 0x00000000 | |
545 #define DST_Y_MAJOR_S 0x00000001 | |
546 #define DST_Y_BOTTOM_TO_TOP_S 0x00000000 | |
547 #define DST_Y_TOP_TO_BOTTOM_S 0x00008000 | |
548 #define DST_X_RIGHT_TO_LEFT_S 0x00000000 | |
549 #define DST_X_LEFT_TO_RIGHT_S 0x80000000 | |
550 | |
551 | |
552 /* DP_DATATYPE bit constants */ | |
553 #define DST_8BPP 0x00000002 | |
554 #define DST_15BPP 0x00000003 | |
555 #define DST_16BPP 0x00000004 | |
556 #define DST_24BPP 0x00000005 | |
557 #define DST_32BPP 0x00000006 | |
558 #define DST_8BPP_RGB332 0x00000007 | |
559 #define DST_8BPP_Y8 0x00000008 | |
560 #define DST_8BPP_RGB8 0x00000009 | |
561 #define DST_16BPP_VYUY422 0x0000000b | |
562 #define DST_16BPP_YVYU422 0x0000000c | |
563 #define DST_32BPP_AYUV444 0x0000000e | |
564 #define DST_16BPP_ARGB4444 0x0000000f | |
565 #define BRUSH_SOLIDCOLOR 0x00000d00 | |
566 #define SRC_MONO 0x00000000 | |
567 #define SRC_MONO_LBKGD 0x00010000 | |
568 #define SRC_DSTCOLOR 0x00030000 | |
569 #define BYTE_ORDER_MSB_TO_LSB 0x00000000 | |
570 #define BYTE_ORDER_LSB_TO_MSB 0x40000000 | |
571 #define DP_CONVERSION_TEMP 0x80000000 | |
572 #define HOST_BIG_ENDIAN_EN (1 << 29) | |
573 | |
574 | |
575 /* DP_GUI_MASTER_CNTL bit constants */ | |
576 #define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000 | |
577 #define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001 | |
578 #define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000 | |
579 #define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002 | |
580 #define GMC_SRC_CLIP_DEFAULT 0x00000000 | |
581 #define GMC_SRC_CLIP_LEAVE 0x00000004 | |
582 #define GMC_DST_CLIP_DEFAULT 0x00000000 | |
583 #define GMC_DST_CLIP_LEAVE 0x00000008 | |
584 #define GMC_BRUSH_8x8MONO 0x00000000 | |
585 #define GMC_BRUSH_8x8MONO_LBKGD 0x00000010 | |
586 #define GMC_BRUSH_8x1MONO 0x00000020 | |
587 #define GMC_BRUSH_8x1MONO_LBKGD 0x00000030 | |
588 #define GMC_BRUSH_1x8MONO 0x00000040 | |
589 #define GMC_BRUSH_1x8MONO_LBKGD 0x00000050 | |
590 #define GMC_BRUSH_32x1MONO 0x00000060 | |
591 #define GMC_BRUSH_32x1MONO_LBKGD 0x00000070 | |
592 #define GMC_BRUSH_32x32MONO 0x00000080 | |
593 #define GMC_BRUSH_32x32MONO_LBKGD 0x00000090 | |
594 #define GMC_BRUSH_8x8COLOR 0x000000a0 | |
595 #define GMC_BRUSH_8x1COLOR 0x000000b0 | |
596 #define GMC_BRUSH_1x8COLOR 0x000000c0 | |
597 #define GMC_BRUSH_SOLID_COLOR 0x000000d0 | |
598 #define GMC_DST_8BPP 0x00000200 | |
599 #define GMC_DST_15BPP 0x00000300 | |
600 #define GMC_DST_16BPP 0x00000400 | |
601 #define GMC_DST_24BPP 0x00000500 | |
602 #define GMC_DST_32BPP 0x00000600 | |
603 #define GMC_DST_8BPP_RGB332 0x00000700 | |
604 #define GMC_DST_8BPP_Y8 0x00000800 | |
605 #define GMC_DST_8BPP_RGB8 0x00000900 | |
606 #define GMC_DST_16BPP_VYUY422 0x00000b00 | |
607 #define GMC_DST_16BPP_YVYU422 0x00000c00 | |
608 #define GMC_DST_32BPP_AYUV444 0x00000e00 | |
609 #define GMC_DST_16BPP_ARGB4444 0x00000f00 | |
610 #define GMC_SRC_MONO 0x00000000 | |
611 #define GMC_SRC_MONO_LBKGD 0x00001000 | |
612 #define GMC_SRC_DSTCOLOR 0x00003000 | |
613 #define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 | |
614 #define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000 | |
615 #define GMC_DP_CONVERSION_TEMP_9300 0x00008000 | |
616 #define GMC_DP_CONVERSION_TEMP_6500 0x00000000 | |
617 #define GMC_DP_SRC_RECT 0x02000000 | |
618 #define GMC_DP_SRC_HOST 0x03000000 | |
619 #define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000 | |
620 #define GMC_3D_FCN_EN_CLR 0x00000000 | |
621 #define GMC_3D_FCN_EN_SET 0x08000000 | |
622 #define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000 | |
623 #define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000 | |
624 #define GMC_AUX_CLIP_LEAVE 0x00000000 | |
625 #define GMC_AUX_CLIP_CLEAR 0x20000000 | |
626 #define GMC_WRITE_MASK_LEAVE 0x00000000 | |
627 #define GMC_WRITE_MASK_SET 0x40000000 | |
628 #define GMC_CLR_CMP_CNTL_DIS (1 << 28) | |
629 #define GMC_SRC_DATATYPE_COLOR (3 << 12) | |
630 #define ROP3_S 0x00cc0000 | |
631 #define ROP3_P 0x00f00000 | |
632 #define DP_SRC_SOURCE_MASK (7 << 24) | |
633 #define GMC_BRUSH_NONE (15 << 4) | |
634 #define DP_SRC_SOURCE_MEMORY (2 << 24) | |
635 #define GMC_BRUSH_SOLIDCOLOR 0x000000d0 | |
636 | |
637 /* DP_MIX bit constants */ | |
638 #define DP_SRC_RECT 0x00000200 | |
639 #define DP_SRC_HOST 0x00000300 | |
640 #define DP_SRC_HOST_BYTEALIGN 0x00000400 | |
641 | |
642 #define ROP3_PATCOPY 0x00f00000 | |
643 | |
644 /* masks */ | |
645 | |
646 #define CONFIG_MEMSIZE_MASK 0x1f000000 | |
647 #define MEM_CFG_TYPE 0x40000000 | |
648 #define DST_OFFSET_MASK 0x003fffff | |
649 #define DST_PITCH_MASK 0x3fc00000 | |
650 #define DEFAULT_TILE_MASK 0xc0000000 | |
651 #define PPLL_DIV_SEL_MASK 0x00000300 | |
652 #define PPLL_RESET 0x00000001 | |
653 #define PPLL_ATOMIC_UPDATE_EN 0x00010000 | |
654 #define PPLL_REF_DIV_MASK 0x000003ff | |
655 #define PPLL_FB3_DIV_MASK 0x000007ff | |
656 #define PPLL_POST3_DIV_MASK 0x00070000 | |
657 #define PPLL_ATOMIC_UPDATE_R 0x00008000 | |
658 #define PPLL_ATOMIC_UPDATE_W 0x00008000 | |
659 #define PPLL_VGA_ATOMIC_UPDATE_EN 0x00020000 | |
660 | |
661 #define GUI_ACTIVE 0x80000000 | |
662 | |
663 #endif /* _RADEON_H */ | |
664 |