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comparison vidix/drivers/radeon_vid.c @ 5041:8a708971d372

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Fixed swapping of UV planes in single buffered mode
author nick
date Mon, 11 Mar 2002 07:46:04 +0000
parents d5280777c2f0
children 43dc579db3d1
comparison
equal deleted inserted replaced
5040:568ca851a05b 5041:8a708971d372
964 OUTREG(OV0_P3_X_START_END, besr.p3_x_start_end); 964 OUTREG(OV0_P3_X_START_END, besr.p3_x_start_end);
965 #ifdef RADEON 965 #ifdef RADEON
966 OUTREG(OV0_BASE_ADDR, besr.base_addr); 966 OUTREG(OV0_BASE_ADDR, besr.base_addr);
967 #endif 967 #endif
968 OUTREG(OV0_VID_BUF0_BASE_ADRS, besr.vid_buf_base_adrs_y[0]); 968 OUTREG(OV0_VID_BUF0_BASE_ADRS, besr.vid_buf_base_adrs_y[0]);
969 OUTREG(OV0_VID_BUF1_BASE_ADRS, besr.vid_buf_base_adrs_u[0]); 969 OUTREG(OV0_VID_BUF1_BASE_ADRS, besr.vid_buf_base_adrs_v[0]);
970 OUTREG(OV0_VID_BUF2_BASE_ADRS, besr.vid_buf_base_adrs_v[0]); 970 OUTREG(OV0_VID_BUF2_BASE_ADRS, besr.vid_buf_base_adrs_u[0]);
971 radeon_fifo_wait(9); 971 radeon_fifo_wait(9);
972 OUTREG(OV0_VID_BUF3_BASE_ADRS, besr.vid_buf_base_adrs_y[0]); 972 OUTREG(OV0_VID_BUF3_BASE_ADRS, besr.vid_buf_base_adrs_y[0]);
973 OUTREG(OV0_VID_BUF4_BASE_ADRS, besr.vid_buf_base_adrs_u[0]); 973 OUTREG(OV0_VID_BUF4_BASE_ADRS, besr.vid_buf_base_adrs_v[0]);
974 OUTREG(OV0_VID_BUF5_BASE_ADRS, besr.vid_buf_base_adrs_v[0]); 974 OUTREG(OV0_VID_BUF5_BASE_ADRS, besr.vid_buf_base_adrs_u[0]);
975 OUTREG(OV0_P1_V_ACCUM_INIT, besr.p1_v_accum_init); 975 OUTREG(OV0_P1_V_ACCUM_INIT, besr.p1_v_accum_init);
976 OUTREG(OV0_P1_H_ACCUM_INIT, besr.p1_h_accum_init); 976 OUTREG(OV0_P1_H_ACCUM_INIT, besr.p1_h_accum_init);
977 OUTREG(OV0_P23_H_ACCUM_INIT, besr.p23_h_accum_init); 977 OUTREG(OV0_P23_H_ACCUM_INIT, besr.p23_h_accum_init);
978 OUTREG(OV0_P23_V_ACCUM_INIT, besr.p23_v_accum_init); 978 OUTREG(OV0_P23_V_ACCUM_INIT, besr.p23_v_accum_init);
979 979