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comparison vidix/nvidia_vid.c @ 22880:8b0cfdc71759

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GeForce 6x00 and above are actually referenced as NV40 in X.Org driver (though it doesn't work better right now)
author ben
date Sun, 01 Apr 2007 20:48:34 +0000
parents 9a8f6901e888
children a9e111b88c4a
comparison
equal deleted inserted replaced
22879:910cdc3f2afb 22880:8b0cfdc71759
55 #define NV_ARCH_03 0x03 55 #define NV_ARCH_03 0x03
56 #define NV_ARCH_04 0x04 56 #define NV_ARCH_04 0x04
57 #define NV_ARCH_10 0x10 57 #define NV_ARCH_10 0x10
58 #define NV_ARCH_20 0x20 58 #define NV_ARCH_20 0x20
59 #define NV_ARCH_30 0x30 59 #define NV_ARCH_30 0x30
60 #define NV_ARCH_40 0x40
60 61
61 // since no useful information whatsoever is passed 62 // since no useful information whatsoever is passed
62 // to the equalizer functions we need this 63 // to the equalizer functions we need this
63 static struct { 64 static struct {
64 uint32_t lum; // luminance (brightness + contrast) 65 uint32_t lum; // luminance (brightness + contrast)
216 {DEVICE_NVIDIA_NV36_GEFORCE_PCX,NV_ARCH_30}, 217 {DEVICE_NVIDIA_NV36_GEFORCE_PCX,NV_ARCH_30},
217 {DEVICE_NVIDIA_NV35_GEFORCE_PCX,NV_ARCH_30}, 218 {DEVICE_NVIDIA_NV35_GEFORCE_PCX,NV_ARCH_30},
218 {DEVICE_NVIDIA_NV37GL_QUADRO_FX,NV_ARCH_30}, 219 {DEVICE_NVIDIA_NV37GL_QUADRO_FX,NV_ARCH_30},
219 {DEVICE_NVIDIA_NV37GL_QUADRO_FX2,NV_ARCH_30}, 220 {DEVICE_NVIDIA_NV37GL_QUADRO_FX2,NV_ARCH_30},
220 {DEVICE_NVIDIA_NV38GL_QUADRO_FX,NV_ARCH_30}, 221 {DEVICE_NVIDIA_NV38GL_QUADRO_FX,NV_ARCH_30},
221 /* FIXME are they different? */ 222 /* NV40: GeForce 6x00 to 7x00 */
222 {DEVICE_NVIDIA_NV40_GEFORCE_6800,NV_ARCH_30}, 223 {DEVICE_NVIDIA_NV40_GEFORCE_6800,NV_ARCH_40},
223 {DEVICE_NVIDIA_NV40_GEFORCE_68002,NV_ARCH_30}, 224 {DEVICE_NVIDIA_NV40_GEFORCE_68002,NV_ARCH_40},
224 {DEVICE_NVIDIA_NV40_2_GEFORCE_6800,NV_ARCH_30}, 225 {DEVICE_NVIDIA_NV40_2_GEFORCE_6800,NV_ARCH_40},
225 {DEVICE_NVIDIA_NV40_3,NV_ARCH_30}, 226 {DEVICE_NVIDIA_NV40_3,NV_ARCH_40},
226 {DEVICE_NVIDIA_NV40_GEFORCE_68003,NV_ARCH_30}, 227 {DEVICE_NVIDIA_NV40_GEFORCE_68003,NV_ARCH_40},
227 {DEVICE_NVIDIA_NV40_GEFORCE_68004,NV_ARCH_30}, 228 {DEVICE_NVIDIA_NV40_GEFORCE_68004,NV_ARCH_40},
228 {DEVICE_NVIDIA_NV40_GEFORCE_68005,NV_ARCH_30}, 229 {DEVICE_NVIDIA_NV40_GEFORCE_68005,NV_ARCH_40},
229 {DEVICE_NVIDIA_NV40_GEFORCE_68006,NV_ARCH_30}, 230 {DEVICE_NVIDIA_NV40_GEFORCE_68006,NV_ARCH_40},
230 {DEVICE_NVIDIA_NV40_GEFORCE_68007,NV_ARCH_30}, 231 {DEVICE_NVIDIA_NV40_GEFORCE_68007,NV_ARCH_40},
231 {DEVICE_NVIDIA_NV40_GEFORCE_68008,NV_ARCH_30}, 232 {DEVICE_NVIDIA_NV40_GEFORCE_68008,NV_ARCH_40},
232 {DEVICE_NVIDIA_NV40_GEFORCE_68009,NV_ARCH_30}, 233 {DEVICE_NVIDIA_NV40_GEFORCE_68009,NV_ARCH_40},
233 {DEVICE_NVIDIA_NV40_GEFORCE_680010,NV_ARCH_30}, 234 {DEVICE_NVIDIA_NV40_GEFORCE_680010,NV_ARCH_40},
234 {DEVICE_NVIDIA_NV40_GEFORCE_680011,NV_ARCH_30}, 235 {DEVICE_NVIDIA_NV40_GEFORCE_680011,NV_ARCH_40},
235 {DEVICE_NVIDIA_NV40_GEFORCE_680012,NV_ARCH_30}, 236 {DEVICE_NVIDIA_NV40_GEFORCE_680012,NV_ARCH_40},
236 {DEVICE_NVIDIA_NV40_GEFORCE_68008,NV_ARCH_30}, 237 {DEVICE_NVIDIA_NV40_GEFORCE_68008,NV_ARCH_40},
237 {DEVICE_NVIDIA_NV40GL,NV_ARCH_30}, 238 {DEVICE_NVIDIA_NV40GL,NV_ARCH_40},
238 {DEVICE_NVIDIA_NV40GL_QUADRO_FX,NV_ARCH_30}, 239 {DEVICE_NVIDIA_NV40GL_QUADRO_FX,NV_ARCH_40},
239 {DEVICE_NVIDIA_NV40GL_QUADRO_FX2,NV_ARCH_30}, 240 {DEVICE_NVIDIA_NV40GL_QUADRO_FX2,NV_ARCH_40},
240 {DEVICE_NVIDIA_NV41_GEFORCE_6800,NV_ARCH_30}, 241 {DEVICE_NVIDIA_NV41_GEFORCE_6800,NV_ARCH_40},
241 {DEVICE_NVIDIA_NV41_1_GEFORCE_6800,NV_ARCH_30}, 242 {DEVICE_NVIDIA_NV41_1_GEFORCE_6800,NV_ARCH_40},
242 {DEVICE_NVIDIA_NV41_2_GEFORCE_6800,NV_ARCH_30}, 243 {DEVICE_NVIDIA_NV41_2_GEFORCE_6800,NV_ARCH_40},
243 {DEVICE_NVIDIA_NV41_8_GEFORCE_GO,NV_ARCH_30}, 244 {DEVICE_NVIDIA_NV41_8_GEFORCE_GO,NV_ARCH_40},
244 {DEVICE_NVIDIA_NV41_9_GEFORCE_GO,NV_ARCH_30}, 245 {DEVICE_NVIDIA_NV41_9_GEFORCE_GO,NV_ARCH_40},
245 {DEVICE_NVIDIA_NV41_QUADRO_FX,NV_ARCH_30}, 246 {DEVICE_NVIDIA_NV41_QUADRO_FX,NV_ARCH_40},
246 {DEVICE_NVIDIA_NV41_QUADRO_FX2,NV_ARCH_30}, 247 {DEVICE_NVIDIA_NV41_QUADRO_FX2,NV_ARCH_40},
247 {DEVICE_NVIDIA_NV41GL_QUADRO_FX,NV_ARCH_30}, 248 {DEVICE_NVIDIA_NV41GL_QUADRO_FX,NV_ARCH_40},
248 {DEVICE_NVIDIA_NV41GL_QUADRO_FX,NV_ARCH_30}, 249 {DEVICE_NVIDIA_NV41GL_QUADRO_FX,NV_ARCH_40},
249 {DEVICE_NVIDIA_NV40_GEFORCE_6800_GEFORCE,NV_ARCH_30}, 250 {DEVICE_NVIDIA_NV40_GEFORCE_6800_GEFORCE,NV_ARCH_40},
250 {DEVICE_NVIDIA_NV43_GEFORCE_6600_GEFORCE,NV_ARCH_30}, 251 {DEVICE_NVIDIA_NV43_GEFORCE_6600_GEFORCE,NV_ARCH_40},
251 {DEVICE_NVIDIA_NV43_GEFORCE_6600_GEFORCE2,NV_ARCH_30}, 252 {DEVICE_NVIDIA_NV43_GEFORCE_6600_GEFORCE2,NV_ARCH_40},
252 {DEVICE_NVIDIA_NV43_GEFORCE_6200,NV_ARCH_30}, 253 {DEVICE_NVIDIA_NV43_GEFORCE_6200,NV_ARCH_40},
253 {DEVICE_NVIDIA_NV43_GEFORCE_62002,NV_ARCH_30}, 254 {DEVICE_NVIDIA_NV43_GEFORCE_62002,NV_ARCH_40},
254 {DEVICE_NVIDIA_NV43_GEFORCE_6600,NV_ARCH_30}, 255 {DEVICE_NVIDIA_NV43_GEFORCE_6600,NV_ARCH_40},
255 {DEVICE_NVIDIA_NV43_GEFORCE_66002,NV_ARCH_30}, 256 {DEVICE_NVIDIA_NV43_GEFORCE_66002,NV_ARCH_40},
256 {DEVICE_NVIDIA_NV43_GEFORCE_66003,NV_ARCH_30}, 257 {DEVICE_NVIDIA_NV43_GEFORCE_66003,NV_ARCH_40},
257 {DEVICE_NVIDIA_NV43_GEFORCE_66004,NV_ARCH_30}, 258 {DEVICE_NVIDIA_NV43_GEFORCE_66004,NV_ARCH_40},
258 {DEVICE_NVIDIA_NV43_GEFORCE_66005,NV_ARCH_30}, 259 {DEVICE_NVIDIA_NV43_GEFORCE_66005,NV_ARCH_40},
259 {DEVICE_NVIDIA_NV43_GEFORCE_GO,NV_ARCH_30}, 260 {DEVICE_NVIDIA_NV43_GEFORCE_GO,NV_ARCH_40},
260 {DEVICE_NVIDIA_NV43_GEFORCE_GO2,NV_ARCH_30}, 261 {DEVICE_NVIDIA_NV43_GEFORCE_GO2,NV_ARCH_40},
261 {DEVICE_NVIDIA_NV43_GEFORCE_GO3,NV_ARCH_30}, 262 {DEVICE_NVIDIA_NV43_GEFORCE_GO3,NV_ARCH_40},
262 {DEVICE_NVIDIA_NV43_GEFORCE_GO4,NV_ARCH_30}, 263 {DEVICE_NVIDIA_NV43_GEFORCE_GO4,NV_ARCH_40},
263 {DEVICE_NVIDIA_NV43_GEFORCE_GO5,NV_ARCH_30}, 264 {DEVICE_NVIDIA_NV43_GEFORCE_GO5,NV_ARCH_40},
264 {DEVICE_NVIDIA_NV43_GEFORCE_GO6,NV_ARCH_30}, 265 {DEVICE_NVIDIA_NV43_GEFORCE_GO6,NV_ARCH_40},
265 {DEVICE_NVIDIA_NV43_GEFORCE_6610,NV_ARCH_30}, 266 {DEVICE_NVIDIA_NV43_GEFORCE_6610,NV_ARCH_40},
266 {DEVICE_NVIDIA_NV43GL_QUADRO_FX,NV_ARCH_30}, 267 {DEVICE_NVIDIA_NV43GL_QUADRO_FX,NV_ARCH_40},
267 {DEVICE_NVIDIA_GEFORCE_6100_NFORCE,NV_ARCH_30}, 268 {DEVICE_NVIDIA_GEFORCE_6100_NFORCE,NV_ARCH_40},
268 {DEVICE_NVIDIA_GEFORCE_6100_NFORCE2,NV_ARCH_30}, 269 {DEVICE_NVIDIA_GEFORCE_6100_NFORCE2,NV_ARCH_40},
269 {DEVICE_NVIDIA_GEFORCE_6100_NFORCE3,NV_ARCH_30}, 270 {DEVICE_NVIDIA_GEFORCE_6100_NFORCE3,NV_ARCH_40},
270 {DEVICE_NVIDIA_GEFORCE_6100_NFORCE4,NV_ARCH_30}, 271 {DEVICE_NVIDIA_GEFORCE_6100_NFORCE4,NV_ARCH_40},
271 {DEVICE_NVIDIA_C51G_GEFORCE_6100,NV_ARCH_30}, 272 {DEVICE_NVIDIA_C51G_GEFORCE_6100,NV_ARCH_40},
272 {DEVICE_NVIDIA_C51PV_GEFORCE_6150,NV_ARCH_30}, 273 {DEVICE_NVIDIA_C51PV_GEFORCE_6150,NV_ARCH_40},
273 {DEVICE_NVIDIA_NV44_GEFORCE_6200,NV_ARCH_30}, 274 {DEVICE_NVIDIA_NV44_GEFORCE_6200,NV_ARCH_40},
274 {DEVICE_NVIDIA_NV44_GEFORCE_62002,NV_ARCH_30}, 275 {DEVICE_NVIDIA_NV44_GEFORCE_62002,NV_ARCH_40},
275 {DEVICE_NVIDIA_NV44_GEFORCE_62003,NV_ARCH_30}, 276 {DEVICE_NVIDIA_NV44_GEFORCE_62003,NV_ARCH_40},
276 {DEVICE_NVIDIA_NV44_GEFORCE_GO,NV_ARCH_30}, 277 {DEVICE_NVIDIA_NV44_GEFORCE_GO,NV_ARCH_40},
277 {DEVICE_NVIDIA_NV44_QUADRO_NVS,NV_ARCH_30}, 278 {DEVICE_NVIDIA_NV44_QUADRO_NVS,NV_ARCH_40},
278 {DEVICE_NVIDIA_GEFORCE_GO_6200,NV_ARCH_30}, 279 {DEVICE_NVIDIA_GEFORCE_GO_6200,NV_ARCH_40},
279 {DEVICE_NVIDIA_NV44A_GEFORCE_6200,NV_ARCH_30}, 280 {DEVICE_NVIDIA_NV44A_GEFORCE_6200,NV_ARCH_40},
280 {DEVICE_NVIDIA_NV45GL_QUADRO_FX,NV_ARCH_30}, 281 {DEVICE_NVIDIA_NV45GL_QUADRO_FX,NV_ARCH_40},
281 {DEVICE_NVIDIA_GEFORCE_GO_7200,NV_ARCH_30}, 282 {DEVICE_NVIDIA_GEFORCE_GO_7200,NV_ARCH_40},
282 {DEVICE_NVIDIA_QUADRO_NVS_110M,NV_ARCH_30}, 283 {DEVICE_NVIDIA_QUADRO_NVS_110M,NV_ARCH_40},
283 {DEVICE_NVIDIA_GEFORCE_GO_7400,NV_ARCH_30}, 284 {DEVICE_NVIDIA_GEFORCE_GO_7400,NV_ARCH_40},
284 {DEVICE_NVIDIA_QUADRO_NVS_110M2,NV_ARCH_30}, 285 {DEVICE_NVIDIA_QUADRO_NVS_110M2,NV_ARCH_40},
285 {DEVICE_NVIDIA_QUADRO_FX_350,NV_ARCH_30}, 286 {DEVICE_NVIDIA_QUADRO_FX_350,NV_ARCH_40},
286 {DEVICE_NVIDIA_G70_GEFORCE_7300,NV_ARCH_30}, 287 {DEVICE_NVIDIA_G70_GEFORCE_7300,NV_ARCH_40},
287 {DEVICE_NVIDIA_GEFORCE_7300_GS,NV_ARCH_30}, 288 {DEVICE_NVIDIA_GEFORCE_7300_GS,NV_ARCH_40},
288 {DEVICE_NVIDIA_G70_GEFORCE_7600,NV_ARCH_30}, 289 {DEVICE_NVIDIA_G70_GEFORCE_7600,NV_ARCH_40},
289 {DEVICE_NVIDIA_G70_GEFORCE_76002,NV_ARCH_30}, 290 {DEVICE_NVIDIA_G70_GEFORCE_76002,NV_ARCH_40},
290 {DEVICE_NVIDIA_GEFORCE_7600_GS,NV_ARCH_30}, 291 {DEVICE_NVIDIA_GEFORCE_7600_GS,NV_ARCH_40},
291 {DEVICE_NVIDIA_G70_GEFORCE_GO,NV_ARCH_30}, 292 {DEVICE_NVIDIA_G70_GEFORCE_GO,NV_ARCH_40},
292 {DEVICE_NVIDIA_QUADRO_FX_560,NV_ARCH_30}, 293 {DEVICE_NVIDIA_QUADRO_FX_560,NV_ARCH_40},
293 {DEVICE_NVIDIA_G70_GEFORCE_7800,NV_ARCH_30}, 294 {DEVICE_NVIDIA_G70_GEFORCE_7800,NV_ARCH_40},
294 {DEVICE_NVIDIA_G70_GEFORCE_78002,NV_ARCH_30}, 295 {DEVICE_NVIDIA_G70_GEFORCE_78002,NV_ARCH_40},
295 {DEVICE_NVIDIA_G70_GEFORCE_78003,NV_ARCH_30}, 296 {DEVICE_NVIDIA_G70_GEFORCE_78003,NV_ARCH_40},
296 {DEVICE_NVIDIA_G70_GEFORCE_78004,NV_ARCH_30}, 297 {DEVICE_NVIDIA_G70_GEFORCE_78004,NV_ARCH_40},
297 {DEVICE_NVIDIA_G70_GEFORCE_78005,NV_ARCH_30}, 298 {DEVICE_NVIDIA_G70_GEFORCE_78005,NV_ARCH_40},
298 {DEVICE_NVIDIA_GEFORCE_GO_7800,NV_ARCH_30}, 299 {DEVICE_NVIDIA_GEFORCE_GO_7800,NV_ARCH_40},
299 {DEVICE_NVIDIA_GEFORCE_7900_GTX,NV_ARCH_30}, 300 {DEVICE_NVIDIA_GEFORCE_7900_GTX,NV_ARCH_40},
300 {DEVICE_NVIDIA_GEFORCE_7900_GT,NV_ARCH_30}, 301 {DEVICE_NVIDIA_GEFORCE_7900_GT,NV_ARCH_40},
301 {DEVICE_NVIDIA_GEFORCE_7900_GS,NV_ARCH_30}, 302 {DEVICE_NVIDIA_GEFORCE_7900_GS,NV_ARCH_40},
302 {DEVICE_NVIDIA_GEFORCE_GO_7900,NV_ARCH_30}, 303 {DEVICE_NVIDIA_GEFORCE_GO_7900,NV_ARCH_40},
303 {DEVICE_NVIDIA_GEFORCE_GO_79002,NV_ARCH_30}, 304 {DEVICE_NVIDIA_GEFORCE_GO_79002,NV_ARCH_40},
304 {DEVICE_NVIDIA_GE_FORCE_GO,NV_ARCH_30}, 305 {DEVICE_NVIDIA_GE_FORCE_GO,NV_ARCH_40},
305 {DEVICE_NVIDIA_G70GL_QUADRO_FX4500,NV_ARCH_30}, 306 {DEVICE_NVIDIA_G70GL_QUADRO_FX4500,NV_ARCH_40},
306 {DEVICE_NVIDIA_G71_QUADRO_FX,NV_ARCH_30}, 307 {DEVICE_NVIDIA_G71_QUADRO_FX,NV_ARCH_40},
307 {DEVICE_NVIDIA_G71_QUADRO_FX2,NV_ARCH_30} 308 {DEVICE_NVIDIA_G71_QUADRO_FX2,NV_ARCH_40}
308 }; 309 };
309 310
310 311
311 static int find_chip(unsigned chip_id){ 312 static int find_chip(unsigned chip_id){
312 unsigned i; 313 unsigned i;
522 /* save the current colorkey */ 523 /* save the current colorkey */
523 switch (info->chip.arch ) { 524 switch (info->chip.arch ) {
524 case NV_ARCH_10: 525 case NV_ARCH_10:
525 case NV_ARCH_20: 526 case NV_ARCH_20:
526 case NV_ARCH_30: 527 case NV_ARCH_30:
528 case NV_ARCH_40:
527 /* NV_PVIDEO_COLOR_KEY */ 529 /* NV_PVIDEO_COLOR_KEY */
528 info->colorkey = VID_RD32 (info->chip.PVIDEO, 0xB00); 530 info->colorkey = VID_RD32 (info->chip.PVIDEO, 0xB00);
529 break; 531 break;
530 case NV_ARCH_03: 532 case NV_ARCH_03:
531 case NV_ARCH_04: 533 case NV_ARCH_04:
543 /* Stop overlay video. */ 545 /* Stop overlay video. */
544 static void rivatv_overlay_stop (struct rivatv_info *info) { 546 static void rivatv_overlay_stop (struct rivatv_info *info) {
545 switch (info->chip.arch ) { 547 switch (info->chip.arch ) {
546 case NV_ARCH_10: 548 case NV_ARCH_10:
547 case NV_ARCH_20: 549 case NV_ARCH_20:
548 case NV_ARCH_30: 550 case NV_ARCH_30:
551 case NV_ARCH_40:
549 /* NV_PVIDEO_COLOR_KEY */ 552 /* NV_PVIDEO_COLOR_KEY */
550 /* Xv-Extension-Hack: Restore previously saved value. */ 553 /* Xv-Extension-Hack: Restore previously saved value. */
551 VID_WR32 (info->chip.PVIDEO, 0xB00, info->colorkey); 554 VID_WR32 (info->chip.PVIDEO, 0xB00, info->colorkey);
552 /* NV_PVIDEO_STOP */ 555 /* NV_PVIDEO_STOP */
553 VID_OR32 (info->chip.PVIDEO, 0x704, 0x11); 556 VID_OR32 (info->chip.PVIDEO, 0x704, 0x11);
622 //printf("[nvidia_vid] depth=%d %08X \n", info->depth, chromakey); 625 //printf("[nvidia_vid] depth=%d %08X \n", info->depth, chromakey);
623 switch (info->chip.arch) { 626 switch (info->chip.arch) {
624 case NV_ARCH_10: 627 case NV_ARCH_10:
625 case NV_ARCH_20: 628 case NV_ARCH_20:
626 case NV_ARCH_30: 629 case NV_ARCH_30:
630 case NV_ARCH_40:
627 VID_WR32 (info->chip.PVIDEO, 0xB00, key); 631 VID_WR32 (info->chip.PVIDEO, 0xB00, key);
628 break; 632 break;
629 case NV_ARCH_03: 633 case NV_ARCH_03:
630 case NV_ARCH_04: 634 case NV_ARCH_04:
631 VID_WR32 (info->chip.PVIDEO, 0x240, key); 635 VID_WR32 (info->chip.PVIDEO, 0x240, key);
714 718
715 switch (info->chip.arch) { 719 switch (info->chip.arch) {
716 case NV_ARCH_10: 720 case NV_ARCH_10:
717 case NV_ARCH_20: 721 case NV_ARCH_20:
718 case NV_ARCH_30: 722 case NV_ARCH_30:
723 case NV_ARCH_40:
719 724
720 /* NV_PVIDEO_BASE */ 725 /* NV_PVIDEO_BASE */
721 VID_WR32 (info->chip.PVIDEO, 0x900 + 0, base + offset); 726 VID_WR32 (info->chip.PVIDEO, 0x900 + 0, base + offset);
722 //VID_WR32 (info->chip.PVIDEO, 0x900 + 4, base); 727 //VID_WR32 (info->chip.PVIDEO, 0x900 + 4, base);
723 /* NV_PVIDEO_LIMIT */ 728 /* NV_PVIDEO_LIMIT */
724 VID_WR32 (info->chip.PVIDEO, 0x908 + 0, base + offset + size - 1); 729 VID_WR32 (info->chip.PVIDEO, 0x908 + 0, base + offset + size - 1);
725 //VID_WR32 (info->chip.PVIDEO, 0x908 + 4, base + size - 1); 730 //VID_WR32 (info->chip.PVIDEO, 0x908 + 4, base + size - 1);
726 731
727 /* extra code for NV20 && NV30 architectures */ 732 /* extra code for NV20 && NV30 architectures */
728 if (info->chip.arch == NV_ARCH_20 || info->chip.arch == NV_ARCH_30) { 733 if (info->chip.arch == NV_ARCH_20 || info->chip.arch == NV_ARCH_30 || info->chip.arch == NV_ARCH_40) {
729 VID_WR32 (info->chip.PVIDEO, 0x800 + 0, base + offset); 734 VID_WR32 (info->chip.PVIDEO, 0x800 + 0, base + offset);
730 //VID_WR32 (info->chip.PVIDEO, 0x800 + 4, base); 735 //VID_WR32 (info->chip.PVIDEO, 0x800 + 4, base);
731 VID_WR32 (info->chip.PVIDEO, 0x808 + 0, base + offset + size - 1); 736 VID_WR32 (info->chip.PVIDEO, 0x808 + 0, base + offset + size - 1);
732 //VID_WR32 (info->chip.PVIDEO, 0x808 + 4, base + size - 1); 737 //VID_WR32 (info->chip.PVIDEO, 0x808 + 4, base + size - 1);
733 } 738 }
884 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00680000); 889 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00680000);
885 break; 890 break;
886 case NV_ARCH_10: 891 case NV_ARCH_10:
887 case NV_ARCH_20: 892 case NV_ARCH_20:
888 case NV_ARCH_30: 893 case NV_ARCH_30:
894 case NV_ARCH_40:
889 info->chip.lock = rivatv_lock_nv04; 895 info->chip.lock = rivatv_lock_nv04;
890 info->chip.fbsize = rivatv_fbsize_nv10 (&info->chip); 896 info->chip.fbsize = rivatv_fbsize_nv10 (&info->chip);
891 info->chip.PRAMIN = (uint32_t *) (info->control_base + 0x00700000); 897 info->chip.PRAMIN = (uint32_t *) (info->control_base + 0x00700000);
892 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00008000); 898 info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00008000);
893 break; 899 break;
905 } 911 }
906 case NV_ARCH_04: 912 case NV_ARCH_04:
907 case NV_ARCH_10: 913 case NV_ARCH_10:
908 case NV_ARCH_20: 914 case NV_ARCH_20:
909 case NV_ARCH_30: 915 case NV_ARCH_30:
916 case NV_ARCH_40:
910 { 917 {
911 info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize); 918 info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize);
912 info->picture_offset = info->chip.fbsize - NV04_BES_SIZE; 919 info->picture_offset = info->chip.fbsize - NV04_BES_SIZE;
913 if(info->chip.fbsize > 16*1024*1024) 920 if(info->chip.fbsize > 16*1024*1024)
914 info->picture_offset -= NV04_BES_SIZE; 921 info->picture_offset -= NV04_BES_SIZE;