Mercurial > mplayer.hg
comparison vidix/savage_vid.c @ 22850:9a1e26fef45b
Move driver files directly into the vidix directory.
author | diego |
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date | Sun, 01 Apr 2007 00:02:43 +0000 |
parents | |
children | 77def5093daf |
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1 /* | |
2 Driver for S3 Savage Series | |
3 | |
4 Copyright (C) 2004 by Reza Jelveh | |
5 | |
6 Based on the X11 driver and nvidia vid | |
7 | |
8 Thanks to Alex Deucher for Support | |
9 | |
10 This program is free software; you can redistribute it and/or modify | |
11 it under the terms of the GNU General Public License as published by | |
12 the Free Software Foundation; either version 2 of the License, or | |
13 (at your option) any later version. | |
14 | |
15 This program is distributed in the hope that it will be useful, | |
16 but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 GNU General Public License for more details. | |
19 | |
20 You should have received a copy of the GNU General Public License | |
21 along with this program; if not, write to the Free Software | |
22 Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA | |
23 | |
24 Changes: | |
25 2004-11-09 | |
26 Initial version | |
27 | |
28 To Do: | |
29 | |
30 */ | |
31 | |
32 | |
33 #include <errno.h> | |
34 #include <stdio.h> | |
35 #include <stdlib.h> | |
36 #include <string.h> | |
37 #include <inttypes.h> | |
38 #include <unistd.h> | |
39 #include <math.h> | |
40 | |
41 #include "vidix.h" | |
42 #include "fourcc.h" | |
43 #include "../libdha/libdha.h" | |
44 #include "../libdha/pci_ids.h" | |
45 #include "../libdha/pci_names.h" | |
46 #include "../config.h" | |
47 | |
48 #include "savage_regs.h" | |
49 | |
50 | |
51 #define VF_STREAMS_ON 0x0001 | |
52 #define BASE_PAD 0xf | |
53 #define FRAMEBUFFER_SIZE 1024*2000*4 | |
54 /************************************** | |
55 S3 streams processor | |
56 **************************************/ | |
57 | |
58 #define EXT_MISC_CTRL2 0x67 | |
59 | |
60 /* New streams */ | |
61 | |
62 /* CR67[2] = 1 : enable stream 1 */ | |
63 #define ENABLE_STREAM1 0x04 | |
64 /* CR67[1] = 1 : enable stream 2 */ | |
65 #define ENABLE_STREAM2 0x02 | |
66 /* mask to clear CR67[2,1] */ | |
67 #define NO_STREAMS 0xF9 | |
68 /* CR67[3] = 1 : Mem-mapped regs */ | |
69 #define USE_MM_FOR_PRI_STREAM 0x08 | |
70 | |
71 #define HDM_SHIFT 16 | |
72 #define HDSCALE_4 (2 << HDM_SHIFT) | |
73 #define HDSCALE_8 (3 << HDM_SHIFT) | |
74 #define HDSCALE_16 (4 << HDM_SHIFT) | |
75 #define HDSCALE_32 (5 << HDM_SHIFT) | |
76 #define HDSCALE_64 (6 << HDM_SHIFT) | |
77 | |
78 /* Old Streams */ | |
79 | |
80 #define ENABLE_STREAMS_OLD 0x0c | |
81 #define NO_STREAMS_OLD 0xf3 | |
82 /* CR69[0] = 1 : Mem-mapped regs */ | |
83 #define USE_MM_FOR_PRI_STREAM_OLD 0x01 | |
84 | |
85 void SavageStreamsOn(void); | |
86 | |
87 /* | |
88 * There are two different streams engines used in the Savage line. | |
89 * The old engine is in the 3D, 4, Pro, and Twister. | |
90 * The new engine is in the 2000, MX, IX, and Super. | |
91 */ | |
92 | |
93 | |
94 /* streams registers for old engine */ | |
95 #define PSTREAM_CONTROL_REG 0x8180 | |
96 #define COL_CHROMA_KEY_CONTROL_REG 0x8184 | |
97 #define SSTREAM_CONTROL_REG 0x8190 | |
98 #define CHROMA_KEY_UPPER_BOUND_REG 0x8194 | |
99 #define SSTREAM_STRETCH_REG 0x8198 | |
100 #define COLOR_ADJUSTMENT_REG 0x819C | |
101 #define BLEND_CONTROL_REG 0x81A0 | |
102 #define PSTREAM_FBADDR0_REG 0x81C0 | |
103 #define PSTREAM_FBADDR1_REG 0x81C4 | |
104 #define PSTREAM_STRIDE_REG 0x81C8 | |
105 #define DOUBLE_BUFFER_REG 0x81CC | |
106 #define SSTREAM_FBADDR0_REG 0x81D0 | |
107 #define SSTREAM_FBADDR1_REG 0x81D4 | |
108 #define SSTREAM_STRIDE_REG 0x81D8 | |
109 #define SSTREAM_VSCALE_REG 0x81E0 | |
110 #define SSTREAM_VINITIAL_REG 0x81E4 | |
111 #define SSTREAM_LINES_REG 0x81E8 | |
112 #define STREAMS_FIFO_REG 0x81EC | |
113 #define PSTREAM_WINDOW_START_REG 0x81F0 | |
114 #define PSTREAM_WINDOW_SIZE_REG 0x81F4 | |
115 #define SSTREAM_WINDOW_START_REG 0x81F8 | |
116 #define SSTREAM_WINDOW_SIZE_REG 0x81FC | |
117 #define FIFO_CONTROL 0x8200 | |
118 #define PSTREAM_FBSIZE_REG 0x8300 | |
119 #define SSTREAM_FBSIZE_REG 0x8304 | |
120 #define SSTREAM_FBADDR2_REG 0x8308 | |
121 | |
122 #define OS_XY(x,y) (((x+1)<<16)|(y+1)) | |
123 #define OS_WH(x,y) (((x-1)<<16)|(y)) | |
124 | |
125 #define PCI_COMMAND_MEM 0x2 | |
126 #define MAX_FRAMES 3 | |
127 /** | |
128 * @brief Information on PCI device. | |
129 */ | |
130 pciinfo_t pci_info; | |
131 | |
132 /** | |
133 * @brief Unichrome driver colorkey settings. | |
134 */ | |
135 static vidix_grkey_t savage_grkey; | |
136 | |
137 static int frames[VID_PLAY_MAXFRAMES]; | |
138 uint8_t *vio; | |
139 uint8_t mclk_save[3]; | |
140 | |
141 #define outb(reg,val) OUTPORT8(reg,val) | |
142 #define inb(reg) INPORT8(reg) | |
143 #define outw(reg,val) OUTPORT16(reg,val) | |
144 #define inw(reg) INPORT16(reg) | |
145 #define outl(reg,val) OUTPORT32(reg,val) | |
146 #define inl(reg) INPORT32(reg) | |
147 | |
148 | |
149 /* | |
150 * PCI-Memory IO access macros. | |
151 */ | |
152 #define VID_WR08(p,i,val) (((uint8_t *)(p))[(i)]=(val)) | |
153 #define VID_RD08(p,i) (((uint8_t *)(p))[(i)]) | |
154 | |
155 #define VID_WR32(p,i,val) (((uint32_t *)(p))[(i)/4]=(val)) | |
156 #define VID_RD32(p,i) (((uint32_t *)(p))[(i)/4]) | |
157 | |
158 #ifndef USE_RMW_CYCLES | |
159 /* | |
160 * Can be used to inhibit READ-MODIFY-WRITE cycles. On by default. | |
161 */ | |
162 | |
163 #define MEM_BARRIER() __asm__ __volatile__ ("" : : : "memory") | |
164 | |
165 #undef VID_WR08 | |
166 #define VID_WR08(p,i,val) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]=(val); }) | |
167 #undef VID_RD08 | |
168 #define VID_RD08(p,i) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]; }) | |
169 | |
170 #undef VID_WR16 | |
171 #define VID_WR16(p,i,val) ({ MEM_BARRIER(); ((uint16_t *)(p))[(i)/2]=(val); }) | |
172 #undef VID_RD16 | |
173 #define VID_RD16(p,i) ({ MEM_BARRIER(); ((uint16_t *)(p))[(i)/2]; }) | |
174 | |
175 #undef VID_WR32 | |
176 #define VID_WR32(p,i,val) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]=(val); }) | |
177 #undef VID_RD32 | |
178 #define VID_RD32(p,i) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]; }) | |
179 #endif /* USE_RMW_CYCLES */ | |
180 | |
181 #define VID_AND32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)&(val)) | |
182 #define VID_OR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)|(val)) | |
183 #define VID_XOR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)^(val)) | |
184 | |
185 | |
186 /* from x driver */ | |
187 | |
188 #define VGAIN8(addr) VID_RD08(info->control_base+0x8000, addr) | |
189 #define VGAIN16(addr) VID_RD16(info->control_base+0x8000, addr) | |
190 #define VGAIN(addr) VID_RD32(info->control_base+0x8000, addr) | |
191 | |
192 #define VGAOUT8(addr,val) VID_WR08(info->control_base+0x8000, addr, val) | |
193 #define VGAOUT16(addr,val) VID_WR16(info->control_base+0x8000, addr, val) | |
194 #define VGAOUT(addr,val) VID_WR32(info->control_base+0x8000, addr, val) | |
195 | |
196 #define INREG(addr) VID_RD32(info->control_base, addr) | |
197 #define OUTREG(addr,val) VID_WR32(info->control_base, addr, val) | |
198 #define INREG8(addr) VID_RD08(info->control_base, addr) | |
199 #define OUTREG8(addr,val) VID_WR08(info->control_base, addr, val) | |
200 #define INREG16(addr) VID_RD16(info->control_base, addr) | |
201 #define OUTREG16(addr,val) VID_WR16(info->control_base, addr, val) | |
202 | |
203 #define ALIGN_TO(v, n) (((v) + (n-1)) & ~(n-1)) | |
204 | |
205 | |
206 void debugout(unsigned int addr, unsigned int val); | |
207 | |
208 | |
209 struct savage_chip { | |
210 volatile uint32_t *PMC; /* general control */ | |
211 volatile uint32_t *PME; /* multimedia port */ | |
212 volatile uint32_t *PFB; /* framebuffer control */ | |
213 volatile uint32_t *PVIDEO; /* overlay control */ | |
214 volatile uint8_t *PCIO; /* SVGA (CRTC, ATTR) registers */ | |
215 volatile uint8_t *PVIO; /* SVGA (MISC, GRAPH, SEQ) registers */ | |
216 volatile uint32_t *PRAMIN; /* instance memory */ | |
217 volatile uint32_t *PRAMHT; /* hash table */ | |
218 volatile uint32_t *PRAMFC; /* fifo context table */ | |
219 volatile uint32_t *PRAMRO; /* fifo runout table */ | |
220 volatile uint32_t *PFIFO; /* fifo control region */ | |
221 volatile uint32_t *FIFO; /* fifo channels (USER) */ | |
222 volatile uint32_t *PGRAPH; /* graphics engine */ | |
223 | |
224 int arch; /* compatible NV_ARCH_XX define */ | |
225 unsigned long fbsize; /* framebuffer size */ | |
226 void (* lock) (struct savage_chip *, int); | |
227 }; | |
228 typedef struct savage_chip savage_chip; | |
229 | |
230 | |
231 struct savage_info { | |
232 unsigned int use_colorkey; | |
233 unsigned int colorkey; /* saved xv colorkey*/ | |
234 unsigned int vidixcolorkey; /*currently used colorkey*/ | |
235 unsigned int depth; | |
236 unsigned int bpp; | |
237 unsigned int videoFlags; | |
238 unsigned int format; | |
239 unsigned int pitch; | |
240 unsigned int blendBase; | |
241 unsigned int lastKnownPitch; | |
242 unsigned int displayWidth, displayHeight; | |
243 unsigned int brightness,hue,saturation,contrast; | |
244 unsigned int src_w,src_h; | |
245 unsigned int drw_w,drw_h; /*scaled width && height*/ | |
246 unsigned int wx,wy; /*window x && y*/ | |
247 unsigned int screen_x; /*screen width*/ | |
248 unsigned int screen_y; /*screen height*/ | |
249 unsigned long buffer_size; /* size of the image buffer */ | |
250 struct savage_chip chip; /* NV architecture structure */ | |
251 void* video_base; /* virtual address of control region */ | |
252 void* control_base; /* virtual address of fb region */ | |
253 unsigned long picture_base; /* direct pointer to video picture */ | |
254 unsigned long picture_offset; /* offset of video picture in frame buffer */ | |
255 // struct savage_dma dma; /* DMA structure */ | |
256 unsigned int cur_frame; | |
257 unsigned int num_frames; /* number of buffers */ | |
258 int bps; /* bytes per line */ | |
259 void (*SavageWaitIdle) (); | |
260 void (*SavageWaitFifo) (int space); | |
261 }; | |
262 typedef struct savage_info savage_info; | |
263 | |
264 | |
265 static savage_info* info; | |
266 | |
267 | |
268 /** | |
269 * @brief Unichrome driver vidix capabilities. | |
270 */ | |
271 static vidix_capability_t savage_cap = { | |
272 "Savage/ProSavage/Twister vidix", | |
273 "Reza Jelveh <reza.jelveh@tuhh.de>", | |
274 TYPE_OUTPUT, | |
275 {0, 0, 0, 0}, | |
276 4096, | |
277 4096, | |
278 4, | |
279 4, | |
280 -1, | |
281 FLAG_UPSCALER | FLAG_DOWNSCALER, | |
282 VENDOR_S3_INC, | |
283 -1, | |
284 {0, 0, 0, 0} | |
285 }; | |
286 | |
287 struct savage_cards { | |
288 unsigned short chip_id; | |
289 unsigned short arch; | |
290 }; | |
291 | |
292 | |
293 static | |
294 unsigned int GetBlendForFourCC( int id ) | |
295 { | |
296 switch( id ) { | |
297 case IMGFMT_YUY2: | |
298 case IMGFMT_YV12: | |
299 case IMGFMT_I420: | |
300 return 1; | |
301 case IMGFMT_Y211: | |
302 return 4; | |
303 case IMGFMT_RGB15: | |
304 return 3; | |
305 case IMGFMT_RGB16: | |
306 return 5; | |
307 default: | |
308 return 0; | |
309 } | |
310 } | |
311 | |
312 /** | |
313 * @brief list of card IDs compliant with the Unichrome driver . | |
314 */ | |
315 static struct savage_cards savage_card_ids[] = { | |
316 /*[ProSavage PN133] AGP4X VGA Controller (Twister)*/ | |
317 { PCI_CHIP_S3TWISTER_P, S3_PROSAVAGE }, | |
318 /*[ProSavage KN133] AGP4X VGA Controller (TwisterK)*/ | |
319 { PCI_CHIP_S3TWISTER_K, S3_PROSAVAGE }, | |
320 /*ProSavage DDR*/ | |
321 { PCI_CHIP_PROSAVAGE_DDR , S3_PROSAVAGE }, | |
322 /*[ProSavageDDR P4M266 K] */ | |
323 { PCI_CHIP_PROSAVAGE_DDRK , S3_PROSAVAGE }, | |
324 }; | |
325 | |
326 static void SavageSetColorOld(void) | |
327 { | |
328 | |
329 | |
330 if( | |
331 (info->format == IMGFMT_RGB15) || | |
332 (info->format == IMGFMT_RGB16) | |
333 ) | |
334 { | |
335 OUTREG( COLOR_ADJUSTMENT_REG, 0 ); | |
336 } | |
337 else | |
338 { | |
339 /* Change 0..255 into 0..15 */ | |
340 long sat = info->saturation * 16 / 256; | |
341 double hue = info->hue * 0.017453292; | |
342 unsigned long hs1 = ((long)(sat * cos(hue))) & 0x1f; | |
343 unsigned long hs2 = ((long)(sat * sin(hue))) & 0x1f; | |
344 | |
345 OUTREG( COLOR_ADJUSTMENT_REG, | |
346 0x80008000 | | |
347 (info->brightness + 128) | | |
348 ((info->contrast & 0xf8) << (12-7)) | | |
349 (hs1 << 16) | | |
350 (hs2 << 24) | |
351 ); | |
352 debugout( COLOR_ADJUSTMENT_REG, | |
353 0x80008000 | | |
354 (info->brightness + 128) | | |
355 ((info->contrast & 0xf8) << (12-7)) | | |
356 (hs1 << 16) | | |
357 (hs2 << 24) | |
358 ); | |
359 | |
360 } | |
361 } | |
362 | |
363 static void SavageSetColorKeyOld(void) | |
364 { | |
365 int red, green, blue; | |
366 | |
367 /* Here, we reset the colorkey and all the controls. */ | |
368 | |
369 red = (info->vidixcolorkey & 0x00FF0000) >> 16; | |
370 green = (info->vidixcolorkey & 0x0000FF00) >> 8; | |
371 blue = info->vidixcolorkey & 0x000000FF; | |
372 | |
373 if( !info->vidixcolorkey ) { | |
374 printf("SavageSetColorKey disabling colorkey\n"); | |
375 OUTREG( COL_CHROMA_KEY_CONTROL_REG, 0 ); | |
376 OUTREG( CHROMA_KEY_UPPER_BOUND_REG, 0 ); | |
377 OUTREG( BLEND_CONTROL_REG, 0 ); | |
378 } | |
379 else { | |
380 switch (info->depth) { | |
381 // FIXME: isnt fixed yet | |
382 case 8: | |
383 OUTREG( COL_CHROMA_KEY_CONTROL_REG, | |
384 0x37000000 | (info->vidixcolorkey & 0xFF) ); | |
385 OUTREG( CHROMA_KEY_UPPER_BOUND_REG, | |
386 0x00000000 | (info->vidixcolorkey & 0xFF) ); | |
387 break; | |
388 case 15: | |
389 /* 15 bpp 555 */ | |
390 red&=0x1f; | |
391 green&=0x1f; | |
392 blue&=0x1f; | |
393 OUTREG( COL_CHROMA_KEY_CONTROL_REG, | |
394 0x05000000 | (red<<19) | (green<<11) | (blue<<3) ); | |
395 OUTREG( CHROMA_KEY_UPPER_BOUND_REG, | |
396 0x00000000 | (red<<19) | (green<<11) | (blue<<3) ); | |
397 break; | |
398 case 16: | |
399 /* 16 bpp 565 */ | |
400 red&=0x1f; | |
401 green&=0x3f; | |
402 blue&=0x1f; | |
403 OUTREG( COL_CHROMA_KEY_CONTROL_REG, | |
404 0x16000000 | (red<<19) | (green<<10) | (blue<<3) ); | |
405 OUTREG( CHROMA_KEY_UPPER_BOUND_REG, | |
406 0x00020002 | (red<<19) | (green<<10) | (blue<<3) ); | |
407 break; | |
408 case 24: | |
409 /* 24 bpp 888 */ | |
410 OUTREG( COL_CHROMA_KEY_CONTROL_REG, | |
411 0x17000000 | (red<<16) | (green<<8) | (blue) ); | |
412 OUTREG( CHROMA_KEY_UPPER_BOUND_REG, | |
413 0x00000000 | (red<<16) | (green<<8) | (blue) ); | |
414 break; | |
415 } | |
416 | |
417 /* We use destination colorkey */ | |
418 OUTREG( BLEND_CONTROL_REG, 0x05000000 ); | |
419 } | |
420 } | |
421 | |
422 | |
423 static void | |
424 SavageDisplayVideoOld(void) | |
425 { | |
426 int vgaCRIndex, vgaCRReg, vgaIOBase; | |
427 unsigned int ssControl; | |
428 int cr92; | |
429 | |
430 | |
431 vgaIOBase = 0x3d0; | |
432 vgaCRIndex = vgaIOBase + 4; | |
433 vgaCRReg = vgaIOBase + 5; | |
434 | |
435 // if( psav->videoFourCC != id ) | |
436 // SavageStreamsOff(pScrn); | |
437 | |
438 if( !info->videoFlags & VF_STREAMS_ON ) | |
439 { | |
440 SavageStreamsOn(); | |
441 // SavageResetVideo(); | |
442 SavageSetColorOld(); | |
443 SavageSetColorKeyOld(); | |
444 } | |
445 | |
446 | |
447 | |
448 | |
449 /* Set surface format. */ | |
450 | |
451 OUTREG(SSTREAM_CONTROL_REG,GetBlendForFourCC(info->format) << 24 | info->src_w); | |
452 | |
453 debugout(SSTREAM_CONTROL_REG,GetBlendForFourCC(info->format) << 24 | info->src_w); | |
454 | |
455 /* Calculate horizontal scale factor. */ | |
456 | |
457 //FIXME: enable scaling | |
458 OUTREG(SSTREAM_STRETCH_REG, (info->src_w << 15) / info->drw_w ); | |
459 // debugout(SSTREAM_STRETCH_REG, 1 << 15); | |
460 | |
461 OUTREG(SSTREAM_LINES_REG, info->src_h ); | |
462 debugout(SSTREAM_LINES_REG, info->src_h ); | |
463 | |
464 | |
465 OUTREG(SSTREAM_VINITIAL_REG, 0 ); | |
466 debugout(SSTREAM_VINITIAL_REG, 0 ); | |
467 /* Calculate vertical scale factor. */ | |
468 | |
469 // OUTREG(SSTREAM_VSCALE_REG, 1 << 15); | |
470 OUTREG(SSTREAM_VSCALE_REG, VSCALING(info->src_h,info->drw_h) ); | |
471 debugout(SSTREAM_VSCALE_REG, VSCALING(info->src_h,info->drw_h) ); | |
472 // OUTREG(SSTREAM_VSCALE_REG, (info->src_h << 15) / info->drw_h ); | |
473 | |
474 /* Set surface location and stride. */ | |
475 | |
476 OUTREG(SSTREAM_FBADDR0_REG, info->picture_offset ); | |
477 debugout(SSTREAM_FBADDR0_REG, info->picture_offset ); | |
478 | |
479 OUTREG(SSTREAM_FBADDR1_REG, 0 ); | |
480 debugout(SSTREAM_FBADDR1_REG, 0 ); | |
481 | |
482 OUTREG(SSTREAM_STRIDE_REG, info->pitch ); | |
483 debugout(SSTREAM_STRIDE_REG, info->pitch ); | |
484 | |
485 OUTREG(SSTREAM_WINDOW_START_REG, OS_XY(info->wx, info->wy) ); | |
486 debugout(SSTREAM_WINDOW_START_REG, OS_XY(info->wx, info->wy) ); | |
487 OUTREG(SSTREAM_WINDOW_SIZE_REG, OS_WH(info->drw_w, info->drw_h) ); | |
488 debugout(SSTREAM_WINDOW_SIZE_REG, OS_WH(info->drw_w, info->drw_h) ); | |
489 | |
490 | |
491 | |
492 ssControl = 0; | |
493 | |
494 if( info->src_w > (info->drw_w << 1) ) | |
495 { | |
496 /* BUGBUG shouldn't this be >=? */ | |
497 if( info->src_w <= (info->drw_w << 2) ) | |
498 ssControl |= HDSCALE_4; | |
499 else if( info->src_w > (info->drw_w << 3) ) | |
500 ssControl |= HDSCALE_8; | |
501 else if( info->src_w > (info->drw_w << 4) ) | |
502 ssControl |= HDSCALE_16; | |
503 else if( info->src_w > (info->drw_w << 5) ) | |
504 ssControl |= HDSCALE_32; | |
505 else if( info->src_w > (info->drw_w << 6) ) | |
506 ssControl |= HDSCALE_64; | |
507 } | |
508 | |
509 ssControl |= info->src_w; | |
510 ssControl |= (1 << 24); | |
511 | |
512 //FIXME: enable scaling | |
513 OUTREG(SSTREAM_CONTROL_REG, ssControl); | |
514 debugout(SSTREAM_CONTROL_REG, ssControl); | |
515 | |
516 // FIXME: this should actually be enabled | |
517 | |
518 info->pitch = (info->pitch + 7) / 8; | |
519 VGAOUT8(vgaCRIndex, 0x92); | |
520 cr92 = VGAIN8(vgaCRReg); | |
521 VGAOUT8(vgaCRReg, (cr92 & 0x40) | (info->pitch >> 8) | 0x80); | |
522 VGAOUT8(vgaCRIndex, 0x93); | |
523 VGAOUT8(vgaCRReg, info->pitch); | |
524 OUTREG(STREAMS_FIFO_REG, 2 | 25 << 5 | 32 << 11); | |
525 | |
526 | |
527 | |
528 | |
529 } | |
530 | |
531 static void SavageInitStreamsOld(void) | |
532 { | |
533 /*unsigned long jDelta;*/ | |
534 unsigned long format = 0; | |
535 | |
536 /* | |
537 * For the OLD streams engine, several of these registers | |
538 * cannot be touched unless streams are on. Seems backwards to me; | |
539 * I'd want to set 'em up, then cut 'em loose. | |
540 */ | |
541 | |
542 | |
543 /*jDelta = pScrn->displayWidth * (pScrn->bitsPerPixel + 7) / 8;*/ | |
544 switch( info->depth ) { | |
545 case 8: format = 0 << 24; break; | |
546 case 15: format = 3 << 24; break; | |
547 case 16: format = 5 << 24; break; | |
548 case 24: format = 7 << 24; break; | |
549 } | |
550 #warning enable this again | |
551 OUTREG(PSTREAM_FBSIZE_REG, | |
552 info->screen_y * info->screen_x * (info->bpp >> 3)); | |
553 | |
554 OUTREG( PSTREAM_WINDOW_START_REG, OS_XY(0,0) ); | |
555 OUTREG( PSTREAM_WINDOW_SIZE_REG, OS_WH(info->screen_x, info->screen_y) ); | |
556 OUTREG( PSTREAM_FBADDR1_REG, 0 ); | |
557 /*OUTREG( PSTREAM_STRIDE_REG, jDelta );*/ | |
558 OUTREG( PSTREAM_CONTROL_REG, format ); | |
559 OUTREG( PSTREAM_FBADDR0_REG, 0 ); | |
560 | |
561 /*OUTREG( PSTREAM_FBSIZE_REG, jDelta * pScrn->virtualY >> 3 );*/ | |
562 | |
563 OUTREG( COL_CHROMA_KEY_CONTROL_REG, 0 ); | |
564 OUTREG( SSTREAM_CONTROL_REG, 0 ); | |
565 OUTREG( CHROMA_KEY_UPPER_BOUND_REG, 0 ); | |
566 OUTREG( SSTREAM_STRETCH_REG, 0 ); | |
567 OUTREG( COLOR_ADJUSTMENT_REG, 0 ); | |
568 OUTREG( BLEND_CONTROL_REG, 1 << 24 ); | |
569 OUTREG( DOUBLE_BUFFER_REG, 0 ); | |
570 OUTREG( SSTREAM_FBADDR0_REG, 0 ); | |
571 OUTREG( SSTREAM_FBADDR1_REG, 0 ); | |
572 OUTREG( SSTREAM_FBADDR2_REG, 0 ); | |
573 OUTREG( SSTREAM_FBSIZE_REG, 0 ); | |
574 OUTREG( SSTREAM_STRIDE_REG, 0 ); | |
575 OUTREG( SSTREAM_VSCALE_REG, 0 ); | |
576 OUTREG( SSTREAM_LINES_REG, 0 ); | |
577 OUTREG( SSTREAM_VINITIAL_REG, 0 ); | |
578 #warning is this needed? | |
579 OUTREG( SSTREAM_WINDOW_START_REG, OS_XY(0xfffe, 0xfffe) ); | |
580 OUTREG( SSTREAM_WINDOW_SIZE_REG, OS_WH(10,2) ); | |
581 | |
582 } | |
583 | |
584 void | |
585 SavageStreamsOn(void) | |
586 { | |
587 unsigned char jStreamsControl; | |
588 unsigned short vgaCRIndex = 0x3d0 + 4; | |
589 unsigned short vgaCRReg = 0x3d0 + 5; | |
590 | |
591 // xf86ErrorFVerb(STREAMS_TRACE, "SavageStreamsOn\n" ); | |
592 | |
593 /* Sequence stolen from streams.c in M7 NT driver */ | |
594 | |
595 | |
596 enable_app_io (); | |
597 | |
598 /* Unlock extended registers. */ | |
599 | |
600 /* FIXME: it looks like mmaped io is broken with vgaout16 */ | |
601 VGAOUT16(vgaCRIndex, 0x4838 ); | |
602 VGAOUT16(vgaCRIndex, 0xa039); | |
603 VGAOUT16(0x3c4, 0x0608); | |
604 | |
605 | |
606 | |
607 VGAOUT8( vgaCRIndex, EXT_MISC_CTRL2 ); | |
608 | |
609 if( S3_SAVAGE_MOBILE_SERIES(info->chip.arch) ) | |
610 { | |
611 // SavageInitStreamsNew( pScrn ); | |
612 | |
613 jStreamsControl = VGAIN8( vgaCRReg ) | ENABLE_STREAM1; | |
614 | |
615 /* Wait for VBLANK. */ | |
616 VerticalRetraceWait(); | |
617 /* Fire up streams! */ | |
618 VGAOUT16( vgaCRIndex, (jStreamsControl << 8) | EXT_MISC_CTRL2 ); | |
619 /* These values specify brightness, contrast, saturation and hue. */ | |
620 OUTREG( SEC_STREAM_COLOR_CONVERT1, 0x0000C892 ); | |
621 OUTREG( SEC_STREAM_COLOR_CONVERT2, 0x00039F9A ); | |
622 OUTREG( SEC_STREAM_COLOR_CONVERT3, 0x01F1547E ); | |
623 } | |
624 else if (info->chip.arch == S3_SAVAGE2000) | |
625 { | |
626 // SavageInitStreams2000( pScrn ); | |
627 | |
628 jStreamsControl = VGAIN8( vgaCRReg ) | ENABLE_STREAM1; | |
629 | |
630 /* Wait for VBLANK. */ | |
631 VerticalRetraceWait(); | |
632 /* Fire up streams! */ | |
633 VGAOUT16( vgaCRIndex, (jStreamsControl << 8) | EXT_MISC_CTRL2 ); | |
634 /* These values specify brightness, contrast, saturation and hue. */ | |
635 OUTREG( SEC_STREAM_COLOR_CONVERT0_2000, 0x0000C892 ); | |
636 OUTREG( SEC_STREAM_COLOR_CONVERT1_2000, 0x00033400 ); | |
637 OUTREG( SEC_STREAM_COLOR_CONVERT2_2000, 0x000001CF ); | |
638 OUTREG( SEC_STREAM_COLOR_CONVERT3_2000, 0x01F1547E ); | |
639 } | |
640 else | |
641 { | |
642 jStreamsControl = VGAIN8( vgaCRReg ) | ENABLE_STREAMS_OLD; | |
643 | |
644 /* Wait for VBLANK. */ | |
645 | |
646 VerticalRetraceWait(); | |
647 | |
648 /* Fire up streams! */ | |
649 | |
650 VGAOUT16( vgaCRIndex, (jStreamsControl << 8) | EXT_MISC_CTRL2 ); | |
651 | |
652 SavageInitStreamsOld( ); | |
653 } | |
654 | |
655 /* Wait for VBLANK. */ | |
656 | |
657 VerticalRetraceWait(); | |
658 | |
659 /* Turn on secondary stream TV flicker filter, once we support TV. */ | |
660 | |
661 /* SR70 |= 0x10 */ | |
662 | |
663 info->videoFlags |= VF_STREAMS_ON; | |
664 | |
665 } | |
666 | |
667 | |
668 | |
669 | |
670 static void savage_getscreenproperties(struct savage_info *info){ | |
671 unsigned char bpp=0; | |
672 uint32_t width=0; | |
673 | |
674 uint32_t vgaIOBase, vgaCRIndex, vgaCRReg; | |
675 | |
676 vgaIOBase = 0x3d0; | |
677 vgaCRIndex = vgaIOBase + 4; | |
678 vgaCRReg = vgaIOBase + 5; | |
679 | |
680 | |
681 /* a little reversed from x driver source code */ | |
682 VGAOUT8(vgaCRIndex, 0x67); | |
683 bpp = VGAIN8(vgaCRReg); | |
684 | |
685 | |
686 switch (bpp&0xf0) { | |
687 case 0x00: | |
688 case 0x10: | |
689 info->depth=8; | |
690 info->bpp=8; | |
691 break; | |
692 case 0x20: | |
693 case 0x30: | |
694 info->depth=15; | |
695 info->bpp=16; | |
696 break; | |
697 case 0x40: | |
698 case 0x50: | |
699 info->depth=16; | |
700 info->bpp=16; | |
701 break; | |
702 case 0x70: | |
703 case 0xd0: | |
704 info->depth=24; | |
705 info->bpp=32; | |
706 break; | |
707 | |
708 | |
709 } | |
710 | |
711 | |
712 VGAOUT8(vgaCRIndex, 0x1); | |
713 info->screen_x = (1 + VGAIN8(vgaCRReg)) <<3; | |
714 /*get screen height*/ | |
715 /* get first 8 bits in VT_DISPLAY_END*/ | |
716 VGAOUT8(0x03D4, 0x12); | |
717 info->screen_y = VGAIN8(0x03D5); | |
718 VGAOUT8(0x03D4,0x07); | |
719 /* get 9th bit in CRTC_OVERFLOW*/ | |
720 info->screen_y |= (VGAIN8(0x03D5) &0x02)<<7; | |
721 /* and the 10th in CRTC_OVERFLOW*/ | |
722 info->screen_y |=(VGAIN8(0x03D5) &0x40)<<3; | |
723 ++info->screen_y; | |
724 | |
725 printf("screen_x = %d, screen_y = %d, bpp = %d\n",info->screen_x,info->screen_y,info->bpp); | |
726 } | |
727 | |
728 | |
729 static void SavageStreamsOff(void) | |
730 { | |
731 unsigned char jStreamsControl; | |
732 unsigned short vgaCRIndex = 0x3d0 + 4; | |
733 unsigned short vgaCRReg = 0x3d0 + 5; | |
734 | |
735 | |
736 /* Unlock extended registers. */ | |
737 | |
738 VGAOUT16(vgaCRIndex, 0x4838); | |
739 VGAOUT16(vgaCRIndex, 0xa039); | |
740 VGAOUT16(0x3c4, 0x0608); | |
741 | |
742 VGAOUT8( vgaCRIndex, EXT_MISC_CTRL2 ); | |
743 if( S3_SAVAGE_MOBILE_SERIES(info->chip.arch) || | |
744 (info->chip.arch == S3_SUPERSAVAGE) || | |
745 (info->chip.arch == S3_SAVAGE2000) ) | |
746 jStreamsControl = VGAIN8( vgaCRReg ) & NO_STREAMS; | |
747 else | |
748 jStreamsControl = VGAIN8( vgaCRReg ) & NO_STREAMS_OLD; | |
749 | |
750 /* Wait for VBLANK. */ | |
751 | |
752 VerticalRetraceWait(); | |
753 | |
754 /* Kill streams. */ | |
755 | |
756 VGAOUT16(vgaCRIndex, (jStreamsControl << 8) | EXT_MISC_CTRL2 ); | |
757 | |
758 VGAOUT16(vgaCRIndex, 0x0093 ); | |
759 VGAOUT8( vgaCRIndex, 0x92 ); | |
760 VGAOUT8( vgaCRReg, VGAIN8(vgaCRReg) & 0x40 ); | |
761 | |
762 info->videoFlags &= ~VF_STREAMS_ON; | |
763 } | |
764 | |
765 | |
766 /** | |
767 * @brief Check age of driver. | |
768 * | |
769 * @return vidix version number. | |
770 */ | |
771 unsigned int | |
772 vixGetVersion (void) | |
773 { | |
774 return (VIDIX_VERSION); | |
775 } | |
776 | |
777 /** | |
778 * @brief Find chip index in Unichrome compliant devices list. | |
779 * | |
780 * @param chip_id PCI device ID. | |
781 * | |
782 * @returns index position in savage_card_ids if successful. | |
783 * -1 if chip_id is not a compliant chipset ID. | |
784 */ | |
785 | |
786 static int find_chip(unsigned chip_id){ | |
787 unsigned i; | |
788 for(i = 0;i < sizeof(savage_card_ids)/sizeof(struct savage_cards);i++) | |
789 { | |
790 if(chip_id == savage_card_ids[i].chip_id)return i; | |
791 } | |
792 return -1; | |
793 } | |
794 | |
795 /** | |
796 * @brief Probe hardware to find some useable chipset. | |
797 * | |
798 * @param verbose specifies verbose level. | |
799 * @param force specifies force mode : driver should ignore | |
800 * device_id (danger but useful for new devices) | |
801 * | |
802 * @returns 0 if it can handle something in PC. | |
803 * a negative error code otherwise. | |
804 */ | |
805 | |
806 int vixProbe(int verbose, int force){ | |
807 pciinfo_t lst[MAX_PCI_DEVICES]; | |
808 unsigned i,num_pci; | |
809 int err; | |
810 | |
811 if (force) | |
812 printf("[savage_vid]: warning: forcing not supported yet!\n"); | |
813 err = pci_scan(lst,&num_pci); | |
814 if(err){ | |
815 printf("[savage_vid] Error occurred during pci scan: %s\n",strerror(err)); | |
816 return err; | |
817 } | |
818 else { | |
819 err = ENXIO; | |
820 for(i=0; i < num_pci; i++){ | |
821 if(lst[i].vendor == VENDOR_S3_INC) { | |
822 int idx; | |
823 const char *dname; | |
824 idx = find_chip(lst[i].device); | |
825 if(idx == -1) | |
826 continue; | |
827 dname = pci_device_name(lst[i].vendor, lst[i].device); | |
828 dname = dname ? dname : "Unknown chip"; | |
829 printf("[savage_vid] Found chip: %s\n", dname); | |
830 // FIXME: whats wrong here? | |
831 if ((lst[i].command & PCI_COMMAND_IO ) == 0){ | |
832 printf("[savage_vid] Device is disabled, ignoring\n"); | |
833 continue; | |
834 } | |
835 savage_cap.device_id = lst[i].device; | |
836 err = 0; | |
837 memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); | |
838 break; | |
839 } | |
840 } | |
841 } | |
842 if(err && verbose) printf("[savage_vid] Can't find chip\n"); | |
843 return err; | |
844 } | |
845 | |
846 /** | |
847 * @brief Initializes driver. | |
848 * | |
849 * @returns 0 if ok. | |
850 * a negative error code otherwise. | |
851 */ | |
852 int | |
853 vixInit (void) | |
854 { | |
855 int mtrr; | |
856 unsigned char config1, m, n, n1, n2, sr8, cr3f, cr66 = 0, tmp; | |
857 | |
858 static unsigned char RamSavage3D[] = { 8, 4, 4, 2 }; | |
859 static unsigned char RamSavage4[] = { 2, 4, 8, 12, 16, 32, 64, 32 }; | |
860 static unsigned char RamSavageMX[] = { 2, 8, 4, 16, 8, 16, 4, 16 }; | |
861 static unsigned char RamSavageNB[] = { 0, 2, 4, 8, 16, 32, 16, 2 }; | |
862 | |
863 int videoRam, videoRambytes; | |
864 | |
865 uint32_t vgaIOBase, vgaCRIndex, vgaCRReg ; | |
866 | |
867 unsigned char val; | |
868 | |
869 vgaIOBase = 0x3d0; | |
870 vgaCRIndex = vgaIOBase + 4; | |
871 vgaCRReg = vgaIOBase + 5; | |
872 | |
873 fprintf(stderr, "vixInit enter \n"); | |
874 // //getc(stdin); | |
875 | |
876 info = calloc(1,sizeof(savage_info)); | |
877 | |
878 | |
879 /* need this if we want direct outb and inb access? */ | |
880 enable_app_io (); | |
881 | |
882 /* 12mb + 32kb ? */ | |
883 /* allocate some space for control registers */ | |
884 info->chip.arch = savage_card_ids[find_chip(pci_info.device)].arch; | |
885 | |
886 if (info->chip.arch == S3_SAVAGE3D) { | |
887 info->control_base = map_phys_mem(pci_info.base0+SAVAGE_NEWMMIO_REGBASE_S3, SAVAGE_NEWMMIO_REGSIZE); | |
888 } | |
889 else { | |
890 info->control_base = map_phys_mem(pci_info.base0+SAVAGE_NEWMMIO_REGBASE_S4, SAVAGE_NEWMMIO_REGSIZE); | |
891 } | |
892 | |
893 // info->chip.PCIO = (uint8_t *) (info->control_base + SAVAGE_NEWMMIO_VGABASE); | |
894 | |
895 // FIXME: enable mmio? | |
896 val = VGAIN8 (0x3c3); | |
897 VGAOUT8 (0x3c3, val | 0x01); | |
898 val = VGAIN8 (0x3cc); | |
899 VGAOUT8 (0x3c2, val | 0x01); | |
900 | |
901 if (info->chip.arch >= S3_SAVAGE4) | |
902 { | |
903 VGAOUT8 (0x3d4, 0x40); | |
904 val = VGAIN8 (0x3d5); | |
905 VGAOUT8 (0x3d5, val | 1); | |
906 } | |
907 | |
908 | |
909 | |
910 /* unprotect CRTC[0-7] */ | |
911 VGAOUT8(vgaCRIndex, 0x11); | |
912 tmp = VGAIN8(vgaCRReg); | |
913 // printf("$########## tmp = %d\n",tmp); | |
914 VGAOUT8(vgaCRReg, tmp & 0x7f); | |
915 | |
916 | |
917 /* unlock extended regs */ | |
918 VGAOUT16(vgaCRIndex, 0x4838); | |
919 VGAOUT16(vgaCRIndex, 0xa039); | |
920 VGAOUT16(0x3c4, 0x0608); | |
921 | |
922 VGAOUT8(vgaCRIndex, 0x40); | |
923 tmp = VGAIN8(vgaCRReg); | |
924 VGAOUT8(vgaCRReg, tmp & ~0x01); | |
925 | |
926 /* unlock sys regs */ | |
927 VGAOUT8(vgaCRIndex, 0x38); | |
928 VGAOUT8(vgaCRReg, 0x48); | |
929 | |
930 /* Unlock system registers. */ | |
931 VGAOUT16(vgaCRIndex, 0x4838); | |
932 | |
933 /* Next go on to detect amount of installed ram */ | |
934 | |
935 VGAOUT8(vgaCRIndex, 0x36); /* for register CR36 (CONFG_REG1), */ | |
936 config1 = VGAIN8(vgaCRReg); /* get amount of vram installed */ | |
937 | |
938 | |
939 switch( info->chip.arch ) { | |
940 case S3_SAVAGE3D: | |
941 videoRam = RamSavage3D[ (config1 & 0xC0) >> 6 ] * 1024; | |
942 break; | |
943 | |
944 case S3_SAVAGE4: | |
945 /* | |
946 * The Savage4 has one ugly special case to consider. On | |
947 * systems with 4 banks of 2Mx32 SDRAM, the BIOS says 4MB | |
948 * when it really means 8MB. Why do it the same when you | |
949 * can do it different... | |
950 */ | |
951 VGAOUT8(0x3d4, 0x68); /* memory control 1 */ | |
952 if( (VGAIN8(0x3d5) & 0xC0) == (0x01 << 6) ) | |
953 RamSavage4[1] = 8; | |
954 | |
955 /*FALLTHROUGH*/ | |
956 | |
957 case S3_SAVAGE2000: | |
958 videoRam = RamSavage4[ (config1 & 0xE0) >> 5 ] * 1024; | |
959 break; | |
960 | |
961 case S3_SAVAGE_MX: | |
962 videoRam = RamSavageMX[ (config1 & 0x0E) >> 1 ] * 1024; | |
963 break; | |
964 | |
965 case S3_PROSAVAGE: | |
966 videoRam = RamSavageNB[ (config1 & 0xE0) >> 5 ] * 1024; | |
967 break; | |
968 | |
969 default: | |
970 /* How did we get here? */ | |
971 videoRam = 0; | |
972 break; | |
973 } | |
974 | |
975 | |
976 printf("###### videoRam = %d\n",videoRam); | |
977 info->chip.fbsize = videoRam * 1024; | |
978 | |
979 | |
980 /* reset graphics engine to avoid memory corruption */ | |
981 /* VGAOUT8 (0x3d4, 0x66); | |
982 cr66 = VGAIN8 (0x3d5); | |
983 VGAOUT8 (0x3d5, cr66 | 0x02); | |
984 udelay (10000); | |
985 | |
986 VGAOUT8 (0x3d4, 0x66); | |
987 VGAOUT8 (0x3d5, cr66 & ~0x02); /* clear reset flag */ | |
988 /* udelay (10000); */ | |
989 | |
990 /* This maps framebuffer @6MB, thus 2MB are left for video. */ | |
991 if (info->chip.arch == S3_SAVAGE3D) { | |
992 info->video_base = map_phys_mem(pci_info.base0, info->chip.fbsize); | |
993 info->picture_offset = 1024*768* 4 * ((info->chip.fbsize > 4194304)?2:1); | |
994 } | |
995 else { | |
996 info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize); | |
997 info->picture_offset = info->chip.fbsize - FRAMEBUFFER_SIZE; | |
998 // info->picture_offset = 1024*1024* 4 * 2; | |
999 } | |
1000 if ( info->video_base < 0 ){ | |
1001 printf("errno = %s\n", strerror(errno)); | |
1002 return -1; | |
1003 } | |
1004 | |
1005 | |
1006 info->picture_base = (uint32_t) info->video_base + info->picture_offset; | |
1007 | |
1008 if ( info->chip.arch == S3_SAVAGE3D ){ | |
1009 mtrr = mtrr_set_type(pci_info.base0, info->chip.fbsize, MTRR_TYPE_WRCOMB); | |
1010 } | |
1011 else{ | |
1012 mtrr = mtrr_set_type(pci_info.base1, info->chip.fbsize, MTRR_TYPE_WRCOMB); | |
1013 } | |
1014 | |
1015 if (mtrr!= 0) | |
1016 printf("[savage_vid] unable to setup MTRR: %s\n", strerror(mtrr)); | |
1017 else | |
1018 printf("[savage_vid] MTRR set up\n"); | |
1019 | |
1020 /* This may trash your screen for resolutions greater than 1024x768, sorry. */ | |
1021 | |
1022 | |
1023 savage_getscreenproperties(info); | |
1024 // return -1; | |
1025 info->videoFlags = 0; | |
1026 | |
1027 SavageStreamsOn(); | |
1028 //getc(stdin); | |
1029 //FIXME ADD | |
1030 return 0; | |
1031 } | |
1032 | |
1033 /** | |
1034 * @brief Destroys driver. | |
1035 */ | |
1036 void | |
1037 vixDestroy (void) | |
1038 { | |
1039 unmap_phys_mem(info->video_base, info->chip.fbsize); | |
1040 unmap_phys_mem(info->control_base, SAVAGE_NEWMMIO_REGSIZE); | |
1041 //FIXME ADD | |
1042 } | |
1043 | |
1044 /** | |
1045 * @brief Get chipset's hardware capabilities. | |
1046 * | |
1047 * @param to Pointer to the vidix_capability_t structure to be filled. | |
1048 * | |
1049 * @returns 0. | |
1050 */ | |
1051 int | |
1052 vixGetCapability (vidix_capability_t * to) | |
1053 { | |
1054 memcpy (to, &savage_cap, sizeof (vidix_capability_t)); | |
1055 return 0; | |
1056 } | |
1057 | |
1058 /** | |
1059 * @brief Report if the video FourCC is supported by hardware. | |
1060 * | |
1061 * @param fourcc input image format. | |
1062 * | |
1063 * @returns 1 if the fourcc is supported. | |
1064 * 0 otherwise. | |
1065 */ | |
1066 static int | |
1067 is_supported_fourcc (uint32_t fourcc) | |
1068 { | |
1069 switch (fourcc) | |
1070 { | |
1071 //FIXME: YV12 isnt working properly yet | |
1072 // case IMGFMT_YV12: | |
1073 // case IMGFMT_I420: | |
1074 case IMGFMT_UYVY: | |
1075 case IMGFMT_YVYU: | |
1076 case IMGFMT_YUY2: | |
1077 case IMGFMT_RGB15: | |
1078 case IMGFMT_RGB16: | |
1079 // case IMGFMT_BGR32: | |
1080 return 1; | |
1081 default: | |
1082 return 0; | |
1083 } | |
1084 } | |
1085 | |
1086 /** | |
1087 * @brief Try to configure video memory for given fourcc. | |
1088 * | |
1089 * @param to Pointer to the vidix_fourcc_t structure to be filled. | |
1090 * | |
1091 * @returns 0 if ok. | |
1092 * errno otherwise. | |
1093 */ | |
1094 int | |
1095 vixQueryFourcc (vidix_fourcc_t * to) | |
1096 { | |
1097 if (is_supported_fourcc (to->fourcc)) | |
1098 { | |
1099 to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | | |
1100 VID_DEPTH_4BPP | VID_DEPTH_8BPP | | |
1101 VID_DEPTH_12BPP | VID_DEPTH_15BPP | | |
1102 VID_DEPTH_16BPP | VID_DEPTH_24BPP | VID_DEPTH_32BPP; | |
1103 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; | |
1104 return 0; | |
1105 } | |
1106 else | |
1107 to->depth = to->flags = 0; | |
1108 | |
1109 return ENOSYS; | |
1110 } | |
1111 | |
1112 /** | |
1113 * @brief Get the GrKeys | |
1114 * | |
1115 * @param grkey Pointer to the vidix_grkey_t structure to be filled by driver. | |
1116 * | |
1117 * @return 0. | |
1118 */ | |
1119 /*int | |
1120 vixGetGrKeys (vidix_grkey_t * grkey) | |
1121 { | |
1122 | |
1123 // if(info->d_width && info->d_height)savage_overlay_start(info,0); | |
1124 | |
1125 return (0); | |
1126 } | |
1127 * */ | |
1128 | |
1129 /** | |
1130 * @brief Set the GrKeys | |
1131 * | |
1132 * @param grkey Colorkey to be set. | |
1133 * | |
1134 * @return 0. | |
1135 */ | |
1136 int | |
1137 vixSetGrKeys (const vidix_grkey_t * grkey) | |
1138 { | |
1139 if (grkey->ckey.op == CKEY_FALSE) | |
1140 { | |
1141 info->use_colorkey = 0; | |
1142 info->vidixcolorkey=0; | |
1143 printf("[savage_vid] colorkeying disabled\n"); | |
1144 } | |
1145 else { | |
1146 info->use_colorkey = 1; | |
1147 info->vidixcolorkey = ((grkey->ckey.red<<16)|(grkey->ckey.green<<8)|grkey->ckey.blue); | |
1148 | |
1149 printf("[savage_vid] set colorkey 0x%x\n",info->vidixcolorkey); | |
1150 } | |
1151 //FIXME: freezes if streams arent enabled | |
1152 SavageSetColorKeyOld(); | |
1153 return (0); | |
1154 } | |
1155 | |
1156 /** | |
1157 * @brief Unichrome driver equalizer capabilities. | |
1158 */ | |
1159 vidix_video_eq_t equal = { | |
1160 VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION | VEQ_CAP_HUE, | |
1161 300, 100, 0, 0, 0, 0, 0, 0 | |
1162 }; | |
1163 | |
1164 | |
1165 /** | |
1166 * @brief Get the equalizer capabilities. | |
1167 * | |
1168 * @param eq Pointer to the vidix_video_eq_t structure to be filled by driver. | |
1169 * | |
1170 * @return 0. | |
1171 */ | |
1172 int | |
1173 vixPlaybackGetEq (vidix_video_eq_t * eq) | |
1174 { | |
1175 memcpy (eq, &equal, sizeof (vidix_video_eq_t)); | |
1176 return 0; | |
1177 } | |
1178 | |
1179 /** | |
1180 * @brief Set the equalizer capabilities for color correction | |
1181 * | |
1182 * @param eq equalizer capabilities to be set. | |
1183 * | |
1184 * @return 0. | |
1185 */ | |
1186 int | |
1187 vixPlaybackSetEq (const vidix_video_eq_t * eq) | |
1188 { | |
1189 return 0; | |
1190 } | |
1191 | |
1192 /** | |
1193 * @brief Y, U, V offsets. | |
1194 */ | |
1195 static int YOffs, UOffs, VOffs; | |
1196 | |
1197 /** | |
1198 * @brief Configure driver for playback. Driver should prepare BES. | |
1199 * | |
1200 * @param info configuration description for playback. | |
1201 * | |
1202 * @returns 0 in case of success. | |
1203 * -1 otherwise. | |
1204 */ | |
1205 int | |
1206 vixConfigPlayback (vidix_playback_t * vinfo) | |
1207 { | |
1208 int uv_size, swap_uv; | |
1209 unsigned int i; | |
1210 int extfifo_on; | |
1211 int srcPitch,srcPitch2; | |
1212 | |
1213 /* Overlay register settings */ | |
1214 uint32_t win_start, win_end; | |
1215 uint32_t zoom, mini; | |
1216 uint32_t dcount, falign, qwfetch; | |
1217 uint32_t y_start, u_start, v_start; | |
1218 uint32_t v_ctrl, fifo_ctrl; | |
1219 | |
1220 if (!is_supported_fourcc (vinfo->fourcc)) | |
1221 return -1; | |
1222 | |
1223 | |
1224 | |
1225 info->src_w = vinfo->src.w; | |
1226 info->src_h = vinfo->src.h; | |
1227 | |
1228 info->drw_w = vinfo->dest.w; | |
1229 info->drw_h = vinfo->dest.h; | |
1230 | |
1231 info->wx = vinfo->dest.x; | |
1232 info->wy = vinfo->dest.y; | |
1233 info->format = vinfo->fourcc; | |
1234 | |
1235 info->lastKnownPitch = 0; | |
1236 info->brightness = 0; | |
1237 info->contrast = 128; | |
1238 info->saturation = 128; | |
1239 info->hue = 0; | |
1240 | |
1241 | |
1242 vinfo->dga_addr=(void*)(info->picture_base); | |
1243 | |
1244 | |
1245 vinfo->offset.y = 0; | |
1246 vinfo->offset.v = 0; | |
1247 vinfo->offset.u = 0; | |
1248 | |
1249 vinfo->dest.pitch.y = 32; | |
1250 vinfo->dest.pitch.u = 32; | |
1251 vinfo->dest.pitch.v = 32; | |
1252 // vinfo->dest.pitch.u = 0; | |
1253 // vinfo->dest.pitch.v = 0; | |
1254 | |
1255 | |
1256 info->pitch = ((info->src_w << 1) + 15) & ~15; | |
1257 | |
1258 swap_uv = 0; | |
1259 switch (vinfo->fourcc) | |
1260 { | |
1261 case IMGFMT_YUY2: | |
1262 case IMGFMT_UYVY: | |
1263 | |
1264 info->pitch = ((info->src_w << 1) + (vinfo->dest.pitch.y-1)) & ~(vinfo->dest.pitch.y-1); | |
1265 | |
1266 info->pitch = info->src_w << 1; | |
1267 info->pitch = ALIGN_TO (info->src_w << 1, 32); | |
1268 uv_size = 0; | |
1269 break; | |
1270 case IMGFMT_YV12: | |
1271 swap_uv = 1; | |
1272 | |
1273 | |
1274 | |
1275 /* | |
1276 srcPitch = (info->src_w + 3) & ~3; | |
1277 vinfo->offset.u = srcPitch * info->src_h; | |
1278 srcPitch2 = ((info->src_w >> 1) + 3) & ~3; | |
1279 vinfo->offset.v = (srcPitch2 * (info->src_h >> 1)) + vinfo->offset.v; | |
1280 | |
1281 vinfo->dest.pitch.y=srcPitch ; | |
1282 vinfo->dest.pitch.v=srcPitch2 ; | |
1283 vinfo->dest.pitch.u=srcPitch2 ; | |
1284 */ | |
1285 | |
1286 | |
1287 info->pitch = ALIGN_TO (info->src_w, 32); | |
1288 uv_size = (info->pitch >> 1) * (info->src_h >> 1); | |
1289 | |
1290 vinfo->offset.y = 0; | |
1291 vinfo->offset.v = vinfo->offset.y + info->pitch * info->src_h; | |
1292 vinfo->offset.u = vinfo->offset.v + uv_size; | |
1293 vinfo->frame_size = vinfo->offset.u + uv_size; | |
1294 /* YOffs = info->offset.y; | |
1295 UOffs = (swap_uv ? vinfo->offset.v : vinfo->offset.u); | |
1296 VOffs = (swap_uv ? vinfo->offset.u : vinfo->offset.v); | |
1297 */ | |
1298 // vinfo->offset.y = info->src_w; | |
1299 // vinfo->offset.v = vinfo->offset.y + info->src_w /2 * info->src_h; | |
1300 // vinfo->offset.u = vinfo->offset.v + (info->src_w >> 1) * (info->src_h >> 1) ; | |
1301 | |
1302 break; | |
1303 } | |
1304 info->pitch |= ((info->pitch >> 1) << 16); | |
1305 | |
1306 vinfo->frame_size = info->pitch * info->src_h; | |
1307 | |
1308 printf("$#### destination pitch = %u\n", info->pitch&0xffff); | |
1309 | |
1310 | |
1311 | |
1312 | |
1313 info->buffer_size = vinfo->frame_size; | |
1314 info->num_frames = vinfo->num_frames= (info->chip.fbsize - info->picture_offset)/vinfo->frame_size; | |
1315 if(vinfo->num_frames > MAX_FRAMES)vinfo->num_frames = MAX_FRAMES; | |
1316 // vinfo->num_frames = 1; | |
1317 // printf("[nvidia_vid] Number of frames %i\n",vinfo->num_frames); | |
1318 for(i=0;i <vinfo->num_frames;i++)vinfo->offsets[i] = vinfo->frame_size*i; | |
1319 | |
1320 return 0; | |
1321 } | |
1322 | |
1323 /** | |
1324 * @brief Set playback on : driver should activate BES on this call. | |
1325 * | |
1326 * @return 0. | |
1327 */ | |
1328 int | |
1329 vixPlaybackOn (void) | |
1330 { | |
1331 // FIXME: enable | |
1332 SavageDisplayVideoOld(); | |
1333 //FIXME ADD | |
1334 return 0; | |
1335 } | |
1336 | |
1337 /** | |
1338 * @brief Set playback off : driver should deactivate BES on this call. | |
1339 * | |
1340 * @return 0. | |
1341 */ | |
1342 int | |
1343 vixPlaybackOff (void) | |
1344 { | |
1345 // otherwise we wont disable streams properly in new xorg | |
1346 // FIXME: shouldnt this be enabled? | |
1347 // SavageStreamsOn(); | |
1348 SavageStreamsOff(); | |
1349 // info->vidixcolorkey=0x0; | |
1350 | |
1351 // OUTREG( SSTREAM_WINDOW_START_REG, OS_XY(0xfffe, 0xfffe) ); | |
1352 // SavageSetColorKeyOld(); | |
1353 //FIXME ADD | |
1354 return 0; | |
1355 } | |
1356 | |
1357 /** | |
1358 * @brief Driver should prepare and activate corresponded frame. | |
1359 * | |
1360 * @param frame the frame index. | |
1361 * | |
1362 * @return 0. | |
1363 * | |
1364 * @note This function is used only for double and triple buffering | |
1365 * and never used for single buffering playback. | |
1366 */ | |
1367 #if 0 | |
1368 int | |
1369 vixPlaybackFrameSelect (unsigned int frame) | |
1370 { | |
1371 ////FIXME ADD | |
1372 // savage_overlay_start(info, frame); | |
1373 //if (info->num_frames >= 1) | |
1374 // info->cur_frame = frame//(frame+1)%info->num_frames; | |
1375 // | |
1376 // savage4_waitidle(info); | |
1377 | |
1378 printf("vixPlaybackFrameSelect Leave\n" ); | |
1379 // FIXME: does this work to avoid tearing? | |
1380 // VerticalRetraceWait(); | |
1381 | |
1382 return 0; | |
1383 } | |
1384 | |
1385 #endif | |
1386 | |
1387 | |
1388 | |
1389 void debugout(unsigned int addr, unsigned int val){ | |
1390 return ; | |
1391 switch ( addr ){ | |
1392 case PSTREAM_CONTROL_REG: | |
1393 fprintf(stderr,"PSTREAM_CONTROL_REG"); | |
1394 break; | |
1395 case COL_CHROMA_KEY_CONTROL_REG: | |
1396 fprintf(stderr,"COL_CHROMA_KEY_CONTROL_REG"); | |
1397 break; | |
1398 case SSTREAM_CONTROL_REG: | |
1399 fprintf(stderr,"SSTREAM_CONTROL_REG"); | |
1400 break; | |
1401 case CHROMA_KEY_UPPER_BOUND_REG: | |
1402 fprintf(stderr,"CHROMA_KEY_UPPER_BOUND_REG"); | |
1403 break; | |
1404 case SSTREAM_STRETCH_REG: | |
1405 fprintf(stderr,"SSTREAM_STRETCH_REG"); | |
1406 break; | |
1407 case COLOR_ADJUSTMENT_REG: | |
1408 fprintf(stderr,"COLOR_ADJUSTMENT_REG"); | |
1409 break; | |
1410 case BLEND_CONTROL_REG: | |
1411 fprintf(stderr,"BLEND_CONTROL_REG"); | |
1412 break; | |
1413 case PSTREAM_FBADDR0_REG: | |
1414 fprintf(stderr,"PSTREAM_FBADDR0_REG"); | |
1415 break; | |
1416 case PSTREAM_FBADDR1_REG: | |
1417 fprintf(stderr,"PSTREAM_FBADDR1_REG"); | |
1418 break; | |
1419 case PSTREAM_STRIDE_REG: | |
1420 fprintf(stderr,"PSTREAM_STRIDE_REG"); | |
1421 break; | |
1422 case DOUBLE_BUFFER_REG: | |
1423 fprintf(stderr,"DOUBLE_BUFFER_REG"); | |
1424 break; | |
1425 case SSTREAM_FBADDR0_REG: | |
1426 fprintf(stderr,"SSTREAM_FBADDR0_REG"); | |
1427 break; | |
1428 case SSTREAM_FBADDR1_REG: | |
1429 fprintf(stderr,"SSTREAM_FBADDR1_REG"); | |
1430 break; | |
1431 case SSTREAM_STRIDE_REG: | |
1432 fprintf(stderr,"SSTREAM_STRIDE_REG"); | |
1433 break; | |
1434 case SSTREAM_VSCALE_REG: | |
1435 fprintf(stderr,"SSTREAM_VSCALE_REG"); | |
1436 break; | |
1437 case SSTREAM_VINITIAL_REG: | |
1438 fprintf(stderr,"SSTREAM_VINITIAL_REG"); | |
1439 break; | |
1440 case SSTREAM_LINES_REG: | |
1441 fprintf(stderr,"SSTREAM_LINES_REG"); | |
1442 break; | |
1443 case STREAMS_FIFO_REG: | |
1444 fprintf(stderr,"STREAMS_FIFO_REG"); | |
1445 break; | |
1446 case PSTREAM_WINDOW_START_REG: | |
1447 fprintf(stderr,"PSTREAM_WINDOW_START_REG"); | |
1448 break; | |
1449 case PSTREAM_WINDOW_SIZE_REG: | |
1450 fprintf(stderr,"PSTREAM_WINDOW_SIZE_REG"); | |
1451 break; | |
1452 case SSTREAM_WINDOW_START_REG: | |
1453 fprintf(stderr,"SSTREAM_WINDOW_START_REG"); | |
1454 break; | |
1455 case SSTREAM_WINDOW_SIZE_REG: | |
1456 fprintf(stderr,"SSTREAM_WINDOW_SIZE_REG"); | |
1457 break; | |
1458 case FIFO_CONTROL: | |
1459 fprintf(stderr,"FIFO_CONTROL"); | |
1460 break; | |
1461 case PSTREAM_FBSIZE_REG: | |
1462 fprintf(stderr,"PSTREAM_FBSIZE_REG"); | |
1463 break; | |
1464 case SSTREAM_FBSIZE_REG: | |
1465 fprintf(stderr,"SSTREAM_FBSIZE_REG"); | |
1466 break; | |
1467 case SSTREAM_FBADDR2_REG: | |
1468 fprintf(stderr,"SSTREAM_FBADDR2_REG"); | |
1469 break; | |
1470 | |
1471 } | |
1472 fprintf(stderr,":\t\t 0x%08X = %u\n",val,val); | |
1473 } | |
1474 | |
1475 |