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comparison vidix/drivers/nvidia_vid.c @ 11160:b5a3ef555164

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double buffering fix for cards > NV04 && windows colorkeying fix
author faust3
date Fri, 17 Oct 2003 11:26:36 +0000
parents 8ac4d769a1fb
children e1c3f72da3d1
comparison
equal deleted inserted replaced
11159:8ac4d769a1fb 11160:b5a3ef555164
414 r = (chromakey & 0x00FF0000) >> 16; 414 r = (chromakey & 0x00FF0000) >> 16;
415 g = (chromakey & 0x0000FF00) >> 8; 415 g = (chromakey & 0x0000FF00) >> 8;
416 b = chromakey & 0x000000FF; 416 b = chromakey & 0x000000FF;
417 switch (info->depth) { 417 switch (info->depth) {
418 case 15: 418 case 15:
419 key = ((r >> 3) << 10) | ((g >> 3) << 5) | ((b >> 3)) | 0x00008000; 419 key = ((r >> 3) << 10) | ((g >> 3) << 5) | ((b >> 3));
420 #ifndef WIN32
421 key = key | 0x00008000;
422 #endif
420 break; 423 break;
421 case 16: // XXX unchecked 424 case 16: // XXX unchecked
422 key = ((r >> 3) << 11) | ((g >> 2) << 5) | ((b >> 3)) | 0x00008000; 425 key = ((r >> 3) << 11) | ((g >> 2) << 5) | ((b >> 3));
423 break; 426 #ifndef WIN32
424 case 24: // XXX unchecked, maybe swap order of masking 427 key = key | 0x00008000;
428 #endif
429 break;
430 case 24: // XXX unchecked, maybe swap order of masking - FIXME Can the card be in 24 bit mode anyway?
425 key = (chromakey & 0x00FFFFFF) | 0x00800000; 431 key = (chromakey & 0x00FFFFFF) | 0x00800000;
426 break; 432 break;
427 case 32: 433 case 32:
428 key = chromakey | 0x80000000; 434 key = chromakey;
435 #ifndef WIN32
436 key = key | 0x80000000;
437 #endif
429 break; 438 break;
430 } 439 }
431 //printf("[nvidia_vid] depth=%d %08X \n", info->depth, chromakey); 440 //printf("[nvidia_vid] depth=%d %08X \n", info->depth, chromakey);
432 switch (info->chip.arch) { 441 switch (info->chip.arch) {
433 case NV_ARCH_10: 442 case NV_ARCH_10:
513 case NV_ARCH_10: 522 case NV_ARCH_10:
514 case NV_ARCH_20: 523 case NV_ARCH_20:
515 case NV_ARCH_30: 524 case NV_ARCH_30:
516 525
517 /* NV_PVIDEO_BASE */ 526 /* NV_PVIDEO_BASE */
518 VID_WR32 (info->chip.PVIDEO, 0x900 + 0, base); 527 VID_WR32 (info->chip.PVIDEO, 0x900 + 0, base + offset);
519 //VID_WR32 (info->chip.PVIDEO, 0x900 + 4, base); 528 //VID_WR32 (info->chip.PVIDEO, 0x900 + 4, base);
520 /* NV_PVIDEO_LIMIT */ 529 /* NV_PVIDEO_LIMIT */
521 VID_WR32 (info->chip.PVIDEO, 0x908 + 0, base + size - 1); 530 VID_WR32 (info->chip.PVIDEO, 0x908 + 0, base + offset + size - 1);
522 //VID_WR32 (info->chip.PVIDEO, 0x908 + 4, base + size - 1); 531 //VID_WR32 (info->chip.PVIDEO, 0x908 + 4, base + size - 1);
523 532
524 /* extra code for NV20 && NV30 architectures */ 533 /* extra code for NV20 && NV30 architectures */
525 if (info->chip.arch == NV_ARCH_20 || info->chip.arch == NV_ARCH_30) { 534 if (info->chip.arch == NV_ARCH_20 || info->chip.arch == NV_ARCH_30) {
526 VID_WR32 (info->chip.PVIDEO, 0x800 + 0, base); 535 VID_WR32 (info->chip.PVIDEO, 0x800 + 0, base + offset);
527 //VID_WR32 (info->chip.PVIDEO, 0x800 + 4, base); 536 //VID_WR32 (info->chip.PVIDEO, 0x800 + 4, base);
528 VID_WR32 (info->chip.PVIDEO, 0x808 + 0, base + size - 1); 537 VID_WR32 (info->chip.PVIDEO, 0x808 + 0, base + offset + size - 1);
529 //VID_WR32 (info->chip.PVIDEO, 0x808 + 4, base + size - 1); 538 //VID_WR32 (info->chip.PVIDEO, 0x808 + 4, base + size - 1);
530 } 539 }
531 540
532 /* NV_PVIDEO_LUMINANCE */ 541 /* NV_PVIDEO_LUMINANCE */
533 VID_WR32 (info->chip.PVIDEO, 0x910 + 0, 0x00001000); 542 VID_WR32 (info->chip.PVIDEO, 0x910 + 0, 0x00001000);
535 /* NV_PVIDEO_CHROMINANCE */ 544 /* NV_PVIDEO_CHROMINANCE */
536 VID_WR32 (info->chip.PVIDEO, 0x918 + 0, 0x00001000); 545 VID_WR32 (info->chip.PVIDEO, 0x918 + 0, 0x00001000);
537 //VID_WR32 (info->chip.PVIDEO, 0x918 + 4, 0x00001000); 546 //VID_WR32 (info->chip.PVIDEO, 0x918 + 4, 0x00001000);
538 547
539 /* NV_PVIDEO_OFFSET */ 548 /* NV_PVIDEO_OFFSET */
540 VID_WR32 (info->chip.PVIDEO, 0x920 + 0, offset + 0); 549 VID_WR32 (info->chip.PVIDEO, 0x920 + 0, 0x0);
541 //VID_WR32 (info->chip.PVIDEO, 0x920 + 4, offset + pitch); 550 //VID_WR32 (info->chip.PVIDEO, 0x920 + 4, offset + pitch);
542 /* NV_PVIDEO_SIZE_IN */ 551 /* NV_PVIDEO_SIZE_IN */
543 VID_WR32 (info->chip.PVIDEO, 0x928 + 0, ((info->height) << 16) | info->width); 552 VID_WR32 (info->chip.PVIDEO, 0x928 + 0, ((info->height) << 16) | info->width);
544 //VID_WR32 (info->chip.PVIDEO, 0x928 + 4, ((port->org_height/2) << 16) | port->org_width); 553 //VID_WR32 (info->chip.PVIDEO, 0x928 + 4, ((port->org_height/2) << 16) | port->org_width);
545 /* NV_PVIDEO_POINT_IN */ 554 /* NV_PVIDEO_POINT_IN */