Mercurial > mplayer.hg

comparison drivers/radeon/radeon_vid.c @ 3047:ef3b9b104648

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
Minor speedup of YUY2 decoding. Radeon it's tricked chip
author nick
date Wed, 21 Nov 2001 09:48:52 +0000
parents e5ebde3ebdd6
children 2d2a1358d563
comparison
equal deleted inserted replaced
3046:cf927aec7c6a 3047:ef3b9b104648
314 #define XXX_DRW_W config->dest_width 314 #define XXX_DRW_W config->dest_width
315 #define XXX_DRW_H config->dest_height 315 #define XXX_DRW_H config->dest_height
316 316
317 static int radeon_vid_init_video( mga_vid_config_t *config ) 317 static int radeon_vid_init_video( mga_vid_config_t *config )
318 { 318 {
319 uint32_t tmp,src_w,pitch,h_inc,step_by,left,leftUV,top; 319 uint32_t tmp,src_w,src_h,pitch,h_inc,step_by,left,leftUV,top;
320 int is_420; 320 int is_420;
321 RTRACE("radeon_vid: usr_config: version = %x format=%x card=%x ram=%u src(%ux%u) dest(%u:%ux%u:%u) frame_size=%u num_frames=%u\n" 321 RTRACE("radeon_vid: usr_config: version = %x format=%x card=%x ram=%u src(%ux%u) dest(%u:%ux%u:%u) frame_size=%u num_frames=%u\n"
322 ,(uint32_t)config->version 322 ,(uint32_t)config->version
323 ,(uint32_t)config->format 323 ,(uint32_t)config->format
324 ,(uint32_t)config->card_type 324 ,(uint32_t)config->card_type
330 ,(uint32_t)config->dest_width 330 ,(uint32_t)config->dest_width
331 ,(uint32_t)config->dest_height 331 ,(uint32_t)config->dest_height
332 ,(uint32_t)config->frame_size 332 ,(uint32_t)config->frame_size
333 ,(uint32_t)config->num_frames); 333 ,(uint32_t)config->num_frames);
334 radeon_vid_stop_video(); 334 radeon_vid_stop_video();
335 left = XXX_SRC_X << 16;
336 top = XXX_SRC_Y << 16;
337 src_h = config->src_height;
338 src_w = config->src_width;
335 switch(config->format) 339 switch(config->format)
336 { 340 {
337 case IMGFMT_RGB15: 341 case IMGFMT_RGB15:
338 case IMGFMT_BGR15: 342 case IMGFMT_BGR15:
339 case IMGFMT_RGB16: 343 case IMGFMT_RGB16:
367 case IMGFMT_I420: 371 case IMGFMT_I420:
368 case IMGFMT_YUY2: 372 case IMGFMT_YUY2:
369 case IMGFMT_RGB15: 373 case IMGFMT_RGB15:
370 case IMGFMT_BGR15: 374 case IMGFMT_BGR15:
371 case IMGFMT_RGB16: 375 case IMGFMT_RGB16:
372 case IMGFMT_BGR16: pitch = ((XXX_WIDTH*2) + 15) & ~15; break; 376 case IMGFMT_BGR16: pitch = ((src_w*2) + 15) & ~15; break;
373 case IMGFMT_RGB24: 377 case IMGFMT_RGB24:
374 case IMGFMT_BGR24: pitch = ((XXX_WIDTH*3) + 15) & ~15; break; 378 case IMGFMT_BGR24: pitch = ((src_w*3) + 15) & ~15; break;
375 case IMGFMT_RGB32: 379 case IMGFMT_RGB32:
376 case IMGFMT_BGR32: pitch = ((XXX_WIDTH*4) + 15) & ~15; break; 380 case IMGFMT_BGR32: pitch = ((src_w*4) + 15) & ~15; break;
377 } 381 }
378 382
379 left = XXX_SRC_X << 16;
380 top = XXX_SRC_Y << 16;
381
382 besr.fourcc = config->format; 383 besr.fourcc = config->format;
383 384
384 besr.v_inc = (config->src_height << 20) / XXX_DRW_H; 385 besr.v_inc = (src_h << 20) / XXX_DRW_H;
385 h_inc = (config->src_width << 12) / XXX_DRW_W; 386 h_inc = (src_w << 12) / XXX_DRW_W;
386 step_by = 1; 387 step_by = 1;
387 388
388 while(h_inc >= (2 << 12)) { 389 while(h_inc >= (2 << 12)) {
389 step_by++; 390 step_by++;
390 h_inc >>= 1; 391 h_inc >>= 1;
393 /* keep everything in 16.16 */ 394 /* keep everything in 16.16 */
394 395
395 if(is_420) 396 if(is_420)
396 { 397 {
397 uint32_t dstPitch,d1line,d2line,d3line; 398 uint32_t dstPitch,d1line,d2line,d3line;
398 dstPitch = (XXX_WIDTH + 15) & ~15; /* of luma */ 399 dstPitch = ((src_w + 15) & ~15); /* of luma */
399 d1line = top * dstPitch; 400 d1line = top * dstPitch;
400 d2line = (XXX_HEIGHT * dstPitch) + ((top >> 1) * (dstPitch >> 1)); 401 d2line = (src_h * dstPitch) + ((top >> 1) * (dstPitch >> 1));
401 d3line = d2line + ((XXX_HEIGHT >> 1) * (dstPitch >> 1)); 402 d3line = d2line + ((src_h >> 1) * (dstPitch >> 1));
402 d1line += (left >> 16) & ~15; 403 besr.vid_buf0_base_adrs = (radeon_overlay_off + d1line) & VIF_BUF0_BASE_ADRS_MASK;
403 d2line += (left >> 17) & ~15; 404 besr.vid_buf1_base_adrs = ((radeon_overlay_off + d2line) & VIF_BUF1_BASE_ADRS_MASK) | VIF_BUF1_PITCH_SEL;
404 d3line += (left >> 17) & ~15; 405 besr.vid_buf2_base_adrs = ((radeon_overlay_off + d3line) & VIF_BUF2_BASE_ADRS_MASK) | VIF_BUF2_PITCH_SEL;
405 besr.vid_buf0_base_adrs = (radeon_overlay_off + d1line) & 0xfffffff0;
406 besr.vid_buf1_base_adrs = ((radeon_overlay_off + d2line) & 0xfffffff0) | 0x00000001;
407 besr.vid_buf2_base_adrs = ((radeon_overlay_off + d3line) & 0xfffffff0) | 0x00000001;
408 besr.vid_buf3_base_adrs = besr.vid_buf0_base_adrs;
409 besr.vid_buf4_base_adrs = besr.vid_buf1_base_adrs;
410 besr.vid_buf5_base_adrs = besr.vid_buf2_base_adrs;
411 } 406 }
412 else 407 else
413 { 408 {
414 besr.vid_buf0_base_adrs = radeon_overlay_off; 409 besr.vid_buf0_base_adrs = radeon_overlay_off;
415 besr.vid_buf0_base_adrs += ((left & ~7) << 1)&0xfffffff0; 410 besr.vid_buf0_base_adrs += ((left & ~7) << 1)&0xfffffff0;
416 besr.vid_buf1_base_adrs = besr.vid_buf0_base_adrs + config->frame_size; 411 besr.vid_buf1_base_adrs = besr.vid_buf0_base_adrs;
417 besr.vid_buf2_base_adrs = besr.vid_buf0_base_adrs; 412 besr.vid_buf2_base_adrs = besr.vid_buf0_base_adrs;
418 besr.vid_buf3_base_adrs = besr.vid_buf0_base_adrs + config->frame_size;
419 besr.vid_buf4_base_adrs = besr.vid_buf0_base_adrs;
420 besr.vid_buf5_base_adrs = besr.vid_buf0_base_adrs + config->frame_size;
421 } 413 }
414 besr.vid_buf3_base_adrs = besr.vid_buf0_base_adrs+config->frame_size;
415 besr.vid_buf4_base_adrs = besr.vid_buf1_base_adrs+config->frame_size;
416 besr.vid_buf5_base_adrs = besr.vid_buf2_base_adrs+config->frame_size;
422 417
423 tmp = (left & 0x0003ffff) + 0x00028000 + (h_inc << 3); 418 tmp = (left & 0x0003ffff) + 0x00028000 + (h_inc << 3);
424 besr.p1_h_accum_init = ((tmp << 4) & 0x000f8000) | 419 besr.p1_h_accum_init = ((tmp << 4) & 0x000f8000) |
425 ((tmp << 12) & 0xf0000000); 420 ((tmp << 12) & 0xf0000000);
426 421
433 428
434 429
435 tmp = ((top >> 1) & 0x0000ffff) + 0x00018000; 430 tmp = ((top >> 1) & 0x0000ffff) + 0x00018000;
436 besr.p23_v_accum_init = is_420 ? ((tmp << 4) & 0x01ff8000) | 0x00000001 : 0; 431 besr.p23_v_accum_init = is_420 ? ((tmp << 4) & 0x01ff8000) | 0x00000001 : 0;
437 432
438 leftUV = (left >> 17) & 7; 433 leftUV = (left >> 17) & 15;
439 left = (left >> 16) & 7; 434 left = (left >> 16) & 15;
440 besr.h_inc = h_inc | ((h_inc >> 1) << 16); 435 besr.h_inc = h_inc | ((h_inc >> 1) << 16);
441 besr.step_by = step_by | (step_by << 8); 436 besr.step_by = step_by | (step_by << 8);
442 besr.y_x_start = (config->x_org+8) | (config->y_org << 16); 437 besr.y_x_start = (config->x_org+8) | (config->y_org << 16);
443 besr.y_x_end = (config->x_org + config->dest_width+8) | ((config->y_org + config->dest_height) << 16); 438 besr.y_x_end = (config->x_org + config->dest_width+8) | ((config->y_org + config->dest_height) << 16);
444 besr.p1_blank_lines_at_top = 0x00000fff | ((config->src_height - 1) << 16); 439 besr.p1_blank_lines_at_top = P1_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16);
445 besr.p23_blank_lines_at_top = is_420 ? 0x000007ff | ((((config->src_height+1)>>1) - 1) << 16) : 0; 440 src_h = (src_h + 1) >> 1;
441 besr.p23_blank_lines_at_top = is_420 ? P23_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16):0;
446 besr.vid_buf_pitch0_value = pitch; 442 besr.vid_buf_pitch0_value = pitch;
447 besr.vid_buf_pitch1_value = is_420 ? pitch/2 : pitch; 443 besr.vid_buf_pitch1_value = is_420 ? pitch>>1 : pitch;
448 RTRACE("radeon_vid: BES: v_inc=%x h_inc=%x step_by=%x\n",besr.v_inc,besr.h_inc,besr.step_by); 444 RTRACE("radeon_vid: BES: v_inc=%x h_inc=%x step_by=%x\n",besr.v_inc,besr.h_inc,besr.step_by);
449 RTRACE("radeon_vid: BES: vid_buf0_basey=%x\n",besr.vid_buf0_base_adrs); 445 RTRACE("radeon_vid: BES: vid_buf0_basey=%x\n",besr.vid_buf0_base_adrs);
450 RTRACE("radeon_vid: BES: y_x_start=%x y_x_end=%x blank_at_top=%x pitch0_value=%x\n" 446 RTRACE("radeon_vid: BES: y_x_start=%x y_x_end=%x blank_at_top=%x pitch0_value=%x\n"
451 ,besr.y_x_start,besr.y_x_end,besr.p1_blank_lines_at_top,besr.vid_buf_pitch0_value); 447 ,besr.y_x_start,besr.y_x_end,besr.p1_blank_lines_at_top,besr.vid_buf_pitch0_value);
452 besr.p1_x_start_end = (config->src_width + left - 1) | (left << 16); 448 besr.p1_x_start_end = (src_w+left-1)|(left<<16);
453 src_w=config->src_width >> 1; 449 src_w>>=1;
454 besr.p2_x_start_end = (src_w + left - 1) | (leftUV << 16); 450 besr.p2_x_start_end = (src_w+left-1)|(leftUV<<16);
455 besr.p3_x_start_end = besr.p2_x_start_end; 451 besr.p3_x_start_end = besr.p2_x_start_end;
456 return 0; 452 return 0;
457 } 453 }
458 454
459 static void radeon_vid_frame_sel(int frame) 455 static void radeon_vid_frame_sel(int frame)
460 { 456 {
461 uint32_t off; 457 uint32_t off;
462 switch(frame) 458 off = frame%2?besr.vid_buf3_base_adrs:besr.vid_buf0_base_adrs;
463 {
464 default:
465 case 0: off = besr.vid_buf0_base_adrs; break;
466 case 1: off = besr.vid_buf3_base_adrs; break;
467 case 2: off = besr.vid_buf0_base_adrs; break;
468 case 3: off = besr.vid_buf3_base_adrs; break;
469 case 4: off = besr.vid_buf0_base_adrs; break;
470 case 5: off = besr.vid_buf3_base_adrs; break;
471 }
472 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); 459 OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK);
473 while(!(INREG(OV0_REG_LOAD_CNTL)&REG_LD_CTL_LOCK_READBACK)); 460 while(!(INREG(OV0_REG_LOAD_CNTL)&REG_LD_CTL_LOCK_READBACK));
474 OUTREG(OV0_VID_BUF0_BASE_ADRS, off); 461 OUTREG(OV0_VID_BUF0_BASE_ADRS, off);
475 OUTREG(OV0_REG_LOAD_CNTL, 0); 462 OUTREG(OV0_REG_LOAD_CNTL, 0);
476 } 463 }