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comparison vidix/drivers/nvidia_vid.c @ 16371:f3e6984c415c

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initial endianess fixes
author faust3
date Sat, 03 Sep 2005 10:27:22 +0000
parents b2e4d3f3c0af
children 71180d64e6cc
comparison
equal deleted inserted replaced
16370:b2e4d3f3c0af 16371:f3e6984c415c
191 191
192 192
193 /* 193 /*
194 * PCI-Memory IO access macros. 194 * PCI-Memory IO access macros.
195 */ 195 */
196 #define VID_WR08(p,i,val) (((uint8_t *)(p))[(i)]=(val))
197 #define VID_RD08(p,i) (((uint8_t *)(p))[(i)])
198
199 #define VID_WR32(p,i,val) (((uint32_t *)(p))[(i)/4]=(val))
200 #define VID_RD32(p,i) (((uint32_t *)(p))[(i)/4])
201
202 #ifndef USE_RMW_CYCLES
203 /*
204 * Can be used to inhibit READ-MODIFY-WRITE cycles. On by default.
205 */
206 196
207 #define MEM_BARRIER() __asm__ __volatile__ ("" : : : "memory") 197 #define MEM_BARRIER() __asm__ __volatile__ ("" : : : "memory")
208 198
209 #undef VID_WR08 199 #undef VID_WR08
210 #define VID_WR08(p,i,val) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]=(val); }) 200 #define VID_WR08(p,i,val) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]=(val); })
211 #undef VID_RD08 201 #undef VID_RD08
212 #define VID_RD08(p,i) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]; }) 202 #define VID_RD08(p,i) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]; })
213 203
214 #undef VID_WR32 204 #undef VID_WR32
215 #define VID_WR32(p,i,val) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]=(val); }) 205 #define VID_WR32(p,i,val) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]=le2me_32(val); })
216 #undef VID_RD32 206 #undef VID_RD32
217 #define VID_RD32(p,i) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]; }) 207 #define VID_RD32(p,i) ({ MEM_BARRIER(); le2me_32(((uint32_t *)(p))[(i)/4]); })
218 #endif /* USE_RMW_CYCLES */
219 208
220 #define VID_AND32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)&(val)) 209 #define VID_AND32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)&(val))
221 #define VID_OR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)|(val)) 210 #define VID_OR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)|(val))
222 #define VID_XOR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)^(val)) 211 #define VID_XOR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)^(val))
223 212
286 return 1024 * 1024 * 8; 275 return 1024 * 1024 * 8;
287 } 276 }
288 } 277 }
289 else { 278 else {
290 /* SGRAM 128. */ 279 /* SGRAM 128. */
291 switch (chip->PFB[0x00000000] & 0x00000003) { 280 switch (VID_RD32(chip->PFB, 0) & 0x00000003) {
292 case 0: 281 case 0:
293 return 1024 * 1024 * 8; 282 return 1024 * 1024 * 8;
294 break; 283 break;
295 case 2: 284 case 2:
296 return 1024 * 1024 * 4; 285 return 1024 * 1024 * 4;
480 info->chip.lock(&info->chip, 0); 469 info->chip.lock(&info->chip, 0);
481 /*get screen depth*/ 470 /*get screen depth*/
482 VID_WR08(info->chip.PCIO, 0x03D4,0x28); 471 VID_WR08(info->chip.PCIO, 0x03D4,0x28);
483 bpp = VID_RD08(info->chip.PCIO,0x03D5)&0x3; 472 bpp = VID_RD08(info->chip.PCIO,0x03D5)&0x3;
484 if(bpp==3)bpp=4; 473 if(bpp==3)bpp=4;
485 if((bpp == 2) && (info->chip.PVIDEO[0x00000600/4] & 0x00001000) == 0x0)info->depth=15; 474 if((bpp == 2) && (VID_RD32(info->chip.PVIDEO,0x600) & 0x00001000) == 0x0)info->depth=15;
486 else info->depth = bpp*8; 475 else info->depth = bpp*8;
487 info->bps=bpp; 476 info->bps=bpp;
488 /*get screen width*/ 477 /*get screen width*/
489 VID_WR08(info->chip.PCIO, 0x03D4, 0x1); 478 VID_WR08(info->chip.PCIO, 0x03D4, 0x1);
490 info->screen_x = (1 + VID_RD08(info->chip.PCIO, 0x3D5)) * 8; 479 info->screen_x = (1 + VID_RD08(info->chip.PCIO, 0x3D5)) * 8;
507 void rivatv_overlay_start (struct rivatv_info *info,int bufno){ 496 void rivatv_overlay_start (struct rivatv_info *info,int bufno){
508 uint32_t base, size, offset, xscale, yscale, pan; 497 uint32_t base, size, offset, xscale, yscale, pan;
509 uint32_t value; 498 uint32_t value;
510 int x=info->wx, y=info->wy; 499 int x=info->wx, y=info->wy;
511 int lwidth=info->d_width, lheight=info->d_height; 500 int lwidth=info->d_width, lheight=info->d_height;
512 int i;
513 501
514 size = info->buffer_size; 502 size = info->buffer_size;
515 base = info->picture_offset; 503 base = info->picture_offset;
516 offset = bufno*size; 504 offset = bufno*size;
517 /*update depth & dimensions here because it may change with vo vesa or vo fbdev*/ 505 /*update depth & dimensions here because it may change with vo vesa or vo fbdev*/