mplayer.hg: drivers/radeon/radeon

comparison drivers/radeon/radeon_vid.c @ 3607:f5cc15e11d6e

+ Added support of FIFO engine (suggested by Vladimir Dergachev) - Disabled save/restore state functions (caused a lots of problems during driver reloading)

author	nick
date	Wed, 19 Dec 2001 10:41:08 +0000
parents	135926174ee8
children	80d0864322b9

comparison

equal deleted inserted replaced

-:1ceab741e3e6
+:f5cc15e11d6e
 *
 * SPECIAL THANKS TO: Hans-Peter Raschke for active testing and hacking
 * Rage128(pro) stuff of this driver.
 */
-#define RADEON_VID_VERSION "1.1.1"
+#define RADEON_VID_VERSION "1.1.2"
 /*
 It's entirely possible this major conflicts with something else
 mknod /dev/radeon_vid c 178 0
 or
 #ifdef DEBUG
 #define DECLARE_VREG(name) { #name, name, 0 }
 #else
 #define DECLARE_VREG(name) { name, 0 }
 #endif
+#ifdef DEBUG
 static video_registers_t vregs[] =
 {
 DECLARE_VREG(VIDEOMUX_CNTL),
 DECLARE_VREG(VIPPAD_MASK),
 DECLARE_VREG(VIPPAD1_A),
 DECLARE_VREG(IDCT_LEVELS),
 DECLARE_VREG(IDCT_AUTH_CONTROL),
 DECLARE_VREG(IDCT_AUTH),
 DECLARE_VREG(IDCT_CONTROL)
 };
+#endif
 static uint32_t radeon_vid_in_use = 0;
 static uint8_t *radeon_mmio_base = 0;
 static uint32_t radeon_mem_base = 0;
 static int32_t radeon_overlay_off = 0;
 #define INREG8(addr)		readb((radeon_mmio_base)+addr)
 #define OUTREG8(addr,val)	writeb(val, (radeon_mmio_base)+addr)
 #define INREG(addr)		readl((radeon_mmio_base)+addr)
 #define OUTREG(addr,val)	writel(val, (radeon_mmio_base)+addr)
+#define OUTREGP(addr,val,mask)  					\
+	do {								\
+		unsigned int _tmp = INREG(addr);			\
+		_tmp &= (mask);						\
+		_tmp |= (val);						\
+		OUTREG(addr, _tmp);					\
+	} while (0)
 static uint32_t radeon_vid_get_dbpp( void )
 {
 uint32_t dbpp,retval;
 dbpp = (INREG(CRTC_GEN_CNTL)>>8)& 0xF;
 static int radeon_is_interlace( void )
 {
 return (INREG(CRTC_GEN_CNTL))&CRTC_INTERLACE_EN;
 }
+static __inline__ void radeon_engine_flush ( void )
+{
+	int i;
+	/* initiate flush */
+	OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
+	        ~RB2D_DC_FLUSH_ALL);
+	for (i=0; i < 2000000; i++) {
+		if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
+			break;
+	}
+}
+static __inline__ void _radeon_fifo_wait (int entries)
+{
+	int i;
+	for (i=0; i<2000000; i++)
+		if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
+			return;
+}
+static __inline__ void _radeon_engine_idle ( void )
+{
+	int i;
+	/* ensure FIFO is empty before waiting for idle */
+	_radeon_fifo_wait (64);
+	for (i=0; i<2000000; i++) {
+		if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
+			radeon_engine_flush ();
+			return;
+		}
+	}
+}
+#define radeon_engine_idle()		_radeon_engine_idle()
+#define radeon_fifo_wait(entries)	_radeon_fifo_wait(entries)
+#if 0
 static void __init radeon_vid_save_state( void )
 {
 size_t i;
 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++)
 	vregs[i].value = INREG(vregs[i].name);
 }
 static void __exit radeon_vid_restore_state( void )
 {
 size_t i;
+radeon_fifo_wait(2);
+OUTREG(OV0_REG_LOAD_CNTL,		REG_LD_CTL_LOCK);
+radeon_engine_idle();
+while(!(INREG(OV0_REG_LOAD_CNTL)&REG_LD_CTL_LOCK_READBACK));
+radeon_fifo_wait(15);
 for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++)
+{
+	radeon_fifo_wait(1);
 	OUTREG(vregs[i].name,vregs[i].value);
 }
+OUTREG(OV0_REG_LOAD_CNTL,		0);
+}
+#endif
 #ifdef DEBUG
 static void radeon_vid_dump_regs( void )
 {
 size_t i;
 printk(RVID_MSG"*** Begin of OV0 registers dump ***\n");
 }
 #endif
 static void radeon_vid_stop_video( void )
 {
+radeon_engine_idle();
 OUTREG(OV0_SCALE_CNTL, SCALER_SOFT_RESET);
 OUTREG(OV0_EXCLUSIVE_HORZ, 0);
 OUTREG(OV0_AUTO_FLIP_CNTL, 0);   /* maybe */
 OUTREG(OV0_FILTER_CNTL, FILTER_HARDCODED_COEF);
 OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_NE);
 }
 static void radeon_vid_display_video( void )
 {
 int bes_flags;
+radeon_fifo_wait(2);
 OUTREG(OV0_REG_LOAD_CNTL,		REG_LD_CTL_LOCK);
+radeon_engine_idle();
 while(!(INREG(OV0_REG_LOAD_CNTL)&REG_LD_CTL_LOCK_READBACK));
+radeon_fifo_wait(15);
 OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD);
 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE));
 OUTREG(OV0_AUTO_FLIP_CNTL,(INREG(OV0_AUTO_FLIP_CNTL)^OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE));
 OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern);
 #ifdef RAGE128
 OUTREG(OV0_COLOUR_CNTL, (besr.brightness & 0x7f) |
 			    (besr.saturation << 8) |
 			    (besr.saturation << 16));
 #endif
+radeon_fifo_wait(2);
 if(besr.ckey_on)
 {
 	OUTREG(OV0_GRAPHICS_KEY_MSK, besr.graphics_key_msk);
 	OUTREG(OV0_GRAPHICS_KEY_CLR, besr.graphics_key_clr);
 	OUTREG(OV0_KEY_CNTL,GRAPHIC_KEY_FN_EQ|VIDEO_KEY_FN_FALSE|CMP_MIX_OR);
 OUTREG(OV0_BASE_ADDR,		besr.base_addr);
 #endif
 OUTREG(OV0_VID_BUF0_BASE_ADRS,	besr.vid_buf0_base_adrs);
 OUTREG(OV0_VID_BUF1_BASE_ADRS,	besr.vid_buf1_base_adrs);
 OUTREG(OV0_VID_BUF2_BASE_ADRS,	besr.vid_buf2_base_adrs);
+radeon_fifo_wait(9);
 OUTREG(OV0_VID_BUF3_BASE_ADRS,	besr.vid_buf3_base_adrs);
 OUTREG(OV0_VID_BUF4_BASE_ADRS,	besr.vid_buf4_base_adrs);
 OUTREG(OV0_VID_BUF5_BASE_ADRS,	besr.vid_buf5_base_adrs);
 OUTREG(OV0_P1_V_ACCUM_INIT,		besr.p1_v_accum_init);
 OUTREG(OV0_P1_H_ACCUM_INIT,		besr.p1_h_accum_init);
 		unregister_chrdev(RADEON_VID_MAJOR, "radeon_vid");
 		return -EINVAL;
 	}
 	radeon_param_buff = kmalloc(PARAM_BUFF_SIZE,GFP_KERNEL);
 	if(radeon_param_buff) radeon_param_buff_size = PARAM_BUFF_SIZE;
+#if 0
 	radeon_vid_save_state();
+#endif
 	radeon_vid_make_default();
 	radeon_vid_preset();
 #ifdef CONFIG_MTRR
 	if (mtrr) {
 		smtrr.vram = mtrr_add(radeon_mem_base,
 	return radeon_vid_initialize();
 }
 void __exit cleanup_module(void)
 {
+#if 0
 	radeon_vid_restore_state();
+#endif
 	if(radeon_mmio_base)
 		iounmap(radeon_mmio_base);
 	kfree(radeon_param_buff);
 	RTRACE(RVID_MSG"Cleaning up module\n");
 	unregister_chrdev(RADEON_VID_MAJOR, "radeon_vid");

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comparison drivers/radeon/radeon_vid.c @ 3607:f5cc15e11d6e