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diff vidix/unichrome_regs.h @ 29263:0f1b5b68af32

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whitespace cosmetics: Remove all trailing whitespace.
author diego
date Wed, 13 May 2009 02:58:57 +0000
parents a93e46adb54c
children
line wrap: on
line diff
--- a/vidix/unichrome_regs.h	Tue May 12 19:25:35 2009 +0000
+++ b/vidix/unichrome_regs.h	Wed May 13 02:58:57 2009 +0000
@@ -53,7 +53,7 @@
 #define SW_USE_V1               0x00000010  /*[ 4] : 1:Capture 1 use V1, 0:Capture 1 use V3             */
 #define SW_USE_V3               0x00000000  /*[ 4] : 1:Capture 1 use V1, 0:Capture 1 use V3             */
 #define SW_USE_HQV              0x00000020  /*[ 5] : 1:Capture 1 use HQV,0:Capture 1 not use HQV        */
-     
+
 /*
 #define VIDEO1_INUSE            0x00000010  //[ 4] : 1:Video 1 is used with S/W flip
 #define VIDEO1_USE_HQV          0x00000020  //[ 5] : 1:Video 1 use HQV with S/W flip
@@ -146,7 +146,7 @@
 #define V1_STARTADDR_CR2        0xF8
 #define V1_STARTADDR_CR3        0xFC
 
-/* Video Capture Engine Registers 
+/* Video Capture Engine Registers
  * Capture Port 1
  */
 #define CAP0_MASKS          0x100
@@ -154,15 +154,15 @@
 #define CAP0_CONTROL        0x110
 #define CAP0_H_RANGE        0x114
 #define CAP0_V_RANGE        0x118
-#define CAP0_SCAL_CONTROL   0x11C 
+#define CAP0_SCAL_CONTROL   0x11C
 #define CAP0_VBI_H_RANGE    0x120
 #define CAP0_VBI_V_RANGE    0x124
 #define CAP0_VBI_STARTADDR  0x128
-#define CAP0_VBI_STRIDE     0x12C 
+#define CAP0_VBI_STRIDE     0x12C
 #define CAP0_ANCIL_COUNT    0x130
 #define CAP0_MAXCOUNT       0x134
 #define CAP0_VBIMAX_COUNT   0x138
-#define CAP0_DATA_COUNT     0x13C 
+#define CAP0_DATA_COUNT     0x13C
 #define CAP0_FB_STARTADDR0  0x140
 #define CAP0_FB_STARTADDR1  0x144
 #define CAP0_FB_STARTADDR2  0x148
@@ -177,10 +177,10 @@
 #define CAP1_ANCIL_COUNT    0x174 /*To be deleted*/
 #define CAP1_MAXCOUNT       0x178
 #define CAP1_VBIMAX_COUNT   0x17C /*To be deleted*/
-#define CAP1_DATA_COUNT     0x180 
+#define CAP1_DATA_COUNT     0x180
 #define CAP1_FB_STARTADDR0  0x184
 #define CAP1_FB_STARTADDR1  0x188
-#define CAP1_STRIDE         0x18C 
+#define CAP1_STRIDE         0x18C
 
 /* SUBPICTURE Registers */
 #define SUBP_CONTROL_STRIDE     0x1C0
@@ -288,24 +288,24 @@
 #define V1_FIFO_DEPTH16         0x0000000F
 #define V1_FIFO_DEPTH32         0x0000001F
 #define V1_FIFO_DEPTH48         0x0000002F
-#define V1_FIFO_DEPTH64         0x0000003F   
+#define V1_FIFO_DEPTH64         0x0000003F
 #define V1_FIFO_THRESHOLD6      0x00000600
 #define V1_FIFO_THRESHOLD8      0x00000800
 #define V1_FIFO_THRESHOLD12     0x00000C00
 #define V1_FIFO_THRESHOLD16     0x00001000
 #define V1_FIFO_THRESHOLD24     0x00001800
 #define V1_FIFO_THRESHOLD32     0x00002000
-#define V1_FIFO_THRESHOLD40     0x00002800  
-#define V1_FIFO_THRESHOLD48     0x00003000   
-#define V1_FIFO_THRESHOLD56     0x00003800  
-#define V1_FIFO_THRESHOLD61     0x00003D00  
+#define V1_FIFO_THRESHOLD40     0x00002800
+#define V1_FIFO_THRESHOLD48     0x00003000
+#define V1_FIFO_THRESHOLD56     0x00003800
+#define V1_FIFO_THRESHOLD61     0x00003D00
 #define V1_FIFO_PRETHRESHOLD10  0x0A000000
 #define V1_FIFO_PRETHRESHOLD12  0x0C000000
 #define V1_FIFO_PRETHRESHOLD29  0x1d000000
-#define V1_FIFO_PRETHRESHOLD40  0x28000000  
+#define V1_FIFO_PRETHRESHOLD40  0x28000000
 #define V1_FIFO_PRETHRESHOLD44  0x2c000000
-#define V1_FIFO_PRETHRESHOLD56  0x38000000   
-#define V1_FIFO_PRETHRESHOLD61  0x3D000000   
+#define V1_FIFO_PRETHRESHOLD56  0x38000000
+#define V1_FIFO_PRETHRESHOLD61  0x3D000000
 
 /* ALPHA_V3_FIFO_CONTROL        0x278
  * IA2 has 32 level FIFO for packet mode video format
@@ -318,23 +318,23 @@
 #define V3_FIFO_DEPTH24         0x00000017
 #define V3_FIFO_DEPTH32         0x0000001F
 #define V3_FIFO_DEPTH48         0x0000002F
-#define V3_FIFO_DEPTH64         0x0000003F   
+#define V3_FIFO_DEPTH64         0x0000003F
 #define V3_FIFO_THRESHOLD8      0x00000800
 #define V3_FIFO_THRESHOLD12     0x00000C00
 #define V3_FIFO_THRESHOLD16     0x00001000
 #define V3_FIFO_THRESHOLD24     0x00001800
 #define V3_FIFO_THRESHOLD32     0x00002000
-#define V3_FIFO_THRESHOLD40     0x00002800  
-#define V3_FIFO_THRESHOLD48     0x00003000   
-#define V3_FIFO_THRESHOLD56     0x00003800   
-#define V3_FIFO_THRESHOLD61     0x00003D00   
+#define V3_FIFO_THRESHOLD40     0x00002800
+#define V3_FIFO_THRESHOLD48     0x00003000
+#define V3_FIFO_THRESHOLD56     0x00003800
+#define V3_FIFO_THRESHOLD61     0x00003D00
 #define V3_FIFO_PRETHRESHOLD10  0x0000000A
 #define V3_FIFO_PRETHRESHOLD12  0x0000000C
 #define V3_FIFO_PRETHRESHOLD29  0x0000001d
-#define V3_FIFO_PRETHRESHOLD40  0x00000028  
+#define V3_FIFO_PRETHRESHOLD40  0x00000028
 #define V3_FIFO_PRETHRESHOLD44  0x0000002c
-#define V3_FIFO_PRETHRESHOLD56  0x00000038   
-#define V3_FIFO_PRETHRESHOLD61  0x0000003D   
+#define V3_FIFO_PRETHRESHOLD56  0x00000038
+#define V3_FIFO_PRETHRESHOLD61  0x0000003D
 #define V3_FIFO_MASK            0x0000007F
 #define ALPHA_FIFO_DEPTH8       0x00070000
 #define ALPHA_FIFO_THRESHOLD4   0x04000000
@@ -401,8 +401,8 @@
 #define BUFFER_2_MODE       		0x00000000
 #define BUFFER_3_MODE       		0x00000004
 #define BUFFER_4_MODE       		0x00000006
-#define SWAP_YUYV           		0x00000000 
-#define SWAP_UYVY           		0x00000100   
+#define SWAP_YUYV           		0x00000000
+#define SWAP_UYVY           		0x00000100
 #define SWAP_YVYU           		0x00000200
 #define SWAP_VYUY           		0x00000300
 #define IN_601_8            		0x00000000
@@ -410,17 +410,17 @@
 #define IN_601_16           		0x00000020
 #define IN_656_16           		0x00000030
 #define DEINTER_ODD         		0x00000000
-#define DEINTER_EVEN        		0x00001000   
+#define DEINTER_EVEN        		0x00001000
 #define DEINTER_ODD_EVEN    		0x00002000
 #define DEINTER_FRAME       		0x00003000
-#define VIP_1               		0x00000000 
+#define VIP_1               		0x00000000
 #define VIP_2               		0x00000400
 #define H_FILTER_2          		0x00010000
-#define H_FILTER_4          		0x00020000 
-#define H_FILTER_8_1331     		0x00030000 
+#define H_FILTER_4          		0x00020000
+#define H_FILTER_8_1331     		0x00030000
 #define H_FILTER_8_12221    		0x00040000
 #define VIP_ENABLE          		0x00000008
-#define EN_FIELD_SIG        		0x00000800  
+#define EN_FIELD_SIG        		0x00000800
 #define VREF_INVERT         		0x00100000
 #define FIELD_INPUT_INVERSE    		0x00400000
 #define FIELD_INVERSE       		0x40000000
@@ -443,7 +443,7 @@
 #define V3_RGB16                0x0000000C
 #define V3_COLORSPACE_SIGN      0x00000080
 #define V3_EXPIRE_NUM           0x00040000
-#define V3_EXPIRE_NUM_F         0x000f0000 
+#define V3_EXPIRE_NUM_F         0x000f0000
 #define V3_BOB_ENABLE           0x00400000
 #define V3_FIELD_BASE           0x00000000
 #define V3_FRAME_BASE           0x01000000
@@ -475,12 +475,12 @@
 #define HQV_FRAME_2_FIELD   0x00040000   /* Src is field. Display field */
 #define HQV_FRAME_UV        0x00000000   /* Src is Non-interleaved */
 #define HQV_FIELD_UV        0x00100000   /* Src is interleaved */
-#define HQV_IDLE            0x00000008   
-#define HQV_FLIP_STATUS     0x00000001   
+#define HQV_IDLE            0x00000008
+#define HQV_FLIP_STATUS     0x00000001
 #define HQV_DOUBLE_BUFF     0x00000000
 #define HQV_TRIPLE_BUFF     0x04000000
 #define HQV_SUBPIC_FLIP     0x00008000
-#define HQV_FIFO_STATUS     0x00001000  
+#define HQV_FIFO_STATUS     0x00001000
 
 /* HQV_FILTER_CONTROL      0x3E4 */
 #define HQV_H_LOWPASS_2TAP  0x00000001
@@ -565,7 +565,7 @@
 #define VIDOutD(port, data)     *((volatile CARD32 *)(pVia->VidMapBase + (port))) = (data)
 #define MPGOutD(port, data)     *((volatile CARD32 *)(lpMPEGMMIO +(port))) = (data)
 #define MPGInD(port)            *((volatile CARD32 *)(lpMPEGMMIO +(port)))
-#endif 
+#endif
 
 /*
  *      Macros for GE MMIO
@@ -578,7 +578,7 @@
 /*
  *	MPEG 1/2 Slice Engine (at 0xC00 relative to base)
  */
- 
+
 #define MPG_CONTROL		0x00
 #define 	MPG_CONTROL_STRUCT	0x03
 #define			MPG_CONTROL_STRUCT_TOP		0x01