view libdha/sysdep/pci_isc.c @ 17067:2f4f6c278741

AMD's Family 6 CPUs come with two flavors: one that supports SSE and one that dosen't. However, they're not easily distinguishible from their signature (family, model and stepping). Original configure might set -march=athlon-4 for a CPU that dosen't support SSE and causes gcc to generate code that won't run on the target machine. Closes bug #267. patch by Zuxy Meng zuxy -- dot -- meng -- at -- gmail -- dot -- com

/*
   This file is based on:
   $XFree86: xc/programs/Xserver/hw/xfree86/etc/scanpci.c,v 3.34.2.17 1998/11/10 11:55:40 dawes Exp $
   Modified for readability by Nick Kurshev
*/
#include <sys/param.h>
#include <sys/immu.h>
#include <sys/region.h>
#include <sys/proc.h>
#include <sys/tss.h>
#include <sys/sysi86.h>
#include <sys/v86.h>

static __inline__ int enable_os_io(void)
{
#if defined(SI86IOPL)
    sysi86(SI86IOPL, 3);
#else
    sysi86(SI86V86, V86SC_IOPL, PS_IOPL);
#endif
    return(0);
}

static __inline__ int disable_os_io(void)
{
#if defined(SI86IOPL)
    sysi86(SI86IOPL, 0);
#else
    sysi86(SI86V86, V86SC_IOPL, 0);
#endif
    return(0);
}