# HG changeset patch # User gpoirier # Date 1132773671 0 # Node ID 0bfb8718801598a65165a10918cbc2aed416280c # Parent 5c87173bb774ffcad868dfae398802432de85d4e correct k6_mtrr detection, add a great deal of infos about newer processors patch by Zuxy Meng < zuxy POIS meng @gmail POIS com > Original thread: Date: Nov 21, 2005 11:36 AM Subject: [MPlayer-dev-eng] [PATCH] TOOLS/cpuinfo.c: correct k6_mtrr detection diff -r 5c87173bb774 -r 0bfb87188015 TOOLS/cpuinfo.c --- a/TOOLS/cpuinfo.c Wed Nov 23 19:14:05 2005 +0000 +++ b/TOOLS/cpuinfo.c Wed Nov 23 19:21:11 2005 +0000 @@ -4,6 +4,8 @@ #include #include +#include +#include #ifdef __MINGW32__ #include @@ -79,6 +81,7 @@ unsigned max_cpuid; unsigned max_ext_cpuid; unsigned int amd_flags; + unsigned int amd_flags2; char *model_name = "Unknown CPU"; int i; char processor_name[49]; @@ -103,6 +106,7 @@ if (max_ext_cpuid >= (1<<31) + 1) { regs_ext = cpuid((1<<31) + 1); amd_flags = regs_ext.edx; + amd_flags2 = regs_ext.ecx; if (max_ext_cpuid >= (1<<31) + 4) { for (i = 2; i <= 4; i++) { @@ -117,6 +121,7 @@ } } else { amd_flags = 0; + amd_flags2 = 0; } if (max_cpuid >= 1) { @@ -151,7 +156,25 @@ { 25, "sse", "SSE Extensions" }, { 26, "sse2", "SSE2 Extensions" }, { 27, "ss", "Self Snoop" }, + { 28, "htt", "Multi-threading" }, { 29, "tm", "Therm. Monitor" }, + { 30, "ia64", "IA-64 Processor" }, + { 31, "pbe", "Pend. Brk. EN." }, + { -1 } + }; + static struct { + int bit; + char *desc; + char *description; + } cap2[] = { + { 0, "sse3", "SSE3 Extensions" }, + { 3, "monitor", "MONITOR/MWAIT" }, + { 4, "ds-cpl", "CPL Qualified Debug Store" }, + { 5, "vmx", "Virtual Machine Extensions" }, + { 7, "est", "Enhanced Intel SpeedStep Technology" }, + { 8, "tm2", "Thermal Monitor 2" }, + { 10, "cnxt-id", "L1 Context ID" }, + { 13, "cmpxchg16b", "CMPXCHG16B Available" }, { -1 } }; static struct { @@ -159,21 +182,36 @@ char *desc;; char *description; } cap_amd[] = { - { 22, "mmxext","MMX Technology (AMD Extensions)" }, + { 11, "syscall", "SYSCALL and SYSRET" }, + { 19, "mp", "MP Capable" }, + { 20, "nx", "No-Execute Page Protection" }, + { 22, "mmxext","MMX Technology (AMD Extensions)" }, + { 25, "fxsr_opt", "Fast FXSAVE/FXRSTOR" }, + { 27, "rdtscp", "RDTSCP Instruction" }, { 30, "3dnowext","3Dnow! Extensions" }, { 31, "3dnow", "3Dnow!" }, - { 32, "k6_mtrr", "Memory Type Range Registers" }, { -1 } }; - int i; + static struct { + int bit; + char *desc; + char *description; + } cap_amd2[] = { + { 0, "lahf_lm", "LAHF/SAHF Supported in 64-bit Mode" }, + { 1, "cmp_legacy", "Chip Multi-Core" }, + { 2, "svm", "Secure Virtual Machine" }, + { 4, "cr8", "CR8 Available in Legacy Mode" }, + { -1 } + }; + unsigned int family, model, stepping; regs = cpuid(1); printf("cpu family\t: %d\n" "model\t\t: %d\n" "stepping\t: %d\n" , - (regs.eax >> 8) & 0xf, - (regs.eax >> 4) & 0xf, - regs.eax & 0xf); + family = (regs.eax >> 8) & 0xf, + model = (regs.eax >> 4) & 0xf, + stepping = regs.eax & 0xf); printf("flags\t\t:"); for (i = 0; cap[i].bit >= 0; i++) { @@ -181,11 +219,29 @@ printf(" %s", cap[i].desc); } } + for (i = 0; cap2[i].bit >= 0; i++) { + if (regs.ecx & (1 << cap[i].bit)) { + printf(" %s", cap2[i].desc); + } + } + /* k6_mtrr is supported by some AMD K6-2/K6-III CPUs but + it is not indicated by a CPUID feature bit, so we + have to check the family, model and stepping instead. */ + if (strstr(idstr, "AMD") && + family == 5 && + (model >= 9 || model == 8 && stepping >= 8)) + printf(" %s", "k6_mtrr"); + for (i = 0; cap_amd[i].bit >= 0; i++) { if (amd_flags & (1 << cap_amd[i].bit)) { printf(" %s", cap_amd[i].desc); } } + for (i = 0; cap_amd2[i].bit >= 0; i++) { + if (amd_flags2 & (1 << cap_amd2[i].bit)) { + printf(" %s", cap_amd2[i].desc); + } + } printf("\n"); if (regs.edx & (1 << 4)) {