# HG changeset patch
# User nickols_k
# Date 992448734 0
# Node ID 5b69dabe58239e6509f11afd87e27d92de96971f
# Parent  fe9ef743be91986c321b7eb8a0cb77e40d50bb6f
Issues about P3 performance and SSE2 support.

diff -r fe9ef743be91 -r 5b69dabe5823 libvo/aclib.c
--- a/libvo/aclib.c	Wed Jun 13 15:03:27 2001 +0000
+++ b/libvo/aclib.c	Wed Jun 13 16:12:14 2001 +0000
@@ -8,8 +8,15 @@
 
 #include <stddef.h>
 
-/* Enable this code, if SSE version works (faster) for you! */
-#if 1
+#ifndef HAVE_SSE2
+/*
+   P3 processor has only one SSE decoder so can execute only 1 sse insn per
+   cpu clock, but it has 3 mmx decoders (include load/store unit)
+   and executes 3 mmx insns per cpu clock.
+   P4 processor has some chances, but after reading:
+   http://www.emulators.com/pentium4.htm
+   I have doubts. Anyway SSE2 version of this code can be written better.
+*/
 #undef HAVE_SSE
 #endif
 
diff -r fe9ef743be91 -r 5b69dabe5823 libvo/aclib_template.c
--- a/libvo/aclib_template.c	Wed Jun 13 15:03:27 2001 +0000
+++ b/libvo/aclib_template.c	Wed Jun 13 16:12:14 2001 +0000
@@ -8,8 +8,15 @@
 
 #include <stddef.h>
 
-/* Enable this code, if SSE version works (faster) for you! */
-#if 1
+#ifndef HAVE_SSE2
+/*
+   P3 processor has only one SSE decoder so can execute only 1 sse insn per
+   cpu clock, but it has 3 mmx decoders (include load/store unit)
+   and executes 3 mmx insns per cpu clock.
+   P4 processor has some chances, but after reading:
+   http://www.emulators.com/pentium4.htm
+   I have doubts. Anyway SSE2 version of this code can be written better.
+*/
 #undef HAVE_SSE
 #endif