# HG changeset patch
# User ben
# Date 1189881746 0
# Node ID 610500ad2e6c97d7537ebb639737a0fac7a321c7
# Parent  c5c0cb0e90d2556833da4b6750656d1cad162f1d
fix screen width and height calculation on nvidia vidix (patch by Guillaume Lecerf (fox at geexbox dot org)

diff -r c5c0cb0e90d2 -r 610500ad2e6c vidix/nvidia_vid.c
--- a/vidix/nvidia_vid.c	Sat Sep 15 18:13:56 2007 +0000
+++ b/vidix/nvidia_vid.c	Sat Sep 15 18:42:26 2007 +0000
@@ -658,7 +658,11 @@
   else info->depth = 0x04 << bpp;
   /*get screen width*/
   VID_WR08(info->chip.PCIO, 0x03D4, 0x1);
-  info->screen_x = (1 + VID_RD08(info->chip.PCIO, 0x3D5)) * 8;
+  info->screen_x = VID_RD08(info->chip.PCIO, 0x3D5);
+  /* NV_PCRTC_HORIZ_EXTRA_DISPLAY_END_8 */
+  VID_WR08 (info->chip.PCIO, 0x3D4, 0x2D);
+  info->screen_x |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0x02) << 7;
+  info->screen_x = (info->screen_x + 1) << 3;
   /*get screen height*/
   /* get first 8 bits in VT_DISPLAY_END*/
   VID_WR08(info->chip.PCIO, 0x03D4, 0x12);
@@ -669,6 +673,12 @@
   /* and the 10th in CRTC_OVERFLOW*/
   info->screen_y |=(VID_RD08(info->chip.PCIO,0x03D5) &0x40)<<3;
   ++info->screen_y;
+  /* NV_PCRTC_EXTRA_VERT_DISPLAY_END_10 */
+  VID_WR08(info->chip.PCIO,0x03D4,0x25);
+  info->screen_y |= (VID_RD08(info->chip.PCIO,0x03D5) &0x02)<<9;
+  /* NV_PCRTC_???_VERT_DISPLAY_END_11 */
+  VID_WR08(info->chip.PCIO,0x03D4,0x41);
+  info->screen_y |= (VID_RD08(info->chip.PCIO,0x03D5) &0x04)<<9;
 
   /* NV_PCRTC_OFFSET */
   VID_WR08 (info->chip.PCIO, 0x3D4, 0x13);