# HG changeset patch
# User ben
# Date 1182877650 0
# Node ID 82443ed07f230607167e34753421533c814708ee
# Parent  604f56414432300275e6432218531bf41080327c
fix Radeon/Rage128 vidix with I420 colorspace (U/V were inverted)

diff -r 604f56414432 -r 82443ed07f23 vidix/radeon_vid.c
--- a/vidix/radeon_vid.c	Tue Jun 26 16:33:43 2007 +0000
+++ b/vidix/radeon_vid.c	Tue Jun 26 17:07:30 2007 +0000
@@ -3055,8 +3055,16 @@
 	    }
 	    else
 	    {
-		besr.vid_buf_base_adrs_v[i]=((radeon_overlay_off+config->offsets[i]+config->offset.v)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL;
-		besr.vid_buf_base_adrs_u[i]=((radeon_overlay_off+config->offsets[i]+config->offset.u)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL;
+              	if (besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV)
+		{
+		    besr.vid_buf_base_adrs_u[i]=((radeon_overlay_off+config->offsets[i]+config->offset.v)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL;
+		    besr.vid_buf_base_adrs_v[i]=((radeon_overlay_off+config->offsets[i]+config->offset.u)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL;
+		}
+		else
+		{
+		    besr.vid_buf_base_adrs_v[i]=((radeon_overlay_off+config->offsets[i]+config->offset.v)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL;
+		    besr.vid_buf_base_adrs_u[i]=((radeon_overlay_off+config->offsets[i]+config->offset.u)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL;
+		}
 	    }
 	}
 	config->offset.y = ((besr.vid_buf_base_adrs_y[0])&VIF_BUF0_BASE_ADRS_MASK) - radeon_overlay_off;
@@ -3070,13 +3078,6 @@
 	    config->offset.v = ((besr.vid_buf_base_adrs_v[0])&VIF_BUF1_BASE_ADRS_MASK) - radeon_overlay_off;
 	    config->offset.u = ((besr.vid_buf_base_adrs_u[0])&VIF_BUF2_BASE_ADRS_MASK) - radeon_overlay_off;
 	}
-	if(besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV)
-	{
-	  uint32_t tmp;
-	  tmp = config->offset.u;
-	  config->offset.u = config->offset.v;
-	  config->offset.v = tmp;
-	}
     }
     else
     {