# HG changeset patch
# User nick
# Date 1008182887 0
# Node ID 8a46f6a9efd04c23ce674d1d46f3140faa9b0ba7
# Parent  27d6e7af93368796becd7edf14b163a773e57f4e
Preparing to next acceleration level

diff -r 27d6e7af9336 -r 8a46f6a9efd0 drivers/radeon/hacking
--- a/drivers/radeon/hacking	Wed Dec 12 18:25:29 2001 +0000
+++ b/drivers/radeon/hacking	Wed Dec 12 18:48:07 2001 +0000
@@ -279,6 +279,34 @@
               (is not MMX optimized that's gladly accepted, but probably
                will be never optimized due portability).
 
+hardware IDCT support diagram:
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+                                      |
+[ Video parser ] <---------- [ Transport demuxing ] --> [ Audio ]
+       |                                |       |
+[ Variable length decoder]              |D      |
+       |                                |V      |
+[ Inverse quantization ]                |D      |
+       |                                |       |
+-------|---[ video card ]---------+     |s      |
+       |                          |     |u      |
+[ Run level decode & de-zigzag ]  |     |b      |
+       |                          |     |p      |
+[    IDCT   ]                     |     |i      |
+       |                          |     |c      |
+[  Motion compensation  ]         |     |t      |
+       |                          |     |u      |
+[ Advanced deinterlacing ]        |     |r      |
+       |                          |     |e      |
+[ Filtered X-Y scaling ] [SUBPIC]-|-----+s   [ OSD ]
+       |                     |    |     |       |
+[ 4-bit alpha blending ] <---+    |     +-------+
+       |                          |
+[ YUV to RGB conversion ]         |
+-------|--------------------------+
+TV-screen or CRT-display
+
+
 Conslusion:
 ~~~~~~~~~~~
 
diff -r 27d6e7af9336 -r 8a46f6a9efd0 drivers/radeon/radeon.h
--- a/drivers/radeon/radeon.h	Wed Dec 12 18:25:29 2001 +0000
+++ b/drivers/radeon/radeon.h	Wed Dec 12 18:48:07 2001 +0000
@@ -523,7 +523,6 @@
 #	define REG_LD_CTL_VBLANK_DURING_LOCK	0x00000002L
 #	define REG_LD_CTL_STALL_GUI_UNTIL_FLIP	0x00000004L
 #	define REG_LD_CTL_LOCK_READBACK		0x00000008L
-/*#define OV0_REG_SLICE_CNTL			 0xXXXX*/
 #define	OV0_SCALE_CNTL				0x0420
 #	define SCALER_PIX_EXPAND		0x00000001L
 #	define SCALER_Y2R_TEMP			0x00000002L
diff -r 27d6e7af9336 -r 8a46f6a9efd0 drivers/radeon/radeon_vid.c
--- a/drivers/radeon/radeon_vid.c	Wed Dec 12 18:25:29 2001 +0000
+++ b/drivers/radeon/radeon_vid.c	Wed Dec 12 18:48:07 2001 +0000
@@ -183,6 +183,11 @@
 
 static video_registers_t vregs[] = 
 {
+  DECLARE_VREG(VIDEOMUX_CNTL),
+  DECLARE_VREG(VIPPAD_MASK),
+  DECLARE_VREG(VIPPAD1_A),
+  DECLARE_VREG(VIPPAD1_EN),
+  DECLARE_VREG(VIPPAD1_Y),
   DECLARE_VREG(OV0_Y_X_START),
   DECLARE_VREG(OV0_Y_X_END),
   DECLARE_VREG(OV0_PIPELINE_CNTL),
@@ -243,7 +248,30 @@
   DECLARE_VREG(OV0_GAMMA_20_3F),
   DECLARE_VREG(OV0_GAMMA_40_7F),
   DECLARE_VREG(OV0_GAMMA_380_3BF),
-  DECLARE_VREG(OV0_GAMMA_3C0_3FF)
+  DECLARE_VREG(OV0_GAMMA_3C0_3FF),
+  DECLARE_VREG(SUBPIC_CNTL),
+  DECLARE_VREG(SUBPIC_DEFCOLCON),
+  DECLARE_VREG(SUBPIC_Y_X_START),
+  DECLARE_VREG(SUBPIC_Y_X_END),
+  DECLARE_VREG(SUBPIC_V_INC),
+  DECLARE_VREG(SUBPIC_H_INC),
+  DECLARE_VREG(SUBPIC_BUF0_OFFSET),
+  DECLARE_VREG(SUBPIC_BUF1_OFFSET),
+  DECLARE_VREG(SUBPIC_LC0_OFFSET),
+  DECLARE_VREG(SUBPIC_LC1_OFFSET),
+  DECLARE_VREG(SUBPIC_PITCH),
+  DECLARE_VREG(SUBPIC_BTN_HLI_COLCON),
+  DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_START),
+  DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_END),
+  DECLARE_VREG(SUBPIC_PALETTE_INDEX),
+  DECLARE_VREG(SUBPIC_PALETTE_DATA),
+  DECLARE_VREG(SUBPIC_H_ACCUM_INIT),
+  DECLARE_VREG(SUBPIC_V_ACCUM_INIT),
+  DECLARE_VREG(IDCT_RUNS),
+  DECLARE_VREG(IDCT_LEVELS),
+  DECLARE_VREG(IDCT_AUTH_CONTROL),
+  DECLARE_VREG(IDCT_AUTH),
+  DECLARE_VREG(IDCT_CONTROL)
 };
 
 static uint32_t radeon_vid_in_use = 0;