# HG changeset patch
# User reimar
# Date 1189777386 0
# Node ID 999a0a1e47485b64b4fb4911cc0bfa11f3dbeac4
# Parent  2f31f31deccc917b578b75b047ddaaa8295bda7d
Remove unused sigfpe handler

diff -r 2f31f31deccc -r 999a0a1e4748 cpudetect.c
--- a/cpudetect.c	Fri Sep 14 13:25:20 2007 +0000
+++ b/cpudetect.c	Fri Sep 14 13:43:06 2007 +0000
@@ -305,25 +305,6 @@
 
    gCpuCaps.hasSSE=0;
 }
-
-static void sigfpe_handler_sse( int signal, struct sigcontext sc )
-{
-   mp_msg(MSGT_CPUDETECT,MSGL_V, "SIGFPE, " );
-
-   if ( sc.fpstate->magic != 0xffff ) {
-      /* Our signal context has the extended FPU state, so reset the
-       * divide-by-zero exception mask and clear the divide-by-zero
-       * exception bit.
-       */
-      sc.fpstate->mxcsr |= 0x00000200;
-      sc.fpstate->mxcsr &= 0xfffffffb;
-   } else {
-      /* If we ever get here, we're completely hosed.
-       */
-      mp_msg(MSGT_CPUDETECT,MSGL_V, "\n\n" );
-      mp_msg(MSGT_CPUDETECT,MSGL_V, "SSE enabling test failed badly!" );
-   }
-}
 #endif /* __linux__ && _POSIX_SOURCE && X86_FXSR_MAGIC */
 
 #ifdef WIN32
@@ -417,10 +398,8 @@
    /* Save the original signal handlers.
     */
    sigaction( SIGILL, NULL, &saved_sigill );
-   sigaction( SIGFPE, NULL, &saved_sigfpe );
 
    signal( SIGILL, (void (*)(int))sigill_handler_sse );
-   signal( SIGFPE, (void (*)(int))sigfpe_handler_sse );
 
    /* Emulate test for OSFXSR in CR4.  The OS will set this bit if it
     * supports the extended FPU save and restore required for SSE.  If
@@ -444,7 +423,6 @@
    /* Restore the original signal handlers.
     */
    sigaction( SIGILL, &saved_sigill, NULL );
-   sigaction( SIGFPE, &saved_sigfpe, NULL );
 
    /* If we've gotten to here and the XMM CPUID bit is still set, we're
     * safe to go ahead and hook out the SSE code throughout Mesa.