changeset 32579:b25a7879b23c

Add horrible hack to make xvidix work on big-endian.

--- a/vidix/radeon_vid.c	Sun Nov 28 15:33:45 2010 +0000
+++ b/vidix/radeon_vid.c	Sun Nov 28 16:10:56 2010 +0000
@@ -1308,6 +1308,24 @@
 #endif
 }
 
+/**
+ * Clear swap bits of surface data control regs for bigendian
+ */
+static void clear_swap(void)
+{
+#if HAVE_BIGENDIAN
+#ifdef RAGE128
+   OUTREG(CONFIG_CNTL,
+          savreg.config_cntl &
+          ~(APER_0_BIG_ENDIAN_16BPP_SWAP | APER_0_BIG_ENDIAN_32BPP_SWAP));
+#else
+   OUTREG(SURFACE_CNTL,
+          savreg.config_cntl &
+          ~(NONSURF_AP0_SWP_32BPP | NONSURF_AP0_SWP_16BPP));
+#endif
+#endif
+}
+
 static int radeon_init(void)
 {
   int err;
@@ -1367,18 +1385,7 @@
   }
 #endif
   save_regs();
-  /* XXX: hack, but it works for me (tm) */
-#if HAVE_BIGENDIAN
-#ifdef RAGE128
-   OUTREG(CONFIG_CNTL,
-          savreg.config_cntl &
-          ~(APER_0_BIG_ENDIAN_16BPP_SWAP | APER_0_BIG_ENDIAN_32BPP_SWAP));
-#else
-   OUTREG(SURFACE_CNTL,
-          savreg.config_cntl &
-          ~(NONSURF_AP0_SWP_32BPP | NONSURF_AP0_SWP_16BPP));
-#endif
-#endif
+  clear_swap();
   return 0;
 }
 
@@ -3178,6 +3185,11 @@
 {
     uint32_t off[6];
     int prev_frame= (frame-1+besr.vid_nbufs) % besr.vid_nbufs;
+    // This really only needs to be set during data writes,
+    // however we don't have a hook there.
+    // The setup at startup is not enough since X11 regularly
+    // resets this to values to the wrong values for us.
+    clear_swap();
     /*
     buf3-5 always should point onto second buffer for better
     deinterlacing and TV-in