annotate driver/pt1_tuner_data.h @ 124:9c7bc6c0327e

Add DLNA server function test. (from uShare project)
author naoyan@johnstown.minaminoshima.org
date Wed, 29 Sep 2010 23:18:55 +0900 (2010-09-29)
parents 6e661e828b43
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
0
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
1 #ifndef __PT1_TUNER_DATA_H__
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
2 #define __PT1_TUNER_DATA_H__
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
3 /***************************************************************************/
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
4 /* */
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
5 /***************************************************************************/
77
517e61637f7b a bit cleanup
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 71
diff changeset
6 #define PT1_MAX_ISDB_S_INIT 19 // ISDB-S 初期化データ数
517e61637f7b a bit cleanup
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 71
diff changeset
7 #define PT1_MAX_ISDB_T_INIT 16 // ISDB-T 初期化データ数
517e61637f7b a bit cleanup
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 71
diff changeset
8 #define PT2_MAX_ISDB_S_INIT 18 // ISDB-S 初期化データ数
517e61637f7b a bit cleanup
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 71
diff changeset
9 #define PT2_MAX_ISDB_T_INIT 12 // ISDB-T 初期化データ数
517e61637f7b a bit cleanup
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 71
diff changeset
10
0
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
11 #define MAX_BS_CHANNEL 36 // 周波数テーブル数
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
12 #define MAX_ISDB_T_CHANNEL 113 // 周波数テーブル数(地デジタル)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
13 #define MAX_BS_CHANNEL_PLL_COMMAND 3 // PLLロックするためのコマンド数
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
14 /***************************************************************************/
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
15 /* */
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
16 /***************************************************************************/
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
17
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
18 /***************************************************************************/
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
19 /* */
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
20 /***************************************************************************/
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
21 typedef struct _WBLOCK_BS_PLL{
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
22 WBLOCK *wblock[MAX_BS_CHANNEL_PLL_COMMAND] ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
23 }WBLOCK_BS_PLL;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
24
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
25 /***************************************************************************/
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
26 /* */
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
27 /***************************************************************************/
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
28 extern WBLOCK com_initdata; //初期化(共通)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
29 extern WBLOCK isdb_s_init1; //ISDB-S先頭
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
30 extern WBLOCK isdb_s_init21; //ISDB-S最終
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
31 extern WBLOCK isdb_t_init17; //ISDB-T最終
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
32 extern WBLOCK bs_pll_lock; //ISDB-S PLLロック確認
77
517e61637f7b a bit cleanup
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 71
diff changeset
33 extern WBLOCK *isdb_s_initial_pt1[PT1_MAX_ISDB_S_INIT];
517e61637f7b a bit cleanup
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 71
diff changeset
34 extern WBLOCK *isdb_t_initial_pt1[PT1_MAX_ISDB_T_INIT];
517e61637f7b a bit cleanup
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 71
diff changeset
35 extern WBLOCK *isdb_s_initial_pt2[PT2_MAX_ISDB_S_INIT];
517e61637f7b a bit cleanup
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 71
diff changeset
36 extern WBLOCK *isdb_t_initial_pt2[PT2_MAX_ISDB_T_INIT];
0
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
37 /***************************************************************************/
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
38 /* BS用データ定義 */
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
39 /***************************************************************************/
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
40 extern WBLOCK_BS_PLL bs_pll[MAX_BS_CHANNEL] ; // 周波数テーブル
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
41 extern WBLOCK *bs_get_ts_id[(MAX_BS_TS_ID / 2)] ; // TS-ID取得テーブル
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
42 extern WBLOCK bs_tmcc_get_1; // TMCC取得テーブル
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
43 extern WBLOCK bs_tmcc_get_2; // TMCC取得テーブル
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
44 extern WBLOCK bs_get_ts_lock;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
45 extern WBLOCK bs_set_ts_lock;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
46 extern WBLOCK bs_get_slot;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
47 extern WBLOCK bs_get_clock;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
48 extern WBLOCK bs_get_carrir;
9
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
49 extern WBLOCK bs_get_signal1;
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
50 extern WBLOCK bs_get_signal2;
0
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
51 extern WBLOCK bs_get_agc;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
52 /***************************************************************************/
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
53 /* 地デジ用データ定義 */
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
54 /***************************************************************************/
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
55 extern WBLOCK isdb_t_pll_base; // 地デジ用周波数テーブルbase
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
56 extern WBLOCK isdb_t_pll_lock;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
57 extern WBLOCK_BS_PLL isdb_t_info[MAX_ISDB_T_INFO_LEN];
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
58 extern WBLOCK isdb_t_check_tune;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
59 extern WBLOCK isdb_t_tune_read;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
60 extern WBLOCK isdb_t_tmcc_read_1;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
61 extern WBLOCK isdb_t_tmcc_read_1;
9
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
62 extern WBLOCK isdb_t_signal1;
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
63 extern WBLOCK isdb_t_signal2;
07b2fc07ff48 updated to current driver to support signal strength.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
64 extern WBLOCK isdb_t_agc2;
0
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
65
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
66 extern WBLOCK isdb_t_get_clock;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
67 extern WBLOCK isdb_t_get_carrir;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
68
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
69 /***************************************************************************/
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
70 /* 省電力用データ定義 */
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
71 /***************************************************************************/
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
72 extern WBLOCK isdb_s_wake;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
73 extern WBLOCK isdb_t_wake;
102
6e661e828b43 send tuners to sleep mode when they are inactive
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 77
diff changeset
74 extern WBLOCK isdb_s_wake2;
6e661e828b43 send tuners to sleep mode when they are inactive
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 77
diff changeset
75 extern WBLOCK isdb_t_wake2;
0
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
76
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
77 extern WBLOCK isdb_s_sleep;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
78 extern WBLOCK isdb_t_sleep;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
79
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
80 extern ISDB_S_CH_TABLE isdb_t_table[11];
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
81
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
82 #endif