annotate driver/pt1_i2c.c @ 185:7a0f498af035 default tip

Fix a race condition.
author Naoya OYAMA <naoya.oyama@gmail.com>
date Wed, 14 May 2014 22:43:57 +0900
parents ee69ddb11f93
children
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
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1 /***************************************************************************/
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2 /* I2C情報作成 */
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3 /***************************************************************************/
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4 #include <linux/module.h>
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5 #include <linux/kernel.h>
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6 #include <linux/errno.h>
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7 #include <linux/pci.h>
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8 #include <linux/init.h>
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9 #include <linux/interrupt.h>
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10 #include <linux/mutex.h>
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11 #include <linux/sched.h>
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12
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13 #include <asm/io.h>
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14 #include <asm/irq.h>
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15 #include <asm/uaccess.h>
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16
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17 #include "pt1_com.h"
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18 #include "pt1_i2c.h"
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19 #include "pt1_pci.h"
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20 #include "pt1_tuner.h"
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21
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22 #define PROGRAM_ADDRESS 1024
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23 static int state = STATE_STOP ;
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24 static int i2c_lock(void __iomem *, __u32, __u32, __u32);
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25 static int i2c_lock_one(void __iomem *, __u32, __u32);
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26 static int i2c_unlock(void __iomem *, int);
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27 static void writebits(void __iomem *, __u32 *, __u32, __u32);
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28 static void begin_i2c(void __iomem *, __u32 *, __u32 *);
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29 static void start_i2c(void __iomem *, __u32 *, __u32 *, __u32);
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30 static void stop_i2c(void __iomem *, __u32 *, __u32 *, __u32, __u32);
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31
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32
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33 // PCIに書き込むI2Cデータ生成
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34 void makei2c(void __iomem *regs, __u32 base_addr, __u32 i2caddr, __u32 writemode, __u32 data_en, __u32 clock, __u32 busy)
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35 {
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36
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37 __u32 val ;
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38 val = ((base_addr << I2C_DATA) | (writemode << I2C_WRIET_MODE) |
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39 ( data_en << I2C_DATA_EN) |
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40 (clock << I2C_CLOCK) | (busy << I2C_BUSY) | i2caddr) ;
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41 writel(val, regs + FIFO_ADDR);
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42 }
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43
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44 int xc3s_init(void __iomem *regs, int cardtype)
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45 {
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46
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47 __u32 val ;
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48 int lp ;
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49 int rc ;
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50 int phase = XC3S_PCI_CLOCK;
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51
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52 /*
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53 val = (1 << 19) | (1 << 27) | (1 << 16) | (1 << 24) | (1 << 17) | (1 << 25);
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54 writel(WRITE_PULSE, regs);
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55 BIT 19, 19+8 ON
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56 BIT 16, 16+8 ON
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57 BIT 17, 17+8 ON
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58 */
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59 // XC3S初期化
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60 for(lp = 0 ; lp < PROGRAM_ADDRESS ; lp++){
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61 makei2c(regs, lp, 0, READ_EN, DATA_DIS, CLOCK_DIS, BUSY_DIS);
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62 }
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63 // XC3S 初期化待ち (512 PCI Clocks)
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64 for(lp = 0 ; lp < XC3S_PCI_CLOCK ; lp++){
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65 makei2c(regs, 0, 0, READ_EN, DATA_DIS, CLOCK_DIS, BUSY_DIS);
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66 }
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67 // プロテクト解除
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68 // これは何を意図しているんだろう?
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69 // 元コードが良く判らない
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70 for(lp = 0 ; lp < 57 ; lp++){
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71 val = readl(regs);
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72 if(val & I2C_READ_SYNC){
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73 break ;
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74 }
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75 writel(WRITE_PULSE, regs);
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76 }
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77
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78 for(lp = 0 ; lp < 57 ; lp++){
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79 val = readl(regs);
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80 if(val & READ_DATA){
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81 break ;
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82 }
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83 writel(WRITE_PULSE, regs);
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84 }
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85
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86 // UNLOCK
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87 rc = i2c_unlock(regs, READ_UNLOCK);
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88 if(rc < 0){
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89 return rc ;
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90 }
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91
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92 // Enable PCI
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93 rc =i2c_lock(regs, (WRITE_PCI_RESET | WRITE_PCI_RESET_), WRITE_PCI_RESET_, PCI_LOCKED);
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94 if(rc < 0){
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95 return -EIO ;
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96 }
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97
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98 // Enable RAM
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99 rc =i2c_lock(regs, (WRITE_RAM_RESET | WRITE_RAM_RESET_), WRITE_RAM_RESET_, RAM_LOCKED);
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100 if(rc){
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101 return -EIO ;
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102 }
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103 switch(cardtype) {
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104 case PT1:
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105 phase = XC3S_PCI_CLOCK;
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106 break;
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107 case PT2:
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108 phase = XC3S_PCI_CLOCK_PT2;
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109 break;
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110 }
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111 for(lp = 0; lp < phase; lp++){
0
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112 rc = i2c_lock_one(regs, WRITE_RAM_ENABLE, RAM_SHIFT);
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113 if(rc < 0){
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114 printk(KERN_ERR "PT1:LOCK FALUT\n");
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115 return rc ;
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116 }
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117 }
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118
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119 // ストリームごとの転送制御(OFF)
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120 for(lp = 0 ; lp < MAX_CHANNEL ; lp++){
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121 SetStream(regs, lp, 0);
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122 SetStream(regs, lp, 0);
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123 }
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124 return 0 ;
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125 }
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126 //
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127 //
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128 //BIT 0. 1 : Tuner番号 (Enable/Disable)
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129 //BIT 8. 9 : Tuner番号
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130 //
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131 //
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132 void SetStream(void __iomem *regs, __u32 channel, __u32 enable)
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133 {
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134 __u32 val ;
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135
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136 val = (1 << (8 + channel));
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137 if(enable){
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138 val |= (1 << channel);
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139 }
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140 writel(val, regs + TS_TEST_ENABLE_ADDR);
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141 }
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142
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143 static int i2c_lock(void __iomem *regs, __u32 firstval, __u32 secondval, __u32 lockval)
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144 {
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145
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146 __u32 val ;
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147 int lp ;
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148
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149 writel(firstval, regs);
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150 writel(secondval, regs);
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151
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152 // RAMがロックされた?
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153 for(lp = 0 ; lp < XC3S_PCI_CLOCK ; lp++){
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154 val = readl(regs);
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155 if((val & lockval)){
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156 return 0 ;
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157 }
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Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
158 schedule_timeout_interruptible(msecs_to_jiffies(1));
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
159 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
160 return -EIO ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
161 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
162
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
163 static int i2c_lock_one(void __iomem *regs, __u32 firstval, __u32 lockval)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
164 {
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
165
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
166 __u32 val ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
167 __u32 val2 ;
160
ee69ddb11f93 When it takes too much time to lock the RAM, addresses the problem of failed to initialize.
Naoya OYAMA <naoya.oyama@gmail.com>
parents: 137
diff changeset
168 int lp,lp2 ;
0
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
169
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
170 val = (readl(regs) & lockval);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
171 writel(firstval, regs);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
172
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
173 // RAMがロックされた?
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
174 for(lp = 0 ; lp < 10 ; lp++){
160
ee69ddb11f93 When it takes too much time to lock the RAM, addresses the problem of failed to initialize.
Naoya OYAMA <naoya.oyama@gmail.com>
parents: 137
diff changeset
175 for(lp2 = 0 ; lp2 < 1024 ; lp2++){
0
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
176 val2 = readl(regs);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
177 // 最初に取得したデータと逆になればOK
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
178 if(((val2 & lockval) != val)){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
179 return 0 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
180 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
181 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
182 schedule_timeout_interruptible(msecs_to_jiffies(1));
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
183 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
184 printk(KERN_INFO "PT1:Lock Fault(%x:%x)\n", val, val2);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
185 return -EIO ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
186 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
187 static int i2c_unlock(void __iomem *regs, int lockval)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
188 {
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
189 int lp ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
190 __u32 val ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
191
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
192 writel(WRITE_PULSE, regs);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
193
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
194 for(lp = 0 ; lp < 3 ; lp++){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
195 val = readl(regs);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
196 if((val &lockval)){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
197 return 0 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
198 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
199 schedule_timeout_interruptible(msecs_to_jiffies(1));
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
200 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
201 return -EIO ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
202 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
203 void blockwrite(void __iomem *regs, WBLOCK *wblock)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
204 {
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
205 int lp ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
206 int bitpos ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
207 __u32 bits ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
208 __u32 old_bits = 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
209 __u32 address = 0;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
210 __u32 clock = 0;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
211
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
212 begin_i2c(regs, &address, &clock);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
213 if(state == STATE_STOP){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
214 start_i2c(regs, &address, &clock, old_bits);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
215 old_bits = 0 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
216 stop_i2c(regs, &address, &clock, old_bits, FALSE);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
217 state = STATE_START ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
218 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
219 old_bits = 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
220 start_i2c(regs, &address, &clock, old_bits);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
221 old_bits = 0 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
222
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
223 // まずアドレスを書く
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
224 for(bitpos = 0 ; bitpos < 7 ; bitpos++){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
225 bits = ((wblock->addr >> (6 - bitpos)) & 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
226 writebits(regs, &address, old_bits, bits);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
227 old_bits = bits ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
228 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
229 // タイプ:WRT
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
230 writebits(regs, &address, old_bits, 0);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
231 // ACK/NACK用(必ず1)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
232 writebits(regs, &address, 0, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
233
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
234 old_bits = 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
235 // 実際のデータを書く
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
236 for (lp = 0 ; lp < wblock->count ; lp++){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
237 for(bitpos = 0 ; bitpos < 8 ; bitpos++){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
238 bits = ((wblock->value[lp] >> (7 - bitpos)) & 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
239 writebits(regs, &address, old_bits, bits);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
240 old_bits = bits ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
241 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
242 // ACK/NACK用(必ず1)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
243 writebits(regs, &address, old_bits, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
244 old_bits = 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
245 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
246
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
247 // Clock negedge
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
248 makei2c(regs, address, address + 1, 0, (old_bits ^ 1), 1, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
249 clock = TRUE ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
250 address += 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
251 stop_i2c(regs, &address, &clock, old_bits, TRUE);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
252
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
253 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
254
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
255 void blockread(void __iomem *regs, WBLOCK *wblock, int count)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
256 {
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
257 int lp ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
258 int bitpos ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
259 __u32 bits ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
260 __u32 old_bits = 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
261 __u32 address = 0;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
262 __u32 clock = 0;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
263
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
264 begin_i2c(regs, &address, &clock);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
265 if(state == STATE_STOP){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
266 start_i2c(regs, &address, &clock, old_bits);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
267 old_bits = 0 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
268 stop_i2c(regs, &address, &clock, old_bits, FALSE);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
269 state = STATE_START ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
270 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
271 old_bits = 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
272 start_i2c(regs, &address, &clock, old_bits);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
273 old_bits = 0 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
274
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
275 // まずアドレスを書く
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
276 for(bitpos = 0 ; bitpos < 7 ; bitpos++){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
277 bits = ((wblock->addr >> (6 - bitpos)) & 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
278 writebits(regs, &address, old_bits, bits);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
279 old_bits = bits ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
280 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
281 // タイプ:WRT
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
282 writebits(regs, &address, old_bits, 0);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
283 // ACK/NACK用(必ず1)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
284 writebits(regs, &address, 0, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
285
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
286 old_bits = 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
287 // 実際のデータを書く
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
288 for (lp = 0 ; lp < wblock->count ; lp++){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
289 for(bitpos = 0 ; bitpos < 8 ; bitpos++){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
290 bits = ((wblock->value[lp] >> (7 - bitpos)) & 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
291 writebits(regs, &address, old_bits, bits);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
292 old_bits = bits ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
293 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
294 // ACK/NACK用(必ず1)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
295 writebits(regs, &address, old_bits, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
296 old_bits = 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
297 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
298
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
299 // Clock negedge
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
300 makei2c(regs, address, address + 1, 0, (old_bits ^ 1), 1, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
301 clock = TRUE ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
302 address += 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
303
77
517e61637f7b a bit cleanup
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
304 // ここから Read
0
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
305 start_i2c(regs, &address, &clock, old_bits);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
306 old_bits = 0 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
307 // まずアドレスを書く
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
308 for(bitpos = 0 ; bitpos < 7 ; bitpos++){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
309 bits = ((wblock->addr >> (6 - bitpos)) & 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
310 writebits(regs, &address, old_bits, bits);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
311 old_bits = bits ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
312 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
313 // タイプ:RD
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
314 writebits(regs, &address, old_bits, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
315 // ACK/NACK用(必ず1)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
316 writebits(regs, &address, 1, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
317
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
318 old_bits = 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
319 // 実際のデータを書く
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
320 for (lp = 0 ; lp < count ; lp++){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
321 for(bitpos = 0 ; bitpos < 8 ; bitpos++){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
322 writebits(regs, &address, old_bits, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
323 // Read Mode Set
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
324 makei2c(regs, address, address + 1, 1, 0, 0, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
325 address += 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
326 old_bits = 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
327 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
328 if(lp >= (count - 1)){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
329 // ACK/NACK用(必ず1)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
330 writebits(regs, &address, old_bits, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
331 old_bits = 0 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
332 }else{
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
333 // ACK/NACK用(必ず1)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
334 writebits(regs, &address, old_bits, 0);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
335 old_bits = 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
336 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
337 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
338
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
339 // Clock negedge
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
340 makei2c(regs, address, address + 1, 0, 0, 1, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
341 clock = TRUE ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
342 address += 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
343 old_bits = 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
344 stop_i2c(regs, &address, &clock, old_bits, TRUE);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
345
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
346 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
347 static void writebits(void __iomem *regs, __u32 *address, __u32 old_bits, __u32 bits)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
348 {
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
349 // CLOCK UP
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
350 makei2c(regs, *address, *address + 1, 0, (old_bits ^ 1), 1, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
351 *address += 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
352
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
353 // CLOCK UP
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
354 makei2c(regs, *address, *address + 1, 0, (bits ^ 1), 1, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
355 *address += 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
356
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
357 // CLOCK DOWN
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
358 makei2c(regs, *address, *address + 1, 0, (bits ^ 1), 0, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
359 *address += 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
360
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
361 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
362 static void begin_i2c(void __iomem *regs, __u32 *address, __u32 *clock)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
363 {
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
364 // bus FREE
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
365 makei2c(regs, *address, *address, 0, 0, 0, 0);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
366 *address += 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
367
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
368 // bus busy
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
369 makei2c(regs, *address, *address + 1, 0, 0, 0, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
370 *address += 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
371 *clock = FALSE ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
372 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
373
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
374 static void start_i2c(void __iomem *regs, __u32 *address, __u32 *clock, __u32 data)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
375 {
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
376 // データが残っていなければデータを下げる
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
377 if(!data){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
378 // CLOCKがあればCLOCKを下げる
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
379 if(*clock != TRUE){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
380 *clock = TRUE ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
381 makei2c(regs, *address, *address + 1, 0, 1, 1, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
382 *address += 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
383 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
384 makei2c(regs, *address, *address + 1, 0, 0, 1, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
385 *address += 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
386 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
387
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
388 if(*clock != FALSE){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
389 *clock = FALSE ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
390 makei2c(regs, *address, *address + 1, 0, 0, 0, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
391 *address += 1;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
392 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
393 makei2c(regs, *address, *address + 1, 0, 1, 0, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
394 *address += 1;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
395 *clock = FALSE ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
396 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
397
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
398 static void stop_i2c(void __iomem *regs, __u32 *address, __u32 *clock, __u32 data, __u32 end)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
399 {
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
400 // データが残っていて
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
401 if(data){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
402 // クロックがあれば
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
403 if(*clock != TRUE){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
404 *clock = TRUE ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
405 makei2c(regs, *address, *address + 1, 0, 0, 1, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
406 *address += 1;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
407 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
408 makei2c(regs, *address, *address + 1, 0, 1, 1, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
409 *address += 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
410 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
411 // クロックが落ちていれば
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
412 if(*clock){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
413 *clock = FALSE ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
414 makei2c(regs, *address, *address + 1, 0, 1, 0, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
415 *address += 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
416 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
417
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
418 if(end){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
419 makei2c(regs, *address, 0, 0, 0, 0, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
420 }else{
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
421 makei2c(regs, *address, *address + 1, 0, 0, 0, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
422 *address += 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
423 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
424 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
425
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
426 void i2c_write(void __iomem *regs, struct mutex *lock, WBLOCK *wblock)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
427 {
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
428
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
429 int lp;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
430 __u32 val ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
431
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
432 // ロックする
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
433 mutex_lock(lock);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
434 #if 0
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
435 printk(KERN_INFO "Addr=%x(%d)\n", wblock->addr, wblock->count);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
436 for(lp = 0 ; lp < wblock->count ; lp++){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
437 printk(KERN_INFO "%x\n", wblock->value[lp]);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
438 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
439 printk(KERN_INFO "\n");
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
440 #endif
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
441
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
442 blockwrite(regs, wblock);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
443 writel(FIFO_GO, regs + FIFO_GO_ADDR);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
444 //とりあえずロックしないように。
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
445 for(lp = 0 ; lp < 100 ; lp++){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
446 val = readl(regs + FIFO_RESULT_ADDR);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
447 if(!(val & FIFO_DONE)){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
448 break ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
449 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
450 schedule_timeout_interruptible(msecs_to_jiffies(1));
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
451 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
452 mutex_unlock(lock);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
453 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
454
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
455 __u32 i2c_read(void __iomem *regs, struct mutex *lock, WBLOCK *wblock, int size)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
456 {
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
457
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
458 int lp;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
459 __u32 val ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
460
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
461 // ロックする
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
462 mutex_lock(lock);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
463 #if 0
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
464 printk(KERN_INFO "Addr=%x:%d:%d\n", wblock->addr, wblock->count, size);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
465 for(lp = 0 ; lp < wblock->count ; lp++){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
466 printk(KERN_INFO "%x\n", wblock->value[lp]);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
467 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
468 printk(KERN_INFO "\n");
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
469 #endif
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
470 blockread(regs, wblock, size);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
471
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
472 writel(FIFO_GO, regs + FIFO_GO_ADDR);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
473
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
474 for(lp = 0 ; lp < 100 ; lp++){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
475 schedule_timeout_interruptible(msecs_to_jiffies(1));
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
476 val = readl(regs + FIFO_RESULT_ADDR);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
477 if(!(val & FIFO_DONE)){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
478 break ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
479 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
480 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
481
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
482 val = readl(regs + I2C_RESULT_ADDR);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
483 mutex_unlock(lock);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
484 return val ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
485 }