Mercurial > pt1.oyama
annotate driver/pt1_tuner.c @ 185:7a0f498af035 default tip
Fix a race condition.
author | Naoya OYAMA <naoya.oyama@gmail.com> |
---|---|
date | Wed, 14 May 2014 22:43:57 +0900 |
parents | 13f0666bd088 |
children |
rev | line source |
---|---|
0 | 1 /* pt1-tuner.c: A PT1 on Tuner driver for Linux. */ |
2 | |
3 #include <linux/module.h> | |
4 #include <linux/kernel.h> | |
5 #include <linux/errno.h> | |
6 #include <linux/pci.h> | |
7 #include <linux/init.h> | |
8 #include <linux/interrupt.h> | |
9 #include <linux/mutex.h> | |
10 | |
11 #include <asm/io.h> | |
12 #include <asm/irq.h> | |
13 #include <asm/uaccess.h> | |
14 | |
15 #include "pt1_com.h" | |
16 #include "pt1_pci.h" | |
17 #include "pt1_i2c.h" | |
18 #include "pt1_tuner.h" | |
19 #include "pt1_tuner_data.h" | |
20 | |
21 typedef struct _TUNER_INFO{ | |
22 int isdb_s ; | |
23 int isdb_t ; | |
24 }TUNER_INFO; | |
25 | |
26 TUNER_INFO tuner_info[2] = { | |
27 {T0_ISDB_S, T0_ISDB_T}, | |
28 {T1_ISDB_S, T1_ISDB_T} | |
29 }; | |
30 | |
31 typedef struct _isdb_t_freq_add_table{ | |
32 __u16 pos ; // Äɲ乤ë¥Á¥ã¥ó¥Í¥ë¥Ý¥¸¥·¥ç¥ó | |
33 __u16 add_freq ; // Äɲ乤ëÃÍ | |
34 }isdb_t_freq_add_table; | |
35 | |
36 isdb_t_freq_add_table isdb_t_freq_add[10] = { | |
64
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
diff
changeset
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37 { 7, 0x8081}, // 0¡Á7Ëø |
0 | 38 { 12, 0x80A1}, // 8¡Á12Ëø |
39 { 21, 0x8062}, // 13¡Á21Ëø | |
40 { 39, 0x80A2}, // 22¡Á39Ëø | |
41 { 51, 0x80E2}, // 40¡Á51Ëø | |
42 { 59, 0x8064}, // 52¡Á59Ëø | |
43 { 75, 0x8084}, // 60¡Á75Ëø | |
44 { 84, 0x80a4}, // 76¡Á84Ëø | |
45 {100, 0x80C4}, // 85¡Á100Ëø | |
46 {112, 0x80E4} // 101¡Á112Ëø | |
47 }; | |
48 | |
64
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
diff
changeset
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49 void settuner_reset(void __iomem *regs, int cardtype, __u32 lnb, __u32 tuner) |
0 | 50 { |
77 | 51 __u32 val = TUNER_POWER_OFF; |
0 | 52 switch(lnb){ |
64
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
diff
changeset
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53 case LNB_11V: |
65 | 54 val = (1 << BIT_LNB_DOWN); |
55 break ; | |
64
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
diff
changeset
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56 case LNB_15V: |
65 | 57 val = (1 << BIT_LNB_UP) | (1 << BIT_LNB_DOWN); |
58 break ; | |
0 | 59 } |
60 | |
64
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
diff
changeset
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61 if(cardtype == PT1) { |
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
diff
changeset
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62 switch(tuner){ |
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
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changeset
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63 case TUNER_POWER_ON_RESET_ENABLE: |
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
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changeset
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64 val |= (1 << BIT_TUNER); |
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
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changeset
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65 break; |
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
diff
changeset
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66 case TUNER_POWER_ON_RESET_DISABLE: |
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
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changeset
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67 val |= (1 << BIT_TUNER) | (1 << BIT_RESET); |
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
diff
changeset
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68 break ; |
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
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changeset
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69 } |
0 | 70 } |
64
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
diff
changeset
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71 else if(cardtype == PT2) { |
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
diff
changeset
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72 switch(tuner){ |
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
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changeset
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73 case TUNER_POWER_ON_RESET_ENABLE: |
69
272a8fba970b
added very rough support for PT2.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
65
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74 val |= (1 << BIT_TUNER) |
272a8fba970b
added very rough support for PT2.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
65
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75 | (1 << BIT_33A1) |
272a8fba970b
added very rough support for PT2.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
65
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76 | (1 << BIT_33A2) |
272a8fba970b
added very rough support for PT2.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
65
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77 | (1 << BIT_5A_) |
272a8fba970b
added very rough support for PT2.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
65
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78 | (1 << BIT_5A1) |
272a8fba970b
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Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
65
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79 | (1 << BIT_5A2); |
64
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
diff
changeset
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80 break; |
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
diff
changeset
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81 case TUNER_POWER_ON_RESET_DISABLE: |
69
272a8fba970b
added very rough support for PT2.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
65
diff
changeset
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82 val |= (1 << BIT_TUNER) |
272a8fba970b
added very rough support for PT2.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
65
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83 | (1 << BIT_RESET) |
272a8fba970b
added very rough support for PT2.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
65
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changeset
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84 | (1 << BIT_33A1) |
272a8fba970b
added very rough support for PT2.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
65
diff
changeset
|
85 | (1 << BIT_33A2) |
272a8fba970b
added very rough support for PT2.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
65
diff
changeset
|
86 | (1 << BIT_5A_) |
272a8fba970b
added very rough support for PT2.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
65
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changeset
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87 | (1 << BIT_5A1) |
272a8fba970b
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Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
65
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changeset
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88 | (1 << BIT_5A2); |
64
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
diff
changeset
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89 break ; |
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
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90 } |
98a92ce5382e
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Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
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changeset
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91 } |
98a92ce5382e
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Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
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92 writel(val, (regs + CFG_REGS_ADDR)); |
0 | 93 } |
69
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parents:
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94 static int init_isdb_s(void __iomem *regs, int cardtype, struct mutex *lock, __u32 addr) |
0 | 95 { |
96 | |
97 WBLOCK wk; | |
98 int lp ; | |
99 __u32 val ; | |
100 | |
101 // ISDB-S/T½é´ü²½ | |
102 memcpy(&wk, &com_initdata, sizeof(WBLOCK)); | |
103 | |
104 // ½é´ü²½£±(¤Ê¤¼¤«READ¤Ê¤Î¤Ç) | |
105 memcpy(&wk, &isdb_s_init1, sizeof(WBLOCK)); | |
106 wk.addr = addr; | |
107 val = i2c_read(regs, lock, &wk, 1); | |
71
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108 |
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109 if(cardtype == PT1) { |
79 | 110 if((val & 0xff) != 0x4c) { |
111 printk(KERN_INFO "PT1:ISDB-S Read(%x)\n", val); | |
112 return -EIO ; | |
113 } | |
114 for(lp = 0 ; lp < PT1_MAX_ISDB_S_INIT ; lp++) { | |
69
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115 memcpy(&wk, isdb_s_initial_pt1[lp], sizeof(WBLOCK)); |
71
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116 wk.addr = addr; |
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117 i2c_write(regs, lock, &wk); |
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118 } |
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119 } |
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120 else if(cardtype == PT2) { |
79 | 121 if((val & 0xff) != 0x52) { |
122 printk(KERN_INFO "PT2:ISDB-S Read(%x)\n", val); | |
123 return -EIO ; | |
124 } | |
125 for(lp = 0 ; lp < PT2_MAX_ISDB_S_INIT ; lp++) { | |
69
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126 memcpy(&wk, isdb_s_initial_pt2[lp], sizeof(WBLOCK)); |
71
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127 wk.addr = addr; |
28f25ec7f962
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128 i2c_write(regs, lock, &wk); |
28f25ec7f962
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129 } |
0 | 130 } |
131 | |
132 return 0 ; | |
133 } | |
69
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134 static void init_isdb_t(void __iomem *regs, int cardtype, struct mutex *lock, __u32 addr) |
0 | 135 { |
136 int lp ; | |
137 WBLOCK wk; | |
138 | |
139 // ISDB-S/T½é´ü²½ | |
71
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140 if(cardtype == PT1) { |
77 | 141 for(lp = 0 ; lp < PT1_MAX_ISDB_T_INIT ; lp++){ |
69
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parents:
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142 memcpy(&wk, isdb_t_initial_pt1[lp], sizeof(WBLOCK)); |
71
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143 wk.addr = addr; |
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144 i2c_write(regs, lock, &wk); |
28f25ec7f962
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145 } |
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Yoshiki Yazawa <yaz@honeyplanet.jp>
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146 } |
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147 else if(cardtype == PT2) { |
77 | 148 for(lp = 0 ; lp < PT2_MAX_ISDB_T_INIT ; lp++){ |
69
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parents:
65
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149 memcpy(&wk, isdb_t_initial_pt2[lp], sizeof(WBLOCK)); |
71
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150 wk.addr = addr; |
28f25ec7f962
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151 i2c_write(regs, lock, &wk); |
28f25ec7f962
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Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
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152 } |
0 | 153 } |
71
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parents:
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154 } |
0 | 155 |
69
272a8fba970b
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Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
65
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156 int tuner_init(void __iomem *regs, int cardtype, struct mutex *lock, int tuner_no) |
0 | 157 { |
158 | |
159 int rc ; | |
160 WBLOCK wk; | |
161 | |
162 // ISDB-S/T½é´ü²½ | |
163 memcpy(&wk, &com_initdata, sizeof(WBLOCK)); | |
164 | |
165 // ½é´ü²½(¶¦ÄÌ) | |
166 wk.addr = tuner_info[tuner_no].isdb_t ; | |
167 i2c_write(regs, lock, &wk); | |
168 wk.addr = tuner_info[tuner_no].isdb_s ; | |
169 i2c_write(regs, lock, &wk); | |
170 | |
69
272a8fba970b
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Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
65
diff
changeset
|
171 rc = init_isdb_s(regs, cardtype, lock, tuner_info[tuner_no].isdb_s); |
0 | 172 if(rc < 0){ |
173 return rc ; | |
174 } | |
69
272a8fba970b
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Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
65
diff
changeset
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175 init_isdb_t(regs, cardtype, lock, tuner_info[tuner_no].isdb_t); |
0 | 176 |
177 memcpy(&wk, &isdb_s_init21, sizeof(WBLOCK)); | |
178 wk.addr = tuner_info[tuner_no].isdb_s ; | |
179 i2c_write(regs, lock, &wk); | |
180 | |
181 memcpy(&wk, &isdb_t_init17, sizeof(WBLOCK)); | |
182 wk.addr = tuner_info[tuner_no].isdb_t ; | |
183 i2c_write(regs, lock, &wk); | |
184 | |
185 return 0 ; | |
186 } | |
187 void set_sleepmode(void __iomem *regs, struct mutex *lock, int address, int tuner_type, int type) | |
188 { | |
189 WBLOCK wk; | |
190 | |
191 if(type == TYPE_WAKEUP){ | |
192 switch(tuner_type){ | |
77 | 193 case CHANNEL_TYPE_ISDB_S: |
194 printk(KERN_INFO "PT1:ISDB-S Wakeup\n"); | |
195 memcpy(&wk, &isdb_s_wake, sizeof(WBLOCK)); | |
102
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parents:
94
diff
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196 wk.addr = address; |
77 | 197 i2c_write(regs, lock, &wk); |
198 | |
102
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199 memcpy(&wk, &isdb_s_wake2, sizeof(WBLOCK)); |
6e661e828b43
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parents:
94
diff
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200 wk.addr = address; |
77 | 201 i2c_write(regs, lock, &wk); |
202 break ; | |
203 case CHANNEL_TYPE_ISDB_T: | |
204 printk(KERN_INFO "PT1:ISDB-T Wakeup\n"); | |
205 memcpy(&wk, &isdb_t_wake, sizeof(WBLOCK)); | |
102
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94
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206 wk.addr = address; |
77 | 207 i2c_write(regs, lock, &wk); |
208 | |
102
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94
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209 memcpy(&wk, &isdb_t_wake2, sizeof(WBLOCK)); |
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210 wk.addr = address; |
77 | 211 i2c_write(regs, lock, &wk); |
212 break ; | |
0 | 213 } |
214 } | |
77 | 215 if(type == TYPE_SLEEP){ |
216 switch(tuner_type){ | |
0 | 217 case CHANNEL_TYPE_ISDB_S: |
218 printk(KERN_INFO "PT1:ISDB-S Sleep\n"); | |
219 memcpy(&wk, &isdb_s_sleep, sizeof(WBLOCK)); | |
77 | 220 wk.addr = address; |
221 i2c_write(regs, lock, &wk); | |
0 | 222 break ; |
223 case CHANNEL_TYPE_ISDB_T: | |
224 printk(KERN_INFO "PT1:ISDB-T Sleep\n"); | |
225 memcpy(&wk, &isdb_t_sleep, sizeof(WBLOCK)); | |
77 | 226 wk.addr = address; |
227 i2c_write(regs, lock, &wk); | |
0 | 228 break ; |
77 | 229 } |
0 | 230 } |
231 } | |
232 | |
233 int bs_frequency(void __iomem *regs, struct mutex *lock, int addr, int channel) | |
234 { | |
235 int lp ; | |
236 int tmcclock = FALSE ; | |
237 WBLOCK wk; | |
238 __u32 val ; | |
239 | |
240 if(channel >= MAX_BS_CHANNEL){ | |
241 return -EIO ; | |
242 } | |
243 // ISDB-S PLL¥í¥Ã¥¯ | |
244 for(lp = 0 ; lp < MAX_BS_CHANNEL_PLL_COMMAND ; lp++){ | |
245 memcpy(&wk, bs_pll[channel].wblock[lp], sizeof(WBLOCK)); | |
246 wk.addr = addr ; | |
247 i2c_write(regs, lock, &wk); | |
248 } | |
249 | |
250 // PLL¥í¥Ã¥¯³Îǧ | |
251 // ¥Á¥§¥Ã¥¯ÍÑ | |
252 for(lp = 0 ; lp < 200 ; lp++){ | |
253 memcpy(&wk, &bs_pll_lock, sizeof(WBLOCK)); | |
254 wk.addr = addr; | |
255 val = i2c_read(regs, lock, &wk, 1); | |
256 if(((val & 0xFF) != 0) && ((val & 0XFF) != 0XFF)){ | |
257 tmcclock = TRUE ; | |
258 break ; | |
259 } | |
260 } | |
261 | |
262 if(tmcclock == FALSE){ | |
263 printk(KERN_INFO "PLL LOCK ERROR\n"); | |
264 return -EIO; | |
265 } | |
266 | |
267 memcpy(&wk, &bs_tmcc_get_1, sizeof(WBLOCK)); | |
268 wk.addr = addr; | |
269 i2c_write(regs, lock, &wk); | |
270 | |
271 tmcclock = FALSE ; | |
272 | |
273 for(lp = 0 ; lp < 200 ; lp++){ | |
274 memcpy(&wk, &bs_tmcc_get_2, sizeof(WBLOCK)); | |
275 wk.addr = addr; | |
276 | |
277 val = i2c_read(regs, lock, &wk, 1); | |
278 if(((val & 0XFF) != 0XFF) && (!(val & 0x10))){ | |
279 tmcclock = TRUE ; | |
280 break ; | |
281 } | |
282 } | |
283 | |
284 if(tmcclock == FALSE){ | |
285 printk(KERN_INFO "TMCC LOCK ERROR\n"); | |
286 return -EIO; | |
287 } | |
288 | |
289 return 0 ; | |
290 } | |
291 int ts_lock(void __iomem *regs, struct mutex *lock, int addr, __u16 ts_id) | |
292 { | |
293 | |
294 int lp ; | |
295 WBLOCK wk; | |
296 __u32 val ; | |
297 union{ | |
298 __u8 ts[2]; | |
299 __u16 tsid; | |
300 }uts_id ; | |
301 | |
302 uts_id.tsid = ts_id ; | |
303 memcpy(&wk, &bs_set_ts_lock, sizeof(WBLOCK)); | |
304 wk.addr = addr; | |
305 // TS-IDÀßÄê | |
306 wk.value[1] = uts_id.ts[1]; | |
307 wk.value[2] = uts_id.ts[0]; | |
308 i2c_write(regs, lock, &wk); | |
309 | |
310 for(lp = 0 ; lp < 100 ; lp++){ | |
311 memcpy(&wk, &bs_get_ts_lock, sizeof(WBLOCK)); | |
312 wk.addr = addr; | |
313 val = i2c_read(regs, lock, &wk, 2); | |
314 if((val & 0xFFFF) == ts_id){ | |
315 return 0 ; | |
316 } | |
317 } | |
318 printk(KERN_INFO "PT1:ERROR TS-LOCK(%x)\n", ts_id); | |
319 return -EIO ; | |
320 } | |
321 int bs_tune(void __iomem *regs, struct mutex *lock, int addr, int channel, ISDB_S_TMCC *tmcc) | |
322 { | |
323 | |
324 int lp ; | |
325 int lp2; | |
326 WBLOCK wk; | |
327 __u32 val ; | |
328 ISDB_S_TS_ID *tsid ; | |
329 union{ | |
330 __u8 slot[4]; | |
331 __u32 u32slot; | |
332 }ts_slot ; | |
333 union{ | |
334 __u16 ts[2]; | |
335 __u32 tsid; | |
336 }ts_id ; | |
337 | |
338 if(channel >= MAX_BS_CHANNEL){ | |
339 printk(KERN_INFO "Invalid Channel(%d)\n", channel); | |
340 return -EIO ; | |
341 } | |
342 val = bs_frequency(regs, lock, addr, channel); | |
343 if(val == -EIO){ | |
344 return val ; | |
345 } | |
346 | |
347 tsid = &tmcc->ts_id[0] ; | |
348 // ³ºÅö¼þÇÈ¿ô¤ÎTS-ID¤ò¼èÆÀ | |
349 for(lp = 0 ; lp < (MAX_BS_TS_ID / 2) ; lp++){ | |
350 for(lp2 = 0 ; lp2 < 100 ; lp2++){ | |
351 memcpy(&wk, bs_get_ts_id[lp], sizeof(WBLOCK)); | |
352 wk.addr = addr; | |
353 ts_id.tsid = i2c_read(regs, lock, &wk, 4); | |
354 // TS-ID¤¬0¤Î¾ì¹ç¤ÏºÆ¼èÆÀ¤¹¤ë | |
355 if((ts_id.ts[0] != 0) && (ts_id.ts[1] != 0)){ | |
356 break ; | |
357 } | |
358 } | |
359 tsid->ts_id = ts_id.ts[1] ; | |
360 tsid += 1; | |
361 tsid->ts_id = ts_id.ts[0] ; | |
362 tsid += 1; | |
363 } | |
364 | |
365 memcpy(&wk, &bs_get_agc, sizeof(WBLOCK)); | |
366 wk.addr = addr; | |
367 tmcc->agc = i2c_read(regs, lock, &wk, 1); | |
368 | |
369 // TS-IDÊ̤ξðÊó¤ò¼èÆÀ | |
370 tsid = &tmcc->ts_id[0] ; | |
371 for(lp = 0 ; lp < MAX_BS_TS_ID ; lp++, tsid += 1){ | |
372 // TS-ID¤Ê¤·=0XFFFF | |
373 if(tsid->ts_id == 0xFFFF){ | |
374 continue ; | |
375 } | |
376 ts_lock(regs, lock, addr, tsid->ts_id); | |
377 | |
378 //¥¹¥í¥Ã¥È¼èÆÀ | |
379 memcpy(&wk, &bs_get_slot, sizeof(WBLOCK)); | |
380 wk.addr = addr; | |
381 ts_slot.u32slot = i2c_read(regs, lock, &wk, 3); | |
382 tsid->high_mode = 0; | |
383 tsid->low_slot = ts_slot.slot[0] ; | |
384 tsid->high_slot = ts_slot.slot[1] ; | |
385 tsid->low_mode = ts_slot.slot[2] ; | |
386 } | |
387 | |
388 memcpy(&wk, &bs_get_clock, sizeof(WBLOCK)); | |
389 wk.addr = addr; | |
390 tmcc->clockmargin = i2c_read(regs, lock, &wk, 1); | |
391 | |
392 memcpy(&wk, &bs_get_carrir, sizeof(WBLOCK)); | |
393 wk.addr = addr; | |
394 tmcc->carriermargin = i2c_read(regs, lock, &wk, 1); | |
395 return 0 ; | |
396 } | |
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397 int isdb_s_read_signal_strength(void __iomem *regs, struct mutex *lock, int addr) |
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398 { |
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399 WBLOCK wk; |
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400 __u32 val ; |
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401 __u32 val2; |
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402 int val3 ; |
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403 |
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404 memcpy(&wk, &bs_get_signal1, sizeof(WBLOCK)); |
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405 wk.addr = addr; |
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406 val = i2c_read(regs, lock, &wk, 1); |
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407 |
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408 memcpy(&wk, &bs_get_signal2, sizeof(WBLOCK)); |
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409 wk.addr = addr; |
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410 val2 = i2c_read(regs, lock, &wk, 1); |
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411 val3 = (((val << 8) & 0XFF00) | (val2 & 0XFF)); |
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412 |
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413 return val3 ; |
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414 } |
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415 |
0 | 416 __u32 getfrequency_add(__u32 channel) |
417 { | |
418 int lp ; | |
419 | |
420 for(lp = 0 ; lp < 10 ; lp++){ | |
421 if(channel <= isdb_t_freq_add[lp].pos){ | |
422 return isdb_t_freq_add[lp].add_freq ; | |
423 } | |
424 } | |
425 return 0 ; | |
426 } | |
427 __u32 getfrequency(__u32 channel, int addfreq) | |
428 { | |
429 __u32 frequencyoffset = 0; | |
430 __u32 frequencyOffset = 0; | |
431 | |
94
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432 if (12 <= channel) |
0 | 433 frequencyoffset += 2; |
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434 if (17 <= channel) |
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435 frequencyoffset -= 2; |
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436 if (63 <= channel){ |
0 | 437 frequencyoffset += 2; |
438 } | |
439 #if 0 | |
440 return (((93 + channel * 6 + frequencyOffset) + addfreq) * 7) + 400; | |
441 #endif | |
442 frequencyOffset = 93 + channel * 6 + frequencyoffset; | |
443 frequencyOffset = 7 * (frequencyOffset + addfreq); | |
444 return frequencyOffset + 400; | |
445 | |
446 } | |
447 int isdb_t_frequency(void __iomem *regs, struct mutex *lock, int addr, int channel, int addfreq) | |
448 { | |
449 | |
450 int lp ; | |
451 WBLOCK wk; | |
452 __u32 val ; | |
453 int tmcclock = FALSE ; | |
454 union{ | |
455 __u8 charfreq[2]; | |
456 __u16 freq; | |
457 }freq[2] ; | |
458 | |
459 if(channel >= MAX_ISDB_T_CHANNEL){ | |
182
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460 printk(KERN_INFO "PT1:ISDB-T CHANNEL OVER(%i:113)\n", channel); |
0 | 461 return -EIO ; |
462 } | |
463 | |
464 freq[0].freq = getfrequency(channel, addfreq); | |
465 freq[1].freq = getfrequency_add(channel); | |
466 //»ØÄê¼þÇÈ¿ô | |
467 memcpy(&wk, &isdb_t_pll_base, sizeof(WBLOCK)); | |
468 wk.addr = addr ; | |
469 // ·×»»¤·¤¿¼þÇÈ¿ô¤òÀßÄê | |
470 wk.value[wk.count] = freq[0].charfreq[1]; | |
471 wk.count += 1 ; | |
472 wk.value[wk.count] = freq[0].charfreq[0]; | |
473 wk.count += 1 ; | |
474 | |
475 // ·×»»¤·¤¿¼þÇÈ¿ôÉղþðÊó¤òÀßÄê | |
476 wk.value[wk.count] = freq[1].charfreq[1]; | |
477 wk.count += 1 ; | |
478 wk.value[wk.count] = freq[1].charfreq[0]; | |
479 wk.count += 1 ; | |
480 | |
481 i2c_write(regs, lock, &wk); | |
482 | |
483 for(lp = 0 ; lp < 100 ; lp++){ | |
484 memcpy(&wk, &isdb_t_pll_lock, sizeof(WBLOCK)); | |
485 wk.addr = addr; | |
486 val = i2c_read(regs, lock, &wk, 1); | |
487 if(((val & 0xFF) != 0XFF) && ((val & 0X50) == 0x50)){ | |
488 tmcclock = TRUE ; | |
489 break ; | |
490 } | |
491 } | |
492 if(tmcclock != TRUE){ | |
182
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493 printk(KERN_INFO "PT1:ISDB-T PLL LOCK NG(%08x)\n", val); |
0 | 494 return -EIO ; |
495 } | |
496 | |
497 memcpy(&wk, &isdb_t_check_tune, sizeof(WBLOCK)); | |
498 wk.addr = addr ; | |
499 i2c_write(regs, lock, &wk); | |
500 | |
501 tmcclock = FALSE ; | |
502 for(lp = 0 ; lp < 1000 ; lp++){ | |
503 memcpy(&wk, &isdb_t_tune_read, sizeof(WBLOCK)); | |
504 wk.addr = addr; | |
505 val = i2c_read(regs, lock, &wk, 1); | |
506 if(((val & 0xFF) != 0XFF) && ((val & 0X8) != 8)){ | |
507 tmcclock = TRUE ; | |
508 break ; | |
509 } | |
510 } | |
511 if(tmcclock != TRUE){ | |
182
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512 printk(KERN_INFO "PT1:ISDB-T TUNE READ NG(%08x)\n", val); |
0 | 513 return -EIO ; |
514 } | |
515 return 0 ; | |
516 } | |
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517 int isdb_t_read_signal_strength(void __iomem *regs, struct mutex *lock, int addr) |
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518 { |
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519 __u32 val ; |
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520 __u32 val2; |
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521 __u32 val3; |
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522 WBLOCK wk; |
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523 |
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524 memcpy(&wk, &isdb_t_signal1, sizeof(WBLOCK)); |
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525 wk.addr = addr; |
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526 val = i2c_read(regs, lock, &wk, 1); |
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527 printk(KERN_INFO "CN(1)Val(%x)\n", val); |
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528 |
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529 memcpy(&wk, &isdb_t_signal2, sizeof(WBLOCK)); |
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530 wk.addr = addr; |
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531 val2 = i2c_read(regs, lock, &wk, 1); |
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532 val3 = (((val << 8) & 0XFF00) | (val2 & 0XFF)); |
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533 return val3 ; |
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534 } |
0 | 535 #if 0 |
536 int isdb_t_tune(void __iomem *regs, struct mutex *lock, int addr, int channel, ISDB_T_TMCC *tmcc) | |
537 { | |
538 | |
539 int lp ; | |
540 int rc ; | |
541 int lp2 ; | |
542 WBLOCK wk; | |
543 __u32 val ; | |
544 | |
545 printk(KERN_INFO "Channel(%d) Start\n", channel); | |
546 if(channel >= MAX_ISDB_T_CHANNEL){ | |
547 return -EIO ; | |
548 } | |
549 rc = isdb_t_frequency(regs, lock, addr, channel); | |
550 if(rc < 0){ | |
551 return -EIO ; | |
552 } | |
553 for(lp = 0 ; lp < 100 ; lp++){ | |
554 memcpy(&wk, &isdb_t_tmcc_read_1, sizeof(WBLOCK)); | |
555 wk.addr = addr; | |
556 val = i2c_read(regs, lock, &wk, 4); | |
557 if((val & 0xFF) != 0){ | |
558 break ; | |
559 } | |
560 } | |
561 printk(KERN_INFO "TMCC(1)Val(%x)\n", val); | |
562 | |
563 for(lp = 0 ; lp < 100 ; lp++){ | |
564 memcpy(&wk, &isdb_t_tmcc_read_2, sizeof(WBLOCK)); | |
565 wk.addr = addr; | |
566 val = i2c_read(regs, lock, &wk, 4); | |
567 if((val & 0xFF) != 0){ | |
568 break ; | |
569 } | |
570 } | |
571 printk(KERN_INFO "TMCC(2)Val(%x)\n", val); | |
572 | |
573 memcpy(&wk, &isdb_t_cn_1, sizeof(WBLOCK)); | |
574 wk.addr = addr; | |
575 val = i2c_read(regs, lock, &wk, 1); | |
576 printk(KERN_INFO "CN(1)Val(%x)\n", val); | |
577 | |
578 memcpy(&wk, &isdb_t_cn_2, sizeof(WBLOCK)); | |
579 wk.addr = addr; | |
580 val = i2c_read(regs, lock, &wk, 1); | |
581 printk(KERN_INFO "CN(2)Val(%x)\n", val); | |
582 | |
583 memcpy(&wk, &isdb_t_agc_1, sizeof(WBLOCK)); | |
584 wk.addr = addr; | |
585 val = i2c_read(regs, lock, &wk, 1); | |
586 printk(KERN_INFO "AGC(1)Val(%x)\n", val); | |
587 | |
588 memcpy(&wk, &isdb_t_agc_2, sizeof(WBLOCK)); | |
589 wk.addr = addr; | |
590 val = i2c_read(regs, lock, &wk, 1); | |
591 printk(KERN_INFO "AGC(2)Val(%x)\n", val); | |
592 return 0; | |
593 } | |
594 #endif |