annotate driver/pt1_i2c.c @ 116:38a793ac3d9d

- fix version string - tweak option definitions
author Yoshiki Yazawa <yaz@honeyplanet.jp>
date Thu, 25 Mar 2010 20:47:09 +0900
parents b8032e8099de
children 2dc994610477
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1 /***************************************************************************/
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2 /* I2C情報作成 */
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3 /***************************************************************************/
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4 #include <linux/module.h>
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5 #include <linux/kernel.h>
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6 #include <linux/errno.h>
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7 #include <linux/pci.h>
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8 #include <linux/init.h>
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9 #include <linux/interrupt.h>
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10 #include <linux/mutex.h>
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11 #include <linux/sched.h>
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12
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13 #include <asm/system.h>
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14 #include <asm/io.h>
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15 #include <asm/irq.h>
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16 #include <asm/uaccess.h>
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17
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18 #include "pt1_com.h"
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19 #include "pt1_i2c.h"
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20 #include "pt1_pci.h"
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21 #include "pt1_tuner.h"
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22
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23 #define PROGRAM_ADDRESS 1024
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24 static int state = STATE_STOP ;
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25 static int i2c_lock(void __iomem *, __u32, __u32, __u32);
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26 static int i2c_lock_one(void __iomem *, __u32, __u32);
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27 static int i2c_unlock(void __iomem *, int);
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28 static void writebits(void __iomem *, __u32 *, __u32, __u32);
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29 static void begin_i2c(void __iomem *, __u32 *, __u32 *);
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30 static void start_i2c(void __iomem *, __u32 *, __u32 *, __u32);
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31 static void stop_i2c(void __iomem *, __u32 *, __u32 *, __u32, __u32);
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32
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33
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34 // PCIに書き込むI2Cデータ生成
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35 void makei2c(void __iomem *regs, __u32 base_addr, __u32 i2caddr, __u32 writemode, __u32 data_en, __u32 clock, __u32 busy)
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36 {
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37
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38 __u32 val ;
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39 val = ((base_addr << I2C_DATA) | (writemode << I2C_WRIET_MODE) |
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40 ( data_en << I2C_DATA_EN) |
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41 (clock << I2C_CLOCK) | (busy << I2C_BUSY) | i2caddr) ;
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42 writel(val, regs + FIFO_ADDR);
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43 }
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44
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45 int xc3s_init(void __iomem *regs, int cardtype)
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46 {
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47
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48 __u32 val ;
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49 int lp ;
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50 int rc ;
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51 int phase = XC3S_PCI_CLOCK;
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52
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53 /*
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54 val = (1 << 19) | (1 << 27) | (1 << 16) | (1 << 24) | (1 << 17) | (1 << 25);
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55 writel(WRITE_PULSE, regs);
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56 BIT 19, 19+8 ON
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57 BIT 16, 16+8 ON
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58 BIT 17, 17+8 ON
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59 */
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60 // XC3S初期化
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61 for(lp = 0 ; lp < PROGRAM_ADDRESS ; lp++){
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62 makei2c(regs, lp, 0, READ_EN, DATA_DIS, CLOCK_DIS, BUSY_DIS);
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63 }
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64 // XC3S 初期化待ち (512 PCI Clocks)
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65 for(lp = 0 ; lp < XC3S_PCI_CLOCK ; lp++){
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66 makei2c(regs, 0, 0, READ_EN, DATA_DIS, CLOCK_DIS, BUSY_DIS);
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67 }
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68 // プロテクト解除
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69 // これは何を意図しているんだろう?
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70 // 元コードが良く判らない
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71 for(lp = 0 ; lp < 57 ; lp++){
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72 val = readl(regs);
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73 if(val & I2C_READ_SYNC){
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74 break ;
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75 }
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76 writel(WRITE_PULSE, regs);
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77 }
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78
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79 for(lp = 0 ; lp < 57 ; lp++){
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80 val = readl(regs);
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81 if(val & READ_DATA){
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82 break ;
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83 }
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84 writel(WRITE_PULSE, regs);
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85 }
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86
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87 // UNLOCK
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88 rc = i2c_unlock(regs, READ_UNLOCK);
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89 if(rc < 0){
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90 return rc ;
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91 }
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92
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93 // Enable PCI
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94 rc =i2c_lock(regs, (WRITE_PCI_RESET | WRITE_PCI_RESET_), WRITE_PCI_RESET_, PCI_LOCKED);
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95 if(rc < 0){
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96 return -EIO ;
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97 }
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98
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99 // Enable RAM
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100 rc =i2c_lock(regs, (WRITE_RAM_RESET | WRITE_RAM_RESET_), WRITE_RAM_RESET_, RAM_LOCKED);
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101 if(rc){
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102 return -EIO ;
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103 }
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104 switch(cardtype) {
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105 case PT1:
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106 phase = XC3S_PCI_CLOCK;
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107 break;
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108 case PT2:
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109 phase = XC3S_PCI_CLOCK_PT2;
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110 break;
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111 }
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112 for(lp = 0; lp < phase; lp++){
0
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113 rc = i2c_lock_one(regs, WRITE_RAM_ENABLE, RAM_SHIFT);
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114 if(rc < 0){
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115 printk(KERN_ERR "PT1:LOCK FALUT\n");
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116 return rc ;
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117 }
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118 }
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119
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120 // ストリームごとの転送制御(OFF)
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121 for(lp = 0 ; lp < MAX_CHANNEL ; lp++){
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122 SetStream(regs, lp, 0);
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123 SetStream(regs, lp, 0);
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124 }
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125 return 0 ;
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126 }
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127 //
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128 //
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129 //BIT 0. 1 : Tuner番号 (Enable/Disable)
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130 //BIT 8. 9 : Tuner番号
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131 //
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132 //
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133 void SetStream(void __iomem *regs, __u32 channel, __u32 enable)
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134 {
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135 __u32 val ;
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136
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137 val = (1 << (8 + channel));
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138 if(enable){
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139 val |= (1 << channel);
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140 }
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141 writel(val, regs + TS_TEST_ENABLE_ADDR);
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142 }
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143
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144 static int i2c_lock(void __iomem *regs, __u32 firstval, __u32 secondval, __u32 lockval)
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145 {
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146
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147 __u32 val ;
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148 int lp ;
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149
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150 writel(firstval, regs);
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151 writel(secondval, regs);
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152
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153 // RAMがロックされた?
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154 for(lp = 0 ; lp < XC3S_PCI_CLOCK ; lp++){
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155 val = readl(regs);
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156 if((val & lockval)){
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157 return 0 ;
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parents:
diff changeset
158 }
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Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
159 schedule_timeout_interruptible(msecs_to_jiffies(1));
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Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
160 }
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Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
161 return -EIO ;
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Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
162 }
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Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
163
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parents:
diff changeset
164 static int i2c_lock_one(void __iomem *regs, __u32 firstval, __u32 lockval)
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diff changeset
165 {
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parents:
diff changeset
166
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parents:
diff changeset
167 __u32 val ;
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parents:
diff changeset
168 __u32 val2 ;
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parents:
diff changeset
169 int lp ;
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parents:
diff changeset
170
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diff changeset
171 val = (readl(regs) & lockval);
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parents:
diff changeset
172 writel(firstval, regs);
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parents:
diff changeset
173
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parents:
diff changeset
174 // RAMがロックされた?
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parents:
diff changeset
175 for(lp = 0 ; lp < 10 ; lp++){
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parents:
diff changeset
176 for(lp = 0 ; lp < 1024 ; lp++){
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parents:
diff changeset
177 val2 = readl(regs);
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parents:
diff changeset
178 // 最初に取得したデータと逆になればOK
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parents:
diff changeset
179 if(((val2 & lockval) != val)){
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parents:
diff changeset
180 return 0 ;
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Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
181 }
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Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
182 }
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parents:
diff changeset
183 schedule_timeout_interruptible(msecs_to_jiffies(1));
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parents:
diff changeset
184 }
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parents:
diff changeset
185 printk(KERN_INFO "PT1:Lock Fault(%x:%x)\n", val, val2);
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parents:
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186 return -EIO ;
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parents:
diff changeset
187 }
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parents:
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188 static int i2c_unlock(void __iomem *regs, int lockval)
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parents:
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189 {
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190 int lp ;
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parents:
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191 __u32 val ;
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parents:
diff changeset
192
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193 writel(WRITE_PULSE, regs);
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parents:
diff changeset
194
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parents:
diff changeset
195 for(lp = 0 ; lp < 3 ; lp++){
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196 val = readl(regs);
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parents:
diff changeset
197 if((val &lockval)){
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parents:
diff changeset
198 return 0 ;
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parents:
diff changeset
199 }
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parents:
diff changeset
200 schedule_timeout_interruptible(msecs_to_jiffies(1));
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Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
201 }
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Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
202 return -EIO ;
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Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
203 }
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Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
204 void blockwrite(void __iomem *regs, WBLOCK *wblock)
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parents:
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205 {
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206 int lp ;
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diff changeset
207 int bitpos ;
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diff changeset
208 __u32 bits ;
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parents:
diff changeset
209 __u32 old_bits = 1 ;
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parents:
diff changeset
210 __u32 address = 0;
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Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
211 __u32 clock = 0;
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Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
212
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diff changeset
213 begin_i2c(regs, &address, &clock);
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Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
214 if(state == STATE_STOP){
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parents:
diff changeset
215 start_i2c(regs, &address, &clock, old_bits);
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parents:
diff changeset
216 old_bits = 0 ;
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parents:
diff changeset
217 stop_i2c(regs, &address, &clock, old_bits, FALSE);
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parents:
diff changeset
218 state = STATE_START ;
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parents:
diff changeset
219 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
220 old_bits = 1 ;
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parents:
diff changeset
221 start_i2c(regs, &address, &clock, old_bits);
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Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
222 old_bits = 0 ;
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Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
223
67e8eca28a80 initial import
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parents:
diff changeset
224 // まずアドレスを書く
67e8eca28a80 initial import
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parents:
diff changeset
225 for(bitpos = 0 ; bitpos < 7 ; bitpos++){
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parents:
diff changeset
226 bits = ((wblock->addr >> (6 - bitpos)) & 1);
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parents:
diff changeset
227 writebits(regs, &address, old_bits, bits);
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diff changeset
228 old_bits = bits ;
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parents:
diff changeset
229 }
67e8eca28a80 initial import
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parents:
diff changeset
230 // タイプ:WRT
67e8eca28a80 initial import
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parents:
diff changeset
231 writebits(regs, &address, old_bits, 0);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
232 // ACK/NACK用(必ず1)
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parents:
diff changeset
233 writebits(regs, &address, 0, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
234
67e8eca28a80 initial import
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parents:
diff changeset
235 old_bits = 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
236 // 実際のデータを書く
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
237 for (lp = 0 ; lp < wblock->count ; lp++){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
238 for(bitpos = 0 ; bitpos < 8 ; bitpos++){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
239 bits = ((wblock->value[lp] >> (7 - bitpos)) & 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
240 writebits(regs, &address, old_bits, bits);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
241 old_bits = bits ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
242 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
243 // ACK/NACK用(必ず1)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
244 writebits(regs, &address, old_bits, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
245 old_bits = 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
246 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
247
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
248 // Clock negedge
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
249 makei2c(regs, address, address + 1, 0, (old_bits ^ 1), 1, 1);
67e8eca28a80 initial import
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parents:
diff changeset
250 clock = TRUE ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
251 address += 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
252 stop_i2c(regs, &address, &clock, old_bits, TRUE);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
253
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
254 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
255
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
256 void blockread(void __iomem *regs, WBLOCK *wblock, int count)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
257 {
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
258 int lp ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
259 int bitpos ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
260 __u32 bits ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
261 __u32 old_bits = 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
262 __u32 address = 0;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
263 __u32 clock = 0;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
264
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
265 begin_i2c(regs, &address, &clock);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
266 if(state == STATE_STOP){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
267 start_i2c(regs, &address, &clock, old_bits);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
268 old_bits = 0 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
269 stop_i2c(regs, &address, &clock, old_bits, FALSE);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
270 state = STATE_START ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
271 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
272 old_bits = 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
273 start_i2c(regs, &address, &clock, old_bits);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
274 old_bits = 0 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
275
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
276 // まずアドレスを書く
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
277 for(bitpos = 0 ; bitpos < 7 ; bitpos++){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
278 bits = ((wblock->addr >> (6 - bitpos)) & 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
279 writebits(regs, &address, old_bits, bits);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
280 old_bits = bits ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
281 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
282 // タイプ:WRT
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
283 writebits(regs, &address, old_bits, 0);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
284 // ACK/NACK用(必ず1)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
285 writebits(regs, &address, 0, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
286
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
287 old_bits = 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
288 // 実際のデータを書く
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
289 for (lp = 0 ; lp < wblock->count ; lp++){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
290 for(bitpos = 0 ; bitpos < 8 ; bitpos++){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
291 bits = ((wblock->value[lp] >> (7 - bitpos)) & 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
292 writebits(regs, &address, old_bits, bits);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
293 old_bits = bits ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
294 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
295 // ACK/NACK用(必ず1)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
296 writebits(regs, &address, old_bits, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
297 old_bits = 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
298 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
299
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
300 // Clock negedge
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
301 makei2c(regs, address, address + 1, 0, (old_bits ^ 1), 1, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
302 clock = TRUE ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
303 address += 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
304
77
517e61637f7b a bit cleanup
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents: 0
diff changeset
305 // ここから Read
0
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
306 start_i2c(regs, &address, &clock, old_bits);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
307 old_bits = 0 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
308 // まずアドレスを書く
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
309 for(bitpos = 0 ; bitpos < 7 ; bitpos++){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
310 bits = ((wblock->addr >> (6 - bitpos)) & 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
311 writebits(regs, &address, old_bits, bits);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
312 old_bits = bits ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
313 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
314 // タイプ:RD
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
315 writebits(regs, &address, old_bits, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
316 // ACK/NACK用(必ず1)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
317 writebits(regs, &address, 1, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
318
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
319 old_bits = 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
320 // 実際のデータを書く
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
321 for (lp = 0 ; lp < count ; lp++){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
322 for(bitpos = 0 ; bitpos < 8 ; bitpos++){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
323 writebits(regs, &address, old_bits, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
324 // Read Mode Set
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
325 makei2c(regs, address, address + 1, 1, 0, 0, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
326 address += 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
327 old_bits = 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
328 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
329 if(lp >= (count - 1)){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
330 // ACK/NACK用(必ず1)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
331 writebits(regs, &address, old_bits, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
332 old_bits = 0 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
333 }else{
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
334 // ACK/NACK用(必ず1)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
335 writebits(regs, &address, old_bits, 0);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
336 old_bits = 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
337 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
338 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
339
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
340 // Clock negedge
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
341 makei2c(regs, address, address + 1, 0, 0, 1, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
342 clock = TRUE ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
343 address += 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
344 old_bits = 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
345 stop_i2c(regs, &address, &clock, old_bits, TRUE);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
346
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
347 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
348 static void writebits(void __iomem *regs, __u32 *address, __u32 old_bits, __u32 bits)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
349 {
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
350 // CLOCK UP
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
351 makei2c(regs, *address, *address + 1, 0, (old_bits ^ 1), 1, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
352 *address += 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
353
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
354 // CLOCK UP
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
355 makei2c(regs, *address, *address + 1, 0, (bits ^ 1), 1, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
356 *address += 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
357
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
358 // CLOCK DOWN
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
359 makei2c(regs, *address, *address + 1, 0, (bits ^ 1), 0, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
360 *address += 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
361
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
362 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
363 static void begin_i2c(void __iomem *regs, __u32 *address, __u32 *clock)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
364 {
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
365 // bus FREE
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
366 makei2c(regs, *address, *address, 0, 0, 0, 0);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
367 *address += 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
368
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
369 // bus busy
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
370 makei2c(regs, *address, *address + 1, 0, 0, 0, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
371 *address += 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
372 *clock = FALSE ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
373 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
374
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
375 static void start_i2c(void __iomem *regs, __u32 *address, __u32 *clock, __u32 data)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
376 {
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
377 // データが残っていなければデータを下げる
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
378 if(!data){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
379 // CLOCKがあればCLOCKを下げる
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
380 if(*clock != TRUE){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
381 *clock = TRUE ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
382 makei2c(regs, *address, *address + 1, 0, 1, 1, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
383 *address += 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
384 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
385 makei2c(regs, *address, *address + 1, 0, 0, 1, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
386 *address += 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
387 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
388
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
389 if(*clock != FALSE){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
390 *clock = FALSE ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
391 makei2c(regs, *address, *address + 1, 0, 0, 0, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
392 *address += 1;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
393 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
394 makei2c(regs, *address, *address + 1, 0, 1, 0, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
395 *address += 1;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
396 *clock = FALSE ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
397 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
398
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
399 static void stop_i2c(void __iomem *regs, __u32 *address, __u32 *clock, __u32 data, __u32 end)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
400 {
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
401 // データが残っていて
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
402 if(data){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
403 // クロックがあれば
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
404 if(*clock != TRUE){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
405 *clock = TRUE ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
406 makei2c(regs, *address, *address + 1, 0, 0, 1, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
407 *address += 1;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
408 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
409 makei2c(regs, *address, *address + 1, 0, 1, 1, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
410 *address += 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
411 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
412 // クロックが落ちていれば
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
413 if(*clock){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
414 *clock = FALSE ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
415 makei2c(regs, *address, *address + 1, 0, 1, 0, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
416 *address += 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
417 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
418
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
419 if(end){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
420 makei2c(regs, *address, 0, 0, 0, 0, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
421 }else{
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
422 makei2c(regs, *address, *address + 1, 0, 0, 0, 1);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
423 *address += 1 ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
424 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
425 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
426
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
427 void i2c_write(void __iomem *regs, struct mutex *lock, WBLOCK *wblock)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
428 {
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
429
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
430 int lp;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
431 __u32 val ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
432
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
433 // ロックする
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
434 mutex_lock(lock);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
435 #if 0
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
436 printk(KERN_INFO "Addr=%x(%d)\n", wblock->addr, wblock->count);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
437 for(lp = 0 ; lp < wblock->count ; lp++){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
438 printk(KERN_INFO "%x\n", wblock->value[lp]);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
439 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
440 printk(KERN_INFO "\n");
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
441 #endif
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
442
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
443 blockwrite(regs, wblock);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
444 writel(FIFO_GO, regs + FIFO_GO_ADDR);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
445 //とりあえずロックしないように。
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
446 for(lp = 0 ; lp < 100 ; lp++){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
447 val = readl(regs + FIFO_RESULT_ADDR);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
448 if(!(val & FIFO_DONE)){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
449 break ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
450 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
451 schedule_timeout_interruptible(msecs_to_jiffies(1));
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
452 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
453 mutex_unlock(lock);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
454 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
455
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
456 __u32 i2c_read(void __iomem *regs, struct mutex *lock, WBLOCK *wblock, int size)
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
457 {
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
458
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
459 int lp;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
460 __u32 val ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
461
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
462 // ロックする
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
463 mutex_lock(lock);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
464 #if 0
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
465 printk(KERN_INFO "Addr=%x:%d:%d\n", wblock->addr, wblock->count, size);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
466 for(lp = 0 ; lp < wblock->count ; lp++){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
467 printk(KERN_INFO "%x\n", wblock->value[lp]);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
468 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
469 printk(KERN_INFO "\n");
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
470 #endif
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
471 blockread(regs, wblock, size);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
472
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
473 writel(FIFO_GO, regs + FIFO_GO_ADDR);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
474
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
475 for(lp = 0 ; lp < 100 ; lp++){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
476 schedule_timeout_interruptible(msecs_to_jiffies(1));
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
477 val = readl(regs + FIFO_RESULT_ADDR);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
478 if(!(val & FIFO_DONE)){
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
479 break ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
480 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
481 }
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
482
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
483 val = readl(regs + I2C_RESULT_ADDR);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
484 mutex_unlock(lock);
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
485 return val ;
67e8eca28a80 initial import
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
diff changeset
486 }