Mercurial > pt1
annotate driver/pt1_tuner.c @ 77:517e61637f7b
a bit cleanup
author | Yoshiki Yazawa <yaz@honeyplanet.jp> |
---|---|
date | Tue, 01 Dec 2009 18:33:01 +0900 |
parents | 28f25ec7f962 |
children | 3c2123189edf |
rev | line source |
---|---|
0 | 1 /* pt1-tuner.c: A PT1 on Tuner driver for Linux. */ |
2 | |
3 #include <linux/module.h> | |
4 #include <linux/kernel.h> | |
5 #include <linux/errno.h> | |
6 #include <linux/pci.h> | |
7 #include <linux/init.h> | |
8 #include <linux/interrupt.h> | |
9 #include <linux/mutex.h> | |
10 | |
11 #include <asm/system.h> | |
12 #include <asm/io.h> | |
13 #include <asm/irq.h> | |
14 #include <asm/uaccess.h> | |
15 | |
16 #include "pt1_com.h" | |
17 #include "pt1_pci.h" | |
18 #include "pt1_i2c.h" | |
19 #include "pt1_tuner.h" | |
20 #include "pt1_tuner_data.h" | |
21 | |
22 typedef struct _TUNER_INFO{ | |
23 int isdb_s ; | |
24 int isdb_t ; | |
25 }TUNER_INFO; | |
26 | |
27 TUNER_INFO tuner_info[2] = { | |
28 {T0_ISDB_S, T0_ISDB_T}, | |
29 {T1_ISDB_S, T1_ISDB_T} | |
30 }; | |
31 | |
32 typedef struct _isdb_t_freq_add_table{ | |
33 __u16 pos ; // Äɲ乤ë¥Á¥ã¥ó¥Í¥ë¥Ý¥¸¥·¥ç¥ó | |
34 __u16 add_freq ; // Äɲ乤ëÃÍ | |
35 }isdb_t_freq_add_table; | |
36 | |
37 isdb_t_freq_add_table isdb_t_freq_add[10] = { | |
64
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
diff
changeset
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38 { 7, 0x8081}, // 0¡Á7Ëø |
0 | 39 { 12, 0x80A1}, // 8¡Á12Ëø |
40 { 21, 0x8062}, // 13¡Á21Ëø | |
41 { 39, 0x80A2}, // 22¡Á39Ëø | |
42 { 51, 0x80E2}, // 40¡Á51Ëø | |
43 { 59, 0x8064}, // 52¡Á59Ëø | |
44 { 75, 0x8084}, // 60¡Á75Ëø | |
45 { 84, 0x80a4}, // 76¡Á84Ëø | |
46 {100, 0x80C4}, // 85¡Á100Ëø | |
47 {112, 0x80E4} // 101¡Á112Ëø | |
48 }; | |
49 | |
64
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
diff
changeset
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50 void settuner_reset(void __iomem *regs, int cardtype, __u32 lnb, __u32 tuner) |
0 | 51 { |
77 | 52 __u32 val = TUNER_POWER_OFF; |
0 | 53 switch(lnb){ |
64
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
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changeset
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54 case LNB_11V: |
65 | 55 val = (1 << BIT_LNB_DOWN); |
56 break ; | |
64
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
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changeset
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57 case LNB_15V: |
65 | 58 val = (1 << BIT_LNB_UP) | (1 << BIT_LNB_DOWN); |
59 break ; | |
0 | 60 } |
61 | |
64
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
diff
changeset
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62 if(cardtype == PT1) { |
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
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changeset
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63 switch(tuner){ |
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
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changeset
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64 case TUNER_POWER_ON_RESET_ENABLE: |
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
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65 val |= (1 << BIT_TUNER); |
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
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changeset
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66 break; |
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
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changeset
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67 case TUNER_POWER_ON_RESET_DISABLE: |
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
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changeset
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68 val |= (1 << BIT_TUNER) | (1 << BIT_RESET); |
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
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changeset
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69 break ; |
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
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changeset
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70 } |
0 | 71 } |
64
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
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changeset
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72 else if(cardtype == PT2) { |
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
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changeset
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73 switch(tuner){ |
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
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changeset
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74 case TUNER_POWER_ON_RESET_ENABLE: |
69
272a8fba970b
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parents:
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75 val |= (1 << BIT_TUNER) |
272a8fba970b
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Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
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76 | (1 << BIT_33A1) |
272a8fba970b
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Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
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77 | (1 << BIT_33A2) |
272a8fba970b
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Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
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78 | (1 << BIT_5A_) |
272a8fba970b
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79 | (1 << BIT_5A1) |
272a8fba970b
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parents:
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80 | (1 << BIT_5A2); |
64
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
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81 break; |
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
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changeset
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82 case TUNER_POWER_ON_RESET_DISABLE: |
69
272a8fba970b
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Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
65
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83 val |= (1 << BIT_TUNER) |
272a8fba970b
added very rough support for PT2.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
65
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84 | (1 << BIT_RESET) |
272a8fba970b
added very rough support for PT2.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
65
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changeset
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85 | (1 << BIT_33A1) |
272a8fba970b
added very rough support for PT2.
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
65
diff
changeset
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86 | (1 << BIT_33A2) |
272a8fba970b
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Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
65
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changeset
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87 | (1 << BIT_5A_) |
272a8fba970b
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Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
65
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changeset
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88 | (1 << BIT_5A1) |
272a8fba970b
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Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
65
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changeset
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89 | (1 << BIT_5A2); |
64
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
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changeset
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90 break ; |
98a92ce5382e
added fake support code for PT2. the PT2 part is not expected to work. be careful!
Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
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91 } |
98a92ce5382e
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Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
9
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92 } |
98a92ce5382e
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Yoshiki Yazawa <yaz@honeyplanet.jp>
parents:
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93 writel(val, (regs + CFG_REGS_ADDR)); |
0 | 94 } |
69
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95 static int init_isdb_s(void __iomem *regs, int cardtype, struct mutex *lock, __u32 addr) |
0 | 96 { |
97 | |
98 WBLOCK wk; | |
99 int lp ; | |
100 __u32 val ; | |
101 | |
102 // ISDB-S/T½é´ü²½ | |
103 memcpy(&wk, &com_initdata, sizeof(WBLOCK)); | |
104 | |
105 // ½é´ü²½£±(¤Ê¤¼¤«READ¤Ê¤Î¤Ç) | |
106 memcpy(&wk, &isdb_s_init1, sizeof(WBLOCK)); | |
107 wk.addr = addr; | |
108 val = i2c_read(regs, lock, &wk, 1); | |
109 if((val & 0xff) != 0x41){ | |
110 printk(KERN_INFO "PT1:ISDB-S Read(%x)\n", val); | |
111 return -EIO ; | |
112 } | |
71
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113 |
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114 if(cardtype == PT1) { |
77 | 115 for(lp = 0 ; lp < PT1_MAX_ISDB_S_INIT ; lp++){ |
69
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116 memcpy(&wk, isdb_s_initial_pt1[lp], sizeof(WBLOCK)); |
71
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117 wk.addr = addr; |
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118 i2c_write(regs, lock, &wk); |
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119 } |
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120 } |
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121 else if(cardtype == PT2) { |
77 | 122 for(lp = 0 ; lp < PT2_MAX_ISDB_S_INIT ; lp++){ |
69
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123 memcpy(&wk, isdb_s_initial_pt2[lp], sizeof(WBLOCK)); |
71
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124 wk.addr = addr; |
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125 i2c_write(regs, lock, &wk); |
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126 } |
0 | 127 } |
128 | |
129 return 0 ; | |
130 } | |
69
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131 static void init_isdb_t(void __iomem *regs, int cardtype, struct mutex *lock, __u32 addr) |
0 | 132 { |
133 int lp ; | |
134 WBLOCK wk; | |
135 | |
136 // ISDB-S/T½é´ü²½ | |
71
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137 if(cardtype == PT1) { |
77 | 138 for(lp = 0 ; lp < PT1_MAX_ISDB_T_INIT ; lp++){ |
69
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parents:
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139 memcpy(&wk, isdb_t_initial_pt1[lp], sizeof(WBLOCK)); |
71
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140 wk.addr = addr; |
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141 i2c_write(regs, lock, &wk); |
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142 } |
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143 } |
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144 else if(cardtype == PT2) { |
77 | 145 for(lp = 0 ; lp < PT2_MAX_ISDB_T_INIT ; lp++){ |
69
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146 memcpy(&wk, isdb_t_initial_pt2[lp], sizeof(WBLOCK)); |
71
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147 wk.addr = addr; |
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148 i2c_write(regs, lock, &wk); |
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149 } |
0 | 150 } |
71
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151 } |
0 | 152 |
69
272a8fba970b
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parents:
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153 int tuner_init(void __iomem *regs, int cardtype, struct mutex *lock, int tuner_no) |
0 | 154 { |
155 | |
156 int rc ; | |
157 WBLOCK wk; | |
158 | |
159 // ISDB-S/T½é´ü²½ | |
160 memcpy(&wk, &com_initdata, sizeof(WBLOCK)); | |
161 | |
162 // ½é´ü²½(¶¦ÄÌ) | |
163 wk.addr = tuner_info[tuner_no].isdb_t ; | |
164 i2c_write(regs, lock, &wk); | |
165 wk.addr = tuner_info[tuner_no].isdb_s ; | |
166 i2c_write(regs, lock, &wk); | |
167 | |
69
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parents:
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168 rc = init_isdb_s(regs, cardtype, lock, tuner_info[tuner_no].isdb_s); |
0 | 169 if(rc < 0){ |
170 return rc ; | |
171 } | |
69
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parents:
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172 init_isdb_t(regs, cardtype, lock, tuner_info[tuner_no].isdb_t); |
0 | 173 |
174 memcpy(&wk, &isdb_s_init21, sizeof(WBLOCK)); | |
175 wk.addr = tuner_info[tuner_no].isdb_s ; | |
176 i2c_write(regs, lock, &wk); | |
177 | |
178 memcpy(&wk, &isdb_t_init17, sizeof(WBLOCK)); | |
179 wk.addr = tuner_info[tuner_no].isdb_t ; | |
180 i2c_write(regs, lock, &wk); | |
181 | |
182 return 0 ; | |
183 } | |
184 void set_sleepmode(void __iomem *regs, struct mutex *lock, int address, int tuner_type, int type) | |
185 { | |
186 WBLOCK wk; | |
187 | |
188 if(type == TYPE_WAKEUP){ | |
189 switch(tuner_type){ | |
77 | 190 case CHANNEL_TYPE_ISDB_S: |
191 printk(KERN_INFO "PT1:ISDB-S Wakeup\n"); | |
192 memcpy(&wk, &isdb_s_wake, sizeof(WBLOCK)); | |
193 wk.addr = address ; | |
194 i2c_write(regs, lock, &wk); | |
195 | |
196 memcpy(&wk, &isdb_s_sleep, sizeof(WBLOCK)); | |
197 wk.value[1] = 0x01 ; | |
198 wk.addr = address ; | |
199 i2c_write(regs, lock, &wk); | |
200 break ; | |
201 case CHANNEL_TYPE_ISDB_T: | |
202 printk(KERN_INFO "PT1:ISDB-T Wakeup\n"); | |
203 memcpy(&wk, &isdb_t_wake, sizeof(WBLOCK)); | |
204 wk.addr = address ; | |
205 i2c_write(regs, lock, &wk); | |
206 | |
207 memcpy(&wk, &isdb_s_sleep, sizeof(WBLOCK)); | |
208 wk.value[1] = 0x90 ; | |
209 wk.addr = address ; | |
210 i2c_write(regs, lock, &wk); | |
211 break ; | |
0 | 212 } |
213 } | |
77 | 214 if(type == TYPE_SLEEP){ |
215 switch(tuner_type){ | |
0 | 216 case CHANNEL_TYPE_ISDB_S: |
217 printk(KERN_INFO "PT1:ISDB-S Sleep\n"); | |
218 memcpy(&wk, &isdb_s_sleep, sizeof(WBLOCK)); | |
77 | 219 wk.addr = address; |
220 i2c_write(regs, lock, &wk); | |
0 | 221 break ; |
222 case CHANNEL_TYPE_ISDB_T: | |
223 printk(KERN_INFO "PT1:ISDB-T Sleep\n"); | |
224 memcpy(&wk, &isdb_t_sleep, sizeof(WBLOCK)); | |
77 | 225 wk.addr = address; |
226 i2c_write(regs, lock, &wk); | |
0 | 227 break ; |
77 | 228 } |
0 | 229 } |
230 } | |
231 | |
232 int bs_frequency(void __iomem *regs, struct mutex *lock, int addr, int channel) | |
233 { | |
234 int lp ; | |
235 int tmcclock = FALSE ; | |
236 WBLOCK wk; | |
237 __u32 val ; | |
238 | |
239 if(channel >= MAX_BS_CHANNEL){ | |
240 return -EIO ; | |
241 } | |
242 // ISDB-S PLL¥í¥Ã¥¯ | |
243 for(lp = 0 ; lp < MAX_BS_CHANNEL_PLL_COMMAND ; lp++){ | |
244 memcpy(&wk, bs_pll[channel].wblock[lp], sizeof(WBLOCK)); | |
245 wk.addr = addr ; | |
246 i2c_write(regs, lock, &wk); | |
247 } | |
248 | |
249 // PLL¥í¥Ã¥¯³Îǧ | |
250 // ¥Á¥§¥Ã¥¯ÍÑ | |
251 for(lp = 0 ; lp < 200 ; lp++){ | |
252 memcpy(&wk, &bs_pll_lock, sizeof(WBLOCK)); | |
253 wk.addr = addr; | |
254 val = i2c_read(regs, lock, &wk, 1); | |
255 if(((val & 0xFF) != 0) && ((val & 0XFF) != 0XFF)){ | |
256 tmcclock = TRUE ; | |
257 break ; | |
258 } | |
259 } | |
260 | |
261 if(tmcclock == FALSE){ | |
262 printk(KERN_INFO "PLL LOCK ERROR\n"); | |
263 return -EIO; | |
264 } | |
265 | |
266 memcpy(&wk, &bs_tmcc_get_1, sizeof(WBLOCK)); | |
267 wk.addr = addr; | |
268 i2c_write(regs, lock, &wk); | |
269 | |
270 tmcclock = FALSE ; | |
271 | |
272 for(lp = 0 ; lp < 200 ; lp++){ | |
273 memcpy(&wk, &bs_tmcc_get_2, sizeof(WBLOCK)); | |
274 wk.addr = addr; | |
275 | |
276 val = i2c_read(regs, lock, &wk, 1); | |
277 if(((val & 0XFF) != 0XFF) && (!(val & 0x10))){ | |
278 tmcclock = TRUE ; | |
279 break ; | |
280 } | |
281 } | |
282 | |
283 if(tmcclock == FALSE){ | |
284 printk(KERN_INFO "TMCC LOCK ERROR\n"); | |
285 return -EIO; | |
286 } | |
287 | |
288 return 0 ; | |
289 } | |
290 int ts_lock(void __iomem *regs, struct mutex *lock, int addr, __u16 ts_id) | |
291 { | |
292 | |
293 int lp ; | |
294 WBLOCK wk; | |
295 __u32 val ; | |
296 union{ | |
297 __u8 ts[2]; | |
298 __u16 tsid; | |
299 }uts_id ; | |
300 | |
301 uts_id.tsid = ts_id ; | |
302 memcpy(&wk, &bs_set_ts_lock, sizeof(WBLOCK)); | |
303 wk.addr = addr; | |
304 // TS-IDÀßÄê | |
305 wk.value[1] = uts_id.ts[1]; | |
306 wk.value[2] = uts_id.ts[0]; | |
307 i2c_write(regs, lock, &wk); | |
308 | |
309 for(lp = 0 ; lp < 100 ; lp++){ | |
310 memcpy(&wk, &bs_get_ts_lock, sizeof(WBLOCK)); | |
311 wk.addr = addr; | |
312 val = i2c_read(regs, lock, &wk, 2); | |
313 if((val & 0xFFFF) == ts_id){ | |
314 return 0 ; | |
315 } | |
316 } | |
317 printk(KERN_INFO "PT1:ERROR TS-LOCK(%x)\n", ts_id); | |
318 return -EIO ; | |
319 } | |
320 int bs_tune(void __iomem *regs, struct mutex *lock, int addr, int channel, ISDB_S_TMCC *tmcc) | |
321 { | |
322 | |
323 int lp ; | |
324 int lp2; | |
325 WBLOCK wk; | |
326 __u32 val ; | |
327 ISDB_S_TS_ID *tsid ; | |
328 union{ | |
329 __u8 slot[4]; | |
330 __u32 u32slot; | |
331 }ts_slot ; | |
332 union{ | |
333 __u16 ts[2]; | |
334 __u32 tsid; | |
335 }ts_id ; | |
336 | |
337 if(channel >= MAX_BS_CHANNEL){ | |
338 printk(KERN_INFO "Invalid Channel(%d)\n", channel); | |
339 return -EIO ; | |
340 } | |
341 val = bs_frequency(regs, lock, addr, channel); | |
342 if(val == -EIO){ | |
343 return val ; | |
344 } | |
345 | |
346 tsid = &tmcc->ts_id[0] ; | |
347 // ³ºÅö¼þÇÈ¿ô¤ÎTS-ID¤ò¼èÆÀ | |
348 for(lp = 0 ; lp < (MAX_BS_TS_ID / 2) ; lp++){ | |
349 for(lp2 = 0 ; lp2 < 100 ; lp2++){ | |
350 memcpy(&wk, bs_get_ts_id[lp], sizeof(WBLOCK)); | |
351 wk.addr = addr; | |
352 ts_id.tsid = i2c_read(regs, lock, &wk, 4); | |
353 // TS-ID¤¬0¤Î¾ì¹ç¤ÏºÆ¼èÆÀ¤¹¤ë | |
354 if((ts_id.ts[0] != 0) && (ts_id.ts[1] != 0)){ | |
355 break ; | |
356 } | |
357 } | |
358 tsid->ts_id = ts_id.ts[1] ; | |
359 tsid += 1; | |
360 tsid->ts_id = ts_id.ts[0] ; | |
361 tsid += 1; | |
362 } | |
363 | |
364 memcpy(&wk, &bs_get_agc, sizeof(WBLOCK)); | |
365 wk.addr = addr; | |
366 tmcc->agc = i2c_read(regs, lock, &wk, 1); | |
367 | |
368 // TS-IDÊ̤ξðÊó¤ò¼èÆÀ | |
369 tsid = &tmcc->ts_id[0] ; | |
370 for(lp = 0 ; lp < MAX_BS_TS_ID ; lp++, tsid += 1){ | |
371 // TS-ID¤Ê¤·=0XFFFF | |
372 if(tsid->ts_id == 0xFFFF){ | |
373 continue ; | |
374 } | |
375 ts_lock(regs, lock, addr, tsid->ts_id); | |
376 | |
377 //¥¹¥í¥Ã¥È¼èÆÀ | |
378 memcpy(&wk, &bs_get_slot, sizeof(WBLOCK)); | |
379 wk.addr = addr; | |
380 ts_slot.u32slot = i2c_read(regs, lock, &wk, 3); | |
381 tsid->high_mode = 0; | |
382 tsid->low_slot = ts_slot.slot[0] ; | |
383 tsid->high_slot = ts_slot.slot[1] ; | |
384 tsid->low_mode = ts_slot.slot[2] ; | |
385 } | |
386 | |
387 memcpy(&wk, &bs_get_clock, sizeof(WBLOCK)); | |
388 wk.addr = addr; | |
389 tmcc->clockmargin = i2c_read(regs, lock, &wk, 1); | |
390 | |
391 memcpy(&wk, &bs_get_carrir, sizeof(WBLOCK)); | |
392 wk.addr = addr; | |
393 tmcc->carriermargin = i2c_read(regs, lock, &wk, 1); | |
394 return 0 ; | |
395 } | |
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396 int isdb_s_read_signal_strength(void __iomem *regs, struct mutex *lock, int addr) |
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397 { |
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398 WBLOCK wk; |
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399 __u32 val ; |
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400 __u32 val2; |
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401 int val3 ; |
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402 |
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403 memcpy(&wk, &bs_get_signal1, sizeof(WBLOCK)); |
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404 wk.addr = addr; |
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405 val = i2c_read(regs, lock, &wk, 1); |
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406 |
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407 memcpy(&wk, &bs_get_signal2, sizeof(WBLOCK)); |
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408 wk.addr = addr; |
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409 val2 = i2c_read(regs, lock, &wk, 1); |
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410 val3 = (((val << 8) & 0XFF00) | (val2 & 0XFF)); |
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411 |
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412 return val3 ; |
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413 } |
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414 |
0 | 415 __u32 getfrequency_add(__u32 channel) |
416 { | |
417 int lp ; | |
418 | |
419 for(lp = 0 ; lp < 10 ; lp++){ | |
420 if(channel <= isdb_t_freq_add[lp].pos){ | |
421 return isdb_t_freq_add[lp].add_freq ; | |
422 } | |
423 } | |
424 return 0 ; | |
425 } | |
426 __u32 getfrequency(__u32 channel, int addfreq) | |
427 { | |
428 __u32 frequencyoffset = 0; | |
429 __u32 frequencyOffset = 0; | |
430 | |
431 if (12 <= channel){ | |
432 frequencyoffset += 2; | |
433 }else if (17 <= channel){ | |
434 frequencyoffset = 0; | |
435 }else if (63 <= channel){ | |
436 frequencyoffset += 2; | |
437 } | |
438 #if 0 | |
439 return (((93 + channel * 6 + frequencyOffset) + addfreq) * 7) + 400; | |
440 #endif | |
441 frequencyOffset = 93 + channel * 6 + frequencyoffset; | |
442 frequencyOffset = 7 * (frequencyOffset + addfreq); | |
443 return frequencyOffset + 400; | |
444 | |
445 } | |
446 int isdb_t_frequency(void __iomem *regs, struct mutex *lock, int addr, int channel, int addfreq) | |
447 { | |
448 | |
449 int lp ; | |
450 WBLOCK wk; | |
451 __u32 val ; | |
452 int tmcclock = FALSE ; | |
453 union{ | |
454 __u8 charfreq[2]; | |
455 __u16 freq; | |
456 }freq[2] ; | |
457 | |
458 if(channel >= MAX_ISDB_T_CHANNEL){ | |
459 return -EIO ; | |
460 } | |
461 | |
462 freq[0].freq = getfrequency(channel, addfreq); | |
463 freq[1].freq = getfrequency_add(channel); | |
464 //»ØÄê¼þÇÈ¿ô | |
465 memcpy(&wk, &isdb_t_pll_base, sizeof(WBLOCK)); | |
466 wk.addr = addr ; | |
467 // ·×»»¤·¤¿¼þÇÈ¿ô¤òÀßÄê | |
468 wk.value[wk.count] = freq[0].charfreq[1]; | |
469 wk.count += 1 ; | |
470 wk.value[wk.count] = freq[0].charfreq[0]; | |
471 wk.count += 1 ; | |
472 | |
473 // ·×»»¤·¤¿¼þÇÈ¿ôÉղþðÊó¤òÀßÄê | |
474 wk.value[wk.count] = freq[1].charfreq[1]; | |
475 wk.count += 1 ; | |
476 wk.value[wk.count] = freq[1].charfreq[0]; | |
477 wk.count += 1 ; | |
478 | |
479 i2c_write(regs, lock, &wk); | |
480 | |
481 for(lp = 0 ; lp < 100 ; lp++){ | |
482 memcpy(&wk, &isdb_t_pll_lock, sizeof(WBLOCK)); | |
483 wk.addr = addr; | |
484 val = i2c_read(regs, lock, &wk, 1); | |
485 if(((val & 0xFF) != 0XFF) && ((val & 0X50) == 0x50)){ | |
486 tmcclock = TRUE ; | |
487 break ; | |
488 } | |
489 } | |
490 if(tmcclock != TRUE){ | |
491 printk(KERN_INFO "PT1:ISDB-T LOCK NG(%08x)\n", val); | |
492 return -EIO ; | |
493 } | |
494 | |
495 memcpy(&wk, &isdb_t_check_tune, sizeof(WBLOCK)); | |
496 wk.addr = addr ; | |
497 i2c_write(regs, lock, &wk); | |
498 | |
499 tmcclock = FALSE ; | |
500 for(lp = 0 ; lp < 1000 ; lp++){ | |
501 memcpy(&wk, &isdb_t_tune_read, sizeof(WBLOCK)); | |
502 wk.addr = addr; | |
503 val = i2c_read(regs, lock, &wk, 1); | |
504 if(((val & 0xFF) != 0XFF) && ((val & 0X8) != 8)){ | |
505 tmcclock = TRUE ; | |
506 break ; | |
507 } | |
508 } | |
509 if(tmcclock != TRUE){ | |
510 return -EIO ; | |
511 } | |
512 return 0 ; | |
513 } | |
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514 int isdb_t_read_signal_strength(void __iomem *regs, struct mutex *lock, int addr) |
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515 { |
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516 __u32 val ; |
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517 __u32 val2; |
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518 __u32 val3; |
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519 WBLOCK wk; |
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520 |
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521 memcpy(&wk, &isdb_t_signal1, sizeof(WBLOCK)); |
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522 wk.addr = addr; |
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523 val = i2c_read(regs, lock, &wk, 1); |
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524 printk(KERN_INFO "CN(1)Val(%x)\n", val); |
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525 |
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526 memcpy(&wk, &isdb_t_signal2, sizeof(WBLOCK)); |
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527 wk.addr = addr; |
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528 val2 = i2c_read(regs, lock, &wk, 1); |
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529 val3 = (((val << 8) & 0XFF00) | (val2 & 0XFF)); |
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530 return val3 ; |
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531 } |
0 | 532 #if 0 |
533 int isdb_t_tune(void __iomem *regs, struct mutex *lock, int addr, int channel, ISDB_T_TMCC *tmcc) | |
534 { | |
535 | |
536 int lp ; | |
537 int rc ; | |
538 int lp2 ; | |
539 WBLOCK wk; | |
540 __u32 val ; | |
541 | |
542 printk(KERN_INFO "Channel(%d) Start\n", channel); | |
543 if(channel >= MAX_ISDB_T_CHANNEL){ | |
544 return -EIO ; | |
545 } | |
546 rc = isdb_t_frequency(regs, lock, addr, channel); | |
547 if(rc < 0){ | |
548 return -EIO ; | |
549 } | |
550 for(lp = 0 ; lp < 100 ; lp++){ | |
551 memcpy(&wk, &isdb_t_tmcc_read_1, sizeof(WBLOCK)); | |
552 wk.addr = addr; | |
553 val = i2c_read(regs, lock, &wk, 4); | |
554 if((val & 0xFF) != 0){ | |
555 break ; | |
556 } | |
557 } | |
558 printk(KERN_INFO "TMCC(1)Val(%x)\n", val); | |
559 | |
560 for(lp = 0 ; lp < 100 ; lp++){ | |
561 memcpy(&wk, &isdb_t_tmcc_read_2, sizeof(WBLOCK)); | |
562 wk.addr = addr; | |
563 val = i2c_read(regs, lock, &wk, 4); | |
564 if((val & 0xFF) != 0){ | |
565 break ; | |
566 } | |
567 } | |
568 printk(KERN_INFO "TMCC(2)Val(%x)\n", val); | |
569 | |
570 memcpy(&wk, &isdb_t_cn_1, sizeof(WBLOCK)); | |
571 wk.addr = addr; | |
572 val = i2c_read(regs, lock, &wk, 1); | |
573 printk(KERN_INFO "CN(1)Val(%x)\n", val); | |
574 | |
575 memcpy(&wk, &isdb_t_cn_2, sizeof(WBLOCK)); | |
576 wk.addr = addr; | |
577 val = i2c_read(regs, lock, &wk, 1); | |
578 printk(KERN_INFO "CN(2)Val(%x)\n", val); | |
579 | |
580 memcpy(&wk, &isdb_t_agc_1, sizeof(WBLOCK)); | |
581 wk.addr = addr; | |
582 val = i2c_read(regs, lock, &wk, 1); | |
583 printk(KERN_INFO "AGC(1)Val(%x)\n", val); | |
584 | |
585 memcpy(&wk, &isdb_t_agc_2, sizeof(WBLOCK)); | |
586 wk.addr = addr; | |
587 val = i2c_read(regs, lock, &wk, 1); | |
588 printk(KERN_INFO "AGC(2)Val(%x)\n", val); | |
589 return 0; | |
590 } | |
591 #endif |