comparison driver/pt1_pci.c @ 142:1e7718cc2556

use utf-8 instead of euc-jp
author Yoshiki Yazawa <yaz@honeyplanet.jp>
date Wed, 30 Apr 2014 11:26:24 +0900
parents 45b4afa656d2
children d56831676696
comparison
equal deleted inserted replaced
141:c8688d7d6382 142:1e7718cc2556
78 { 0, } 78 { 0, }
79 }; 79 };
80 MODULE_DEVICE_TABLE(pci, pt1_pci_tbl); 80 MODULE_DEVICE_TABLE(pci, pt1_pci_tbl);
81 #define DEV_NAME "pt1video" 81 #define DEV_NAME "pt1video"
82 82
83 #define PACKET_SIZE 188 // 1パケット長 83 #define PACKET_SIZE 188 // 1宴
84 #define MAX_READ_BLOCK 4 // 1度に読み出す最大DMAバッファ数 84 #define MAX_READ_BLOCK 4 // 1綺茯水冴紊DMA≧
85 #define MAX_PCI_DEVICE 128 // 最大64枚 85 #define MAX_PCI_DEVICE 128 // 紊64
86 #define DMA_SIZE 4096 // DMAバッファサイズ 86 #define DMA_SIZE 4096 // DMA<泣ゃ
87 #define DMA_RING_SIZE 128 // number of DMA RINGS 87 #define DMA_RING_SIZE 128 // number of DMA RINGS
88 #define DMA_RING_MAX 511 // number of DMA entries in a RING(1023はNGで511まで) 88 #define DMA_RING_MAX 511 // number of DMA entries in a RING(1023NG511障)
89 #define CHANNEL_DMA_SIZE (2*1024*1024) // 地デジ用(16Mbps) 89 #define CHANNEL_DMA_SIZE (2*1024*1024) // 違悟(16Mbps)
90 #define BS_CHANNEL_DMA_SIZE (4*1024*1024) // BS用(32Mbps) 90 #define BS_CHANNEL_DMA_SIZE (4*1024*1024) // BS(32Mbps)
91 #define READ_SIZE (16*DMA_SIZE) 91 #define READ_SIZE (16*DMA_SIZE)
92 92
93 typedef struct _DMA_CONTROL{ 93 typedef struct _DMA_CONTROL{
94 dma_addr_t ring_dma[DMA_RING_MAX] ; // DMA情報 94 dma_addr_t ring_dma[DMA_RING_MAX] ; // DMA
95 __u32 *data[DMA_RING_MAX]; 95 __u32 *data[DMA_RING_MAX];
96 }DMA_CONTROL; 96 }DMA_CONTROL;
97 97
98 typedef struct _PT1_CHANNEL PT1_CHANNEL; 98 typedef struct _PT1_CHANNEL PT1_CHANNEL;
99 99
100 typedef struct _pt1_device{ 100 typedef struct _pt1_device{
101 unsigned long mmio_start ; 101 unsigned long mmio_start ;
102 __u32 mmio_len ; 102 __u32 mmio_len ;
103 void __iomem *regs; 103 void __iomem *regs;
104 struct mutex lock ; 104 struct mutex lock ;
105 dma_addr_t ring_dma[DMA_RING_SIZE] ; // DMA情報 105 dma_addr_t ring_dma[DMA_RING_SIZE] ; // DMA
106 void *dmaptr[DMA_RING_SIZE] ; 106 void *dmaptr[DMA_RING_SIZE] ;
107 struct task_struct *kthread; 107 struct task_struct *kthread;
108 dev_t dev ; 108 dev_t dev ;
109 int card_number; 109 int card_number;
110 __u32 base_minor ; 110 __u32 base_minor ;
119 char data[3]; 119 char data[3];
120 char head ; 120 char head ;
121 }MICRO_PACKET; 121 }MICRO_PACKET;
122 122
123 struct _PT1_CHANNEL{ 123 struct _PT1_CHANNEL{
124 __u32 valid ; // 使用中フラグ 124 __u32 valid ; // 篏睡筝
125 __u32 address ; // I2Cアドレス 125 __u32 address ; // I2C≪
126 __u32 channel ; // チャネル番号 126 __u32 channel ; // c
127 int type ; // チャネルタイプ 127 int type ; // c帥ゃ
128 __u32 packet_size ; // パケットサイズ 128 __u32 packet_size ; // 宴泣ゃ
129 __u32 drop ; // パケットドロップ数 129 __u32 drop ; // 宴
130 struct mutex lock ; // CH別mutex_lock用 130 struct mutex lock ; // CHmutex_lock
131 __u32 size ; // DMAされたサイズ 131 __u32 size ; // DMA泣ゃ
132 __u32 maxsize ; // DMA用バッファサイズ 132 __u32 maxsize ; // DMA<泣ゃ
133 __u32 bufsize ; // チャネルに割り振られたサイズ 133 __u32 bufsize ; // c蚊泣ゃ
134 __u32 overflow ; // オーバーフローエラー発生 134 __u32 overflow ; // 若若若主榊
135 __u32 counetererr ; // 転送カウンタ1エラー 135 __u32 counetererr ; // 荵∫潟随
136 __u32 transerr ; // 転送エラー 136 __u32 transerr ; // 荵∫
137 __u32 minor ; // マイナー番号 137 __u32 minor ; // ゃ主
138 __u8 *buf; // CH別受信メモリ 138 __u8 *buf; // CHュ篆<<≪
139 __u32 pointer; 139 __u32 pointer;
140 __u8 req_dma ; // 溢れたチャネル 140 __u8 req_dma ; // 羣≪c
141 __u8 packet_buf[PACKET_SIZE] ; // 溢れたチャネル 141 __u8 packet_buf[PACKET_SIZE] ; // 羣≪c
142 PT1_DEVICE *ptr ; // カード別情報 142 PT1_DEVICE *ptr ; // 若ユ
143 wait_queue_head_t wait_q ; // for poll on reading 143 wait_queue_head_t wait_q ; // for poll on reading
144 }; 144 };
145 145
146 // I2Cアドレス(video0, 1 = ISDB-S) (video2, 3 = ISDB-T) 146 // I2C≪(video0, 1 = ISDB-S) (video2, 3 = ISDB-T)
147 int i2c_address[MAX_CHANNEL] = {T0_ISDB_S, T1_ISDB_S, T0_ISDB_T, T1_ISDB_T}; 147 int i2c_address[MAX_CHANNEL] = {T0_ISDB_S, T1_ISDB_S, T0_ISDB_T, T1_ISDB_T};
148 int real_channel[MAX_CHANNEL] = {0, 2, 1, 3}; 148 int real_channel[MAX_CHANNEL] = {0, 2, 1, 3};
149 int channeltype[MAX_CHANNEL] = {CHANNEL_TYPE_ISDB_S, CHANNEL_TYPE_ISDB_S, 149 int channeltype[MAX_CHANNEL] = {CHANNEL_TYPE_ISDB_S, CHANNEL_TYPE_ISDB_S,
150 CHANNEL_TYPE_ISDB_T, CHANNEL_TYPE_ISDB_T}; 150 CHANNEL_TYPE_ISDB_T, CHANNEL_TYPE_ISDB_T};
151 151
162 __u32 addr ; 162 __u32 addr ;
163 int ring_pos = 0; 163 int ring_pos = 0;
164 int data_pos = 0 ; 164 int data_pos = 0 ;
165 __u32 *dataptr ; 165 __u32 *dataptr ;
166 166
167 // データ初期化 167 // 若水
168 for(ring_pos = 0 ; ring_pos < DMA_RING_SIZE ; ring_pos++){ 168 for(ring_pos = 0 ; ring_pos < DMA_RING_SIZE ; ring_pos++){
169 for(data_pos = 0 ; data_pos < DMA_RING_MAX ; data_pos++){ 169 for(data_pos = 0 ; data_pos < DMA_RING_MAX ; data_pos++){
170 dataptr = (dev_conf->dmactl[ring_pos])->data[data_pos]; 170 dataptr = (dev_conf->dmactl[ring_pos])->data[data_pos];
171 dataptr[(DMA_SIZE / sizeof(__u32)) - 2] = 0; 171 dataptr[(DMA_SIZE / sizeof(__u32)) - 2] = 0;
172 } 172 }
173 } 173 }
174 // 転送カウンタをリセット 174 // 荵∫潟帥祉
175 writel(0x00000010, dev_conf->regs); 175 writel(0x00000010, dev_conf->regs);
176 // 転送カウンタをインクリメント 176 // 荵∫潟帥ゃ潟<潟
177 for(lp = 0 ; lp < DMA_RING_SIZE ; lp++){ 177 for(lp = 0 ; lp < DMA_RING_SIZE ; lp++){
178 writel(0x00000020, dev_conf->regs); 178 writel(0x00000020, dev_conf->regs);
179 } 179 }
180 180
181 addr = (int)dev_conf->ring_dma[0] ; 181 addr = (int)dev_conf->ring_dma[0] ;
182 addr >>= 12 ; 182 addr >>= 12 ;
183 // DMAバッファ設定 183 // DMA∴┃絎
184 writel(addr, dev_conf->regs + DMA_ADDR); 184 writel(addr, dev_conf->regs + DMA_ADDR);
185 // DMA開始 185 // DMA紮
186 writel(0x0c000040, dev_conf->regs); 186 writel(0x0c000040, dev_conf->regs);
187 187
188 } 188 }
189 static int pt1_thread(void *data) 189 static int pt1_thread(void *data)
190 { 190 {
213 break ; 213 break ;
214 } 214 }
215 215
216 for(;;){ 216 for(;;){
217 dataptr = (dev_conf->dmactl[ring_pos])->data[data_pos]; 217 dataptr = (dev_conf->dmactl[ring_pos])->data[data_pos];
218 // データあり? 218 // 若帥鐚
219 if(dataptr[(DMA_SIZE / sizeof(__u32)) - 2] == 0){ 219 if(dataptr[(DMA_SIZE / sizeof(__u32)) - 2] == 0){
220 break ; 220 break ;
221 } 221 }
222 micro.val = *dataptr ; 222 micro.val = *dataptr ;
223 curdataptr = dataptr ; 223 curdataptr = dataptr ;
224 data_pos += 1 ; 224 data_pos += 1 ;
225 for(lp = 0 ; lp < (DMA_SIZE / sizeof(__u32)) ; lp++, dataptr++){ 225 for(lp = 0 ; lp < (DMA_SIZE / sizeof(__u32)) ; lp++, dataptr++){
226 micro.val = *dataptr ; 226 micro.val = *dataptr ;
227 dma_channel = ((micro.packet.head >> 5) & 0x07); 227 dma_channel = ((micro.packet.head >> 5) & 0x07);
228 //チャネル情報不正 228 //c延罩
229 if(dma_channel > MAX_CHANNEL){ 229 if(dma_channel > MAX_CHANNEL){
230 printk(KERN_ERR "DMA Channel Number Error(%d)\n", dma_channel); 230 printk(KERN_ERR "DMA Channel Number Error(%d)\n", dma_channel);
231 continue ; 231 continue ;
232 } 232 }
233 chno = real_channel[(((micro.packet.head >> 5) & 0x07) - 1)]; 233 chno = real_channel[(((micro.packet.head >> 5) & 0x07) - 1)];
234 packet_pos = ((micro.packet.head >> 2) & 0x07); 234 packet_pos = ((micro.packet.head >> 2) & 0x07);
235 channel = dev_conf->channel[chno] ; 235 channel = dev_conf->channel[chno] ;
236 // エラーチェック 236 // 若с
237 if((micro.packet.head & MICROPACKET_ERROR)){ 237 if((micro.packet.head & MICROPACKET_ERROR)){
238 val = readl(dev_conf->regs); 238 val = readl(dev_conf->regs);
239 if((val & BIT_RAM_OVERFLOW)){ 239 if((val & BIT_RAM_OVERFLOW)){
240 channel->overflow += 1 ; 240 channel->overflow += 1 ;
241 } 241 }
243 channel->counetererr += 1 ; 243 channel->counetererr += 1 ;
244 } 244 }
245 if((val & BIT_INITIATOR_WARNING)){ 245 if((val & BIT_INITIATOR_WARNING)){
246 channel->transerr += 1 ; 246 channel->transerr += 1 ;
247 } 247 }
248 // 初期化して先頭から 248 //
249 reset_dma(dev_conf); 249 reset_dma(dev_conf);
250 ring_pos = data_pos = 0 ; 250 ring_pos = data_pos = 0 ;
251 break ; 251 break ;
252 } 252 }
253 // 未使用チャネルは捨てる 253 // 篏睡c
254 if(channel->valid == FALSE){ 254 if(channel->valid == FALSE){
255 continue ; 255 continue ;
256 } 256 }
257 mutex_lock(&channel->lock); 257 mutex_lock(&channel->lock);
258 // あふれたら読み出すまで待つ 258 // 泣茯水冴障у
259 while(1){ 259 while(1){
260 if(channel->size >= (channel->maxsize - PACKET_SIZE - 4)){ 260 if(channel->size >= (channel->maxsize - PACKET_SIZE - 4)){
261 // 該当チャンネルのDMA読みだし待ちにする 261 // 荅峨c潟DMA茯帥緇<
262 wake_up(&channel->wait_q); 262 wake_up(&channel->wait_q);
263 channel->req_dma = TRUE ; 263 channel->req_dma = TRUE ;
264 mutex_unlock(&channel->lock); 264 mutex_unlock(&channel->lock);
265 // タスクに時間を渡す為中断 265 // 帥鴻羝<坂賢
266 wait_event_timeout(dev_conf->dma_wait_q, (channel->req_dma == FALSE), 266 wait_event_timeout(dev_conf->dma_wait_q, (channel->req_dma == FALSE),
267 msecs_to_jiffies(500)); 267 msecs_to_jiffies(500));
268 mutex_lock(&channel->lock); 268 mutex_lock(&channel->lock);
269 channel->drop += 1 ; 269 channel->drop += 1 ;
270 }else{ 270 }else{
271 break ; 271 break ;
272 } 272 }
273 } 273 }
274 // 先頭で、一時バッファに残っている場合 274 // с筝<罧c翫
275 if((micro.packet.head & 0x02) && (channel->packet_size != 0)){ 275 if((micro.packet.head & 0x02) && (channel->packet_size != 0)){
276 channel->packet_size = 0 ; 276 channel->packet_size = 0 ;
277 } 277 }
278 // データコピー 278 // 若帥潟
279 channel->packet_buf[channel->packet_size] = micro.packet.data[2]; 279 channel->packet_buf[channel->packet_size] = micro.packet.data[2];
280 channel->packet_buf[channel->packet_size+1] = micro.packet.data[1]; 280 channel->packet_buf[channel->packet_size+1] = micro.packet.data[1];
281 channel->packet_buf[channel->packet_size+2] = micro.packet.data[0]; 281 channel->packet_buf[channel->packet_size+2] = micro.packet.data[0];
282 channel->packet_size += 3; 282 channel->packet_size += 3;
283 283
284 // パケットが出来たらコピーする 284 // 宴堺ャ潟若
285 if(channel->packet_size >= PACKET_SIZE){ 285 if(channel->packet_size >= PACKET_SIZE){
286 if (channel->pointer + channel->size >= channel->maxsize) { 286 if (channel->pointer + channel->size >= channel->maxsize) {
287 // リングバッファの境界を越えていてリングバッファの先頭に戻っている場合 287 // 潟違<紜莇潟違<祉c翫
288 // channel->pointer + channel->size - channel->maxsize でリングバッファ先頭からのアドレスになる 288 // channel->pointer + channel->size - channel->maxsize с潟違≦≪鴻
289 memcpy(&channel->buf[channel->pointer + channel->size - channel->maxsize], channel->packet_buf, PACKET_SIZE); 289 memcpy(&channel->buf[channel->pointer + channel->size - channel->maxsize], channel->packet_buf, PACKET_SIZE);
290 } else if (channel->pointer + channel->size + PACKET_SIZE > channel->maxsize) { 290 } else if (channel->pointer + channel->size + PACKET_SIZE > channel->maxsize) {
291 // リングバッファの境界をまたぐように書き込まれる場合 291 // 潟違<紜障吾莨若障翫
292 // リングバッファの境界まで書き込み 292 // 潟違<紜障ф吾莨若
293 __u32 tmp_size = channel->maxsize - (channel->pointer + channel->size); 293 __u32 tmp_size = channel->maxsize - (channel->pointer + channel->size);
294 memcpy(&channel->buf[channel->pointer + channel->size], channel->packet_buf, tmp_size); 294 memcpy(&channel->buf[channel->pointer + channel->size], channel->packet_buf, tmp_size);
295 // 先頭に戻って書き込み 295 // 祉c吾莨若
296 memcpy(channel->buf, &channel->packet_buf[tmp_size], PACKET_SIZE - tmp_size); 296 memcpy(channel->buf, &channel->packet_buf[tmp_size], PACKET_SIZE - tmp_size);
297 } else { 297 } else {
298 // リングバッファ内で収まる場合 298 // 潟違≦у障翫
299 // 通常の書き込み 299 // 絽吾吾莨若
300 memcpy(&channel->buf[channel->pointer + channel->size], channel->packet_buf, PACKET_SIZE); 300 memcpy(&channel->buf[channel->pointer + channel->size], channel->packet_buf, PACKET_SIZE);
301 } 301 }
302 channel->size += PACKET_SIZE ; 302 channel->size += PACKET_SIZE ;
303 channel->packet_size = 0 ; 303 channel->packet_size = 0 ;
304 } 304 }
307 curdataptr[(DMA_SIZE / sizeof(__u32)) - 2] = 0; 307 curdataptr[(DMA_SIZE / sizeof(__u32)) - 2] = 0;
308 308
309 if(data_pos >= DMA_RING_MAX){ 309 if(data_pos >= DMA_RING_MAX){
310 data_pos = 0; 310 data_pos = 0;
311 ring_pos += 1 ; 311 ring_pos += 1 ;
312 // DMAリングが変わった場合はインクリメント 312 // DMA潟違紊c翫ゃ潟<潟
313 writel(0x00000020, dev_conf->regs); 313 writel(0x00000020, dev_conf->regs);
314 if(ring_pos >= DMA_RING_SIZE){ 314 if(ring_pos >= DMA_RING_SIZE){
315 ring_pos = 0 ; 315 ring_pos = 0 ;
316 } 316 }
317 } 317 }
318 318
319 // 頻度を落す(wait until READ_SIZE) 319 // 糸墾純(wait until READ_SIZE)
320 for(lp = 0 ; lp < MAX_CHANNEL ; lp++){ 320 for(lp = 0 ; lp < MAX_CHANNEL ; lp++){
321 channel = dev_conf->channel[real_channel[lp]] ; 321 channel = dev_conf->channel[real_channel[lp]] ;
322 if((channel->size >= READ_SIZE) && (channel->valid == TRUE)){ 322 if((channel->size >= READ_SIZE) && (channel->valid == TRUE)){
323 wake_up(&channel->wait_q); 323 wake_up(&channel->wait_q);
324 } 324 }
366 channel->counetererr = 0 ; 366 channel->counetererr = 0 ;
367 channel->transerr = 0 ; 367 channel->transerr = 0 ;
368 channel->packet_size = 0 ; 368 channel->packet_size = 0 ;
369 file->private_data = channel; 369 file->private_data = channel;
370 mutex_lock(&channel->lock); 370 mutex_lock(&channel->lock);
371 // データ初期化 371 // 若水
372 channel->size = 0 ; 372 channel->size = 0 ;
373 mutex_unlock(&channel->lock); 373 mutex_unlock(&channel->lock);
374 mutex_unlock(&device[lp]->lock); 374 mutex_unlock(&device[lp]->lock);
375 return 0 ; 375 return 0 ;
376 } 376 }
390 channel->overflow, channel->counetererr, channel->transerr); 390 channel->overflow, channel->counetererr, channel->transerr);
391 channel->overflow = 0 ; 391 channel->overflow = 0 ;
392 channel->counetererr = 0 ; 392 channel->counetererr = 0 ;
393 channel->transerr = 0 ; 393 channel->transerr = 0 ;
394 channel->drop = 0 ; 394 channel->drop = 0 ;
395 // 停止している場合は起こす 395 // 罩≪翫莎激
396 if(channel->req_dma == TRUE){ 396 if(channel->req_dma == TRUE){
397 channel->req_dma = FALSE ; 397 channel->req_dma = FALSE ;
398 wake_up(&channel->ptr->dma_wait_q); 398 wake_up(&channel->ptr->dma_wait_q);
399 } 399 }
400 mutex_unlock(&channel->ptr->lock); 400 mutex_unlock(&channel->ptr->lock);
411 { 411 {
412 PT1_CHANNEL *channel = file->private_data; 412 PT1_CHANNEL *channel = file->private_data;
413 __u32 size ; 413 __u32 size ;
414 unsigned long dummy; 414 unsigned long dummy;
415 415
416 // READ_SIZE単位で起こされるのを待つ(CPU負荷対策) 416 // READ_SIZE篏ц儀緇(CPU莢桁丞)
417 if(channel->size < READ_SIZE){ 417 if(channel->size < READ_SIZE){
418 wait_event_timeout(channel->wait_q, (channel->size >= READ_SIZE), 418 wait_event_timeout(channel->wait_q, (channel->size >= READ_SIZE),
419 msecs_to_jiffies(500)); 419 msecs_to_jiffies(500));
420 } 420 }
421 mutex_lock(&channel->lock); 421 mutex_lock(&channel->lock);
422 if(!channel->size){ 422 if(!channel->size){
423 size = 0 ; 423 size = 0 ;
424 }else{ 424 }else{
425 __u32 tmp_size = 0; 425 __u32 tmp_size = 0;
426 if (cnt < channel->size) { 426 if (cnt < channel->size) {
427 // バッファにあるデータより小さい読み込みの場合 427 // <若帥絨茯粋昭帥翫
428 size = cnt; 428 size = cnt;
429 } else { 429 } else {
430 // バッファにあるデータ以上の読み込みの場合 430 // <若推札筝茯粋昭帥翫
431 size = channel->size; 431 size = channel->size;
432 } 432 }
433 if (channel->maxsize <= size + channel->pointer) { 433 if (channel->maxsize <= size + channel->pointer) {
434 // リングバッファの境界を越える場合 434 // 潟違<紜莇翫
435 tmp_size = channel->maxsize - channel->pointer; 435 tmp_size = channel->maxsize - channel->pointer;
436 // 境界までコピー 436 // 紜障с潟
437 dummy = copy_to_user(buf, &channel->buf[channel->pointer], tmp_size); 437 dummy = copy_to_user(buf, &channel->buf[channel->pointer], tmp_size);
438 // 残りをコピー 438 // 罧潟
439 dummy = copy_to_user(&buf[tmp_size], channel->buf, size - tmp_size); 439 dummy = copy_to_user(&buf[tmp_size], channel->buf, size - tmp_size);
440 channel->pointer = size - tmp_size; 440 channel->pointer = size - tmp_size;
441 } else { 441 } else {
442 // 普通にコピー 442 // 潟
443 dummy = copy_to_user(buf, &channel->buf[channel->pointer], size); 443 dummy = copy_to_user(buf, &channel->buf[channel->pointer], size);
444 channel->pointer += size; 444 channel->pointer += size;
445 } 445 }
446 channel->size -= size; 446 channel->size -= size;
447 } 447 }
448 // 読み終わったかつ使用しているのがが4K以下 448 // 茯睡cや戎4K篁ヤ
449 if(channel->req_dma == TRUE){ 449 if(channel->req_dma == TRUE){
450 channel->req_dma = FALSE ; 450 channel->req_dma = FALSE ;
451 wake_up(&channel->ptr->dma_wait_q); 451 wake_up(&channel->ptr->dma_wait_q);
452 } 452 }
453 mutex_unlock(&channel->lock); 453 mutex_unlock(&channel->lock);
632 DMA_CONTROL *dmactl; 632 DMA_CONTROL *dmactl;
633 __u32 *dmaptr ; 633 __u32 *dmaptr ;
634 __u32 addr ; 634 __u32 addr ;
635 __u32 *ptr ; 635 __u32 *ptr ;
636 636
637 //DMAリング作成 637 //DMA潟遺
638 for(lp = 0 ; lp < DMA_RING_SIZE ; lp++){ 638 for(lp = 0 ; lp < DMA_RING_SIZE ; lp++){
639 ptr = dev_conf->dmaptr[lp]; 639 ptr = dev_conf->dmaptr[lp];
640 if(lp == (DMA_RING_SIZE - 1)){ 640 if(lp == (DMA_RING_SIZE - 1)){
641 addr = (__u32)dev_conf->ring_dma[0]; 641 addr = (__u32)dev_conf->ring_dma[0];
642 }else{ 642 }else{
652 if(dmaptr == NULL){ 652 if(dmaptr == NULL){
653 printk(KERN_INFO "PT1:DMA ALLOC ERROR\n"); 653 printk(KERN_INFO "PT1:DMA ALLOC ERROR\n");
654 return -1 ; 654 return -1 ;
655 } 655 }
656 dmactl->data[lp2] = dmaptr ; 656 dmactl->data[lp2] = dmaptr ;
657 // DMAデータエリア初期化 657 // DMA若帥√
658 dmaptr[(DMA_SIZE / sizeof(__u32)) - 2] = 0 ; 658 dmaptr[(DMA_SIZE / sizeof(__u32)) - 2] = 0 ;
659 addr = (__u32)dmactl->ring_dma[lp2]; 659 addr = (__u32)dmactl->ring_dma[lp2];
660 addr >>= 12 ; 660 addr >>= 12 ;
661 memcpy(ptr, &addr, sizeof(__u32)); 661 memcpy(ptr, &addr, sizeof(__u32));
662 ptr += 1 ; 662 ptr += 1 ;
761 break; 761 break;
762 default: 762 default:
763 break; 763 break;
764 } 764 }
765 765
766 // PCIアドレスをマップする 766 // PCI≪鴻
767 dev_conf->mmio_start = pci_resource_start(pdev, 0); 767 dev_conf->mmio_start = pci_resource_start(pdev, 0);
768 dev_conf->mmio_len = pci_resource_len(pdev, 0); 768 dev_conf->mmio_len = pci_resource_len(pdev, 0);
769 dummy = request_mem_region(dev_conf->mmio_start, dev_conf->mmio_len, DEV_NAME); 769 dummy = request_mem_region(dev_conf->mmio_start, dev_conf->mmio_len, DEV_NAME);
770 if (!dummy) { 770 if (!dummy) {
771 printk(KERN_ERR "PT1:cannot request iomem (0x%llx).\n", (unsigned long long) dev_conf->mmio_start); 771 printk(KERN_ERR "PT1:cannot request iomem (0x%llx).\n", (unsigned long long) dev_conf->mmio_start);
775 dev_conf->regs = ioremap(dev_conf->mmio_start, dev_conf->mmio_len); 775 dev_conf->regs = ioremap(dev_conf->mmio_start, dev_conf->mmio_len);
776 if (!dev_conf->regs){ 776 if (!dev_conf->regs){
777 printk(KERN_ERR "pt1:Can't remap register area.\n"); 777 printk(KERN_ERR "pt1:Can't remap register area.\n");
778 goto out_err_regbase; 778 goto out_err_regbase;
779 } 779 }
780 // 初期化処理 780 //
781 if(xc3s_init(dev_conf->regs, dev_conf->cardtype)){ 781 if(xc3s_init(dev_conf->regs, dev_conf->cardtype)){
782 printk(KERN_ERR "Error xc3s_init\n"); 782 printk(KERN_ERR "Error xc3s_init\n");
783 goto out_err_fpga; 783 goto out_err_fpga;
784 } 784 }
785 // チューナリセット 785 // ャ若祉
786 settuner_reset(dev_conf->regs, dev_conf->cardtype, LNB_OFF, TUNER_POWER_ON_RESET_ENABLE); 786 settuner_reset(dev_conf->regs, dev_conf->cardtype, LNB_OFF, TUNER_POWER_ON_RESET_ENABLE);
787 schedule_timeout_interruptible(msecs_to_jiffies(100)); 787 schedule_timeout_interruptible(msecs_to_jiffies(100));
788 788
789 settuner_reset(dev_conf->regs, dev_conf->cardtype, LNB_OFF, TUNER_POWER_ON_RESET_DISABLE); 789 settuner_reset(dev_conf->regs, dev_conf->cardtype, LNB_OFF, TUNER_POWER_ON_RESET_DISABLE);
790 schedule_timeout_interruptible(msecs_to_jiffies(100)); 790 schedule_timeout_interruptible(msecs_to_jiffies(100));
791 mutex_init(&dev_conf->lock); 791 mutex_init(&dev_conf->lock);
792 792
793 // Tuner 初期化処理 793 // Tuner
794 for(lp = 0 ; lp < MAX_TUNER ; lp++){ 794 for(lp = 0 ; lp < MAX_TUNER ; lp++){
795 rc = tuner_init(dev_conf->regs, dev_conf->cardtype, &dev_conf->lock, lp); 795 rc = tuner_init(dev_conf->regs, dev_conf->cardtype, &dev_conf->lock, lp);
796 if(rc < 0){ 796 if(rc < 0){
797 printk(KERN_ERR "Error tuner_init\n"); 797 printk(KERN_ERR "Error tuner_init\n");
798 goto out_err_fpga; 798 goto out_err_fpga;
799 } 799 }
800 } 800 }
801 // 初期化完了 801 // 絎篋
802 for(lp = 0 ; lp < MAX_CHANNEL ; lp++){ 802 for(lp = 0 ; lp < MAX_CHANNEL ; lp++){
803 set_sleepmode(dev_conf->regs, &dev_conf->lock, 803 set_sleepmode(dev_conf->regs, &dev_conf->lock,
804 i2c_address[lp], channeltype[lp], TYPE_SLEEP); 804 i2c_address[lp], channeltype[lp], TYPE_SLEEP);
805 805
806 schedule_timeout_interruptible(msecs_to_jiffies(100)); 806 schedule_timeout_interruptible(msecs_to_jiffies(100));
808 rc = alloc_chrdev_region(&dev_conf->dev, 0, MAX_CHANNEL, DEV_NAME); 808 rc = alloc_chrdev_region(&dev_conf->dev, 0, MAX_CHANNEL, DEV_NAME);
809 if(rc < 0){ 809 if(rc < 0){
810 goto out_err_fpga; 810 goto out_err_fpga;
811 } 811 }
812 812
813 // 初期化 813 //
814 init_waitqueue_head(&dev_conf->dma_wait_q); 814 init_waitqueue_head(&dev_conf->dma_wait_q);
815 815
816 minor = MINOR(dev_conf->dev) ; 816 minor = MINOR(dev_conf->dev) ;
817 dev_conf->base_minor = minor ; 817 dev_conf->base_minor = minor ;
818 for(lp = 0 ; lp < MAX_PCI_DEVICE ; lp++){ 818 for(lp = 0 ; lp < MAX_PCI_DEVICE ; lp++){
832 if(!channel){ 832 if(!channel){
833 printk(KERN_ERR "PT1:out of memory !"); 833 printk(KERN_ERR "PT1:out of memory !");
834 return -ENOMEM ; 834 return -ENOMEM ;
835 } 835 }
836 836
837 // 共通情報 837 // 演
838 mutex_init(&channel->lock); 838 mutex_init(&channel->lock);
839 // 待ち状態を解除 839 // 緇∞倶茹i
840 channel->req_dma = FALSE ; 840 channel->req_dma = FALSE ;
841 // マイナー番号設定 841 // ゃ主埈┃絎
842 channel->minor = MINOR(dev_conf->dev) + lp ; 842 channel->minor = MINOR(dev_conf->dev) + lp ;
843 // 対象のI2Cデバイス 843 // 絲乗院I2Cゃ
844 channel->address = i2c_address[lp] ; 844 channel->address = i2c_address[lp] ;
845 channel->type = channeltype[lp] ; 845 channel->type = channeltype[lp] ;
846 // 実際のチューナ番号 846 // 絎ャ若
847 channel->channel = real_channel[lp] ; 847 channel->channel = real_channel[lp] ;
848 channel->ptr = dev_conf ; 848 channel->ptr = dev_conf ;
849 channel->size = 0 ; 849 channel->size = 0 ;
850 dev_conf->channel[lp] = channel ; 850 dev_conf->channel[lp] = channel ;
851 851
939 if(dev_conf->kthread) { 939 if(dev_conf->kthread) {
940 kthread_stop(dev_conf->kthread); 940 kthread_stop(dev_conf->kthread);
941 dev_conf->kthread = NULL; 941 dev_conf->kthread = NULL;
942 } 942 }
943 943
944 // DMA終了 944 // DMA腟篋
945 writel(0x08080000, dev_conf->regs); 945 writel(0x08080000, dev_conf->regs);
946 for(lp = 0 ; lp < 10 ; lp++){ 946 for(lp = 0 ; lp < 10 ; lp++){
947 val = readl(dev_conf->regs); 947 val = readl(dev_conf->regs);
948 if(!(val & (1 << 6))){ 948 if(!(val & (1 << 6))){
949 break ; 949 break ;