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comparison driver/pt1_pci.c @ 0:67e8eca28a80

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initial import
author Yoshiki Yazawa <yaz@honeyplanet.jp>
date Mon, 16 Feb 2009 15:41:49 +0900
parents
children 07b2fc07ff48
comparison
equal deleted inserted replaced
-1:000000000000 0:67e8eca28a80
1 /* pt1-pci.c: A PT1 on PCI bus driver for Linux. */
2 #define DRV_NAME "pt1-pci"
3 #define DRV_VERSION "1.00"
4 #define DRV_RELDATE "11/28/2008"
5
6
7 #include <linux/module.h>
8 #include <linux/kernel.h>
9 #include <linux/errno.h>
10 #include <linux/pci.h>
11 #include <linux/init.h>
12 #include <linux/interrupt.h>
13
14 #include <asm/system.h>
15 #include <asm/io.h>
16 #include <asm/irq.h>
17 #include <asm/uaccess.h>
18 #include <linux/version.h>
19 #include <linux/mutex.h>
20 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,23)
21 #include <linux/freezer.h>
22 #else
23 #define set_freezable()
24 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,11)
25 typedef struct pm_message {
26 int event;
27 } pm_message_t;
28 #endif
29 #endif
30 #include <linux/kthread.h>
31 #include <linux/dma-mapping.h>
32
33 #include <linux/fs.h>
34 #include <linux/cdev.h>
35
36 #include <linux/ioctl.h>
37
38 #include "pt1_com.h"
39 #include "pt1_pci.h"
40 #include "pt1_tuner.h"
41 #include "pt1_i2c.h"
42 #include "pt1_tuner_data.h"
43 #include "pt1_ioctl.h"
44
45 /* These identify the driver base version and may not be removed. */
46 static char version[] __devinitdata =
47 KERN_INFO DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " \n";
48
49 MODULE_AUTHOR("Tomoaki Ishikawa tomy@users.sourceforge.jp");
50 #define DRIVER_DESC "PCI earthsoft PT1 driver"
51 MODULE_DESCRIPTION(DRIVER_DESC);
52 MODULE_LICENSE("GPL");
53
54 static int debug = 1; /* 1 normal messages, 0 quiet .. 7 verbose. */
55 static int lnb = 0; /* LNB OFF:0 +11V:1 +15V:2 */
56
57 module_param(debug, int, 0);
58 module_param(lnb, int, 0);
59 MODULE_PARM_DESC(debug, "debug level (1-2)");
60 MODULE_PARM_DESC(debug, "LNB level (0:OFF 1:+11V 2:+15V)");
61
62 static struct pci_device_id pt1_pci_tbl[] = {
63 { 0x10ee, 0x211a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
64 { 0, }
65 };
66 MODULE_DEVICE_TABLE(pci, pt1_pci_tbl);
67 #define DEV_NAME "pt1video"
68
69 #define MAX_READ_BLOCK 4 // 1度に読み出す最大DMAバッファ数
70 #define MAX_PCI_DEVICE 64 // 最大64枚
71 #define DMA_SIZE 4096 // DMAバッファサイズ
72 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,22)
73 #define DMA_RING_SIZE 64 // RINGサイズ
74 #define DMA_RING_MAX 511 // 1RINGにいくつ詰めるか(1023はNGで511まで)
75 #define CHANEL_DMA_SIZE (1*1024*1024) // 地デジ用(16Mbps)
76 #define BS_CHANEL_DMA_SIZE (1*1024*1024) // BS用(32Mbps)
77 #else
78 #define DMA_RING_SIZE 28 // RINGサイズ
79 #define DMA_RING_MAX 511 // 1RINGにいくつ詰めるか(1023はNGで511まで)
80 #define CHANEL_DMA_SIZE (1*128*1024) // 地デジ用(16Mbps)
81 #define BS_CHANEL_DMA_SIZE (1*128*1024) // BS用(32Mbps)
82 #endif
83
84 typedef struct _DMA_CONTROL{
85 dma_addr_t ring_dma[DMA_RING_MAX] ; // DMA情報
86 __u32 *data[DMA_RING_MAX];
87 }DMA_CONTROL;
88
89 typedef struct _PT1_CHANNEL PT1_CHANNEL;
90
91 typedef struct _pt1_device{
92 unsigned long mmio_start ;
93 __u32 mmio_len ;
94 void __iomem *regs;
95 struct mutex lock ;
96 dma_addr_t ring_dma[DMA_RING_SIZE] ; // DMA情報
97 void *dmaptr[DMA_RING_SIZE] ;
98 struct task_struct *kthread;
99 dev_t dev ;
100 __u32 base_minor ;
101 struct cdev cdev[MAX_CHANNEL];
102 wait_queue_head_t dma_wait_q ;// for poll on reading
103 DMA_CONTROL dmactl[DMA_RING_SIZE];
104 PT1_CHANNEL *channel[MAX_CHANNEL];
105 }PT1_DEVICE;
106
107 typedef struct _MICRO_PACKET{
108 char data[3];
109 char head ;
110 }MICRO_PACKET;
111
112 struct _PT1_CHANNEL{
113 __u32 valid ; // 使用中フラグ
114 __u32 address ; // I2Cアドレス
115 __u32 channel ; // チャネル番号
116 int type ; // チャネルタイプ
117 __u32 drop ; // パケットドロップ数
118 struct mutex lock ; // CH別mutex_lock用
119 __u32 size ; // DMAされたサイズ
120 __u32 maxsize ; // DMA用バッファサイズ
121 __u32 bufsize ; // チャネルに割り振られたサイズ
122 __u32 overflow ; // オーバーフローエラー発生
123 __u32 counetererr ; // 転送カウンタ１エラー
124 __u32 transerr ; // 転送エラー
125 __u32 minor ; // マイナー番号
126 __u8 *buf; // CH別受信メモリ
127 __u8 req_dma ; // 溢れたチャネル
128 PT1_DEVICE *ptr ; // カード別情報
129 wait_queue_head_t wait_q ; // for poll on reading
130 };
131
132 // I2Cアドレス(video0, 1 = ISDB-S) (video2, 3 = ISDB-T)
133 int i2c_address[MAX_CHANNEL] = {T0_ISDB_S, T1_ISDB_S, T0_ISDB_T, T1_ISDB_T};
134 int real_chanel[MAX_CHANNEL] = {0, 2, 1, 3};
135 int channeltype[MAX_CHANNEL] = {CHANNEL_TYPE_ISDB_S, CHANNEL_TYPE_ISDB_S,
136 CHANNEL_TYPE_ISDB_T, CHANNEL_TYPE_ISDB_T};
137
138 static PT1_DEVICE *device[MAX_PCI_DEVICE];
139
140 #define PT1MAJOR 251
141 #define DRIVERNAME "pt1video"
142
143 static void reset_dma(PT1_DEVICE *dev_conf)
144 {
145
146 int lp ;
147 __u32 addr ;
148 int ring_pos = 0;
149 int data_pos = 0 ;
150 __u32 *dataptr ;
151
152 // データ初期化
153 for(ring_pos = 0 ; ring_pos < DMA_RING_SIZE ; ring_pos++){
154 for(data_pos = 0 ; data_pos < DMA_RING_MAX ; data_pos++){
155 dataptr = dev_conf->dmactl[ring_pos].data[data_pos];
156 // データあり？
157 if(dataptr[(DMA_SIZE / sizeof(__u32)) - 2] == 0){
158 break ;
159 }
160 }
161 }
162 // 転送カウンタをリセット
163 writel(0x00000010, dev_conf->regs);
164 // 転送カウンタをインクリメント
165 for(lp = 0 ; lp < DMA_RING_SIZE ; lp++){
166 writel(0x00000020, dev_conf->regs);
167 }
168
169 addr = (int)dev_conf->ring_dma[0] ;
170 addr >>= 12 ;
171 // DMAバッファ設定
172 writel(addr, dev_conf->regs + DMA_ADDR);
173 // DMA開始
174 writel(0x0c000040, dev_conf->regs);
175
176 }
177 static int pt1_thread(void *data)
178 {
179 PT1_DEVICE *dev_conf = data ;
180 PT1_CHANNEL *channel ;
181 int ring_pos = 0;
182 int data_pos = 0 ;
183 int lp ;
184 int chno ;
185 int lp2 ;
186 __u32 addr ;
187 __u32 *dataptr ;
188 __u32 *curdataptr ;
189 __u32 val ;
190 union mpacket{
191 __u32 val ;
192 MICRO_PACKET packet ;
193 }micro;
194
195 set_freezable();
196 reset_dma(dev_conf);
197 printk(KERN_INFO "pt1_thread run\n");
198
199 for(;;){
200 if(kthread_should_stop()){
201 break ;
202 }
203
204 for(;;){
205 dataptr = dev_conf->dmactl[ring_pos].data[data_pos];
206 // データあり？
207 if(dataptr[(DMA_SIZE / sizeof(__u32)) - 2] == 0){
208 break ;
209 }
210 micro.val = *dataptr ;
211 curdataptr = dataptr ;
212 data_pos += 1 ;
213 for(lp = 0 ; lp < (DMA_SIZE / sizeof(__u32)) ; lp++, dataptr++){
214 micro.val = *dataptr ;
215 chno = real_chanel[(((micro.packet.head >> 5) & 0x07) - 1)];
216 channel = dev_conf->channel[chno] ;
217 // エラーチェック
218 if((micro.packet.head & MICROPACKET_ERROR)){
219 val = readl(dev_conf->regs);
220 if((val & BIT_RAM_OVERFLOW)){
221 channel->overflow += 1 ;
222 }
223 if((val & BIT_INITIATOR_ERROR)){
224 channel->counetererr += 1 ;
225 }
226 if((val & BIT_INITIATOR_WARNING)){
227 channel->transerr += 1 ;
228 }
229 // 初期化して先頭から
230 reset_dma(dev_conf);
231 ring_pos = data_pos = 0 ;
232 break ;
233 }
234 // 未使用チャネルは捨てる
235 if(channel->valid == FALSE){
236 continue ;
237 }
238 mutex_lock(&channel->lock);
239 // あふれたら読み出すまで待つ
240 while(1){
241 if(channel->size >= (channel->maxsize - 4)){
242 // 該当チャンネルのDMA読みだし待ちにする
243 wake_up(&channel->wait_q);
244 channel->req_dma = TRUE ;
245 mutex_unlock(&channel->lock);
246 // タスクに時間を渡す為中断
247 wait_event_timeout(dev_conf->dma_wait_q, (channel->req_dma == FALSE),
248 msecs_to_jiffies(500));
249 mutex_lock(&channel->lock);
250 channel->drop += 1 ;
251 }else{
252 break ;
253 }
254 }
255 // データコピー
256 for(lp2 = 2 ; lp2 >= 0 ; lp2--){
257 channel->buf[channel->size] = micro.packet.data[lp2];
258 channel->size += 1 ;
259 }
260 mutex_unlock(&channel->lock);
261 }
262 curdataptr[(DMA_SIZE / sizeof(__u32)) - 2] = 0;
263
264 if(data_pos >= DMA_RING_MAX){
265 data_pos = 0;
266 ring_pos += 1 ;
267 // DMAリングが変わった場合はインクリメント
268 writel(0x00000020, dev_conf->regs);
269 if(ring_pos >= DMA_RING_SIZE){
270 ring_pos = 0 ;
271 }
272 }
273
274 // 頻度を落す(4Kで起動させる)
275 for(lp = 0 ; lp < MAX_CHANNEL ; lp++){
276 channel = dev_conf->channel[real_chanel[lp]] ;
277 if((channel->size >= DMA_SIZE) && (channel->valid == TRUE)){
278 wake_up(&channel->wait_q);
279 }
280 }
281 }
282 schedule_timeout_interruptible(msecs_to_jiffies(1));
283 }
284 return 0 ;
285 }
286 static int pt1_open(struct inode *inode, struct file *file)
287 {
288
289 int minor = iminor(inode);
290 int lp ;
291 int lp2 ;
292 PT1_CHANNEL *channel ;
293
294 for(lp = 0 ; lp < MAX_PCI_DEVICE ; lp++){
295 if(device[lp] == NULL){
296 return -EIO ;
297 }
298 printk(KERN_INFO "(%d)base_minor=%d: MAX=%d(%d)\n",
299 lp, device[lp]->base_minor,
300 (device[lp]->base_minor + MAX_CHANNEL), minor);
301 if((device[lp]->base_minor <= minor) &&
302 ((device[lp]->base_minor + MAX_CHANNEL) > minor)){
303 mutex_lock(&device[lp]->lock);
304 for(lp2 = 0 ; lp2 < MAX_CHANNEL ; lp2++){
305 channel = device[lp]->channel[lp2] ;
306 printk(KERN_INFO "Minor(%d:%d)\n", channel->minor, minor);
307 if(channel->minor == minor){
308 if(channel->valid == TRUE){
309 mutex_unlock(&device[lp]->lock);
310 return -EIO ;
311 }
312 channel->drop = 0 ;
313 channel->valid = TRUE ;
314 channel->overflow = 0 ;
315 channel->counetererr = 0 ;
316 channel->transerr = 0 ;
317 file->private_data = channel;
318 mutex_lock(&channel->lock);
319 // データ初期化
320 channel->size = 0 ;
321 mutex_unlock(&channel->lock);
322 mutex_unlock(&device[lp]->lock);
323 return 0 ;
324 }
325 }
326 }
327 }
328 return -EIO;
329 }
330 static int pt1_release(struct inode *inode, struct file *file)
331 {
332 int minor = iminor(inode);
333 PT1_CHANNEL *channel = file->private_data;
334
335 mutex_lock(&channel->ptr->lock);
336 SetStream(channel->ptr->regs, channel->channel, FALSE);
337 channel->valid = FALSE ;
338 printk(KERN_INFO "(%d)Drop=%08d:%08d:%08d:%08d\n", iminor(inode), channel->drop,
339 channel->overflow, channel->counetererr, channel->transerr);
340 channel->overflow = 0 ;
341 channel->counetererr = 0 ;
342 channel->transerr = 0 ;
343 channel->drop = 0 ;
344 // 停止している場合は起こす
345 if(channel->req_dma == TRUE){
346 channel->req_dma = FALSE ;
347 wake_up(&channel->ptr->dma_wait_q);
348 }
349 mutex_unlock(&channel->ptr->lock);
350 return 0;
351 }
352
353 static ssize_t pt1_read(struct file *file, char __user *buf, size_t cnt, loff_t * ppos)
354 {
355 PT1_CHANNEL *channel = file->private_data;
356 __u32 size ;
357
358
359 // 4K単位で起こされるのを待つ(CPU負荷対策)
360 if(channel->size < DMA_SIZE){
361 wait_event_timeout(channel->wait_q, (channel->size >= DMA_SIZE),
362 msecs_to_jiffies(500));
363 }
364 mutex_lock(&channel->lock);
365 if(!channel->size){
366 size = 0 ;
367 }else{
368 if(cnt < channel->size){
369 // バッファが足りない場合は残りを移動する
370 size = cnt ;
371 copy_to_user(buf, channel->buf, cnt);
372 memmove(channel->buf, &channel->buf[cnt], (channel->size - cnt));
373 channel->size -= cnt ;
374 }else{
375 size = channel->size ;
376 copy_to_user(buf, channel->buf, size);
377 channel->size = 0 ;
378 }
379 }
380 // 読み終わったかつ使用しているのがが4K以下
381 if((channel->req_dma == TRUE) && (channel->size < DMA_SIZE)){
382 channel->req_dma = FALSE ;
383 wake_up(&channel->ptr->dma_wait_q);
384 }
385 mutex_unlock(&channel->lock);
386 return size ;
387 }
388 static int SetFreq(PT1_CHANNEL *channel, FREQUENCY *freq)
389 {
390
391 switch(channel->type){
392 case CHANNEL_TYPE_ISDB_S:
393 {
394 ISDB_S_TMCC tmcc ;
395 int lp ;
396
397 if(bs_tune(channel->ptr->regs,
398 &channel->ptr->lock,
399 channel->address,
400 freq->frequencyno,
401 &tmcc) < 0){
402 return -EIO ;
403 }
404 printk(KERN_INFO "cn = (%x:%x)\n", (tmcc.cn[0] & 0xFF),
405 (tmcc.cn[1] & 0xFF));
406 printk(KERN_INFO "agc = (%x)\n", (tmcc.agc & 0xFF));
407
408 #if 0
409 printk(KERN_INFO "clockmargin = (%x)\n", (tmcc.clockmargin & 0xFF));
410 printk(KERN_INFO "carriermargin = (%x)\n", (tmcc.carriermargin & 0xFF));
411
412 for(lp = 0 ; lp < MAX_BS_TS_ID ; lp++){
413 if(tmcc.ts_id[lp].ts_id == 0xFFFF){
414 continue ;
415 }
416 printk(KERN_INFO "Slot(%d:%x)\n", lp, tmcc.ts_id[lp].ts_id);
417 printk(KERN_INFO "mode (low/high) = (%x:%x)\n",
418 tmcc.ts_id[lp].low_mode, tmcc.ts_id[lp].high_mode);
419 printk(KERN_INFO "slot (low/high) = (%x:%x)\n",
420 tmcc.ts_id[lp].low_slot,
421 tmcc.ts_id[lp].high_slot);
422 }
423 #endif
424 ts_lock(channel->ptr->regs,
425 &channel->ptr->lock,
426 channel->address,
427 tmcc.ts_id[freq->slot].ts_id);
428 }
429 break ;
430 case CHANNEL_TYPE_ISDB_T:
431 {
432 if(isdb_t_frequency(channel->ptr->regs,
433 &channel->ptr->lock,
434 channel->address,
435 freq->frequencyno, freq->slot) < 0){
436 return -EINVAL ;
437 }
438 }
439 }
440 return 0 ;
441 }
442 static int pt1_ioctl(struct inode *inode, struct file *file, unsigned int cmd, void *arg)
443 {
444 PT1_CHANNEL *channel = file->private_data;
445
446 switch(cmd){
447 case SET_CHANNEL:
448 {
449 FREQUENCY freq ;
450 copy_from_user(&freq, arg, sizeof(FREQUENCY));
451 return SetFreq(channel, &freq);
452 }
453 case START_REC:
454 SetStream(channel->ptr->regs, channel->channel, TRUE);
455 return 0 ;
456 case STOP_REC:
457 SetStream(channel->ptr->regs, channel->channel, FALSE);
458 return 0 ;
459 }
460 return -EINVAL;
461 }
462
463 /*
464 */
465 static const struct file_operations pt1_fops = {
466 .owner = THIS_MODULE,
467 .open = pt1_open,
468 .release = pt1_release,
469 .read = pt1_read,
470 .ioctl = pt1_ioctl,
471 .llseek = no_llseek,
472 };
473
474 int pt1_makering(struct pci_dev *pdev, PT1_DEVICE *dev_conf)
475 {
476 int lp ;
477 int lp2 ;
478 DMA_CONTROL *dmactl;
479 __u32 *dmaptr ;
480 __u32 addr ;
481 __u32 *ptr ;
482
483 //DMAリング作成
484 for(lp = 0 ; lp < DMA_RING_SIZE ; lp++){
485 ptr = dev_conf->dmaptr[lp];
486 if(lp == (DMA_RING_SIZE - 1)){
487 addr = (__u32)dev_conf->ring_dma[0];
488 }else{
489 addr = (__u32)dev_conf->ring_dma[(lp + 1)];
490 }
491 addr >>= 12 ;
492 memcpy(ptr, &addr, sizeof(__u32));
493 ptr += 1 ;
494
495 dmactl = &dev_conf->dmactl[lp];
496 for(lp2 = 0 ; lp2 < DMA_RING_MAX ; lp2++){
497 dmaptr = pci_alloc_consistent(pdev, DMA_SIZE, &dmactl->ring_dma[lp2]);
498 if(dmaptr == NULL){
499 printk(KERN_INFO "PT1:DMA ALLOC ERROR\n");
500 return -1 ;
501 }
502 dmactl->data[lp2] = dmaptr ;
503 // DMAデータエリア初期化
504 dmaptr[(DMA_SIZE / sizeof(__u32)) - 2] = 0 ;
505 addr = (__u32)dmactl->ring_dma[lp2];
506 addr >>= 12 ;
507 memcpy(ptr, &addr, sizeof(__u32));
508 ptr += 1 ;
509 }
510 }
511 return 0 ;
512 }
513 int pt1_dma_init(struct pci_dev *pdev, PT1_DEVICE *dev_conf)
514 {
515 int lp ;
516 void *ptr ;
517
518 for(lp = 0 ; lp < DMA_RING_SIZE ; lp++){
519 ptr = pci_alloc_consistent(pdev, DMA_SIZE, &dev_conf->ring_dma[lp]);
520 if(ptr == NULL){
521 printk(KERN_INFO "PT1:DMA ALLOC ERROR\n");
522 return -1 ;
523 }
524 dev_conf->dmaptr[lp] = ptr ;
525 }
526
527 return pt1_makering(pdev, dev_conf);
528 }
529 int pt1_dma_free(struct pci_dev *pdev, PT1_DEVICE *dev_conf)
530 {
531
532 int lp ;
533 int lp2 ;
534
535 for(lp = 0 ; lp < DMA_RING_SIZE ; lp++){
536 if(dev_conf->dmaptr[lp] != NULL){
537 pci_free_consistent(pdev, DMA_SIZE,
538 dev_conf->dmaptr[lp], dev_conf->ring_dma[lp]);
539 for(lp2 = 0 ; lp2 < DMA_RING_MAX ; lp2++){
540 if(dev_conf->dmactl[lp].data[lp2] != NULL){
541 pci_free_consistent(pdev, DMA_SIZE,
542 dev_conf->dmactl[lp].data[lp2],
543 dev_conf->dmactl[lp].ring_dma[lp2]);
544 }
545 }
546 }
547 }
548 return 0 ;
549 }
550 static int __devinit pt1_pci_init_one (struct pci_dev *pdev,
551 const struct pci_device_id *ent)
552 {
553 int rc ;
554 int lp ;
555 int minor ;
556 u16 cmd ;
557 PT1_DEVICE *dev_conf ;
558 PT1_CHANNEL *channel ;
559
560 rc = pci_enable_device(pdev);
561 if (rc)
562 return rc;
563 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
564 if (rc) {
565 printk(KERN_ERR "PT1:DMA MASK ERROR");
566 return rc;
567 }
568
569 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
570 if (!(cmd & PCI_COMMAND_MASTER)) {
571 printk(KERN_INFO "Attempting to enable Bus Mastering\n");
572 pci_set_master(pdev);
573 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
574 if (!(cmd & PCI_COMMAND_MASTER)) {
575 printk(KERN_ERR "Bus Mastering is not enabled\n");
576 return -EIO;
577 }
578 }
579 printk(KERN_INFO "Bus Mastering Enabled.\n");
580
581 dev_conf = kzalloc(sizeof(PT1_DEVICE), GFP_KERNEL);
582 if(!dev_conf){
583 printk(KERN_ERR "PT1:out of memory !");
584 return -ENOMEM ;
585 }
586 // PCIアドレスをマップする
587 dev_conf->mmio_start = pci_resource_start(pdev, 0);
588 dev_conf->mmio_len = pci_resource_len(pdev, 0);
589 rc = request_mem_region(dev_conf->mmio_start, dev_conf->mmio_len, DEV_NAME);
590 if (!rc) {
591 printk(KERN_ERR "PT1: cannot request iomem (0x%llx).\n", (unsigned long long) dev_conf->mmio_start);
592 goto out_err_regbase;
593 }
594
595 dev_conf->regs = ioremap(dev_conf->mmio_start, dev_conf->mmio_len);
596 if (!dev_conf->regs){
597 printk(KERN_ERR "pt1: Can't remap register area.\n");
598 goto out_err_regbase;
599 }
600 // 初期化処理
601 if(xc3s_init(dev_conf->regs)){
602 printk(KERN_ERR "Error xc3s_init\n");
603 goto out_err_fpga;
604 }
605 // チューナリセット
606 settuner_reset(dev_conf->regs, LNB_OFF, TUNER_POWER_ON_RESET_ENABLE);
607 schedule_timeout_interruptible(msecs_to_jiffies(50));
608
609 settuner_reset(dev_conf->regs, lnb, TUNER_POWER_ON_RESET_DISABLE);
610 schedule_timeout_interruptible(msecs_to_jiffies(10));
611 mutex_init(&dev_conf->lock);
612
613 // Tuner 初期化処理
614 for(lp = 0 ; lp < MAX_TUNER ; lp++){
615 rc = tuner_init(dev_conf->regs, &dev_conf->lock, lp);
616 if(rc < 0){
617 printk(KERN_ERR "Error tuner_init\n");
618 goto out_err_fpga;
619 }
620 }
621 // 初期化完了
622 for(lp = 0 ; lp < MAX_CHANNEL ; lp++){
623 set_sleepmode(dev_conf->regs, &dev_conf->lock,
624 i2c_address[lp], channeltype[lp], TYPE_SLEEP);
625
626 schedule_timeout_interruptible(msecs_to_jiffies(50));
627 }
628 rc = alloc_chrdev_region(&dev_conf->dev, 0, MAX_CHANNEL, DEV_NAME);
629 if(rc < 0){
630 goto out_err_fpga;
631 }
632
633 // 初期化
634 init_waitqueue_head(&dev_conf->dma_wait_q);
635
636 minor = MINOR(dev_conf->dev) ;
637 dev_conf->base_minor = minor ;
638 for(lp = 0 ; lp < MAX_PCI_DEVICE ; lp++){
639 if(device[lp] == NULL){
640 device[lp] = dev_conf ;
641 printk(KERN_INFO "Alloc[%d]\n", lp);
642 break ;
643 }
644 }
645 for(lp = 0 ; lp < MAX_CHANNEL ; lp++){
646 cdev_init(&dev_conf->cdev[lp], &pt1_fops);
647 cdev_add(&dev_conf->cdev[lp], MKDEV(MAJOR(dev_conf->dev), (MINOR(dev_conf->dev) + lp)), 1);
648 channel = kzalloc(sizeof(PT1_CHANNEL), GFP_KERNEL);
649 if(!channel){
650 printk(KERN_ERR "PT1:out of memory !");
651 return -ENOMEM ;
652 }
653
654 // 共通情報
655 mutex_init(&channel->lock);
656 // 待ち状態を解除
657 channel->req_dma = FALSE ;
658 // マイナー番号設定
659 channel->minor = MINOR(dev_conf->dev) + lp ;
660 printk(KERN_INFO "Minor[%d]\n", channel->minor);
661 // 対象のI2Cデバイス
662 channel->address = i2c_address[lp] ;
663 channel->type = channeltype[lp] ;
664 // 実際のチューナ番号
665 channel->channel = real_chanel[lp] ;
666 channel->ptr = dev_conf ;
667 channel->size = 0 ;
668 dev_conf->channel[lp] = channel ;
669
670 init_waitqueue_head(&channel->wait_q);
671
672 switch(channel->type){
673 case CHANNEL_TYPE_ISDB_T:
674 channel->maxsize = CHANEL_DMA_SIZE ;
675 channel->buf = kzalloc(CHANEL_DMA_SIZE, GFP_KERNEL);
676 break ;
677 case CHANNEL_TYPE_ISDB_S:
678 channel->maxsize = BS_CHANEL_DMA_SIZE ;
679 channel->buf = kzalloc(BS_CHANEL_DMA_SIZE, GFP_KERNEL);
680 break ;
681 }
682 if(channel->buf == NULL){
683 goto out_err_v4l;
684 }
685 #if 0
686 dev_conf->vdev[lp] = video_device_alloc();
687 memcpy(dev_conf->vdev[lp], &pt1_template, sizeof(pt1_template));
688 video_set_drvdata(dev_conf->vdev[lp], channel);
689 video_register_device(dev_conf->vdev[lp], VFL_TYPE_GRABBER, -1);
690 #endif
691 }
692 if(pt1_dma_init(pdev, dev_conf) < 0){
693 goto out_err_dma;
694 }
695 dev_conf->kthread = kthread_run(pt1_thread, dev_conf, "pt1");
696 pci_set_drvdata(pdev, dev_conf);
697 return 0;
698
699 out_err_dma:
700 pt1_dma_free(pdev, dev_conf);
701 out_err_v4l:
702 for(lp = 0 ; lp < MAX_CHANNEL ; lp++){
703 if(dev_conf->channel[lp] != NULL){
704 if(dev_conf->channel[lp]->buf != NULL){
705 kfree(dev_conf->channel[lp]->buf);
706 }
707 kfree(dev_conf->channel[lp]);
708 }
709 }
710 out_err_fpga:
711 writel(0xb0b0000, dev_conf->regs);
712 writel(0, dev_conf->regs + 4);
713 iounmap(dev_conf->regs);
714 release_mem_region(dev_conf->mmio_start, dev_conf->mmio_len);
715 kfree(dev_conf);
716 out_err_regbase:
717 return -EIO;
718
719 }
720
721 static void __devexit pt1_pci_remove_one(struct pci_dev *pdev)
722 {
723
724 int lp ;
725 __u32 val ;
726 PT1_DEVICE *dev_conf = (PT1_DEVICE *)pci_get_drvdata(pdev);
727
728 if(dev_conf){
729 if(dev_conf->kthread) {
730 kthread_stop(dev_conf->kthread);
731 dev_conf->kthread = NULL;
732 }
733
734 // DMA終了
735 writel(0x08080000, dev_conf->regs);
736 for(lp = 0 ; lp < 10 ; lp++){
737 val = readl(dev_conf->regs);
738 if(!(val & (1 << 6))){
739 break ;
740 }
741 schedule_timeout_interruptible(msecs_to_jiffies(1));
742 }
743 pt1_dma_free(pdev, dev_conf);
744 for(lp = 0 ; lp < MAX_CHANNEL ; lp++){
745 if(dev_conf->channel[lp] != NULL){
746 cdev_del(&dev_conf->cdev[lp]);
747 kfree(dev_conf->channel[lp]->buf);
748 kfree(dev_conf->channel[lp]);
749 }
750 }
751 unregister_chrdev_region(dev_conf->dev, MAX_CHANNEL);
752 writel(0xb0b0000, dev_conf->regs);
753 writel(0, dev_conf->regs + 4);
754 settuner_reset(dev_conf->regs, LNB_OFF, TUNER_POWER_OFF);
755 release_mem_region(dev_conf->mmio_start, dev_conf->mmio_len);
756 iounmap(dev_conf->regs);
757 kfree(dev_conf);
758 }
759 pci_set_drvdata(pdev, NULL);
760 }
761 #ifdef CONFIG_PM
762
763 static int pt1_pci_suspend (struct pci_dev *pdev, pm_message_t state)
764 {
765 return 0;
766 }
767
768 static int pt1_pci_resume (struct pci_dev *pdev)
769 {
770 return 0;
771 }
772
773 #endif /* CONFIG_PM */
774
775
776 static struct pci_driver pt1_driver = {
777 .name = DRV_NAME,
778 .probe = pt1_pci_init_one,
779 .remove = __devexit_p(pt1_pci_remove_one),
780 .id_table = pt1_pci_tbl,
781 #ifdef CONFIG_PM
782 .suspend = pt1_pci_suspend,
783 .resume = pt1_pci_resume,
784 #endif /* CONFIG_PM */
785
786 };
787
788
789 static int __init pt1_pci_init(void)
790 {
791 return pci_register_driver(&pt1_driver);
792 }
793
794
795 static void __exit pt1_pci_cleanup(void)
796 {
797 pci_unregister_driver (&pt1_driver);
798 }
799
800 module_init(pt1_pci_init);
801 module_exit(pt1_pci_cleanup);