comparison driver/pt1_pci.c @ 124:f2ae5ddeed7e

minor improvement: - extend yielding period - unroll loop where copying from micro-packet
author Yoshiki Yazawa <yaz@honeyplanet.jp>
date Thu, 16 Feb 2012 13:11:38 +0900
parents 3914cc1b2375
children 2dc994610477
comparison
equal deleted inserted replaced
122:313d8551b66c 124:f2ae5ddeed7e
72 72
73 #define PACKET_SIZE 188 // 1パケット長 73 #define PACKET_SIZE 188 // 1パケット長
74 #define MAX_READ_BLOCK 4 // 1度に読み出す最大DMAバッファ数 74 #define MAX_READ_BLOCK 4 // 1度に読み出す最大DMAバッファ数
75 #define MAX_PCI_DEVICE 128 // 最大64枚 75 #define MAX_PCI_DEVICE 128 // 最大64枚
76 #define DMA_SIZE 4096 // DMAバッファサイズ 76 #define DMA_SIZE 4096 // DMAバッファサイズ
77 #define DMA_RING_SIZE 128 // RINGサイズ 77 #define DMA_RING_SIZE 128 // number of DMA RINGS
78 #define DMA_RING_MAX 511 // 1RINGにいくつ詰めるか(1023はNGで511まで) 78 #define DMA_RING_MAX 511 // number of DMA entries in a RING(1023はNGで511まで)
79 #define CHANEL_DMA_SIZE (2*1024*1024) // 地デジ用(16Mbps) 79 #define CHANNEL_DMA_SIZE (2*1024*1024) // 地デジ用(16Mbps)
80 #define BS_CHANEL_DMA_SIZE (4*1024*1024) // BS用(32Mbps) 80 #define BS_CHANNEL_DMA_SIZE (4*1024*1024) // BS用(32Mbps)
81 #define READ_SIZE (16*DMA_SIZE) 81 #define READ_SIZE (16*DMA_SIZE)
82 82
83 typedef struct _DMA_CONTROL{ 83 typedef struct _DMA_CONTROL{
84 dma_addr_t ring_dma[DMA_RING_MAX] ; // DMA情報 84 dma_addr_t ring_dma[DMA_RING_MAX] ; // DMA情報
85 __u32 *data[DMA_RING_MAX]; 85 __u32 *data[DMA_RING_MAX];
182 PT1_CHANNEL *channel ; 182 PT1_CHANNEL *channel ;
183 int ring_pos = 0; 183 int ring_pos = 0;
184 int data_pos = 0 ; 184 int data_pos = 0 ;
185 int lp ; 185 int lp ;
186 int chno ; 186 int chno ;
187 int lp2 ;
188 int dma_channel ; 187 int dma_channel ;
189 int packet_pos ; 188 int packet_pos ;
190 __u32 *dataptr ; 189 __u32 *dataptr ;
191 __u32 *curdataptr ; 190 __u32 *curdataptr ;
192 __u32 val ; 191 __u32 val ;
265 // 先頭で、一時バッファに残っている場合 264 // 先頭で、一時バッファに残っている場合
266 if((micro.packet.head & 0x02) && (channel->packet_size != 0)){ 265 if((micro.packet.head & 0x02) && (channel->packet_size != 0)){
267 channel->packet_size = 0 ; 266 channel->packet_size = 0 ;
268 } 267 }
269 // データコピー 268 // データコピー
270 for(lp2 = 2 ; lp2 >= 0 ; lp2--){ 269 channel->packet_buf[channel->packet_size] = micro.packet.data[2];
271 channel->packet_buf[channel->packet_size] = micro.packet.data[lp2] ; 270 channel->packet_buf[channel->packet_size+1] = micro.packet.data[1];
272 channel->packet_size += 1 ; 271 channel->packet_buf[channel->packet_size+2] = micro.packet.data[0];
273 } 272 channel->packet_size += 3;
274 273
275 // パケットが出来たらコピーする 274 // パケットが出来たらコピーする
276 if(channel->packet_size >= PACKET_SIZE){ 275 if(channel->packet_size >= PACKET_SIZE){
277 if (channel->pointer + channel->size >= channel->maxsize) { 276 if (channel->pointer + channel->size >= channel->maxsize) {
278 // リングバッファの境界を越えていてリングバッファの先頭に戻っている場合 277 // リングバッファの境界を越えていてリングバッファの先頭に戻っている場合
313 if((channel->size >= READ_SIZE) && (channel->valid == TRUE)){ 312 if((channel->size >= READ_SIZE) && (channel->valid == TRUE)){
314 wake_up(&channel->wait_q); 313 wake_up(&channel->wait_q);
315 } 314 }
316 } 315 }
317 } 316 }
318 schedule_timeout_interruptible(msecs_to_jiffies(10)); 317 schedule_timeout_interruptible(msecs_to_jiffies(100));
319 } 318 }
320 return 0 ; 319 return 0 ;
321 } 320 }
322 static int pt1_open(struct inode *inode, struct file *file) 321 static int pt1_open(struct inode *inode, struct file *file)
323 { 322 {
347 346
348 /* wake tuner up */ 347 /* wake tuner up */
349 set_sleepmode(channel->ptr->regs, &channel->lock, 348 set_sleepmode(channel->ptr->regs, &channel->lock,
350 channel->address, channel->type, 349 channel->address, channel->type,
351 TYPE_WAKEUP); 350 TYPE_WAKEUP);
352 schedule_timeout_interruptible(msecs_to_jiffies(50)); 351 schedule_timeout_interruptible(msecs_to_jiffies(100));
353 352
354 channel->drop = 0 ; 353 channel->drop = 0 ;
355 channel->valid = TRUE ; 354 channel->valid = TRUE ;
356 channel->overflow = 0 ; 355 channel->overflow = 0 ;
357 channel->counetererr = 0 ; 356 channel->counetererr = 0 ;
391 mutex_unlock(&channel->ptr->lock); 390 mutex_unlock(&channel->ptr->lock);
392 391
393 /* send tuner to sleep */ 392 /* send tuner to sleep */
394 set_sleepmode(channel->ptr->regs, &channel->lock, 393 set_sleepmode(channel->ptr->regs, &channel->lock,
395 channel->address, channel->type, TYPE_SLEEP); 394 channel->address, channel->type, TYPE_SLEEP);
396 schedule_timeout_interruptible(msecs_to_jiffies(50)); 395 schedule_timeout_interruptible(msecs_to_jiffies(100));
397 396
398 return 0; 397 return 0;
399 } 398 }
400 399
401 static ssize_t pt1_read(struct file *file, char __user *buf, size_t cnt, loff_t * ppos) 400 static ssize_t pt1_read(struct file *file, char __user *buf, size_t cnt, loff_t * ppos)
773 printk(KERN_ERR "Error xc3s_init\n"); 772 printk(KERN_ERR "Error xc3s_init\n");
774 goto out_err_fpga; 773 goto out_err_fpga;
775 } 774 }
776 // チューナリセット 775 // チューナリセット
777 settuner_reset(dev_conf->regs, dev_conf->cardtype, LNB_OFF, TUNER_POWER_ON_RESET_ENABLE); 776 settuner_reset(dev_conf->regs, dev_conf->cardtype, LNB_OFF, TUNER_POWER_ON_RESET_ENABLE);
778 schedule_timeout_interruptible(msecs_to_jiffies(50)); 777 schedule_timeout_interruptible(msecs_to_jiffies(100));
779 778
780 settuner_reset(dev_conf->regs, dev_conf->cardtype, LNB_OFF, TUNER_POWER_ON_RESET_DISABLE); 779 settuner_reset(dev_conf->regs, dev_conf->cardtype, LNB_OFF, TUNER_POWER_ON_RESET_DISABLE);
781 schedule_timeout_interruptible(msecs_to_jiffies(10)); 780 schedule_timeout_interruptible(msecs_to_jiffies(100));
782 mutex_init(&dev_conf->lock); 781 mutex_init(&dev_conf->lock);
783 782
784 // Tuner 初期化処理 783 // Tuner 初期化処理
785 for(lp = 0 ; lp < MAX_TUNER ; lp++){ 784 for(lp = 0 ; lp < MAX_TUNER ; lp++){
786 rc = tuner_init(dev_conf->regs, dev_conf->cardtype, &dev_conf->lock, lp); 785 rc = tuner_init(dev_conf->regs, dev_conf->cardtype, &dev_conf->lock, lp);
792 // 初期化完了 791 // 初期化完了
793 for(lp = 0 ; lp < MAX_CHANNEL ; lp++){ 792 for(lp = 0 ; lp < MAX_CHANNEL ; lp++){
794 set_sleepmode(dev_conf->regs, &dev_conf->lock, 793 set_sleepmode(dev_conf->regs, &dev_conf->lock,
795 i2c_address[lp], channeltype[lp], TYPE_SLEEP); 794 i2c_address[lp], channeltype[lp], TYPE_SLEEP);
796 795
797 schedule_timeout_interruptible(msecs_to_jiffies(50)); 796 schedule_timeout_interruptible(msecs_to_jiffies(100));
798 } 797 }
799 rc = alloc_chrdev_region(&dev_conf->dev, 0, MAX_CHANNEL, DEV_NAME); 798 rc = alloc_chrdev_region(&dev_conf->dev, 0, MAX_CHANNEL, DEV_NAME);
800 if(rc < 0){ 799 if(rc < 0){
801 goto out_err_fpga; 800 goto out_err_fpga;
802 } 801 }
842 841
843 init_waitqueue_head(&channel->wait_q); 842 init_waitqueue_head(&channel->wait_q);
844 843
845 switch(channel->type){ 844 switch(channel->type){
846 case CHANNEL_TYPE_ISDB_T: 845 case CHANNEL_TYPE_ISDB_T:
847 channel->maxsize = CHANEL_DMA_SIZE ; 846 channel->maxsize = CHANNEL_DMA_SIZE ;
848 channel->buf = vmalloc(CHANEL_DMA_SIZE); 847 channel->buf = vmalloc(CHANNEL_DMA_SIZE);
849 channel->pointer = 0; 848 channel->pointer = 0;
850 break ; 849 break ;
851 case CHANNEL_TYPE_ISDB_S: 850 case CHANNEL_TYPE_ISDB_S:
852 channel->maxsize = BS_CHANEL_DMA_SIZE ; 851 channel->maxsize = BS_CHANNEL_DMA_SIZE ;
853 channel->buf = vmalloc(BS_CHANEL_DMA_SIZE); 852 channel->buf = vmalloc(BS_CHANNEL_DMA_SIZE);
854 channel->pointer = 0; 853 channel->pointer = 0;
855 break ; 854 break ;
856 } 855 }
857 if(channel->buf == NULL){ 856 if(channel->buf == NULL){
858 goto out_err_v4l; 857 goto out_err_v4l;
937 for(lp = 0 ; lp < 10 ; lp++){ 936 for(lp = 0 ; lp < 10 ; lp++){
938 val = readl(dev_conf->regs); 937 val = readl(dev_conf->regs);
939 if(!(val & (1 << 6))){ 938 if(!(val & (1 << 6))){
940 break ; 939 break ;
941 } 940 }
942 schedule_timeout_interruptible(msecs_to_jiffies(1)); 941 schedule_timeout_interruptible(msecs_to_jiffies(100));
943 } 942 }
944 pt1_dma_free(pdev, dev_conf); 943 pt1_dma_free(pdev, dev_conf);
945 for(lp = 0 ; lp < MAX_CHANNEL ; lp++){ 944 for(lp = 0 ; lp < MAX_CHANNEL ; lp++){
946 if(dev_conf->channel[lp] != NULL){ 945 if(dev_conf->channel[lp] != NULL){
947 cdev_del(&dev_conf->cdev[lp]); 946 cdev_del(&dev_conf->cdev[lp]);