annotate src/console/Spc_Dsp.cxx @ 1219:31c44eb25a4a

Fix more crashes and metadata.
author William Pitcock <nenolod@atheme-project.org>
date Sun, 08 Jul 2007 22:39:59 -0500
parents b391fddc35b2
children a1fccf242404
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1 // snes_spc 0.9.0. http://www.slack.net/~ant/
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3 #include "Spc_Dsp.h"
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4
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5 #include "blargg_endian.h"
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6 #include <string.h>
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7
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8 /* Copyright (C) 2007 Shay Green. This module is free software; you
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9 can redistribute it and/or modify it under the terms of the GNU Lesser
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10 General Public License as published by the Free Software Foundation; either
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11 version 2.1 of the License, or (at your option) any later version. This
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12 module is distributed in the hope that it will be useful, but WITHOUT ANY
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13 WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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14 FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more
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15 details. You should have received a copy of the GNU Lesser General Public
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16 License along with this module; if not, write to the Free Software Foundation,
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17 Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
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18
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19 #include "blargg_source.h"
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20
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21 #ifdef BLARGG_ENABLE_OPTIMIZER
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22 #include BLARGG_ENABLE_OPTIMIZER
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23 #endif
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24
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25 #if INT_MAX < 0x7FFFFFFF
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26 #error "Requires that int type have at least 32 bits"
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27 #endif
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29
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30 // TODO: add to blargg_endian.h
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31 #define GET_LE16SA( addr ) ((BOOST::int16_t) GET_LE16( addr ))
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32 #define GET_LE16A( addr ) GET_LE16( addr )
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33 #define SET_LE16A( addr, data ) SET_LE16( addr, data )
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34
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35 static BOOST::uint8_t const initial_regs [Spc_Dsp::register_count] =
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36 {
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37 0x45,0x8B,0x5A,0x9A,0xE4,0x82,0x1B,0x78,0x00,0x00,0xAA,0x96,0x89,0x0E,0xE0,0x80,
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38 0x2A,0x49,0x3D,0xBA,0x14,0xA0,0xAC,0xC5,0x00,0x00,0x51,0xBB,0x9C,0x4E,0x7B,0xFF,
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39 0xF4,0xFD,0x57,0x32,0x37,0xD9,0x42,0x22,0x00,0x00,0x5B,0x3C,0x9F,0x1B,0x87,0x9A,
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40 0x6F,0x27,0xAF,0x7B,0xE5,0x68,0x0A,0xD9,0x00,0x00,0x9A,0xC5,0x9C,0x4E,0x7B,0xFF,
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41 0xEA,0x21,0x78,0x4F,0xDD,0xED,0x24,0x14,0x00,0x00,0x77,0xB1,0xD1,0x36,0xC1,0x67,
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42 0x52,0x57,0x46,0x3D,0x59,0xF4,0x87,0xA4,0x00,0x00,0x7E,0x44,0x9C,0x4E,0x7B,0xFF,
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43 0x75,0xF5,0x06,0x97,0x10,0xC3,0x24,0xBB,0x00,0x00,0x7B,0x7A,0xE0,0x60,0x12,0x0F,
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44 0xF7,0x74,0x1C,0xE5,0x39,0x3D,0x73,0xC1,0x00,0x00,0x7A,0xB3,0xFF,0x4E,0x7B,0xFF
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45 };
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46
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47 // if ( io < -32768 ) io = -32768;
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48 // if ( io > 32767 ) io = 32767;
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49 #define CLAMP16( io )\
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50 {\
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51 if ( (int16_t) io != io )\
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52 io = (io >> 31) ^ 0x7FFF;\
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53 }
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54
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55 // Access global DSP register
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56 #define REG(n) m.regs [r_##n]
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57
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58 // Access voice DSP register
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59 #define VREG(r,n) r [v_##n]
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60
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61 #define WRITE_SAMPLES( l, r, out ) \
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62 {\
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63 out [0] = l;\
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64 out [1] = r;\
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65 out += 2;\
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66 if ( out >= m.out_end )\
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67 {\
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68 check( out == m.out_end );\
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69 check( m.out_end != &m.extra [extra_size] || \
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70 (m.extra <= m.out_begin && m.extra < &m.extra [extra_size]) );\
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71 out = m.extra;\
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72 m.out_end = &m.extra [extra_size];\
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73 }\
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74 }\
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75
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76 void Spc_Dsp::set_output( sample_t* out, int size )
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77 {
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78 require( (size & 1) == 0 ); // must be even
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79 if ( !out )
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80 {
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81 out = m.extra;
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82 size = extra_size;
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83 }
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84 m.out_begin = out;
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85 m.out = out;
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86 m.out_end = out + size;
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87 }
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88
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89 // Volume registers and efb are signed! Easy to forget int8_t cast.
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90 // Prefixes are to avoid accidental use of locals with same names.
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91
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92 // Interleved gauss table (to improve cache coherency)
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93 // interleved_gauss [i] = gauss [(i & 1) * 256 + 255 - (i >> 1 & 0xFF)]
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94 static short const interleved_gauss [512] =
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95 {
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96 370,1305, 366,1305, 362,1304, 358,1304, 354,1304, 351,1304, 347,1304, 343,1303,
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97 339,1303, 336,1303, 332,1302, 328,1302, 325,1301, 321,1300, 318,1300, 314,1299,
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98 311,1298, 307,1297, 304,1297, 300,1296, 297,1295, 293,1294, 290,1293, 286,1292,
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99 283,1291, 280,1290, 276,1288, 273,1287, 270,1286, 267,1284, 263,1283, 260,1282,
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100 257,1280, 254,1279, 251,1277, 248,1275, 245,1274, 242,1272, 239,1270, 236,1269,
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101 233,1267, 230,1265, 227,1263, 224,1261, 221,1259, 218,1257, 215,1255, 212,1253,
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102 210,1251, 207,1248, 204,1246, 201,1244, 199,1241, 196,1239, 193,1237, 191,1234,
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103 188,1232, 186,1229, 183,1227, 180,1224, 178,1221, 175,1219, 173,1216, 171,1213,
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104 168,1210, 166,1207, 163,1205, 161,1202, 159,1199, 156,1196, 154,1193, 152,1190,
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105 150,1186, 147,1183, 145,1180, 143,1177, 141,1174, 139,1170, 137,1167, 134,1164,
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106 132,1160, 130,1157, 128,1153, 126,1150, 124,1146, 122,1143, 120,1139, 118,1136,
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107 117,1132, 115,1128, 113,1125, 111,1121, 109,1117, 107,1113, 106,1109, 104,1106,
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108 102,1102, 100,1098, 99,1094, 97,1090, 95,1086, 94,1082, 92,1078, 90,1074,
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109 89,1070, 87,1066, 86,1061, 84,1057, 83,1053, 81,1049, 80,1045, 78,1040,
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110 77,1036, 76,1032, 74,1027, 73,1023, 71,1019, 70,1014, 69,1010, 67,1005,
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111 66,1001, 65, 997, 64, 992, 62, 988, 61, 983, 60, 978, 59, 974, 58, 969,
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112 56, 965, 55, 960, 54, 955, 53, 951, 52, 946, 51, 941, 50, 937, 49, 932,
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113 48, 927, 47, 923, 46, 918, 45, 913, 44, 908, 43, 904, 42, 899, 41, 894,
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114 40, 889, 39, 884, 38, 880, 37, 875, 36, 870, 36, 865, 35, 860, 34, 855,
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115 33, 851, 32, 846, 32, 841, 31, 836, 30, 831, 29, 826, 29, 821, 28, 816,
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116 27, 811, 27, 806, 26, 802, 25, 797, 24, 792, 24, 787, 23, 782, 23, 777,
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117 22, 772, 21, 767, 21, 762, 20, 757, 20, 752, 19, 747, 19, 742, 18, 737,
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118 17, 732, 17, 728, 16, 723, 16, 718, 15, 713, 15, 708, 15, 703, 14, 698,
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119 14, 693, 13, 688, 13, 683, 12, 678, 12, 674, 11, 669, 11, 664, 11, 659,
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120 10, 654, 10, 649, 10, 644, 9, 640, 9, 635, 9, 630, 8, 625, 8, 620,
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121 8, 615, 7, 611, 7, 606, 7, 601, 6, 596, 6, 592, 6, 587, 6, 582,
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122 5, 577, 5, 573, 5, 568, 5, 563, 4, 559, 4, 554, 4, 550, 4, 545,
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123 4, 540, 3, 536, 3, 531, 3, 527, 3, 522, 3, 517, 2, 513, 2, 508,
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124 2, 504, 2, 499, 2, 495, 2, 491, 2, 486, 1, 482, 1, 477, 1, 473,
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125 1, 469, 1, 464, 1, 460, 1, 456, 1, 451, 1, 447, 1, 443, 1, 439,
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126 0, 434, 0, 430, 0, 426, 0, 422, 0, 418, 0, 414, 0, 410, 0, 405,
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127 0, 401, 0, 397, 0, 393, 0, 389, 0, 385, 0, 381, 0, 378, 0, 374,
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128 };
1037
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129
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130
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131 //// Counters
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132
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133 #define RATE( rate, div )\
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134 (rate >= div ? rate / div * 8 - 1 : rate - 1)
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135
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136 static unsigned const counter_mask [32] =
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137 {
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138 RATE( 2,2), RATE(2048,4), RATE(1536,3),
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139 RATE(1280,5), RATE(1024,4), RATE( 768,3),
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140 RATE( 640,5), RATE( 512,4), RATE( 384,3),
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141 RATE( 320,5), RATE( 256,4), RATE( 192,3),
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142 RATE( 160,5), RATE( 128,4), RATE( 96,3),
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143 RATE( 80,5), RATE( 64,4), RATE( 48,3),
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144 RATE( 40,5), RATE( 32,4), RATE( 24,3),
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145 RATE( 20,5), RATE( 16,4), RATE( 12,3),
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146 RATE( 10,5), RATE( 8,4), RATE( 6,3),
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147 RATE( 5,5), RATE( 4,4), RATE( 3,3),
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148 RATE( 2,4),
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149 RATE( 1,4)
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150 };
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151 #undef RATE
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152
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153 inline void Spc_Dsp::init_counter()
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154 {
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155 // counters start out with this synchronization
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156 m.counters [0] = 1;
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157 m.counters [1] = 0;
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158 m.counters [2] = -0x20u;
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159 m.counters [3] = 0x0B;
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160
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161 int n = 2;
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162 for ( int i = 1; i < 32; i++ )
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163 {
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164 m.counter_select [i] = &m.counters [n];
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165 if ( !--n )
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166 n = 3;
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167 }
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168 m.counter_select [ 0] = &m.counters [0];
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169 m.counter_select [30] = &m.counters [2];
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170 }
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171
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172 inline void Spc_Dsp::run_counter( int i )
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173 {
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174 int n = m.counters [i];
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175 if ( !(n-- & 7) )
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176 n -= 6 - i;
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177 m.counters [i] = n;
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178 }
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179
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180 #define READ_COUNTER( rate )\
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181 (*m.counter_select [rate] & counter_mask [rate])
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182
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183
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184 //// Emulation
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185
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186 void Spc_Dsp::run( int clock_count )
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187 {
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188 int new_phase = m.phase + clock_count;
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189 int count = new_phase >> 5;
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190 m.phase = new_phase & 31;
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191 if ( !count )
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192 return;
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193
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194 uint8_t* const ram = m.ram;
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195 uint8_t const* const dir = &ram [REG(dir) * 0x100];
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196 int const slow_gaussian = (REG(pmon) >> 1) | REG(non);
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197 int const noise_rate = REG(flg) & 0x1F;
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198
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199 // Global volume
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200 int mvoll = (int8_t) REG(mvoll);
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201 int mvolr = (int8_t) REG(mvolr);
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202 if ( mvoll * mvolr < m.surround_threshold )
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203 mvoll = -mvoll; // eliminate surround
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204
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205 do
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206 {
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207 // KON/KOFF reading
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208 if ( (m.every_other_sample ^= 1) != 0 )
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209 {
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210 m.new_kon &= ~m.kon;
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211 m.kon = m.new_kon;
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212 m.t_koff = REG(koff);
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213 }
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214
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215 run_counter( 1 );
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216 run_counter( 2 );
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217 run_counter( 3 );
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218
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219 // Noise
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220 if ( !READ_COUNTER( noise_rate ) )
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221 {
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222 int feedback = (m.noise << 13) ^ (m.noise << 14);
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223 m.noise = (feedback & 0x4000) ^ (m.noise >> 1);
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224 }
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225
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226 // Voices
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227 int pmon_input = 0;
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228 int main_out_l = 0;
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229 int main_out_r = 0;
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230 int echo_out_l = 0;
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231 int echo_out_r = 0;
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232 voice_t* v = m.voices;
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233 uint8_t* v_regs = m.regs;
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234 int vbit = 1;
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235 do
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236 {
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237 #define SAMPLE_PTR(i) GET_LE16A( &dir [VREG(v_regs,srcn) * 4 + i * 2] )
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238
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239 int brr_header = ram [v->brr_addr];
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240 int kon_delay = v->kon_delay;
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241
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242 // Pitch
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243 int pitch = GET_LE16A( &VREG(v_regs,pitchl) ) & 0x3FFF;
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244 if ( REG(pmon) & vbit )
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245 pitch += ((pmon_input >> 5) * pitch) >> 10;
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246
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247 // KON phases
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248 if ( --kon_delay >= 0 )
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249 {
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250 v->kon_delay = kon_delay;
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251
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252 // Get ready to start BRR decoding on next sample
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253 if ( kon_delay == 4 )
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254 {
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255 v->brr_addr = SAMPLE_PTR( 0 );
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256 v->brr_offset = 1;
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257 v->buf_pos = v->buf;
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258 brr_header = 0; // header is ignored on this sample
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259 }
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260
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261 // Envelope is never run during KON
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262 v->env = 0;
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263 v->hidden_env = 0;
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264
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265 // Disable BRR decoding until last three samples
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266 v->interp_pos = (kon_delay & 3 ? 0x4000 : 0);
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267
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268 // Pitch is never added during KON
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269 pitch = 0;
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270 }
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271
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272 int env = v->env;
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273
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274 // Gaussian interpolation
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275 {
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276 int output = 0;
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277 VREG(v_regs,envx) = (uint8_t) (env >> 4);
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278 if ( env )
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279 {
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diff changeset
280 // Make pointers into gaussian based on fractional position between samples
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
281 int offset = (unsigned) v->interp_pos >> 3 & 0x1FE;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
282 short const* fwd = interleved_gauss + offset;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
283 short const* rev = interleved_gauss + 510 - offset; // mirror left half of gaussian
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
284
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
285 int const* in = &v->buf_pos [(unsigned) v->interp_pos >> 12];
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
286
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
287 if ( !(slow_gaussian & vbit) ) // 99%
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
288 {
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
289 // Faster approximation when exact sample value isn't necessary for pitch mod
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
290 output = (fwd [0] * in [0] +
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
291 fwd [1] * in [1] +
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
292 rev [1] * in [2] +
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
293 rev [0] * in [3]) >> 11;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
294 output = (output * env) >> 11;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
295 }
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
296 else
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
297 {
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
298 output = (int16_t) (m.noise * 2);
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
299 if ( !(REG(non) & vbit) )
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
300 {
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
301 output = (fwd [0] * in [0]) >> 11;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
302 output += (fwd [1] * in [1]) >> 11;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
303 output += (rev [1] * in [2]) >> 11;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
304 output = (int16_t) output;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
305 output += (rev [0] * in [3]) >> 11;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
306
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
307 CLAMP16( output );
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
308 output &= ~1;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
309 }
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
310 output = (output * env) >> 11 & ~1;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
311 }
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
312
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
313 // Output
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
314 int l = output * v->volume [0];
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
315 int r = output * v->volume [1];
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
316
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
317 main_out_l += l;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
318 main_out_r += r;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
319
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
320 if ( REG(eon) & vbit )
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
321 {
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
322 echo_out_l += l;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
323 echo_out_r += r;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
324 }
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
325 }
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
326
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
327 pmon_input = output;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
328 VREG(v_regs,outx) = (uint8_t) (output >> 8);
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
329 }
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
330
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
331 // Soft reset or end of sample
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
332 if ( REG(flg) & 0x80 || (brr_header & 3) == 1 )
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
333 {
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
334 v->env_mode = env_release;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
335 env = 0;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
336 }
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
337
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
338 if ( m.every_other_sample )
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
339 {
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
340 // KOFF
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
341 if ( m.t_koff & vbit )
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
342 v->env_mode = env_release;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
343
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
344 // KON
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
345 if ( m.kon & vbit )
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
346 {
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
347 v->kon_delay = 5;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
348 v->env_mode = env_attack;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
349 REG(endx) &= ~vbit;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
350 }
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
351 }
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
352
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
353 // Envelope
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
354 if ( !v->kon_delay )
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
355 {
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
356 if ( v->env_mode == env_release ) // 97%
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
357 {
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
358 env -= 0x8;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
359 v->env = env;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
360 if ( env <= 0 )
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
361 {
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
362 v->env = 0;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
363 goto skip_brr; // no BRR decoding for you!
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
364 }
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
365 }
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
366 else // 3%
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
367 {
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
368 int rate;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
369 int const adsr0 = VREG(v_regs,adsr0);
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
370 int env_data = VREG(v_regs,adsr1);
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
371 if ( adsr0 >= 0x80 ) // 97% ADSR
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
372 {
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
373 if ( v->env_mode > env_decay ) // 89%
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
374 {
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
375 env--;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
376 env -= env >> 8;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
377 rate = env_data & 0x1F;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
378
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
379 // optimized handling
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
380 v->hidden_env = env;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
381 if ( READ_COUNTER( rate ) )
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
382 goto exit_env;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
383 v->env = env;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
384 goto exit_env;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
385 }
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
386 else if ( v->env_mode == env_decay )
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
387 {
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
388 env--;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
389 env -= env >> 8;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
390 rate = (adsr0 >> 3 & 0x0E) + 0x10;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
391 }
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
392 else // env_attack
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
393 {
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
394 rate = (adsr0 & 0x0F) * 2 + 1;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
395 env += rate < 31 ? 0x20 : 0x400;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
396 }
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
397 }
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
398 else // GAIN
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
399 {
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
400 int mode;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
401 env_data = VREG(v_regs,gain);
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
402 mode = env_data >> 5;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
403 if ( mode < 4 ) // direct
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
404 {
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
405 env = env_data * 0x10;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
406 rate = 31;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
407 }
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
408 else
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
409 {
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
410 rate = env_data & 0x1F;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
411 if ( mode == 4 ) // 4: linear decrease
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
412 {
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
413 env -= 0x20;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
414 }
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
415 else if ( mode < 6 ) // 5: exponential decrease
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
416 {
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
417 env--;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
418 env -= env >> 8;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
419 }
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
420 else // 6,7: linear increase
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
421 {
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
422 env += 0x20;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
423 if ( mode > 6 && (unsigned) v->hidden_env >= 0x600 )
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
424 env += 0x8 - 0x20; // 7: two-slope linear increase
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
425 }
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
426 }
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
427 }
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
428
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
429 // Sustain level
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
430 if ( (env >> 8) == (env_data >> 5) && v->env_mode == env_decay )
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
431 v->env_mode = env_sustain;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
432
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
433 v->hidden_env = env;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
434
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
435 // unsigned cast because linear decrease going negative also triggers this
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
436 if ( (unsigned) env > 0x7FF )
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
437 {
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
438 env = (env < 0 ? 0 : 0x7FF);
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
439 if ( v->env_mode == env_attack )
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
440 v->env_mode = env_decay;
c31e94fefd2a [svn] - upstream updates regarding handling of SPC700 instructions and runtime
nenolod
parents: 341
diff changeset
441 }
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442
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443 if ( !READ_COUNTER( rate ) )
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444 v->env = env; // nothing else is controlled by the counter
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445 }
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446 }
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447 exit_env:
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448
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449 {
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450 // Apply pitch
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diff changeset
451 int old_pos = v->interp_pos;
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452 int interp_pos = (old_pos & 0x3FFF) + pitch;
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453 if ( interp_pos > 0x7FFF )
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diff changeset
454 interp_pos = 0x7FFF;
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diff changeset
455 v->interp_pos = interp_pos;
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diff changeset
456
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diff changeset
457 // BRR decode if necessary
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458 if ( old_pos >= 0x4000 )
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459 {
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diff changeset
460 // Arrange the four input nybbles in 0xABCD order for easy decoding
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461 int nybbles = ram [(v->brr_addr + v->brr_offset) & 0xFFFF] * 0x100 +
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462 ram [(v->brr_addr + v->brr_offset + 1) & 0xFFFF];
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463
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diff changeset
464 // Advance read position
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diff changeset
465 int const brr_block_size = 9;
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466 int brr_offset = v->brr_offset;
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467 if ( (brr_offset += 2) >= brr_block_size )
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468 {
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469 // Next BRR block
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470 int brr_addr = (v->brr_addr + brr_block_size) & 0xFFFF;
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471 assert( brr_offset == brr_block_size );
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472 if ( brr_header & 1 )
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473 {
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474 brr_addr = SAMPLE_PTR( 1 );
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475 if ( !v->kon_delay )
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476 REG(endx) |= vbit;
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477 }
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478 v->brr_addr = brr_addr;
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479 brr_offset = 1;
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480 }
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diff changeset
481 v->brr_offset = brr_offset;
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482
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483 // Decode
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484
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485 // 0: >>1 1: <<0 2: <<1 ... 12: <<11 13-15: >>4 <<11
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486 static unsigned char const shifts [16 * 2] = {
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487 13,12,12,12,12,12,12,12,12,12,12, 12, 12, 16, 16, 16,
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diff changeset
488 0, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 11, 11, 11
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489 };
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490 int const scale = brr_header >> 4;
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491 int const right_shift = shifts [scale];
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diff changeset
492 int const left_shift = shifts [scale + 16];
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493
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diff changeset
494 // Write to next four samples in circular buffer
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495 int* pos = v->buf_pos;
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496 int* end;
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497
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diff changeset
498 // Decode four samples
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diff changeset
499 for ( end = pos + 4; pos < end; pos++, nybbles <<= 4 )
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500 {
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501 // Extract upper nybble and scale appropriately
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diff changeset
502 int s = ((int16_t) nybbles >> right_shift) << left_shift;
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diff changeset
503
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diff changeset
504 // Apply IIR filter (8 is the most commonly used)
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diff changeset
505 int const filter = brr_header & 0x0C;
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506 int const p1 = pos [brr_buf_size - 1];
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507 int const p2 = pos [brr_buf_size - 2] >> 1;
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508 if ( filter >= 8 )
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509 {
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510 s += p1;
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diff changeset
511 s -= p2;
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512 if ( filter == 8 ) // s += p1 * 0.953125 - p2 * 0.46875
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513 {
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514 s += p2 >> 4;
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515 s += (p1 * -3) >> 6;
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516 }
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517 else // s += p1 * 0.8984375 - p2 * 0.40625
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518 {
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519 s += (p1 * -13) >> 7;
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520 s += (p2 * 3) >> 4;
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521 }
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522 }
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523 else if ( filter ) // s += p1 * 0.46875
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524 {
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525 s += p1 >> 1;
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526 s += (-p1) >> 5;
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527 }
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diff changeset
528
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diff changeset
529 // Adjust and write sample
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530 CLAMP16( s );
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531 s = (int16_t) (s * 2);
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532 pos [brr_buf_size] = pos [0] = s; // second copy simplifies wrap-around
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533 }
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diff changeset
534
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535 if ( pos >= &v->buf [brr_buf_size] )
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diff changeset
536 pos = v->buf;
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diff changeset
537 v->buf_pos = pos;
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538 }
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539 }
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diff changeset
540 skip_brr:
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diff changeset
541 // Next voice
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542 vbit <<= 1;
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diff changeset
543 v_regs += 0x10;
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544 v++;
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545 }
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546 while ( vbit < 0x100 );
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547
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diff changeset
548 // Echo position
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549 int echo_offset = m.echo_offset;
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550 uint8_t* const echo_ptr = &ram [(REG(esa) * 0x100 + echo_offset) & 0xFFFF];
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diff changeset
551 if ( !echo_offset )
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diff changeset
552 m.echo_length = (REG(edl) & 0x0F) * 0x800;
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diff changeset
553 echo_offset += 4;
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554 if ( echo_offset >= m.echo_length )
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diff changeset
555 echo_offset = 0;
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556 m.echo_offset = echo_offset;
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diff changeset
557
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diff changeset
558 // FIR
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diff changeset
559 int echo_in_l = GET_LE16SA( echo_ptr + 0 );
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diff changeset
560 int echo_in_r = GET_LE16SA( echo_ptr + 2 );
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diff changeset
561
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diff changeset
562 int (*echo_hist_pos) [2] = m.echo_hist_pos;
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563 if ( ++echo_hist_pos >= &m.echo_hist [echo_hist_size] )
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diff changeset
564 echo_hist_pos = m.echo_hist;
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diff changeset
565 m.echo_hist_pos = echo_hist_pos;
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diff changeset
566
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diff changeset
567 echo_hist_pos [0] [0] = echo_hist_pos [8] [0] = echo_in_l;
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diff changeset
568 echo_hist_pos [0] [1] = echo_hist_pos [8] [1] = echo_in_r;
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diff changeset
569
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diff changeset
570 #define CALC_FIR_( i, in ) ((in) * (int8_t) REG(fir + i * 0x10))
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571 echo_in_l = CALC_FIR_( 7, echo_in_l );
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572 echo_in_r = CALC_FIR_( 7, echo_in_r );
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573
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diff changeset
574 #define CALC_FIR( i, ch ) CALC_FIR_( i, echo_hist_pos [i + 1] [ch] )
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diff changeset
575 #define DO_FIR( i )\
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576 echo_in_l += CALC_FIR( i, 0 );\
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diff changeset
577 echo_in_r += CALC_FIR( i, 1 );
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diff changeset
578 DO_FIR( 0 );
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diff changeset
579 DO_FIR( 1 );
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diff changeset
580 DO_FIR( 2 );
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diff changeset
581 #if defined (__MWERKS__) && __MWERKS__ < 0x3200
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diff changeset
582 __eieio(); // keeps compiler from stupidly "caching" things in memory
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583 #endif
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diff changeset
584 DO_FIR( 3 );
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diff changeset
585 DO_FIR( 4 );
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diff changeset
586 DO_FIR( 5 );
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587 DO_FIR( 6 );
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diff changeset
588
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diff changeset
589 // Echo out
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diff changeset
590 if ( !(REG(flg) & 0x20) )
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diff changeset
591 {
1153
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diff changeset
592 int l = (echo_out_l >> 7) + ((echo_in_l * (int8_t) REG(efb)) >> 16);
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593 int r = (echo_out_r >> 7) + ((echo_in_r * (int8_t) REG(efb)) >> 16);
1037
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594
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595 // just to help pass more validation tests
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596 #if SPC_MORE_ACCURACY
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597 l &= ~1;
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598 r &= ~1;
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599 #endif
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600
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601 CLAMP16( l );
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602 CLAMP16( r );
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603
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604 SET_LE16A( echo_ptr + 0, l );
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605 SET_LE16A( echo_ptr + 2, r );
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606 }
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607
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608 // Sound out
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609 int l = (((main_out_l * mvoll + echo_in_l * (int8_t) REG(evoll)) >> 14) * m.gain) >> 8;
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610 int r = (((main_out_r * mvolr + echo_in_r * (int8_t) REG(evolr)) >> 14) * m.gain) >> 8;
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611
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612 CLAMP16( l );
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613 CLAMP16( r );
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614
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615 if ( (REG(flg) & 0x40) )
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616 {
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617 l = 0;
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618 r = 0;
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619 }
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620
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621 sample_t* out = m.out;
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622 WRITE_SAMPLES( l, r, out );
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623 m.out = out;
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624 }
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625 while ( --count );
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626 }
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627
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628
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629 //// Setup
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630
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631 void Spc_Dsp::mute_voices( int mask )
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632 {
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633 m.mute_mask = mask;
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634 for ( int i = 0; i < voice_count; i++ )
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635 {
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636 m.voices [i].enabled = (mask >> i & 1) - 1;
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637 update_voice_vol( i * 0x10 );
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638 }
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639 }
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640
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641 void Spc_Dsp::init( void* ram_64k )
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642 {
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643 m.ram = (uint8_t*) ram_64k;
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644 set_gain( gain_unit );
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645 mute_voices( 0 );
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646 disable_surround( false );
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647 set_output( 0, 0 );
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648 reset();
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649
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650 #ifndef NDEBUG
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651 // be sure this sign-extends
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652 assert( (int16_t) 0x8000 == -0x8000 );
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653
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654 // be sure right shift preserves sign
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655 assert( (-1 >> 1) == -1 );
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656
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657 // check clamp macro
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658 int i;
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659 i = +0x8000; CLAMP16( i ); assert( i == +0x7FFF );
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660 i = -0x8001; CLAMP16( i ); assert( i == -0x8000 );
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661
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662 blargg_verify_byte_order();
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663 #endif
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664 }
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665
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666 void Spc_Dsp::soft_reset_common()
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667 {
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668 require( m.ram ); // init() must have been called already
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669
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670 m.noise = 0x4000;
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671 m.echo_hist_pos = m.echo_hist;
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672 m.every_other_sample = 1;
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673 m.echo_offset = 0;
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674 m.phase = 0;
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675
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676 init_counter();
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677 }
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678
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679 void Spc_Dsp::soft_reset()
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680 {
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681 REG(flg) = 0xE0;
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682 soft_reset_common();
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683 }
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684
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685 void Spc_Dsp::load( uint8_t const regs [register_count] )
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686 {
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687 memcpy( m.regs, regs, sizeof m.regs );
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688 memset( &m.regs [register_count], 0, offsetof (state_t,ram) - register_count );
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689
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690 // Internal state
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691 int i;
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692 for ( i = voice_count; --i >= 0; )
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693 {
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694 voice_t& v = m.voices [i];
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695 v.brr_offset = 1;
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696 v.buf_pos = v.buf;
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697 }
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698 m.new_kon = REG(kon);
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699
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700 mute_voices( m.mute_mask );
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701 soft_reset_common();
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702 }
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703
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704 void Spc_Dsp::reset() { load( initial_regs ); }