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1 ;; verilog-mode.el --- major mode for editing verilog source in Emacs
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2 ;;
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3
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4 ;; Copyright (C) 1996-2007 Free Software Foundation, Inc.
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5
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6 ;; Author: Michael McNamara (mac@verilog.com)
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7 ;; http://www.verilog.com
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8 ;;
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9 ;; AUTO features, signal, modsig; by: Wilson Snyder
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10 ;; (wsnyder@wsnyder.org)
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11 ;; http://www.veripool.com
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12 ;; Keywords: languages
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13
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14 ;; This program is free software; you can redistribute it and/or modify
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15 ;; it under the terms of the GNU General Public License as published by
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16 ;; the Free Software Foundation; either version 2 of the License, or
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17 ;; (at your option) any later version.
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18
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19 ;; This program is distributed in the hope that it will be useful,
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20 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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21 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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22 ;; GNU General Public License for more details.
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23
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24 ;; You should have received a copy of the GNU General Public License
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25 ;; along with this program; if not, write to the Free Software
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26 ;; Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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27
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28 ;;; Commentary:
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29
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30 ;; This mode borrows heavily from the Pascal-mode and the cc-mode of emacs
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31
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32 ;; USAGE
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33 ;; =====
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34
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35 ;; A major mode for editing Verilog HDL source code. When you have
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36 ;; entered Verilog mode, you may get more info by pressing C-h m. You
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37 ;; may also get online help describing various functions by: C-h f
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38 ;; <Name of function you want described>
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39
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40 ;; KNOWN BUGS / BUG REPORTS
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41 ;; =======================
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42
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43 ;; Verilog is a rapidly evolving language, and hence this mode is
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44 ;; under continuous development. Hence this is beta code, and likely
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45 ;; has bugs. Please report any and all bugs to me at mac@verilog.com.
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46 ;; Please use verilog-submit-bug-report to submit a report; type C-c
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47 ;; C-b to invoke this and as a result I will have a much easier time
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48 ;; of reproducing the bug you find, and hence fixing it.
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49
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50 ;; INSTALLING THE MODE
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51 ;; ===================
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52
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53 ;; An older version of this mode may be already installed as a part of
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54 ;; your environment, and one method of updating would be to update
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55 ;; your emacs environment. Sometimes this is difficult for local
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56 ;; political/control reasons, and hence you can always install a
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57 ;; private copy (or even a shared copy) which overrides the system
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58 ;; default.
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59
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60 ;; You can get step by step help in installing this file by going to
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61 ;; <http://www.verilog.com/emacs_install.html>
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62
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63 ;; The short list of installation instructions are: To set up
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64 ;; automatic verilog mode, put this file in your load path, and put
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65 ;; the following in code (please un comment it first!) in your
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66 ;; .emacs, or in your site's site-load.el
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67
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68 ; (autoload 'verilog-mode "verilog-mode" "Verilog mode" t )
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69 ; (setq auto-mode-alist (cons '("\\.v\\'" . verilog-mode) auto-mode-alist))
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70 ; (setq auto-mode-alist (cons '("\\.dv\\'" . verilog-mode) auto-mode-alist))
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71
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72 ;; If you want to customize Verilog mode to fit your needs better,
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73 ;; you may add these lines (the values of the variables presented
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74 ;; here are the defaults). Note also that if you use an emacs that
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75 ;; supports custom, it's probably better to use the custom menu to
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76 ;; edit these.
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77 ;;
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78 ;; Be sure to examine at the help for verilog-auto, and the other
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79 ;; verilog-auto-* functions for some major coding time savers.
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80 ;;
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81 ; ;; User customization for Verilog mode
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82 ; (setq verilog-indent-level 3
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83 ; verilog-indent-level-module 3
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84 ; verilog-indent-level-declaration 3
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85 ; verilog-indent-level-behavioral 3
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86 ; verilog-indent-level-directive 1
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87 ; verilog-case-indent 2
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88 ; verilog-auto-newline t
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89 ; verilog-auto-indent-on-newline t
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90 ; verilog-tab-always-indent t
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91 ; verilog-auto-endcomments t
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92 ; verilog-minimum-comment-distance 40
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93 ; verilog-indent-begin-after-if t
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94 ; verilog-auto-lineup '(all)
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95 ; verilog-highlight-p1800-keywords nil
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96 ; verilog-linter "my_lint_shell_command"
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97 ; )
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98
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99 ;;
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100
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101 ;;; History:
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102 ;;
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103 ;;
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104 ;;; Code:
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105
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106 ;; This variable will always hold the version number of the mode
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107 (defconst verilog-mode-version "377"
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108 "Version of this verilog mode.")
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109 (defconst verilog-mode-release-date "2007-12-07"
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110 "Version of this verilog mode.")
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111
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112 (defun verilog-version ()
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113 "Inform caller of the version of this file."
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114 (interactive)
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115 (message (concat "Using verilog-mode version " verilog-mode-version) ))
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116
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117 ;; Insure we have certain packages, and deal with it if we don't
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118 (eval-when-compile
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119 (condition-case nil
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120 (require 'imenu)
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121 (error nil))
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122 (condition-case nil
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123 (require 'reporter)
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124 (error nil))
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125 (condition-case nil
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126 (require 'easymenu)
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127 (error nil))
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128 (condition-case nil
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129 (require 'regexp-opt)
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130 (error nil))
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131 (condition-case nil
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132 (load "skeleton") ;; bug in 19.28 through 19.30 skeleton.el, not provided.
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133 (error nil))
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134 (condition-case nil
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135 (require 'vc)
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136 (error nil))
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137 (condition-case nil
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138 (if (fboundp 'when)
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139 nil ;; fab
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140 (defmacro when (cond &rest body)
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141 (list 'if cond (cons 'progn body))))
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142 (error nil))
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143 (condition-case nil
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144 (if (fboundp 'unless)
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145 nil ;; fab
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146 (defmacro unless (cond &rest body)
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147 (cons 'if (cons cond (cons nil body)))))
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148 (error nil))
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149 (condition-case nil
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150 (if (fboundp 'store-match-data)
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151 nil ;; fab
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152 (defmacro store-match-data (&rest args) nil))
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153 (error nil))
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154 (condition-case nil
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155 (if (boundp 'current-menubar)
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156 nil ;; great
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157 (progn
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158 (defmacro set-buffer-menubar (&rest args) nil)
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159 (defmacro add-submenu (&rest args) nil))
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160 )
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161 (error nil))
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162 (condition-case nil
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163 (if (fboundp 'zmacs-activate-region)
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164 nil ;; great
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165 (defmacro zmacs-activate-region (&rest args) nil))
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166 (error nil))
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167 (condition-case nil
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168 (if (fboundp 'char-before)
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169 nil ;; great
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170 (defmacro char-before (&rest body)
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171 (char-after (1- (point)))))
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172 (error nil))
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173 ;; Requires to define variables that would be "free" warnings
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174 (condition-case nil
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175 (require 'font-lock)
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176 (error nil))
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177 (condition-case nil
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178 (require 'compile)
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179 (error nil))
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180 (condition-case nil
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181 (require 'custom)
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182 (error nil))
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183 (condition-case nil
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184 (require 'dinotrace)
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185 (error nil))
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186 (condition-case nil
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187 (if (fboundp 'dinotrace-unannotate-all)
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188 nil ;; great
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189 (defun dinotrace-unannotate-all (&rest args) nil))
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190 (error nil))
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191 (condition-case nil
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192 (if (fboundp 'customize-apropos)
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193 nil ;; great
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194 (defun customize-apropos (&rest args) nil))
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195 (error nil))
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196 (condition-case nil
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197 (if (fboundp 'match-string-no-properties)
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198 nil ;; great
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199 (defsubst match-string-no-properties (num &optional string)
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200 "Return string of text matched by last search, without text properties.
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201 NUM specifies which parenthesized expression in the last regexp.
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202 Value is nil if NUMth pair didn't match, or there were less than NUM pairs.
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203 Zero means the entire text matched by the whole regexp or whole string.
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204 STRING should be given if the last search was by `string-match' on STRING."
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205 (if (match-beginning num)
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206 (if string
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207 (let ((result
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208 (substring string (match-beginning num) (match-end num))))
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209 (set-text-properties 0 (length result) nil result)
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210 result)
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211 (buffer-substring-no-properties (match-beginning num)
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212 (match-end num)
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213 (current-buffer)
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214 )))))
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215 (error nil))
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216 (if (and (featurep 'custom) (fboundp 'custom-declare-variable))
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217 nil ;; We've got what we needed
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218 ;; We have the old custom-library, hack around it!
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219 (defmacro defgroup (&rest args) nil)
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220 (defmacro customize (&rest args)
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221 (message "Sorry, Customize is not available with this version of emacs"))
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222 (defmacro defcustom (var value doc &rest args)
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223 `(defvar ,var ,value ,doc))
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224 )
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225 (if (fboundp 'defface)
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226 nil ; great!
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227 (defmacro defface (var values doc &rest args)
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228 `(make-face ,var))
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229 )
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230
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231 (if (and (featurep 'custom) (fboundp 'customize-group))
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232 nil ;; We've got what we needed
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233 ;; We have an intermediate custom-library, hack around it!
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234 (defmacro customize-group (var &rest args)
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235 `(customize ,var))
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236 )
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237
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238 )
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239 ;; Provide a regular expression optimization routine, using regexp-opt
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240 ;; if provided by the user's elisp libraries
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241 (eval-and-compile
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242 (if (fboundp 'regexp-opt)
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243 ;; regexp-opt is defined, does it take 3 or 2 arguments?
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244 (if (fboundp 'function-max-args)
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245 (let ((args (function-max-args `regexp-opt)))
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246 (cond
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247 ((eq args 3) ;; It takes 3
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248 (condition-case nil ; Hide this defun from emacses
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249 ;with just a two input regexp
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250 (defun verilog-regexp-opt (a b)
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251 "Deal with differing number of required arguments for `regexp-opt'.
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252 Call 'regexp-opt' on A and B."
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253 (regexp-opt a b 't)
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254 )
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255 (error nil))
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256 )
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257 ((eq args 2) ;; It takes 2
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258 (defun verilog-regexp-opt (a b)
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259 "Call 'regexp-opt' on A and B."
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260 (regexp-opt a b))
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261 )
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262 (t nil)))
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263 ;; We can't tell; assume it takes 2
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264 (defun verilog-regexp-opt (a b)
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265 "Call 'regexp-opt' on A and B."
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266 (regexp-opt a b))
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267 )
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268 ;; There is no regexp-opt, provide our own
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269 (defun verilog-regexp-opt (strings &optional paren shy)
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270 (let ((open (if paren "\\(" "")) (close (if paren "\\)" "")))
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271 (concat open (mapconcat 'regexp-quote strings "\\|") close)))
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272 ))
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273
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274 (defun verilog-regexp-words (a)
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275 "Call 'regexp-opt' with word delimiters for the words A."
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276 (concat "\\<" (verilog-regexp-opt a t) "\\>"))
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277
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278 (defun verilog-customize ()
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279 "Link to customize screen for Verilog."
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280 (interactive)
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281 (customize-group 'verilog-mode))
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282
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283 (defun verilog-font-customize ()
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284 "Link to customize fonts used for Verilog."
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285 (interactive)
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286 (customize-apropos "font-lock-*" 'faces))
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287
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288 (defgroup verilog-mode nil
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289 "Facilitates easy editing of Verilog source text"
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290 :group 'languages)
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291
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292 ; (defgroup verilog-mode-fonts nil
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293 ; "Facilitates easy customization fonts used in Verilog source text"
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294 ; :link '(customize-apropos "font-lock-*" 'faces)
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295 ; :group 'verilog-mode)
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296
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297 (defgroup verilog-mode-indent nil
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298 "Customize indentation and highlighting of verilog source text"
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299 :group 'verilog-mode)
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300
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301 (defgroup verilog-mode-actions nil
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302 "Customize actions on verilog source text"
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303 :group 'verilog-mode)
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304
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305 (defgroup verilog-mode-auto nil
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306 "Customize AUTO actions when expanding verilog source text"
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307 :group 'verilog-mode)
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308
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309 (defcustom verilog-linter
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310 "echo 'No verilog-linter set, see \"M-x describe-variable verilog-linter\"'"
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311 "*Unix program and arguments to call to run a lint checker on verilog source.
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312 Depending on the `verilog-set-compile-command', this may be invoked when
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313 you type \\[compile]. When the compile completes, \\[next-error] will take
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314 you to the next lint error."
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315 :type 'string
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316 :group 'verilog-mode-actions)
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317
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318 (defcustom verilog-coverage
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319 "echo 'No verilog-coverage set, see \"M-x describe-variable verilog-coverage\"'"
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320 "*Program and arguments to use to annotate for coverage verilog source.
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321 Depending on the `verilog-set-compile-command', this may be invoked when
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322 you type \\[compile]. When the compile completes, \\[next-error] will take
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323 you to the next lint error."
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324 :type 'string
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325 :group 'verilog-mode-actions)
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326
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327 (defcustom verilog-simulator
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328 "echo 'No verilog-simulator set, see \"M-x describe-variable verilog-simulator\"'"
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329 "*Program and arguments to use to interpret verilog source.
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330 Depending on the `verilog-set-compile-command', this may be invoked when
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331 you type \\[compile]. When the compile completes, \\[next-error] will take
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332 you to the next lint error."
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333 :type 'string
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334 :group 'verilog-mode-actions)
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335
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336 (defcustom verilog-compiler
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337 "echo 'No verilog-compiler set, see \"M-x describe-variable verilog-compiler\"'"
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338 "*Program and arguments to use to compile verilog source.
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339 Depending on the `verilog-set-compile-command', this may be invoked when
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340 you type \\[compile]. When the compile completes, \\[next-error] will take
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341 you to the next lint error."
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342 :type 'string
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343 :group 'verilog-mode-actions)
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344
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345 (defvar verilog-tool 'verilog-linter
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346 "Which tool to use for building compiler-command.
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347 Either nil, `verilog-linter, `verilog-coverage, `verilog-simulator, or
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348 `verilog-compiler. Alternatively use the \"Choose Compilation Action\"
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349 menu. See `verilog-set-compile-command' for more information.")
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350
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351 (defcustom verilog-highlight-translate-off nil
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352 "*Non-nil means background-highlight code excluded from translation.
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353 That is, all code between \"// synopsys translate_off\" and
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354 \"// synopsys translate_on\" is highlighted using a different background color
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355 \(face `verilog-font-lock-translate-off-face').
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356
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357 Note: This will slow down on-the-fly fontification (and thus editing).
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358
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359 Note: Activate the new setting in a Verilog buffer by re-fontifying it (menu
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360 entry \"Fontify Buffer\"). XEmacs: turn off and on font locking."
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361 :type 'boolean
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362 :group 'verilog-mode-indent)
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363
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364 (defcustom verilog-indent-level 3
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365 "*Indentation of Verilog statements with respect to containing block."
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366 :group 'verilog-mode-indent
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367 :type 'integer)
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368
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369 (defcustom verilog-indent-level-module 3
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370 "*Indentation of Module level Verilog statements. (eg always, initial)
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371 Set to 0 to get initial and always statements lined up on the left side of
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372 your screen."
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373 :group 'verilog-mode-indent
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374 :type 'integer)
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375
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376 (defcustom verilog-indent-level-declaration 3
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377 "*Indentation of declarations with respect to containing block.
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378 Set to 0 to get them list right under containing block."
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379 :group 'verilog-mode-indent
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380 :type 'integer)
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381
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382 (defcustom verilog-indent-declaration-macros nil
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383 "*How to treat macro expansions in a declaration.
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384 If nil, indent as:
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385 input [31:0] a;
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386 input `CP;
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387 output c;
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388 If non nil, treat as:
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389 input [31:0] a;
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390 input `CP ;
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391 output c;"
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392 :group 'verilog-mode-indent
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393 :type 'boolean)
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394
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395 (defcustom verilog-indent-lists t
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396 "*How to treat indenting items in a list.
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397 If t (the default), indent as:
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398 always @( posedge a or
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399 reset ) begin
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400
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401 If nil, treat as:
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402 always @( posedge a or
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403 reset ) begin"
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404 :group 'verilog-mode-indent
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405 :type 'boolean)
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406
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407 (defcustom verilog-indent-level-behavioral 3
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408 "*Absolute indentation of first begin in a task or function block.
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409 Set to 0 to get such code to start at the left side of the screen."
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410 :group 'verilog-mode-indent
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411 :type 'integer)
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412
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413 (defcustom verilog-indent-level-directive 1
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414 "*Indentation to add to each level of `ifdef declarations.
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415 Set to 0 to have all directives start at the left side of the screen."
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416 :group 'verilog-mode-indent
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417 :type 'integer)
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418
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419 (defcustom verilog-cexp-indent 2
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420 "*Indentation of Verilog statements split across lines."
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421 :group 'verilog-mode-indent
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422 :type 'integer)
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423
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424 (defcustom verilog-case-indent 2
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425 "*Indentation for case statements."
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426 :group 'verilog-mode-indent
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427 :type 'integer)
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428
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429 (defcustom verilog-auto-newline t
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430 "*True means automatically newline after semicolons."
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431 :group 'verilog-mode-indent
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432 :type 'boolean)
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433
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434 (defcustom verilog-auto-indent-on-newline t
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435 "*True means automatically indent line after newline."
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436 :group 'verilog-mode-indent
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437 :type 'boolean)
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438
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439 (defcustom verilog-tab-always-indent t
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440 "*True means TAB should always re-indent the current line.
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441 Nil means TAB will only reindent when at the beginning of the line."
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442 :group 'verilog-mode-indent
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443 :type 'boolean)
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444
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445 (defcustom verilog-tab-to-comment nil
|
|
446 "*True means TAB moves to the right hand column in preparation for a comment."
|
|
447 :group 'verilog-mode-actions
|
|
448 :type 'boolean)
|
|
449
|
|
450 (defcustom verilog-indent-begin-after-if t
|
|
451 "*If true, indent begin statements following if, else, while, for and repeat.
|
|
452 Otherwise, line them up."
|
|
453 :group 'verilog-mode-indent
|
|
454 :type 'boolean )
|
|
455
|
|
456
|
|
457 (defcustom verilog-align-ifelse nil
|
|
458 "*If true, align `else' under matching `if'.
|
|
459 Otherwise else is lined up with first character on line holding matching if."
|
|
460 :group 'verilog-mode-indent
|
|
461 :type 'boolean )
|
|
462
|
|
463 (defcustom verilog-minimum-comment-distance 10
|
|
464 "*Minimum distance (in lines) between begin and end required before a comment.
|
|
465 Setting this variable to zero results in every end acquiring a comment; the
|
|
466 default avoids too many redundant comments in tight quarters"
|
|
467 :group 'verilog-mode-indent
|
|
468 :type 'integer)
|
|
469
|
|
470 (defcustom verilog-auto-lineup '(declaration)
|
|
471 "*Algorithm for lining up statements on multiple lines.
|
|
472
|
|
473 If this list contains the symbol 'all', then all line ups described below
|
|
474 are done.
|
|
475
|
|
476 If this list contains the symbol 'declaration', then declarations are lined up
|
|
477 with any preceding declarations, taking into account widths and the like, so
|
|
478 for example the code:
|
|
479 reg [31:0] a;
|
|
480 reg b;
|
|
481 would become
|
|
482 reg [31:0] a;
|
|
483 reg b;
|
|
484
|
|
485 If this list contains the symbol 'assignment', then assignments are lined up
|
|
486 with any preceding assignments, so for example the code
|
|
487 a_long_variable = b + c;
|
|
488 d = e + f;
|
|
489 would become
|
|
490 a_long_variable = b + c;
|
|
491 d = e + f;"
|
|
492
|
|
493 ;; The following is not implemented:
|
|
494 ;If this list contains the symbol 'case', then case items are lined up
|
|
495 ;with any preceding case items, so for example the code
|
|
496 ; case (a) begin
|
|
497 ; a_long_state : a = 3;
|
|
498 ; b: a = 4;
|
|
499 ; endcase
|
|
500 ;would become
|
|
501 ; case (a) begin
|
|
502 ; a_long_state : a = 3;
|
|
503 ; b : a = 4;
|
|
504 ; endcase
|
|
505 ;
|
|
506
|
|
507 :group 'verilog-mode-indent
|
|
508 :type 'list )
|
|
509
|
|
510 (defcustom verilog-highlight-p1800-keywords nil
|
|
511 "*If true highlight words newly reserved by IEEE-1800 in
|
|
512 verilog-font-lock-p1800-face in order to gently suggest changing where
|
|
513 these words are used as variables to something else. Nil means highlight
|
|
514 these words as appropriate for the SystemVerilog IEEE-1800 standard. Note
|
|
515 that changing this will require restarting emacs to see the effect as font
|
|
516 color choices are cached by emacs"
|
|
517 :group 'verilog-mode-indent
|
|
518 :type 'boolean)
|
|
519
|
|
520 (defcustom verilog-auto-endcomments t
|
|
521 "*True means insert a comment /* ... */ after 'end's.
|
|
522 The name of the function or case will be set between the braces."
|
|
523 :group 'verilog-mode-actions
|
|
524 :type 'boolean )
|
|
525
|
|
526 (defcustom verilog-auto-read-includes nil
|
|
527 "*True means to automatically read includes before AUTOs.
|
|
528 This will do a `verilog-read-defines' and `verilog-read-includes' before
|
|
529 each AUTO expansion. This makes it easier to embed defines and includes,
|
|
530 but can result in very slow reading times if there are many or large
|
|
531 include files."
|
|
532 :group 'verilog-mode-actions
|
|
533 :type 'boolean )
|
|
534
|
|
535 (defcustom verilog-auto-save-policy nil
|
|
536 "*Non-nil indicates action to take when saving a Verilog buffer with AUTOs.
|
|
537 A value of `force' will always do a \\[verilog-auto] automatically if
|
|
538 needed on every save. A value of `detect' will do \\[verilog-auto]
|
|
539 automatically when it thinks necessary. A value of `ask' will query the
|
|
540 user when it thinks updating is needed.
|
|
541
|
|
542 You should not rely on the 'ask or 'detect policies, they are safeguards
|
|
543 only. They do not detect when AUTOINSTs need to be updated because a
|
|
544 sub-module's port list has changed."
|
|
545 :group 'verilog-mode-actions
|
|
546 :type '(choice (const nil) (const ask) (const detect) (const force)))
|
|
547
|
|
548 (defcustom verilog-auto-star-expand t
|
|
549 "*Non-nil indicates to expand a SystemVerilog .* instance ports.
|
|
550 They will be expanded in the same way as if there was a AUTOINST in the
|
|
551 instantiation. See also `verilog-auto-star' and `verilog-auto-star-save'."
|
|
552 :group 'verilog-mode-actions
|
|
553 :type 'boolean)
|
|
554
|
|
555 (defcustom verilog-auto-star-save nil
|
|
556 "*Non-nil indicates to save to disk SystemVerilog .* instance expansions.
|
|
557 Nil indicates direct connections will be removed before saving. Only
|
|
558 meaningful to those created due to `verilog-auto-star-expand' being set.
|
|
559
|
|
560 Instead of setting this, you may want to use /*AUTOINST*/, which will
|
|
561 always be saved."
|
|
562 :group 'verilog-mode-actions
|
|
563 :type 'boolean)
|
|
564
|
|
565 (defvar verilog-auto-update-tick nil
|
|
566 "Modification tick at which autos were last performed.")
|
|
567
|
|
568 (defvar verilog-auto-last-file-locals nil
|
|
569 "Text from file-local-variables during last evaluation.")
|
|
570
|
|
571 (defvar verilog-error-regexp-add-didit nil)
|
|
572 (defvar verilog-error-regexp nil)
|
|
573 (setq verilog-error-regexp-add-didit nil
|
|
574 verilog-error-regexp
|
|
575 '(
|
|
576 ; SureLint
|
|
577 ;; ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 2)
|
|
578 ; Most SureFire tools
|
|
579 ("\\(WARNING\\|ERROR\\|INFO\\)[^:]*: \\([^,]+\\), \\(line \\|\\)\\([0-9]+\\):" 2 4 )
|
|
580 ("\
|
|
581 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
|
|
582 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 2 5)
|
|
583 ; xsim
|
|
584 ; Error! in file /homes/mac/Axis/Xsim/test.v at line 13 [OBJ_NOT_DECLARED]
|
|
585 ("\\(Error\\|Warning\\).*in file (\\([^ \t]+\\) at line *\\([0-9]+\\))" 2 3)
|
|
586 ; vcs
|
|
587 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 3)
|
|
588 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 2)
|
|
589 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 3)
|
|
590 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 2)
|
|
591 ; Verilator
|
|
592 ("%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 4)
|
|
593 ("%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 4)
|
|
594 ; vxl
|
|
595 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 3)
|
|
596 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\([0-9]+\\):.*$" 1 2) ; vxl
|
|
597 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+line[ \t]+\\([0-9]+\\):.*$" 1 2)
|
|
598 ; nc-verilog
|
|
599 (".*\\*[WE],[0-9A-Z]+ (\\([^ \t,]+\\),\\([0-9]+\\)|" 1 2)
|
|
600 ; Leda
|
|
601 ("In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\[\\(Warning\\|Error\\|Failure\\)\\][^\n]*" 1 2)
|
|
602 )
|
|
603 ; "*List of regexps for verilog compilers, like verilint. See compilation-error-regexp-alist for the formatting."
|
|
604 )
|
|
605
|
|
606 (defvar verilog-error-font-lock-keywords
|
|
607 '(
|
|
608 ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 bold t)
|
|
609 ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 2 bold t)
|
|
610
|
|
611 ("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 2 bold t)
|
|
612 ("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 3 bold t)
|
|
613
|
|
614 ("\
|
|
615 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
|
|
616 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 bold t)
|
|
617 ("\
|
|
618 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\
|
|
619 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 bold t)
|
|
620
|
|
621 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 bold t)
|
|
622 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 3 bold t)
|
|
623
|
|
624 ("%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 bold t)
|
|
625 ("%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 4 bold t)
|
|
626
|
|
627 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t)
|
|
628 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t)
|
|
629
|
|
630 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 bold t)
|
|
631 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 3 bold t)
|
|
632
|
|
633 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 bold t)
|
|
634 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 2 bold t)
|
|
635 ; vxl
|
|
636 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 bold t)
|
|
637 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 bold t)
|
|
638
|
|
639 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\([0-9]+\\):.*$" 1 bold t)
|
|
640 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\([0-9]+\\):.*$" 2 bold t)
|
|
641
|
|
642 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+line[ \t]+\\([0-9]+\\):.*$" 1 bold t)
|
|
643 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+line[ \t]+\\([0-9]+\\):.*$" 2 bold t)
|
|
644 ; nc-verilog
|
|
645 (".*[WE],[0-9A-Z]+ (\\([^ \t,]+\\),\\([0-9]+\\)|" 1 bold t)
|
|
646 (".*[WE],[0-9A-Z]+ (\\([^ \t,]+\\),\\([0-9]+\\)|" 2 bold t)
|
|
647 ; Leda
|
|
648 ("In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\[\\(Warning\\|Error\\|Failure\\)\\][^\n]*" 1 bold t)
|
|
649 ("In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\[\\(Warning\\|Error\\|Failure\\)\\][^\n]*" 2 bold t)
|
|
650 )
|
|
651 "*Keywords to also highlight in Verilog *compilation* buffers."
|
|
652 )
|
|
653
|
|
654 (defcustom verilog-library-flags '("")
|
|
655 "*List of standard Verilog arguments to use for /*AUTOINST*/.
|
|
656 These arguments are used to find files for `verilog-auto', and match
|
|
657 the flags accepted by a standard Verilog-XL simulator.
|
|
658
|
|
659 -f filename Reads more `verilog-library-flags' from the filename.
|
|
660 +incdir+dir Adds the directory to `verilog-library-directories'.
|
|
661 -Idir Adds the directory to `verilog-library-directories'.
|
|
662 -y dir Adds the directory to `verilog-library-directories'.
|
|
663 +libext+.v Adds the extensions to `verilog-library-extensions'.
|
|
664 -v filename Adds the filename to `verilog-library-files'.
|
|
665
|
|
666 filename Adds the filename to `verilog-library-files'.
|
|
667 This is not recommended, -v is a better choice.
|
|
668
|
|
669 You might want these defined in each file; put at the *END* of your file
|
|
670 something like:
|
|
671
|
|
672 // Local Variables:
|
|
673 // verilog-library-flags:(\"-y dir -y otherdir\")
|
|
674 // End:
|
|
675
|
|
676 Verilog-mode attempts to detect changes to this local variable, but they
|
|
677 are only insured to be correct when the file is first visited. Thus if you
|
|
678 have problems, use \\[find-alternate-file] RET to have these take effect.
|
|
679
|
|
680 See also the variables mentioned above."
|
|
681 :group 'verilog-mode-auto
|
|
682 :type '(repeat string))
|
|
683
|
|
684 (defcustom verilog-library-directories '(".")
|
|
685 "*List of directories when looking for files for /*AUTOINST*/.
|
|
686 The directory may be relative to the current file, or absolute.
|
|
687 Environment variables are also expanded in the directory names.
|
|
688 Having at least the current directory is a good idea.
|
|
689
|
|
690 You might want these defined in each file; put at the *END* of your file
|
|
691 something like:
|
|
692
|
|
693 // Local Variables:
|
|
694 // verilog-library-directories:(\".\" \"subdir\" \"subdir2\")
|
|
695 // End:
|
|
696
|
|
697 Verilog-mode attempts to detect changes to this local variable, but they
|
|
698 are only insured to be correct when the file is first visited. Thus if you
|
|
699 have problems, use \\[find-alternate-file] RET to have these take effect.
|
|
700
|
|
701 See also `verilog-library-flags', `verilog-library-files'
|
|
702 and `verilog-library-extensions'."
|
|
703 :group 'verilog-mode-auto
|
|
704 :type '(repeat file))
|
|
705
|
|
706 (defcustom verilog-library-files '()
|
|
707 "*List of files to search for modules when looking for AUTOINST files.
|
|
708 This is a complete path, usually to a technology file with many standard
|
|
709 cells defined in it.
|
|
710
|
|
711 You might want these defined in each file; put at the *END* of your file
|
|
712 something like:
|
|
713
|
|
714 // Local Variables:
|
|
715 // verilog-library-files:(\"/some/path/technology.v\" \"/some/path/tech2.v\")
|
|
716 // End:
|
|
717
|
|
718 Verilog-mode attempts to detect changes to this local variable, but they
|
|
719 are only insured to be correct when the file is first visited. Thus if you
|
|
720 have problems, use \\[find-alternate-file] RET to have these take effect.
|
|
721
|
|
722 See also `verilog-library-flags', `verilog-library-directories'."
|
|
723 :group 'verilog-mode-auto
|
|
724 :type '(repeat directory))
|
|
725
|
|
726 (defcustom verilog-library-extensions '(".v")
|
|
727 "*List of extensions to use when looking for files for /*AUTOINST*/.
|
|
728 See also `verilog-library-flags', `verilog-library-directories'."
|
|
729 :type '(repeat string)
|
|
730 :group 'verilog-mode-auto)
|
|
731
|
|
732 (defcustom verilog-active-low-regexp nil
|
|
733 "*If set, treat signals matching this regexp as active low.
|
|
734 This is used for AUTORESET and AUTOTIEOFF. For proper behavior,
|
|
735 you will probably also need `verilog-auto-reset-widths' set."
|
|
736 :group 'verilog-mode-auto
|
|
737 :type 'string)
|
|
738
|
|
739 (defcustom verilog-auto-sense-include-inputs nil
|
|
740 "*If true, AUTOSENSE should include all inputs.
|
|
741 If nil, only inputs that are NOT output signals in the same block are
|
|
742 included."
|
|
743 :type 'boolean
|
|
744 :group 'verilog-mode-auto)
|
|
745
|
|
746 (defcustom verilog-auto-sense-defines-constant nil
|
|
747 "*If true, AUTOSENSE should assume all defines represent constants.
|
|
748 When true, the defines will not be included in sensitivity lists. To
|
|
749 maintain compatibility with other sites, this should be set at the bottom
|
|
750 of each verilog file that requires it, rather than being set globally."
|
|
751 :type 'boolean
|
|
752 :group 'verilog-mode-auto)
|
|
753
|
|
754 (defcustom verilog-auto-reset-widths t
|
|
755 "*If true, AUTORESET should determine the width of signals.
|
|
756 This is then used to set the width of the zero (32'h0 for example). This
|
|
757 is required by some lint tools that aren't smart enough to ignore widths of
|
|
758 the constant zero. This may result in ugly code when parameters determine
|
|
759 the MSB or LSB of a signal inside a AUTORESET."
|
|
760 :type 'boolean
|
|
761 :group 'verilog-mode-auto)
|
|
762
|
|
763 (defcustom verilog-assignment-delay ""
|
|
764 "*Text used for delays in delayed assignments. Add a trailing space if set."
|
|
765 :type 'string
|
|
766 :group 'verilog-mode-auto)
|
|
767
|
|
768 (defcustom verilog-auto-inst-vector t
|
|
769 "*If true, when creating default ports with AUTOINST, use bus subscripts.
|
|
770 If nil, skip the subscript when it matches the entire bus as declared in
|
|
771 the module (AUTOWIRE signals always are subscripted, you must manually
|
|
772 declare the wire to have the subscripts removed.) Nil may speed up some
|
|
773 simulators, but is less general and harder to read, so avoid."
|
|
774 :group 'verilog-mode-auto
|
|
775 :type 'boolean )
|
|
776
|
|
777 (defcustom verilog-auto-inst-template-numbers nil
|
|
778 "*If true, when creating templated ports with AUTOINST, add a comment.
|
|
779 The comment will add the line number of the template that was used for that
|
|
780 port declaration. Setting this aids in debugging, but nil is suggested for
|
|
781 regular use to prevent large numbers of merge conflicts."
|
|
782 :group 'verilog-mode-auto
|
|
783 :type 'boolean )
|
|
784
|
|
785 (defvar verilog-auto-inst-column 40
|
|
786 "Column number for first part of auto-inst.")
|
|
787
|
|
788 (defcustom verilog-auto-input-ignore-regexp nil
|
|
789 "*If set, when creating AUTOINPUT list, ignore signals matching this regexp.
|
|
790 See the \\[verilog-faq] for examples on using this."
|
|
791 :group 'verilog-mode-auto
|
|
792 :type 'string )
|
|
793
|
|
794 (defcustom verilog-auto-inout-ignore-regexp nil
|
|
795 "*If set, when creating AUTOINOUT list, ignore signals matching this regexp.
|
|
796 See the \\[verilog-faq] for examples on using this."
|
|
797 :group 'verilog-mode-auto
|
|
798 :type 'string )
|
|
799
|
|
800 (defcustom verilog-auto-output-ignore-regexp nil
|
|
801 "*If set, when creating AUTOOUTPUT list, ignore signals matching this regexp.
|
|
802 See the \\[verilog-faq] for examples on using this."
|
|
803 :group 'verilog-mode-auto
|
|
804 :type 'string )
|
|
805
|
|
806 (defcustom verilog-auto-unused-ignore-regexp nil
|
|
807 "*If set, when creating AUTOUNUSED list, ignore signals matching this regexp.
|
|
808 See the \\[verilog-faq] for examples on using this."
|
|
809 :group 'verilog-mode-auto
|
|
810 :type 'string )
|
|
811
|
|
812 (defcustom verilog-typedef-regexp nil
|
|
813 "*If non-nil, regular expression that matches Verilog-2001 typedef names.
|
|
814 For example, \"_t$\" matches typedefs named with _t, as in the C language."
|
|
815 :group 'verilog-mode-auto
|
|
816 :type 'string )
|
|
817
|
|
818 (defcustom verilog-mode-hook 'verilog-set-compile-command
|
|
819 "*Hook (List of functions) run after verilog mode is loaded."
|
|
820 :type 'hook
|
|
821 :group 'verilog-mode)
|
|
822
|
|
823 (defcustom verilog-auto-hook nil
|
|
824 "*Hook run after `verilog-mode' updates AUTOs."
|
|
825 :type 'hook
|
|
826 :group 'verilog-mode-auto)
|
|
827
|
|
828 (defcustom verilog-before-auto-hook nil
|
|
829 "*Hook run before `verilog-mode' updates AUTOs."
|
|
830 :type 'hook
|
|
831 :group 'verilog-mode-auto)
|
|
832
|
|
833 (defcustom verilog-delete-auto-hook nil
|
|
834 "*Hook run after `verilog-mode' deletes AUTOs."
|
|
835 :type 'hook
|
|
836 :group 'verilog-mode-auto)
|
|
837
|
|
838 (defcustom verilog-before-delete-auto-hook nil
|
|
839 "*Hook run before `verilog-mode' deletes AUTOs."
|
|
840 :type 'hook
|
|
841 :group 'verilog-mode-auto)
|
|
842
|
|
843 (defcustom verilog-getopt-flags-hook nil
|
|
844 "*Hook run after `verilog-getopt-flags' determines the Verilog option lists."
|
|
845 :type 'hook
|
|
846 :group 'verilog-mode-auto)
|
|
847
|
|
848 (defcustom verilog-before-getopt-flags-hook nil
|
|
849 "*Hook run before `verilog-getopt-flags' determines the Verilog option lists."
|
|
850 :type 'hook
|
|
851 :group 'verilog-mode-auto)
|
|
852
|
|
853 (defvar verilog-imenu-generic-expression
|
|
854 '((nil "^\\s-*\\(\\(m\\(odule\\|acromodule\\)\\)\\|primitive\\)\\s-+\\([a-zA-Z0-9_.:]+\\)" 4)
|
|
855 ("*Vars*" "^\\s-*\\(reg\\|wire\\)\\s-+\\(\\|\\[[^]]+\\]\\s-+\\)\\([A-Za-z0-9_]+\\)" 3))
|
|
856 "Imenu expression for Verilog-mode. See `imenu-generic-expression'.")
|
|
857
|
|
858 ;;
|
|
859 ;; provide a verilog-header function.
|
|
860 ;; Customization variables:
|
|
861 ;;
|
|
862 (defvar verilog-date-scientific-format nil
|
|
863 "*If non-nil, dates are written in scientific format (e.g. 1997/09/17).
|
|
864 If nil, in European format (e.g. 17.09.1997). The brain-dead American
|
|
865 format (e.g. 09/17/1997) is not supported.")
|
|
866
|
|
867 (defvar verilog-company nil
|
|
868 "*Default name of Company for verilog header.
|
|
869 If set will become buffer local.")
|
|
870
|
|
871 (defvar verilog-project nil
|
|
872 "*Default name of Project for verilog header.
|
|
873 If set will become buffer local.")
|
|
874
|
|
875 (defvar verilog-mode-map ()
|
79546
|
876 (let ((map (make-sparse-keymap)))
|
|
877 (define-key map ";" 'electric-verilog-semi)
|
|
878 (define-key map [(control 59)] 'electric-verilog-semi-with-comment)
|
|
879 (define-key map ":" 'electric-verilog-colon)
|
|
880 ;;(define-key map "=" 'electric-verilog-equal)
|
|
881 (define-key map "\`" 'electric-verilog-tick)
|
|
882 (define-key map "\t" 'electric-verilog-tab)
|
|
883 (define-key map "\r" 'electric-verilog-terminate-line)
|
|
884 ;; backspace/delete key bindings
|
|
885 (define-key map [backspace] 'backward-delete-char-untabify)
|
|
886 (unless (boundp 'delete-key-deletes-forward) ; XEmacs variable
|
|
887 (define-key map [delete] 'delete-char)
|
|
888 (define-key map [(meta delete)] 'kill-word))
|
|
889 (define-key map "\M-\C-b" 'electric-verilog-backward-sexp)
|
|
890 (define-key map "\M-\C-f" 'electric-verilog-forward-sexp)
|
|
891 (define-key map "\M-\r" `electric-verilog-terminate-and-indent)
|
|
892 (define-key map "\M-\t" 'verilog-complete-word)
|
|
893 (define-key map "\M-?" 'verilog-show-completions)
|
|
894 (define-key map [(meta control h)] 'verilog-mark-defun)
|
|
895 (define-key map "\C-c\`" 'verilog-lint-off)
|
|
896 (define-key map "\C-c\*" 'verilog-delete-auto-star-implicit)
|
|
897 (define-key map "\C-c\C-r" 'verilog-label-be)
|
|
898 (define-key map "\C-c\C-i" 'verilog-pretty-declarations)
|
|
899 (define-key map "\C-c=" 'verilog-pretty-expr)
|
|
900 (define-key map "\C-c\C-b" 'verilog-submit-bug-report)
|
|
901 (define-key map "\M-*" 'verilog-star-comment)
|
|
902 (define-key map "\C-c\C-c" 'verilog-comment-region)
|
|
903 (define-key map "\C-c\C-u" 'verilog-uncomment-region)
|
|
904 (define-key map "\M-\C-a" 'verilog-beg-of-defun)
|
|
905 (define-key map "\M-\C-e" 'verilog-end-of-defun)
|
|
906 (define-key map "\C-c\C-d" 'verilog-goto-defun)
|
|
907 (define-key map "\C-c\C-k" 'verilog-delete-auto)
|
|
908 (define-key map "\C-c\C-a" 'verilog-auto)
|
|
909 (define-key map "\C-c\C-s" 'verilog-auto-save-compile)
|
|
910 (define-key map "\C-c\C-z" 'verilog-inject-auto)
|
|
911 (define-key map "\C-c\C-e" 'verilog-expand-vector)
|
|
912 (define-key map "\C-c\C-h" 'verilog-header))
|
79545
|
913 "Keymap used in Verilog mode.")
|
|
914
|
|
915 ;; menus
|
|
916 (defvar verilog-xemacs-menu
|
|
917 '("Verilog"
|
|
918 ("Choose Compilation Action"
|
|
919 ["None"
|
|
920 (progn
|
|
921 (setq verilog-tool nil)
|
|
922 (verilog-set-compile-command))
|
|
923 :style radio
|
|
924 :selected (equal verilog-tool nil)]
|
|
925 ["Lint"
|
|
926 (progn
|
|
927 (setq verilog-tool 'verilog-linter)
|
|
928 (verilog-set-compile-command))
|
|
929 :style radio
|
|
930 :selected (equal verilog-tool `verilog-linter)]
|
|
931 ["Coverage"
|
|
932 (progn
|
|
933 (setq verilog-tool 'verilog-coverage)
|
|
934 (verilog-set-compile-command))
|
|
935 :style radio
|
|
936 :selected (equal verilog-tool `verilog-coverage)]
|
|
937 ["Simulator"
|
|
938 (progn
|
|
939 (setq verilog-tool 'verilog-simulator)
|
|
940 (verilog-set-compile-command))
|
|
941 :style radio
|
|
942 :selected (equal verilog-tool `verilog-simulator)]
|
|
943 ["Compiler"
|
|
944 (progn
|
|
945 (setq verilog-tool 'verilog-compiler)
|
|
946 (verilog-set-compile-command))
|
|
947 :style radio
|
|
948 :selected (equal verilog-tool `verilog-compiler)]
|
|
949 )
|
|
950 ("Move"
|
|
951 ["Beginning of function" verilog-beg-of-defun t]
|
|
952 ["End of function" verilog-end-of-defun t]
|
|
953 ["Mark function" verilog-mark-defun t]
|
|
954 ["Goto function/module" verilog-goto-defun t]
|
|
955 ["Move to beginning of block" electric-verilog-backward-sexp t]
|
|
956 ["Move to end of block" electric-verilog-forward-sexp t]
|
|
957 )
|
|
958 ("Comments"
|
|
959 ["Comment Region" verilog-comment-region t]
|
|
960 ["UnComment Region" verilog-uncomment-region t]
|
|
961 ["Multi-line comment insert" verilog-star-comment t]
|
|
962 ["Lint error to comment" verilog-lint-off t]
|
|
963 )
|
|
964 "----"
|
|
965 ["Compile" compile t]
|
|
966 ["AUTO, Save, Compile" verilog-auto-save-compile t]
|
|
967 ["Next Compile Error" next-error t]
|
|
968 ["Ignore Lint Warning at point" verilog-lint-off t]
|
|
969 "----"
|
|
970 ["Line up declarations around point" verilog-pretty-declarations t]
|
|
971 ["Line up equations around point" verilog-pretty-expr t]
|
|
972 ["Redo/insert comments on every end" verilog-label-be t]
|
|
973 ["Expand [x:y] vector line" verilog-expand-vector t]
|
|
974 ["Insert begin-end block" verilog-insert-block t]
|
|
975 ["Complete word" verilog-complete-word t]
|
|
976 "----"
|
|
977 ["Recompute AUTOs" verilog-auto t]
|
|
978 ["Kill AUTOs" verilog-delete-auto t]
|
|
979 ["Inject AUTOs" verilog-inject-auto t]
|
|
980 ("AUTO Help..."
|
|
981 ["AUTO General" (describe-function 'verilog-auto) t]
|
|
982 ["AUTO Library Flags" (describe-variable 'verilog-library-flags) t]
|
|
983 ["AUTO Library Path" (describe-variable 'verilog-library-directories) t]
|
|
984 ["AUTO Library Files" (describe-variable 'verilog-library-files) t]
|
|
985 ["AUTO Library Extensions" (describe-variable 'verilog-library-extensions) t]
|
|
986 ["AUTO `define Reading" (describe-function 'verilog-read-defines) t]
|
|
987 ["AUTO `include Reading" (describe-function 'verilog-read-includes) t]
|
|
988 ["AUTOARG" (describe-function 'verilog-auto-arg) t]
|
|
989 ["AUTOASCIIENUM" (describe-function 'verilog-auto-ascii-enum) t]
|
|
990 ["AUTOINOUTMODULE" (describe-function 'verilog-auto-inout-module) t]
|
|
991 ["AUTOINOUT" (describe-function 'verilog-auto-inout) t]
|
|
992 ["AUTOINPUT" (describe-function 'verilog-auto-input) t]
|
|
993 ["AUTOINST" (describe-function 'verilog-auto-inst) t]
|
|
994 ["AUTOINST (.*)" (describe-function 'verilog-auto-star) t]
|
|
995 ["AUTOINSTPARAM" (describe-function 'verilog-auto-inst-param) t]
|
|
996 ["AUTOOUTPUT" (describe-function 'verilog-auto-output) t]
|
|
997 ["AUTOOUTPUTEVERY" (describe-function 'verilog-auto-output-every) t]
|
|
998 ["AUTOREG" (describe-function 'verilog-auto-reg) t]
|
|
999 ["AUTOREGINPUT" (describe-function 'verilog-auto-reg-input) t]
|
|
1000 ["AUTORESET" (describe-function 'verilog-auto-reset) t]
|
|
1001 ["AUTOSENSE" (describe-function 'verilog-auto-sense) t]
|
|
1002 ["AUTOTIEOFF" (describe-function 'verilog-auto-tieoff) t]
|
|
1003 ["AUTOUNUSED" (describe-function 'verilog-auto-unused) t]
|
|
1004 ["AUTOWIRE" (describe-function 'verilog-auto-wire) t]
|
|
1005 )
|
|
1006 "----"
|
|
1007 ["Submit bug report" verilog-submit-bug-report t]
|
|
1008 ["Version and FAQ" verilog-faq t]
|
|
1009 ["Customize Verilog Mode..." verilog-customize t]
|
|
1010 ["Customize Verilog Fonts & Colors" verilog-font-customize t]
|
|
1011 )
|
|
1012 "Emacs menu for VERILOG mode."
|
|
1013 )
|
|
1014 (defvar verilog-statement-menu
|
|
1015 '("Statements"
|
|
1016 ["Header" verilog-sk-header t]
|
|
1017 ["Comment" verilog-sk-comment t]
|
|
1018 "----"
|
|
1019 ["Module" verilog-sk-module t]
|
|
1020 ["Primitive" verilog-sk-primitive t]
|
|
1021 "----"
|
|
1022 ["Input" verilog-sk-input t]
|
|
1023 ["Output" verilog-sk-output t]
|
|
1024 ["Inout" verilog-sk-inout t]
|
|
1025 ["Wire" verilog-sk-wire t]
|
|
1026 ["Reg" verilog-sk-reg t]
|
|
1027 ["Define thing under point as a register" verilog-sk-define-signal t]
|
|
1028 "----"
|
|
1029 ["Initial" verilog-sk-initial t]
|
|
1030 ["Always" verilog-sk-always t]
|
|
1031 ["Function" verilog-sk-function t]
|
|
1032 ["Task" verilog-sk-task t]
|
|
1033 ["Specify" verilog-sk-specify t]
|
|
1034 ["Generate" verilog-sk-generate t]
|
|
1035 "----"
|
|
1036 ["Begin" verilog-sk-begin t]
|
|
1037 ["If" verilog-sk-if t]
|
|
1038 ["(if) else" verilog-sk-else-if t]
|
|
1039 ["For" verilog-sk-for t]
|
|
1040 ["While" verilog-sk-while t]
|
|
1041 ["Fork" verilog-sk-fork t]
|
|
1042 ["Repeat" verilog-sk-repeat t]
|
|
1043 ["Case" verilog-sk-case t]
|
|
1044 ["Casex" verilog-sk-casex t]
|
|
1045 ["Casez" verilog-sk-casez t]
|
|
1046 )
|
|
1047 "Menu for statement templates in Verilog."
|
|
1048 )
|
|
1049
|
|
1050 (easy-menu-define verilog-menu verilog-mode-map "Menu for Verilog mode"
|
|
1051 verilog-xemacs-menu)
|
|
1052 (easy-menu-define verilog-stmt-menu verilog-mode-map "Menu for statement templates in Verilog."
|
|
1053 verilog-statement-menu)
|
|
1054
|
|
1055 (defvar verilog-mode-abbrev-table nil
|
|
1056 "Abbrev table in use in Verilog-mode buffers.")
|
|
1057
|
|
1058 (define-abbrev-table 'verilog-mode-abbrev-table ())
|
|
1059
|
|
1060 ;; compilation program
|
|
1061 (defun verilog-set-compile-command ()
|
|
1062 "Function to compute shell command to compile verilog.
|
|
1063
|
|
1064 This reads `verilog-tool' and sets `compile-command'. This specifies the
|
|
1065 program that executes when you type \\[compile] or
|
|
1066 \\[verilog-auto-save-compile].
|
|
1067
|
|
1068 By default `verilog-tool' uses a Makefile if one exists in the current
|
|
1069 directory. If not, it is set to the `verilog-linter', `verilog-coverage',
|
|
1070 `verilog-simulator', or `verilog-compiler' variables, as selected with the
|
|
1071 Verilog -> \"Choose Compilation Action\" menu.
|
|
1072
|
|
1073 You should set `verilog-tool' or the other variables to the path and
|
|
1074 arguments for your Verilog simulator. For example:
|
|
1075 \"vcs -p123 -O\"
|
|
1076 or a string like:
|
|
1077 \"(cd /tmp; surecov %s)\".
|
|
1078
|
|
1079 In the former case, the path to the current buffer is concat'ed to the
|
|
1080 value of `verilog-tool'; in the later, the path to the current buffer is
|
|
1081 substituted for the %s.
|
|
1082
|
|
1083 Where __FILE__ appears in the string, the buffer-file-name of the current
|
|
1084 buffer, without the directory portion, will be substituted."
|
|
1085 (interactive)
|
|
1086 (cond
|
|
1087 ((or (file-exists-p "makefile") ;If there is a makefile, use it
|
|
1088 (file-exists-p "Makefile"))
|
|
1089 (make-local-variable 'compile-command)
|
|
1090 (setq compile-command "make "))
|
|
1091 (t
|
|
1092 (make-local-variable 'compile-command)
|
|
1093 (setq compile-command
|
|
1094 (if verilog-tool
|
|
1095 (if (string-match "%s" (eval verilog-tool))
|
|
1096 (format (eval verilog-tool) (or buffer-file-name ""))
|
|
1097 (concat (eval verilog-tool) " " (or buffer-file-name "")))
|
|
1098 ""))))
|
|
1099 (verilog-modify-compile-command))
|
|
1100
|
|
1101 (defun verilog-modify-compile-command ()
|
|
1102 "Replace meta-information in `compile-command'.
|
|
1103 Where __FILE__ appears in the string, the current buffer's file-name,
|
|
1104 without the directory portion, will be substituted."
|
|
1105 (when (and
|
|
1106 (stringp compile-command)
|
|
1107 (string-match "\\b__FILE__\\b" compile-command))
|
|
1108 (make-local-variable 'compile-command)
|
|
1109 (setq compile-command
|
|
1110 (verilog-string-replace-matches
|
|
1111 "\\b__FILE__\\b" (file-name-nondirectory (buffer-file-name))
|
|
1112 t t compile-command))))
|
|
1113
|
|
1114 (defun verilog-error-regexp-add ()
|
|
1115 "Add the messages to the `compilation-error-regexp-alist'.
|
|
1116 Called by `compilation-mode-hook'. This allows \\[next-error] to find the errors."
|
|
1117 (if (not verilog-error-regexp-add-didit)
|
|
1118 (progn
|
|
1119 (setq verilog-error-regexp-add-didit t)
|
|
1120 (setq-default compilation-error-regexp-alist
|
|
1121 (append verilog-error-regexp
|
|
1122 (default-value 'compilation-error-regexp-alist)))
|
|
1123 ;; Could be buffer local at this point; maybe also in let; change all three
|
|
1124 (setq compilation-error-regexp-alist (default-value 'compilation-error-regexp-alist))
|
|
1125 (set (make-local-variable 'compilation-error-regexp-alist)
|
|
1126 (default-value 'compilation-error-regexp-alist))
|
|
1127 )))
|
|
1128
|
|
1129 (add-hook 'compilation-mode-hook 'verilog-error-regexp-add)
|
|
1130
|
|
1131 (defconst verilog-directive-re
|
|
1132 ;; "`case" "`default" "`define" "`define" "`else" "`endfor" "`endif"
|
|
1133 ;; "`endprotect" "`endswitch" "`endwhile" "`for" "`format" "`if" "`ifdef"
|
|
1134 ;; "`ifndef" "`include" "`let" "`protect" "`switch" "`timescale"
|
|
1135 ;; "`time_scale" "`undef" "`while"
|
|
1136 "\\<`\\(case\\|def\\(ault\\|ine\\(\\)?\\)\\|e\\(lse\\|nd\\(for\\|if\\|protect\\|switch\\|while\\)\\)\\|for\\(mat\\)?\\|i\\(f\\(def\\|ndef\\)?\\|nclude\\)\\|let\\|protect\\|switch\\|time\\(_scale\\|scale\\)\\|undef\\|while\\)\\>")
|
|
1137
|
|
1138 (defconst verilog-directive-begin
|
|
1139 "\\<`\\(for\\|i\\(f\\|fdef\\|fndef\\)\\|switch\\|while\\)\\>")
|
|
1140
|
|
1141 (defconst verilog-directive-middle
|
|
1142 "\\<`\\(else\\|default\\|case\\)\\>")
|
|
1143
|
|
1144 (defconst verilog-directive-end
|
|
1145 "`\\(endfor\\|endif\\|endswitch\\|endwhile\\)\\>")
|
|
1146
|
|
1147 (defconst verilog-directive-re-1
|
|
1148 (concat "[ \t]*" verilog-directive-re))
|
|
1149
|
|
1150 ;;
|
|
1151 ;; Regular expressions used to calculate indent, etc.
|
|
1152 ;;
|
|
1153 (defconst verilog-symbol-re "\\<[a-zA-Z_][a-zA-Z_0-9.]*\\>")
|
|
1154 (defconst verilog-case-re "\\(\\<case[xz]?\\>\\|\\<randcase\\>\\)")
|
|
1155 ;; Want to match
|
|
1156 ;; aa :
|
|
1157 ;; aa,bb :
|
|
1158 ;; a[34:32] :
|
|
1159 ;; a,
|
|
1160 ;; b :
|
|
1161
|
|
1162 (defconst verilog-no-indent-begin-re
|
|
1163 "\\<\\(if\\|else\\|while\\|for\\|repeat\\|always\\|always_comb\\|always_ff\\|always_latch\\)\\>")
|
|
1164
|
|
1165 (defconst verilog-ends-re
|
|
1166 ;; Parenthesis indicate type of keyword found
|
|
1167 (concat
|
|
1168 "\\(\\<else\\>\\)\\|" ; 1
|
|
1169 "\\(\\<if\\>\\)\\|" ; 2
|
|
1170 "\\(\\<end\\>\\)\\|" ; 3
|
|
1171 "\\(\\<endcase\\>\\)\\|" ; 4
|
|
1172 "\\(\\<endfunction\\>\\)\\|" ; 5
|
|
1173 "\\(\\<endtask\\>\\)\\|" ; 6
|
|
1174 "\\(\\<endspecify\\>\\)\\|" ; 7
|
|
1175 "\\(\\<endtable\\>\\)\\|" ; 8
|
|
1176 "\\(\\<endgenerate\\>\\)\\|" ; 9
|
|
1177 "\\(\\<join\\(_any\\|_none\\)?\\>\\)\\|" ; 10
|
|
1178 "\\(\\<endclass\\>\\)\\|" ; 11
|
|
1179 "\\(\\<endgroup\\>\\)" ; 12
|
|
1180 ))
|
|
1181
|
|
1182 (defconst verilog-auto-end-comment-lines-re
|
|
1183 ;; Matches to names in this list cause auto-end-commentation
|
|
1184 (concat "\\("
|
|
1185 verilog-directive-re "\\)\\|\\("
|
|
1186 (eval-when-compile
|
|
1187 (verilog-regexp-words
|
|
1188 `( "begin"
|
|
1189 "else"
|
|
1190 "end"
|
|
1191 "endcase"
|
|
1192 "endclass"
|
|
1193 "endclocking"
|
|
1194 "endgroup"
|
|
1195 "endfunction"
|
|
1196 "endmodule"
|
|
1197 "endprogram"
|
|
1198 "endprimitive"
|
|
1199 "endinterface"
|
|
1200 "endpackage"
|
|
1201 "endsequence"
|
|
1202 "endspecify"
|
|
1203 "endtable"
|
|
1204 "endtask"
|
|
1205 "join"
|
|
1206 "join_any"
|
|
1207 "join_none"
|
|
1208 "module"
|
|
1209 "macromodule"
|
|
1210 "primitive"
|
|
1211 "interface"
|
|
1212 "package")))
|
|
1213 "\\)"))
|
|
1214
|
|
1215 ;;; NOTE: verilog-leap-to-head expects that verilog-end-block-re and
|
|
1216 ;;; verilog-end-block-ordered-re matches exactly the same strings.
|
|
1217 (defconst verilog-end-block-ordered-re
|
|
1218 ;; Parenthesis indicate type of keyword found
|
|
1219 (concat "\\(\\<endcase\\>\\)\\|" ; 1
|
|
1220 "\\(\\<end\\>\\)\\|" ; 2
|
|
1221 "\\(\\<end" ; 3, but not used
|
|
1222 "\\(" ; 4, but not used
|
|
1223 "\\(function\\)\\|" ; 5
|
|
1224 "\\(task\\)\\|" ; 6
|
|
1225 "\\(module\\)\\|" ; 7
|
|
1226 "\\(primitive\\)\\|" ; 8
|
|
1227 "\\(interface\\)\\|" ; 9
|
|
1228 "\\(package\\)\\|" ; 10
|
|
1229 "\\(class\\)\\|" ; 11
|
|
1230 "\\(group\\)\\|" ; 12
|
|
1231 "\\(program\\)\\|" ; 13
|
|
1232 "\\(sequence\\)\\|" ; 14
|
|
1233 "\\(clocking\\)\\|" ; 15
|
|
1234 "\\)\\>\\)"))
|
|
1235 (defconst verilog-end-block-re
|
|
1236 (eval-when-compile
|
|
1237 (verilog-regexp-words
|
|
1238
|
|
1239 `("end" ;; closes begin
|
|
1240 "endcase" ;; closes any of case, casex casez or randcase
|
|
1241 "join" "join_any" "join_none" ;; closes fork
|
|
1242 "endclass"
|
|
1243 "endtable"
|
|
1244 "endspecify"
|
|
1245 "endfunction"
|
|
1246 "endgenerate"
|
|
1247 "endtask"
|
|
1248 "endgroup"
|
|
1249 "endproperty"
|
|
1250 "endinterface"
|
|
1251 "endpackage"
|
|
1252 "endprogram"
|
|
1253 "endsequence"
|
|
1254 "endclocking"
|
|
1255 )
|
|
1256 )))
|
|
1257
|
|
1258
|
|
1259 (defconst verilog-endcomment-reason-re
|
|
1260 ;; Parenthesis indicate type of keyword found
|
|
1261 (concat
|
|
1262 "\\(\\<fork\\>\\)\\|"
|
|
1263 "\\(\\<begin\\>\\)\\|"
|
|
1264 "\\(\\<if\\>\\)\\|"
|
|
1265 "\\(\\<clocking\\>\\)\\|"
|
|
1266 "\\(\\<else\\>\\)\\|"
|
|
1267 "\\(\\<end\\>.*\\<else\\>\\)\\|"
|
|
1268 "\\(\\<task\\>\\)\\|"
|
|
1269 "\\(\\<function\\>\\)\\|"
|
|
1270 "\\(\\<initial\\>\\)\\|"
|
|
1271 "\\(\\<interface\\>\\)\\|"
|
|
1272 "\\(\\<package\\>\\)\\|"
|
|
1273 "\\(\\<final\\>\\)\\|"
|
|
1274 "\\(\\<always\\>\\(\[ \t\]*@\\)?\\)\\|"
|
|
1275 "\\(\\<always_comb\\>\\(\[ \t\]*@\\)?\\)\\|"
|
|
1276 "\\(\\<always_ff\\>\\(\[ \t\]*@\\)?\\)\\|"
|
|
1277 "\\(\\<always_latch\\>\\(\[ \t\]*@\\)?\\)\\|"
|
|
1278 "\\(@\\)\\|"
|
|
1279 "\\(\\<while\\>\\)\\|"
|
|
1280 "\\(\\<for\\(ever\\|each\\)?\\>\\)\\|"
|
|
1281 "\\(\\<repeat\\>\\)\\|\\(\\<wait\\>\\)\\|"
|
|
1282 "#"))
|
|
1283
|
|
1284 (defconst verilog-named-block-re "begin[ \t]*:")
|
|
1285
|
|
1286 ;; These words begin a block which can occur inside a module which should be indented,
|
|
1287 ;; and closed with the respective word from the end-block list
|
|
1288
|
|
1289 (defconst verilog-beg-block-re
|
|
1290 (eval-when-compile
|
|
1291 (verilog-regexp-words
|
|
1292 `("begin"
|
|
1293 "case" "casex" "casez" "randcase"
|
|
1294 "clocking"
|
|
1295 "generate"
|
|
1296 "fork"
|
|
1297 "function"
|
|
1298 "property"
|
|
1299 "specify"
|
|
1300 "table"
|
|
1301 "task"
|
|
1302 ))))
|
|
1303 ;; These are the same words, in a specific order in the regular
|
|
1304 ;; expression so that matching will work nicely for
|
|
1305 ;; verilog-forward-sexp and verilog-calc-indent
|
|
1306
|
|
1307 (defconst verilog-beg-block-re-ordered
|
|
1308 ( concat "\\<"
|
|
1309 "\\(begin\\)" ;1
|
|
1310 "\\|\\(randcase\\|\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?\\)" ; 2
|
|
1311 ;; "\\|\\(randcase\\|case[xz]?\\)" ; 2
|
|
1312 "\\|\\(fork\\)" ;3
|
|
1313 "\\|\\(class\\)" ;4
|
|
1314 "\\|\\(table\\)" ;5
|
|
1315 "\\|\\(specify\\)" ;6
|
|
1316 "\\|\\(function\\)" ;7
|
|
1317 "\\|\\(task\\)" ;8
|
|
1318 "\\|\\(generate\\)" ;9
|
|
1319 "\\|\\(covergroup\\)" ;10
|
|
1320 "\\|\\(property\\)" ;11
|
|
1321 "\\|\\(\\(rand\\)?sequence\\)" ;12
|
|
1322 "\\|\\(clocking\\)" ;13
|
|
1323 "\\>"))
|
|
1324
|
|
1325 (defconst verilog-end-block-ordered-rry
|
|
1326 [ "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)"
|
|
1327 "\\(\\<randcase\\>\\|\\<case[xz]?\\>\\)\\|\\(\\<endcase\\>\\)"
|
|
1328 "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)"
|
|
1329 "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)"
|
|
1330 "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)"
|
|
1331 "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)"
|
|
1332 "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)"
|
|
1333 "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)"
|
|
1334 "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)"
|
|
1335 "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)"
|
|
1336 "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)"
|
|
1337 "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)"
|
|
1338 "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)"
|
|
1339 ] )
|
|
1340
|
|
1341 (defconst verilog-nameable-item-re
|
|
1342 (eval-when-compile
|
|
1343 (verilog-regexp-words
|
|
1344 `("begin"
|
|
1345 "fork"
|
|
1346 "join" "join_any" "join_none"
|
|
1347 "end"
|
|
1348 "endcase"
|
|
1349 "endconfig"
|
|
1350 "endclass"
|
|
1351 "endclocking"
|
|
1352 "endfunction"
|
|
1353 "endgenerate"
|
|
1354 "endmodule"
|
|
1355 "endprimative"
|
|
1356 "endinterface"
|
|
1357 "endpackage"
|
|
1358 "endspecify"
|
|
1359 "endtable"
|
|
1360 "endtask" )
|
|
1361 )))
|
|
1362
|
|
1363 (defconst verilog-declaration-opener
|
|
1364 (eval-when-compile
|
|
1365 (verilog-regexp-words
|
|
1366 `("module" "begin" "task" "function"))))
|
|
1367
|
|
1368 (defconst verilog-declaration-prefix-re
|
|
1369 (eval-when-compile
|
|
1370 (verilog-regexp-words
|
|
1371 `(
|
|
1372 ;; port direction
|
79546
|
1373 "inout" "input" "output" "ref"
|
79545
|
1374 ;; changeableness
|
|
1375 "const" "static" "protected" "local"
|
|
1376 ;; parameters
|
79546
|
1377 "localparam" "parameter" "var"
|
79545
|
1378 ;; type creation
|
|
1379 "typedef"
|
|
1380 ))))
|
|
1381 (defconst verilog-declaration-core-re
|
|
1382 (eval-when-compile
|
|
1383 (verilog-regexp-words
|
|
1384 `(
|
|
1385 ;; integer_atom_type
|
|
1386 "byte" "shortint" "int" "longint" "integer" "time"
|
|
1387 ;; integer_vector_type
|
|
1388 "bit" "logic" "reg"
|
|
1389 ;; non_integer_type
|
|
1390 "shortreal" "real" "realtime"
|
|
1391 ;; net_type
|
|
1392 "supply0" "supply1" "tri" "triand" "trior" "trireg" "tri0" "tri1" "uwire" "wire" "wand" "wor"
|
|
1393 ;; misc
|
|
1394 "string" "event" "chandle" "virtual" "enum" "genvar"
|
|
1395 "struct" "union"
|
|
1396 ;; builtin classes
|
79546
|
1397 "mailbox" "semaphore"
|
79545
|
1398 ))))
|
79546
|
1399 (defconst verilog-declaration-re
|
79545
|
1400 (concat "\\(" verilog-declaration-prefix-re "\\s-*\\)?" verilog-declaration-core-re))
|
|
1401 (defconst verilog-range-re "\\(\\[[^]]*\\]\\s-*\\)+")
|
|
1402 (defconst verilog-optional-signed-re "\\s-*\\(signed\\)?")
|
|
1403 (defconst verilog-optional-signed-range-re
|
|
1404 (concat
|
|
1405 "\\s-*\\(\\<\\(reg\\|wire\\)\\>\\s-*\\)?\\(\\<signed\\>\\s-*\\)?\\(" verilog-range-re "\\)?"))
|
|
1406 (defconst verilog-macroexp-re "`\\sw+")
|
|
1407
|
|
1408 (defconst verilog-delay-re "#\\s-*\\(\\([0-9_]+\\('s?[hdxbo][0-9a-fA-F_xz]+\\)?\\)\\|\\(([^()]*)\\)\\|\\(\\sw+\\)\\)")
|
|
1409 (defconst verilog-declaration-re-2-no-macro
|
|
1410 (concat "\\s-*" verilog-declaration-re
|
|
1411 "\\s-*\\(\\(" verilog-optional-signed-range-re "\\)\\|\\(" verilog-delay-re "\\)"
|
|
1412 "\\)?"))
|
|
1413 (defconst verilog-declaration-re-2-macro
|
|
1414 (concat "\\s-*" verilog-declaration-re
|
|
1415 "\\s-*\\(\\(" verilog-optional-signed-range-re "\\)\\|\\(" verilog-delay-re "\\)"
|
|
1416 "\\|\\(" verilog-macroexp-re "\\)"
|
|
1417 "\\)?"))
|
|
1418 (defconst verilog-declaration-re-1-macro
|
|
1419 (concat "^" verilog-declaration-re-2-macro))
|
|
1420
|
|
1421 (defconst verilog-declaration-re-1-no-macro (concat "^" verilog-declaration-re-2-no-macro))
|
|
1422
|
|
1423 (defconst verilog-defun-re
|
|
1424 (eval-when-compile (verilog-regexp-words `("macromodule" "module" "class" "program" "interface" "package" "primitive" "config"))))
|
|
1425 (defconst verilog-end-defun-re
|
|
1426 (eval-when-compile (verilog-regexp-words `("endmodule" "endclass" "endprogram" "endinterface" "endpackage" "endprimitive" "endconfig"))))
|
|
1427 (defconst verilog-zero-indent-re
|
|
1428 (concat verilog-defun-re "\\|" verilog-end-defun-re))
|
|
1429
|
|
1430 (defconst verilog-behavioral-block-beg-re
|
|
1431 (concat "\\(\\<initial\\>\\|\\<final\\>\\|\\<always\\>\\|\\<always_comb\\>\\|\\<always_ff\\>\\|"
|
|
1432 "\\<always_latch\\>\\|\\<function\\>\\|\\<task\\>\\)"))
|
|
1433
|
|
1434 (defconst verilog-indent-re
|
|
1435 (eval-when-compile
|
|
1436 (verilog-regexp-words
|
|
1437 `(
|
|
1438 "{"
|
|
1439 "always" "always_latch" "always_ff" "always_comb"
|
|
1440 "begin" "end"
|
|
1441 ; "unique" "priority"
|
|
1442 "case" "casex" "casez" "randcase" "endcase"
|
|
1443 "class" "endclass"
|
|
1444 "clocking" "endclocking"
|
|
1445 "config" "endconfig"
|
|
1446 "covergroup" "endgroup"
|
|
1447 "fork" "join" "join_any" "join_none"
|
|
1448 "function" "endfunction"
|
|
1449 "final"
|
|
1450 "generate" "endgenerate"
|
|
1451 "initial"
|
|
1452 "interface" "endinterface"
|
|
1453 "module" "macromodule" "endmodule"
|
|
1454 "package" "endpackage"
|
|
1455 "primitive" "endprimative"
|
|
1456 "program" "endprogram"
|
|
1457 "property" "endproperty"
|
|
1458 "sequence" "randsequence" "endsequence"
|
|
1459 "specify" "endspecify"
|
|
1460 "table" "endtable"
|
|
1461 "task" "endtask"
|
|
1462 "`case"
|
|
1463 "`default"
|
|
1464 "`define" "`undef"
|
|
1465 "`if" "`ifdef" "`ifndef" "`else" "`endif"
|
|
1466 "`while" "`endwhile"
|
|
1467 "`for" "`endfor"
|
|
1468 "`format"
|
|
1469 "`include"
|
|
1470 "`let"
|
|
1471 "`protect" "`endprotect"
|
|
1472 "`switch" "`endswitch"
|
|
1473 "`timescale"
|
|
1474 "`time_scale"
|
|
1475 ))))
|
|
1476
|
|
1477 (defconst verilog-defun-level-re
|
|
1478 (eval-when-compile
|
|
1479 (verilog-regexp-words
|
|
1480 `(
|
|
1481 "module" "macromodule" "primitive" "class" "program" "initial" "final" "always" "always_comb"
|
|
1482 "always_ff" "always_latch" "endtask" "endfunction" "interface" "package"
|
|
1483 "config"))))
|
|
1484
|
|
1485 (defconst verilog-defun-level-not-generate-re
|
|
1486 (eval-when-compile
|
|
1487 (verilog-regexp-words
|
|
1488 `(
|
|
1489 "module" "macromodule" "primitive" "class" "program" "interface" "package" "config"))))
|
|
1490
|
|
1491 (defconst verilog-cpp-level-re
|
|
1492 (eval-when-compile
|
|
1493 (verilog-regexp-words
|
|
1494 `(
|
|
1495 "endmodule" "endprimitive" "endinterface" "endpackage" "endprogram" "endclass"
|
|
1496 ))))
|
|
1497 (defconst verilog-extended-case-re "\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?")
|
|
1498 (defconst verilog-extended-complete-re
|
|
1499 (concat "\\(\\<extern\\s-+\\|\\<virtual\\s-+\\|\\<protected\\s-+\\)*\\(\\<function\\>\\|\\<task\\>\\)"
|
|
1500 "\\|\\(\\<typedef\\>\\s-+\\)*\\(\\<struct\\>\\|\\<union\\>\\|\\<class\\>\\)"
|
|
1501 "\\|" verilog-extended-case-re ))
|
|
1502 (defconst verilog-basic-complete-re
|
|
1503 (eval-when-compile
|
|
1504 (verilog-regexp-words
|
|
1505 `(
|
|
1506 "always" "assign" "always_latch" "always_ff" "always_comb" "constraint"
|
|
1507 "import" "initial" "final" "module" "macromodule" "repeat" "randcase" "while"
|
|
1508 "if" "for" "forever" "foreach" "else" "parameter" "do"
|
|
1509 ))))
|
|
1510 (defconst verilog-complete-reg
|
|
1511 (concat
|
|
1512 verilog-extended-complete-re
|
|
1513 "\\|"
|
|
1514 verilog-basic-complete-re))
|
|
1515
|
|
1516 (defconst verilog-end-statement-re
|
|
1517 (concat "\\(" verilog-beg-block-re "\\)\\|\\("
|
|
1518 verilog-end-block-re "\\)"))
|
|
1519
|
|
1520 (defconst verilog-endcase-re
|
|
1521 (concat verilog-case-re "\\|"
|
|
1522 "\\(endcase\\)\\|"
|
|
1523 verilog-defun-re
|
|
1524 ))
|
|
1525
|
|
1526 (defconst verilog-exclude-str-start "/* -----\\/----- EXCLUDED -----\\/-----"
|
|
1527 "String used to mark beginning of excluded text.")
|
|
1528 (defconst verilog-exclude-str-end " -----/\\----- EXCLUDED -----/\\----- */"
|
|
1529 "String used to mark end of excluded text.")
|
|
1530 (defconst verilog-preprocessor-re
|
|
1531 (eval-when-compile
|
|
1532 (verilog-regexp-words
|
|
1533 `(
|
|
1534 "`define" "`include" "`ifdef" "`ifndef" "`if" "`endif" "`else"
|
|
1535 ))))
|
|
1536
|
|
1537 (defconst verilog-keywords
|
|
1538 '( "`case" "`default" "`define" "`else" "`endfor" "`endif"
|
|
1539 "`endprotect" "`endswitch" "`endwhile" "`for" "`format" "`if" "`ifdef"
|
|
1540 "`ifndef" "`include" "`let" "`protect" "`switch" "`timescale"
|
|
1541 "`time_scale" "`undef" "`while"
|
|
1542
|
|
1543 "after" "alias" "always" "always_comb" "always_ff" "always_latch" "and"
|
|
1544 "assert" "assign" "assume" "automatic" "before" "begin" "bind"
|
|
1545 "bins" "binsof" "bit" "break" "buf" "bufif0" "bufif1" "byte"
|
|
1546 "case" "casex" "casez" "cell" "chandle" "class" "clocking" "cmos"
|
|
1547 "config" "const" "constraint" "context" "continue" "cover"
|
|
1548 "covergroup" "coverpoint" "cross" "deassign" "default" "defparam"
|
|
1549 "design" "disable" "dist" "do" "edge" "else" "end" "endcase"
|
|
1550 "endclass" "endclocking" "endconfig" "endfunction" "endgenerate"
|
|
1551 "endgroup" "endinterface" "endmodule" "endpackage" "endprimitive"
|
|
1552 "endprogram" "endproperty" "endspecify" "endsequence" "endtable"
|
|
1553 "endtask" "enum" "event" "expect" "export" "extends" "extern"
|
|
1554 "final" "first_match" "for" "force" "foreach" "forever" "fork"
|
|
1555 "forkjoin" "function" "generate" "genvar" "highz0" "highz1" "if"
|
|
1556 "iff" "ifnone" "ignore_bins" "illegal_bins" "import" "incdir"
|
|
1557 "include" "initial" "inout" "input" "inside" "instance" "int"
|
|
1558 "integer" "interface" "intersect" "join" "join_any" "join_none"
|
|
1559 "large" "liblist" "library" "local" "localparam" "logic"
|
|
1560 "longint" "macromodule" "mailbox" "matches" "medium" "modport" "module"
|
|
1561 "nand" "negedge" "new" "nmos" "nor" "noshowcancelled" "not"
|
|
1562 "notif0" "notif1" "null" "or" "output" "package" "packed"
|
|
1563 "parameter" "pmos" "posedge" "primitive" "priority" "program"
|
|
1564 "property" "protected" "pull0" "pull1" "pulldown" "pullup"
|
|
1565 "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc"
|
|
1566 "randcase" "randsequence" "rcmos" "real" "realtime" "ref" "reg"
|
|
1567 "release" "repeat" "return" "rnmos" "rpmos" "rtran" "rtranif0"
|
|
1568 "rtranif1" "scalared" "semaphore" "sequence" "shortint" "shortreal"
|
|
1569 "showcancelled" "signed" "small" "solve" "specify" "specparam"
|
|
1570 "static" "string" "strong0" "strong1" "struct" "super" "supply0"
|
|
1571 "supply1" "table" "tagged" "task" "this" "throughout" "time"
|
|
1572 "timeprecision" "timeunit" "tran" "tranif0" "tranif1" "tri"
|
|
1573 "tri0" "tri1" "triand" "trior" "trireg" "type" "typedef" "union"
|
|
1574 "unique" "unsigned" "use" "uwire" "var" "vectored" "virtual" "void"
|
|
1575 "wait" "wait_order" "wand" "weak0" "weak1" "while" "wildcard"
|
|
1576 "wire" "with" "within" "wor" "xnor" "xor"
|
|
1577 )
|
|
1578 "List of Verilog keywords.")
|
|
1579
|
|
1580
|
|
1581 (defconst verilog-emacs-features
|
|
1582 ;; Documentation at the bottom
|
|
1583 (let ((major (and (boundp 'emacs-major-version)
|
|
1584 emacs-major-version))
|
|
1585 (minor (and (boundp 'emacs-minor-version)
|
|
1586 emacs-minor-version))
|
|
1587 flavor comments flock-syntax)
|
|
1588 ;; figure out version numbers if not already discovered
|
|
1589 (and (or (not major) (not minor))
|
|
1590 (string-match "\\([0-9]+\\).\\([0-9]+\\)" emacs-version)
|
|
1591 (setq major (string-to-int (substring emacs-version
|
|
1592 (match-beginning 1)
|
|
1593 (match-end 1)))
|
|
1594 minor (string-to-int (substring emacs-version
|
|
1595 (match-beginning 2)
|
|
1596 (match-end 2)))))
|
|
1597 (if (not (and major minor))
|
|
1598 (error "Cannot figure out the major and minor version numbers"))
|
|
1599 ;; calculate the major version
|
|
1600 (cond
|
|
1601 ((= major 4) (setq major 'v18)) ;Epoch 4
|
|
1602 ((= major 18) (setq major 'v18)) ;Emacs 18
|
|
1603 ((= major 19) (setq major 'v19 ;Emacs 19
|
|
1604 flavor (if (or (string-match "Lucid" emacs-version)
|
|
1605 (string-match "XEmacs" emacs-version))
|
|
1606 'XEmacs 'FSF)))
|
|
1607 ((> major 19) (setq major 'v20
|
|
1608 flavor (if (or (string-match "Lucid" emacs-version)
|
|
1609 (string-match "XEmacs" emacs-version))
|
|
1610 'XEmacs 'FSF)))
|
|
1611 ;; I don't know
|
|
1612 (t (error "Cannot recognize major version number: %s" major)))
|
|
1613 ;; XEmacs 19 uses 8-bit modify-syntax-entry flags, as do all
|
|
1614 ;; patched Emacs 19, Emacs 18, Epoch 4's. Only Emacs 19 uses a
|
|
1615 ;; 1-bit flag. Let's be as smart as we can about figuring this
|
|
1616 ;; out.
|
|
1617 (if (or (eq major 'v20) (eq major 'v19))
|
|
1618 (let ((table (copy-syntax-table)))
|
|
1619 (modify-syntax-entry ?a ". 12345678" table)
|
|
1620 (cond
|
|
1621 ;; XEmacs pre 20 and Emacs pre 19.30 use vectors for syntax tables.
|
|
1622 ((vectorp table)
|
|
1623 (if (= (logand (lsh (aref table ?a) -16) 255) 255)
|
|
1624 (setq comments '8-bit)
|
|
1625 (setq comments '1-bit)))
|
|
1626 ;; XEmacs 20 is known to be 8-bit
|
|
1627 ((eq flavor 'XEmacs) (setq comments '8-bit))
|
|
1628 ;; Emacs 19.30 and beyond are known to be 1-bit
|
|
1629 ((eq flavor 'FSF) (setq comments '1-bit))
|
|
1630 ;; Don't know what this is
|
|
1631 (t (error "Couldn't figure out syntax table format"))
|
|
1632 ))
|
|
1633 ;; Emacs 18 has no support for dual comments
|
|
1634 (setq comments 'no-dual-comments))
|
|
1635 ;; determine whether to use old or new font lock syntax
|
|
1636 ;; We can assume 8-bit syntax table emacsen support new syntax, otherwise
|
|
1637 ;; look for version > 19.30
|
|
1638 (setq flock-syntax
|
|
1639 (if (or (equal comments '8-bit)
|
|
1640 (equal major 'v20)
|
|
1641 (and (equal major 'v19) (> minor 30)))
|
|
1642 'flock-syntax-after-1930
|
|
1643 'flock-syntax-before-1930))
|
|
1644 ;; lets do some minimal sanity checking.
|
|
1645 (if (or
|
|
1646 ;; Emacs before 19.6 had bugs
|
|
1647 (and (eq major 'v19) (eq flavor 'XEmacs) (< minor 6))
|
|
1648 ;; Emacs 19 before 19.21 has known bugs
|
|
1649 (and (eq major 'v19) (eq flavor 'FSF) (< minor 21))
|
|
1650 )
|
|
1651 (with-output-to-temp-buffer "*verilog-mode warnings*"
|
|
1652 (print (format
|
|
1653 "The version of Emacs that you are running, %s,
|
|
1654 has known bugs in its syntax parsing routines which will affect the
|
|
1655 performance of verilog-mode. You should strongly consider upgrading to the
|
|
1656 latest available version. verilog-mode may continue to work, after a
|
|
1657 fashion, but strange indentation errors could be encountered."
|
|
1658 emacs-version))))
|
|
1659 ;; Emacs 18, with no patch is not too good
|
|
1660 (if (and (eq major 'v18) (eq comments 'no-dual-comments))
|
|
1661 (with-output-to-temp-buffer "*verilog-mode warnings*"
|
|
1662 (print (format
|
|
1663 "The version of Emacs 18 you are running, %s,
|
|
1664 has known deficiencies in its ability to handle the dual verilog
|
79546
|
1665 \(and C++) comments, (e.g. the // and /* */ comments). This will
|
79545
|
1666 not be much of a problem for you if you only use the /* */ comments,
|
|
1667 but you really should strongly consider upgrading to one of the latest
|
|
1668 Emacs 19's. In Emacs 18, you may also experience performance degradations.
|
|
1669 Emacs 19 has some new built-in routines which will speed things up for you.
|
|
1670 Because of these inherent problems, verilog-mode is not supported
|
|
1671 on emacs-18."
|
|
1672 emacs-version))))
|
|
1673 ;; Emacs 18 with the syntax patches are no longer supported
|
|
1674 (if (and (eq major 'v18) (not (eq comments 'no-dual-comments)))
|
|
1675 (with-output-to-temp-buffer "*verilog-mode warnings*"
|
|
1676 (print (format
|
|
1677 "You are running a syntax patched Emacs 18 variant. While this should
|
|
1678 work for you, you may want to consider upgrading to Emacs 19.
|
|
1679 The syntax patches are no longer supported either for verilog-mode."))))
|
|
1680 (list major comments flock-syntax))
|
|
1681 "A list of features extant in the Emacs you are using.
|
|
1682 There are many flavors of Emacs out there, each with different
|
|
1683 features supporting those needed by `verilog-mode'. Here's the current
|
|
1684 supported list, along with the values for this variable:
|
|
1685
|
|
1686 Vanilla Emacs 18/Epoch 4: (v18 no-dual-comments flock-syntax-before-1930)
|
|
1687 Emacs 18/Epoch 4 (patch2): (v18 8-bit flock-syntax-after-1930)
|
|
1688 XEmacs (formerly Lucid) 19: (v19 8-bit flock-syntax-after-1930)
|
|
1689 XEmacs 20: (v20 8-bit flock-syntax-after-1930)
|
|
1690 Emacs 19.1-19.30: (v19 8-bit flock-syntax-before-1930)
|
|
1691 Emacs 19.31-19.xx: (v19 8-bit flock-syntax-after-1930)
|
|
1692 Emacs20 : (v20 1-bit flock-syntax-after-1930).")
|
|
1693
|
|
1694 (defconst verilog-comment-start-regexp "//\\|/\\*"
|
|
1695 "Dual comment value for `comment-start-regexp'.")
|
|
1696
|
|
1697 (defun verilog-populate-syntax-table (table)
|
|
1698 "Populate the syntax TABLE."
|
|
1699 (modify-syntax-entry ?\\ "\\" table)
|
|
1700 (modify-syntax-entry ?+ "." table)
|
|
1701 (modify-syntax-entry ?- "." table)
|
|
1702 (modify-syntax-entry ?= "." table)
|
|
1703 (modify-syntax-entry ?% "." table)
|
|
1704 (modify-syntax-entry ?< "." table)
|
|
1705 (modify-syntax-entry ?> "." table)
|
|
1706 (modify-syntax-entry ?& "." table)
|
|
1707 (modify-syntax-entry ?| "." table)
|
|
1708 (modify-syntax-entry ?` "w" table)
|
|
1709 (modify-syntax-entry ?_ "w" table)
|
|
1710 (modify-syntax-entry ?\' "." table)
|
|
1711 )
|
|
1712
|
|
1713 (defun verilog-setup-dual-comments (table)
|
|
1714 "Set up TABLE to handle block and line style comments."
|
|
1715 (cond
|
|
1716 ((memq '8-bit verilog-emacs-features)
|
|
1717 ;; XEmacs (formerly Lucid) has the best implementation
|
|
1718 (modify-syntax-entry ?/ ". 1456" table)
|
|
1719 (modify-syntax-entry ?* ". 23" table)
|
|
1720 (modify-syntax-entry ?\n "> b" table)
|
|
1721 )
|
|
1722 ((memq '1-bit verilog-emacs-features)
|
|
1723 ;; Emacs 19 does things differently, but we can work with it
|
|
1724 (modify-syntax-entry ?/ ". 124b" table)
|
|
1725 (modify-syntax-entry ?* ". 23" table)
|
|
1726 (modify-syntax-entry ?\n "> b" table)
|
|
1727 )
|
|
1728 ))
|
|
1729
|
|
1730 (defvar verilog-mode-syntax-table nil
|
|
1731 "Syntax table used in `verilog-mode' buffers.")
|
|
1732
|
|
1733 (defconst verilog-font-lock-keywords nil
|
|
1734 "Default highlighting for Verilog mode.")
|
|
1735
|
|
1736 (defconst verilog-font-lock-keywords-1 nil
|
|
1737 "Subdued level highlighting for Verilog mode.")
|
|
1738
|
|
1739 (defconst verilog-font-lock-keywords-2 nil
|
|
1740 "Medium level highlighting for Verilog mode.
|
|
1741 See also `verilog-font-lock-extra-types'.")
|
|
1742
|
|
1743 (defconst verilog-font-lock-keywords-3 nil
|
|
1744 "Gaudy level highlighting for Verilog mode.
|
|
1745 See also `verilog-font-lock-extra-types'.")
|
|
1746 (defvar verilog-font-lock-translate-off-face
|
|
1747 'verilog-font-lock-translate-off-face
|
|
1748 "Font to use for translated off regions.")
|
|
1749 (defface verilog-font-lock-translate-off-face
|
|
1750 '((((class color)
|
|
1751 (background light))
|
|
1752 (:background "gray90" :italic t ))
|
|
1753 (((class color)
|
|
1754 (background dark))
|
|
1755 (:background "gray10" :italic t ))
|
|
1756 (((class grayscale) (background light))
|
|
1757 (:foreground "DimGray" :italic t))
|
|
1758 (((class grayscale) (background dark))
|
|
1759 (:foreground "LightGray" :italic t))
|
|
1760 (t (:italis t)))
|
|
1761 "Font lock mode face used to background highlight translate-off regions."
|
|
1762 :group 'font-lock-highlighting-faces)
|
|
1763
|
|
1764 (defvar verilog-font-lock-p1800-face
|
|
1765 'verilog-font-lock-p1800-face
|
|
1766 "Font to use for p1800 keywords.")
|
|
1767 (defface verilog-font-lock-p1800-face
|
|
1768 '((((class color)
|
|
1769 (background light))
|
|
1770 (:foreground "DarkOrange3" :bold t ))
|
|
1771 (((class color)
|
|
1772 (background dark))
|
|
1773 (:foreground "orange1" :bold t ))
|
|
1774 (t (:italic t)))
|
|
1775 "Font lock mode face used to highlight P1800 keywords."
|
|
1776 :group 'font-lock-highlighting-faces)
|
|
1777
|
|
1778 (defvar verilog-font-lock-ams-face
|
|
1779 'verilog-font-lock-ams-face
|
|
1780 "Font to use for Analog/Mixed Signal keywords.")
|
|
1781 (defface verilog-font-lock-ams-face
|
|
1782 '((((class color)
|
|
1783 (background light))
|
|
1784 (:foreground "Purple" :bold t ))
|
|
1785 (((class color)
|
|
1786 (background dark))
|
|
1787 (:foreground "orange1" :bold t ))
|
|
1788 (t (:italic t)))
|
|
1789 "Font lock mode face used to highlight AMS keywords."
|
|
1790 :group 'font-lock-highlighting-faces)
|
|
1791
|
|
1792 (let* ((verilog-type-font-keywords
|
|
1793 (eval-when-compile
|
|
1794 (verilog-regexp-opt
|
|
1795 '(
|
|
1796 "and" "bit" "buf" "bufif0" "bufif1" "cmos" "defparam"
|
|
1797 "event" "genvar" "inout" "input" "integer" "localparam"
|
|
1798 "logic" "mailbox" "nand" "nmos" "not" "notif0" "notif1" "or"
|
|
1799 "output" "parameter" "pmos" "pull0" "pull1" "pullup"
|
|
1800 "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran"
|
|
1801 "rtranif0" "rtranif1" "semaphore" "signed" "struct" "supply"
|
|
1802 "supply0" "supply1" "time" "tran" "tranif0" "tranif1"
|
|
1803 "tri" "tri0" "tri1" "triand" "trior" "trireg" "typedef"
|
|
1804 "uwire" "vectored" "wand" "wire" "wor" "xnor" "xor"
|
|
1805 ) nil )))
|
|
1806
|
|
1807 (verilog-pragma-keywords
|
|
1808 (eval-when-compile
|
|
1809 (verilog-regexp-opt
|
|
1810 '("surefire" "synopsys" "rtl_synthesis" "verilint" ) nil
|
|
1811 )))
|
|
1812
|
|
1813 (verilog-p1800-keywords
|
|
1814 (eval-when-compile
|
|
1815 (verilog-regexp-opt
|
|
1816 '("alias" "assert" "assume" "automatic" "before" "bind"
|
|
1817 "bins" "binsof" "break" "byte" "cell" "chandle" "class"
|
|
1818 "clocking" "config" "const" "constraint" "context" "continue"
|
|
1819 "cover" "covergroup" "coverpoint" "cross" "deassign" "design"
|
|
1820 "dist" "do" "edge" "endclass" "endclocking" "endconfig"
|
|
1821 "endgroup" "endprogram" "endproperty" "endsequence" "enum"
|
|
1822 "expect" "export" "extends" "extern" "first_match" "foreach"
|
|
1823 "forkjoin" "genvar" "highz0" "highz1" "ifnone" "ignore_bins"
|
|
1824 "illegal_bins" "import" "incdir" "include" "inside" "instance"
|
|
1825 "int" "intersect" "large" "liblist" "library" "local" "longint"
|
|
1826 "matches" "medium" "modport" "new" "noshowcancelled" "null"
|
|
1827 "packed" "program" "property" "protected" "pull0" "pull1"
|
|
1828 "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc"
|
|
1829 "randcase" "randsequence" "ref" "release" "return" "scalared"
|
|
1830 "sequence" "shortint" "shortreal" "showcancelled" "small" "solve"
|
|
1831 "specparam" "static" "string" "strong0" "strong1" "struct"
|
|
1832 "super" "tagged" "this" "throughout" "timeprecision" "timeunit"
|
|
1833 "type" "union" "unsigned" "use" "var" "virtual" "void"
|
|
1834 "wait_order" "weak0" "weak1" "wildcard" "with" "within"
|
|
1835 ) nil )))
|
|
1836
|
|
1837 (verilog-ams-keywords
|
|
1838 (eval-when-compile
|
|
1839 (verilog-regexp-opt
|
|
1840 '("above" "abs" "absdelay" "acos" "acosh" "ac_stim"
|
|
1841 "aliasparam" "analog" "analysis" "asin" "asinh" "atan" "atan2" "atanh"
|
|
1842 "branch" "ceil" "connectmodule" "connectrules" "cos" "cosh" "ddt"
|
|
1843 "ddx" "discipline" "driver_update" "enddiscipline" "endconnectrules"
|
|
1844 "endnature" "endparamset" "exclude" "exp" "final_step" "flicker_noise"
|
|
1845 "floor" "flow" "from" "ground" "hypot" "idt" "idtmod" "inf"
|
|
1846 "initial_step" "laplace_nd" "laplace_np" "laplace_zd" "laplace_zp"
|
|
1847 "last_crossing" "limexp" "ln" "log" "max" "min" "nature"
|
|
1848 "net_resolution" "noise_table" "paramset" "potential" "pow" "sin"
|
|
1849 "sinh" "slew" "sqrt" "tan" "tanh" "timer" "transition" "white_noise"
|
|
1850 "wreal" "zi_nd" "zi_np" "zi_zd" ) nil )))
|
|
1851
|
|
1852 (verilog-font-keywords
|
|
1853 (eval-when-compile
|
|
1854 (verilog-regexp-opt
|
|
1855 '(
|
|
1856 "assign" "begin" "case" "casex" "casez" "randcase" "deassign"
|
|
1857 "default" "disable" "else" "end" "endcase" "endfunction"
|
|
1858 "endgenerate" "endinterface" "endmodule" "endprimitive"
|
|
1859 "endspecify" "endtable" "endtask" "final" "for" "force" "return" "break"
|
|
1860 "continue" "forever" "fork" "function" "generate" "if" "iff" "initial"
|
|
1861 "interface" "join" "join_any" "join_none" "macromodule" "module" "negedge"
|
|
1862 "package" "endpackage" "always" "always_comb" "always_ff"
|
|
1863 "always_latch" "posedge" "primitive" "priority" "release"
|
|
1864 "repeat" "specify" "table" "task" "unique" "wait" "while"
|
|
1865 "class" "program" "endclass" "endprogram"
|
|
1866 ) nil ))))
|
|
1867
|
|
1868 (setq verilog-font-lock-keywords
|
|
1869 (list
|
|
1870 ;; Fontify all builtin keywords
|
|
1871 (concat "\\<\\(" verilog-font-keywords "\\|"
|
|
1872 ;; And user/system tasks and functions
|
|
1873 "\\$[a-zA-Z][a-zA-Z0-9_\\$]*"
|
|
1874 "\\)\\>")
|
|
1875 ;; Fontify all types
|
|
1876 (cons (concat "\\<\\(" verilog-type-font-keywords "\\)\\>")
|
|
1877 'font-lock-type-face)
|
|
1878 ;; Fontify IEEE-P1800 keywords appropriately
|
|
1879 (if verilog-highlight-p1800-keywords
|
|
1880 (cons (concat "\\<\\(" verilog-p1800-keywords "\\)\\>")
|
|
1881 'verilog-font-lock-p1800-face)
|
|
1882 (cons (concat "\\<\\(" verilog-p1800-keywords "\\)\\>")
|
|
1883 'font-lock-type-face))
|
|
1884 ;; Fontify Verilog-AMS keywords
|
|
1885 (cons (concat "\\<\\(" verilog-ams-keywords "\\)\\>")
|
|
1886 'verilog-font-lock-ams-face)
|
|
1887 ))
|
|
1888
|
|
1889 (setq verilog-font-lock-keywords-1
|
|
1890 (append verilog-font-lock-keywords
|
|
1891 (list
|
|
1892 ;; Fontify module definitions
|
|
1893 (list
|
|
1894 "\\<\\(\\(macro\\)?module\\|primitive\\|class\\|program\\|interface\\|package\\|task\\)\\>\\s-*\\(\\sw+\\)"
|
|
1895 '(1 font-lock-keyword-face)
|
|
1896 '(3 font-lock-function-name-face 'prepend))
|
|
1897 ;; Fontify function definitions
|
|
1898 (list
|
|
1899 (concat "\\<function\\>\\s-+\\(integer\\|real\\(time\\)?\\|time\\)\\s-+\\(\\sw+\\)" )
|
|
1900 '(1 font-lock-keyword-face)
|
|
1901 '(3 font-lock-reference-face prepend)
|
|
1902 )
|
|
1903 '("\\<function\\>\\s-+\\(\\[[^]]+\\]\\)\\s-+\\(\\sw+\\)"
|
|
1904 (1 font-lock-keyword-face)
|
|
1905 (2 font-lock-reference-face append)
|
|
1906 )
|
|
1907 '("\\<function\\>\\s-+\\(\\sw+\\)"
|
|
1908 1 'font-lock-reference-face append)
|
|
1909 )))
|
|
1910
|
|
1911 (setq verilog-font-lock-keywords-2
|
|
1912 (append verilog-font-lock-keywords-1
|
|
1913 (list
|
|
1914 ;; Fontify pragmas
|
|
1915 (concat "\\(//\\s-*" verilog-pragma-keywords "\\s-.*\\)")
|
|
1916 ;; Fontify escaped names
|
|
1917 '("\\(\\\\\\S-*\\s-\\)" 0 font-lock-function-name-face)
|
|
1918 ;; Fontify macro definitions/ uses
|
|
1919 '("`\\s-*[A-Za-z][A-Za-z0-9_]*" 0 (if (boundp 'font-lock-preprocessor-face)
|
|
1920 'font-lock-preprocessor-face
|
|
1921 'font-lock-type-face))
|
|
1922 ;; Fontify delays/numbers
|
|
1923 '("\\(@\\)\\|\\(#\\s-*\\(\\(\[0-9_.\]+\\('s?[hdxbo][0-9a-fA-F_xz]*\\)?\\)\\|\\(([^()]+)\\|\\sw+\\)\\)\\)"
|
|
1924 0 font-lock-type-face append)
|
|
1925 ;; Fontify instantiation names
|
|
1926 '("\\([A-Za-z][A-Za-z0-9_]+\\)\\s-*(" 1 font-lock-function-name-face)
|
|
1927
|
|
1928 )))
|
|
1929
|
|
1930 (setq verilog-font-lock-keywords-3
|
|
1931 (append verilog-font-lock-keywords-2
|
|
1932 (when verilog-highlight-translate-off
|
|
1933 (list
|
|
1934 ;; Fontify things in translate off regions
|
|
1935 '(verilog-match-translate-off (0 'verilog-font-lock-translate-off-face prepend))
|
|
1936 )))
|
|
1937 )
|
|
1938 )
|
|
1939
|
|
1940
|
|
1941
|
|
1942 (defun verilog-inside-comment-p ()
|
|
1943 "Check if point inside a nested comment."
|
|
1944 (save-excursion
|
|
1945 (let ((st-point (point)) hitbeg)
|
|
1946 (or (search-backward "//" (verilog-get-beg-of-line) t)
|
|
1947 (if (progn
|
|
1948 ;; This is for tricky case //*, we keep searching if /* is proceeded by // on same line
|
|
1949 (while (and (setq hitbeg (search-backward "/*" nil t))
|
|
1950 (progn (forward-char 1) (search-backward "//" (verilog-get-beg-of-line) t))))
|
|
1951 hitbeg)
|
|
1952 (not (search-forward "*/" st-point t)))))))
|
|
1953
|
|
1954 (defun verilog-declaration-end ()
|
|
1955 (search-forward ";"))
|
|
1956
|
|
1957 (defun verilog-point-text (&optional pointnum)
|
|
1958 "Return text describing where POINTNUM or current point is (for errors).
|
|
1959 Use filename, if current buffer being edited shorten to just buffer name."
|
|
1960 (concat (or (and (equal (window-buffer (selected-window)) (current-buffer))
|
|
1961 (buffer-name))
|
|
1962 buffer-file-name
|
|
1963 (buffer-name))
|
|
1964 ":" (int-to-string (count-lines (point-min) (or pointnum (point))))))
|
|
1965
|
|
1966 (defun electric-verilog-backward-sexp ()
|
|
1967 "Move backward over a sexp."
|
|
1968 (interactive)
|
|
1969 ;; before that see if we are in a comment
|
|
1970 (verilog-backward-sexp)
|
|
1971 )
|
|
1972 (defun electric-verilog-forward-sexp ()
|
|
1973 "Move backward over a sexp."
|
|
1974 (interactive)
|
|
1975 ;; before that see if we are in a comment
|
|
1976 (verilog-forward-sexp)
|
|
1977 )
|
|
1978 ;;;used by hs-minor-mode
|
|
1979 (defun verilog-forward-sexp-function (arg)
|
|
1980 (if (< arg 0)
|
|
1981 (verilog-backward-sexp)
|
|
1982 (verilog-forward-sexp)))
|
|
1983
|
|
1984
|
|
1985 (defun verilog-backward-sexp ()
|
|
1986 (let ((reg)
|
|
1987 (elsec 1)
|
|
1988 (found nil)
|
|
1989 (st (point))
|
|
1990 )
|
|
1991 (if (not (looking-at "\\<"))
|
|
1992 (forward-word -1))
|
|
1993 (cond
|
|
1994 ((verilog-skip-backward-comment-or-string)
|
|
1995 )
|
|
1996 ((looking-at "\\<else\\>")
|
|
1997 (setq reg (concat
|
|
1998 verilog-end-block-re
|
|
1999 "\\|\\(\\<else\\>\\)"
|
|
2000 "\\|\\(\\<if\\>\\)"
|
|
2001 ))
|
|
2002 (while (and (not found)
|
|
2003 (verilog-re-search-backward reg nil 'move))
|
|
2004 (cond
|
|
2005 ((match-end 1) ; matched verilog-end-block-re
|
|
2006 ; try to leap back to matching outward block by striding across
|
|
2007 ; indent level changing tokens then immediately
|
|
2008 ; previous line governs indentation.
|
|
2009 (verilog-leap-to-head))
|
|
2010 ((match-end 2) ; else, we're in deep
|
|
2011 (setq elsec (1+ elsec)))
|
|
2012 ((match-end 3) ; found it
|
|
2013 (setq elsec (1- elsec))
|
|
2014 (if (= 0 elsec)
|
|
2015 ;; Now previous line describes syntax
|
|
2016 (setq found 't)
|
|
2017 ))
|
|
2018 )
|
|
2019 )
|
|
2020 )
|
|
2021 ((looking-at verilog-end-block-re)
|
|
2022 (verilog-leap-to-head))
|
|
2023 ((looking-at "\\(endmodule\\>\\)\\|\\(\\<endprimitive\\>\\)\\|\\(\\<endclass\\>\\)\\|\\(\\<endprogram\\>\\)\\|\\(\\<endinterface\\>\\)\\|\\(\\<endpackage\\>\\)")
|
|
2024 (cond
|
|
2025 ((match-end 1)
|
|
2026 (verilog-re-search-backward "\\<\\(macro\\)?module\\>" nil 'move))
|
|
2027 ((match-end 2)
|
|
2028 (verilog-re-search-backward "\\<primitive\\>" nil 'move))
|
|
2029 ((match-end 3)
|
|
2030 (verilog-re-search-backward "\\<class\\>" nil 'move))
|
|
2031 ((match-end 4)
|
|
2032 (verilog-re-search-backward "\\<program\\>" nil 'move))
|
|
2033 ((match-end 5)
|
|
2034 (verilog-re-search-backward "\\<interface\\>" nil 'move))
|
|
2035 ((match-end 6)
|
|
2036 (verilog-re-search-backward "\\<package\\>" nil 'move))
|
|
2037 (t
|
|
2038 (goto-char st)
|
|
2039 (backward-sexp 1))))
|
|
2040 (t
|
|
2041 (goto-char st)
|
|
2042 (backward-sexp))
|
|
2043 ) ;; cond
|
|
2044 ))
|
|
2045
|
|
2046 (defun verilog-forward-sexp ()
|
|
2047 (let ((reg)
|
|
2048 (md 2)
|
|
2049 (st (point)))
|
|
2050 (if (not (looking-at "\\<"))
|
|
2051 (forward-word -1))
|
|
2052 (cond
|
|
2053 ((verilog-skip-forward-comment-or-string)
|
|
2054 (verilog-forward-syntactic-ws)
|
|
2055 )
|
|
2056 ((looking-at verilog-beg-block-re-ordered);; begin|case|fork|class|table|specify|function|task|generate|covergroup|property|sequence|clocking
|
|
2057 (cond
|
|
2058 ((match-end 1) ; end
|
|
2059 ;; Search forward for matching begin
|
|
2060 (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
|
|
2061 ((match-end 2) ; endcase
|
|
2062 ;; Search forward for matching case
|
|
2063 (setq reg "\\(\\<randcase\\>\\|\\(\\<unique\\>\\s-+\\|\\<priority\\>\\s-+\\)?\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" )
|
|
2064 )
|
|
2065 ((match-end 3) ; join
|
|
2066 ;; Search forward for matching fork
|
|
2067 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
|
|
2068 ((match-end 4) ; endclass
|
|
2069 ;; Search forward for matching class
|
|
2070 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
|
|
2071 ((match-end 5) ; endtable
|
|
2072 ;; Search forward for matching table
|
|
2073 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
|
|
2074 ((match-end 6) ; endspecify
|
|
2075 ;; Search forward for matching specify
|
|
2076 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
|
|
2077 ((match-end 7) ; endfunction
|
|
2078 ;; Search forward for matching function
|
|
2079 (setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
|
|
2080 ((match-end 8) ; endtask
|
|
2081 ;; Search forward for matching task
|
|
2082 (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" ))
|
|
2083 ((match-end 9) ; endgenerate
|
|
2084 ;; Search forward for matching generate
|
|
2085 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
|
|
2086 ((match-end 10) ; endgroup
|
|
2087 ;; Search forward for matching covergroup
|
|
2088 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
|
|
2089 ((match-end 11) ; endproperty
|
|
2090 ;; Search forward for matching property
|
|
2091 (setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" ))
|
|
2092 ((match-end 12) ; endsequence
|
|
2093 ;; Search forward for matching sequence
|
|
2094 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" )
|
|
2095 (setq md 3) ; 3 to get to endsequence in the reg above
|
|
2096 )
|
|
2097 ((match-end 13) ; endclocking
|
|
2098 ;; Search forward for matching clocking
|
|
2099 (setq reg "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)" ))
|
|
2100 )
|
|
2101 (if (forward-word 1)
|
|
2102 (catch 'skip
|
|
2103 (let ((nest 1))
|
|
2104 (while (verilog-re-search-forward reg nil 'move)
|
|
2105 (cond
|
|
2106 ((match-end md) ; the closer in reg, so we are climbing out
|
|
2107 (setq nest (1- nest))
|
|
2108 (if (= 0 nest) ; we are out!
|
|
2109 (throw 'skip 1)))
|
|
2110 ((match-end 1) ; the opener in reg, so we are deeper now
|
|
2111 (setq nest (1+ nest)))))
|
|
2112 )))
|
|
2113 )
|
|
2114 ((looking-at (concat
|
|
2115 "\\(\\<\\(macro\\)?module\\>\\)\\|"
|
|
2116 "\\(\\<primitive\\>\\)\\|"
|
|
2117 "\\(\\<class\\>\\)\\|"
|
|
2118 "\\(\\<program\\>\\)\\|"
|
|
2119 "\\(\\<interface\\>\\)\\|"
|
|
2120 "\\(\\<package\\>\\)"))
|
|
2121 (cond
|
|
2122 ((match-end 1)
|
|
2123 (verilog-re-search-forward "\\<endmodule\\>" nil 'move))
|
|
2124 ((match-end 2)
|
|
2125 (verilog-re-search-forward "\\<endprimitive\\>" nil 'move))
|
|
2126 ((match-end 3)
|
|
2127 (verilog-re-search-forward "\\<endclass\\>" nil 'move))
|
|
2128 ((match-end 4)
|
|
2129 (verilog-re-search-forward "\\<endprogram\\>" nil 'move))
|
|
2130 ((match-end 5)
|
|
2131 (verilog-re-search-forward "\\<endinterface\\>" nil 'move))
|
|
2132 ((match-end 6)
|
|
2133 (verilog-re-search-forward "\\<endpackage\\>" nil 'move))
|
|
2134 (t
|
|
2135 (goto-char st)
|
|
2136 (if (= (following-char) ?\) )
|
|
2137 (forward-char 1)
|
|
2138 (forward-sexp 1)))))
|
|
2139 (t
|
|
2140 (goto-char st)
|
|
2141 (if (= (following-char) ?\) )
|
|
2142 (forward-char 1)
|
|
2143 (forward-sexp 1)))
|
|
2144 ) ;; cond
|
|
2145 ))
|
|
2146
|
|
2147 (defun verilog-declaration-beg ()
|
|
2148 (verilog-re-search-backward verilog-declaration-re (bobp) t))
|
|
2149
|
|
2150 ;;
|
|
2151 ;; Macros
|
|
2152 ;;
|
|
2153
|
|
2154 (defsubst verilog-string-replace-matches (from-string to-string fixedcase literal string)
|
|
2155 "Replace occurrences of FROM-STRING with TO-STRING.
|
|
2156 FIXEDCASE and LITERAL as in `replace-match`. STRING is what to replace.
|
|
2157 The case (verilog-string-replace-matches \"o\" \"oo\" nil nil \"foobar\")
|
|
2158 will break, as the o's continuously replace. xa -> x works ok though."
|
|
2159 ;; Hopefully soon to a emacs built-in
|
|
2160 (let ((start 0))
|
|
2161 (while (string-match from-string string start)
|
|
2162 (setq string (replace-match to-string fixedcase literal string)
|
|
2163 start (min (length string) (match-end 0))))
|
|
2164 string))
|
|
2165
|
|
2166 (defsubst verilog-string-remove-spaces (string)
|
|
2167 "Remove spaces surrounding STRING."
|
|
2168 (save-match-data
|
|
2169 (setq string (verilog-string-replace-matches "^\\s-+" "" nil nil string))
|
|
2170 (setq string (verilog-string-replace-matches "\\s-+$" "" nil nil string))
|
|
2171 string))
|
|
2172
|
|
2173 (defsubst verilog-re-search-forward (REGEXP BOUND NOERROR)
|
|
2174 ; checkdoc-params: (REGEXP BOUND NOERROR)
|
|
2175 "Like `re-search-forward', but skips over match in comments or strings."
|
|
2176 (store-match-data '(nil nil))
|
|
2177 (while (and
|
|
2178 (re-search-forward REGEXP BOUND NOERROR)
|
|
2179 (and (verilog-skip-forward-comment-or-string)
|
|
2180 (progn
|
|
2181 (store-match-data '(nil nil))
|
|
2182 (if BOUND
|
|
2183 (< (point) BOUND)
|
|
2184 t)
|
|
2185 ))))
|
|
2186 (match-end 0))
|
|
2187
|
|
2188 (defsubst verilog-re-search-backward (REGEXP BOUND NOERROR)
|
|
2189 ; checkdoc-params: (REGEXP BOUND NOERROR)
|
|
2190 "Like `re-search-backward', but skips over match in comments or strings."
|
|
2191 (store-match-data '(nil nil))
|
|
2192 (while (and
|
|
2193 (re-search-backward REGEXP BOUND NOERROR)
|
|
2194 (and (verilog-skip-backward-comment-or-string)
|
|
2195 (progn
|
|
2196 (store-match-data '(nil nil))
|
|
2197 (if BOUND
|
|
2198 (> (point) BOUND)
|
|
2199 t)
|
|
2200 ))))
|
|
2201 (match-end 0))
|
|
2202
|
|
2203 (defsubst verilog-re-search-forward-quick (regexp bound noerror)
|
|
2204 "Like `verilog-re-search-forward', including use of REGEXP BOUND and NOERROR,
|
|
2205 but trashes match data and is faster for REGEXP that doesn't match often.
|
|
2206 This may at some point use text properties to ignore comments,
|
|
2207 so there may be a large up front penalty for the first search."
|
|
2208 (let (pt)
|
|
2209 (while (and (not pt)
|
|
2210 (re-search-forward regexp bound noerror))
|
|
2211 (if (not (verilog-inside-comment-p))
|
|
2212 (setq pt (match-end 0))))
|
|
2213 pt))
|
|
2214
|
|
2215 (defsubst verilog-re-search-backward-quick (regexp bound noerror)
|
|
2216 ; checkdoc-params: (REGEXP BOUND NOERROR)
|
|
2217 "Like `verilog-re-search-backward', including use of REGEXP BOUND and NOERROR,
|
|
2218 but trashes match data and is faster for REGEXP that doesn't match often.
|
|
2219 This may at some point use text properties to ignore comments,
|
|
2220 so there may be a large up front penalty for the first search."
|
|
2221 (let (pt)
|
|
2222 (while (and (not pt)
|
|
2223 (re-search-backward regexp bound noerror))
|
|
2224 (if (not (verilog-inside-comment-p))
|
|
2225 (setq pt (match-end 0))))
|
|
2226 pt))
|
|
2227
|
|
2228 (defsubst verilog-get-beg-of-line (&optional arg)
|
|
2229 (save-excursion
|
|
2230 (beginning-of-line arg)
|
|
2231 (point)))
|
|
2232
|
|
2233 (defsubst verilog-get-end-of-line (&optional arg)
|
|
2234 (save-excursion
|
|
2235 (end-of-line arg)
|
|
2236 (point)))
|
|
2237
|
|
2238 (defsubst verilog-within-string ()
|
|
2239 (save-excursion
|
|
2240 (nth 3 (parse-partial-sexp (verilog-get-beg-of-line) (point)))))
|
|
2241
|
|
2242 (require 'font-lock)
|
|
2243 (defvar verilog-need-fld 1)
|
|
2244 (defvar font-lock-defaults-alist nil) ;In case we are XEmacs
|
|
2245
|
|
2246 (defun verilog-font-lock-init ()
|
|
2247 "Initialize fontification."
|
|
2248 ;; highlight keywords and standardized types, attributes, enumeration
|
|
2249 ;; values, and subprograms
|
|
2250 (setq verilog-font-lock-keywords-3
|
|
2251 (append verilog-font-lock-keywords-2
|
|
2252 (when verilog-highlight-translate-off
|
|
2253 (list
|
|
2254 ;; Fontify things in translate off regions
|
|
2255 '(verilog-match-translate-off (0 'verilog-font-lock-translate-off-face prepend))
|
|
2256 ))
|
|
2257 )
|
|
2258 )
|
|
2259 (put 'verilog-mode 'font-lock-defaults
|
|
2260 '((verilog-font-lock-keywords
|
|
2261 verilog-font-lock-keywords-1
|
|
2262 verilog-font-lock-keywords-2
|
|
2263 verilog-font-lock-keywords-3
|
|
2264 )
|
|
2265 nil ;; nil means highlight strings & comments as well as keywords
|
|
2266 nil ;; nil means keywords must match case
|
|
2267 nil ;; syntax table handled elsewhere
|
|
2268 verilog-beg-of-defun ;; function to move to beginning of reasonable region to highlight
|
|
2269 ))
|
|
2270 (if verilog-need-fld
|
|
2271 (let ((verilog-mode-defaults
|
|
2272 '((verilog-font-lock-keywords
|
|
2273 verilog-font-lock-keywords-1
|
|
2274 verilog-font-lock-keywords-2
|
|
2275 verilog-font-lock-keywords-3
|
|
2276 )
|
|
2277 nil ;; nil means highlight strings & comments as well as keywords
|
|
2278 nil ;; nil means keywords must match case
|
|
2279 nil ;; syntax table handled elsewhere
|
|
2280 verilog-beg-of-defun ;; function to move to beginning of reasonable region to highlight
|
|
2281 )))
|
|
2282 (setq font-lock-defaults-alist
|
|
2283 (append
|
|
2284 font-lock-defaults-alist
|
|
2285 (list (cons 'verilog-mode verilog-mode-defaults))))
|
|
2286 (setq verilog-need-fld 0))))
|
|
2287
|
|
2288 ;; initialize fontification for Verilog Mode
|
|
2289 (verilog-font-lock-init)
|
|
2290 ;; start up message
|
|
2291 (defconst verilog-startup-message-lines
|
|
2292 '("Please use \\[verilog-submit-bug-report] to report bugs."
|
|
2293 "Visit http://www.verilog.com to check for updates"
|
|
2294 ))
|
|
2295 (defconst verilog-startup-message-displayed t)
|
|
2296 (defun verilog-display-startup-message ()
|
|
2297 (if (not verilog-startup-message-displayed)
|
|
2298 (if (sit-for 5)
|
|
2299 (let ((lines verilog-startup-message-lines))
|
|
2300 (message "verilog-mode version %s, released %s; type \\[describe-mode] for help"
|
|
2301 verilog-mode-version verilog-mode-release-date)
|
|
2302 (setq verilog-startup-message-displayed t)
|
|
2303 (while (and (sit-for 4) lines)
|
|
2304 (message (substitute-command-keys (car lines)))
|
|
2305 (setq lines (cdr lines)))))
|
|
2306 (message "")))
|
|
2307 ;;
|
|
2308 ;;
|
|
2309 ;; Mode
|
|
2310 ;;
|
|
2311 (defvar verilog-which-tool 1)
|
79546
|
2312 ;;;###autoload
|
79545
|
2313 (defun verilog-mode ()
|
|
2314 "Major mode for editing Verilog code.
|
|
2315 \\<verilog-mode-map>
|
|
2316 See \\[describe-function] verilog-auto (\\[verilog-auto]) for details on how
|
|
2317 AUTOs can improve coding efficiency.
|
|
2318
|
|
2319 Use \\[verilog-faq] for a pointer to frequently asked questions.
|
|
2320
|
|
2321 NEWLINE, TAB indents for Verilog code.
|
|
2322 Delete converts tabs to spaces as it moves back.
|
|
2323
|
|
2324 Supports highlighting.
|
|
2325
|
|
2326 Turning on Verilog mode calls the value of the variable `verilog-mode-hook'
|
|
2327 with no args, if that value is non-nil.
|
|
2328
|
|
2329 Variables controlling indentation/edit style:
|
|
2330
|
|
2331 variable `verilog-indent-level' (default 3)
|
|
2332 Indentation of Verilog statements with respect to containing block.
|
|
2333 `verilog-indent-level-module' (default 3)
|
|
2334 Absolute indentation of Module level Verilog statements.
|
|
2335 Set to 0 to get initial and always statements lined up
|
|
2336 on the left side of your screen.
|
|
2337 `verilog-indent-level-declaration' (default 3)
|
|
2338 Indentation of declarations with respect to containing block.
|
|
2339 Set to 0 to get them list right under containing block.
|
|
2340 `verilog-indent-level-behavioral' (default 3)
|
|
2341 Indentation of first begin in a task or function block
|
|
2342 Set to 0 to get such code to lined up underneath the task or function keyword
|
|
2343 `verilog-indent-level-directive' (default 1)
|
|
2344 Indentation of `ifdef/`endif blocks
|
|
2345 `verilog-cexp-indent' (default 1)
|
|
2346 Indentation of Verilog statements broken across lines i.e.:
|
|
2347 if (a)
|
|
2348 begin
|
|
2349 `verilog-case-indent' (default 2)
|
|
2350 Indentation for case statements.
|
|
2351 `verilog-auto-newline' (default nil)
|
|
2352 Non-nil means automatically newline after semicolons and the punctuation
|
|
2353 mark after an end.
|
|
2354 `verilog-auto-indent-on-newline' (default t)
|
|
2355 Non-nil means automatically indent line after newline
|
|
2356 `verilog-tab-always-indent' (default t)
|
|
2357 Non-nil means TAB in Verilog mode should always reindent the current line,
|
|
2358 regardless of where in the line point is when the TAB command is used.
|
|
2359 `verilog-indent-begin-after-if' (default t)
|
|
2360 Non-nil means to indent begin statements following a preceding
|
|
2361 if, else, while, for and repeat statements, if any. otherwise,
|
|
2362 the begin is lined up with the preceding token. If t, you get:
|
|
2363 if (a)
|
|
2364 begin // amount of indent based on `verilog-cexp-indent'
|
|
2365 otherwise you get:
|
|
2366 if (a)
|
|
2367 begin
|
|
2368 `verilog-auto-endcomments' (default t)
|
|
2369 Non-nil means a comment /* ... */ is set after the ends which ends
|
|
2370 cases, tasks, functions and modules.
|
|
2371 The type and name of the object will be set between the braces.
|
|
2372 `verilog-minimum-comment-distance' (default 10)
|
|
2373 Minimum distance (in lines) between begin and end required before a comment
|
|
2374 will be inserted. Setting this variable to zero results in every
|
|
2375 end acquiring a comment; the default avoids too many redundant
|
|
2376 comments in tight quarters.
|
|
2377 `verilog-auto-lineup' (default `(all))
|
|
2378 List of contexts where auto lineup of code should be done.
|
|
2379
|
|
2380 Variables controlling other actions:
|
|
2381
|
|
2382 `verilog-linter' (default surelint)
|
|
2383 Unix program to call to run the lint checker. This is the default
|
|
2384 command for \\[compile-command] and \\[verilog-auto-save-compile].
|
|
2385
|
|
2386 See \\[customize] for the complete list of variables.
|
|
2387
|
|
2388 AUTO expansion functions are, in part:
|
|
2389
|
|
2390 \\[verilog-auto] Expand AUTO statements.
|
|
2391 \\[verilog-delete-auto] Remove the AUTOs.
|
|
2392 \\[verilog-inject-auto] Insert AUTOs for the first time.
|
|
2393
|
|
2394 Some other functions are:
|
|
2395
|
|
2396 \\[verilog-complete-word] Complete word with appropriate possibilities.
|
|
2397 \\[verilog-mark-defun] Mark function.
|
|
2398 \\[verilog-beg-of-defun] Move to beginning of current function.
|
|
2399 \\[verilog-end-of-defun] Move to end of current function.
|
|
2400 \\[verilog-label-be] Label matching begin ... end, fork ... join, etc statements.
|
|
2401
|
|
2402 \\[verilog-comment-region] Put marked area in a comment.
|
|
2403 \\[verilog-uncomment-region] Uncomment an area commented with \\[verilog-comment-region].
|
|
2404 \\[verilog-insert-block] Insert begin ... end;.
|
|
2405 \\[verilog-star-comment] Insert /* ... */.
|
|
2406
|
|
2407 \\[verilog-sk-always] Insert a always @(AS) begin .. end block.
|
|
2408 \\[verilog-sk-begin] Insert a begin .. end block.
|
|
2409 \\[verilog-sk-case] Insert a case block, prompting for details.
|
|
2410 \\[verilog-sk-for] Insert a for (...) begin .. end block, prompting for details.
|
|
2411 \\[verilog-sk-generate] Insert a generate .. endgenerate block.
|
|
2412 \\[verilog-sk-header] Insert a nice header block at the top of file.
|
|
2413 \\[verilog-sk-initial] Insert an initial begin .. end block.
|
|
2414 \\[verilog-sk-fork] Insert a fork begin .. end .. join block.
|
|
2415 \\[verilog-sk-module] Insert a module .. (/*AUTOARG*/);.. endmodule block.
|
|
2416 \\[verilog-sk-primitive] Insert a primitive .. (.. );.. endprimitive block.
|
|
2417 \\[verilog-sk-repeat] Insert a repeat (..) begin .. end block.
|
|
2418 \\[verilog-sk-specify] Insert a specify .. endspecify block.
|
|
2419 \\[verilog-sk-task] Insert a task .. begin .. end endtask block.
|
|
2420 \\[verilog-sk-while] Insert a while (...) begin .. end block, prompting for details.
|
|
2421 \\[verilog-sk-casex] Insert a casex (...) item: begin.. end endcase block, prompting for details.
|
|
2422 \\[verilog-sk-casez] Insert a casez (...) item: begin.. end endcase block, prompting for details.
|
|
2423 \\[verilog-sk-if] Insert an if (..) begin .. end block.
|
|
2424 \\[verilog-sk-else-if] Insert an else if (..) begin .. end block.
|
|
2425 \\[verilog-sk-comment] Insert a comment block.
|
|
2426 \\[verilog-sk-assign] Insert an assign .. = ..; statement.
|
|
2427 \\[verilog-sk-function] Insert a function .. begin .. end endfunction block.
|
|
2428 \\[verilog-sk-input] Insert an input declaration, prompting for details.
|
|
2429 \\[verilog-sk-output] Insert an output declaration, prompting for details.
|
|
2430 \\[verilog-sk-state-machine] Insert a state machine definition, prompting for details.
|
|
2431 \\[verilog-sk-inout] Insert an inout declaration, prompting for details.
|
|
2432 \\[verilog-sk-wire] Insert a wire declaration, prompting for details.
|
|
2433 \\[verilog-sk-reg] Insert a register declaration, prompting for details.
|
|
2434 \\[verilog-sk-define-signal] Define signal under point as a register at the top of the module.
|
|
2435
|
|
2436 All key bindings can be seen in a Verilog-buffer with \\[describe-bindings].
|
|
2437 Key bindings specific to `verilog-mode-map' are:
|
|
2438
|
|
2439 \\{verilog-mode-map}"
|
|
2440 (interactive)
|
|
2441 (kill-all-local-variables)
|
|
2442 (use-local-map verilog-mode-map)
|
|
2443 (setq major-mode 'verilog-mode)
|
|
2444 (setq mode-name "Verilog")
|
|
2445 (setq local-abbrev-table verilog-mode-abbrev-table)
|
|
2446 (setq verilog-mode-syntax-table (make-syntax-table))
|
|
2447 (verilog-populate-syntax-table verilog-mode-syntax-table)
|
79546
|
2448 (set (make-local-variable 'beginning-of-defun-function)
|
|
2449 'verilog-beg-of-defun)
|
|
2450 (set (make-local-variable 'end-of-defun-function)
|
|
2451 'verilog-end-of-defun)
|
79545
|
2452 ;; add extra comment syntax
|
|
2453 (verilog-setup-dual-comments verilog-mode-syntax-table)
|
|
2454 (set-syntax-table verilog-mode-syntax-table)
|
|
2455 (make-local-variable 'indent-line-function)
|
|
2456 (setq indent-line-function 'verilog-indent-line-relative)
|
|
2457 (setq comment-indent-function 'verilog-comment-indent)
|
|
2458 (make-local-variable 'parse-sexp-ignore-comments)
|
|
2459 (setq parse-sexp-ignore-comments nil)
|
|
2460 (make-local-variable 'comment-start)
|
|
2461 (make-local-variable 'comment-end)
|
|
2462 (make-local-variable 'comment-multi-line)
|
|
2463 (make-local-variable 'comment-start-skip)
|
|
2464 (setq comment-start "// "
|
|
2465 comment-end ""
|
|
2466 comment-start-skip "/\\*+ *\\|// *"
|
|
2467 comment-multi-line nil)
|
|
2468 ;; Set up for compilation
|
|
2469 (setq verilog-which-tool 1)
|
|
2470 (setq verilog-tool 'verilog-linter)
|
|
2471 (verilog-set-compile-command)
|
|
2472 (when (boundp 'hack-local-variables-hook) ;; Also modify any file-local-variables
|
|
2473 (add-hook 'hack-local-variables-hook 'verilog-modify-compile-command t))
|
|
2474
|
|
2475 ;; Setting up menus
|
79546
|
2476 (when (featurep 'xemacs)
|
|
2477 (when (and current-menubar
|
|
2478 (not (assoc "Verilog" current-menubar)))
|
|
2479 ;; (set-buffer-menubar (copy-sequence current-menubar))
|
|
2480 (add-submenu nil verilog-xemacs-menu)
|
|
2481 (add-submenu nil verilog-stmt-menu)
|
|
2482 ))
|
79545
|
2483 ;; Stuff for GNU emacs
|
|
2484 (make-local-variable 'font-lock-defaults)
|
|
2485 ;;------------------------------------------------------------
|
|
2486 ;; now hook in 'verilog-colorize-include-files (eldo-mode.el&spice-mode.el)
|
|
2487 ;; all buffer local:
|
|
2488 (make-local-hook 'font-lock-mode-hook)
|
|
2489 (make-local-hook 'font-lock-after-fontify-buffer-hook); doesn't exist in emacs 20
|
|
2490 (add-hook 'font-lock-mode-hook 'verilog-colorize-include-files-buffer t t)
|
|
2491 (add-hook 'font-lock-after-fontify-buffer-hook 'verilog-colorize-include-files-buffer t t) ; not in emacs 20
|
|
2492 (make-local-hook 'after-change-functions)
|
|
2493 (add-hook 'after-change-functions 'verilog-colorize-include-files t t)
|
|
2494
|
|
2495 ;; Tell imenu how to handle verilog.
|
|
2496 (make-local-variable 'imenu-generic-expression)
|
|
2497 (setq imenu-generic-expression verilog-imenu-generic-expression)
|
|
2498 ;; hideshow support
|
|
2499 (unless (assq 'verilog-mode hs-special-modes-alist)
|
|
2500 (setq hs-special-modes-alist
|
|
2501 (cons '(verilog-mode-mode "\\<begin\\>" "\\<end\\>" nil
|
|
2502 verilog-forward-sexp-function)
|
|
2503 hs-special-modes-alist)))
|
|
2504 ;; Display version splash information.
|
|
2505 (verilog-display-startup-message)
|
|
2506
|
|
2507 ;; Stuff for autos
|
|
2508 (add-hook 'write-contents-hooks 'verilog-auto-save-check) ; already local
|
|
2509 ;; (verilog-auto-reeval-locals t) ; Save locals in case user changes them
|
|
2510 ;; (verilog-getopt-flags)
|
|
2511 (run-hooks 'verilog-mode-hook))
|
|
2512
|
|
2513
|
|
2514 ;;
|
|
2515 ;; Electric functions
|
|
2516 ;;
|
|
2517 (defun electric-verilog-terminate-line (&optional arg)
|
|
2518 "Terminate line and indent next line.
|
|
2519 With optional ARG, remove existing end of line comments."
|
|
2520 (interactive)
|
|
2521 ;; before that see if we are in a comment
|
|
2522 (let ((state
|
|
2523 (save-excursion
|
|
2524 (parse-partial-sexp (point-min) (point)))))
|
|
2525 (cond
|
|
2526 ((nth 7 state) ; Inside // comment
|
|
2527 (if (eolp)
|
|
2528 (progn
|
|
2529 (delete-horizontal-space)
|
|
2530 (newline))
|
|
2531 (progn
|
|
2532 (newline)
|
|
2533 (insert-string "// ")
|
|
2534 (beginning-of-line)))
|
|
2535 (verilog-indent-line))
|
|
2536 ((nth 4 state) ; Inside any comment (hence /**/)
|
|
2537 (newline)
|
|
2538 (verilog-more-comment))
|
|
2539 ((eolp)
|
|
2540 ;; First, check if current line should be indented
|
|
2541 (if (save-excursion
|
|
2542 (delete-horizontal-space)
|
|
2543 (beginning-of-line)
|
|
2544 (skip-chars-forward " \t")
|
|
2545 (if (looking-at verilog-auto-end-comment-lines-re)
|
|
2546 (let ((indent-str (verilog-indent-line)))
|
|
2547 ;; Maybe we should set some endcomments
|
|
2548 (if verilog-auto-endcomments
|
|
2549 (verilog-set-auto-endcomments indent-str arg))
|
|
2550 (end-of-line)
|
|
2551 (delete-horizontal-space)
|
|
2552 (if arg
|
|
2553 ()
|
|
2554 (newline))
|
|
2555 nil)
|
|
2556 (progn
|
|
2557 (end-of-line)
|
|
2558 (delete-horizontal-space)
|
|
2559 't
|
|
2560 )
|
|
2561 )
|
|
2562 )
|
|
2563 ;; see if we should line up assignments
|
|
2564 (progn
|
|
2565 (if (or (memq 'all verilog-auto-lineup)
|
|
2566 (memq 'assignments verilog-auto-lineup))
|
|
2567 (verilog-pretty-expr)
|
|
2568 )
|
|
2569 (newline)
|
|
2570 )
|
|
2571 (forward-line 1)
|
|
2572 )
|
|
2573 ;; Indent next line
|
|
2574 (if verilog-auto-indent-on-newline
|
|
2575 (verilog-indent-line))
|
|
2576 )
|
|
2577 (t
|
|
2578 (newline))
|
|
2579 )))
|
|
2580
|
|
2581 (defun electric-verilog-terminate-and-indent ()
|
|
2582 "Insert a newline and indent for the next statement."
|
|
2583 (interactive)
|
|
2584 (electric-verilog-terminate-line 1))
|
|
2585
|
|
2586 (defun electric-verilog-semi ()
|
|
2587 "Insert `;' character and reindent the line."
|
|
2588 (interactive)
|
|
2589 (insert last-command-char)
|
|
2590
|
|
2591 (if (or (verilog-in-comment-or-string-p)
|
|
2592 (verilog-in-escaped-name-p))
|
|
2593 ()
|
|
2594 (save-excursion
|
|
2595 (beginning-of-line)
|
|
2596 (verilog-forward-ws&directives)
|
|
2597 (verilog-indent-line)
|
|
2598 )
|
|
2599 (if (and verilog-auto-newline
|
|
2600 (not (verilog-parenthesis-depth)))
|
|
2601 (electric-verilog-terminate-line))))
|
|
2602
|
|
2603 (defun electric-verilog-semi-with-comment ()
|
|
2604 "Insert `;' character, reindent the line and indent for comment."
|
|
2605 (interactive)
|
|
2606 (insert "\;")
|
|
2607 (save-excursion
|
|
2608 (beginning-of-line)
|
|
2609 (verilog-indent-line))
|
|
2610 (indent-for-comment))
|
|
2611
|
|
2612 (defun electric-verilog-colon ()
|
|
2613 "Insert `:' and do all indentations except line indent on this line."
|
|
2614 (interactive)
|
|
2615 (insert last-command-char)
|
|
2616 ;; Do nothing if within string.
|
|
2617 (if (or
|
|
2618 (verilog-within-string)
|
|
2619 (not (verilog-in-case-region-p)))
|
|
2620 ()
|
|
2621 (save-excursion
|
|
2622 (let ((p (point))
|
|
2623 (lim (progn (verilog-beg-of-statement) (point))))
|
|
2624 (goto-char p)
|
|
2625 (verilog-backward-case-item lim)
|
|
2626 (verilog-indent-line)))
|
|
2627 ;; (let ((verilog-tab-always-indent nil))
|
|
2628 ;; (verilog-indent-line))
|
|
2629 ))
|
|
2630
|
|
2631 ;;(defun electric-verilog-equal ()
|
|
2632 ;; "Insert `=', and do indentation if within block."
|
|
2633 ;; (interactive)
|
|
2634 ;; (insert last-command-char)
|
|
2635 ;; Could auto line up expressions, but not yet
|
|
2636 ;; (if (eq (car (verilog-calculate-indent)) 'block)
|
|
2637 ;; (let ((verilog-tab-always-indent nil))
|
|
2638 ;; (verilog-indent-command)))
|
|
2639 ;; )
|
|
2640
|
|
2641 (defun electric-verilog-tick ()
|
|
2642 "Insert back-tick, and indent to column 0 if this is a CPP directive."
|
|
2643 (interactive)
|
|
2644 (insert last-command-char)
|
|
2645 (save-excursion
|
|
2646 (if (progn
|
|
2647 (beginning-of-line)
|
|
2648 (looking-at verilog-directive-re-1))
|
|
2649 (verilog-indent-line))))
|
|
2650
|
|
2651 (defun electric-verilog-tab ()
|
|
2652 "Function called when TAB is pressed in Verilog mode."
|
|
2653 (interactive)
|
|
2654 ;; If verilog-tab-always-indent, indent the beginning of the line.
|
|
2655 (if (or verilog-tab-always-indent
|
|
2656 (save-excursion
|
|
2657 (skip-chars-backward " \t")
|
|
2658 (bolp)))
|
|
2659 (let* ((oldpnt (point))
|
|
2660 (boi-point
|
|
2661 (save-excursion
|
|
2662 (beginning-of-line)
|
|
2663 (skip-chars-forward " \t")
|
|
2664 (verilog-indent-line)
|
|
2665 (back-to-indentation)
|
|
2666 (point))))
|
|
2667 (if (< (point) boi-point)
|
|
2668 (back-to-indentation)
|
|
2669 (cond ((not verilog-tab-to-comment))
|
|
2670 ((not (eolp))
|
|
2671 (end-of-line))
|
|
2672 (t
|
|
2673 (indent-for-comment)
|
|
2674 (when (and (eolp) (= oldpnt (point)))
|
|
2675 ; kill existing comment
|
|
2676 (beginning-of-line)
|
|
2677 (re-search-forward comment-start-skip oldpnt 'move)
|
|
2678 (goto-char (match-beginning 0))
|
|
2679 (skip-chars-backward " \t")
|
|
2680 (kill-region (point) oldpnt)
|
|
2681 ))))
|
|
2682 )
|
|
2683 (progn (insert "\t"))))
|
|
2684
|
|
2685
|
|
2686
|
|
2687 ;;
|
|
2688 ;; Interactive functions
|
|
2689 ;;
|
|
2690
|
|
2691 (defun verilog-indent-buffer ()
|
|
2692 "Indent-region the entire buffer as Verilog code.
|
|
2693 To call this from the command line, see \\[verilog-batch-indent]."
|
|
2694 (interactive)
|
|
2695 (verilog-mode)
|
|
2696 (indent-region (point-min) (point-max) nil))
|
|
2697
|
|
2698 (defun verilog-insert-block ()
|
|
2699 "Insert Verilog begin ... end; block in the code with right indentation."
|
|
2700 (interactive)
|
|
2701 (verilog-indent-line)
|
|
2702 (insert "begin")
|
|
2703 (electric-verilog-terminate-line)
|
|
2704 (save-excursion
|
|
2705 (electric-verilog-terminate-line)
|
|
2706 (insert "end")
|
|
2707 (beginning-of-line)
|
|
2708 (verilog-indent-line)))
|
|
2709
|
|
2710 (defun verilog-star-comment ()
|
|
2711 "Insert Verilog star comment at point."
|
|
2712 (interactive)
|
|
2713 (verilog-indent-line)
|
|
2714 (insert "/*")
|
|
2715 (save-excursion
|
|
2716 (newline)
|
|
2717 (insert " */"))
|
|
2718 (newline)
|
|
2719 (insert " * "))
|
|
2720
|
|
2721 (defun verilog-insert-indices (MAX)
|
|
2722 "Insert a set of indices at into the rectangle.
|
|
2723 The upper left corner is defined by the current point. Indices always
|
|
2724 begin with 0 and extend to the MAX - 1. If no prefix arg is given, the
|
|
2725 user is prompted for a value. The indices are surrounded by square brackets
|
79546
|
2726 \[]. For example, the following code with the point located after the first
|
79545
|
2727 'a' gives:
|
|
2728
|
|
2729 a = b a[ 0] = b
|
|
2730 a = b a[ 1] = b
|
|
2731 a = b a[ 2] = b
|
|
2732 a = b a[ 3] = b
|
|
2733 a = b ==> insert-indices ==> a[ 4] = b
|
|
2734 a = b a[ 5] = b
|
|
2735 a = b a[ 6] = b
|
|
2736 a = b a[ 7] = b
|
|
2737 a = b a[ 8] = b"
|
|
2738
|
|
2739 (interactive "NMAX?")
|
|
2740 (save-excursion
|
|
2741 (let ((n 0))
|
|
2742 (while (< n MAX)
|
|
2743 (save-excursion
|
|
2744 (insert (format "[%3d]" n)))
|
|
2745 (next-line 1)
|
|
2746 (setq n (1+ n))))))
|
|
2747
|
|
2748
|
|
2749 (defun verilog-generate-numbers (MAX)
|
|
2750 "Insert a set of generated numbers into a rectangle.
|
|
2751 The upper left corner is defined by point. The numbers are padded to three
|
|
2752 digits, starting with 000 and extending to (MAX - 1). If no prefix argument
|
|
2753 is supplied, then the user is prompted for the MAX number. consider the
|
|
2754 following code fragment:
|
|
2755
|
|
2756 buf buf buf buf000
|
|
2757 buf buf buf buf001
|
|
2758 buf buf buf buf002
|
|
2759 buf buf buf buf003
|
|
2760 buf buf ==> insert-indices ==> buf buf004
|
|
2761 buf buf buf buf005
|
|
2762 buf buf buf buf006
|
|
2763 buf buf buf buf007
|
|
2764 buf buf buf buf008"
|
|
2765
|
|
2766 (interactive "NMAX?")
|
|
2767 (save-excursion
|
|
2768 (let ((n 0))
|
|
2769 (while (< n MAX)
|
|
2770 (save-excursion
|
|
2771 (insert (format "%3.3d" n)))
|
|
2772 (next-line 1)
|
|
2773 (setq n (1+ n))))))
|
|
2774
|
|
2775 (defun verilog-mark-defun ()
|
|
2776 "Mark the current verilog function (or procedure).
|
|
2777 This puts the mark at the end, and point at the beginning."
|
|
2778 (interactive)
|
|
2779 (push-mark (point))
|
|
2780 (verilog-end-of-defun)
|
|
2781 (push-mark (point))
|
|
2782 (verilog-beg-of-defun)
|
|
2783 (zmacs-activate-region))
|
|
2784
|
|
2785 (defun verilog-comment-region (start end)
|
|
2786 ; checkdoc-params: (start end)
|
|
2787 "Put the region into a Verilog comment.
|
|
2788 The comments that are in this area are \"deformed\":
|
|
2789 `*)' becomes `!(*' and `}' becomes `!{'.
|
|
2790 These deformed comments are returned to normal if you use
|
|
2791 \\[verilog-uncomment-region] to undo the commenting.
|
|
2792
|
|
2793 The commented area starts with `verilog-exclude-str-start', and ends with
|
|
2794 `verilog-exclude-str-end'. But if you change these variables,
|
|
2795 \\[verilog-uncomment-region] won't recognize the comments."
|
|
2796 (interactive "r")
|
|
2797 (save-excursion
|
|
2798 ;; Insert start and endcomments
|
|
2799 (goto-char end)
|
|
2800 (if (and (save-excursion (skip-chars-forward " \t") (eolp))
|
|
2801 (not (save-excursion (skip-chars-backward " \t") (bolp))))
|
|
2802 (forward-line 1)
|
|
2803 (beginning-of-line))
|
|
2804 (insert verilog-exclude-str-end)
|
|
2805 (setq end (point))
|
|
2806 (newline)
|
|
2807 (goto-char start)
|
|
2808 (beginning-of-line)
|
|
2809 (insert verilog-exclude-str-start)
|
|
2810 (newline)
|
|
2811 ;; Replace end-comments within commented area
|
|
2812 (goto-char end)
|
|
2813 (save-excursion
|
|
2814 (while (re-search-backward "\\*/" start t)
|
|
2815 (replace-match "*-/" t t)))
|
|
2816 (save-excursion
|
|
2817 (let ((s+1 (1+ start)))
|
|
2818 (while (re-search-backward "/\\*" s+1 t)
|
|
2819 (replace-match "/-*" t t))))
|
|
2820 ))
|
|
2821
|
|
2822 (defun verilog-uncomment-region ()
|
|
2823 "Uncomment a commented area; change deformed comments back to normal.
|
|
2824 This command does nothing if the pointer is not in a commented
|
|
2825 area. See also `verilog-comment-region'."
|
|
2826 (interactive)
|
|
2827 (save-excursion
|
|
2828 (let ((start (point))
|
|
2829 (end (point)))
|
|
2830 ;; Find the boundaries of the comment
|
|
2831 (save-excursion
|
|
2832 (setq start (progn (search-backward verilog-exclude-str-start nil t)
|
|
2833 (point)))
|
|
2834 (setq end (progn (search-forward verilog-exclude-str-end nil t)
|
|
2835 (point))))
|
|
2836 ;; Check if we're really inside a comment
|
|
2837 (if (or (equal start (point)) (<= end (point)))
|
|
2838 (message "Not standing within commented area.")
|
|
2839 (progn
|
|
2840 ;; Remove endcomment
|
|
2841 (goto-char end)
|
|
2842 (beginning-of-line)
|
|
2843 (let ((pos (point)))
|
|
2844 (end-of-line)
|
|
2845 (delete-region pos (1+ (point))))
|
|
2846 ;; Change comments back to normal
|
|
2847 (save-excursion
|
|
2848 (while (re-search-backward "\\*-/" start t)
|
|
2849 (replace-match "*/" t t)))
|
|
2850 (save-excursion
|
|
2851 (while (re-search-backward "/-\\*" start t)
|
|
2852 (replace-match "/*" t t)))
|
|
2853 ;; Remove start comment
|
|
2854 (goto-char start)
|
|
2855 (beginning-of-line)
|
|
2856 (let ((pos (point)))
|
|
2857 (end-of-line)
|
|
2858 (delete-region pos (1+ (point)))))))))
|
|
2859
|
|
2860 (defun verilog-beg-of-defun ()
|
|
2861 "Move backward to the beginning of the current function or procedure."
|
|
2862 (interactive)
|
|
2863 (verilog-re-search-backward verilog-defun-re nil 'move))
|
|
2864
|
|
2865 (defun verilog-end-of-defun ()
|
|
2866 "Move forward to the end of the current function or procedure."
|
|
2867 (interactive)
|
|
2868 (verilog-re-search-forward verilog-end-defun-re nil 'move))
|
|
2869
|
|
2870 (defun verilog-get-beg-of-defun (&optional warn)
|
|
2871 (save-excursion
|
|
2872 (cond ((verilog-re-search-forward-quick verilog-defun-re nil t)
|
|
2873 (point))
|
|
2874 (t
|
|
2875 (error "%s: Can't find module beginning" (verilog-point-text))
|
|
2876 (point-max)))))
|
|
2877 (defun verilog-get-end-of-defun (&optional warn)
|
|
2878 (save-excursion
|
|
2879 (cond ((verilog-re-search-forward-quick verilog-end-defun-re nil t)
|
|
2880 (point))
|
|
2881 (t
|
|
2882 (error "%s: Can't find endmodule" (verilog-point-text))
|
|
2883 (point-max)))))
|
|
2884
|
|
2885 (defun verilog-label-be (&optional arg)
|
|
2886 "Label matching begin ... end, fork ... join and case ... endcase statements.
|
|
2887 With ARG, first kill any existing labels."
|
|
2888 (interactive)
|
|
2889 (let ((cnt 0)
|
|
2890 (oldpos (point))
|
|
2891 (b (progn
|
|
2892 (verilog-beg-of-defun)
|
|
2893 (point-marker)))
|
|
2894 (e (progn
|
|
2895 (verilog-end-of-defun)
|
|
2896 (point-marker)))
|
|
2897 )
|
|
2898 (goto-char (marker-position b))
|
|
2899 (if (> (- e b) 200)
|
|
2900 (message "Relabeling module..."))
|
|
2901 (while (and
|
|
2902 (> (marker-position e) (point))
|
|
2903 (verilog-re-search-forward
|
|
2904 (concat
|
|
2905 "\\<end\\(\\(function\\)\\|\\(task\\)\\|\\(module\\)\\|\\(primitive\\)\\|\\(interface\\)\\|\\(package\\)\\|\\(case\\)\\)?\\>"
|
|
2906 "\\|\\(`endif\\)\\|\\(`else\\)")
|
|
2907 nil 'move))
|
|
2908 (goto-char (match-beginning 0))
|
|
2909 (let ((indent-str (verilog-indent-line)))
|
|
2910 (verilog-set-auto-endcomments indent-str 't)
|
|
2911 (end-of-line)
|
|
2912 (delete-horizontal-space)
|
|
2913 )
|
|
2914 (setq cnt (1+ cnt))
|
|
2915 (if (= 9 (% cnt 10))
|
|
2916 (message "%d..." cnt))
|
|
2917 )
|
|
2918 (goto-char oldpos)
|
|
2919 (if (or
|
|
2920 (> (- e b) 200)
|
|
2921 (> cnt 20))
|
|
2922 (message "%d lines auto commented" cnt))
|
|
2923 ))
|
|
2924
|
|
2925 (defun verilog-beg-of-statement ()
|
|
2926 "Move backward to beginning of statement."
|
|
2927 (interactive)
|
|
2928 ;; Move back token by token until we see the end
|
|
2929 ;; of some ealier line.
|
|
2930 (while
|
|
2931 ;; If the current point does not begin a new
|
|
2932 ;; statement, as in the character ahead of us is a ';', or SOF
|
|
2933 ;; or the string after us unambiguosly starts a statement,
|
|
2934 ;; or the token before us unambiguously ends a statement,
|
|
2935 ;; then move back a token and test again.
|
|
2936 (not (or
|
|
2937 (bolp)
|
|
2938 (= (preceding-char) ?\;)
|
|
2939 (not (or
|
|
2940 (looking-at "\\<")
|
|
2941 (forward-word -1)))
|
|
2942 (and
|
|
2943 (looking-at verilog-extended-complete-re)
|
|
2944 (not (save-excursion
|
|
2945 (verilog-backward-token)
|
|
2946 (looking-at verilog-extended-complete-re)))
|
|
2947 )
|
|
2948 (looking-at verilog-basic-complete-re)
|
|
2949 (save-excursion
|
|
2950 (verilog-backward-token)
|
|
2951 (or
|
|
2952 (looking-at verilog-end-block-re)
|
|
2953 (looking-at verilog-preprocessor-re)))
|
|
2954 ))
|
|
2955 (verilog-backward-syntactic-ws)
|
|
2956 (verilog-backward-token))
|
|
2957 ;; Now point is where the previous line ended.
|
|
2958 (verilog-forward-syntactic-ws))
|
|
2959
|
|
2960 (defun verilog-beg-of-statement-1 ()
|
|
2961 "Move backward to beginning of statement."
|
|
2962 (interactive)
|
|
2963 (let ((pt (point)))
|
|
2964
|
|
2965 (while (and (not (looking-at verilog-complete-reg))
|
|
2966 (setq pt (point))
|
|
2967 (verilog-backward-token)
|
|
2968 (not (looking-at verilog-complete-reg))
|
|
2969 (verilog-backward-syntactic-ws)
|
|
2970 (setq pt (point))
|
|
2971 (not (bolp))
|
|
2972 (not (= (preceding-char) ?\;))))
|
|
2973 (goto-char pt)
|
|
2974 (verilog-forward-ws&directives)))
|
|
2975
|
|
2976 (defun verilog-end-of-statement ()
|
|
2977 "Move forward to end of current statement."
|
|
2978 (interactive)
|
|
2979 (let ((nest 0) pos)
|
|
2980 (or (looking-at verilog-beg-block-re)
|
|
2981 ;; Skip to end of statement
|
|
2982 (setq pos (catch 'found
|
|
2983 (while t
|
|
2984 (forward-sexp 1)
|
|
2985 (verilog-skip-forward-comment-or-string)
|
|
2986 (cond ((looking-at "[ \t]*;")
|
|
2987 (skip-chars-forward "^;")
|
|
2988 (forward-char 1)
|
|
2989 (throw 'found (point)))
|
|
2990 ((save-excursion
|
|
2991 (forward-sexp -1)
|
|
2992 (looking-at verilog-beg-block-re))
|
|
2993 (goto-char (match-beginning 0))
|
|
2994 (throw 'found nil))
|
|
2995 ((looking-at "[ \t]*)")
|
79546
|
2996 (throw 'found (point)))
|
79545
|
2997 ((eobp)
|
|
2998 (throw 'found (point))))))))
|
|
2999 (if (not pos)
|
|
3000 ;; Skip a whole block
|
|
3001 (catch 'found
|
|
3002 (while t
|
|
3003 (verilog-re-search-forward verilog-end-statement-re nil 'move)
|
|
3004 (setq nest (if (match-end 1)
|
|
3005 (1+ nest)
|
|
3006 (1- nest)))
|
|
3007 (cond ((eobp)
|
|
3008 (throw 'found (point)))
|
|
3009 ((= 0 nest)
|
|
3010 (throw 'found (verilog-end-of-statement))))))
|
|
3011 pos)))
|
|
3012
|
|
3013 (defun verilog-in-case-region-p ()
|
|
3014 "Return TRUE if in a case region;
|
|
3015 more specifically, point @ in the line foo : @ begin"
|
|
3016 (interactive)
|
|
3017 (save-excursion
|
|
3018 (if (and
|
|
3019 (progn (verilog-forward-syntactic-ws)
|
|
3020 (looking-at "\\<begin\\>"))
|
|
3021 (progn (verilog-backward-syntactic-ws)
|
|
3022 (= (preceding-char) ?\:)))
|
|
3023 (catch 'found
|
|
3024 (let ((nest 1))
|
|
3025 (while t
|
|
3026 (verilog-re-search-backward
|
|
3027 (concat "\\(\\<module\\>\\)\\|\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|"
|
|
3028 "\\(\\<endcase\\>\\)\\>")
|
|
3029 nil 'move)
|
|
3030 (cond
|
|
3031 ((match-end 3)
|
|
3032 (setq nest (1+ nest)))
|
|
3033 ((match-end 2)
|
|
3034 (if (= nest 1)
|
|
3035 (throw 'found 1))
|
|
3036 (setq nest (1- nest)))
|
|
3037 (t
|
|
3038 (throw 'found (= nest 0)))
|
|
3039 ))))
|
|
3040 nil)))
|
|
3041 (defun verilog-in-struct-region-p ()
|
|
3042 "Return TRUE if in a struct region;
|
|
3043 more specifically, in a list after a struct|union keyword"
|
|
3044 (interactive)
|
|
3045 (save-excursion
|
|
3046 (let* ((state (parse-partial-sexp (point-min) (point)))
|
|
3047 (depth (nth 0 state)))
|
|
3048 (if depth
|
|
3049 (progn (backward-up-list depth)
|
|
3050 (verilog-beg-of-statement)
|
|
3051 (looking-at "\\<typedef\\>?\\s-*\\<struct\\|union\\>")
|
|
3052 )
|
|
3053 )
|
|
3054 )
|
|
3055 )
|
|
3056 )
|
|
3057
|
|
3058 (defun verilog-in-generate-region-p ()
|
|
3059 "Return TRUE if in a generate region;
|
|
3060 more specifically, after a generate and before an endgenerate"
|
|
3061 (interactive)
|
|
3062 (let ((lim (save-excursion (verilog-beg-of-defun) (point)))
|
|
3063 (nest 1)
|
|
3064 )
|
|
3065 (save-excursion
|
|
3066 (while (and
|
|
3067 (/= nest 0)
|
|
3068 (verilog-re-search-backward "\\<\\(generate\\)\\|\\(endgenerate\\)\\>" lim 'move)
|
|
3069 (cond
|
|
3070 ((match-end 1) ; generate
|
|
3071 (setq nest (1- nest)))
|
|
3072 ((match-end 2) ; endgenerate
|
|
3073 (setq nest (1+ nest)))
|
|
3074 ))
|
|
3075 ))
|
|
3076 (= nest 0) )) ; return nest
|
|
3077
|
|
3078 (defun verilog-in-fork-region-p ()
|
|
3079 "Return true if between a fork and join."
|
|
3080 (interactive)
|
|
3081 (let ((lim (save-excursion (verilog-beg-of-defun) (point)))
|
|
3082 (nest 1)
|
|
3083 )
|
|
3084 (save-excursion
|
|
3085 (while (and
|
|
3086 (/= nest 0)
|
|
3087 (verilog-re-search-backward "\\<\\(fork\\)\\|\\(join\\(_any\\|_none\\)?\\)\\>" lim 'move)
|
|
3088 (cond
|
|
3089 ((match-end 1) ; fork
|
|
3090 (setq nest (1- nest)))
|
|
3091 ((match-end 2) ; join
|
|
3092 (setq nest (1+ nest)))
|
|
3093 ))
|
|
3094 ))
|
|
3095 (= nest 0) )) ; return nest
|
|
3096
|
|
3097 (defun verilog-backward-case-item (lim)
|
|
3098 "Skip backward to nearest enclosing case item.
|
|
3099 Limit search to point LIM."
|
|
3100 (interactive)
|
|
3101 (let ((str 'nil)
|
|
3102 (lim1
|
|
3103 (progn
|
|
3104 (save-excursion
|
|
3105 (verilog-re-search-backward verilog-endcomment-reason-re
|
|
3106 lim 'move)
|
|
3107 (point)))))
|
|
3108 ;; Try to find the real :
|
|
3109 (if (save-excursion (search-backward ":" lim1 t))
|
|
3110 (let ((colon 0)
|
|
3111 b e )
|
|
3112 (while
|
|
3113 (and
|
|
3114 (< colon 1)
|
|
3115 (verilog-re-search-backward "\\(\\[\\)\\|\\(\\]\\)\\|\\(:\\)"
|
|
3116 lim1 'move))
|
|
3117 (cond
|
|
3118 ((match-end 1) ;; [
|
|
3119 (setq colon (1+ colon))
|
|
3120 (if (>= colon 0)
|
|
3121 (error "%s: unbalanced [" (verilog-point-text))))
|
|
3122 ((match-end 2) ;; ]
|
|
3123 (setq colon (1- colon)))
|
|
3124
|
|
3125 ((match-end 3) ;; :
|
|
3126 (setq colon (1+ colon)))
|
|
3127 ))
|
|
3128 ;; Skip back to beginning of case item
|
|
3129 (skip-chars-backward "\t ")
|
|
3130 (verilog-skip-backward-comment-or-string)
|
|
3131 (setq e (point))
|
|
3132 (setq b
|
|
3133 (progn
|
|
3134 (if
|
|
3135 (verilog-re-search-backward
|
|
3136 "\\<\\(case[zx]?\\)\\>\\|;\\|\\<end\\>" nil 'move)
|
|
3137 (progn
|
|
3138 (cond
|
|
3139 ((match-end 1)
|
|
3140 (goto-char (match-end 1))
|
|
3141 (verilog-forward-ws&directives)
|
|
3142 (if (looking-at "(")
|
|
3143 (progn
|
|
3144 (forward-sexp)
|
|
3145 (verilog-forward-ws&directives)))
|
|
3146 (point))
|
|
3147 (t
|
|
3148 (goto-char (match-end 0))
|
|
3149 (verilog-forward-ws&directives)
|
|
3150 (point))
|
|
3151 ))
|
|
3152 (error "Malformed case item")
|
|
3153 )))
|
|
3154 (setq str (buffer-substring b e))
|
|
3155 (if
|
|
3156 (setq e
|
|
3157 (string-match
|
|
3158 "[ \t]*\\(\\(\n\\)\\|\\(//\\)\\|\\(/\\*\\)\\)" str))
|
|
3159 (setq str (concat (substring str 0 e) "...")))
|
|
3160 str)
|
|
3161 'nil)))
|
|
3162
|
|
3163
|
|
3164 ;;
|
|
3165 ;; Other functions
|
|
3166 ;;
|
|
3167
|
|
3168 (defun kill-existing-comment ()
|
|
3169 "Kill auto comment on this line."
|
|
3170 (save-excursion
|
|
3171 (let* (
|
|
3172 (e (progn
|
|
3173 (end-of-line)
|
|
3174 (point)))
|
|
3175 (b (progn
|
|
3176 (beginning-of-line)
|
|
3177 (search-forward "//" e t))))
|
|
3178 (if b
|
|
3179 (delete-region (- b 2) e)))))
|
|
3180
|
|
3181 (defconst verilog-directive-nest-re
|
|
3182 (concat "\\(`else\\>\\)\\|"
|
|
3183 "\\(`endif\\>\\)\\|"
|
|
3184 "\\(`if\\>\\)\\|"
|
|
3185 "\\(`ifdef\\>\\)\\|"
|
|
3186 "\\(`ifndef\\>\\)"))
|
|
3187 (defun verilog-set-auto-endcomments (indent-str kill-existing-comment)
|
|
3188 "Add ending comment with given INDENT-STR.
|
|
3189 With KILL-EXISTING-COMMENT, remove what was there before.
|
|
3190 Insert `// case: 7 ' or `// NAME ' on this line if appropriate.
|
|
3191 Insert `// case expr ' if this line ends a case block.
|
|
3192 Insert `// ifdef FOO ' if this line ends code conditional on FOO.
|
|
3193 Insert `// NAME ' if this line ends a function, task, module, primitive or interface named NAME."
|
|
3194 (save-excursion
|
|
3195 (cond
|
|
3196 (; Comment close preprocessor directives
|
|
3197 (and
|
|
3198 (looking-at "\\(`endif\\)\\|\\(`else\\)")
|
|
3199 (or kill-existing-comment
|
|
3200 (not (save-excursion
|
|
3201 (end-of-line)
|
|
3202 (search-backward "//" (verilog-get-beg-of-line) t)))))
|
|
3203 (let ((nest 1) b e
|
|
3204 m
|
|
3205 (else (if (match-end 2) "!" " "))
|
|
3206 )
|
|
3207 (end-of-line)
|
|
3208 (if kill-existing-comment
|
|
3209 (kill-existing-comment))
|
|
3210 (delete-horizontal-space)
|
|
3211 (save-excursion
|
|
3212 (backward-sexp 1)
|
|
3213 (while (and (/= nest 0)
|
|
3214 (verilog-re-search-backward verilog-directive-nest-re nil 'move))
|
|
3215 (cond
|
|
3216 ((match-end 1) ; `else
|
|
3217 (if (= nest 1)
|
|
3218 (setq else "!")))
|
|
3219 ((match-end 2) ; `endif
|
|
3220 (setq nest (1+ nest)))
|
|
3221 ((match-end 3) ; `if
|
|
3222 (setq nest (1- nest)))
|
|
3223 ((match-end 4) ; `ifdef
|
|
3224 (setq nest (1- nest)))
|
|
3225 ((match-end 5) ; `ifndef
|
|
3226 (setq nest (1- nest)))
|
|
3227 ))
|
|
3228 (if (match-end 0)
|
|
3229 (setq
|
|
3230 m (buffer-substring
|
|
3231 (match-beginning 0)
|
|
3232 (match-end 0))
|
|
3233 b (progn
|
|
3234 (skip-chars-forward "^ \t")
|
|
3235 (verilog-forward-syntactic-ws)
|
|
3236 (point))
|
|
3237 e (progn
|
|
3238 (skip-chars-forward "a-zA-Z0-9_")
|
|
3239 (point)
|
|
3240 ))))
|
|
3241 (if b
|
|
3242 (if (> (count-lines (point) b) verilog-minimum-comment-distance)
|
|
3243 (insert (concat " // " else m " " (buffer-substring b e))))
|
|
3244 (progn
|
|
3245 (insert " // unmatched `else or `endif")
|
|
3246 (ding 't))
|
|
3247 )))
|
|
3248
|
|
3249 (; Comment close case/class/function/task/module and named block
|
|
3250 (and (looking-at "\\<end")
|
|
3251 (or kill-existing-comment
|
|
3252 (not (save-excursion
|
|
3253 (end-of-line)
|
|
3254 (search-backward "//" (verilog-get-beg-of-line) t)))))
|
|
3255 (let ((type (car indent-str)))
|
|
3256 (unless (eq type 'declaration)
|
|
3257 (unless (looking-at (concat "\\(" verilog-end-block-ordered-re "\\)[ \t]*:")) ;; ignore named ends
|
|
3258 (if (looking-at verilog-end-block-ordered-re)
|
|
3259 (cond
|
|
3260 (;- This is a case block; search back for the start of this case
|
|
3261 (match-end 1) ;; of verilog-end-block-ordered-re
|
|
3262
|
|
3263 (let ((err 't)
|
|
3264 (str "UNMATCHED!!"))
|
|
3265 (save-excursion
|
|
3266 (verilog-leap-to-head)
|
|
3267 (cond
|
|
3268 ((looking-at "\\<randcase\\>")
|
|
3269 (setq str "randcase")
|
|
3270 (setq err nil)
|
|
3271 )
|
|
3272 ((match-end 0)
|
|
3273 (goto-char (match-end 1))
|
|
3274 (if nil
|
|
3275 (let (s f)
|
|
3276 (setq s (match-beginning 1))
|
|
3277 (setq f (progn (end-of-line)
|
|
3278 (point)))
|
|
3279 (setq str (buffer-substring s f)))
|
|
3280 (setq err nil))
|
|
3281 (setq str (concat (buffer-substring (match-beginning 1) (match-end 1))
|
|
3282 " "
|
|
3283 (verilog-get-expr))))))
|
|
3284 (end-of-line)
|
|
3285 (if kill-existing-comment
|
|
3286 (kill-existing-comment))
|
|
3287 (delete-horizontal-space)
|
|
3288 (insert (concat " // " str ))
|
|
3289 (if err (ding 't))
|
|
3290 ))
|
|
3291
|
|
3292 (;- This is a begin..end block
|
|
3293 (match-end 2) ;; of verilog-end-block-ordered-re
|
|
3294 (let ((str " // UNMATCHED !!")
|
|
3295 (err 't)
|
|
3296 (here (point))
|
|
3297 there
|
|
3298 cntx
|
|
3299 )
|
|
3300 (save-excursion
|
|
3301 (verilog-leap-to-head)
|
|
3302 (setq there (point))
|
|
3303 (if (not (match-end 0))
|
|
3304 (progn
|
|
3305 (goto-char here)
|
|
3306 (end-of-line)
|
|
3307 (if kill-existing-comment
|
|
3308 (kill-existing-comment))
|
|
3309 (delete-horizontal-space)
|
|
3310 (insert str)
|
|
3311 (ding 't)
|
|
3312 )
|
|
3313 (let ((lim
|
|
3314 (save-excursion (verilog-beg-of-defun) (point)))
|
|
3315 (here (point))
|
|
3316 )
|
|
3317 (cond
|
|
3318 (;-- handle named block differently
|
|
3319 (looking-at verilog-named-block-re)
|
|
3320 (search-forward ":")
|
|
3321 (setq there (point))
|
|
3322 (setq str (verilog-get-expr))
|
|
3323 (setq err nil)
|
|
3324 (setq str (concat " // block: " str )))
|
|
3325
|
|
3326 ((verilog-in-case-region-p) ;-- handle case item differently
|
|
3327 (goto-char here)
|
|
3328 (setq str (verilog-backward-case-item lim))
|
|
3329 (setq there (point))
|
|
3330 (setq err nil)
|
|
3331 (setq str (concat " // case: " str )))
|
|
3332
|
|
3333 (;- try to find "reason" for this begin
|
|
3334 (cond
|
|
3335 (;
|
|
3336 (eq here (progn
|
|
3337 (verilog-backward-token)
|
|
3338 (verilog-beg-of-statement-1)
|
|
3339 (point)))
|
|
3340 (setq err nil)
|
|
3341 (setq str ""))
|
|
3342 ((looking-at verilog-endcomment-reason-re)
|
|
3343 (setq there (match-end 0))
|
|
3344 (setq cntx (concat
|
|
3345 (buffer-substring (match-beginning 0) (match-end 0)) " "))
|
|
3346 (cond
|
|
3347 (;- begin
|
|
3348 (match-end 2)
|
|
3349 (setq err nil)
|
|
3350 (save-excursion
|
|
3351 (if (and (verilog-continued-line)
|
|
3352 (looking-at "\\<repeat\\>\\|\\<wait\\>\\|\\<always\\>"))
|
|
3353 (progn
|
|
3354 (goto-char (match-end 0))
|
|
3355 (setq there (point))
|
|
3356 (setq str
|
|
3357 (concat " // "
|
|
3358 (buffer-substring (match-beginning 0) (match-end 0)) " "
|
|
3359 (verilog-get-expr))))
|
|
3360 (setq str ""))))
|
|
3361
|
|
3362 (;- else
|
|
3363 (match-end 4)
|
|
3364 (let ((nest 0)
|
|
3365 ( reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)")
|
|
3366 )
|
|
3367 (catch 'skip
|
|
3368 (while (verilog-re-search-backward reg nil 'move)
|
|
3369 (cond
|
|
3370 ((match-end 1) ; begin
|
|
3371 (setq nest (1- nest)))
|
|
3372 ((match-end 2) ; end
|
|
3373 (setq nest (1+ nest)))
|
|
3374 ((match-end 3)
|
|
3375 (if (= 0 nest)
|
|
3376 (progn
|
|
3377 (goto-char (match-end 0))
|
|
3378 (setq there (point))
|
|
3379 (setq err nil)
|
|
3380 (setq str (verilog-get-expr))
|
|
3381 (setq str (concat " // else: !if" str ))
|
|
3382 (throw 'skip 1))
|
|
3383 )))
|
|
3384 ))))
|
|
3385
|
|
3386 (;- end else
|
|
3387 (match-end 5)
|
|
3388 (goto-char there)
|
|
3389 (let ((nest 0)
|
|
3390 ( reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)")
|
|
3391 )
|
|
3392 (catch 'skip
|
|
3393 (while (verilog-re-search-backward reg nil 'move)
|
|
3394 (cond
|
|
3395 ((match-end 1) ; begin
|
|
3396 (setq nest (1- nest)))
|
|
3397 ((match-end 2) ; end
|
|
3398 (setq nest (1+ nest)))
|
|
3399 ((match-end 3)
|
|
3400 (if (= 0 nest)
|
|
3401 (progn
|
|
3402 (goto-char (match-end 0))
|
|
3403 (setq there (point))
|
|
3404 (setq err nil)
|
|
3405 (setq str (verilog-get-expr))
|
|
3406 (setq str (concat " // else: !if" str ))
|
|
3407 (throw 'skip 1))
|
|
3408 )))
|
|
3409 ))))
|
|
3410
|
|
3411 (;- task/function/initial et cetera
|
|
3412 t
|
|
3413 (match-end 0)
|
|
3414 (goto-char (match-end 0))
|
|
3415 (setq there (point))
|
|
3416 (setq err nil)
|
|
3417 (setq str (verilog-get-expr))
|
|
3418 (setq str (concat " // " cntx str )))
|
|
3419
|
|
3420 (;-- otherwise...
|
|
3421 (setq str " // auto-endcomment confused "))
|
|
3422 ))
|
|
3423
|
|
3424 ((and
|
|
3425 (verilog-in-case-region-p) ;-- handle case item differently
|
|
3426 (progn
|
|
3427 (setq there (point))
|
|
3428 (goto-char here)
|
|
3429 (setq str (verilog-backward-case-item lim))))
|
|
3430 (setq err nil)
|
|
3431 (setq str (concat " // case: " str )))
|
|
3432
|
|
3433 ((verilog-in-fork-region-p)
|
|
3434 (setq err nil)
|
|
3435 (setq str " // fork branch" ))
|
|
3436
|
|
3437 ((looking-at "\\<end\\>")
|
|
3438 ;; HERE
|
|
3439 (forward-word 1)
|
|
3440 (verilog-forward-syntactic-ws)
|
|
3441 (setq err nil)
|
|
3442 (setq str (verilog-get-expr))
|
|
3443 (setq str (concat " // " cntx str )))
|
|
3444
|
|
3445 ))))
|
|
3446 (goto-char here)
|
|
3447 (end-of-line)
|
|
3448 (if kill-existing-comment
|
|
3449 (kill-existing-comment))
|
|
3450 (delete-horizontal-space)
|
|
3451 (if (or err
|
|
3452 (> (count-lines here there) verilog-minimum-comment-distance))
|
|
3453 (insert str))
|
|
3454 (if err (ding 't))
|
|
3455 ))))
|
|
3456 (;- this is endclass, which can be nested
|
|
3457 (match-end 11) ;; of verilog-end-block-ordered-re
|
|
3458 ;;(goto-char there)
|
|
3459 (let ((nest 0)
|
|
3460 ( reg "\\<\\(class\\)\\|\\(endclass\\)\\|\\(package\\|primitive\\|\\(macro\\)?module\\)\\>")
|
|
3461 string
|
|
3462 )
|
|
3463 (save-excursion
|
|
3464 (catch 'skip
|
|
3465 (while (verilog-re-search-backward reg nil 'move)
|
|
3466 (cond
|
|
3467 ((match-end 3) ; endclass
|
|
3468 (ding 't)
|
|
3469 (setq string "unmatched endclass")
|
|
3470 (throw 'skip 1))
|
|
3471
|
|
3472 ((match-end 2) ; endclass
|
|
3473 (setq nest (1+ nest)))
|
|
3474
|
|
3475 ((match-end 1) ; class
|
|
3476 (setq nest (1- nest))
|
|
3477 (if (< nest 0)
|
|
3478 (progn
|
|
3479 (goto-char (match-end 0))
|
|
3480 (let (b e)
|
|
3481 (setq b (progn
|
|
3482 (skip-chars-forward "^ \t")
|
|
3483 (verilog-forward-ws&directives)
|
|
3484 (point))
|
|
3485 e (progn
|
|
3486 (skip-chars-forward "a-zA-Z0-9_")
|
|
3487 (point)))
|
|
3488 (setq string (buffer-substring b e)))
|
|
3489 (throw 'skip 1))))
|
|
3490 ))))
|
|
3491 (end-of-line)
|
|
3492 (insert (concat " // " string )))
|
|
3493 )
|
|
3494
|
|
3495 (;- this is end{function,generate,task,module,primitive,table,generate}
|
|
3496 ;- which can not be nested.
|
|
3497 t
|
|
3498 (let (string reg (width nil))
|
|
3499 (end-of-line)
|
|
3500 (if kill-existing-comment
|
|
3501 (save-match-data
|
|
3502 (kill-existing-comment)))
|
|
3503 (delete-horizontal-space)
|
|
3504 (backward-sexp)
|
|
3505 (cond
|
|
3506 ((match-end 5) ;; of verilog-end-block-ordered-re
|
|
3507 (setq reg "\\(\\<function\\>\\)\\|\\(\\<\\(endfunction\\|task\\|\\(macro\\)?module\\|primitive\\)\\>\\)")
|
|
3508 (setq width "\\(\\s-*\\(\\[[^]]*\\]\\)\\|\\(real\\(time\\)?\\)\\|\\(integer\\)\\|\\(time\\)\\)?")
|
|
3509 )
|
|
3510 ((match-end 6) ;; of verilog-end-block-ordered-re
|
|
3511 (setq reg "\\(\\<task\\>\\)\\|\\(\\<\\(endtask\\|function\\|\\(macro\\)?module\\|primitive\\)\\>\\)"))
|
|
3512 ((match-end 7) ;; of verilog-end-block-ordered-re
|
|
3513 (setq reg "\\(\\<\\(macro\\)?module\\>\\)\\|\\<endmodule\\>"))
|
|
3514 ((match-end 8) ;; of verilog-end-block-ordered-re
|
|
3515 (setq reg "\\(\\<primitive\\>\\)\\|\\(\\<\\(endprimitive\\|package\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
|
|
3516 ((match-end 9) ;; of verilog-end-block-ordered-re
|
|
3517 (setq reg "\\(\\<interface\\>\\)\\|\\(\\<\\(endinterface\\|package\\|primitive\\|\\(macro\\)?module\\)\\>\\)"))
|
|
3518 ((match-end 10) ;; of verilog-end-block-ordered-re
|
|
3519 (setq reg "\\(\\<package\\>\\)\\|\\(\\<\\(endpackage\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
|
|
3520 ((match-end 11) ;; of verilog-end-block-ordered-re
|
|
3521 (setq reg "\\(\\<class\\>\\)\\|\\(\\<\\(endclass\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
|
|
3522 ((match-end 12) ;; of verilog-end-block-ordered-re
|
|
3523 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<\\(endcovergroup\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
|
|
3524 ((match-end 13) ;; of verilog-end-block-ordered-re
|
|
3525 (setq reg "\\(\\<program\\>\\)\\|\\(\\<\\(endprogram\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
|
|
3526 ((match-end 14) ;; of verilog-end-block-ordered-re
|
|
3527 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<\\(endsequence\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)"))
|
|
3528 ((match-end 15) ;; of verilog-end-block-ordered-re
|
|
3529 (setq reg "\\(\\<clocking\\>\\)\\|\\<endclocking\\>"))
|
|
3530
|
|
3531 (t (error "Problem in verilog-set-auto-endcomments"))
|
|
3532 )
|
|
3533 (let (b e)
|
|
3534 (save-excursion
|
|
3535 (verilog-re-search-backward reg nil 'move)
|
|
3536 (cond
|
|
3537 ((match-end 1)
|
|
3538 (setq b (progn
|
|
3539 (skip-chars-forward "^ \t")
|
|
3540 (verilog-forward-ws&directives)
|
|
3541 (if (and width (looking-at width))
|
|
3542 (progn
|
|
3543 (goto-char (match-end 0))
|
|
3544 (verilog-forward-ws&directives)
|
|
3545 ))
|
|
3546 (point))
|
|
3547 e (progn
|
|
3548 (skip-chars-forward "a-zA-Z0-9_")
|
|
3549 (point)))
|
|
3550 (setq string (buffer-substring b e)))
|
|
3551 (t
|
|
3552 (ding 't)
|
|
3553 (setq string "unmatched end(function|task|module|primitive|interface|package|class|clocking)")))))
|
|
3554 (end-of-line)
|
|
3555 (insert (concat " // " string )))
|
|
3556 ))))))))))
|
|
3557
|
|
3558 (defun verilog-get-expr()
|
|
3559 "Grab expression at point, e.g, case ( a | b & (c ^d))"
|
|
3560 (let* ((b (progn
|
|
3561 (verilog-forward-syntactic-ws)
|
|
3562 (skip-chars-forward " \t")
|
|
3563 (point)))
|
|
3564 (e (let ((par 1))
|
|
3565 (cond
|
|
3566 ((looking-at "@")
|
|
3567 (forward-char 1)
|
|
3568 (verilog-forward-syntactic-ws)
|
|
3569 (if (looking-at "(")
|
|
3570 (progn
|
|
3571 (forward-char 1)
|
|
3572 (while (and (/= par 0)
|
|
3573 (verilog-re-search-forward "\\((\\)\\|\\()\\)" nil 'move))
|
|
3574 (cond
|
|
3575 ((match-end 1)
|
|
3576 (setq par (1+ par)))
|
|
3577 ((match-end 2)
|
|
3578 (setq par (1- par)))))))
|
|
3579 (point))
|
|
3580 ((looking-at "(")
|
|
3581 (forward-char 1)
|
|
3582 (while (and (/= par 0)
|
|
3583 (verilog-re-search-forward "\\((\\)\\|\\()\\)" nil 'move))
|
|
3584 (cond
|
|
3585 ((match-end 1)
|
|
3586 (setq par (1+ par)))
|
|
3587 ((match-end 2)
|
|
3588 (setq par (1- par)))))
|
|
3589 (point))
|
|
3590 ((looking-at "\\[")
|
|
3591 (forward-char 1)
|
|
3592 (while (and (/= par 0)
|
|
3593 (verilog-re-search-forward "\\(\\[\\)\\|\\(\\]\\)" nil 'move))
|
|
3594 (cond
|
|
3595 ((match-end 1)
|
|
3596 (setq par (1+ par)))
|
|
3597 ((match-end 2)
|
|
3598 (setq par (1- par)))))
|
|
3599 (verilog-forward-syntactic-ws)
|
|
3600 (skip-chars-forward "^ \t\n\f")
|
|
3601 (point))
|
|
3602 ((looking-at "/[/\\*]")
|
|
3603 b)
|
|
3604 ('t
|
|
3605 (skip-chars-forward "^: \t\n\f")
|
|
3606 (point)
|
|
3607 ))))
|
|
3608 (str (buffer-substring b e)))
|
|
3609 (if (setq e (string-match "[ \t]*\\(\\(\n\\)\\|\\(//\\)\\|\\(/\\*\\)\\)" str))
|
|
3610 (setq str (concat (substring str 0 e) "...")))
|
|
3611 str))
|
|
3612
|
|
3613 (defun verilog-expand-vector ()
|
|
3614 "Take a signal vector on the current line and expand it to multiple lines.
|
|
3615 Useful for creating tri's and other expanded fields."
|
|
3616 (interactive)
|
|
3617 (verilog-expand-vector-internal "[" "]"))
|
|
3618
|
|
3619 (defun verilog-expand-vector-internal (bra ket)
|
|
3620 "Given BRA, the start brace and KET, the end brace, expand one line into many lines."
|
|
3621 (save-excursion
|
|
3622 (forward-line 0)
|
|
3623 (let ((signal-string (buffer-substring (point)
|
|
3624 (progn
|
|
3625 (end-of-line) (point)))))
|
|
3626 (if (string-match (concat "\\(.*\\)"
|
|
3627 (regexp-quote bra)
|
|
3628 "\\([0-9]*\\)\\(:[0-9]*\\|\\)\\(::[0-9---]*\\|\\)"
|
|
3629 (regexp-quote ket)
|
|
3630 "\\(.*\\)$") signal-string)
|
|
3631 (let* ((sig-head (match-string 1 signal-string))
|
|
3632 (vec-start (string-to-int (match-string 2 signal-string)))
|
|
3633 (vec-end (if (= (match-beginning 3) (match-end 3))
|
|
3634 vec-start
|
|
3635 (string-to-int (substring signal-string (1+ (match-beginning 3)) (match-end 3)))))
|
|
3636 (vec-range (if (= (match-beginning 4) (match-end 4))
|
|
3637 1
|
|
3638 (string-to-int (substring signal-string (+ 2 (match-beginning 4)) (match-end 4)))))
|
|
3639 (sig-tail (match-string 5 signal-string))
|
|
3640 vec)
|
|
3641 ;; Decode vectors
|
|
3642 (setq vec nil)
|
|
3643 (if (< vec-range 0)
|
|
3644 (let ((tmp vec-start))
|
|
3645 (setq vec-start vec-end
|
|
3646 vec-end tmp
|
|
3647 vec-range (- vec-range))))
|
|
3648 (if (< vec-end vec-start)
|
|
3649 (while (<= vec-end vec-start)
|
|
3650 (setq vec (append vec (list vec-start)))
|
|
3651 (setq vec-start (- vec-start vec-range)))
|
|
3652 (while (<= vec-start vec-end)
|
|
3653 (setq vec (append vec (list vec-start)))
|
|
3654 (setq vec-start (+ vec-start vec-range))))
|
|
3655 ;;
|
|
3656 ;; Delete current line
|
|
3657 (delete-region (point) (progn (forward-line 0) (point)))
|
|
3658 ;;
|
|
3659 ;; Expand vector
|
|
3660 (while vec
|
|
3661 (insert (concat sig-head bra (int-to-string (car vec)) ket sig-tail "\n"))
|
|
3662 (setq vec (cdr vec)))
|
|
3663 (delete-char -1)
|
|
3664 ;;
|
|
3665 )))))
|
|
3666
|
|
3667 (defun verilog-strip-comments ()
|
|
3668 "Strip all comments from the verilog code."
|
|
3669 (interactive)
|
|
3670 (goto-char (point-min))
|
|
3671 (while (re-search-forward "//" nil t)
|
|
3672 (if (verilog-within-string)
|
|
3673 (re-search-forward "\"" nil t)
|
|
3674 (if (verilog-in-star-comment-p)
|
|
3675 (re-search-forward "\*/" nil t)
|
|
3676 (let ((bpt (- (point) 2)))
|
|
3677 (end-of-line)
|
|
3678 (delete-region bpt (point))))))
|
|
3679 ;;
|
|
3680 (goto-char (point-min))
|
|
3681 (while (re-search-forward "/\\*" nil t)
|
|
3682 (if (verilog-within-string)
|
|
3683 (re-search-forward "\"" nil t)
|
|
3684 (let ((bpt (- (point) 2)))
|
|
3685 (re-search-forward "\\*/")
|
|
3686 (delete-region bpt (point))))))
|
|
3687
|
|
3688 (defun verilog-one-line ()
|
|
3689 "Convert structural verilog instances to occupy one line."
|
|
3690 (interactive)
|
|
3691 (goto-char (point-min))
|
|
3692 (while (re-search-forward "\\([^;]\\)[ \t]*\n[ \t]*" nil t)
|
|
3693 (replace-match "\\1 " nil nil)))
|
|
3694
|
|
3695 (defun verilog-linter-name ()
|
|
3696 "Return name of linter, either surelint or verilint."
|
|
3697 (let ((compile-word1 (verilog-string-replace-matches "\\s .*$" "" nil nil
|
|
3698 compile-command))
|
|
3699 (lint-word1 (verilog-string-replace-matches "\\s .*$" "" nil nil
|
|
3700 verilog-linter)))
|
|
3701 (cond ((equal compile-word1 "surelint") `surelint)
|
|
3702 ((equal compile-word1 "verilint") `verilint)
|
|
3703 ((equal lint-word1 "surelint") `surelint)
|
|
3704 ((equal lint-word1 "verilint") `verilint)
|
|
3705 (t `surelint)))) ;; back compatibility
|
|
3706
|
|
3707 (defun verilog-lint-off ()
|
|
3708 "Convert a Verilog linter warning line into a disable statement.
|
|
3709 For example:
|
|
3710 pci_bfm_null.v, line 46: Unused input: pci_rst_
|
|
3711 becomes a comment for the appropriate tool.
|
|
3712
|
|
3713 The first word of the `compile-command' or `verilog-linter'
|
|
3714 variables are used to determine which product is being used.
|
|
3715
|
|
3716 See \\[verilog-surelint-off] and \\[verilog-verilint-off]."
|
|
3717 (interactive)
|
|
3718 (let ((linter (verilog-linter-name)))
|
|
3719 (cond ((equal linter `surelint)
|
|
3720 (verilog-surelint-off))
|
|
3721 ((equal linter `verilint)
|
|
3722 (verilog-verilint-off))
|
|
3723 (t (error "Linter name not set")))))
|
|
3724
|
|
3725 (defun verilog-surelint-off ()
|
|
3726 "Convert a SureLint warning line into a disable statement.
|
|
3727 Run from Verilog source window; assumes there is a *compile* buffer
|
|
3728 with point set appropriately.
|
|
3729
|
|
3730 For example:
|
|
3731 WARNING [STD-UDDONX]: xx.v, line 8: output out is never assigned.
|
|
3732 becomes:
|
|
3733 // surefire lint_line_off UDDONX"
|
|
3734 (interactive)
|
|
3735 (save-excursion
|
|
3736 (switch-to-buffer compilation-last-buffer)
|
|
3737 (beginning-of-line)
|
|
3738 (when
|
|
3739 (looking-at "\\(INFO\\|WARNING\\|ERROR\\) \\[[^-]+-\\([^]]+\\)\\]: \\([^,]+\\), line \\([0-9]+\\): \\(.*\\)$")
|
|
3740 (let* ((code (match-string 2))
|
|
3741 (file (match-string 3))
|
|
3742 (line (match-string 4))
|
|
3743 (buffer (get-file-buffer file))
|
|
3744 dir filename)
|
|
3745 (unless buffer
|
|
3746 (progn
|
|
3747 (setq buffer
|
|
3748 (and (file-exists-p file)
|
|
3749 (find-file-noselect file)))
|
|
3750 (or buffer
|
|
3751 (let* ((pop-up-windows t))
|
|
3752 (let ((name (expand-file-name
|
|
3753 (read-file-name
|
|
3754 (format "Find this error in: (default %s) "
|
|
3755 file)
|
|
3756 dir file t))))
|
|
3757 (if (file-directory-p name)
|
|
3758 (setq name (expand-file-name filename name)))
|
|
3759 (setq buffer
|
|
3760 (and (file-exists-p name)
|
|
3761 (find-file-noselect name))))))))
|
|
3762 (switch-to-buffer buffer)
|
|
3763 (goto-line (string-to-number line))
|
|
3764 (end-of-line)
|
|
3765 (catch 'already
|
|
3766 (cond
|
|
3767 ((verilog-in-slash-comment-p)
|
|
3768 (re-search-backward "//")
|
|
3769 (cond
|
|
3770 ((looking-at "// surefire lint_off_line ")
|
|
3771 (goto-char (match-end 0))
|
|
3772 (let ((lim (save-excursion (end-of-line) (point))))
|
|
3773 (if (re-search-forward code lim 'move)
|
|
3774 (throw 'already t)
|
|
3775 (insert-string (concat " " code)))))
|
|
3776 (t
|
|
3777 )))
|
|
3778 ((verilog-in-star-comment-p)
|
|
3779 (re-search-backward "/\*")
|
|
3780 (insert-string (format " // surefire lint_off_line %6s" code ))
|
|
3781 )
|
|
3782 (t
|
|
3783 (insert-string (format " // surefire lint_off_line %6s" code ))
|
|
3784 )))))))
|
|
3785
|
|
3786 (defun verilog-verilint-off ()
|
|
3787 "Convert a Verilint warning line into a disable statement.
|
|
3788
|
|
3789 For example:
|
|
3790 (W240) pci_bfm_null.v, line 46: Unused input: pci_rst_
|
|
3791 becomes:
|
|
3792 //Verilint 240 off // WARNING: Unused input"
|
|
3793 (interactive)
|
|
3794 (save-excursion
|
|
3795 (beginning-of-line)
|
|
3796 (when (looking-at "\\(.*\\)([WE]\\([0-9A-Z]+\\)).*,\\s +line\\s +[0-9]+:\\s +\\([^:\n]+\\):?.*$")
|
|
3797 (replace-match (format
|
|
3798 ;; %3s makes numbers 1-999 line up nicely
|
|
3799 "\\1//Verilint %3s off // WARNING: \\3"
|
|
3800 (match-string 2)))
|
|
3801 (beginning-of-line)
|
|
3802 (verilog-indent-line))))
|
|
3803
|
|
3804 (defun verilog-auto-save-compile ()
|
|
3805 "Update automatics with \\[verilog-auto], save the buffer, and compile."
|
|
3806 (interactive)
|
|
3807 (verilog-auto) ; Always do it for safety
|
|
3808 (save-buffer)
|
|
3809 (compile compile-command))
|
|
3810
|
|
3811
|
|
3812
|
|
3813 ;;
|
|
3814 ;; Batch
|
|
3815 ;;
|
|
3816
|
|
3817 (defmacro verilog-batch-error-wrapper (&rest body)
|
|
3818 "Execute BODY and add error prefix to any errors found.
|
|
3819 This lets programs calling batch mode to easily extract error messages."
|
79546
|
3820 `(condition-case err
|
|
3821 (progn ,@body)
|
|
3822 (error
|
|
3823 (error "%%Error: %s%s" (error-message-string err)
|
|
3824 (if (featurep 'xemacs) "\n" ""))))) ;; xemacs forgets to add a newline
|
79545
|
3825
|
|
3826 (defun verilog-batch-execute-func (funref)
|
|
3827 "Internal processing of a batch command, running FUNREF on all command arguments."
|
|
3828 (verilog-batch-error-wrapper
|
|
3829 ;; General globals needed
|
|
3830 (setq make-backup-files nil)
|
|
3831 (setq-default make-backup-files nil)
|
|
3832 (setq enable-local-variables t)
|
|
3833 (setq enable-local-eval t)
|
|
3834 ;; Make sure any sub-files we read get proper mode
|
|
3835 (setq default-major-mode `verilog-mode)
|
|
3836 ;; Ditto files already read in
|
|
3837 (mapcar '(lambda (buf)
|
|
3838 (when (buffer-file-name buf)
|
|
3839 (save-excursion
|
|
3840 (set-buffer buf)
|
|
3841 (verilog-mode))))
|
|
3842 (buffer-list))
|
|
3843 ;; Process the files
|
|
3844 (mapcar '(lambda (buf)
|
|
3845 (when (buffer-file-name buf)
|
|
3846 (save-excursion
|
|
3847 (if (not (file-exists-p (buffer-file-name buf)))
|
|
3848 (error (concat "File not found: " (buffer-file-name buf))))
|
|
3849 (message (concat "Processing " (buffer-file-name buf)))
|
|
3850 (set-buffer buf)
|
|
3851 (funcall funref)
|
|
3852 (save-buffer))))
|
|
3853 (buffer-list))))
|
|
3854
|
|
3855 (defun verilog-batch-auto ()
|
|
3856 "For use with --batch, perform automatic expansions as a stand-alone tool.
|
|
3857 This sets up the appropriate Verilog-Mode environment, updates automatics
|
|
3858 with \\[verilog-auto] on all command-line files, and saves the buffers.
|
|
3859 For proper results, multiple filenames need to be passed on the command
|
|
3860 line in bottom-up order."
|
|
3861 (unless noninteractive
|
|
3862 (error "Use verilog-batch-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
|
|
3863 (verilog-batch-execute-func `verilog-auto))
|
|
3864
|
|
3865 (defun verilog-batch-delete-auto ()
|
|
3866 "For use with --batch, perform automatic deletion as a stand-alone tool.
|
|
3867 This sets up the appropriate Verilog-Mode environment, deletes automatics
|
|
3868 with \\[verilog-delete-auto] on all command-line files, and saves the buffers."
|
|
3869 (unless noninteractive
|
|
3870 (error "Use verilog-batch-delete-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
|
|
3871 (verilog-batch-execute-func `verilog-delete-auto))
|
|
3872
|
|
3873 (defun verilog-batch-inject-auto ()
|
|
3874 "For use with --batch, perform automatic injection as a stand-alone tool.
|
|
3875 This sets up the appropriate Verilog-Mode environment, injects new automatics
|
|
3876 with \\[verilog-inject-auto] on all command-line files, and saves the buffers.
|
|
3877 For proper results, multiple filenames need to be passed on the command
|
|
3878 line in bottom-up order."
|
|
3879 (unless noninteractive
|
|
3880 (error "Use verilog-batch-inject-auto only with --batch")) ;; Otherwise we'd mess up buffer modes
|
|
3881 (verilog-batch-execute-func `verilog-inject-auto))
|
|
3882
|
|
3883 (defun verilog-batch-indent ()
|
|
3884 "For use with --batch, reindent an a entire file as a stand-alone tool.
|
|
3885 This sets up the appropriate Verilog-Mode environment, calls
|
|
3886 \\[verilog-indent-buffer] on all command-line files, and saves the buffers."
|
|
3887 (unless noninteractive
|
|
3888 (error "Use verilog-batch-indent only with --batch")) ;; Otherwise we'd mess up buffer modes
|
|
3889 (verilog-batch-execute-func `verilog-indent-buffer))
|
|
3890
|
|
3891
|
|
3892 ;;
|
|
3893 ;; Indentation
|
|
3894 ;;
|
|
3895 (defconst verilog-indent-alist
|
|
3896 '((block . (+ ind verilog-indent-level))
|
|
3897 (case . (+ ind verilog-case-indent))
|
|
3898 (cparenexp . (+ ind verilog-indent-level))
|
|
3899 (cexp . (+ ind verilog-cexp-indent))
|
|
3900 (defun . verilog-indent-level-module)
|
|
3901 (declaration . verilog-indent-level-declaration)
|
|
3902 (directive . (verilog-calculate-indent-directive))
|
|
3903 (tf . verilog-indent-level)
|
|
3904 (behavioral . (+ verilog-indent-level-behavioral verilog-indent-level-module))
|
|
3905 (statement . ind)
|
|
3906 (cpp . 0)
|
|
3907 (comment . (verilog-comment-indent))
|
|
3908 (unknown . 3)
|
|
3909 (string . 0)))
|
|
3910
|
|
3911 (defun verilog-continued-line-1 (lim)
|
|
3912 "Return true if this is a continued line.
|
|
3913 Set point to where line starts. Limit search to point LIM."
|
|
3914 (let ((continued 't))
|
|
3915 (if (eq 0 (forward-line -1))
|
|
3916 (progn
|
|
3917 (end-of-line)
|
|
3918 (verilog-backward-ws&directives lim)
|
|
3919 (if (bobp)
|
|
3920 (setq continued nil)
|
|
3921 (setq continued (verilog-backward-token))))
|
|
3922 (setq continued nil))
|
|
3923 continued))
|
|
3924
|
|
3925 (defun verilog-calculate-indent ()
|
|
3926 "Calculate the indent of the current Verilog line.
|
|
3927 Examine previous lines. Once a line is found that is definitive as to the
|
|
3928 type of the current line, return that lines' indent level and its
|
|
3929 type. Return a list of two elements: (INDENT-TYPE INDENT-LEVEL)."
|
|
3930 (save-excursion
|
|
3931 (let* ((starting_position (point))
|
|
3932 (par 0)
|
|
3933 (begin (looking-at "[ \t]*begin\\>"))
|
|
3934 (lim (save-excursion (verilog-re-search-backward "\\(\\<begin\\>\\)\\|\\(\\<module\\>\\)" nil t)))
|
|
3935 (type (catch 'nesting
|
|
3936 ;; Keep working backwards until we can figure out
|
|
3937 ;; what type of statement this is.
|
|
3938 ;; Basically we need to figure out
|
|
3939 ;; 1) if this is a continuation of the previous line;
|
|
3940 ;; 2) are we in a block scope (begin..end)
|
|
3941
|
|
3942 ;; if we are in a comment, done.
|
|
3943 (if (verilog-in-star-comment-p)
|
|
3944 (throw 'nesting 'comment))
|
|
3945
|
|
3946 ;; if we have a directive, done.
|
|
3947 (if (save-excursion (beginning-of-line) (looking-at verilog-directive-re-1))
|
|
3948 (throw 'nesting 'directive))
|
|
3949
|
|
3950 ;; unless we are in the newfangled coverpoint or constraint blocks
|
|
3951 ;; if we are in a parenthesized list, and the user likes to indent these, return.
|
|
3952 (if (and
|
|
3953 verilog-indent-lists
|
|
3954 (not (verilog-in-coverage))
|
|
3955 (verilog-in-paren))
|
|
3956 (progn (setq par 1)
|
|
3957 (throw 'nesting 'block))
|
|
3958 )
|
|
3959
|
|
3960 ;; See if we are continuing a previous line
|
|
3961 (while t
|
|
3962 ;; trap out if we crawl off the top of the buffer
|
|
3963 (if (bobp) (throw 'nesting 'cpp))
|
|
3964
|
|
3965 (if (verilog-continued-line-1 lim)
|
|
3966 (let ((sp (point)))
|
|
3967 (if (and
|
|
3968 (not (looking-at verilog-complete-reg))
|
|
3969 (verilog-continued-line-1 lim))
|
|
3970 (progn (goto-char sp)
|
|
3971 (throw 'nesting 'cexp))
|
|
3972
|
|
3973 (goto-char sp))
|
|
3974
|
|
3975 (if (and begin
|
|
3976 (not verilog-indent-begin-after-if)
|
|
3977 (looking-at verilog-no-indent-begin-re))
|
|
3978 (progn
|
|
3979 (beginning-of-line)
|
|
3980 (skip-chars-forward " \t")
|
|
3981 (throw 'nesting 'statement))
|
|
3982 (progn
|
|
3983 (throw 'nesting 'cexp))))
|
|
3984 ;; not a continued line
|
|
3985 (goto-char starting_position))
|
|
3986
|
|
3987 (if (looking-at "\\<else\\>")
|
|
3988 ;; search back for governing if, striding across begin..end pairs
|
|
3989 ;; appropriately
|
|
3990 (let ((elsec 1))
|
|
3991 (while (verilog-re-search-backward verilog-ends-re nil 'move)
|
|
3992 (cond
|
|
3993 ((match-end 1) ; else, we're in deep
|
|
3994 (setq elsec (1+ elsec)))
|
|
3995 ((match-end 2) ; if
|
|
3996 (setq elsec (1- elsec))
|
|
3997 (if (= 0 elsec)
|
|
3998 (if verilog-align-ifelse
|
|
3999 (throw 'nesting 'statement)
|
|
4000 (progn ;; back up to first word on this line
|
|
4001 (beginning-of-line)
|
|
4002 (verilog-forward-syntactic-ws)
|
|
4003 (throw 'nesting 'statement)))))
|
|
4004 (t ; endblock
|
|
4005 ; try to leap back to matching outward block by striding across
|
|
4006 ; indent level changing tokens then immediately
|
|
4007 ; previous line governs indentation.
|
|
4008 (let (( reg) (nest 1))
|
|
4009 ;; verilog-ends => else|if|end|join(_any|_none|)|endcase|endclass|endtable|endspecify|endfunction|endtask|endgenerate|endgroup
|
|
4010 (cond
|
|
4011 ((match-end 3) ; end
|
|
4012 ;; Search back for matching begin
|
|
4013 (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" ))
|
|
4014 ((match-end 4) ; endcase
|
|
4015 ;; Search back for matching case
|
|
4016 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ))
|
|
4017 ((match-end 5) ; endfunction
|
|
4018 ;; Search back for matching function
|
|
4019 (setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
|
|
4020 ((match-end 6) ; endtask
|
|
4021 ;; Search back for matching task
|
|
4022 (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" ))
|
|
4023 ((match-end 7) ; endspecify
|
|
4024 ;; Search back for matching specify
|
|
4025 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
|
|
4026 ((match-end 8) ; endtable
|
|
4027 ;; Search back for matching table
|
|
4028 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
|
|
4029 ((match-end 9) ; endgenerate
|
|
4030 ;; Search back for matching generate
|
|
4031 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
|
|
4032 ((match-end 10) ; joins
|
|
4033 ;; Search back for matching fork
|
|
4034 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|none\\)?\\>\\)" ))
|
|
4035 ((match-end 11) ; class
|
|
4036 ;; Search back for matching class
|
|
4037 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
|
|
4038 ((match-end 12) ; covergroup
|
|
4039 ;; Search back for matching covergroup
|
|
4040 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
|
|
4041 )
|
|
4042 (catch 'skip
|
|
4043 (while (verilog-re-search-backward reg nil 'move)
|
|
4044 (cond
|
|
4045 ((match-end 1) ; begin
|
|
4046 (setq nest (1- nest))
|
|
4047 (if (= 0 nest)
|
|
4048 (throw 'skip 1)))
|
|
4049 ((match-end 2) ; end
|
|
4050 (setq nest (1+ nest)))))
|
|
4051 )
|
|
4052 ))
|
|
4053 ))))
|
|
4054 (throw 'nesting (verilog-calc-1))
|
|
4055 )
|
|
4056 );; catch nesting
|
|
4057 );; type
|
|
4058 )
|
|
4059 ;; Return type of block and indent level.
|
|
4060 (if (not type)
|
|
4061 (setq type 'cpp))
|
|
4062 (if (> par 0) ; Unclosed Parenthesis
|
|
4063 (list 'cparenexp par)
|
|
4064 (cond
|
|
4065 ((eq type 'case)
|
|
4066 (list type (verilog-case-indent-level)))
|
|
4067 ((eq type 'statement)
|
|
4068 (list type (current-column)))
|
|
4069 ((eq type 'defun)
|
|
4070 (list type 0))
|
|
4071 (t
|
|
4072 (list type (verilog-current-indent-level)))))
|
|
4073 )))
|
|
4074 (defun verilog-wai ()
|
|
4075 "Show matching nesting block for debugging."
|
|
4076 (interactive)
|
|
4077 (save-excursion
|
|
4078 (let ((nesting (verilog-calc-1)))
|
|
4079 (message "You are at nesting %s" nesting))))
|
|
4080
|
|
4081 (defun verilog-calc-1 ()
|
|
4082 (catch 'nesting
|
|
4083 (while (verilog-re-search-backward (concat "\\({\\|}\\|" verilog-indent-re "\\)") nil 'move)
|
|
4084 (cond
|
|
4085 ((equal (char-after) ?\{)
|
|
4086 (if (verilog-at-constraint-p)
|
|
4087 (throw 'nesting 'block)
|
|
4088 ))
|
|
4089 ((equal (char-after) ?\})
|
|
4090
|
|
4091 (let ((there (verilog-at-close-constraint-p)))
|
|
4092 (if there (goto-char there))))
|
|
4093
|
|
4094 ((looking-at verilog-beg-block-re-ordered)
|
|
4095 (cond
|
|
4096 ((match-end 2) ; *sigh* could be "unique case" or "priority casex"
|
|
4097 (let ((here (point)))
|
|
4098 (verilog-beg-of-statement)
|
|
4099 (if (looking-at verilog-extended-case-re)
|
|
4100 (throw 'nesting 'case)
|
|
4101 (goto-char here)))
|
|
4102 (throw 'nesting 'case))
|
|
4103
|
|
4104 ;; need to consider typedef struct here...
|
|
4105 ((looking-at "\\<class\\|struct\\|function\\|task\\|property\\>")
|
|
4106 ; *sigh* These words have an optional prefix:
|
|
4107 ; extern {virtual|protected}? function a();
|
|
4108 ; assert property (p_1);
|
|
4109 ; typedef class foo;
|
|
4110 ; and we don't want to confuse this with
|
|
4111 ; function a();
|
|
4112 ; property
|
|
4113 ; ...
|
|
4114 ; endfunction
|
|
4115 (let ((here (point)))
|
|
4116 (save-excursion
|
|
4117 (verilog-beg-of-statement)
|
|
4118 (if (= (point) here)
|
|
4119 (throw 'nesting 'block))
|
|
4120 )))
|
|
4121 (t (throw 'nesting 'block))))
|
|
4122
|
|
4123 ((looking-at verilog-end-block-re)
|
|
4124 (verilog-leap-to-head)
|
|
4125 (if (verilog-in-case-region-p)
|
|
4126 (progn
|
|
4127 (verilog-leap-to-case-head)
|
|
4128 (if (looking-at verilog-case-re)
|
|
4129 (throw 'nesting 'case)))))
|
|
4130
|
|
4131 ((looking-at (if (verilog-in-generate-region-p)
|
|
4132 verilog-defun-level-not-generate-re
|
|
4133 verilog-defun-level-re))
|
|
4134 (throw 'nesting 'defun))
|
|
4135
|
|
4136 ((looking-at verilog-cpp-level-re)
|
|
4137 (throw 'nesting 'cpp))
|
|
4138
|
|
4139 ((bobp)
|
|
4140 (throw 'nesting 'cpp))
|
|
4141 ))
|
|
4142 (throw 'nesting 'cpp)
|
|
4143 )
|
|
4144 )
|
|
4145
|
|
4146 (defun verilog-calculate-indent-directive ()
|
|
4147 "Return indentation level for directive.
|
|
4148 For speed, the searcher looks at the last directive, not the indent
|
|
4149 of the appropriate enclosing block."
|
|
4150 (let ((base -1) ;; Indent of the line that determines our indentation
|
|
4151 (ind 0) ;; Relative offset caused by other directives (like `endif on same line as `else)
|
|
4152 )
|
|
4153 ;; Start at current location, scan back for another directive
|
|
4154
|
|
4155 (save-excursion
|
|
4156 (beginning-of-line)
|
|
4157 (while (and (< base 0)
|
|
4158 (verilog-re-search-backward verilog-directive-re nil t))
|
|
4159 (cond ((save-excursion (skip-chars-backward " \t") (bolp))
|
|
4160 (setq base (current-indentation))
|
|
4161 ))
|
|
4162 (cond ((and (looking-at verilog-directive-end) (< base 0)) ;; Only matters when not at BOL
|
|
4163 (setq ind (- ind verilog-indent-level-directive)))
|
|
4164 ((and (looking-at verilog-directive-middle) (>= base 0)) ;; Only matters when at BOL
|
|
4165 (setq ind (+ ind verilog-indent-level-directive)))
|
|
4166 ((looking-at verilog-directive-begin)
|
|
4167 (setq ind (+ ind verilog-indent-level-directive)))))
|
|
4168 ;; Adjust indent to starting indent of critical line
|
|
4169 (setq ind (max 0 (+ ind base))))
|
|
4170
|
|
4171 (save-excursion
|
|
4172 (beginning-of-line)
|
|
4173 (skip-chars-forward " \t")
|
|
4174 (cond ((or (looking-at verilog-directive-middle)
|
|
4175 (looking-at verilog-directive-end))
|
|
4176 (setq ind (max 0 (- ind verilog-indent-level-directive))))))
|
|
4177 ind))
|
|
4178
|
|
4179 (defun verilog-leap-to-case-head ()
|
|
4180 (let ((nest 1))
|
|
4181 (while (/= 0 nest)
|
|
4182 (verilog-re-search-backward "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" nil 'move)
|
|
4183 (cond
|
|
4184 ((match-end 1)
|
|
4185 (setq nest (1- nest)))
|
|
4186 ((match-end 2)
|
|
4187 (setq nest (1+ nest)))
|
|
4188 ((bobp)
|
|
4189 (ding 't)
|
|
4190 (setq nest 0))))))
|
|
4191
|
|
4192 (defun verilog-leap-to-head ()
|
|
4193 "Move point to the head of this block; jump from end to matching begin,
|
|
4194 from endcase to matching case, and so on."
|
|
4195 (let ((reg nil)
|
|
4196 snest
|
|
4197 (nest 1))
|
|
4198 (cond
|
|
4199 ((looking-at "\\<end\\>")
|
|
4200 ;; 1: Search back for matching begin
|
|
4201 (setq reg (concat "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|"
|
|
4202 "\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" )))
|
|
4203 ((looking-at "\\<endcase\\>")
|
|
4204 ;; 2: Search back for matching case
|
|
4205 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>\\)\\|\\(\\<endcase\\>\\)" ))
|
|
4206 ((looking-at "\\<join\\(_any\\|_none\\)?\\>")
|
|
4207 ;; 3: Search back for matching fork
|
|
4208 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
|
|
4209 ((looking-at "\\<endclass\\>")
|
|
4210 ;; 4: Search back for matching class
|
|
4211 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" ))
|
|
4212 ((looking-at "\\<endtable\\>")
|
|
4213 ;; 5: Search back for matching table
|
|
4214 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" ))
|
|
4215 ((looking-at "\\<endspecify\\>")
|
|
4216 ;; 6: Search back for matching specify
|
|
4217 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" ))
|
|
4218 ((looking-at "\\<endfunction\\>")
|
|
4219 ;; 7: Search back for matching function
|
|
4220 (setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" ))
|
|
4221 ((looking-at "\\<endgenerate\\>")
|
|
4222 ;; 8: Search back for matching generate
|
|
4223 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" ))
|
|
4224 ((looking-at "\\<endtask\\>")
|
|
4225 ;; 9: Search back for matching task
|
|
4226 (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" ))
|
|
4227 ((looking-at "\\<endgroup\\>")
|
|
4228 ;; 10: Search back for matching covergroup
|
|
4229 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))
|
|
4230 ((looking-at "\\<endproperty\\>")
|
|
4231 ;; 11: Search back for matching property
|
|
4232 (setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" ))
|
|
4233 ((looking-at "\\<endinterface\\>")
|
|
4234 ;; 12: Search back for matching interface
|
|
4235 (setq reg "\\(\\<interface\\>\\)\\|\\(\\<endinterface\\>\\)" ))
|
|
4236 ((looking-at "\\<endsequence\\>")
|
|
4237 ;; 12: Search back for matching sequence
|
|
4238 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" ))
|
|
4239 ((looking-at "\\<endclocking\\>")
|
|
4240 ;; 12: Search back for matching clocking
|
|
4241 (setq reg "\\(\\<clocking\\)\\|\\(\\<endclocking\\>\\)" ))
|
|
4242 )
|
|
4243 (if reg
|
|
4244 (catch 'skip
|
|
4245 (let (sreg)
|
|
4246 (while (verilog-re-search-backward reg nil 'move)
|
|
4247 (cond
|
|
4248 ((match-end 1) ; begin
|
|
4249 (setq nest (1- nest))
|
|
4250 (if (= 0 nest)
|
|
4251 ;; Now previous line describes syntax
|
|
4252 (throw 'skip 1))
|
|
4253 (if (and snest
|
|
4254 (= snest nest))
|
|
4255 (setq reg sreg)))
|
|
4256 ((match-end 2) ; end
|
|
4257 (setq nest (1+ nest)))
|
|
4258 ((match-end 3)
|
|
4259 ;; endcase, jump to case
|
|
4260 (setq snest nest)
|
|
4261 (setq nest (1+ nest))
|
|
4262 (setq sreg reg)
|
|
4263 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" ))
|
|
4264 ((match-end 4)
|
|
4265 ;; join, jump to fork
|
|
4266 (setq snest nest)
|
|
4267 (setq nest (1+ nest))
|
|
4268 (setq sreg reg)
|
|
4269 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))
|
|
4270 )))))))
|
|
4271
|
|
4272 (defun verilog-continued-line ()
|
|
4273 "Return true if this is a continued line.
|
|
4274 Set point to where line starts"
|
|
4275 (let ((continued 't))
|
|
4276 (if (eq 0 (forward-line -1))
|
|
4277 (progn
|
|
4278 (end-of-line)
|
|
4279 (verilog-backward-ws&directives)
|
|
4280 (if (bobp)
|
|
4281 (setq continued nil)
|
|
4282 (while (and continued
|
|
4283 (save-excursion
|
|
4284 (skip-chars-backward " \t")
|
|
4285 (not (bolp))))
|
|
4286 (setq continued (verilog-backward-token))
|
|
4287 ) ;; while
|
|
4288 ))
|
|
4289 (setq continued nil))
|
|
4290 continued))
|
|
4291
|
|
4292 (defun verilog-backward-token ()
|
|
4293 "Step backward token, returning true if we are now at an end of line token."
|
|
4294 (interactive)
|
|
4295 (verilog-backward-syntactic-ws)
|
|
4296 (cond
|
|
4297 ((bolp)
|
|
4298 nil)
|
|
4299 (;-- Anything ending in a ; is complete
|
|
4300 (= (preceding-char) ?\;)
|
|
4301 nil)
|
|
4302 (; If a "}" is prefixed by a ";", then this is a complete statement
|
|
4303 ; i.e.: constraint foo { a = b; }
|
|
4304 (= (preceding-char) ?\})
|
|
4305 (progn
|
|
4306 (backward-char)
|
|
4307 (verilog-at-close-constraint-p))
|
|
4308 )
|
|
4309 (;-- constraint foo { a = b }
|
|
4310 ; is a complete statement. *sigh*
|
|
4311 (= (preceding-char) ?\{)
|
|
4312 (progn
|
|
4313 (backward-char)
|
|
4314 (not (verilog-at-constraint-p)))
|
|
4315 )
|
|
4316 (;-- Could be 'case (foo)' or 'always @(bar)' which is complete
|
|
4317 ; also could be simply '@(foo)'
|
|
4318 ; or foo u1 #(a=8)
|
|
4319 ; (b, ... which ISN'T complete
|
|
4320 ;;;; Do we need this???
|
|
4321 (= (preceding-char) ?\))
|
|
4322 (progn
|
|
4323 (backward-char)
|
|
4324 (backward-up-list 1)
|
|
4325 (verilog-backward-syntactic-ws)
|
|
4326 (let ((back (point)))
|
|
4327 (forward-word -1)
|
|
4328 (cond
|
|
4329 ((looking-at "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|case\\(\\|[xz]\\)\\|for\\(\\|each\\|ever\\)\\|i\\(f\\|nitial\\)\\|repeat\\|while\\)\\>")
|
|
4330 (not (looking-at "\\<randcase\\>\\|\\<case[xz]?\\>[^:]")))
|
|
4331 (t
|
|
4332 (goto-char back)
|
|
4333 (cond
|
|
4334 ((= (preceding-char) ?\@)
|
|
4335 (backward-char)
|
|
4336 (save-excursion
|
|
4337 (verilog-backward-token)
|
|
4338 (not (looking-at "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|initial\\|while\\)\\>"))))
|
|
4339 ((= (preceding-char) ?\#)
|
|
4340 (backward-char)
|
|
4341 )
|
|
4342 (t t))
|
|
4343 )))))
|
|
4344
|
|
4345 (;-- any of begin|initial|while are complete statements; 'begin : foo' is also complete
|
|
4346 t
|
|
4347 (forward-word -1)
|
|
4348 (cond
|
|
4349 ((looking-at "\\<else\\>")
|
|
4350 t)
|
|
4351 ((looking-at verilog-indent-re)
|
|
4352 nil)
|
|
4353 (t
|
|
4354 (let
|
|
4355 ((back (point)))
|
|
4356 (verilog-backward-syntactic-ws)
|
|
4357 (cond
|
|
4358 ((= (preceding-char) ?\:)
|
|
4359 (backward-char)
|
|
4360 (verilog-backward-syntactic-ws)
|
|
4361 (backward-sexp)
|
|
4362 (if (looking-at verilog-nameable-item-re )
|
|
4363 nil
|
|
4364 t)
|
|
4365 )
|
|
4366 ((= (preceding-char) ?\#)
|
|
4367 (backward-char)
|
|
4368 t)
|
|
4369 ((= (preceding-char) ?\`)
|
|
4370 (backward-char)
|
|
4371 t)
|
|
4372
|
|
4373 (t
|
|
4374 (goto-char back)
|
|
4375 t)
|
|
4376 )))))))
|
|
4377
|
|
4378 (defun verilog-backward-syntactic-ws (&optional bound)
|
|
4379 "Backward skip over syntactic whitespace for Emacs 19.
|
|
4380 Optional BOUND limits search."
|
|
4381 (save-restriction
|
|
4382 (let* ((bound (or bound (point-min))) (here bound) )
|
|
4383 (if (< bound (point))
|
|
4384 (progn
|
|
4385 (narrow-to-region bound (point))
|
|
4386 (while (/= here (point))
|
|
4387 (setq here (point))
|
|
4388 (verilog-skip-backward-comments)
|
|
4389 )))
|
|
4390 ))
|
|
4391 t)
|
|
4392
|
|
4393 (defun verilog-forward-syntactic-ws (&optional bound)
|
|
4394 "Forward skip over syntactic whitespace for Emacs 19.
|
|
4395 Optional BOUND limits search."
|
|
4396 (save-restriction
|
|
4397 (let* ((bound (or bound (point-max)))
|
|
4398 (here bound)
|
|
4399 )
|
|
4400 (if (> bound (point))
|
|
4401 (progn
|
|
4402 (narrow-to-region (point) bound)
|
|
4403 (while (/= here (point))
|
|
4404 (setq here (point))
|
|
4405 (forward-comment (buffer-size))
|
|
4406 )))
|
|
4407 )))
|
|
4408
|
|
4409 (defun verilog-backward-ws&directives (&optional bound)
|
|
4410 "Backward skip over syntactic whitespace and compiler directives for Emacs 19.
|
|
4411 Optional BOUND limits search."
|
|
4412 (save-restriction
|
|
4413 (let* ((bound (or bound (point-min)))
|
|
4414 (here bound)
|
|
4415 (p nil) )
|
|
4416 (if (< bound (point))
|
|
4417 (progn
|
|
4418 (let ((state
|
|
4419 (save-excursion
|
|
4420 (parse-partial-sexp (point-min) (point)))))
|
|
4421 (cond
|
|
4422 ((nth 7 state) ;; in // comment
|
|
4423 (verilog-re-search-backward "//" nil 'move)
|
|
4424 (skip-chars-backward "/"))
|
|
4425 ((nth 4 state) ;; in /* */ comment
|
|
4426 (verilog-re-search-backward "/\*" nil 'move))))
|
|
4427 (narrow-to-region bound (point))
|
|
4428 (while (/= here (point))
|
|
4429 (setq here (point))
|
|
4430 (verilog-skip-backward-comments)
|
|
4431 (setq p
|
|
4432 (save-excursion
|
|
4433 (beginning-of-line)
|
|
4434 (cond
|
|
4435 ((verilog-within-translate-off)
|
|
4436 (verilog-back-to-start-translate-off (point-min)))
|
|
4437 ((looking-at verilog-directive-re-1)
|
|
4438 (point))
|
|
4439 (t
|
|
4440 nil))))
|
|
4441 (if p (goto-char p))
|
|
4442 )))
|
|
4443 )))
|
|
4444
|
|
4445 (defun verilog-forward-ws&directives (&optional bound)
|
|
4446 "Forward skip over syntactic whitespace and compiler directives for Emacs 19.
|
|
4447 Optional BOUND limits search."
|
|
4448 (save-restriction
|
|
4449 (let* ((bound (or bound (point-max)))
|
|
4450 (here bound)
|
|
4451 jump
|
|
4452 )
|
|
4453 (if (> bound (point))
|
|
4454 (progn
|
|
4455 (let ((state
|
|
4456 (save-excursion
|
|
4457 (parse-partial-sexp (point-min) (point)))))
|
|
4458 (cond
|
|
4459 ((nth 7 state) ;; in // comment
|
|
4460 (verilog-re-search-forward "//" nil 'move))
|
|
4461 ((nth 4 state) ;; in /* */ comment
|
|
4462 (verilog-re-search-forward "/\*" nil 'move))))
|
|
4463 (narrow-to-region (point) bound)
|
|
4464 (while (/= here (point))
|
|
4465 (setq here (point)
|
|
4466 jump nil)
|
|
4467 (forward-comment (buffer-size))
|
|
4468 (save-excursion
|
|
4469 (beginning-of-line)
|
|
4470 (if (looking-at verilog-directive-re-1)
|
|
4471 (setq jump t)))
|
|
4472 (if jump
|
|
4473 (beginning-of-line 2))
|
|
4474 )))
|
|
4475 )))
|
|
4476
|
|
4477 (defun verilog-in-comment-p ()
|
|
4478 "Return true if in a star or // comment."
|
|
4479 (let ((state
|
|
4480 (save-excursion
|
|
4481 (parse-partial-sexp (point-min) (point)))))
|
|
4482 (or (nth 4 state) (nth 7 state))))
|
|
4483
|
|
4484 (defun verilog-in-star-comment-p ()
|
|
4485 "Return true if in a star comment."
|
|
4486 (let ((state
|
|
4487 (save-excursion
|
|
4488 (parse-partial-sexp (point-min) (point)))))
|
|
4489 (and
|
|
4490 (nth 4 state) ; t if in a comment of style a // or b /**/
|
|
4491 (not
|
|
4492 (nth 7 state) ; t if in a comment of style b /**/
|
|
4493 ))))
|
|
4494
|
|
4495 (defun verilog-in-slash-comment-p ()
|
|
4496 "Return true if in a slash comment."
|
|
4497 (let ((state
|
|
4498 (save-excursion
|
|
4499 (parse-partial-sexp (point-min) (point)))))
|
|
4500 (nth 7 state)))
|
|
4501
|
|
4502 (defun verilog-in-comment-or-string-p ()
|
|
4503 "Return true if in a string or comment."
|
|
4504 (let ((state
|
|
4505 (save-excursion
|
|
4506 (parse-partial-sexp (point-min) (point)))))
|
|
4507 (or (nth 3 state) (nth 4 state) (nth 7 state)))) ; Inside string or comment)
|
|
4508
|
|
4509 (defun verilog-in-escaped-name-p ()
|
|
4510 "Return true if in an escaped name."
|
|
4511 (save-excursion
|
|
4512 (backward-char)
|
|
4513 (skip-chars-backward "^ \t\n\f")
|
|
4514 (if (equal (char-after (point) ) ?\\ )
|
|
4515 t
|
|
4516 nil)))
|
|
4517
|
|
4518 (defun verilog-in-paren ()
|
|
4519 "Return true if in a parenthetical expression."
|
|
4520 (let ((state
|
|
4521 (save-excursion
|
|
4522 (parse-partial-sexp (point-min) (point)))))
|
|
4523 (> (nth 0 state) 0 )))
|
|
4524
|
|
4525 (defun verilog-in-coverage ()
|
|
4526 "Return true if in a constraint or coverpoint expression."
|
|
4527 (interactive)
|
|
4528 (save-excursion
|
|
4529 (if (verilog-in-paren)
|
|
4530 (progn
|
|
4531 (backward-up-list 1)
|
|
4532 (verilog-at-constraint-p)
|
|
4533 )
|
|
4534 nil)))
|
|
4535 (defun verilog-at-close-constraint-p ()
|
|
4536 "If at the } that closes a constraint or covergroup, return true."
|
|
4537 (if (and
|
|
4538 (equal (char-after) ?\})
|
|
4539 (verilog-in-paren))
|
|
4540
|
|
4541 (save-excursion
|
|
4542 (verilog-backward-ws&directives)
|
|
4543 (if (equal (char-before) ?\;)
|
|
4544 (point)
|
|
4545 nil))))
|
|
4546
|
|
4547 (defun verilog-at-constraint-p ()
|
|
4548 "If at the { of a constraint or coverpoint definition, return true, moving point to constraint."
|
|
4549 (if (save-excursion
|
|
4550 (and
|
|
4551 (equal (char-after) ?\{)
|
|
4552 (forward-list)
|
|
4553 (progn (backward-char 1)
|
|
4554 (verilog-backward-ws&directives)
|
|
4555 (equal (char-before) ?\;))
|
|
4556 ))
|
|
4557 ;; maybe
|
|
4558 (verilog-re-search-backward "\\<constraint\\|coverpoint\\|cross\\>" nil 'move)
|
|
4559 ;; not
|
|
4560 nil
|
|
4561 )
|
|
4562 )
|
|
4563
|
|
4564 (defun verilog-parenthesis-depth ()
|
|
4565 "Return non zero if in parenthetical-expression."
|
|
4566 (save-excursion
|
|
4567 (nth 1 (parse-partial-sexp (point-min) (point)))))
|
|
4568
|
|
4569
|
|
4570 (defun verilog-skip-forward-comment-or-string ()
|
|
4571 "Return true if in a string or comment."
|
|
4572 (let ((state
|
|
4573 (save-excursion
|
|
4574 (parse-partial-sexp (point-min) (point)))))
|
|
4575 (cond
|
|
4576 ((nth 3 state) ;Inside string
|
|
4577 (goto-char (nth 3 state))
|
|
4578 t)
|
|
4579 ((nth 7 state) ;Inside // comment
|
|
4580 (forward-line 1)
|
|
4581 t)
|
|
4582 ((nth 4 state) ;Inside any comment (hence /**/)
|
|
4583 (search-forward "*/"))
|
|
4584 (t
|
|
4585 nil))))
|
|
4586
|
|
4587 (defun verilog-skip-backward-comment-or-string ()
|
|
4588 "Return true if in a string or comment."
|
|
4589 (let ((state
|
|
4590 (save-excursion
|
|
4591 (parse-partial-sexp (point-min) (point)))))
|
|
4592 (cond
|
|
4593 ((nth 3 state) ;Inside string
|
|
4594 (search-backward "\"")
|
|
4595 t)
|
|
4596 ((nth 7 state) ;Inside // comment
|
|
4597 (search-backward "//")
|
|
4598 (skip-chars-backward "/")
|
|
4599 t)
|
|
4600 ((nth 4 state) ;Inside /* */ comment
|
|
4601 (search-backward "/*")
|
|
4602 t)
|
|
4603 (t
|
|
4604 nil))))
|
|
4605
|
|
4606 (defun verilog-skip-backward-comments ()
|
|
4607 "Return true if a comment was skipped."
|
|
4608 (let ((more t))
|
|
4609 (while more
|
|
4610 (setq more
|
|
4611 (let ((state
|
|
4612 (save-excursion
|
|
4613 (parse-partial-sexp (point-min) (point)))))
|
|
4614 (cond
|
|
4615 ((nth 7 state) ;Inside // comment
|
|
4616 (search-backward "//")
|
|
4617 (skip-chars-backward "/")
|
|
4618 (skip-chars-backward " \t\n\f")
|
|
4619 t)
|
|
4620 ((nth 4 state) ;Inside /* */ comment
|
|
4621 (search-backward "/*")
|
|
4622 (skip-chars-backward " \t\n\f")
|
|
4623 t)
|
|
4624 ((and (not (bobp))
|
|
4625 (= (char-before) ?\/)
|
|
4626 (= (char-before (1- (point))) ?\*)
|
|
4627 )
|
|
4628 (goto-char (- (point) 2))
|
|
4629 t)
|
|
4630 (t
|
|
4631 (skip-chars-backward " \t\n\f")
|
|
4632 nil)))))))
|
|
4633
|
|
4634 (defun verilog-skip-forward-comment-p ()
|
|
4635 "If in comment, move to end and return true."
|
|
4636 (let (state)
|
|
4637 (progn
|
|
4638 (setq state
|
|
4639 (save-excursion
|
|
4640 (parse-partial-sexp (point-min) (point))))
|
|
4641 (cond
|
|
4642 ((nth 3 state)
|
|
4643 t)
|
|
4644 ((nth 7 state) ;Inside // comment
|
|
4645 (end-of-line)
|
|
4646 (forward-char 1)
|
|
4647 t)
|
|
4648 ((nth 4 state) ;Inside any comment
|
|
4649 t)
|
|
4650 (t
|
|
4651 nil)))))
|
|
4652
|
|
4653 (defun verilog-indent-line-relative ()
|
|
4654 "Cheap version of indent line.
|
|
4655 Only look at a few lines to determine indent level."
|
|
4656 (interactive)
|
|
4657 (let ((indent-str)
|
|
4658 (sp (point)))
|
|
4659 (if (looking-at "^[ \t]*$")
|
|
4660 (cond ;- A blank line; No need to be too smart.
|
|
4661 ((bobp)
|
|
4662 (setq indent-str (list 'cpp 0)))
|
|
4663 ((verilog-continued-line)
|
|
4664 (let ((sp1 (point)))
|
|
4665 (if (verilog-continued-line)
|
|
4666 (progn (goto-char sp)
|
|
4667 (setq indent-str (list 'statement (verilog-current-indent-level))))
|
|
4668 (goto-char sp1)
|
|
4669 (setq indent-str (list 'block (verilog-current-indent-level)))))
|
|
4670 (goto-char sp))
|
|
4671 ((goto-char sp)
|
|
4672 (setq indent-str (verilog-calculate-indent))))
|
|
4673 (progn (skip-chars-forward " \t")
|
|
4674 (setq indent-str (verilog-calculate-indent))))
|
|
4675 (verilog-do-indent indent-str)))
|
|
4676
|
|
4677 (defun verilog-indent-line ()
|
|
4678 "Indent for special part of code."
|
|
4679 (verilog-do-indent (verilog-calculate-indent)))
|
|
4680
|
|
4681 (defun verilog-do-indent (indent-str)
|
|
4682 (let ((type (car indent-str))
|
|
4683 (ind (car (cdr indent-str))))
|
|
4684 (cond
|
|
4685 (; handle continued exp
|
|
4686 (eq type 'cexp)
|
|
4687 (let ((here (point)))
|
|
4688 (verilog-backward-syntactic-ws)
|
|
4689 (cond
|
|
4690 ((or
|
|
4691 (= (preceding-char) ?\,)
|
|
4692 (= (preceding-char) ?\])
|
|
4693 (save-excursion
|
|
4694 (verilog-beg-of-statement-1)
|
|
4695 (looking-at verilog-declaration-re)))
|
|
4696 (let* ( fst
|
|
4697 (val
|
|
4698 (save-excursion
|
|
4699 (backward-char 1)
|
|
4700 (verilog-beg-of-statement-1)
|
|
4701 (setq fst (point))
|
|
4702 (if (looking-at verilog-declaration-re)
|
|
4703 (progn ;; we have multiple words
|
|
4704 (goto-char (match-end 0))
|
|
4705 (skip-chars-forward " \t")
|
|
4706 (cond
|
|
4707 ((and verilog-indent-declaration-macros
|
|
4708 (= (following-char) ?\`))
|
|
4709 (progn
|
|
4710 (forward-char 1)
|
|
4711 (forward-word 1)
|
|
4712 (skip-chars-forward " \t")))
|
|
4713 ((= (following-char) ?\[)
|
|
4714 (progn
|
|
4715 (forward-char 1)
|
|
4716 (backward-up-list -1)
|
|
4717 (skip-chars-forward " \t")))
|
|
4718 )
|
|
4719 (current-column))
|
|
4720 (progn
|
|
4721 (goto-char fst)
|
|
4722 (+ (current-column) verilog-cexp-indent))
|
|
4723 ))))
|
|
4724 (goto-char here)
|
|
4725 (indent-line-to val))
|
|
4726 )
|
|
4727 ((= (preceding-char) ?\) )
|
|
4728 (goto-char here)
|
|
4729 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
|
|
4730 (indent-line-to val)))
|
|
4731 (t
|
|
4732 (goto-char here)
|
|
4733 (let ((val))
|
|
4734 (verilog-beg-of-statement-1)
|
|
4735 (if (and (< (point) here)
|
|
4736 (verilog-re-search-forward "=[ \\t]*" here 'move))
|
|
4737 (setq val (current-column))
|
|
4738 (setq val (eval (cdr (assoc type verilog-indent-alist)))))
|
|
4739 (goto-char here)
|
|
4740 (indent-line-to val)))
|
|
4741 )))
|
|
4742
|
|
4743 (; handle inside parenthetical expressions
|
|
4744 (eq type 'cparenexp)
|
|
4745 (let ((val (save-excursion
|
|
4746 (backward-up-list 1)
|
|
4747 (forward-char 1)
|
|
4748 (skip-chars-forward " \t")
|
|
4749 (current-column))))
|
|
4750 (indent-line-to val)
|
|
4751 (if (and (not (verilog-in-struct-region-p))
|
|
4752 (looking-at verilog-declaration-re))
|
|
4753 (verilog-indent-declaration ind))
|
|
4754 ))
|
|
4755
|
|
4756 (;-- Handle the ends
|
|
4757 (or
|
|
4758 (looking-at verilog-end-block-re )
|
|
4759 (verilog-at-close-constraint-p))
|
|
4760 (let ((val (if (eq type 'statement)
|
|
4761 (- ind verilog-indent-level)
|
|
4762 ind)))
|
|
4763 (indent-line-to val)))
|
|
4764
|
|
4765 (;-- Case -- maybe line 'em up
|
|
4766 (and (eq type 'case) (not (looking-at "^[ \t]*$")))
|
|
4767 (progn
|
|
4768 (cond
|
|
4769 ((looking-at "\\<endcase\\>")
|
|
4770 (indent-line-to ind))
|
|
4771 (t
|
|
4772 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
|
|
4773 (indent-line-to val))))))
|
|
4774
|
|
4775 (;-- defun
|
|
4776 (and (eq type 'defun)
|
|
4777 (looking-at verilog-zero-indent-re))
|
|
4778 (indent-line-to 0))
|
|
4779
|
|
4780 (;-- declaration
|
|
4781 (and (or
|
|
4782 (eq type 'defun)
|
|
4783 (eq type 'block))
|
|
4784 (looking-at verilog-declaration-re))
|
|
4785 (verilog-indent-declaration ind))
|
|
4786
|
|
4787 (;-- Everything else
|
|
4788 t
|
|
4789 (let ((val (eval (cdr (assoc type verilog-indent-alist)))))
|
|
4790 (indent-line-to val)))
|
|
4791 )
|
|
4792 (if (looking-at "[ \t]+$")
|
|
4793 (skip-chars-forward " \t"))
|
|
4794 indent-str ; Return indent data
|
|
4795 ))
|
|
4796
|
|
4797 (defun verilog-current-indent-level ()
|
|
4798 "Return the indent-level the current statement has."
|
|
4799 (save-excursion
|
|
4800 (let (par-pos)
|
|
4801 (beginning-of-line)
|
|
4802 (setq par-pos (verilog-parenthesis-depth))
|
|
4803 (while par-pos
|
|
4804 (goto-char par-pos)
|
|
4805 (beginning-of-line)
|
|
4806 (setq par-pos (verilog-parenthesis-depth)))
|
|
4807 (skip-chars-forward " \t")
|
|
4808 (current-column))))
|
|
4809
|
|
4810 (defun verilog-case-indent-level ()
|
|
4811 "Return the indent-level the current statement has.
|
|
4812 Do not count named blocks or case-statements."
|
|
4813 (save-excursion
|
|
4814 (skip-chars-forward " \t")
|
|
4815 (cond
|
|
4816 ((looking-at verilog-named-block-re)
|
|
4817 (current-column))
|
|
4818 ((and (not (looking-at verilog-case-re))
|
|
4819 (looking-at "^[^:;]+[ \t]*:"))
|
|
4820 (verilog-re-search-forward ":" nil t)
|
|
4821 (skip-chars-forward " \t")
|
|
4822 (current-column))
|
|
4823 (t
|
|
4824 (current-column)))))
|
|
4825
|
|
4826 (defun verilog-indent-comment ()
|
|
4827 "Indent current line as comment."
|
|
4828 (let* ((stcol
|
|
4829 (cond
|
|
4830 ((verilog-in-star-comment-p)
|
|
4831 (save-excursion
|
|
4832 (re-search-backward "/\\*" nil t)
|
|
4833 (1+(current-column))))
|
|
4834 (comment-column
|
|
4835 comment-column )
|
|
4836 (t
|
|
4837 (save-excursion
|
|
4838 (re-search-backward "//" nil t)
|
|
4839 (current-column)))
|
|
4840 )))
|
|
4841 (indent-line-to stcol)
|
|
4842 stcol))
|
|
4843
|
|
4844 (defun verilog-more-comment ()
|
|
4845 "Make more comment lines like the previous."
|
|
4846 (let* ((star 0)
|
|
4847 (stcol
|
|
4848 (cond
|
|
4849 ((verilog-in-star-comment-p)
|
|
4850 (save-excursion
|
|
4851 (setq star 1)
|
|
4852 (re-search-backward "/\\*" nil t)
|
|
4853 (1+(current-column))))
|
|
4854 (comment-column
|
|
4855 comment-column )
|
|
4856 (t
|
|
4857 (save-excursion
|
|
4858 (re-search-backward "//" nil t)
|
|
4859 (current-column)))
|
|
4860 )))
|
|
4861 (progn
|
|
4862 (indent-to stcol)
|
|
4863 (if (and star
|
|
4864 (save-excursion
|
|
4865 (forward-line -1)
|
|
4866 (skip-chars-forward " \t")
|
|
4867 (looking-at "\*")))
|
|
4868 (insert "* ")))))
|
|
4869
|
|
4870 (defun verilog-comment-indent (&optional arg)
|
|
4871 "Return the column number the line should be indented to.
|
|
4872 ARG is ignored, for `comment-indent-function' compatibility."
|
|
4873 (cond
|
|
4874 ((verilog-in-star-comment-p)
|
|
4875 (save-excursion
|
|
4876 (re-search-backward "/\\*" nil t)
|
|
4877 (1+(current-column))))
|
|
4878 ( comment-column
|
|
4879 comment-column )
|
|
4880 (t
|
|
4881 (save-excursion
|
|
4882 (re-search-backward "//" nil t)
|
|
4883 (current-column)))))
|
|
4884
|
|
4885 ;;
|
|
4886
|
|
4887 (defun verilog-pretty-declarations ()
|
|
4888 "Line up declarations around point."
|
|
4889 (interactive)
|
|
4890 (save-excursion
|
|
4891 (if (progn
|
|
4892 (verilog-beg-of-statement-1)
|
|
4893 (looking-at verilog-declaration-re))
|
|
4894 (let* ((m1 (make-marker))
|
|
4895 (e) (r)
|
|
4896 (here (point))
|
|
4897 ;; Start of declaration range
|
|
4898 (start
|
|
4899 (progn
|
|
4900 (verilog-beg-of-statement-1)
|
|
4901 (while (looking-at verilog-declaration-re)
|
|
4902 (beginning-of-line)
|
|
4903 (setq e (point))
|
|
4904 (verilog-backward-syntactic-ws)
|
|
4905 (backward-char)
|
|
4906 (verilog-beg-of-statement-1)) ;Ack, need to grok `define
|
|
4907 e))
|
|
4908 ;; End of declaration range
|
|
4909 (end
|
|
4910 (progn
|
|
4911 (goto-char here)
|
|
4912 (verilog-end-of-statement)
|
|
4913 (setq e (point)) ;Might be on last line
|
|
4914 (verilog-forward-syntactic-ws)
|
|
4915 (while (looking-at verilog-declaration-re)
|
|
4916 (beginning-of-line)
|
|
4917 (verilog-end-of-statement)
|
|
4918 (setq e (point))
|
|
4919 (verilog-forward-syntactic-ws))
|
|
4920 e))
|
|
4921 (edpos (set-marker (make-marker) end))
|
|
4922 (ind)
|
|
4923 (base-ind
|
|
4924 (progn
|
|
4925 (goto-char start)
|
|
4926 (verilog-do-indent (verilog-calculate-indent))
|
|
4927 (verilog-forward-ws&directives)
|
|
4928 (current-column)))
|
|
4929 )
|
|
4930 (goto-char end)
|
|
4931 (goto-char start)
|
|
4932 (if (> (- end start) 100)
|
|
4933 (message "Lining up declarations..(please stand by)"))
|
|
4934 ;; Get the beginning of line indent first
|
|
4935 (while (progn (setq e (marker-position edpos))
|
|
4936 (< (point) e))
|
|
4937 (cond
|
|
4938 ( (save-excursion (skip-chars-backward " \t")
|
|
4939 (bolp))
|
|
4940 (verilog-forward-ws&directives)
|
|
4941 (indent-line-to base-ind)
|
|
4942 (verilog-forward-ws&directives)
|
|
4943 (verilog-re-search-forward "[ \t\n\f]" e 'move)
|
|
4944 )
|
|
4945 (t
|
|
4946 (just-one-space)
|
|
4947 (verilog-re-search-forward "[ \t\n\f]" e 'move)
|
|
4948 )
|
|
4949 )
|
|
4950 )
|
|
4951 ;;(forward-line))
|
|
4952 ;; Now find biggest prefix
|
|
4953 (setq ind (verilog-get-lineup-indent start edpos))
|
|
4954 ;; Now indent each line.
|
|
4955 (goto-char start)
|
|
4956 (while (progn (setq e (marker-position edpos))
|
|
4957 (setq r (- e (point)))
|
|
4958 (> r 0))
|
|
4959 (setq e (point))
|
|
4960 (message "%d" r)
|
|
4961 (cond
|
|
4962 ((or (and verilog-indent-declaration-macros
|
|
4963 (looking-at verilog-declaration-re-1-macro))
|
|
4964 (looking-at verilog-declaration-re-1-no-macro))
|
|
4965 (let ((p (match-end 0)))
|
|
4966 (set-marker m1 p)
|
|
4967 (if (verilog-re-search-forward "[[#`]" p 'move)
|
|
4968 (progn
|
|
4969 (forward-char -1)
|
|
4970 (just-one-space)
|
|
4971 (goto-char (marker-position m1))
|
|
4972 (just-one-space)
|
|
4973 (indent-to ind))
|
|
4974 (progn
|
|
4975 (just-one-space)
|
|
4976 (indent-to ind))
|
|
4977 )))
|
|
4978 ((verilog-continued-line-1 start)
|
|
4979 (goto-char e)
|
|
4980 (indent-line-to ind))
|
|
4981 (t ; Must be comment or white space
|
|
4982 (goto-char e)
|
|
4983 (verilog-forward-ws&directives)
|
|
4984 (forward-line -1))
|
|
4985 )
|
|
4986 (forward-line 1))
|
|
4987 (message "")))))
|
|
4988
|
|
4989 (defun verilog-pretty-expr (&optional myre)
|
|
4990 "Line up expressions around point."
|
|
4991 (interactive "sRegular Expression: ((<|:)?=) ")
|
|
4992 (save-excursion
|
|
4993 (if (or (eq myre nil)
|
|
4994 (string-equal myre ""))
|
|
4995 (setq myre "\\(<\\|:\\)?="))
|
|
4996 ; (setq myre (concat "\\(^[^;" myre "]*\\)\\([" myre "]\\)"))
|
|
4997 (setq myre (concat "\\(^[^;#:?=]*\\)\\([" myre "]\\)"))
|
|
4998 (beginning-of-line)
|
|
4999 (if (and (not (looking-at (concat "^\\s-*" verilog-complete-reg)))
|
|
5000 (looking-at myre))
|
|
5001 (let* ((here (point))
|
|
5002 (e) (r)
|
|
5003 (start
|
|
5004 (progn
|
|
5005 (beginning-of-line)
|
|
5006 (setq e (point))
|
|
5007 (verilog-backward-syntactic-ws)
|
|
5008 (beginning-of-line)
|
|
5009 (while (and (not (looking-at (concat "^\\s-*" verilog-complete-reg)))
|
|
5010 (looking-at myre)
|
|
5011 (not (bobp))
|
|
5012 )
|
|
5013 (setq e (point))
|
|
5014 (verilog-backward-syntactic-ws)
|
|
5015 (beginning-of-line)
|
|
5016 ) ;Ack, need to grok `define
|
|
5017 e))
|
|
5018 (end
|
|
5019 (progn
|
|
5020 (goto-char here)
|
|
5021 (end-of-line)
|
|
5022 (setq e (point)) ;Might be on last line
|
|
5023 (verilog-forward-syntactic-ws)
|
|
5024 (beginning-of-line)
|
|
5025 (while (and (not(looking-at (concat "^\\s-*" verilog-complete-reg)))
|
|
5026 (looking-at myre))
|
|
5027 (end-of-line)
|
|
5028 (setq e (point))
|
|
5029 (verilog-forward-syntactic-ws)
|
|
5030 (beginning-of-line)
|
|
5031 )
|
|
5032 e))
|
|
5033 (edpos (set-marker (make-marker) end))
|
|
5034 (ind)
|
|
5035 )
|
|
5036 (goto-char start)
|
|
5037 (verilog-do-indent (verilog-calculate-indent))
|
|
5038 (if (> (- end start) 100)
|
|
5039 (message "Lining up expressions..(please stand by)"))
|
|
5040
|
|
5041 ;; Set indent to minimum throughout region
|
|
5042 (while (< (point) (marker-position edpos))
|
|
5043 (beginning-of-line)
|
|
5044 (verilog-just-one-space myre)
|
|
5045 (end-of-line)
|
|
5046 (verilog-forward-syntactic-ws)
|
|
5047 )
|
|
5048
|
|
5049 ;; Now find biggest prefix
|
|
5050 (setq ind (verilog-get-lineup-indent-2 myre start edpos))
|
|
5051
|
|
5052 ;; Now indent each line.
|
|
5053 (goto-char start)
|
|
5054 (while (progn (setq e (marker-position edpos))
|
|
5055 (setq r (- e (point)))
|
|
5056 (> r 0))
|
|
5057 (setq e (point))
|
|
5058 (message "%d" r)
|
|
5059 (cond
|
|
5060 ((looking-at myre)
|
|
5061 (goto-char (match-end 1))
|
|
5062 (if (eq (char-after) ?=)
|
|
5063 (indent-to (1+ ind)) ; line up the = of the <= with surrounding =
|
|
5064 (indent-to ind)
|
|
5065 )
|
|
5066 )
|
|
5067 ((verilog-continued-line-1 start)
|
|
5068 (goto-char e)
|
|
5069 (indent-line-to ind))
|
|
5070 (t ; Must be comment or white space
|
|
5071 (goto-char e)
|
|
5072 (verilog-forward-ws&directives)
|
|
5073 (forward-line -1))
|
|
5074 )
|
|
5075 (forward-line 1))
|
|
5076 (message "")
|
|
5077 ))))
|
|
5078
|
|
5079 (defun verilog-just-one-space (myre)
|
|
5080 "Remove extra spaces around regular expression MYRE."
|
|
5081 (interactive)
|
|
5082 (if (and (not(looking-at verilog-complete-reg))
|
|
5083 (looking-at myre))
|
|
5084 (let ((p1 (match-end 1))
|
|
5085 (p2 (match-end 2)))
|
|
5086 (progn
|
|
5087 (goto-char p2)
|
|
5088 (if (looking-at "\\s-") (just-one-space) )
|
|
5089 (goto-char p1)
|
|
5090 (forward-char -1)
|
|
5091 (if (looking-at "\\s-") (just-one-space))
|
|
5092 )
|
|
5093 ))
|
|
5094 (message ""))
|
|
5095
|
|
5096 (defun verilog-indent-declaration (baseind)
|
|
5097 "Indent current lines as declaration.
|
|
5098 Line up the variable names based on previous declaration's indentation.
|
|
5099 BASEIND is the base indent to offset everything."
|
|
5100 (interactive)
|
|
5101 (let ((pos (point-marker))
|
|
5102 (lim (save-excursion
|
|
5103 ;; (verilog-re-search-backward verilog-declaration-opener nil 'move)
|
|
5104 (verilog-re-search-backward "\\(\\<begin\\>\\)\\|\\(\\<module\\>\\)\\|\\(\\<task\\>\\)" nil 'move)
|
|
5105 (point)))
|
|
5106 (ind)
|
|
5107 (val)
|
|
5108 (m1 (make-marker))
|
|
5109 )
|
|
5110 (setq val (+ baseind (eval (cdr (assoc 'declaration verilog-indent-alist)))))
|
|
5111 (indent-line-to val)
|
|
5112
|
|
5113 ;; Use previous declaration (in this module) as template.
|
|
5114 (if (or (memq 'all verilog-auto-lineup)
|
|
5115 (memq 'declaration verilog-auto-lineup))
|
79546
|
5116 (if (verilog-re-search-backward
|
79545
|
5117 (or (and verilog-indent-declaration-macros
|
|
5118 verilog-declaration-re-1-macro)
|
|
5119 verilog-declaration-re-1-no-macro) lim t)
|
|
5120 (progn
|
|
5121 (goto-char (match-end 0))
|
|
5122 (skip-chars-forward " \t")
|
|
5123 (setq ind (current-column))
|
|
5124 (goto-char pos)
|
|
5125 (setq val (+ baseind (eval (cdr (assoc 'declaration verilog-indent-alist)))))
|
|
5126 (indent-line-to val)
|
|
5127 (if (and verilog-indent-declaration-macros
|
|
5128 (looking-at verilog-declaration-re-2-macro))
|
|
5129 (let ((p (match-end 0)))
|
|
5130 (set-marker m1 p)
|
|
5131 (if (verilog-re-search-forward "[[#`]" p 'move)
|
|
5132 (progn
|
|
5133 (forward-char -1)
|
|
5134 (just-one-space)
|
|
5135 (goto-char (marker-position m1))
|
|
5136 (just-one-space)
|
|
5137 (indent-to ind)
|
|
5138 )
|
|
5139 (if (/= (current-column) ind)
|
|
5140 (progn
|
|
5141 (just-one-space)
|
|
5142 (indent-to ind))
|
|
5143 )))
|
|
5144 (if (looking-at verilog-declaration-re-2-no-macro)
|
|
5145 (let ((p (match-end 0)))
|
|
5146 (set-marker m1 p)
|
|
5147 (if (verilog-re-search-forward "[[`#]" p 'move)
|
|
5148 (progn
|
|
5149 (forward-char -1)
|
|
5150 (just-one-space)
|
|
5151 (goto-char (marker-position m1))
|
|
5152 (just-one-space)
|
|
5153 (indent-to ind))
|
|
5154 (if (/= (current-column) ind)
|
|
5155 (progn
|
|
5156 (just-one-space)
|
|
5157 (indent-to ind))
|
|
5158 )))
|
|
5159 )))
|
|
5160 )
|
|
5161 )
|
|
5162 (goto-char pos)
|
|
5163 )
|
|
5164 )
|
|
5165
|
|
5166 (defun verilog-get-lineup-indent (b edpos)
|
|
5167 "Return the indent level that will line up several lines within the region.
|
|
5168 Region is defined by B and EDPOS."
|
|
5169 (save-excursion
|
|
5170 (let ((ind 0) e)
|
|
5171 (goto-char b)
|
|
5172 ;; Get rightmost position
|
|
5173 (while (progn (setq e (marker-position edpos))
|
|
5174 (< (point) e))
|
79546
|
5175 (if (verilog-re-search-forward
|
79545
|
5176 (or (and verilog-indent-declaration-macros
|
|
5177 verilog-declaration-re-1-macro)
|
|
5178 verilog-declaration-re-1-no-macro) e 'move)
|
|
5179 (progn
|
|
5180 (goto-char (match-end 0))
|
|
5181 (verilog-backward-syntactic-ws)
|
|
5182 (if (> (current-column) ind)
|
|
5183 (setq ind (current-column)))
|
|
5184 (goto-char (match-end 0)))))
|
|
5185 (if (> ind 0)
|
|
5186 (1+ ind)
|
|
5187 ;; No lineup-string found
|
|
5188 (goto-char b)
|
|
5189 (end-of-line)
|
|
5190 (skip-chars-backward " \t")
|
|
5191 (1+ (current-column))))))
|
|
5192
|
|
5193 (defun verilog-get-lineup-indent-2 (myre b edpos)
|
|
5194 "Return the indent level that will line up several lines within the region."
|
|
5195 (save-excursion
|
|
5196 (let ((ind 0) e)
|
|
5197 (goto-char b)
|
|
5198 ;; Get rightmost position
|
|
5199 (while (progn (setq e (marker-position edpos))
|
|
5200 (< (point) e))
|
|
5201 (if (verilog-re-search-forward myre e 'move)
|
|
5202 (progn
|
|
5203 (goto-char (match-end 0))
|
|
5204 (verilog-backward-syntactic-ws)
|
|
5205 (if (> (current-column) ind)
|
|
5206 (setq ind (current-column)))
|
|
5207 (goto-char (match-end 0)))))
|
|
5208 (if (> ind 0)
|
|
5209 (1+ ind)
|
|
5210 ;; No lineup-string found
|
|
5211 (goto-char b)
|
|
5212 (end-of-line)
|
|
5213 (skip-chars-backward " \t")
|
|
5214 (1+ (current-column))))))
|
|
5215
|
|
5216 (defun verilog-comment-depth (type val)
|
|
5217 "A useful mode debugging aide. TYPE and VAL are comments for insertion."
|
|
5218 (save-excursion
|
|
5219 (let
|
|
5220 ((b (prog2
|
|
5221 (beginning-of-line)
|
|
5222 (point-marker)
|
|
5223 (end-of-line)))
|
|
5224 (e (point-marker)))
|
|
5225 (if (re-search-backward " /\\* \[#-\]# \[a-zA-Z\]+ \[0-9\]+ ## \\*/" b t)
|
|
5226 (progn
|
|
5227 (replace-match " /* -# ## */")
|
|
5228 (end-of-line))
|
|
5229 (progn
|
|
5230 (end-of-line)
|
|
5231 (insert " /* ## ## */"))))
|
|
5232 (backward-char 6)
|
|
5233 (insert
|
|
5234 (format "%s %d" type val))))
|
|
5235
|
|
5236 ;;
|
|
5237 ;;
|
|
5238 ;; Completion
|
|
5239 ;;
|
|
5240 (defvar verilog-str nil)
|
|
5241 (defvar verilog-all nil)
|
|
5242 (defvar verilog-pred nil)
|
|
5243 (defvar verilog-buffer-to-use nil)
|
|
5244 (defvar verilog-flag nil)
|
|
5245 (defvar verilog-toggle-completions nil
|
|
5246 "*True means \\<verilog-mode-map>\\[verilog-complete-word] should try all possible completions one by one.
|
|
5247 Repeated use of \\[verilog-complete-word] will show you all of them.
|
|
5248 Normally, when there is more than one possible completion,
|
|
5249 it displays a list of all possible completions.")
|
|
5250
|
|
5251
|
|
5252 (defvar verilog-type-keywords
|
|
5253 '(
|
|
5254 "and" "buf" "bufif0" "bufif1" "cmos" "defparam" "inout" "input"
|
|
5255 "integer" "localparam" "logic" "mailbox" "nand" "nmos" "nor" "not" "notif0"
|
|
5256 "notif1" "or" "output" "parameter" "pmos" "pull0" "pull1" "pullup"
|
|
5257 "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran" "rtranif0"
|
|
5258 "rtranif1" "semaphore" "time" "tran" "tranif0" "tranif1" "tri" "tri0" "tri1"
|
|
5259 "triand" "trior" "trireg" "wand" "wire" "wor" "xnor" "xor"
|
|
5260 )
|
|
5261 "*Keywords for types used when completing a word in a declaration or parmlist.
|
|
5262 \(eg. integer, real, reg...)")
|
|
5263
|
|
5264 (defvar verilog-cpp-keywords
|
|
5265 '("module" "macromodule" "primitive" "timescale" "define" "ifdef" "ifndef" "else"
|
|
5266 "endif")
|
|
5267 "*Keywords to complete when at first word of a line in declarative scope.
|
|
5268 \(eg. initial, always, begin, assign.)
|
|
5269 The procedures and variables defined within the Verilog program
|
|
5270 will be completed runtime and should not be added to this list.")
|
|
5271
|
|
5272 (defvar verilog-defun-keywords
|
|
5273 (append
|
|
5274 '(
|
|
5275 "always" "always_comb" "always_ff" "always_latch" "assign"
|
|
5276 "begin" "end" "generate" "endgenerate" "module" "endmodule"
|
|
5277 "specify" "endspecify" "function" "endfunction" "initial" "final"
|
|
5278 "task" "endtask" "primitive" "endprimitive"
|
|
5279 )
|
|
5280 verilog-type-keywords)
|
|
5281 "*Keywords to complete when at first word of a line in declarative scope.
|
|
5282 \(eg. initial, always, begin, assign.)
|
|
5283 The procedures and variables defined within the Verilog program
|
|
5284 will be completed runtime and should not be added to this list.")
|
|
5285
|
|
5286 (defvar verilog-block-keywords
|
|
5287 '(
|
|
5288 "begin" "break" "case" "continue" "else" "end" "endfunction"
|
|
5289 "endgenerate" "endinterface" "endpackage" "endspecify" "endtask"
|
|
5290 "for" "fork" "if" "join" "join_any" "join_none" "repeat" "return"
|
|
5291 "while")
|
|
5292 "*Keywords to complete when at first word of a line in behavioral scope.
|
|
5293 \(eg. begin, if, then, else, for, fork.)
|
|
5294 The procedures and variables defined within the Verilog program
|
|
5295 will be completed runtime and should not be added to this list.")
|
|
5296
|
|
5297 (defvar verilog-tf-keywords
|
|
5298 '("begin" "break" "fork" "join" "join_any" "join_none" "case" "end" "endtask" "endfunction" "if" "else" "for" "while" "repeat")
|
|
5299 "*Keywords to complete when at first word of a line in a task or function.
|
|
5300 \(eg. begin, if, then, else, for, fork.)
|
|
5301 The procedures and variables defined within the Verilog program
|
|
5302 will be completed runtime and should not be added to this list.")
|
|
5303
|
|
5304 (defvar verilog-case-keywords
|
|
5305 '("begin" "fork" "join" "join_any" "join_none" "case" "end" "endcase" "if" "else" "for" "repeat")
|
|
5306 "*Keywords to complete when at first word of a line in case scope.
|
|
5307 \(eg. begin, if, then, else, for, fork.)
|
|
5308 The procedures and variables defined within the Verilog program
|
|
5309 will be completed runtime and should not be added to this list.")
|
|
5310
|
|
5311 (defvar verilog-separator-keywords
|
|
5312 '("else" "then" "begin")
|
|
5313 "*Keywords to complete when NOT standing at the first word of a statement.
|
|
5314 \(eg. else, then.)
|
|
5315 Variables and function names defined within the
|
|
5316 Verilog program are completed runtime and should not be added to this list.")
|
|
5317
|
|
5318 (defun verilog-string-diff (str1 str2)
|
|
5319 "Return index of first letter where STR1 and STR2 differs."
|
|
5320 (catch 'done
|
|
5321 (let ((diff 0))
|
|
5322 (while t
|
|
5323 (if (or (> (1+ diff) (length str1))
|
|
5324 (> (1+ diff) (length str2)))
|
|
5325 (throw 'done diff))
|
|
5326 (or (equal (aref str1 diff) (aref str2 diff))
|
|
5327 (throw 'done diff))
|
|
5328 (setq diff (1+ diff))))))
|
|
5329
|
|
5330 ;; Calculate all possible completions for functions if argument is `function',
|
|
5331 ;; completions for procedures if argument is `procedure' or both functions and
|
|
5332 ;; procedures otherwise.
|
|
5333
|
|
5334 (defun verilog-func-completion (type)
|
|
5335 "Build regular expression for module/task/function names.
|
|
5336 TYPE is 'module, 'tf for task or function, or t if unknown."
|
|
5337 (if (string= verilog-str "")
|
|
5338 (setq verilog-str "[a-zA-Z_]"))
|
|
5339 (let ((verilog-str (concat (cond
|
|
5340 ((eq type 'module) "\\<\\(module\\)\\s +")
|
|
5341 ((eq type 'tf) "\\<\\(task\\|function\\)\\s +")
|
|
5342 (t "\\<\\(task\\|function\\|module\\)\\s +"))
|
|
5343 "\\<\\(" verilog-str "[a-zA-Z0-9_.]*\\)\\>"))
|
|
5344 match)
|
|
5345
|
|
5346 (if (not (looking-at verilog-defun-re))
|
|
5347 (verilog-re-search-backward verilog-defun-re nil t))
|
|
5348 (forward-char 1)
|
|
5349
|
|
5350 ;; Search through all reachable functions
|
|
5351 (goto-char (point-min))
|
|
5352 (while (verilog-re-search-forward verilog-str (point-max) t)
|
|
5353 (progn (setq match (buffer-substring (match-beginning 2)
|
|
5354 (match-end 2)))
|
|
5355 (if (or (null verilog-pred)
|
|
5356 (funcall verilog-pred match))
|
|
5357 (setq verilog-all (cons match verilog-all)))))
|
|
5358 (if (match-beginning 0)
|
|
5359 (goto-char (match-beginning 0)))))
|
|
5360
|
|
5361 (defun verilog-get-completion-decl (end)
|
|
5362 "Macro for searching through current declaration (var, type or const)
|
|
5363 for matches of `str' and adding the occurrence tp `all' through point END."
|
|
5364 (let ((re (or (and verilog-indent-declaration-macros
|
|
5365 verilog-declaration-re-2-macro)
|
|
5366 verilog-declaration-re-2-no-macro))
|
|
5367 decl-end match)
|
|
5368 ;; Traverse lines
|
|
5369 (while (and (< (point) end)
|
|
5370 (verilog-re-search-forward re end t))
|
|
5371 ;; Traverse current line
|
|
5372 (setq decl-end (save-excursion (verilog-declaration-end)))
|
|
5373 (while (and (verilog-re-search-forward verilog-symbol-re decl-end t)
|
|
5374 (not (match-end 1)))
|
|
5375 (setq match (buffer-substring (match-beginning 0) (match-end 0)))
|
|
5376 (if (string-match (concat "\\<" verilog-str) match)
|
|
5377 (if (or (null verilog-pred)
|
|
5378 (funcall verilog-pred match))
|
|
5379 (setq verilog-all (cons match verilog-all)))))
|
|
5380 (forward-line 1)
|
|
5381 )
|
|
5382 )
|
|
5383 verilog-all
|
|
5384 )
|
|
5385
|
|
5386 (defun verilog-type-completion ()
|
|
5387 "Calculate all possible completions for types."
|
|
5388 (let ((start (point))
|
|
5389 goon)
|
|
5390 ;; Search for all reachable type declarations
|
|
5391 (while (or (verilog-beg-of-defun)
|
|
5392 (setq goon (not goon)))
|
|
5393 (save-excursion
|
|
5394 (if (and (< start (prog1 (save-excursion (verilog-end-of-defun)
|
|
5395 (point))
|
|
5396 (forward-char 1)))
|
|
5397 (verilog-re-search-forward
|
|
5398 "\\<type\\>\\|\\<\\(begin\\|function\\|procedure\\)\\>"
|
|
5399 start t)
|
|
5400 (not (match-end 1)))
|
|
5401 ;; Check current type declaration
|
|
5402 (verilog-get-completion-decl start))))))
|
|
5403
|
|
5404 (defun verilog-var-completion ()
|
|
5405 "Calculate all possible completions for variables (or constants)."
|
|
5406 (let ((start (point)))
|
|
5407 ;; Search for all reachable var declarations
|
|
5408 (verilog-beg-of-defun)
|
|
5409 (save-excursion
|
|
5410 ;; Check var declarations
|
|
5411 (verilog-get-completion-decl start))))
|
|
5412
|
|
5413 (defun verilog-keyword-completion (keyword-list)
|
|
5414 "Give list of all possible completions of keywords in KEYWORD-LIST."
|
|
5415 (mapcar '(lambda (s)
|
|
5416 (if (string-match (concat "\\<" verilog-str) s)
|
|
5417 (if (or (null verilog-pred)
|
|
5418 (funcall verilog-pred s))
|
|
5419 (setq verilog-all (cons s verilog-all)))))
|
|
5420 keyword-list))
|
|
5421
|
|
5422
|
|
5423 (defun verilog-completion (verilog-str verilog-pred verilog-flag)
|
|
5424 "Function passed to `completing-read', `try-completion' or `all-completions'.
|
|
5425 Called to get completion on VERILOG-STR. If VERILOG-PRED is non-nil, it
|
|
5426 must be a function to be called for every match to check if this should
|
|
5427 really be a match. If VERILOG-FLAG is t, the function returns a list of all
|
|
5428 possible completions. If VERILOG-FLAG is nil it returns a string, the
|
|
5429 longest possible completion, or t if STR is an exact match. If VERILOG-FLAG
|
|
5430 is 'lambda, the function returns t if STR is an exact match, nil
|
|
5431 otherwise."
|
|
5432 (save-excursion
|
|
5433 (let ((verilog-all nil))
|
|
5434 ;; Set buffer to use for searching labels. This should be set
|
|
5435 ;; within functions which use verilog-completions
|
|
5436 (set-buffer verilog-buffer-to-use)
|
|
5437
|
|
5438 ;; Determine what should be completed
|
|
5439 (let ((state (car (verilog-calculate-indent))))
|
|
5440 (cond ((eq state 'defun)
|
|
5441 (save-excursion (verilog-var-completion))
|
|
5442 (verilog-func-completion 'module)
|
|
5443 (verilog-keyword-completion verilog-defun-keywords))
|
|
5444
|
|
5445 ((eq state 'behavioral)
|
|
5446 (save-excursion (verilog-var-completion))
|
|
5447 (verilog-func-completion 'module)
|
|
5448 (verilog-keyword-completion verilog-defun-keywords))
|
|
5449
|
|
5450 ((eq state 'block)
|
|
5451 (save-excursion (verilog-var-completion))
|
|
5452 (verilog-func-completion 'tf)
|
|
5453 (verilog-keyword-completion verilog-block-keywords))
|
|
5454
|
|
5455 ((eq state 'case)
|
|
5456 (save-excursion (verilog-var-completion))
|
|
5457 (verilog-func-completion 'tf)
|
|
5458 (verilog-keyword-completion verilog-case-keywords))
|
|
5459
|
|
5460 ((eq state 'tf)
|
|
5461 (save-excursion (verilog-var-completion))
|
|
5462 (verilog-func-completion 'tf)
|
|
5463 (verilog-keyword-completion verilog-tf-keywords))
|
|
5464
|
|
5465 ((eq state 'cpp)
|
|
5466 (save-excursion (verilog-var-completion))
|
|
5467 (verilog-keyword-completion verilog-cpp-keywords))
|
|
5468
|
|
5469 ((eq state 'cparenexp)
|
|
5470 (save-excursion (verilog-var-completion)))
|
|
5471
|
|
5472 (t;--Anywhere else
|
|
5473 (save-excursion (verilog-var-completion))
|
|
5474 (verilog-func-completion 'both)
|
|
5475 (verilog-keyword-completion verilog-separator-keywords))))
|
|
5476
|
|
5477 ;; Now we have built a list of all matches. Give response to caller
|
|
5478 (verilog-completion-response))))
|
|
5479
|
|
5480 (defun verilog-completion-response ()
|
|
5481 (cond ((or (equal verilog-flag 'lambda) (null verilog-flag))
|
|
5482 ;; This was not called by all-completions
|
|
5483 (if (null verilog-all)
|
|
5484 ;; Return nil if there was no matching label
|
|
5485 nil
|
|
5486 ;; Get longest string common in the labels
|
|
5487 (let* ((elm (cdr verilog-all))
|
|
5488 (match (car verilog-all))
|
|
5489 (min (length match))
|
|
5490 tmp)
|
|
5491 (if (string= match verilog-str)
|
|
5492 ;; Return t if first match was an exact match
|
|
5493 (setq match t)
|
|
5494 (while (not (null elm))
|
|
5495 ;; Find longest common string
|
|
5496 (if (< (setq tmp (verilog-string-diff match (car elm))) min)
|
|
5497 (progn
|
|
5498 (setq min tmp)
|
|
5499 (setq match (substring match 0 min))))
|
|
5500 ;; Terminate with match=t if this is an exact match
|
|
5501 (if (string= (car elm) verilog-str)
|
|
5502 (progn
|
|
5503 (setq match t)
|
|
5504 (setq elm nil))
|
|
5505 (setq elm (cdr elm)))))
|
|
5506 ;; If this is a test just for exact match, return nil ot t
|
|
5507 (if (and (equal verilog-flag 'lambda) (not (equal match 't)))
|
|
5508 nil
|
|
5509 match))))
|
|
5510 ;; If flag is t, this was called by all-completions. Return
|
|
5511 ;; list of all possible completions
|
|
5512 (verilog-flag
|
|
5513 verilog-all)))
|
|
5514
|
|
5515 (defvar verilog-last-word-numb 0)
|
|
5516 (defvar verilog-last-word-shown nil)
|
|
5517 (defvar verilog-last-completions nil)
|
|
5518
|
|
5519 (defun verilog-complete-word ()
|
|
5520 "Complete word at current point.
|
|
5521 \(See also `verilog-toggle-completions', `verilog-type-keywords',
|
|
5522 and `verilog-separator-keywords'.)"
|
|
5523 (interactive)
|
|
5524 (let* ((b (save-excursion (skip-chars-backward "a-zA-Z0-9_") (point)))
|
|
5525 (e (save-excursion (skip-chars-forward "a-zA-Z0-9_") (point)))
|
|
5526 (verilog-str (buffer-substring b e))
|
|
5527 ;; The following variable is used in verilog-completion
|
|
5528 (verilog-buffer-to-use (current-buffer))
|
|
5529 (allcomp (if (and verilog-toggle-completions
|
|
5530 (string= verilog-last-word-shown verilog-str))
|
|
5531 verilog-last-completions
|
|
5532 (all-completions verilog-str 'verilog-completion)))
|
|
5533 (match (if verilog-toggle-completions
|
|
5534 "" (try-completion
|
|
5535 verilog-str (mapcar '(lambda (elm)
|
|
5536 (cons elm 0)) allcomp)))))
|
|
5537 ;; Delete old string
|
|
5538 (delete-region b e)
|
|
5539
|
|
5540 ;; Toggle-completions inserts whole labels
|
|
5541 (if verilog-toggle-completions
|
|
5542 (progn
|
|
5543 ;; Update entry number in list
|
|
5544 (setq verilog-last-completions allcomp
|
|
5545 verilog-last-word-numb
|
|
5546 (if (>= verilog-last-word-numb (1- (length allcomp)))
|
|
5547 0
|
|
5548 (1+ verilog-last-word-numb)))
|
|
5549 (setq verilog-last-word-shown (elt allcomp verilog-last-word-numb))
|
|
5550 ;; Display next match or same string if no match was found
|
|
5551 (if (not (null allcomp))
|
|
5552 (insert "" verilog-last-word-shown)
|
|
5553 (insert "" verilog-str)
|
|
5554 (message "(No match)")))
|
|
5555 ;; The other form of completion does not necessarily do that.
|
|
5556
|
|
5557 ;; Insert match if found, or the original string if no match
|
|
5558 (if (or (null match) (equal match 't))
|
|
5559 (progn (insert "" verilog-str)
|
|
5560 (message "(No match)"))
|
|
5561 (insert "" match))
|
|
5562 ;; Give message about current status of completion
|
|
5563 (cond ((equal match 't)
|
|
5564 (if (not (null (cdr allcomp)))
|
|
5565 (message "(Complete but not unique)")
|
|
5566 (message "(Sole completion)")))
|
|
5567 ;; Display buffer if the current completion didn't help
|
|
5568 ;; on completing the label.
|
|
5569 ((and (not (null (cdr allcomp))) (= (length verilog-str)
|
|
5570 (length match)))
|
|
5571 (with-output-to-temp-buffer "*Completions*"
|
|
5572 (display-completion-list allcomp))
|
|
5573 ;; Wait for a key press. Then delete *Completion* window
|
|
5574 (momentary-string-display "" (point))
|
|
5575 (delete-window (get-buffer-window (get-buffer "*Completions*")))
|
|
5576 )))))
|
|
5577
|
|
5578 (defun verilog-show-completions ()
|
|
5579 "Show all possible completions at current point."
|
|
5580 (interactive)
|
|
5581 (let* ((b (save-excursion (skip-chars-backward "a-zA-Z0-9_") (point)))
|
|
5582 (e (save-excursion (skip-chars-forward "a-zA-Z0-9_") (point)))
|
|
5583 (verilog-str (buffer-substring b e))
|
|
5584 ;; The following variable is used in verilog-completion
|
|
5585 (verilog-buffer-to-use (current-buffer))
|
|
5586 (allcomp (if (and verilog-toggle-completions
|
|
5587 (string= verilog-last-word-shown verilog-str))
|
|
5588 verilog-last-completions
|
|
5589 (all-completions verilog-str 'verilog-completion))))
|
|
5590 ;; Show possible completions in a temporary buffer.
|
|
5591 (with-output-to-temp-buffer "*Completions*"
|
|
5592 (display-completion-list allcomp))
|
|
5593 ;; Wait for a key press. Then delete *Completion* window
|
|
5594 (momentary-string-display "" (point))
|
|
5595 (delete-window (get-buffer-window (get-buffer "*Completions*")))))
|
|
5596
|
|
5597
|
|
5598 (defun verilog-get-default-symbol ()
|
|
5599 "Return symbol around current point as a string."
|
|
5600 (save-excursion
|
|
5601 (buffer-substring (progn
|
|
5602 (skip-chars-backward " \t")
|
|
5603 (skip-chars-backward "a-zA-Z0-9_")
|
|
5604 (point))
|
|
5605 (progn
|
|
5606 (skip-chars-forward "a-zA-Z0-9_")
|
|
5607 (point)))))
|
|
5608
|
|
5609 (defun verilog-build-defun-re (str &optional arg)
|
|
5610 "Return function/task/module starting with STR as regular expression.
|
|
5611 With optional second ARG non-nil, STR is the complete name of the instruction."
|
|
5612 (if arg
|
|
5613 (concat "^\\(function\\|task\\|module\\)[ \t]+\\(" str "\\)\\>")
|
|
5614 (concat "^\\(function\\|task\\|module\\)[ \t]+\\(" str "[a-zA-Z0-9_]*\\)\\>")))
|
|
5615
|
|
5616 (defun verilog-comp-defun (verilog-str verilog-pred verilog-flag)
|
|
5617 "Function passed to `completing-read', `try-completion' or `all-completions'.
|
|
5618 Returns a completion on any function name based on VERILOG-STR prefix. If
|
|
5619 VERILOG-PRED is non-nil, it must be a function to be called for every match
|
|
5620 to check if this should really be a match. If VERILOG-FLAG is t, the
|
|
5621 function returns a list of all possible completions. If it is nil it
|
|
5622 returns a string, the longest possible completion, or t if VERILOG-STR is
|
|
5623 an exact match. If VERILOG-FLAG is 'lambda, the function returns t if
|
|
5624 VERILOG-STR is an exact match, nil otherwise."
|
|
5625 (save-excursion
|
|
5626 (let ((verilog-all nil)
|
|
5627 match)
|
|
5628
|
|
5629 ;; Set buffer to use for searching labels. This should be set
|
|
5630 ;; within functions which use verilog-completions
|
|
5631 (set-buffer verilog-buffer-to-use)
|
|
5632
|
|
5633 (let ((verilog-str verilog-str))
|
|
5634 ;; Build regular expression for functions
|
|
5635 (if (string= verilog-str "")
|
|
5636 (setq verilog-str (verilog-build-defun-re "[a-zA-Z_]"))
|
|
5637 (setq verilog-str (verilog-build-defun-re verilog-str)))
|
|
5638 (goto-char (point-min))
|
|
5639
|
|
5640 ;; Build a list of all possible completions
|
|
5641 (while (verilog-re-search-forward verilog-str nil t)
|
|
5642 (setq match (buffer-substring (match-beginning 2) (match-end 2)))
|
|
5643 (if (or (null verilog-pred)
|
|
5644 (funcall verilog-pred match))
|
|
5645 (setq verilog-all (cons match verilog-all)))))
|
|
5646
|
|
5647 ;; Now we have built a list of all matches. Give response to caller
|
|
5648 (verilog-completion-response))))
|
|
5649
|
|
5650 (defun verilog-goto-defun ()
|
|
5651 "Move to specified Verilog module/task/function.
|
|
5652 The default is a name found in the buffer around point.
|
|
5653 If search fails, other files are checked based on
|
|
5654 `verilog-library-flags'."
|
|
5655 (interactive)
|
|
5656 (let* ((default (verilog-get-default-symbol))
|
|
5657 ;; The following variable is used in verilog-comp-function
|
|
5658 (verilog-buffer-to-use (current-buffer))
|
|
5659 (label (if (not (string= default ""))
|
|
5660 ;; Do completion with default
|
|
5661 (completing-read (concat "Label: (default " default ") ")
|
|
5662 'verilog-comp-defun nil nil "")
|
|
5663 ;; There is no default value. Complete without it
|
|
5664 (completing-read "Label: "
|
|
5665 'verilog-comp-defun nil nil "")))
|
|
5666 pt)
|
|
5667 ;; If there was no response on prompt, use default value
|
|
5668 (if (string= label "")
|
|
5669 (setq label default))
|
|
5670 ;; Goto right place in buffer if label is not an empty string
|
|
5671 (or (string= label "")
|
|
5672 (progn
|
|
5673 (save-excursion
|
|
5674 (goto-char (point-min))
|
|
5675 (setq pt (re-search-forward (verilog-build-defun-re label t) nil t)))
|
|
5676 (when pt
|
|
5677 (goto-char pt)
|
|
5678 (beginning-of-line))
|
|
5679 pt)
|
|
5680 (verilog-goto-defun-file label)
|
|
5681 )))
|
|
5682
|
|
5683 ;; Eliminate compile warning
|
|
5684 (eval-when-compile
|
|
5685 (if (not (boundp 'occur-pos-list))
|
|
5686 (defvar occur-pos-list nil "Backward compatibility occur positions.")))
|
|
5687
|
|
5688 (defun verilog-showscopes ()
|
|
5689 "List all scopes in this module."
|
|
5690 (interactive)
|
|
5691 (let ((buffer (current-buffer))
|
|
5692 (linenum 1)
|
|
5693 (nlines 0)
|
|
5694 (first 1)
|
|
5695 (prevpos (point-min))
|
|
5696 (final-context-start (make-marker))
|
|
5697 (regexp "\\(module\\s-+\\w+\\s-*(\\)\\|\\(\\w+\\s-+\\w+\\s-*(\\)")
|
|
5698 )
|
|
5699 (with-output-to-temp-buffer "*Occur*"
|
|
5700 (save-excursion
|
|
5701 (message (format "Searching for %s ..." regexp))
|
|
5702 ;; Find next match, but give up if prev match was at end of buffer.
|
|
5703 (while (and (not (= prevpos (point-max)))
|
|
5704 (verilog-re-search-forward regexp nil t))
|
|
5705 (goto-char (match-beginning 0))
|
|
5706 (beginning-of-line)
|
|
5707 (save-match-data
|
|
5708 (setq linenum (+ linenum (count-lines prevpos (point)))))
|
|
5709 (setq prevpos (point))
|
|
5710 (goto-char (match-end 0))
|
|
5711 (let* ((start (save-excursion
|
|
5712 (goto-char (match-beginning 0))
|
|
5713 (forward-line (if (< nlines 0) nlines (- nlines)))
|
|
5714 (point)))
|
|
5715 (end (save-excursion
|
|
5716 (goto-char (match-end 0))
|
|
5717 (if (> nlines 0)
|
|
5718 (forward-line (1+ nlines))
|
|
5719 (forward-line 1))
|
|
5720 (point)))
|
|
5721 (tag (format "%3d" linenum))
|
|
5722 (empty (make-string (length tag) ?\ ))
|
|
5723 tem)
|
|
5724 (save-excursion
|
|
5725 (setq tem (make-marker))
|
|
5726 (set-marker tem (point))
|
|
5727 (set-buffer standard-output)
|
|
5728 (setq occur-pos-list (cons tem occur-pos-list))
|
|
5729 (or first (zerop nlines)
|
|
5730 (insert "--------\n"))
|
|
5731 (setq first nil)
|
|
5732 (insert-buffer-substring buffer start end)
|
|
5733 (backward-char (- end start))
|
|
5734 (setq tem (if (< nlines 0) (- nlines) nlines))
|
|
5735 (while (> tem 0)
|
|
5736 (insert empty ?:)
|
|
5737 (forward-line 1)
|
|
5738 (setq tem (1- tem)))
|
|
5739 (let ((this-linenum linenum))
|
|
5740 (set-marker final-context-start
|
|
5741 (+ (point) (- (match-end 0) (match-beginning 0))))
|
|
5742 (while (< (point) final-context-start)
|
|
5743 (if (null tag)
|
|
5744 (setq tag (format "%3d" this-linenum)))
|
|
5745 (insert tag ?:)))))))
|
|
5746 (set-buffer-modified-p nil))))
|
|
5747
|
|
5748
|
|
5749 ;; Highlight helper functions
|
|
5750 (defconst verilog-directive-regexp "\\(translate\\|coverage\\|lint\\)_")
|
|
5751 (defun verilog-within-translate-off ()
|
|
5752 "Return point if within translate-off region, else nil."
|
|
5753 (and (save-excursion
|
|
5754 (re-search-backward
|
|
5755 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "\\(on\\|off\\)\\>")
|
|
5756 nil t))
|
|
5757 (equal "off" (match-string 2))
|
|
5758 (point)))
|
|
5759
|
|
5760 (defun verilog-start-translate-off (limit)
|
|
5761 "Return point before translate-off directive if before LIMIT, else nil."
|
|
5762 (when (re-search-forward
|
|
5763 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "off\\>")
|
|
5764 limit t)
|
|
5765 (match-beginning 0)))
|
|
5766
|
|
5767 (defun verilog-back-to-start-translate-off (limit)
|
|
5768 "Return point before translate-off directive if before LIMIT, else nil."
|
|
5769 (when (re-search-backward
|
|
5770 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "off\\>")
|
|
5771 limit t)
|
|
5772 (match-beginning 0)))
|
|
5773
|
|
5774 (defun verilog-end-translate-off (limit)
|
|
5775 "Return point after translate-on directive if before LIMIT, else nil."
|
|
5776
|
|
5777 (re-search-forward (concat
|
|
5778 "//\\s-*.*\\s-*" verilog-directive-regexp "on\\>") limit t))
|
|
5779
|
|
5780 (defun verilog-match-translate-off (limit)
|
|
5781 "Match a translate-off block, setting `match-data' and returning t, else nil.
|
|
5782 Bound search by LIMIT."
|
|
5783 (when (< (point) limit)
|
|
5784 (let ((start (or (verilog-within-translate-off)
|
|
5785 (verilog-start-translate-off limit)))
|
|
5786 (case-fold-search t))
|
|
5787 (when start
|
|
5788 (let ((end (or (verilog-end-translate-off limit) limit)))
|
|
5789 (set-match-data (list start end))
|
|
5790 (goto-char end))))))
|
|
5791
|
|
5792 (defun verilog-font-lock-match-item (limit)
|
|
5793 "Match, and move over, any declaration item after point.
|
|
5794 Bound search by LIMIT. Adapted from
|
|
5795 `font-lock-match-c-style-declaration-item-and-skip-to-next'."
|
|
5796 (condition-case nil
|
|
5797 (save-restriction
|
|
5798 (narrow-to-region (point-min) limit)
|
|
5799 ;; match item
|
|
5800 (when (looking-at "\\s-*\\([a-zA-Z]\\w*\\)")
|
|
5801 (save-match-data
|
|
5802 (goto-char (match-end 1))
|
|
5803 ;; move to next item
|
|
5804 (if (looking-at "\\(\\s-*,\\)")
|
|
5805 (goto-char (match-end 1))
|
|
5806 (end-of-line) t))))
|
|
5807 (error nil)))
|
|
5808
|
|
5809
|
|
5810 ;; Added by Subbu Meiyappan for Header
|
|
5811
|
|
5812 (defun verilog-header ()
|
|
5813 "Insert a standard Verilog file header."
|
|
5814 (interactive)
|
|
5815 (let ((start (point)))
|
|
5816 (insert "\
|
|
5817 //-----------------------------------------------------------------------------
|
|
5818 // Title : <title>
|
|
5819 // Project : <project>
|
|
5820 //-----------------------------------------------------------------------------
|
|
5821 // File : <filename>
|
|
5822 // Author : <author>
|
|
5823 // Created : <credate>
|
|
5824 // Last modified : <moddate>
|
|
5825 //-----------------------------------------------------------------------------
|
|
5826 // Description :
|
|
5827 // <description>
|
|
5828 //-----------------------------------------------------------------------------
|
|
5829 // Copyright (c) <copydate> by <company> This model is the confidential and
|
|
5830 // proprietary property of <company> and the possession or use of this
|
|
5831 // file requires a written license from <company>.
|
|
5832 //------------------------------------------------------------------------------
|
|
5833 // Modification history :
|
|
5834 // <modhist>
|
|
5835 //-----------------------------------------------------------------------------
|
|
5836
|
|
5837 ")
|
|
5838 (goto-char start)
|
|
5839 (search-forward "<filename>")
|
|
5840 (replace-match (buffer-name) t t)
|
|
5841 (search-forward "<author>") (replace-match "" t t)
|
|
5842 (insert (user-full-name))
|
|
5843 (insert " <" (user-login-name) "@" (system-name) ">")
|
|
5844 (search-forward "<credate>") (replace-match "" t t)
|
|
5845 (insert-date)
|
|
5846 (search-forward "<moddate>") (replace-match "" t t)
|
|
5847 (insert-date)
|
|
5848 (search-forward "<copydate>") (replace-match "" t t)
|
|
5849 (insert-year)
|
|
5850 (search-forward "<modhist>") (replace-match "" t t)
|
|
5851 (insert-date)
|
|
5852 (insert " : created")
|
|
5853 (goto-char start)
|
|
5854 (let (string)
|
|
5855 (setq string (read-string "title: "))
|
|
5856 (search-forward "<title>")
|
|
5857 (replace-match string t t)
|
|
5858 (setq string (read-string "project: " verilog-project))
|
|
5859 (make-variable-buffer-local 'verilog-project)
|
|
5860 (setq verilog-project string)
|
|
5861 (search-forward "<project>")
|
|
5862 (replace-match string t t)
|
|
5863 (setq string (read-string "Company: " verilog-company))
|
|
5864 (make-variable-buffer-local 'verilog-company)
|
|
5865 (setq verilog-company string)
|
|
5866 (search-forward "<company>")
|
|
5867 (replace-match string t t)
|
|
5868 (search-forward "<company>")
|
|
5869 (replace-match string t t)
|
|
5870 (search-forward "<company>")
|
|
5871 (replace-match string t t)
|
|
5872 (search-backward "<description>")
|
|
5873 (replace-match "" t t)
|
|
5874 )))
|
|
5875
|
|
5876 ;; verilog-header Uses the insert-date function
|
|
5877
|
|
5878 (defun insert-date ()
|
|
5879 "Insert date from the system."
|
|
5880 (interactive)
|
|
5881 (let ((timpos))
|
|
5882 (setq timpos (point))
|
|
5883 (if verilog-date-scientific-format
|
|
5884 (shell-command "date \"+@%Y/%m/%d\"" t)
|
|
5885 (shell-command "date \"+@%d.%m.%Y\"" t))
|
|
5886 (search-forward "@")
|
|
5887 (delete-region timpos (point))
|
|
5888 (end-of-line))
|
|
5889 (delete-char 1))
|
|
5890
|
|
5891 (defun insert-year ()
|
|
5892 "Insert year from the system."
|
|
5893 (interactive)
|
|
5894 (let ((timpos))
|
|
5895 (setq timpos (point))
|
|
5896 (shell-command "date \"+@%Y\"" t)
|
|
5897 (search-forward "@")
|
|
5898 (delete-region timpos (point))
|
|
5899 (end-of-line))
|
|
5900 (delete-char 1))
|
|
5901
|
|
5902
|
|
5903 ;;
|
|
5904 ;; Signal list parsing
|
|
5905 ;;
|
|
5906
|
|
5907 ;; Elements of a signal list
|
|
5908 (defsubst verilog-sig-name (sig)
|
|
5909 (car sig))
|
|
5910 (defsubst verilog-sig-bits (sig)
|
|
5911 (nth 1 sig))
|
|
5912 (defsubst verilog-sig-comment (sig)
|
|
5913 (nth 2 sig))
|
|
5914 (defsubst verilog-sig-memory (sig)
|
|
5915 (nth 3 sig))
|
|
5916 (defsubst verilog-sig-enum (sig)
|
|
5917 (nth 4 sig))
|
|
5918 (defsubst verilog-sig-signed (sig)
|
|
5919 (nth 5 sig))
|
|
5920 (defsubst verilog-sig-type (sig)
|
|
5921 (nth 6 sig))
|
|
5922 (defsubst verilog-sig-multidim (sig)
|
|
5923 (nth 7 sig))
|
|
5924 (defsubst verilog-sig-multidim-string (sig)
|
|
5925 (if (verilog-sig-multidim sig)
|
|
5926 (let ((str "") (args (verilog-sig-multidim sig)))
|
|
5927 (while args
|
|
5928 (setq str (concat str (car args)))
|
|
5929 (setq args (cdr args)))
|
|
5930 str)))
|
|
5931 (defsubst verilog-sig-width (sig)
|
|
5932 (verilog-make-width-expression (verilog-sig-bits sig)))
|
|
5933
|
|
5934 (defsubst verilog-alw-get-inputs (sigs)
|
|
5935 (nth 2 sigs))
|
|
5936 (defsubst verilog-alw-get-outputs (sigs)
|
|
5937 (nth 0 sigs))
|
|
5938 (defsubst verilog-alw-get-uses-delayed (sigs)
|
|
5939 (nth 3 sigs))
|
|
5940
|
|
5941 (defun verilog-signals-not-in (in-list not-list)
|
|
5942 "Return list of signals in IN-LIST that aren't also in NOT-LIST,
|
|
5943 and also remove any duplicates in IN-LIST.
|
|
5944 Signals must be in standard (base vector) form."
|
|
5945 (let (out-list)
|
|
5946 (while in-list
|
|
5947 (if (not (or (assoc (car (car in-list)) not-list)
|
|
5948 (assoc (car (car in-list)) out-list)))
|
|
5949 (setq out-list (cons (car in-list) out-list)))
|
|
5950 (setq in-list (cdr in-list)))
|
|
5951 (nreverse out-list)))
|
|
5952 ;;(verilog-signals-not-in '(("A" "") ("B" "") ("DEL" "[2:3]")) '(("DEL" "") ("EXT" "")))
|
|
5953
|
|
5954 (defun verilog-signals-in (in-list other-list)
|
|
5955 "Return list of signals in IN-LIST that are also in OTHER-LIST.
|
|
5956 Signals must be in standard (base vector) form."
|
|
5957 (let (out-list)
|
|
5958 (while in-list
|
|
5959 (if (assoc (car (car in-list)) other-list)
|
|
5960 (setq out-list (cons (car in-list) out-list)))
|
|
5961 (setq in-list (cdr in-list)))
|
|
5962 (nreverse out-list)))
|
|
5963 ;;(verilog-signals-in '(("A" "") ("B" "") ("DEL" "[2:3]")) '(("DEL" "") ("EXT" "")))
|
|
5964
|
|
5965 (defun verilog-signals-memory (in-list)
|
|
5966 "Return list of signals in IN-LIST that are memoried (multidimensional)."
|
|
5967 (let (out-list)
|
|
5968 (while in-list
|
|
5969 (if (nth 3 (car in-list))
|
|
5970 (setq out-list (cons (car in-list) out-list)))
|
|
5971 (setq in-list (cdr in-list)))
|
|
5972 out-list))
|
|
5973 ;;(verilog-signals-memory '(("A" nil nil "[3:0]")) '(("B" nil nil nil)))
|
|
5974
|
|
5975 (defun verilog-signals-sort-compare (a b)
|
|
5976 "Compare signal A and B for sorting."
|
|
5977 (string< (car a) (car b)))
|
|
5978
|
|
5979 (defun verilog-signals-not-params (in-list)
|
|
5980 "Return list of signals in IN-LIST that aren't parameters or numeric constants."
|
|
5981 (let (out-list)
|
|
5982 (while in-list
|
|
5983 (unless (boundp (intern (concat "vh-" (car (car in-list)))))
|
|
5984 (setq out-list (cons (car in-list) out-list)))
|
|
5985 (setq in-list (cdr in-list)))
|
|
5986 (nreverse out-list)))
|
|
5987
|
|
5988 (defun verilog-signals-combine-bus (in-list)
|
|
5989 "Return a list of signals in IN-LIST, with busses combined.
|
|
5990 Duplicate signals are also removed. For example A[2] and A[1] become A[2:1]."
|
|
5991 (let (combo buswarn
|
|
5992 out-list
|
|
5993 sig highbit lowbit ; Temp information about current signal
|
|
5994 sv-name sv-highbit sv-lowbit ; Details about signal we are forming
|
|
5995 sv-comment sv-memory sv-enum sv-signed sv-type sv-multidim sv-busstring
|
|
5996 bus)
|
|
5997 ;; Shove signals so duplicated signals will be adjacent
|
|
5998 (setq in-list (sort in-list `verilog-signals-sort-compare))
|
|
5999 (while in-list
|
|
6000 (setq sig (car in-list))
|
|
6001 ;; No current signal; form from existing details
|
|
6002 (unless sv-name
|
|
6003 (setq sv-name (verilog-sig-name sig)
|
|
6004 sv-highbit nil
|
|
6005 sv-busstring nil
|
|
6006 sv-comment (verilog-sig-comment sig)
|
|
6007 sv-memory (verilog-sig-memory sig)
|
|
6008 sv-enum (verilog-sig-enum sig)
|
|
6009 sv-signed (verilog-sig-signed sig)
|
|
6010 sv-type (verilog-sig-type sig)
|
|
6011 sv-multidim (verilog-sig-multidim sig)
|
|
6012 combo ""
|
|
6013 buswarn ""
|
|
6014 ))
|
|
6015 ;; Extract bus details
|
|
6016 (setq bus (verilog-sig-bits sig))
|
|
6017 (cond ((and bus
|
|
6018 (or (and (string-match "\\[\\([0-9]+\\):\\([0-9]+\\)\\]" bus)
|
|
6019 (setq highbit (string-to-int (match-string 1 bus))
|
|
6020 lowbit (string-to-int (match-string 2 bus))))
|
|
6021 (and (string-match "\\[\\([0-9]+\\)\\]" bus)
|
|
6022 (setq highbit (string-to-int (match-string 1 bus))
|
|
6023 lowbit highbit))))
|
|
6024 ;; Combine bits in bus
|
|
6025 (if sv-highbit
|
|
6026 (setq sv-highbit (max highbit sv-highbit)
|
|
6027 sv-lowbit (min lowbit sv-lowbit))
|
|
6028 (setq sv-highbit highbit
|
|
6029 sv-lowbit lowbit)))
|
|
6030 (bus
|
|
6031 ;; String, probably something like `preproc:0
|
|
6032 (setq sv-busstring bus)))
|
|
6033 ;; Peek ahead to next signal
|
|
6034 (setq in-list (cdr in-list))
|
|
6035 (setq sig (car in-list))
|
|
6036 (cond ((and sig (equal sv-name (verilog-sig-name sig)))
|
|
6037 ;; Combine with this signal
|
|
6038 (when (and sv-busstring (not (equal sv-busstring (verilog-sig-bits sig))))
|
|
6039 (when nil ;; Debugging
|
|
6040 (message (concat "Warning, can't merge into single bus "
|
|
6041 sv-name bus
|
|
6042 ", the AUTOs may be wrong")))
|
|
6043 (setq buswarn ", Couldn't Merge"))
|
|
6044 (if (verilog-sig-comment sig) (setq combo ", ..."))
|
|
6045 (setq sv-memory (or sv-memory (verilog-sig-memory sig))
|
|
6046 sv-enum (or sv-enum (verilog-sig-enum sig))
|
|
6047 sv-signed (or sv-signed (verilog-sig-signed sig))
|
|
6048 sv-type (or sv-type (verilog-sig-type sig))
|
|
6049 sv-multidim (or sv-multidim (verilog-sig-multidim sig))))
|
|
6050 ;; Doesn't match next signal, add to queue, zero in prep for next
|
|
6051 ;; Note sig may also be nil for the last signal in the list
|
|
6052 (t
|
|
6053 (setq out-list
|
|
6054 (cons (list sv-name
|
|
6055 (or sv-busstring
|
|
6056 (if sv-highbit
|
|
6057 (concat "[" (int-to-string sv-highbit) ":" (int-to-string sv-lowbit) "]")))
|
|
6058 (concat sv-comment combo buswarn)
|
|
6059 sv-memory sv-enum sv-signed sv-type sv-multidim)
|
|
6060 out-list)
|
|
6061 sv-name nil)))
|
|
6062 )
|
|
6063 ;;
|
|
6064 out-list))
|
|
6065
|
|
6066 (defun verilog-sig-tieoff (sig &optional no-width)
|
|
6067 "Return tieoff expression for given SIGNAL, with appropriate width.
|
|
6068 Ignore width if optional NO-WIDTH is set."
|
|
6069 (let* ((width (if no-width nil (verilog-sig-width sig))))
|
|
6070 (concat
|
|
6071 (if (and verilog-active-low-regexp
|
|
6072 (string-match verilog-active-low-regexp (verilog-sig-name sig)))
|
|
6073 "~" "")
|
|
6074 (cond ((not width)
|
|
6075 "0")
|
|
6076 ((string-match "^[0-9]+$" width)
|
|
6077 (concat width (if (verilog-sig-signed sig) "'sh0" "'h0")))
|
|
6078 (t
|
|
6079 (concat "{" width "{1'b0}}"))))))
|
|
6080
|
|
6081 ;;
|
|
6082 ;; Port/Wire/Etc Reading
|
|
6083 ;;
|
|
6084
|
|
6085 (defun verilog-read-inst-backward-name ()
|
|
6086 "Internal. Move point back to beginning of inst-name."
|
|
6087 (verilog-backward-open-paren)
|
|
6088 (let (done)
|
|
6089 (while (not done)
|
|
6090 (verilog-re-search-backward-quick "\\()\\|\\b[a-zA-Z0-9`_\$]\\|\\]\\)" nil nil) ; ] isn't word boundary
|
|
6091 (cond ((looking-at ")")
|
|
6092 (verilog-backward-open-paren))
|
|
6093 (t (setq done t)))))
|
|
6094 (while (looking-at "\\]")
|
|
6095 (verilog-backward-open-bracket)
|
|
6096 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|\\]\\)" nil nil))
|
|
6097 (skip-chars-backward "a-zA-Z0-9`_$"))
|
|
6098
|
|
6099 (defun verilog-read-inst-module ()
|
|
6100 "Return module_name when point is inside instantiation."
|
|
6101 (save-excursion
|
|
6102 (verilog-read-inst-backward-name)
|
|
6103 ;; Skip over instantiation name
|
|
6104 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|)\\)" nil nil) ; ) isn't word boundary
|
|
6105 ;; Check for parameterized instantiations
|
|
6106 (when (looking-at ")")
|
|
6107 (verilog-backward-open-paren)
|
|
6108 (verilog-re-search-backward-quick "\\b[a-zA-Z0-9`_\$]" nil nil))
|
|
6109 (skip-chars-backward "a-zA-Z0-9'_$")
|
|
6110 (looking-at "[a-zA-Z0-9`_\$]+")
|
|
6111 ;; Important: don't use match string, this must work with emacs 19 font-lock on
|
|
6112 (buffer-substring-no-properties (match-beginning 0) (match-end 0))))
|
|
6113
|
|
6114 (defun verilog-read-inst-name ()
|
|
6115 "Return instance_name when point is inside instantiation."
|
|
6116 (save-excursion
|
|
6117 (verilog-read-inst-backward-name)
|
|
6118 (looking-at "[a-zA-Z0-9`_\$]+")
|
|
6119 ;; Important: don't use match string, this must work with emacs 19 font-lock on
|
|
6120 (buffer-substring-no-properties (match-beginning 0) (match-end 0))))
|
|
6121
|
|
6122 (defun verilog-read-module-name ()
|
|
6123 "Return module name when after its ( or ;."
|
|
6124 (save-excursion
|
|
6125 (re-search-backward "[(;]")
|
|
6126 (verilog-re-search-backward-quick "\\b[a-zA-Z0-9`_\$]" nil nil)
|
|
6127 (skip-chars-backward "a-zA-Z0-9`_$")
|
|
6128 (looking-at "[a-zA-Z0-9`_\$]+")
|
|
6129 ;; Important: don't use match string, this must work with emacs 19 font-lock on
|
|
6130 (buffer-substring-no-properties (match-beginning 0) (match-end 0))))
|
|
6131
|
|
6132 (defun verilog-read-auto-params (num-param &optional max-param)
|
|
6133 "Return parameter list inside auto.
|
|
6134 Optional NUM-PARAM and MAX-PARAM check for a specific number of parameters."
|
|
6135 (let ((olist))
|
|
6136 (save-excursion
|
|
6137 ;; /*AUTOPUNT("parameter", "parameter")*/
|
|
6138 (search-backward "(")
|
|
6139 (while (looking-at "(?\\s *\"\\([^\"]*\\)\"\\s *,?")
|
|
6140 (setq olist (cons (match-string 1) olist))
|
|
6141 (goto-char (match-end 0))))
|
|
6142 (or (eq nil num-param)
|
|
6143 (<= num-param (length olist))
|
|
6144 (error "%s: Expected %d parameters" (verilog-point-text) num-param))
|
|
6145 (if (eq max-param nil) (setq max-param num-param))
|
|
6146 (or (eq nil max-param)
|
|
6147 (>= max-param (length olist))
|
|
6148 (error "%s: Expected <= %d parameters" (verilog-point-text) max-param))
|
|
6149 (nreverse olist)))
|
|
6150
|
|
6151 (defun verilog-read-decls ()
|
|
6152 "Compute signal declaration information for the current module at point.
|
|
6153 Return a array of [outputs inouts inputs wire reg assign const]."
|
|
6154 (let ((end-mod-point (or (verilog-get-end-of-defun t) (point-max)))
|
|
6155 (functask 0) (paren 0) (sig-paren 0)
|
|
6156 sigs-in sigs-out sigs-inout sigs-wire sigs-reg sigs-assign sigs-const sigs-gparam
|
|
6157 vec expect-signal keywd newsig rvalue enum io signed typedefed multidim)
|
|
6158 (save-excursion
|
|
6159 (verilog-beg-of-defun)
|
|
6160 (setq sigs-const (verilog-read-auto-constants (point) end-mod-point))
|
|
6161 (while (< (point) end-mod-point)
|
|
6162 ;;(if dbg (setq dbg (cons (format "Pt %s Vec %s Kwd'%s'\n" (point) vec keywd) dbg)))
|
|
6163 (cond
|
|
6164 ((looking-at "//")
|
|
6165 (if (looking-at "[^\n]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
|
|
6166 (setq enum (match-string 1)))
|
|
6167 (search-forward "\n"))
|
|
6168 ((looking-at "/\\*")
|
|
6169 (forward-char 2)
|
|
6170 (if (looking-at "[^*]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
|
|
6171 (setq enum (match-string 1)))
|
|
6172 (or (search-forward "*/")
|
|
6173 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
|
|
6174 ((looking-at "(\\*")
|
|
6175 (forward-char 2)
|
|
6176 (or (looking-at "\\s-*)") ; It's a "always @ (*)"
|
|
6177 (search-forward "*)")
|
|
6178 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
|
|
6179 ((eq ?\" (following-char))
|
|
6180 (or (re-search-forward "[^\\]\"" nil t) ;; don't forward-char first, since we look for a non backslash first
|
|
6181 (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point))))
|
|
6182 ((eq ?\; (following-char))
|
|
6183 (setq vec nil io nil expect-signal nil newsig nil paren 0 rvalue nil)
|
|
6184 (forward-char 1))
|
|
6185 ((eq ?= (following-char))
|
|
6186 (setq rvalue t newsig nil)
|
|
6187 (forward-char 1))
|
|
6188 ((and (or rvalue sig-paren)
|
|
6189 (cond ((and (eq ?, (following-char))
|
|
6190 (eq paren sig-paren))
|
|
6191 (setq rvalue nil)
|
|
6192 (forward-char 1)
|
|
6193 t)
|
|
6194 ;; ,'s can occur inside {} & funcs
|
|
6195 ((looking-at "[{(]")
|
|
6196 (setq paren (1+ paren))
|
|
6197 (forward-char 1)
|
|
6198 t)
|
|
6199 ((looking-at "[})]")
|
|
6200 (setq paren (1- paren))
|
|
6201 (forward-char 1)
|
|
6202 (when (< paren sig-paren)
|
|
6203 (setq expect-signal nil)) ; ) that ends variables inside v2k arg list
|
|
6204 t)
|
|
6205 )))
|
|
6206 ((looking-at "\\s-*\\(\\[[^]]+\\]\\)")
|
|
6207 (goto-char (match-end 0))
|
|
6208 (cond (newsig ; Memory, not just width. Patch last signal added's memory (nth 3)
|
|
6209 (setcar (cdr (cdr (cdr newsig))) (match-string 1)))
|
|
6210 (vec ;; Multidimensional
|
|
6211 (setq multidim (cons vec multidim))
|
|
6212 (setq vec (verilog-string-replace-matches
|
|
6213 "\\s-+" "" nil nil (match-string 1))))
|
|
6214 (t ;; Bit width
|
|
6215 (setq vec (verilog-string-replace-matches
|
|
6216 "\\s-+" "" nil nil (match-string 1))))))
|
|
6217 ;; Normal or escaped identifier -- note we remember the \ if escaped
|
|
6218 ((looking-at "\\s-*\\([a-zA-Z0-9`_$]+\\|\\\\[^ \t\n\f]+\\)")
|
|
6219 (goto-char (match-end 0))
|
|
6220 (setq keywd (match-string 1))
|
|
6221 (when (string-match "^\\\\" keywd)
|
|
6222 (setq keywd (concat keywd " "))) ;; Escaped ID needs space at end
|
|
6223 (cond ((equal keywd "input")
|
|
6224 (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed nil multidim nil sig-paren paren
|
|
6225 expect-signal 'sigs-in io t))
|
|
6226 ((equal keywd "output")
|
|
6227 (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed nil multidim nil sig-paren paren
|
|
6228 expect-signal 'sigs-out io t))
|
|
6229 ((equal keywd "inout")
|
|
6230 (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed nil multidim nil sig-paren paren
|
|
6231 expect-signal 'sigs-inout io t))
|
|
6232 ((or (equal keywd "wire")
|
|
6233 (equal keywd "tri")
|
|
6234 (equal keywd "tri0")
|
|
6235 (equal keywd "tri1"))
|
|
6236 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
|
|
6237 expect-signal 'sigs-wire)))
|
|
6238 ((or (equal keywd "reg")
|
|
6239 (equal keywd "trireg"))
|
|
6240 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
|
|
6241 expect-signal 'sigs-reg)))
|
|
6242 ((equal keywd "assign")
|
|
6243 (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
|
|
6244 expect-signal 'sigs-assign))
|
|
6245 ((or (equal keywd "supply0")
|
|
6246 (equal keywd "supply1")
|
|
6247 (equal keywd "supply")
|
|
6248 (equal keywd "localparam"))
|
|
6249 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
|
|
6250 expect-signal 'sigs-const)))
|
|
6251 ((or (equal keywd "parameter"))
|
|
6252 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren
|
|
6253 expect-signal 'sigs-gparam)))
|
|
6254 ((equal keywd "signed")
|
|
6255 (setq signed "signed"))
|
|
6256 ((or (equal keywd "function")
|
|
6257 (equal keywd "task"))
|
|
6258 (setq functask (1+ functask)))
|
|
6259 ((or (equal keywd "endfunction")
|
|
6260 (equal keywd "endtask"))
|
|
6261 (setq functask (1- functask)))
|
|
6262 ((or (equal keywd "`ifdef")
|
|
6263 (equal keywd "`ifndef"))
|
|
6264 (setq rvalue t))
|
|
6265 ((verilog-typedef-name-p keywd)
|
|
6266 (setq typedefed keywd))
|
|
6267 ((and expect-signal
|
|
6268 (eq functask 0)
|
|
6269 (not rvalue)
|
|
6270 (eq paren sig-paren)
|
|
6271 (not (member keywd verilog-keywords)))
|
|
6272 ;; Add new signal to expect-signal's variable
|
|
6273 (setq newsig (list keywd vec nil nil enum signed typedefed multidim))
|
|
6274 (set expect-signal (cons newsig
|
|
6275 (symbol-value expect-signal))))))
|
|
6276 (t
|
|
6277 (forward-char 1)))
|
|
6278 (skip-syntax-forward " "))
|
|
6279 ;; Return arguments
|
|
6280 (vector (nreverse sigs-out)
|
|
6281 (nreverse sigs-inout)
|
|
6282 (nreverse sigs-in)
|
|
6283 (nreverse sigs-wire)
|
|
6284 (nreverse sigs-reg)
|
|
6285 (nreverse sigs-assign)
|
|
6286 (nreverse sigs-const)
|
|
6287 (nreverse sigs-gparam)
|
|
6288 ))))
|
|
6289
|
|
6290 (defvar sigs-in nil) ; Prevent compile warning
|
|
6291 (defvar sigs-inout nil) ; Prevent compile warning
|
|
6292 (defvar sigs-out nil) ; Prevent compile warning
|
|
6293
|
|
6294 (defun verilog-read-sub-decls-sig (submodi comment port sig vec multidim)
|
|
6295 "For verilog-read-sub-decls-line, add a signal."
|
|
6296 (let (portdata)
|
|
6297 (when sig
|
|
6298 (setq port (verilog-symbol-detick-denumber port))
|
|
6299 (setq sig (verilog-symbol-detick-denumber sig))
|
|
6300 (if sig (setq sig (verilog-string-replace-matches "^[---+~!|&]+" "" nil nil sig)))
|
|
6301 (if vec (setq vec (verilog-symbol-detick-denumber vec)))
|
|
6302 (if multidim (setq multidim (mapcar `verilog-symbol-detick-denumber multidim)))
|
|
6303 (unless (or (not sig)
|
|
6304 (equal sig "")) ;; Ignore .foo(1'b1) assignments
|
|
6305 (cond ((setq portdata (assoc port (verilog-modi-get-inouts submodi)))
|
|
6306 (setq sigs-inout (cons (list sig vec (concat "To/From " comment) nil nil
|
|
6307 (verilog-sig-signed portdata)
|
|
6308 (verilog-sig-type portdata)
|
|
6309 multidim)
|
|
6310 sigs-inout)))
|
|
6311 ((setq portdata (assoc port (verilog-modi-get-outputs submodi)))
|
|
6312 (setq sigs-out (cons (list sig vec (concat "From " comment) nil nil
|
|
6313 (verilog-sig-signed portdata)
|
|
6314 (verilog-sig-type portdata)
|
|
6315 multidim)
|
|
6316 sigs-out)))
|
|
6317 ((setq portdata (assoc port (verilog-modi-get-inputs submodi)))
|
|
6318 (setq sigs-in (cons (list sig vec (concat "To " comment) nil nil
|
|
6319 (verilog-sig-signed portdata)
|
|
6320 (verilog-sig-type portdata)
|
|
6321 multidim)
|
|
6322 sigs-in)))
|
|
6323 ;; (t -- warning pin isn't defined.) ; Leave for lint tool
|
|
6324 )))))
|
|
6325
|
|
6326 (defun verilog-read-sub-decls-line (submodi comment)
|
|
6327 "For read-sub-decls, read lines of port defs until none match anymore.
|
|
6328 Return the list of signals found, using submodi to look up each port."
|
|
6329 (let (done port sig vec multidim)
|
|
6330 (save-excursion
|
|
6331 (forward-line 1)
|
|
6332 (while (not done)
|
|
6333 ;; Get port name
|
|
6334 (cond ((looking-at "\\s-*\\.\\s-*\\([a-zA-Z0-9`_$]*\\)\\s-*(\\s-*")
|
|
6335 (setq port (match-string 1))
|
|
6336 (goto-char (match-end 0)))
|
|
6337 ((looking-at "\\s-*\\.\\s-*\\(\\\\[^ \t\n\f]*\\)\\s-*(\\s-*")
|
|
6338 (setq port (concat (match-string 1) " ")) ;; escaped id's need trailing space
|
|
6339 (goto-char (match-end 0)))
|
|
6340 ((looking-at "\\s-*\\.[^(]*(")
|
|
6341 (setq port nil) ;; skip this line
|
|
6342 (goto-char (match-end 0)))
|
|
6343 (t
|
|
6344 (setq port nil done t))) ;; Unknown, ignore rest of line
|
|
6345 ;; Get signal name
|
|
6346 (when port
|
|
6347 (setq multidim nil)
|
|
6348 (cond ((looking-at "\\(\\\\[^ \t\n\f]*\\)\\s-*)")
|
|
6349 (setq sig (concat (match-string 1) " ") ;; escaped id's need trailing space
|
|
6350 vec nil))
|
|
6351 ; We intentionally ignore (non-escaped) signals with .s in them
|
|
6352 ; this prevents AUTOWIRE etc from noticing hierarchical sigs.
|
|
6353 ((looking-at "\\([^[({).]*\\)\\s-*)")
|
|
6354 (setq sig (verilog-string-remove-spaces (match-string 1))
|
|
6355 vec nil))
|
|
6356 ((looking-at "\\([^[({).]*\\)\\s-*\\(\\[[^]]+\\]\\)\\s-*)")
|
|
6357 (setq sig (verilog-string-remove-spaces (match-string 1))
|
|
6358 vec (match-string 2)))
|
|
6359 ((looking-at "\\([^[({).]*\\)\\s-*/\\*\\(\\[[^*]+\\]\\)\\*/\\s-*)")
|
|
6360 (setq sig (verilog-string-remove-spaces (match-string 1))
|
|
6361 vec nil)
|
|
6362 (let ((parse (match-string 2)))
|
|
6363 (while (string-match "^\\(\\[[^]]+\\]\\)\\(.*\\)$" parse)
|
|
6364 (when vec (setq multidim (cons vec multidim)))
|
|
6365 (setq vec (match-string 1 parse))
|
|
6366 (setq parse (match-string 2 parse)))))
|
|
6367 ((looking-at "{\\(.*\\)}.*\\s-*)")
|
|
6368 (let ((mlst (split-string (match-string 1) ","))
|
|
6369 mstr)
|
|
6370 (while (setq mstr (pop mlst))
|
|
6371 ;;(unless noninteractive (message "sig: %s " mstr))
|
|
6372 (cond
|
|
6373 ((string-match "\\(['`a-zA-Z0-9_$]+\\)\\s-*$" mstr)
|
|
6374 (setq sig (verilog-string-remove-spaces (match-string 1 mstr))
|
|
6375 vec nil)
|
|
6376 ;;(unless noninteractive (message "concat sig1: %s %s" mstr (match-string 1 mstr)))
|
|
6377 )
|
|
6378 ((string-match "\\([^[({).]+\\)\\s-*\\(\\[[^]]+\\]\\)\\s-*" mstr)
|
|
6379 (setq sig (verilog-string-remove-spaces (match-string 1 mstr))
|
|
6380 vec (match-string 2 mstr))
|
|
6381 ;;(unless noninteractive (message "concat sig2: '%s' '%s' '%s'" mstr (match-string 1 mstr) (match-string 2 mstr)))
|
|
6382 )
|
|
6383 (t
|
|
6384 (setq sig nil)))
|
|
6385 ;; Process signals
|
|
6386 (verilog-read-sub-decls-sig submodi comment port sig vec multidim))))
|
|
6387 (t
|
|
6388 (setq sig nil)))
|
|
6389 ;; Process signals
|
|
6390 (verilog-read-sub-decls-sig submodi comment port sig vec multidim))
|
|
6391 ;;
|
|
6392 (forward-line 1)))))
|
|
6393
|
|
6394 (defun verilog-read-sub-decls ()
|
|
6395 "Internally parse signals going to modules under this module.
|
|
6396 Return a array of [ outputs inouts inputs ] signals for modules that are
|
|
6397 instantiated in this module. For example if declare A A (.B(SIG)) and SIG
|
|
6398 is a output, then SIG will be included in the list.
|
|
6399
|
|
6400 This only works on instantiations created with /*AUTOINST*/ converted by
|
|
6401 \\[verilog-auto-inst]. Otherwise, it would have to read in the whole
|
|
6402 component library to determine connectivity of the design.
|
|
6403
|
|
6404 One work around for this problem is to manually create // Inputs and //
|
|
6405 Outputs comments above subcell signals, for example:
|
|
6406
|
|
6407 module1 instance1x (
|
|
6408 // Outputs
|
|
6409 .out (out),
|
|
6410 // Inputs
|
|
6411 .in (in));"
|
|
6412 (save-excursion
|
|
6413 (let ((end-mod-point (verilog-get-end-of-defun t))
|
|
6414 st-point end-inst-point
|
|
6415 ;; below 3 modified by verilog-read-sub-decls-line
|
|
6416 sigs-out sigs-inout sigs-in)
|
|
6417 (verilog-beg-of-defun)
|
|
6418 (while (re-search-forward "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-mod-point t)
|
|
6419 (save-excursion
|
|
6420 (goto-char (match-beginning 0))
|
|
6421 (unless (verilog-inside-comment-p)
|
|
6422 ;; Attempt to snarf a comment
|
|
6423 (let* ((submod (verilog-read-inst-module))
|
|
6424 (inst (verilog-read-inst-name))
|
|
6425 (comment (concat inst " of " submod ".v")) submodi)
|
|
6426 (when (setq submodi (verilog-modi-lookup submod t))
|
|
6427 ;; This could have used a list created by verilog-auto-inst
|
|
6428 ;; However I want it to be runnable even on user's manually added signals
|
|
6429 (verilog-backward-open-paren)
|
|
6430 (setq end-inst-point (save-excursion (forward-sexp 1) (point))
|
|
6431 st-point (point))
|
|
6432 (while (re-search-forward "\\s *(?\\s *// Outputs" end-inst-point t)
|
|
6433 (verilog-read-sub-decls-line submodi comment)) ;; Modifies sigs-out
|
|
6434 (goto-char st-point)
|
|
6435 (while (re-search-forward "\\s *// Inouts" end-inst-point t)
|
|
6436 (verilog-read-sub-decls-line submodi comment)) ;; Modifies sigs-inout
|
|
6437 (goto-char st-point)
|
|
6438 (while (re-search-forward "\\s *// Inputs" end-inst-point t)
|
|
6439 (verilog-read-sub-decls-line submodi comment)) ;; Modifies sigs-in
|
|
6440 )))))
|
|
6441 ;; Combine duplicate bits
|
|
6442 ;;(setq rr (vector sigs-out sigs-inout sigs-in))
|
|
6443 (vector (verilog-signals-combine-bus (nreverse sigs-out))
|
|
6444 (verilog-signals-combine-bus (nreverse sigs-inout))
|
|
6445 (verilog-signals-combine-bus (nreverse sigs-in))))))
|
|
6446
|
|
6447 (defun verilog-read-inst-pins ()
|
|
6448 "Return a array of [ pins ] for the current instantiation at point.
|
|
6449 For example if declare A A (.B(SIG)) then B will be included in the list."
|
|
6450 (save-excursion
|
|
6451 (let ((end-mod-point (point)) ;; presume at /*AUTOINST*/ point
|
|
6452 pins pin)
|
|
6453 (verilog-backward-open-paren)
|
|
6454 (while (re-search-forward "\\.\\([^(,) \t\n\f]*\\)\\s-*" end-mod-point t)
|
|
6455 (setq pin (match-string 1))
|
|
6456 (unless (verilog-inside-comment-p)
|
|
6457 (setq pins (cons (list pin) pins))
|
|
6458 (when (looking-at "(")
|
|
6459 (forward-sexp 1))))
|
|
6460 (vector pins))))
|
|
6461
|
|
6462 (defun verilog-read-arg-pins ()
|
|
6463 "Return a array of [ pins ] for the current argument declaration at point."
|
|
6464 (save-excursion
|
|
6465 (let ((end-mod-point (point)) ;; presume at /*AUTOARG*/ point
|
|
6466 pins pin)
|
|
6467 (verilog-backward-open-paren)
|
|
6468 (while (re-search-forward "\\([a-zA-Z0-9$_.%`]+\\)" end-mod-point t)
|
|
6469 (setq pin (match-string 1))
|
|
6470 (unless (verilog-inside-comment-p)
|
|
6471 (setq pins (cons (list pin) pins))))
|
|
6472 (vector pins))))
|
|
6473
|
|
6474 (defun verilog-read-auto-constants (beg end-mod-point)
|
|
6475 "Return a list of AUTO_CONSTANTs used in the region from BEG to END-MOD-POINT."
|
|
6476 ;; Insert new
|
|
6477 (save-excursion
|
|
6478 (let (sig-list tpl-end-pt)
|
|
6479 (goto-char beg)
|
|
6480 (while (re-search-forward "\\<AUTO_CONSTANT" end-mod-point t)
|
|
6481 (if (not (looking-at "\\s *("))
|
|
6482 (error "%s: Missing () after AUTO_CONSTANT" (verilog-point-text)))
|
|
6483 (search-forward "(" end-mod-point)
|
|
6484 (setq tpl-end-pt (save-excursion
|
|
6485 (backward-char 1)
|
|
6486 (forward-sexp 1) ;; Moves to paren that closes argdecl's
|
|
6487 (backward-char 1)
|
|
6488 (point)))
|
|
6489 (while (re-search-forward "\\s-*\\([\"a-zA-Z0-9$_.%`]+\\)\\s-*,*" tpl-end-pt t)
|
|
6490 (setq sig-list (cons (list (match-string 1) nil nil) sig-list))))
|
|
6491 sig-list)))
|
|
6492
|
|
6493 (defun verilog-read-auto-lisp (start end)
|
|
6494 "Look for and evaluate a AUTO_LISP between START and END."
|
|
6495 (save-excursion
|
|
6496 (goto-char start)
|
|
6497 (while (re-search-forward "\\<AUTO_LISP(" end t)
|
|
6498 (backward-char)
|
|
6499 (let* ((beg-pt (prog1 (point)
|
|
6500 (forward-sexp 1))) ;; Closing paren
|
|
6501 (end-pt (point)))
|
|
6502 (eval-region beg-pt end-pt nil)))))
|
|
6503
|
|
6504 (eval-when-compile
|
|
6505 ;; These are passed in a let, not global
|
|
6506 (if (not (boundp 'sigs-in))
|
|
6507 (defvar sigs-in nil) (defvar sigs-out nil)
|
|
6508 (defvar got-sig nil) (defvar got-rvalue nil) (defvar uses-delayed nil)))
|
|
6509
|
|
6510 (defun verilog-read-always-signals-recurse
|
|
6511 (exit-keywd rvalue ignore-next)
|
|
6512 "Recursive routine for parentheses/bracket matching.
|
|
6513 EXIT-KEYWD is expression to stop at, nil if top level.
|
|
6514 RVALUE is true if at right hand side of equal.
|
|
6515 IGNORE-NEXT is true to ignore next token, fake from inside case statement."
|
|
6516 (let* ((semi-rvalue (equal "endcase" exit-keywd)) ;; true if after a ; we are looking for rvalue
|
|
6517 keywd last-keywd sig-tolk sig-last-tolk gotend got-sig got-rvalue end-else-check)
|
|
6518 ;;(if dbg (setq dbg (concat dbg (format "Recursion %S %S %S\n" exit-keywd rvalue ignore-next))))
|
|
6519 (while (not (or (eobp) gotend))
|
|
6520 (cond
|
|
6521 ((looking-at "//")
|
|
6522 (search-forward "\n"))
|
|
6523 ((looking-at "/\\*")
|
|
6524 (or (search-forward "*/")
|
|
6525 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
|
|
6526 ((looking-at "(\\*")
|
|
6527 (or (looking-at "(\\*\\s-*)") ; It's a "always @ (*)"
|
|
6528 (search-forward "*)")
|
|
6529 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point))))
|
|
6530 (t (setq keywd (buffer-substring-no-properties
|
|
6531 (point)
|
|
6532 (save-excursion (when (eq 0 (skip-chars-forward "a-zA-Z0-9$_.%`"))
|
|
6533 (forward-char 1))
|
|
6534 (point)))
|
|
6535 sig-last-tolk sig-tolk
|
|
6536 sig-tolk nil)
|
|
6537 ;;(if dbg (setq dbg (concat dbg (format "\tPt=%S %S\trv=%S in=%S ee=%S\n" (point) keywd rvalue ignore-next end-else-check))))
|
|
6538 (cond
|
|
6539 ((equal keywd "\"")
|
|
6540 (or (re-search-forward "[^\\]\"" nil t)
|
|
6541 (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point))))
|
|
6542 ;; else at top level loop, keep parsing
|
|
6543 ((and end-else-check (equal keywd "else"))
|
|
6544 ;;(if dbg (setq dbg (concat dbg (format "\tif-check-else %s\n" keywd))))
|
|
6545 ;; no forward movement, want to see else in lower loop
|
|
6546 (setq end-else-check nil))
|
|
6547 ;; End at top level loop
|
|
6548 ((and end-else-check (looking-at "[^ \t\n\f]"))
|
|
6549 ;;(if dbg (setq dbg (concat dbg (format "\tif-check-else-other %s\n" keywd))))
|
|
6550 (setq gotend t))
|
|
6551 ;; Final statement?
|
|
6552 ((and exit-keywd (equal keywd exit-keywd))
|
|
6553 (setq gotend t)
|
|
6554 (forward-char (length keywd)))
|
|
6555 ;; Standard tokens...
|
|
6556 ((equal keywd ";")
|
|
6557 (setq ignore-next nil rvalue semi-rvalue)
|
|
6558 ;; Final statement at top level loop?
|
|
6559 (when (not exit-keywd)
|
|
6560 ;;(if dbg (setq dbg (concat dbg (format "\ttop-end-check %s\n" keywd))))
|
|
6561 (setq end-else-check t))
|
|
6562 (forward-char 1))
|
|
6563 ((equal keywd "'")
|
|
6564 (if (looking-at "'s?[hdxbo][0-9a-fA-F_xz? \t]*")
|
|
6565 (goto-char (match-end 0))
|
|
6566 (forward-char 1)))
|
|
6567 ((equal keywd ":") ;; Case statement, begin/end label, x?y:z
|
|
6568 (cond ((equal "endcase" exit-keywd) ;; case x: y=z; statement next
|
|
6569 (setq ignore-next nil rvalue nil))
|
|
6570 ((equal "?" exit-keywd) ;; x?y:z rvalue
|
|
6571 ) ;; NOP
|
|
6572 (got-sig ;; label: statement
|
|
6573 (setq ignore-next nil rvalue semi-rvalue got-sig nil))
|
|
6574 ((not rvalue) ;; begin label
|
|
6575 (setq ignore-next t rvalue nil)))
|
|
6576 (forward-char 1))
|
|
6577 ((equal keywd "=")
|
|
6578 (if (eq (char-before) ?< )
|
|
6579 (setq uses-delayed 1))
|
|
6580 (setq ignore-next nil rvalue t)
|
|
6581 (forward-char 1))
|
|
6582 ((equal keywd "?")
|
|
6583 (forward-char 1)
|
|
6584 (verilog-read-always-signals-recurse ":" rvalue nil))
|
|
6585 ((equal keywd "[")
|
|
6586 (forward-char 1)
|
|
6587 (verilog-read-always-signals-recurse "]" t nil))
|
|
6588 ((equal keywd "(")
|
|
6589 (forward-char 1)
|
|
6590 (cond (sig-last-tolk ;; Function call; zap last signal
|
|
6591 (setq got-sig nil)))
|
|
6592 (cond ((equal last-keywd "for")
|
|
6593 (verilog-read-always-signals-recurse ";" nil nil)
|
|
6594 (verilog-read-always-signals-recurse ";" t nil)
|
|
6595 (verilog-read-always-signals-recurse ")" nil nil))
|
|
6596 (t (verilog-read-always-signals-recurse ")" t nil))))
|
|
6597 ((equal keywd "begin")
|
|
6598 (skip-syntax-forward "w_")
|
|
6599 (verilog-read-always-signals-recurse "end" nil nil)
|
|
6600 ;;(if dbg (setq dbg (concat dbg (format "\tgot-end %s\n" exit-keywd))))
|
|
6601 (setq ignore-next nil rvalue semi-rvalue)
|
|
6602 (if (not exit-keywd) (setq end-else-check t)))
|
|
6603 ((or (equal keywd "case")
|
|
6604 (equal keywd "casex")
|
|
6605 (equal keywd "casez"))
|
|
6606 (skip-syntax-forward "w_")
|
|
6607 (verilog-read-always-signals-recurse "endcase" t nil)
|
|
6608 (setq ignore-next nil rvalue semi-rvalue)
|
|
6609 (if (not exit-keywd) (setq gotend t))) ;; top level begin/end
|
|
6610 ((string-match "^[$`a-zA-Z_]" keywd) ;; not exactly word constituent
|
|
6611 (cond ((or (equal keywd "`ifdef")
|
|
6612 (equal keywd "`ifndef"))
|
|
6613 (setq ignore-next t))
|
|
6614 ((or ignore-next
|
|
6615 (member keywd verilog-keywords)
|
|
6616 (string-match "^\\$" keywd)) ;; PLI task
|
|
6617 (setq ignore-next nil))
|
|
6618 (t
|
|
6619 (setq keywd (verilog-symbol-detick-denumber keywd))
|
|
6620 (when got-sig
|
|
6621 (if got-rvalue (setq sigs-in (cons got-sig sigs-in))
|
|
6622 (setq sigs-out (cons got-sig sigs-out)))
|
|
6623 ;;(if dbg (setq dbg (concat dbg (format "\t\tgot-sig=%S rv=%S\n" got-sig got-rvalue))))
|
|
6624 )
|
|
6625 (setq got-rvalue rvalue
|
|
6626 got-sig (if (or (not keywd)
|
|
6627 (assoc keywd (if got-rvalue sigs-in sigs-out)))
|
|
6628 nil (list keywd nil nil))
|
|
6629 sig-tolk t)))
|
|
6630 (skip-chars-forward "a-zA-Z0-9$_.%`"))
|
|
6631 (t
|
|
6632 (forward-char 1)))
|
|
6633 ;; End of non-comment token
|
|
6634 (setq last-keywd keywd)
|
|
6635 ))
|
|
6636 (skip-syntax-forward " "))
|
|
6637 ;; Append the final pending signal
|
|
6638 (when got-sig
|
|
6639 (if got-rvalue (setq sigs-in (cons got-sig sigs-in))
|
|
6640 (setq sigs-out (cons got-sig sigs-out)))
|
|
6641 ;;(if dbg (setq dbg (concat dbg (format "\t\tgot-sig=%S rv=%S\n" got-sig got-rvalue))))
|
|
6642 (setq got-sig nil))
|
|
6643 ;;(if dbg (setq dbg (concat dbg (format "ENDRecursion %s\n" exit-keywd))))
|
|
6644 ))
|
|
6645
|
|
6646 (defun verilog-read-always-signals ()
|
|
6647 "Parse always block at point and return list of (outputs inout inputs)."
|
|
6648 ;; Insert new
|
|
6649 (save-excursion
|
|
6650 (let* (;;(dbg "")
|
|
6651 sigs-in sigs-out
|
|
6652 uses-delayed) ;; Found signal/rvalue; push if not function
|
|
6653 (search-forward ")")
|
|
6654 (verilog-read-always-signals-recurse nil nil nil)
|
|
6655 ;;(if dbg (save-excursion (set-buffer (get-buffer-create "*vl-dbg*")) (delete-region (point-min) (point-max)) (insert dbg) (setq dbg "")))
|
|
6656 ;; Return what was found
|
|
6657 (list sigs-out nil sigs-in uses-delayed))))
|
|
6658
|
|
6659 (defun verilog-read-instants ()
|
|
6660 "Parse module at point and return list of ( ( file instance ) ... )."
|
|
6661 (verilog-beg-of-defun)
|
|
6662 (let* ((end-mod-point (verilog-get-end-of-defun t))
|
|
6663 (state nil)
|
|
6664 (instants-list nil))
|
|
6665 (save-excursion
|
|
6666 (while (< (point) end-mod-point)
|
|
6667 ;; Stay at level 0, no comments
|
|
6668 (while (progn
|
|
6669 (setq state (parse-partial-sexp (point) end-mod-point 0 t nil))
|
|
6670 (or (> (car state) 0) ; in parens
|
|
6671 (nth 5 state) ; comment
|
|
6672 ))
|
|
6673 (forward-line 1))
|
|
6674 (beginning-of-line)
|
|
6675 (if (looking-at "^\\s-*\\([a-zA-Z0-9`_$]+\\)\\s-+\\([a-zA-Z0-9`_$]+\\)\\s-*(")
|
|
6676 ;;(if (looking-at "^\\(.+\\)$")
|
|
6677 (let ((module (match-string 1))
|
|
6678 (instant (match-string 2)))
|
|
6679 (if (not (member module verilog-keywords))
|
|
6680 (setq instants-list (cons (list module instant) instants-list)))))
|
|
6681 (forward-line 1)
|
|
6682 ))
|
|
6683 instants-list))
|
|
6684
|
|
6685
|
|
6686 (defun verilog-read-auto-template (module)
|
|
6687 "Look for a auto_template for the instantiation of the given MODULE.
|
|
6688 If found returns the signal name connections. Return REGEXP and
|
|
6689 list of ( (signal_name connection_name)... )"
|
|
6690 (save-excursion
|
|
6691 ;; Find beginning
|
|
6692 (let ((tpl-regexp "\\([0-9]+\\)")
|
|
6693 (lineno 0)
|
|
6694 (templateno 0)
|
|
6695 tpl-sig-list tpl-wild-list tpl-end-pt rep)
|
|
6696 (cond ((or
|
|
6697 (re-search-backward (concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil t)
|
|
6698 (progn
|
|
6699 (goto-char (point-min))
|
|
6700 (re-search-forward (concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil t)))
|
|
6701 (goto-char (match-end 0))
|
|
6702 ;; Parse "REGEXP"
|
|
6703 ;; We reserve @"..." for future lisp expressions that evaluate once-per-AUTOINST
|
|
6704 (when (looking-at "\\s-*\"\\([^\"]*)\\)\"")
|
|
6705 (setq tpl-regexp (match-string 1))
|
|
6706 (goto-char (match-end 0)))
|
|
6707 (search-forward "(")
|
|
6708 ;; Parse lines in the template
|
|
6709 (when verilog-auto-inst-template-numbers
|
|
6710 (save-excursion
|
|
6711 (goto-char (point-min))
|
|
6712 (while (search-forward "AUTO_TEMPLATE" nil t)
|
|
6713 (setq templateno (1+ templateno)))))
|
|
6714 (setq tpl-end-pt (save-excursion
|
|
6715 (backward-char 1)
|
|
6716 (forward-sexp 1) ;; Moves to paren that closes argdecl's
|
|
6717 (backward-char 1)
|
|
6718 (point)))
|
|
6719 ;;
|
|
6720 (while (< (point) tpl-end-pt)
|
|
6721 (cond ((looking-at "\\s-*\\.\\([a-zA-Z0-9`_$]+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)")
|
|
6722 (setq tpl-sig-list (cons (list
|
|
6723 (match-string-no-properties 1)
|
|
6724 (match-string-no-properties 2)
|
|
6725 templateno lineno)
|
|
6726 tpl-sig-list))
|
|
6727 (goto-char (match-end 0)))
|
|
6728 ;; Regexp form??
|
|
6729 ((looking-at
|
|
6730 ;; Regexp bug in xemacs disallows ][ inside [], and wants + last
|
|
6731 "\\s-*\\.\\(\\([a-zA-Z0-9`_$+@^.*?|---]+\\|[][]\\|\\\\[()|]\\)+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)")
|
|
6732 (setq rep (match-string-no-properties 3))
|
|
6733 (goto-char (match-end 0))
|
|
6734 (setq tpl-wild-list
|
|
6735 (cons (list
|
|
6736 (concat "^"
|
|
6737 (verilog-string-replace-matches "@" "\\\\([0-9]+\\\\)" nil nil
|
|
6738 (match-string 1))
|
|
6739 "$")
|
|
6740 rep
|
|
6741 templateno lineno)
|
|
6742 tpl-wild-list)))
|
|
6743 ((looking-at "[ \t\f]+")
|
|
6744 (goto-char (match-end 0)))
|
|
6745 ((looking-at "\n")
|
|
6746 (setq lineno (1+ lineno))
|
|
6747 (goto-char (match-end 0)))
|
|
6748 ((looking-at "//")
|
|
6749 (search-forward "\n"))
|
|
6750 ((looking-at "/\\*")
|
|
6751 (forward-char 2)
|
|
6752 (or (search-forward "*/")
|
|
6753 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point))))
|
|
6754 (t
|
|
6755 (error "%s: AUTO_TEMPLATE parsing error: %s"
|
|
6756 (verilog-point-text)
|
|
6757 (progn (looking-at ".*$") (match-string 0))))
|
|
6758 ))
|
|
6759 ;; Return
|
|
6760 (vector tpl-regexp
|
|
6761 (list tpl-sig-list tpl-wild-list)))
|
|
6762 ;; If no template found
|
|
6763 (t (vector tpl-regexp nil))))))
|
|
6764 ;;(progn (find-file "auto-template.v") (verilog-read-auto-template "ptl_entry"))
|
|
6765
|
|
6766 (defun verilog-set-define (defname defvalue &optional buffer enumname)
|
|
6767 "Set the definition DEFNAME to the DEFVALUE in the given BUFFER.
|
|
6768 Optionally associate it with the specified enumeration ENUMNAME."
|
|
6769 (save-excursion
|
|
6770 (set-buffer (or buffer (current-buffer)))
|
|
6771 (let ((mac (intern (concat "vh-" defname))))
|
|
6772 ;;(message "Define %s=%s" defname defvalue) (sleep-for 1)
|
|
6773 ;; Need to define to a constant if no value given
|
|
6774 (set (make-variable-buffer-local mac)
|
|
6775 (if (equal defvalue "") "1" defvalue)))
|
|
6776 (if enumname
|
|
6777 (let ((enumvar (intern (concat "venum-" enumname))))
|
|
6778 ;;(message "Define %s=%s" defname defvalue) (sleep-for 1)
|
|
6779 (make-variable-buffer-local enumvar)
|
|
6780 (add-to-list enumvar defname)))
|
|
6781 ))
|
|
6782
|
|
6783 (defun verilog-read-defines (&optional filename recurse subcall)
|
|
6784 "Read `defines and parameters for the current file, or optional FILENAME.
|
|
6785 If the filename is provided, `verilog-library-flags' will be used to
|
|
6786 resolve it. If optional RECURSE is non-nil, recurse through `includes.
|
|
6787
|
|
6788 Parameters must be simple assignments to constants, or have their own
|
|
6789 \"parameter\" label rather than a list of parameters. Thus:
|
|
6790
|
|
6791 parameter X = 5, Y = 10; // Ok
|
|
6792 parameter X = {1'b1, 2'h2}; // Ok
|
|
6793 parameter X = {1'b1, 2'h2}, Y = 10; // Bad, make into 2 parameter lines
|
|
6794
|
|
6795 Defines must be simple text substitutions, one on a line, starting
|
|
6796 at the beginning of the line. Any ifdefs or multiline comments around the
|
|
6797 define are ignored.
|
|
6798
|
|
6799 Defines are stored inside Emacs variables using the name vh-{definename}.
|
|
6800
|
|
6801 This function is useful for setting vh-* variables. The file variables
|
|
6802 feature can be used to set defines that `verilog-mode' can see; put at the
|
|
6803 *END* of your file something like:
|
|
6804
|
|
6805 // Local Variables:
|
|
6806 // vh-macro:\"macro_definition\"
|
|
6807 // End:
|
|
6808
|
|
6809 If macros are defined earlier in the same file and you want their values,
|
|
6810 you can read them automatically (provided `enable-local-eval' is on):
|
|
6811
|
|
6812 // Local Variables:
|
|
6813 // eval:(verilog-read-defines)
|
|
6814 // eval:(verilog-read-defines \"group_standard_includes.v\")
|
|
6815 // End:
|
|
6816
|
|
6817 Note these are only read when the file is first visited, you must use
|
|
6818 \\[find-alternate-file] RET to have these take effect after editing them!
|
|
6819
|
|
6820 If you want to disable the \"Process `eval' or hook local variables\"
|
|
6821 warning message, you need to add to your .emacs file:
|
|
6822
|
|
6823 (setq enable-local-eval t)"
|
|
6824 (let ((origbuf (current-buffer)))
|
|
6825 (save-excursion
|
|
6826 (unless subcall (verilog-getopt-flags))
|
|
6827 (when filename
|
|
6828 (let ((fns (verilog-library-filenames filename (buffer-file-name))))
|
|
6829 (if fns
|
|
6830 (set-buffer (find-file-noselect (car fns)))
|
|
6831 (error (concat (verilog-point-text)
|
|
6832 ": Can't find verilog-read-defines file: " filename)))))
|
|
6833 (when recurse
|
|
6834 (goto-char (point-min))
|
|
6835 (while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n\f]+\\)" nil t)
|
|
6836 (let ((inc (verilog-string-replace-matches "\"" "" nil nil (match-string-no-properties 1))))
|
|
6837 (unless (verilog-inside-comment-p)
|
|
6838 (verilog-read-defines inc recurse t)))))
|
|
6839 ;; Read `defines
|
|
6840 ;; note we don't use verilog-re... it's faster this way, and that
|
|
6841 ;; function has problems when comments are at the end of the define
|
|
6842 (goto-char (point-min))
|
|
6843 (while (re-search-forward "^\\s-*`define\\s-+\\([a-zA-Z0-9_$]+\\)\\s-+\\(.*\\)$" nil t)
|
|
6844 (let ((defname (match-string-no-properties 1))
|
|
6845 (defvalue (match-string-no-properties 2)))
|
|
6846 (setq defvalue (verilog-string-replace-matches "\\s-*/[/*].*$" "" nil nil defvalue))
|
|
6847 (verilog-set-define defname defvalue origbuf)))
|
|
6848 ;; Hack: Read parameters
|
|
6849 (goto-char (point-min))
|
|
6850 (while (re-search-forward
|
|
6851 "^\\s-*\\(parameter\\|localparam\\)\\(\\(\\s-*\\[[^]]*\\]\\|\\)\\s-+\\([a-zA-Z0-9_$]+\\)\\s-*=\\s-*\\([^;,]*\\),?\\|\\)\\s-*" nil t)
|
|
6852 (let ((var (match-string-no-properties 4))
|
|
6853 (val (match-string-no-properties 5))
|
|
6854 enumname)
|
|
6855 ;; The primary way of getting defines is verilog-read-decls
|
|
6856 ;; However, that isn't called yet for included files, so we'll add another scheme
|
|
6857 (if (looking-at "[^\n]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)")
|
|
6858 (setq enumname (match-string-no-properties 1)))
|
|
6859 (if var
|
|
6860 (verilog-set-define var val origbuf enumname))
|
|
6861 (forward-comment 999)
|
|
6862 (while (looking-at "\\s-*,?\\s-*\\([a-zA-Z0-9_$]+\\)\\s-*=\\s-*\\([^;,]*\\),?\\s-*")
|
|
6863 (verilog-set-define (match-string-no-properties 1) (match-string-no-properties 2) origbuf enumname)
|
|
6864 (goto-char (match-end 0))
|
|
6865 (forward-comment 999))))
|
|
6866 )))
|
|
6867
|
|
6868 (defun verilog-read-includes ()
|
|
6869 "Read `includes for the current file.
|
|
6870 This will find all of the `includes which are at the beginning of lines,
|
|
6871 ignoring any ifdefs or multiline comments around them.
|
|
6872 `verilog-read-defines' is then performed on the current and each included
|
|
6873 file.
|
|
6874
|
|
6875 It is often useful put at the *END* of your file something like:
|
|
6876
|
|
6877 // Local Variables:
|
|
6878 // eval:(verilog-read-defines)
|
|
6879 // eval:(verilog-read-includes)
|
|
6880 // End:
|
|
6881
|
|
6882 Note includes are only read when the file is first visited, you must use
|
|
6883 \\[find-alternate-file] RET to have these take effect after editing them!
|
|
6884
|
|
6885 It is good to get in the habit of including all needed files in each .v
|
|
6886 file that needs it, rather than waiting for compile time. This will aid
|
|
6887 this process, Verilint, and readability. To prevent defining the same
|
|
6888 variable over and over when many modules are compiled together, put a test
|
|
6889 around the inside each include file:
|
|
6890
|
|
6891 foo.v (a include):
|
|
6892 `ifdef _FOO_V // include if not already included
|
|
6893 `else
|
|
6894 `define _FOO_V
|
|
6895 ... contents of file
|
|
6896 `endif // _FOO_V"
|
|
6897 ;;slow: (verilog-read-defines nil t))
|
|
6898 (save-excursion
|
|
6899 (verilog-getopt-flags)
|
|
6900 (goto-char (point-min))
|
|
6901 (while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n\f]+\\)" nil t)
|
|
6902 (let ((inc (verilog-string-replace-matches "\"" "" nil nil (match-string 1))))
|
|
6903 (verilog-read-defines inc nil t)))))
|
|
6904
|
|
6905 (defun verilog-read-signals (&optional start end)
|
|
6906 "Return a simple list of all possible signals in the file.
|
|
6907 Bounded by optional region from START to END. Overly aggressive but fast.
|
|
6908 Some macros and such are also found and included. For dinotrace.el"
|
|
6909 (let (sigs-all keywd)
|
|
6910 (progn;save-excursion
|
|
6911 (goto-char (or start (point-min)))
|
|
6912 (setq end (or end (point-max)))
|
|
6913 (while (re-search-forward "[\"/a-zA-Z_.%`]" end t)
|
|
6914 (forward-char -1)
|
|
6915 (cond
|
|
6916 ((looking-at "//")
|
|
6917 (search-forward "\n"))
|
|
6918 ((looking-at "/\\*")
|
|
6919 (search-forward "*/"))
|
|
6920 ((looking-at "(\\*")
|
|
6921 (or (looking-at "(\\*\\s-*)") ; It's a "always @ (*)"
|
|
6922 (search-forward "*)")))
|
|
6923 ((eq ?\" (following-char))
|
|
6924 (re-search-forward "[^\\]\"")) ;; don't forward-char first, since we look for a non backslash first
|
|
6925 ((looking-at "\\s-*\\([a-zA-Z0-9$_.%`]+\\)")
|
|
6926 (goto-char (match-end 0))
|
|
6927 (setq keywd (match-string-no-properties 1))
|
|
6928 (or (member keywd verilog-keywords)
|
|
6929 (member keywd sigs-all)
|
|
6930 (setq sigs-all (cons keywd sigs-all))))
|
|
6931 (t (forward-char 1)))
|
|
6932 )
|
|
6933 ;; Return list
|
|
6934 sigs-all)))
|
|
6935
|
|
6936 ;;
|
|
6937 ;; Argument file parsing
|
|
6938 ;;
|
|
6939
|
|
6940 (defun verilog-getopt (arglist)
|
|
6941 "Parse -f, -v etc arguments in ARGLIST list or string."
|
|
6942 (unless (listp arglist) (setq arglist (list arglist)))
|
|
6943 (let ((space-args '())
|
|
6944 arg next-param)
|
|
6945 ;; Split on spaces, so users can pass whole command lines
|
|
6946 (while arglist
|
|
6947 (setq arg (car arglist)
|
|
6948 arglist (cdr arglist))
|
|
6949 (while (string-match "^\\([^ \t\n\f]+\\)[ \t\n\f]*\\(.*$\\)" arg)
|
|
6950 (setq space-args (append space-args
|
|
6951 (list (match-string-no-properties 1 arg))))
|
|
6952 (setq arg (match-string 2 arg))))
|
|
6953 ;; Parse arguments
|
|
6954 (while space-args
|
|
6955 (setq arg (car space-args)
|
|
6956 space-args (cdr space-args))
|
|
6957 (cond
|
|
6958 ;; Need another arg
|
|
6959 ((equal arg "-f")
|
|
6960 (setq next-param arg))
|
|
6961 ((equal arg "-v")
|
|
6962 (setq next-param arg))
|
|
6963 ((equal arg "-y")
|
|
6964 (setq next-param arg))
|
|
6965 ;; +libext+(ext1)+(ext2)...
|
|
6966 ((string-match "^\\+libext\\+\\(.*\\)" arg)
|
|
6967 (setq arg (match-string 1 arg))
|
|
6968 (while (string-match "\\([^+]+\\)\\+?\\(.*\\)" arg)
|
|
6969 (verilog-add-list-unique `verilog-library-extensions
|
|
6970 (match-string 1 arg))
|
|
6971 (setq arg (match-string 2 arg))))
|
|
6972 ;;
|
|
6973 ((or (string-match "^-D\\([^+=]*\\)[+=]\\(.*\\)" arg) ;; -Ddefine=val
|
|
6974 (string-match "^-D\\([^+=]*\\)\\(\\)" arg) ;; -Ddefine
|
|
6975 (string-match "^\\+define\\([^+=]*\\)[+=]\\(.*\\)" arg) ;; +define+val
|
|
6976 (string-match "^\\+define\\([^+=]*\\)\\(\\)" arg)) ;; +define+define
|
|
6977 (verilog-set-define (match-string 1 arg) (match-string 2 arg)))
|
|
6978 ;;
|
|
6979 ((or (string-match "^\\+incdir\\+\\(.*\\)" arg) ;; +incdir+dir
|
|
6980 (string-match "^-I\\(.*\\)" arg)) ;; -Idir
|
|
6981 (verilog-add-list-unique `verilog-library-directories
|
|
6982 (match-string 1 arg)))
|
|
6983 ;; Ignore
|
|
6984 ((equal "+librescan" arg))
|
|
6985 ((string-match "^-U\\(.*\\)" arg)) ;; -Udefine
|
|
6986 ;; Second parameters
|
|
6987 ((equal next-param "-f")
|
|
6988 (setq next-param nil)
|
|
6989 (verilog-getopt-file arg))
|
|
6990 ((equal next-param "-v")
|
|
6991 (setq next-param nil)
|
|
6992 (verilog-add-list-unique `verilog-library-files arg))
|
|
6993 ((equal next-param "-y")
|
|
6994 (setq next-param nil)
|
|
6995 (verilog-add-list-unique `verilog-library-directories arg))
|
|
6996 ;; Filename
|
|
6997 ((string-match "^[^-+]" arg)
|
|
6998 (verilog-add-list-unique `verilog-library-files arg))
|
|
6999 ;; Default - ignore; no warning
|
|
7000 )
|
|
7001 )
|
|
7002 )
|
|
7003 )
|
|
7004 ;;(verilog-getopt (list "+libext+.a+.b" "+incdir+foodir" "+define+a+aval" "-f" "otherf" "-v" "library" "-y" "dir"))
|
|
7005
|
|
7006 (defun verilog-getopt-file (filename)
|
|
7007 "Read verilog options from the specified FILENAME."
|
|
7008 (save-excursion
|
|
7009 (let ((fns (verilog-library-filenames filename (buffer-file-name)))
|
|
7010 (orig-buffer (current-buffer))
|
|
7011 line)
|
|
7012 (if fns
|
|
7013 (set-buffer (find-file-noselect (car fns)))
|
|
7014 (error (concat (verilog-point-text)
|
|
7015 "Can't find verilog-getopt-file -f file: " filename)))
|
|
7016 (goto-char (point-min))
|
|
7017 (while (not (eobp))
|
|
7018 (setq line (buffer-substring (point)
|
|
7019 (save-excursion (end-of-line) (point))))
|
|
7020 (forward-line 1)
|
|
7021 (when (string-match "//" line)
|
|
7022 (setq line (substring line 0 (match-beginning 0))))
|
|
7023 (save-excursion
|
|
7024 (set-buffer orig-buffer) ; Variables are buffer-local, so need right context.
|
|
7025 (verilog-getopt line))))))
|
|
7026
|
|
7027 (defun verilog-getopt-flags ()
|
|
7028 "Convert `verilog-library-flags' into standard library variables."
|
|
7029 ;; If the flags are local, then all the outputs should be local also
|
|
7030 (when (local-variable-p `verilog-library-flags (current-buffer))
|
|
7031 (make-variable-buffer-local 'verilog-library-extensions)
|
|
7032 (make-variable-buffer-local 'verilog-library-directories)
|
|
7033 (make-variable-buffer-local 'verilog-library-files)
|
|
7034 (make-variable-buffer-local 'verilog-library-flags))
|
|
7035 ;; Allow user to customize
|
|
7036 (run-hooks 'verilog-before-getopt-flags-hook)
|
|
7037 ;; Process arguments
|
|
7038 (verilog-getopt verilog-library-flags)
|
|
7039 ;; Allow user to customize
|
|
7040 (run-hooks 'verilog-getopt-flags-hook))
|
|
7041
|
|
7042 (defun verilog-add-list-unique (varref object)
|
|
7043 "Append to VARREF list the given OBJECT,
|
|
7044 unless it is already a member of the variable's list"
|
|
7045 (unless (member object (symbol-value varref))
|
|
7046 (set varref (append (symbol-value varref) (list object))))
|
|
7047 varref)
|
|
7048 ;;(progn (setq l '()) (verilog-add-list-unique `l "a") (verilog-add-list-unique `l "a") l)
|
|
7049
|
|
7050
|
|
7051 ;;
|
|
7052 ;; Module name lookup
|
|
7053 ;;
|
|
7054
|
|
7055 (defun verilog-module-inside-filename-p (module filename)
|
|
7056 "Return point if MODULE is specified inside FILENAME, else nil.
|
|
7057 Allows version control to check out the file if need be."
|
|
7058 (and (or (file-exists-p filename)
|
|
7059 (and
|
|
7060 (condition-case nil
|
|
7061 (fboundp 'vc-backend)
|
|
7062 (error nil))
|
|
7063 (vc-backend filename)))
|
|
7064 (let (pt)
|
|
7065 (save-excursion
|
|
7066 (set-buffer (find-file-noselect filename))
|
|
7067 (goto-char (point-min))
|
|
7068 (while (and
|
|
7069 ;; It may be tempting to look for verilog-defun-re, don't, it slows things down a lot!
|
|
7070 (verilog-re-search-forward-quick "\\<module\\>" nil t)
|
|
7071 (verilog-re-search-forward-quick "[(;]" nil t))
|
|
7072 (if (equal module (verilog-read-module-name))
|
|
7073 (setq pt (point))))
|
|
7074 pt))))
|
|
7075
|
|
7076 (defun verilog-is-number (symbol)
|
|
7077 "Return true if SYMBOL is number-like."
|
|
7078 (or (string-match "^[0-9 \t:]+$" symbol)
|
|
7079 (string-match "^[---]*[0-9]+$" symbol)
|
|
7080 (string-match "^[0-9 \t]+'s?[hdxbo][0-9a-fA-F_xz? \t]*$" symbol)
|
|
7081 ))
|
|
7082
|
|
7083 (defun verilog-symbol-detick (symbol wing-it)
|
|
7084 "Return a expanded SYMBOL name without any defines.
|
|
7085 If the variable vh-{symbol} is defined, return that value.
|
|
7086 If undefined, and WING-IT, return just SYMBOL without the tick, else nil."
|
|
7087 (while (and symbol (string-match "^`" symbol))
|
|
7088 (setq symbol (substring symbol 1))
|
|
7089 (setq symbol
|
|
7090 (if (boundp (intern (concat "vh-" symbol)))
|
|
7091 ;; Emacs has a bug where boundp on a buffer-local
|
|
7092 ;; variable in only one buffer returns t in another.
|
|
7093 ;; This can confuse, so check for nil.
|
|
7094 (let ((val (eval (intern (concat "vh-" symbol)))))
|
|
7095 (if (eq val nil)
|
|
7096 (if wing-it symbol nil)
|
|
7097 val))
|
|
7098 (if wing-it symbol nil))))
|
|
7099 symbol)
|
|
7100 ;;(verilog-symbol-detick "`mod" nil)
|
|
7101
|
|
7102 (defun verilog-symbol-detick-denumber (symbol)
|
|
7103 "Return SYMBOL with defines converted and any numbers dropped to nil."
|
|
7104 (when (string-match "^`" symbol)
|
|
7105 ;; This only will work if the define is a simple signal, not
|
|
7106 ;; something like a[b]. Sorry, it should be substituted into the parser
|
|
7107 (setq symbol
|
|
7108 (verilog-string-replace-matches
|
|
7109 "\[[^0-9: \t]+\]" "" nil nil
|
|
7110 (or (verilog-symbol-detick symbol nil)
|
|
7111 (if verilog-auto-sense-defines-constant
|
|
7112 "0"
|
|
7113 symbol)))))
|
|
7114 (if (verilog-is-number symbol)
|
|
7115 nil
|
|
7116 symbol))
|
|
7117
|
|
7118 (defun verilog-symbol-detick-text (text)
|
|
7119 "Return TEXT with any without any known defines.
|
|
7120 If the variable vh-{symbol} is defined, substitute that value."
|
|
7121 (let ((ok t) symbol val)
|
|
7122 (while (and ok (string-match "`\\([a-zA-Z0-9_]+\\)" text))
|
|
7123 (setq symbol (match-string 1 text))
|
|
7124 (message symbol)
|
|
7125 (cond ((and
|
|
7126 (boundp (intern (concat "vh-" symbol)))
|
|
7127 ;; Emacs has a bug where boundp on a buffer-local
|
|
7128 ;; variable in only one buffer returns t in another.
|
|
7129 ;; This can confuse, so check for nil.
|
|
7130 (setq val (eval (intern (concat "vh-" symbol)))))
|
|
7131 (setq text (replace-match val nil nil text)))
|
|
7132 (t (setq ok nil)))))
|
|
7133 text)
|
|
7134 ;;(progn (setq vh-mod "`foo" vh-foo "bar") (verilog-symbol-detick-text "bar `mod `undefed"))
|
|
7135
|
|
7136 (defun verilog-expand-dirnames (&optional dirnames)
|
|
7137 "Return a list of existing directories given a list of wildcarded DIRNAMES.
|
|
7138 Or, just the existing dirnames themselves if there are no wildcards."
|
|
7139 (interactive)
|
|
7140 (unless dirnames (error "`verilog-library-directories' should include at least '.'"))
|
|
7141 (setq dirnames (reverse dirnames)) ; not nreverse
|
|
7142 (let ((dirlist nil)
|
|
7143 pattern dirfile dirfiles dirname root filename rest)
|
|
7144 (while dirnames
|
|
7145 (setq dirname (substitute-in-file-name (car dirnames))
|
|
7146 dirnames (cdr dirnames))
|
|
7147 (cond ((string-match (concat "^\\(\\|[/\\]*[^*?]*[/\\]\\)" ;; root
|
|
7148 "\\([^/\\]*[*?][^/\\]*\\)" ;; filename with *?
|
|
7149 "\\(.*\\)") ;; rest
|
|
7150 dirname)
|
|
7151 (setq root (match-string 1 dirname)
|
|
7152 filename (match-string 2 dirname)
|
|
7153 rest (match-string 3 dirname)
|
|
7154 pattern filename)
|
|
7155 ;; now replace those * and ? with .+ and .
|
|
7156 ;; use ^ and /> to get only whole file names
|
|
7157 ;;verilog-string-replace-matches
|
|
7158 (setq pattern (verilog-string-replace-matches "[*]" ".+" nil nil pattern)
|
|
7159 pattern (verilog-string-replace-matches "[?]" "." nil nil pattern)
|
|
7160
|
|
7161 ;; Unfortunately allows abc/*/rtl to match abc/rtl
|
|
7162 ;; because abc/.. shows up in dirfiles. Solutions welcome.
|
|
7163 dirfiles (if (file-directory-p root) ; Ignore version control external
|
|
7164 (directory-files root t pattern nil)))
|
|
7165 (while dirfiles
|
|
7166 (setq dirfile (expand-file-name (concat (car dirfiles) rest))
|
|
7167 dirfiles (cdr dirfiles))
|
|
7168 (if (file-directory-p dirfile)
|
|
7169 (setq dirlist (cons dirfile dirlist))))
|
|
7170 )
|
|
7171 ;; Defaults
|
|
7172 (t
|
|
7173 (if (file-directory-p dirname)
|
|
7174 (setq dirlist (cons dirname dirlist))))
|
|
7175 ))
|
|
7176 dirlist))
|
|
7177 ;;(verilog-expand-dirnames (list "." ".." "nonexist" "../*" "/home/wsnyder/*/v"))
|
|
7178
|
|
7179 (defun verilog-library-filenames (filename current &optional check-ext)
|
|
7180 "Return a search path to find the given FILENAME name.
|
|
7181 Uses the CURRENT filename, `verilog-library-directories' and
|
|
7182 `verilog-library-extensions' variables to build the path.
|
|
7183 With optional CHECK-EXT also check `verilog-library-extensions'."
|
|
7184 (let ((ckdir (verilog-expand-dirnames verilog-library-directories))
|
|
7185 fn outlist)
|
|
7186 (while ckdir
|
|
7187 (let ((ckext (if check-ext verilog-library-extensions `(""))))
|
|
7188 (while ckext
|
|
7189 (setq fn (expand-file-name
|
|
7190 (concat filename (car ckext))
|
|
7191 (expand-file-name (car ckdir) (file-name-directory current))))
|
|
7192 (if (file-exists-p fn)
|
|
7193 (setq outlist (cons fn outlist)))
|
|
7194 (setq ckext (cdr ckext))))
|
|
7195 (setq ckdir (cdr ckdir)))
|
|
7196 (nreverse outlist)))
|
|
7197
|
|
7198 (defun verilog-module-filenames (module current)
|
|
7199 "Return a search path to find the given MODULE name.
|
|
7200 Uses the CURRENT filename, `verilog-library-extensions',
|
|
7201 `verilog-library-directories' and `verilog-library-files'
|
|
7202 variables to build the path."
|
|
7203 ;; Return search locations for it
|
|
7204 (append (list current) ; first, current buffer
|
|
7205 (verilog-library-filenames module current t)
|
|
7206 verilog-library-files)) ; finally, any libraries
|
|
7207
|
|
7208 ;;
|
|
7209 ;; Module Information
|
|
7210 ;;
|
|
7211 ;; Many of these functions work on "modi" a module information structure
|
|
7212 ;; A modi is: [module-name-string file-name begin-point]
|
|
7213
|
|
7214 (defvar verilog-cache-enabled t
|
|
7215 "If true, enable caching of signals, etc. Set to nil for debugging to make things SLOW!")
|
|
7216
|
|
7217 (defvar verilog-modi-cache-list nil
|
|
7218 "Cache of ((Module Function) Buf-Tick Buf-Modtime Func-Returns)...
|
|
7219 For speeding up verilog-modi-get-* commands.
|
|
7220 Buffer-local.")
|
|
7221
|
|
7222 (defvar verilog-modi-cache-preserve-tick nil
|
|
7223 "Modification tick after which the cache is still considered valid.
|
|
7224 Use verilog-preserve-cache's to set")
|
|
7225 (defvar verilog-modi-cache-preserve-buffer nil
|
|
7226 "Modification tick after which the cache is still considered valid.
|
|
7227 Use verilog-preserve-cache's to set")
|
|
7228
|
|
7229 (defun verilog-modi-current ()
|
|
7230 "Return the modi structure for the module currently at point."
|
|
7231 (let* (name pt)
|
|
7232 ;; read current module's name
|
|
7233 (save-excursion
|
|
7234 (verilog-re-search-backward-quick verilog-defun-re nil nil)
|
|
7235 (verilog-re-search-forward-quick "(" nil nil)
|
|
7236 (setq name (verilog-read-module-name))
|
|
7237 (setq pt (point)))
|
|
7238 ;; return
|
|
7239 (vector name (or (buffer-file-name) (current-buffer)) pt)))
|
|
7240
|
|
7241 (defvar verilog-modi-lookup-last-mod nil "Cache of last module looked up.")
|
|
7242 (defvar verilog-modi-lookup-last-modi nil "Cache of last modi returned.")
|
|
7243 (defvar verilog-modi-lookup-last-current nil "Cache of last `current-buffer' looked up.")
|
|
7244 (defvar verilog-modi-lookup-last-tick nil "Cache of last `buffer-modified-tick' looked up.")
|
|
7245
|
|
7246 (defun verilog-modi-lookup (module allow-cache &optional ignore-error)
|
|
7247 "Find the file and point at which MODULE is defined.
|
|
7248 If ALLOW-CACHE is set, check and remember cache of previous lookups.
|
|
7249 Return modi if successful, else print message unless IGNORE-ERROR is true."
|
|
7250 (let* ((current (or (buffer-file-name) (current-buffer))))
|
|
7251 (cond ((and verilog-modi-lookup-last-modi
|
|
7252 verilog-cache-enabled
|
|
7253 allow-cache
|
|
7254 (equal verilog-modi-lookup-last-mod module)
|
|
7255 (equal verilog-modi-lookup-last-current current)
|
|
7256 (equal verilog-modi-lookup-last-tick (buffer-modified-tick)))
|
|
7257 ;; ok as is
|
|
7258 )
|
|
7259 (t (let* ((realmod (verilog-symbol-detick module t))
|
|
7260 (orig-filenames (verilog-module-filenames realmod current))
|
|
7261 (filenames orig-filenames)
|
|
7262 pt)
|
|
7263 (while (and filenames (not pt))
|
|
7264 (if (not (setq pt (verilog-module-inside-filename-p realmod (car filenames))))
|
|
7265 (setq filenames (cdr filenames))))
|
|
7266 (cond (pt (setq verilog-modi-lookup-last-modi
|
|
7267 (vector realmod (car filenames) pt)))
|
|
7268 (t (setq verilog-modi-lookup-last-modi nil)
|
|
7269 (or ignore-error
|
|
7270 (error (concat (verilog-point-text)
|
|
7271 ": Can't locate " module " module definition"
|
|
7272 (if (not (equal module realmod))
|
|
7273 (concat " (Expanded macro to " realmod ")")
|
|
7274 "")
|
|
7275 "\n Check the verilog-library-directories variable."
|
|
7276 "\n I looked in (if not listed, doesn't exist):\n\t"
|
|
7277 (mapconcat 'concat orig-filenames "\n\t")))))
|
|
7278 )
|
|
7279 (setq verilog-modi-lookup-last-mod module
|
|
7280 verilog-modi-lookup-last-current current
|
|
7281 verilog-modi-lookup-last-tick (buffer-modified-tick)))))
|
|
7282 verilog-modi-lookup-last-modi
|
|
7283 ))
|
|
7284
|
|
7285 (defsubst verilog-modi-name (modi)
|
|
7286 (aref modi 0))
|
|
7287 (defsubst verilog-modi-file-or-buffer (modi)
|
|
7288 (aref modi 1))
|
|
7289 (defsubst verilog-modi-point (modi)
|
|
7290 (aref modi 2))
|
|
7291
|
|
7292 (defun verilog-modi-filename (modi)
|
|
7293 "Filename of MODI, or name of buffer if its never been saved."
|
|
7294 (if (bufferp (verilog-modi-file-or-buffer modi))
|
|
7295 (or (buffer-file-name (verilog-modi-file-or-buffer modi))
|
|
7296 (buffer-name (verilog-modi-file-or-buffer modi)))
|
|
7297 (verilog-modi-file-or-buffer modi)))
|
|
7298
|
|
7299 (defun verilog-modi-goto (modi)
|
|
7300 "Move point/buffer to specified MODI."
|
|
7301 (or modi (error "Passed unfound modi to goto, check earlier"))
|
|
7302 (set-buffer (if (bufferp (verilog-modi-file-or-buffer modi))
|
|
7303 (verilog-modi-file-or-buffer modi)
|
|
7304 (find-file-noselect (verilog-modi-file-or-buffer modi))))
|
|
7305 (or (equal major-mode `verilog-mode) ;; Put into verilog mode to get syntax
|
|
7306 (verilog-mode))
|
|
7307 (goto-char (verilog-modi-point modi)))
|
|
7308
|
|
7309 (defun verilog-goto-defun-file (module)
|
|
7310 "Move point to the file at which a given MODULE is defined."
|
|
7311 (interactive "sGoto File for Module: ")
|
|
7312 (let* ((modi (verilog-modi-lookup module nil)))
|
|
7313 (when modi
|
|
7314 (verilog-modi-goto modi)
|
|
7315 (switch-to-buffer (current-buffer)))))
|
|
7316
|
|
7317 (defun verilog-modi-cache-results (modi function)
|
|
7318 "Run on MODI the given FUNCTION. Locate the module in a file.
|
|
7319 Cache the output of function so next call may have faster access."
|
|
7320 (let (func-returns fass)
|
|
7321 (save-excursion
|
|
7322 (verilog-modi-goto modi)
|
|
7323 (if (and (setq fass (assoc (list (verilog-modi-name modi) function)
|
|
7324 verilog-modi-cache-list))
|
|
7325 ;; Destroy caching when incorrect; Modified or file changed
|
|
7326 (not (and verilog-cache-enabled
|
|
7327 (or (equal (buffer-modified-tick) (nth 1 fass))
|
|
7328 (and verilog-modi-cache-preserve-tick
|
|
7329 (<= verilog-modi-cache-preserve-tick (nth 1 fass))
|
|
7330 (equal verilog-modi-cache-preserve-buffer (current-buffer))))
|
|
7331 (equal (visited-file-modtime) (nth 2 fass)))))
|
|
7332 (setq verilog-modi-cache-list nil
|
|
7333 fass nil))
|
|
7334 (cond (fass
|
|
7335 ;; Found
|
|
7336 (setq func-returns (nth 3 fass)))
|
|
7337 (t
|
|
7338 ;; Read from file
|
|
7339 ;; Clear then restore any hilighting to make emacs19 happy
|
|
7340 (let ((fontlocked (when (and (boundp 'font-lock-mode)
|
|
7341 font-lock-mode)
|
|
7342 (font-lock-mode nil)
|
|
7343 t)))
|
|
7344 (setq func-returns (funcall function))
|
|
7345 (when fontlocked (font-lock-mode t)))
|
|
7346 ;; Cache for next time
|
|
7347 (make-variable-buffer-local 'verilog-modi-cache-list)
|
|
7348 (setq verilog-modi-cache-list
|
|
7349 (cons (list (list (verilog-modi-name modi) function)
|
|
7350 (buffer-modified-tick)
|
|
7351 (visited-file-modtime)
|
|
7352 func-returns)
|
|
7353 verilog-modi-cache-list)))
|
|
7354 ))
|
|
7355 ;;
|
|
7356 func-returns))
|
|
7357
|
|
7358 (defun verilog-modi-cache-add (modi function element sig-list)
|
|
7359 "Add function return results to the module cache.
|
|
7360 Update MODI's cache for given FUNCTION so that the return ELEMENT of that
|
|
7361 function now contains the additional SIG-LIST parameters."
|
|
7362 (let (fass)
|
|
7363 (save-excursion
|
|
7364 (verilog-modi-goto modi)
|
|
7365 (if (setq fass (assoc (list (verilog-modi-name modi) function)
|
|
7366 verilog-modi-cache-list))
|
|
7367 (let ((func-returns (nth 3 fass)))
|
|
7368 (aset func-returns element
|
|
7369 (append sig-list (aref func-returns element))))))))
|
|
7370
|
|
7371 (defmacro verilog-preserve-cache (&rest body)
|
|
7372 "Execute the BODY forms, allowing cache preservation within BODY.
|
|
7373 This means that changes to the buffer will not result in the cache being
|
|
7374 flushed. If the changes affect the modsig state, they must call the
|
|
7375 modsig-cache-add-* function, else the results of later calls may be
|
|
7376 incorrect. Without this, changes are assumed to be adding/removing signals
|
|
7377 and invalidating the cache."
|
|
7378 `(let ((verilog-modi-cache-preserve-tick (buffer-modified-tick))
|
|
7379 (verilog-modi-cache-preserve-buffer (current-buffer)))
|
|
7380 (progn ,@body)))
|
|
7381
|
|
7382 (defsubst verilog-modi-get-decls (modi)
|
|
7383 (verilog-modi-cache-results modi 'verilog-read-decls))
|
|
7384
|
|
7385 (defsubst verilog-modi-get-sub-decls (modi)
|
|
7386 (verilog-modi-cache-results modi 'verilog-read-sub-decls))
|
|
7387
|
|
7388 ;; Signal reading for given module
|
|
7389 ;; Note these all take modi's - as returned from the verilog-modi-current function
|
|
7390 (defsubst verilog-modi-get-outputs (modi)
|
|
7391 (aref (verilog-modi-get-decls modi) 0))
|
|
7392 (defsubst verilog-modi-get-inouts (modi)
|
|
7393 (aref (verilog-modi-get-decls modi) 1))
|
|
7394 (defsubst verilog-modi-get-inputs (modi)
|
|
7395 (aref (verilog-modi-get-decls modi) 2))
|
|
7396 (defsubst verilog-modi-get-wires (modi)
|
|
7397 (aref (verilog-modi-get-decls modi) 3))
|
|
7398 (defsubst verilog-modi-get-regs (modi)
|
|
7399 (aref (verilog-modi-get-decls modi) 4))
|
|
7400 (defsubst verilog-modi-get-assigns (modi)
|
|
7401 (aref (verilog-modi-get-decls modi) 5))
|
|
7402 (defsubst verilog-modi-get-consts (modi)
|
|
7403 (aref (verilog-modi-get-decls modi) 6))
|
|
7404 (defsubst verilog-modi-get-gparams (modi)
|
|
7405 (aref (verilog-modi-get-decls modi) 7))
|
|
7406 (defsubst verilog-modi-get-sub-outputs (modi)
|
|
7407 (aref (verilog-modi-get-sub-decls modi) 0))
|
|
7408 (defsubst verilog-modi-get-sub-inouts (modi)
|
|
7409 (aref (verilog-modi-get-sub-decls modi) 1))
|
|
7410 (defsubst verilog-modi-get-sub-inputs (modi)
|
|
7411 (aref (verilog-modi-get-sub-decls modi) 2))
|
|
7412
|
|
7413
|
|
7414 (defun verilog-signals-matching-enum (in-list enum)
|
|
7415 "Return all signals in IN-LIST matching the given ENUM."
|
|
7416 (let (out-list)
|
|
7417 (while in-list
|
|
7418 (if (equal (verilog-sig-enum (car in-list)) enum)
|
|
7419 (setq out-list (cons (car in-list) out-list)))
|
|
7420 (setq in-list (cdr in-list)))
|
|
7421 ;; New scheme
|
|
7422 (let* ((enumvar (intern (concat "venum-" enum)))
|
|
7423 (enumlist (and (boundp enumvar) (eval enumvar))))
|
|
7424 (while enumlist
|
|
7425 (add-to-list 'out-list (list (car enumlist)))
|
|
7426 (setq enumlist (cdr enumlist))))
|
|
7427 (nreverse out-list)))
|
|
7428
|
|
7429 (defun verilog-signals-not-matching-regexp (in-list regexp)
|
|
7430 "Return all signals in IN-LIST not matching the given REGEXP, if non-nil."
|
|
7431 (if (not regexp)
|
|
7432 in-list
|
|
7433 (let (out-list)
|
|
7434 (while in-list
|
|
7435 (if (not (string-match regexp (verilog-sig-name (car in-list))))
|
|
7436 (setq out-list (cons (car in-list) out-list)))
|
|
7437 (setq in-list (cdr in-list)))
|
|
7438 (nreverse out-list))))
|
|
7439
|
|
7440 ;; Combined
|
|
7441 (defun verilog-modi-get-signals (modi)
|
|
7442 (append
|
|
7443 (verilog-modi-get-outputs modi)
|
|
7444 (verilog-modi-get-inouts modi)
|
|
7445 (verilog-modi-get-inputs modi)
|
|
7446 (verilog-modi-get-wires modi)
|
|
7447 (verilog-modi-get-regs modi)
|
|
7448 (verilog-modi-get-assigns modi)
|
|
7449 (verilog-modi-get-consts modi)
|
|
7450 (verilog-modi-get-gparams modi)))
|
|
7451
|
|
7452 (defun verilog-modi-get-ports (modi)
|
|
7453 (append
|
|
7454 (verilog-modi-get-outputs modi)
|
|
7455 (verilog-modi-get-inouts modi)
|
|
7456 (verilog-modi-get-inputs modi)))
|
|
7457
|
|
7458 (defsubst verilog-modi-cache-add-outputs (modi sig-list)
|
|
7459 (verilog-modi-cache-add modi 'verilog-read-decls 0 sig-list))
|
|
7460 (defsubst verilog-modi-cache-add-inouts (modi sig-list)
|
|
7461 (verilog-modi-cache-add modi 'verilog-read-decls 1 sig-list))
|
|
7462 (defsubst verilog-modi-cache-add-inputs (modi sig-list)
|
|
7463 (verilog-modi-cache-add modi 'verilog-read-decls 2 sig-list))
|
|
7464 (defsubst verilog-modi-cache-add-wires (modi sig-list)
|
|
7465 (verilog-modi-cache-add modi 'verilog-read-decls 3 sig-list))
|
|
7466 (defsubst verilog-modi-cache-add-regs (modi sig-list)
|
|
7467 (verilog-modi-cache-add modi 'verilog-read-decls 4 sig-list))
|
|
7468
|
|
7469 (defun verilog-signals-from-signame (signame-list)
|
|
7470 "Return signals in standard form from SIGNAME-LIST, a simple list of signal names."
|
|
7471 (mapcar (function (lambda (name) (list name nil nil)))
|
|
7472 signame-list))
|
|
7473
|
|
7474 ;;
|
|
7475 ;; Auto creation utilities
|
|
7476 ;;
|
|
7477
|
|
7478 (defun verilog-auto-search-do (search-for func)
|
|
7479 "Search for the given auto text SEARCH-FOR, and perform FUNC where it occurs."
|
|
7480 (goto-char (point-min))
|
|
7481 (while (search-forward search-for nil t)
|
|
7482 (if (not (save-excursion
|
|
7483 (goto-char (match-beginning 0))
|
|
7484 (verilog-inside-comment-p)))
|
|
7485 (funcall func))))
|
|
7486
|
|
7487 (defun verilog-auto-re-search-do (search-for func)
|
|
7488 "Search for the given auto text SEARCH-FOR, and perform FUNC where it occurs."
|
|
7489 (goto-char (point-min))
|
|
7490 (while (re-search-forward search-for nil t)
|
|
7491 (if (not (save-excursion
|
|
7492 (goto-char (match-beginning 0))
|
|
7493 (verilog-inside-comment-p)))
|
|
7494 (funcall func))))
|
|
7495
|
|
7496 (defun verilog-insert-one-definition (sig type indent-pt)
|
|
7497 "Print out a definition for SIGNAL of the given TYPE,
|
|
7498 with appropriate INDENT-PT indentation."
|
|
7499 (indent-to indent-pt)
|
|
7500 (insert type)
|
|
7501 (when (verilog-sig-signed sig)
|
|
7502 (insert " " (verilog-sig-signed sig)))
|
|
7503 (when (verilog-sig-multidim sig)
|
|
7504 (insert " " (verilog-sig-multidim-string sig)))
|
|
7505 (when (verilog-sig-bits sig)
|
|
7506 (insert " " (verilog-sig-bits sig)))
|
|
7507 (indent-to (max 24 (+ indent-pt 16)))
|
|
7508 (unless (= (char-syntax (preceding-char)) ?\ )
|
|
7509 (insert " ")) ; Need space between "]name" if indent-to did nothing
|
|
7510 (insert (verilog-sig-name sig)))
|
|
7511
|
|
7512 (defun verilog-insert-definition (sigs direction indent-pt v2k &optional dont-sort)
|
|
7513 "Print out a definition for a list of SIGS of the given DIRECTION,
|
|
7514 with appropriate INDENT-PT indentation. If V2K, use Verilog 2001 I/O
|
|
7515 format. Sort unless DONT-SORT. DIRECTION is normally wire/reg/output."
|
|
7516 (or dont-sort
|
|
7517 (setq sigs (sort (copy-alist sigs) `verilog-signals-sort-compare)))
|
|
7518 (while sigs
|
|
7519 (let ((sig (car sigs)))
|
|
7520 (verilog-insert-one-definition
|
|
7521 sig
|
|
7522 ;; Want "type x" or "output type x", not "wire type x"
|
|
7523 (cond ((verilog-sig-type sig)
|
|
7524 (concat
|
|
7525 (if (not (equal direction "wire"))
|
|
7526 (concat direction " "))
|
|
7527 (verilog-sig-type sig)))
|
|
7528 (t direction))
|
|
7529 indent-pt)
|
|
7530 (insert (if v2k "," ";"))
|
|
7531 (if (or (not (verilog-sig-comment sig))
|
|
7532 (equal "" (verilog-sig-comment sig)))
|
|
7533 (insert "\n")
|
|
7534 (indent-to (max 48 (+ indent-pt 40)))
|
|
7535 (insert (concat "// " (verilog-sig-comment sig) "\n")))
|
|
7536 (setq sigs (cdr sigs)))))
|
|
7537
|
|
7538 (eval-when-compile
|
|
7539 (if (not (boundp 'indent-pt))
|
|
7540 (defvar indent-pt nil "Local used by insert-indent")))
|
|
7541
|
|
7542 (defun verilog-insert-indent (&rest stuff)
|
|
7543 "Indent to position stored in local `indent-pt' variable, then insert STUFF.
|
|
7544 Presumes that any newlines end a list element."
|
|
7545 (let ((need-indent t))
|
|
7546 (while stuff
|
|
7547 (if need-indent (indent-to indent-pt))
|
|
7548 (setq need-indent nil)
|
|
7549 (insert (car stuff))
|
|
7550 (setq need-indent (string-match "\n$" (car stuff))
|
|
7551 stuff (cdr stuff)))))
|
|
7552 ;;(let ((indent-pt 10)) (verilog-insert-indent "hello\n" "addon" "there\n"))
|
|
7553
|
|
7554 (defun verilog-repair-open-comma ()
|
|
7555 "If backwards-from-point is other than a open parenthesis insert comma."
|
|
7556 (save-excursion
|
|
7557 (verilog-backward-syntactic-ws)
|
|
7558 (when (save-excursion
|
|
7559 (backward-char 1)
|
|
7560 (and (not (looking-at "[(,]"))
|
|
7561 (progn
|
|
7562 (verilog-re-search-backward "[(`]" nil t)
|
|
7563 (looking-at "("))))
|
|
7564 (insert ","))))
|
|
7565
|
|
7566 (defun verilog-repair-close-comma ()
|
|
7567 "If point is at a comma followed by a close parenthesis, fix it.
|
|
7568 This repairs those mis-inserted by a AUTOARG."
|
|
7569 ;; It would be much nicer if Verilog allowed extra commas like Perl does!
|
|
7570 (save-excursion
|
|
7571 (verilog-forward-close-paren)
|
|
7572 (backward-char 1)
|
|
7573 (verilog-backward-syntactic-ws)
|
|
7574 (backward-char 1)
|
|
7575 (when (looking-at ",")
|
|
7576 (delete-char 1))))
|
|
7577
|
|
7578 (defun verilog-get-list (start end)
|
|
7579 "Return the elements of a comma separated list between START and END."
|
|
7580 (interactive)
|
|
7581 (let ((my-list (list))
|
|
7582 my-string)
|
|
7583 (save-excursion
|
|
7584 (while (< (point) end)
|
|
7585 (when (re-search-forward "\\([^,{]+\\)" end t)
|
|
7586 (setq my-string (verilog-string-remove-spaces (match-string 1)))
|
|
7587 (setq my-list (nconc my-list (list my-string) ))
|
|
7588 (goto-char (match-end 0))))
|
|
7589 my-list)))
|
|
7590
|
|
7591 (defun verilog-make-width-expression (range-exp)
|
|
7592 "Return an expression calculating the length of a range [x:y] in RANGE-EXP."
|
|
7593 ;; strip off the []
|
|
7594 (cond ((not range-exp)
|
|
7595 "1")
|
|
7596 (t
|
|
7597 (if (string-match "^\\[\\(.*\\)\\]$" range-exp)
|
|
7598 (setq range-exp (match-string 1 range-exp)))
|
|
7599 (cond ((not range-exp)
|
|
7600 "1")
|
|
7601 ((string-match "^\\s *\\([0-9]+\\)\\s *:\\s *\\([0-9]+\\)\\s *$" range-exp)
|
|
7602 (int-to-string (1+ (abs (- (string-to-int (match-string 1 range-exp))
|
|
7603 (string-to-int (match-string 2 range-exp)))))))
|
|
7604 ((string-match "^\\(.*\\)\\s *:\\s *\\(.*\\)\\s *$" range-exp)
|
|
7605 (concat "(1+(" (match-string 1 range-exp)
|
|
7606 ")"
|
|
7607 (if (equal "0" (match-string 2 range-exp)) ;; Don't bother with -(0)
|
|
7608 ""
|
|
7609 (concat "-(" (match-string 2 range-exp) ")"))
|
|
7610 ")"))
|
|
7611 (t nil)))))
|
|
7612 ;;(verilog-make-width-expression "`A:`B")
|
|
7613
|
|
7614 (defun verilog-typedef-name-p (variable-name)
|
|
7615 "Return true if the VARIABLE-NAME is a type definition."
|
|
7616 (when verilog-typedef-regexp
|
|
7617 (string-match verilog-typedef-regexp variable-name)))
|
|
7618
|
|
7619 ;;
|
|
7620 ;; Auto deletion
|
|
7621 ;;
|
|
7622
|
|
7623 (defun verilog-delete-autos-lined ()
|
|
7624 "Delete autos that occupy multiple lines, between begin and end comments."
|
|
7625 (let ((pt (point)))
|
|
7626 (forward-line 1)
|
|
7627 (when (and
|
|
7628 (looking-at "\\s-*// Beginning")
|
|
7629 (search-forward "// End of automatic" nil t))
|
|
7630 ;; End exists
|
|
7631 (end-of-line)
|
|
7632 (delete-region pt (point))
|
|
7633 (forward-line 1))
|
|
7634 ))
|
|
7635
|
|
7636 (defun verilog-forward-close-paren ()
|
|
7637 "Find the close parenthesis that match the current point,
|
|
7638 ignore other close parenthesis with matching open parens"
|
|
7639 (let ((parens 1))
|
|
7640 (while (> parens 0)
|
|
7641 (unless (verilog-re-search-forward-quick "[()]" nil t)
|
|
7642 (error "%s: Mismatching ()" (verilog-point-text)))
|
|
7643 (cond ((= (preceding-char) ?\( )
|
|
7644 (setq parens (1+ parens)))
|
|
7645 ((= (preceding-char) ?\) )
|
|
7646 (setq parens (1- parens)))))))
|
|
7647
|
|
7648 (defun verilog-backward-open-paren ()
|
|
7649 "Find the open parenthesis that match the current point,
|
|
7650 ignore other open parenthesis with matching close parens"
|
|
7651 (let ((parens 1))
|
|
7652 (while (> parens 0)
|
|
7653 (unless (verilog-re-search-backward-quick "[()]" nil t)
|
|
7654 (error "%s: Mismatching ()" (verilog-point-text)))
|
|
7655 (cond ((= (following-char) ?\) )
|
|
7656 (setq parens (1+ parens)))
|
|
7657 ((= (following-char) ?\( )
|
|
7658 (setq parens (1- parens)))))))
|
|
7659
|
|
7660 (defun verilog-backward-open-bracket ()
|
|
7661 "Find the open bracket that match the current point,
|
|
7662 ignore other open bracket with matching close bracket"
|
|
7663 (let ((parens 1))
|
|
7664 (while (> parens 0)
|
|
7665 (unless (verilog-re-search-backward-quick "[][]" nil t)
|
|
7666 (error "%s: Mismatching []" (verilog-point-text)))
|
|
7667 (cond ((= (following-char) ?\] )
|
|
7668 (setq parens (1+ parens)))
|
|
7669 ((= (following-char) ?\[ )
|
|
7670 (setq parens (1- parens)))))))
|
|
7671
|
|
7672 (defun verilog-delete-to-paren ()
|
|
7673 "Delete the automatic inst/sense/arg created by autos.
|
|
7674 Deletion stops at the matching end parenthesis."
|
|
7675 (delete-region (point)
|
|
7676 (save-excursion
|
|
7677 (verilog-backward-open-paren)
|
|
7678 (forward-sexp 1) ;; Moves to paren that closes argdecl's
|
|
7679 (backward-char 1)
|
|
7680 (point))))
|
|
7681
|
|
7682 (defun verilog-auto-star-safe ()
|
|
7683 "Return if a .* AUTOINST is safe to delete or expand.
|
|
7684 It was created by the AUTOS themselves, or by the user."
|
|
7685 (and verilog-auto-star-expand
|
|
7686 (looking-at "[ \t\n\f,]*\\([)]\\|// \\(Outputs\\|Inouts\\|Inputs\\)\\)")))
|
|
7687
|
|
7688 (defun verilog-delete-auto-star-all ()
|
|
7689 "Delete a .* AUTOINST, if it is safe."
|
|
7690 (when (verilog-auto-star-safe)
|
|
7691 (verilog-delete-to-paren)))
|
|
7692
|
|
7693 (defun verilog-delete-auto-star-implicit ()
|
|
7694 "Delete all .* implicit connections created by `verilog-auto-star'.
|
|
7695 This function will be called automatically at save unless
|
|
7696 `verilog-auto-star-save' is set, any non-templated expanded pins will be
|
|
7697 removed."
|
|
7698 (interactive)
|
|
7699 (let (paren-pt indent have-close-paren)
|
|
7700 (save-excursion
|
|
7701 (goto-char (point-min))
|
|
7702 ;; We need to match these even outside of comments.
|
|
7703 ;; For reasonable performance, we don't check if inside comments, sorry.
|
|
7704 (while (re-search-forward "// Implicit \\.\\*" nil t)
|
|
7705 (setq paren-pt (point))
|
|
7706 (beginning-of-line)
|
|
7707 (setq have-close-paren
|
|
7708 (save-excursion
|
|
7709 (when (search-forward ");" paren-pt t)
|
|
7710 (setq indent (current-indentation))
|
|
7711 t)))
|
|
7712 (delete-region (point) (+ 1 paren-pt)) ; Nuke line incl CR
|
|
7713 (when have-close-paren
|
|
7714 ;; Delete extra commentary
|
|
7715 (save-excursion
|
|
7716 (while (progn
|
|
7717 (forward-line -1)
|
|
7718 (looking-at "\\s *//\\s *\\(Outputs\\|Inouts\\|Inputs\\)\n"))
|
|
7719 (delete-region (match-beginning 0) (match-end 0))))
|
|
7720 ;; If it is simple, we can put the ); on the same line as the last text
|
|
7721 (let ((rtn-pt (point)))
|
|
7722 (save-excursion
|
|
7723 (while (progn (backward-char 1)
|
|
7724 (looking-at "[ \t\n\f]")))
|
|
7725 (when (looking-at ",")
|
|
7726 (delete-region (+ 1 (point)) rtn-pt))))
|
|
7727 (when (bolp)
|
|
7728 (indent-to indent))
|
|
7729 (insert ");\n")
|
|
7730 ;; Still need to kill final comma - always is one as we put one after the .*
|
|
7731 (re-search-backward ",")
|
|
7732 (delete-char 1))))))
|
|
7733
|
|
7734 (defun verilog-delete-auto ()
|
|
7735 "Delete the automatic outputs, regs, and wires created by \\[verilog-auto].
|
|
7736 Use \\[verilog-auto] to re-insert the updated AUTOs.
|
|
7737
|
|
7738 The hooks `verilog-before-delete-auto-hook' and `verilog-delete-auto-hook' are
|
|
7739 called before and after this function, respectively."
|
|
7740 (interactive)
|
|
7741 (save-excursion
|
|
7742 (if (buffer-file-name)
|
|
7743 (find-file-noselect (buffer-file-name))) ;; To check we have latest version
|
|
7744 ;; Allow user to customize
|
|
7745 (run-hooks 'verilog-before-delete-auto-hook)
|
|
7746
|
|
7747 ;; Remove those that have multi-line insertions
|
|
7748 (verilog-auto-re-search-do "/\\*AUTO\\(OUTPUTEVERY\\|CONCATCOMMENT\\|WIRE\\|REG\\|DEFINEVALUE\\|REGINPUT\\|INPUT\\|OUTPUT\\|INOUT\\|RESET\\|TIEOFF\\|UNUSED\\)\\*/"
|
|
7749 'verilog-delete-autos-lined)
|
|
7750 ;; Remove those that have multi-line insertions with parameters
|
|
7751 (verilog-auto-re-search-do "/\\*AUTO\\(INOUTMODULE\\|ASCIIENUM\\)([^)]*)\\*/"
|
|
7752 'verilog-delete-autos-lined)
|
|
7753 ;; Remove those that are in parenthesis
|
|
7754 (verilog-auto-re-search-do "/\\*\\(AS\\|AUTO\\(ARG\\|CONCATWIDTH\\|INST\\|INSTPARAM\\|SENSE\\)\\)\\*/"
|
|
7755 'verilog-delete-to-paren)
|
|
7756 ;; Do .* instantiations, but avoid removing any user pins by looking for our magic comments
|
|
7757 (verilog-auto-re-search-do "\\.\\*"
|
|
7758 'verilog-delete-auto-star-all)
|
|
7759 ;; Remove template comments ... anywhere in case was pasted after AUTOINST removed
|
|
7760 (goto-char (point-min))
|
|
7761 (while (re-search-forward "\\s-*// \\(Templated\\|Implicit \\.\\*\\)[ \tLT0-9]*$" nil t)
|
|
7762 (replace-match ""))
|
|
7763
|
|
7764 ;; Final customize
|
|
7765 (run-hooks 'verilog-delete-auto-hook)))
|
|
7766
|
|
7767 ;;
|
|
7768 ;; Auto inject
|
|
7769 ;;
|
|
7770
|
|
7771 (defun verilog-inject-auto ()
|
|
7772 "Examine legacy non-AUTO code and insert AUTOs in appropriate places.
|
|
7773
|
|
7774 Any always @ blocks with sensitivity lists that match computed lists will
|
|
7775 be replaced with /*AS*/ comments.
|
|
7776
|
|
7777 Any cells will get /*AUTOINST*/ added to the end of the pin list. Pins with
|
|
7778 have identical names will be deleted.
|
|
7779
|
|
7780 Argument lists will not be deleted, /*AUTOARG*/ will only be inserted to
|
|
7781 support adding new ports. You may wish to delete older ports yourself.
|
|
7782
|
|
7783 For example:
|
|
7784
|
|
7785 module ex_inject (i, o);
|
|
7786 input i;
|
|
7787 input j;
|
|
7788 output o;
|
|
7789 always @ (i or j)
|
|
7790 o = i | j;
|
|
7791 cell cell (.foobar(baz),
|
|
7792 .j(j));
|
|
7793 endmodule
|
|
7794
|
|
7795 Typing \\[verilog-inject-auto] will make this into:
|
|
7796
|
|
7797 module ex_inject (i, o/*AUTOARG*/
|
|
7798 // Inputs
|
|
7799 j);
|
|
7800 input i;
|
|
7801 output o;
|
|
7802 always @ (/*AS*/i or j)
|
|
7803 o = i | j;
|
|
7804 cell cell (.foobar(baz),
|
|
7805 /*AUTOINST*/
|
|
7806 // Outputs
|
|
7807 .j(j));
|
|
7808 endmodule"
|
|
7809 (interactive)
|
|
7810 (verilog-auto t))
|
|
7811
|
|
7812 (defun verilog-inject-arg ()
|
|
7813 "Inject AUTOARG into new code. See `verilog-inject-auto'."
|
|
7814 ;; Presume one module per file.
|
|
7815 (save-excursion
|
|
7816 (goto-char (point-min))
|
|
7817 (while (verilog-re-search-forward-quick "\\<module\\>" nil t)
|
|
7818 (let ((endmodp (save-excursion
|
|
7819 (verilog-re-search-forward-quick "\\<endmodule\\>" nil t)
|
|
7820 (point))))
|
|
7821 ;; See if there's already a comment .. inside a comment so not verilog-re-search
|
|
7822 (when (not (re-search-forward "/\\*AUTOARG\\*/" endmodp t))
|
|
7823 (verilog-re-search-forward-quick ";" nil t)
|
|
7824 (backward-char 1)
|
|
7825 (verilog-backward-syntactic-ws)
|
|
7826 (backward-char 1) ; Moves to paren that closes argdecl's
|
|
7827 (when (looking-at ")")
|
|
7828 (insert "/*AUTOARG*/")))))))
|
|
7829
|
|
7830 (defun verilog-inject-sense ()
|
|
7831 "Inject AUTOSENSE into new code. See `verilog-inject-auto'."
|
|
7832 (save-excursion
|
|
7833 (goto-char (point-min))
|
|
7834 (while (verilog-re-search-forward-quick "\\<always\\s *@\\s *(" nil t)
|
|
7835 (let ((start-pt (point))
|
|
7836 (modi (verilog-modi-current))
|
|
7837 pre-sigs
|
|
7838 got-sigs)
|
|
7839 (backward-char 1)
|
|
7840 (forward-sexp 1)
|
|
7841 (backward-char 1) ;; End )
|
|
7842 (when (not (verilog-re-search-backward "/\\*\\(AUTOSENSE\\|AS\\)\\*/" start-pt t))
|
|
7843 (setq pre-sigs (verilog-signals-from-signame
|
|
7844 (verilog-read-signals start-pt (point)))
|
|
7845 got-sigs (verilog-auto-sense-sigs modi nil))
|
|
7846 (when (not (or (verilog-signals-not-in pre-sigs got-sigs) ; Both are equal?
|
|
7847 (verilog-signals-not-in got-sigs pre-sigs)))
|
|
7848 (delete-region start-pt (point))
|
|
7849 (insert "/*AS*/")))))))
|
|
7850
|
|
7851 (defun verilog-inject-inst ()
|
|
7852 "Inject AUTOINST into new code. See `verilog-inject-auto'."
|
|
7853 (save-excursion
|
|
7854 (goto-char (point-min))
|
|
7855 ;; It's hard to distinguish modules; we'll instead search for pins.
|
|
7856 (while (verilog-re-search-forward-quick "\\.\\s *[a-zA-Z0-9`_\$]+\\s *(\\s *[a-zA-Z0-9`_\$]+\\s *)" nil t)
|
|
7857 (verilog-backward-open-paren) ;; Inst start
|
|
7858 (cond
|
|
7859 ((= (preceding-char) ?\#) ;; #(...) parameter section, not pin. Skip.
|
|
7860 (forward-char 1)
|
|
7861 (verilog-forward-close-paren)) ;; Parameters done
|
|
7862 (t
|
|
7863 (forward-char 1)
|
|
7864 (let ((indent-pt (+ (current-column)))
|
|
7865 (end-pt (save-excursion (verilog-forward-close-paren) (point))))
|
|
7866 (cond ((verilog-re-search-forward "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-pt t)
|
|
7867 (goto-char end-pt)) ;; Already there, continue search with next instance
|
|
7868 (t
|
|
7869 ;; Delete identical interconnect
|
|
7870 (let ((case-fold-search nil)) ;; So we don't convert upper-to-lower, etc
|
|
7871 (while (verilog-re-search-forward "\\.\\s *\\([a-zA-Z0-9`_\$]+\\)*\\s *(\\s *\\1\\s *)\\s *" end-pt t)
|
|
7872 (delete-region (match-beginning 0) (match-end 0))
|
|
7873 (setq end-pt (- end-pt (- (match-end 0) (match-beginning 0)))) ;; Keep it correct
|
|
7874 (while (or (looking-at "[ \t\n\f,]+")
|
|
7875 (looking-at "//[^\n]*"))
|
|
7876 (delete-region (match-beginning 0) (match-end 0))
|
|
7877 (setq end-pt (- end-pt (- (match-end 0) (match-beginning 0)))))))
|
|
7878 (verilog-forward-close-paren)
|
|
7879 (backward-char 1)
|
|
7880 ;; Not verilog-re-search, as we don't want to strip comments
|
|
7881 (while (re-search-backward "[ \t\n\f]+" (- (point) 1) t)
|
|
7882 (delete-region (match-beginning 0) (match-end 0)))
|
|
7883 (insert "\n")
|
|
7884 (indent-to indent-pt)
|
|
7885 (insert "/*AUTOINST*/")))))))))
|
|
7886
|
|
7887 ;;
|
|
7888 ;; Auto save
|
|
7889 ;;
|
|
7890
|
|
7891 (defun verilog-auto-save-check ()
|
|
7892 "On saving see if we need auto update."
|
|
7893 (cond ((not verilog-auto-save-policy)) ; disabled
|
|
7894 ((not (save-excursion
|
|
7895 (save-match-data
|
|
7896 (let ((case-fold-search nil))
|
|
7897 (goto-char (point-min))
|
|
7898 (re-search-forward "AUTO" nil t))))))
|
|
7899 ((eq verilog-auto-save-policy 'force)
|
|
7900 (verilog-auto))
|
|
7901 ((not (buffer-modified-p)))
|
|
7902 ((eq verilog-auto-update-tick (buffer-modified-tick))) ; up-to-date
|
|
7903 ((eq verilog-auto-save-policy 'detect)
|
|
7904 (verilog-auto))
|
|
7905 (t
|
|
7906 (when (yes-or-no-p "AUTO statements not recomputed, do it now? ")
|
|
7907 (verilog-auto))
|
|
7908 ;; Don't ask again if didn't update
|
|
7909 (set (make-local-variable 'verilog-auto-update-tick) (buffer-modified-tick))
|
|
7910 ))
|
|
7911 (when (not verilog-auto-star-save)
|
|
7912 (verilog-delete-auto-star-implicit))
|
|
7913 nil) ;; Always return nil -- we don't write the file ourselves
|
|
7914
|
|
7915 (defun verilog-auto-read-locals ()
|
|
7916 "Return file local variable segment at bottom of file."
|
|
7917 (save-excursion
|
|
7918 (goto-char (point-max))
|
|
7919 (if (re-search-backward "Local Variables:" nil t)
|
|
7920 (buffer-substring-no-properties (point) (point-max))
|
|
7921 "")))
|
|
7922
|
|
7923 (defun verilog-auto-reeval-locals (&optional force)
|
|
7924 "Read file local variable segment at bottom of file if it has changed.
|
|
7925 If FORCE, always reread it."
|
|
7926 (make-variable-buffer-local 'verilog-auto-last-file-locals)
|
|
7927 (let ((curlocal (verilog-auto-read-locals)))
|
|
7928 (when (or force (not (equal verilog-auto-last-file-locals curlocal)))
|
|
7929 (setq verilog-auto-last-file-locals curlocal)
|
|
7930 ;; Note this may cause this function to be recursively invoked.
|
|
7931 ;; The above when statement will prevent it from recursing forever.
|
|
7932 (hack-local-variables)
|
|
7933 t)))
|
|
7934
|
|
7935 ;;
|
|
7936 ;; Auto creation
|
|
7937 ;;
|
|
7938
|
|
7939 (defun verilog-auto-arg-ports (sigs message indent-pt)
|
|
7940 "Print a list of ports for a AUTOINST.
|
|
7941 Takes SIGS list, adds MESSAGE to front and inserts each at INDENT-PT."
|
|
7942 (when sigs
|
|
7943 (insert "\n")
|
|
7944 (indent-to indent-pt)
|
|
7945 (insert message)
|
|
7946 (insert "\n")
|
|
7947 (let ((space ""))
|
|
7948 (indent-to indent-pt)
|
|
7949 (while sigs
|
|
7950 (cond ((> (+ 2 (current-column) (length (verilog-sig-name (car sigs)))) fill-column)
|
|
7951 (insert "\n")
|
|
7952 (indent-to indent-pt))
|
|
7953 (t (insert space)))
|
|
7954 (insert (verilog-sig-name (car sigs)) ",")
|
|
7955 (setq sigs (cdr sigs)
|
|
7956 space " ")))))
|
|
7957
|
|
7958 (defun verilog-auto-arg ()
|
|
7959 "Expand AUTOARG statements.
|
|
7960 Replace the argument declarations at the beginning of the
|
|
7961 module with ones automatically derived from input and output
|
|
7962 statements. This can be dangerous if the module is instantiated
|
|
7963 using position-based connections, so use only name-based when
|
|
7964 instantiating the resulting module. Long lines are split based
|
|
7965 on the `fill-column', see \\[set-fill-column].
|
|
7966
|
|
7967 Limitations:
|
|
7968 Concatenation and outputting partial busses is not supported.
|
|
7969
|
|
7970 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
|
|
7971
|
|
7972 For example:
|
|
7973
|
|
7974 module ex_arg (/*AUTOARG*/);
|
|
7975 input i;
|
|
7976 output o;
|
|
7977 endmodule
|
|
7978
|
|
7979 Typing \\[verilog-auto] will make this into:
|
|
7980
|
|
7981 module ex_arg (/*AUTOARG*/
|
|
7982 // Outputs
|
|
7983 o,
|
|
7984 // Inputs
|
|
7985 i
|
|
7986 );
|
|
7987 input i;
|
|
7988 output o;
|
|
7989 endmodule
|
|
7990
|
|
7991 Any ports declared between the ( and /*AUTOARG*/ are presumed to be
|
|
7992 predeclared and are not redeclared by AUTOARG. AUTOARG will make a
|
|
7993 conservative guess on adding a comma for the first signal, if you have any
|
|
7994 ifdefs or complicated expressions before the AUTOARG you will need to
|
|
7995 choose the comma yourself.
|
|
7996
|
|
7997 Avoid declaring ports manually, as it makes code harder to maintain."
|
|
7998 (save-excursion
|
|
7999 (let ((modi (verilog-modi-current))
|
|
8000 (skip-pins (aref (verilog-read-arg-pins) 0)))
|
|
8001 (verilog-repair-open-comma)
|
|
8002 (verilog-auto-arg-ports (verilog-signals-not-in
|
|
8003 (verilog-modi-get-outputs modi)
|
|
8004 skip-pins)
|
|
8005 "// Outputs"
|
|
8006 verilog-indent-level-declaration)
|
|
8007 (verilog-auto-arg-ports (verilog-signals-not-in
|
|
8008 (verilog-modi-get-inouts modi)
|
|
8009 skip-pins)
|
|
8010 "// Inouts"
|
|
8011 verilog-indent-level-declaration)
|
|
8012 (verilog-auto-arg-ports (verilog-signals-not-in
|
|
8013 (verilog-modi-get-inputs modi)
|
|
8014 skip-pins)
|
|
8015 "// Inputs"
|
|
8016 verilog-indent-level-declaration)
|
|
8017 (verilog-repair-close-comma)
|
|
8018 (unless (eq (char-before) ?/ )
|
|
8019 (insert "\n"))
|
|
8020 (indent-to verilog-indent-level-declaration)
|
|
8021 )))
|
|
8022
|
|
8023 (defun verilog-auto-inst-port-map (port-st)
|
|
8024 nil)
|
|
8025
|
|
8026 (defvar vector-skip-list nil) ; Prevent compile warning
|
|
8027 (defvar vl-cell-type nil "See `verilog-auto-inst'.") ; Prevent compile warning
|
|
8028 (defvar vl-cell-name nil "See `verilog-auto-inst'.") ; Prevent compile warning
|
|
8029 (defvar vl-name nil "See `verilog-auto-inst'.") ; Prevent compile warning
|
|
8030 (defvar vl-width nil "See `verilog-auto-inst'.") ; Prevent compile warning
|
|
8031 (defvar vl-dir nil "See `verilog-auto-inst'.") ; Prevent compile warning
|
|
8032
|
|
8033 (defun verilog-auto-inst-port (port-st indent-pt tpl-list tpl-num for-star)
|
|
8034 "Print out a instantiation connection for this PORT-ST.
|
|
8035 Insert to INDENT-PT, use template TPL-LIST.
|
|
8036 @ are instantiation numbers, replaced with TPL-NUM.
|
|
8037 @\"(expression @)\" are evaluated, with @ as a variable."
|
|
8038 (let* ((port (verilog-sig-name port-st))
|
|
8039 (tpl-ass (or (assoc port (car tpl-list))
|
|
8040 (verilog-auto-inst-port-map port-st)))
|
|
8041 ;; vl-* are documented for user use
|
|
8042 (vl-name (verilog-sig-name port-st))
|
|
8043 (vl-width (verilog-sig-width port-st))
|
|
8044 (vl-bits (if (or verilog-auto-inst-vector
|
|
8045 (not (assoc port vector-skip-list))
|
|
8046 (not (equal (verilog-sig-bits port-st)
|
|
8047 (verilog-sig-bits (assoc port vector-skip-list)))))
|
|
8048 (or (verilog-sig-bits port-st) "")
|
|
8049 ""))
|
|
8050 ;; Default if not found
|
|
8051 (tpl-net (if (verilog-sig-multidim port-st)
|
|
8052 (concat port "/*" (verilog-sig-multidim-string port-st)
|
|
8053 vl-bits "*/")
|
|
8054 (concat port vl-bits)))
|
|
8055 (case-fold-search nil))
|
|
8056 ;; Find template
|
|
8057 (cond (tpl-ass ; Template of exact port name
|
|
8058 (setq tpl-net (nth 1 tpl-ass)))
|
|
8059 ((nth 1 tpl-list) ; Wildcards in template, search them
|
|
8060 (let ((wildcards (nth 1 tpl-list)))
|
|
8061 (while wildcards
|
|
8062 (when (string-match (nth 0 (car wildcards)) port)
|
|
8063 (setq tpl-ass (car wildcards) ; so allow @ parsing
|
|
8064 tpl-net (replace-match (nth 1 (car wildcards))
|
|
8065 t nil port)))
|
|
8066 (setq wildcards (cdr wildcards))))))
|
|
8067 ;; Parse Templated variable
|
|
8068 (when tpl-ass
|
|
8069 ;; Evaluate @"(lispcode)"
|
|
8070 (when (string-match "@\".*[^\\]\"" tpl-net)
|
|
8071 (while (string-match "@\"\\(\\([^\\\"]*\\(\\\\.\\)*\\)*\\)\"" tpl-net)
|
|
8072 (setq tpl-net
|
|
8073 (concat
|
|
8074 (substring tpl-net 0 (match-beginning 0))
|
|
8075 (save-match-data
|
|
8076 (let* ((expr (match-string 1 tpl-net))
|
|
8077 (value
|
|
8078 (progn
|
|
8079 (setq expr (verilog-string-replace-matches "\\\\\"" "\"" nil nil expr))
|
|
8080 (setq expr (verilog-string-replace-matches "@" tpl-num nil nil expr))
|
|
8081 (prin1 (eval (car (read-from-string expr)))
|
|
8082 (lambda (ch) ())))))
|
|
8083 (if (numberp value) (setq value (number-to-string value)))
|
|
8084 value
|
|
8085 ))
|
|
8086 (substring tpl-net (match-end 0))))))
|
|
8087 ;; Replace @ and [] magic variables in final output
|
|
8088 (setq tpl-net (verilog-string-replace-matches "@" tpl-num nil nil tpl-net))
|
|
8089 (setq tpl-net (verilog-string-replace-matches "\\[\\]" vl-bits nil nil tpl-net))
|
|
8090 )
|
|
8091 (indent-to indent-pt)
|
|
8092 (insert "." port)
|
|
8093 (indent-to verilog-auto-inst-column)
|
|
8094 (insert "(" tpl-net "),")
|
|
8095 (cond (tpl-ass
|
|
8096 (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
|
|
8097 verilog-auto-inst-column))
|
|
8098 (insert " // Templated")
|
|
8099 (when verilog-auto-inst-template-numbers
|
|
8100 (insert " T" (int-to-string (nth 2 tpl-ass))
|
|
8101 " L" (int-to-string (nth 3 tpl-ass)))))
|
|
8102 (for-star
|
|
8103 (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16)
|
|
8104 verilog-auto-inst-column))
|
|
8105 (insert " // Implicit .\*"))) ;For some reason the . or * must be escaped...
|
|
8106 (insert "\n")))
|
|
8107 ;;(verilog-auto-inst-port (list "foo" "[5:0]") 10 (list (list "foo" "a@\"(% (+ @ 1) 4)\"a")) "3")
|
|
8108 ;;(x "incom[@\"(+ (* 8 @) 7)\":@\"(* 8 @)\"]")
|
|
8109 ;;(x ".out (outgo[@\"(concat (+ (* 8 @) 7) \\\":\\\" ( * 8 @))\"]));")
|
|
8110
|
|
8111 (defun verilog-auto-inst-first ()
|
|
8112 "Insert , etc before first ever port in this instant, as part of \\[verilog-auto-inst]."
|
|
8113 ;; Do we need a trailing comma?
|
|
8114 ;; There maybe a ifdef or something similar before us. What a mess. Thus
|
|
8115 ;; to avoid trouble we only insert on preceeding ) or *.
|
|
8116 ;; Insert first port on new line
|
|
8117 (insert "\n") ;; Must insert before search, so point will move forward if insert comma
|
|
8118 (save-excursion
|
|
8119 (verilog-re-search-backward "[^ \t\n\f]" nil nil)
|
|
8120 (when (looking-at ")\\|\\*") ;; Generally don't insert, unless we are fairly sure
|
|
8121 (forward-char 1)
|
|
8122 (insert ","))))
|
|
8123
|
|
8124 (defun verilog-auto-star ()
|
|
8125 "Expand SystemVerilog .* pins, as part of \\[verilog-auto].
|
|
8126
|
|
8127 If `verilog-auto-star-expand' is set, .* pins are treated if they were
|
|
8128 AUTOINST statements, otherwise they are ignored. For safety, Verilog-Mode
|
|
8129 will also ignore any .* that are not last in your pin list (this prevents
|
|
8130 it from deleting pins following the .* when it expands the AUTOINST.)
|
|
8131
|
|
8132 On writing your file, unless `verilog-auto-star-save' is set, any
|
|
8133 non-templated expanded pins will be removed. You may do this at any time
|
|
8134 with \\[verilog-delete-auto-star-implicit].
|
|
8135
|
|
8136 If you are converting a module to use .* for the first time, you may wish
|
|
8137 to use \\[verilog-inject-auto] and then replace the created AUTOINST with .*.
|
|
8138
|
|
8139 See `verilog-auto-inst' for examples, templates, and more information."
|
|
8140 (when (verilog-auto-star-safe)
|
|
8141 (verilog-auto-inst)))
|
|
8142
|
|
8143 (defun verilog-auto-inst ()
|
|
8144 "Expand AUTOINST statements, as part of \\[verilog-auto].
|
|
8145 Replace the pin connections to an instantiation with ones
|
|
8146 automatically derived from the module header of the instantiated netlist.
|
|
8147
|
|
8148 If `verilog-auto-star-expand' is set, also expand SystemVerilog .* ports,
|
|
8149 and delete them before saving unless `verilog-auto-star-save' is set.
|
|
8150 See `verilog-auto-star' for more information.
|
|
8151
|
|
8152 Limitations:
|
|
8153 Module names must be resolvable to filenames by adding a
|
|
8154 `verilog-library-extensions', and being found in the same directory, or
|
|
8155 by changing the variable `verilog-library-flags' or
|
|
8156 `verilog-library-directories'. Macros `modname are translated through the
|
|
8157 vh-{name} Emacs variable, if that is not found, it just ignores the `.
|
|
8158
|
|
8159 In templates you must have one signal per line, ending in a ), or ));,
|
|
8160 and have proper () nesting, including a final ); to end the template.
|
|
8161
|
|
8162 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
|
|
8163
|
|
8164 SystemVerilog multidimmensional input/output has only experimental support.
|
|
8165
|
|
8166 For example, first take the submodule inst.v:
|
|
8167
|
|
8168 module inst (o,i)
|
|
8169 output [31:0] o;
|
|
8170 input i;
|
|
8171 wire [31:0] o = {32{i}};
|
|
8172 endmodule
|
|
8173
|
|
8174 This is then used in a upper level module:
|
|
8175
|
|
8176 module ex_inst (o,i)
|
|
8177 output o;
|
|
8178 input i;
|
|
8179 inst inst (/*AUTOINST*/);
|
|
8180 endmodule
|
|
8181
|
|
8182 Typing \\[verilog-auto] will make this into:
|
|
8183
|
|
8184 module ex_inst (o,i)
|
|
8185 output o;
|
|
8186 input i;
|
|
8187 inst inst (/*AUTOINST*/
|
|
8188 // Outputs
|
|
8189 .ov (ov[31:0]),
|
|
8190 // Inputs
|
|
8191 .i (i));
|
|
8192 endmodule
|
|
8193
|
|
8194 Where the list of inputs and outputs came from the inst module.
|
|
8195
|
|
8196 Exceptions:
|
|
8197
|
|
8198 Unless you are instantiating a module multiple times, or the module is
|
|
8199 something trivial like a adder, DO NOT CHANGE SIGNAL NAMES ACROSS HIERARCHY.
|
|
8200 It just makes for unmaintainable code. To sanitize signal names, try
|
|
8201 vrename from http://www.veripool.com
|
|
8202
|
|
8203 When you need to violate this suggestion there are two ways to list
|
|
8204 exceptions, placing them before the AUTOINST, or using templates.
|
|
8205
|
|
8206 Any ports defined before the /*AUTOINST*/ are not included in the list of
|
|
8207 automatics. This is similar to making a template as described below, but
|
|
8208 is restricted to simple connections just like you normally make. Also note
|
|
8209 that any signals before the AUTOINST will only be picked up by AUTOWIRE if
|
|
8210 you have the appropriate // Input or // Output comment, and exactly the
|
|
8211 same line formatting as AUTOINST itself uses.
|
|
8212
|
|
8213 inst inst (// Inputs
|
|
8214 .i (my_i_dont_mess_with_it),
|
|
8215 /*AUTOINST*/
|
|
8216 // Outputs
|
|
8217 .ov (ov[31:0]));
|
|
8218
|
|
8219
|
|
8220 Templates:
|
|
8221
|
|
8222 For multiple instantiations based upon a single template, create a
|
|
8223 commented out template:
|
|
8224
|
|
8225 /* instantiating_module_name AUTO_TEMPLATE (
|
|
8226 .sig3 (sigz[]),
|
|
8227 );
|
|
8228 */
|
|
8229
|
|
8230 Templates go ABOVE the instantiation(s). When a instantiation is
|
|
8231 expanded `verilog-mode' simply searches up for the closest template.
|
|
8232 Thus you can have multiple templates for the same module, just alternate
|
|
8233 between the template for a instantiation and the instantiation itself.
|
|
8234
|
|
8235 The module name must be the same as the name of the module in the
|
|
8236 instantiation name, and the code \"AUTO_TEMPLATE\" must be in these exact
|
|
8237 words and capitalized. Only signals that must be different for each
|
|
8238 instantiation need to be listed.
|
|
8239
|
|
8240 Inside a template, a [] in a connection name (with nothing else inside
|
|
8241 the brackets) will be replaced by the same bus subscript as it is being
|
|
8242 connected to, or the [] will be removed if it is a single bit signal.
|
|
8243 Generally it is a good idea to do this for all connections in a template,
|
|
8244 as then they will work for any width signal, and with AUTOWIRE. See
|
|
8245 PTL_BUS becoming PTL_BUSNEW below.
|
|
8246
|
|
8247 If you have a complicated template, set `verilog-auto-inst-template-numbers'
|
|
8248 to see which regexps are matching. Don't leave that mode set after
|
|
8249 debugging is completed though, it will result in lots of extra differences
|
|
8250 and merge conflicts.
|
|
8251
|
|
8252 For example:
|
|
8253
|
|
8254 /* psm_mas AUTO_TEMPLATE (
|
|
8255 .ptl_bus (ptl_busnew[]),
|
|
8256 );
|
|
8257 */
|
|
8258 psm_mas ms2m (/*AUTOINST*/);
|
|
8259
|
|
8260 Typing \\[verilog-auto] will make this into:
|
|
8261
|
|
8262 psm_mas ms2m (/*AUTOINST*/
|
|
8263 // Outputs
|
|
8264 .NotInTemplate (NotInTemplate),
|
|
8265 .ptl_bus (ptl_busnew[3:0]), // Templated
|
|
8266 ....
|
|
8267
|
|
8268 @ Templates:
|
|
8269
|
|
8270 It is common to instantiate a cell multiple times, so templates make it
|
|
8271 trivial to substitute part of the cell name into the connection name.
|
|
8272
|
|
8273 /* cell_type AUTO_TEMPLATE <optional \"REGEXP\"> (
|
|
8274 .sig1 (sigx[@]),
|
|
8275 .sig2 (sigy[@\"(% (+ 1 @) 4)\"]),
|
|
8276 );
|
|
8277 */
|
|
8278
|
|
8279 If no regular expression is provided immediately after the AUTO_TEMPLATE
|
|
8280 keyword, then the @ character in any connection names will be replaced
|
|
8281 with the instantiation number; the first digits found in the cell's
|
|
8282 instantiation name.
|
|
8283
|
|
8284 If a regular expression is provided, the @ character will be replaced
|
|
8285 with the first \(\) grouping that matches against the cell name. Using a
|
|
8286 regexp of \"\\([0-9]+\\)\" provides identical values for @ as when no
|
|
8287 regexp is provided. If you use multiple layers of parenthesis,
|
|
8288 \"test\\([^0-9]+\\)_\\([0-9]+\\)\" would replace @ with non-number
|
|
8289 characters after test and before _, whereas
|
|
8290 \"\\(test\\([a-z]+\\)_\\([0-9]+\\)\\)\" would replace @ with the entire
|
|
8291 match.
|
|
8292
|
|
8293 For example:
|
|
8294
|
|
8295 /* psm_mas AUTO_TEMPLATE (
|
|
8296 .ptl_mapvalidx (ptl_mapvalid[@]),
|
|
8297 .ptl_mapvalidp1x (ptl_mapvalid[@\"(% (+ 1 @) 4)\"]),
|
|
8298 );
|
|
8299 */
|
|
8300 psm_mas ms2m (/*AUTOINST*/);
|
|
8301
|
|
8302 Typing \\[verilog-auto] will make this into:
|
|
8303
|
|
8304 psm_mas ms2m (/*AUTOINST*/
|
|
8305 // Outputs
|
|
8306 .ptl_mapvalidx (ptl_mapvalid[2]),
|
|
8307 .ptl_mapvalidp1x (ptl_mapvalid[3]));
|
|
8308
|
|
8309 Note the @ character was replaced with the 2 from \"ms2m\".
|
|
8310
|
|
8311 Alternatively, using a regular expression for @:
|
|
8312
|
|
8313 /* psm_mas AUTO_TEMPLATE \"_\\([a-z]+\\)\" (
|
|
8314 .ptl_mapvalidx (@_ptl_mapvalid),
|
|
8315 .ptl_mapvalidp1x (ptl_mapvalid_@),
|
|
8316 );
|
|
8317 */
|
|
8318 psm_mas ms2_FOO (/*AUTOINST*/);
|
|
8319 psm_mas ms2_BAR (/*AUTOINST*/);
|
|
8320
|
|
8321 Typing \\[verilog-auto] will make this into:
|
|
8322
|
|
8323 psm_mas ms2_FOO (/*AUTOINST*/
|
|
8324 // Outputs
|
|
8325 .ptl_mapvalidx (FOO_ptl_mapvalid),
|
|
8326 .ptl_mapvalidp1x (ptl_mapvalid_FOO));
|
|
8327 psm_mas ms2_BAR (/*AUTOINST*/
|
|
8328 // Outputs
|
|
8329 .ptl_mapvalidx (BAR_ptl_mapvalid),
|
|
8330 .ptl_mapvalidp1x (ptl_mapvalid_BAR));
|
|
8331
|
|
8332
|
|
8333 Regexp Templates:
|
|
8334
|
|
8335 A template entry of the form
|
|
8336
|
|
8337 .pci_req\\([0-9]+\\)_l (pci_req_jtag_[\\1]),
|
|
8338
|
|
8339 will apply a Emacs style regular expression search for any port beginning
|
|
8340 in pci_req followed by numbers and ending in _l and connecting that to
|
|
8341 the pci_req_jtag_[] net, with the bus subscript coming from what matches
|
|
8342 inside the first set of \\( \\). Thus pci_req2_l becomes pci_req_jtag_[2].
|
|
8343
|
|
8344 Since \\([0-9]+\\) is so common and ugly to read, a @ in the port name
|
|
8345 does the same thing. (Note a @ in the connection/replacement text is
|
|
8346 completely different -- still use \\1 there!) Thus this is the same as
|
|
8347 the above template:
|
|
8348
|
|
8349 .pci_req@_l (pci_req_jtag_[\\1]),
|
|
8350
|
|
8351 Here's another example to remove the _l, useful when naming conventions
|
|
8352 specify _ alone to mean active low. Note the use of [] to keep the bus
|
|
8353 subscript:
|
|
8354
|
|
8355 .\\(.*\\)_l (\\1_[]),
|
|
8356
|
|
8357 Lisp Templates:
|
|
8358
|
|
8359 First any regular expression template is expanded.
|
|
8360
|
|
8361 If the syntax @\"( ... )\" is found in a connection, the expression in
|
|
8362 quotes will be evaluated as a Lisp expression, with @ replaced by the
|
|
8363 instantiation number. The MAPVALIDP1X example above would put @+1 modulo
|
|
8364 4 into the brackets. Quote all double-quotes inside the expression with
|
|
8365 a leading backslash (\\\"). There are special variables defined that are
|
|
8366 useful in these Lisp functions:
|
|
8367
|
|
8368 vl-name Name portion of the input/output port
|
|
8369 vl-bits Bus bits portion of the input/output port ('[2:0]')
|
|
8370 vl-width Width of the input/output port ('3' for [2:0])
|
|
8371 May be a (...) expression if bits isn't a constant.
|
|
8372 vl-dir Direction of the pin input/output/inout.
|
|
8373 vl-cell-type Module name/type of the cell ('psm_mas')
|
|
8374 vl-cell-name Instance name of the cell ('ms2m')
|
|
8375
|
|
8376 Normal Lisp variables may be used in expressions. See
|
|
8377 `verilog-read-defines' which can set vh-{definename} variables for use
|
|
8378 here. Also, any comments of the form:
|
|
8379
|
|
8380 /*AUTO_LISP(setq foo 1)*/
|
|
8381
|
|
8382 will evaluate any Lisp expression inside the parenthesis between the
|
|
8383 beginning of the buffer and the point of the AUTOINST. This allows
|
|
8384 functions to be defined or variables to be changed between instantiations.
|
|
8385
|
|
8386 Note that when using lisp expressions errors may occur when @ is not a
|
|
8387 number, you may need to use the standard Emacs Lisp functions
|
|
8388 `number-to-string' and `string-to-number'.
|
|
8389
|
|
8390 After the evaluation is completed, @ substitution and [] substitution
|
|
8391 occur."
|
|
8392 (save-excursion
|
|
8393 ;; Find beginning
|
|
8394 (let* ((pt (point))
|
|
8395 (for-star (save-excursion (backward-char 2) (looking-at "\\.\\*")))
|
|
8396 (indent-pt (save-excursion (verilog-backward-open-paren)
|
|
8397 (1+ (current-column))))
|
|
8398 (verilog-auto-inst-column (max verilog-auto-inst-column
|
|
8399 (+ 16 (* 8 (/ (+ indent-pt 7) 8)))))
|
|
8400 (modi (verilog-modi-current))
|
|
8401 (vector-skip-list (unless verilog-auto-inst-vector
|
|
8402 (verilog-modi-get-signals modi)))
|
|
8403 submod submodi inst skip-pins tpl-list tpl-num did-first)
|
|
8404 ;; Find module name that is instantiated
|
|
8405 (setq submod (verilog-read-inst-module)
|
|
8406 inst (verilog-read-inst-name)
|
|
8407 vl-cell-type submod
|
|
8408 vl-cell-name inst
|
|
8409 skip-pins (aref (verilog-read-inst-pins) 0))
|
|
8410
|
|
8411 ;; Parse any AUTO_LISP() before here
|
|
8412 (verilog-read-auto-lisp (point-min) pt)
|
|
8413
|
|
8414 ;; Lookup position, etc of submodule
|
|
8415 ;; Note this may raise an error
|
|
8416 (when (setq submodi (verilog-modi-lookup submod t))
|
|
8417 ;; If there's a number in the instantiation, it may be a argument to the
|
|
8418 ;; automatic variable instantiation program.
|
|
8419 (let* ((tpl-info (verilog-read-auto-template submod))
|
|
8420 (tpl-regexp (aref tpl-info 0)))
|
|
8421 (setq tpl-num (if (string-match tpl-regexp inst)
|
|
8422 (match-string 1 inst)
|
|
8423 "")
|
|
8424 tpl-list (aref tpl-info 1)))
|
|
8425 ;; Find submodule's signals and dump
|
|
8426 (let ((sig-list (verilog-signals-not-in
|
|
8427 (verilog-modi-get-outputs submodi)
|
|
8428 skip-pins))
|
|
8429 (vl-dir "output"))
|
|
8430 (when sig-list
|
|
8431 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
|
|
8432 (indent-to indent-pt)
|
|
8433 (insert "// Outputs\n") ;; Note these are searched for in verilog-read-sub-decls
|
|
8434 (mapcar (function (lambda (port)
|
|
8435 (verilog-auto-inst-port port indent-pt tpl-list tpl-num for-star)))
|
|
8436 sig-list)))
|
|
8437 (let ((sig-list (verilog-signals-not-in
|
|
8438 (verilog-modi-get-inouts submodi)
|
|
8439 skip-pins))
|
|
8440 (vl-dir "inout"))
|
|
8441 (when sig-list
|
|
8442 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
|
|
8443 (indent-to indent-pt)
|
|
8444 (insert "// Inouts\n")
|
|
8445 (mapcar (function (lambda (port)
|
|
8446 (verilog-auto-inst-port port indent-pt tpl-list tpl-num for-star)))
|
|
8447 sig-list)))
|
|
8448 (let ((sig-list (verilog-signals-not-in
|
|
8449 (verilog-modi-get-inputs submodi)
|
|
8450 skip-pins))
|
|
8451 (vl-dir "input"))
|
|
8452 (when sig-list
|
|
8453 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
|
|
8454 (indent-to indent-pt)
|
|
8455 (insert "// Inputs\n")
|
|
8456 (mapcar (function (lambda (port)
|
|
8457 (verilog-auto-inst-port port indent-pt tpl-list tpl-num for-star)))
|
|
8458 sig-list)))
|
|
8459 ;; Kill extra semi
|
|
8460 (save-excursion
|
|
8461 (cond (did-first
|
|
8462 (re-search-backward "," pt t)
|
|
8463 (delete-char 1)
|
|
8464 (insert ");")
|
|
8465 (search-forward "\n") ;; Added by inst-port
|
|
8466 (delete-backward-char 1)
|
|
8467 (if (search-forward ")" nil t) ;; From user, moved up a line
|
|
8468 (delete-backward-char 1))
|
|
8469 (if (search-forward ";" nil t) ;; Don't error if user had syntax error and forgot it
|
|
8470 (delete-backward-char 1))
|
|
8471 )))
|
|
8472 ))))
|
|
8473
|
|
8474 (defun verilog-auto-inst-param ()
|
|
8475 "Expand AUTOINSTPARAM statements, as part of \\[verilog-auto].
|
|
8476 Replace the parameter connections to an instantiation with ones
|
|
8477 automatically derived from the module header of the instantiated netlist.
|
|
8478
|
|
8479 See \\[verilog-auto-inst] for limitations, and templates to customize the
|
|
8480 output.
|
|
8481
|
|
8482 For example, first take the submodule inst.v:
|
|
8483
|
|
8484 module inst (o,i)
|
|
8485 parameter PAR;
|
|
8486 endmodule
|
|
8487
|
|
8488 This is then used in a upper level module:
|
|
8489
|
|
8490 module ex_inst (o,i)
|
|
8491 parameter PAR;
|
|
8492 inst #(/*AUTOINSTPARAM*/)
|
|
8493 inst (/*AUTOINST*/);
|
|
8494 endmodule
|
|
8495
|
|
8496 Typing \\[verilog-auto] will make this into:
|
|
8497
|
|
8498 module ex_inst (o,i)
|
|
8499 output o;
|
|
8500 input i;
|
|
8501 inst (/*AUTOINSTPARAM*/
|
|
8502 // Parameters
|
|
8503 .PAR (PAR));
|
|
8504 inst (/*AUTOINST*/);
|
|
8505 endmodule
|
|
8506
|
|
8507 Where the list of parameter connections come from the inst module.
|
|
8508
|
|
8509 Templates:
|
|
8510
|
|
8511 You can customize the parameter connections using AUTO_TEMPLATEs,
|
|
8512 just as you would with \\[verilog-auto-inst]."
|
|
8513 (save-excursion
|
|
8514 ;; Find beginning
|
|
8515 (let* ((pt (point))
|
|
8516 (indent-pt (save-excursion (verilog-backward-open-paren)
|
|
8517 (1+ (current-column))))
|
|
8518 (verilog-auto-inst-column (max verilog-auto-inst-column
|
|
8519 (+ 16 (* 8 (/ (+ indent-pt 7) 8)))))
|
|
8520 (modi (verilog-modi-current))
|
|
8521 (vector-skip-list (unless verilog-auto-inst-vector
|
|
8522 (verilog-modi-get-signals modi)))
|
|
8523 submod submodi inst skip-pins tpl-list tpl-num did-first)
|
|
8524 ;; Find module name that is instantiated
|
|
8525 (setq submod (save-excursion
|
|
8526 ;; Get to the point where AUTOINST normally is to read the module
|
|
8527 (verilog-re-search-forward-quick "[(;]" nil nil)
|
|
8528 (verilog-read-inst-module))
|
|
8529 inst (save-excursion
|
|
8530 ;; Get to the point where AUTOINST normally is to read the module
|
|
8531 (verilog-re-search-forward-quick "[(;]" nil nil)
|
|
8532 (verilog-read-inst-name))
|
|
8533 vl-cell-type submod
|
|
8534 vl-cell-name inst
|
|
8535 skip-pins (aref (verilog-read-inst-pins) 0))
|
|
8536
|
|
8537 ;; Parse any AUTO_LISP() before here
|
|
8538 (verilog-read-auto-lisp (point-min) pt)
|
|
8539
|
|
8540 ;; Lookup position, etc of submodule
|
|
8541 ;; Note this may raise an error
|
|
8542 (when (setq submodi (verilog-modi-lookup submod t))
|
|
8543 ;; If there's a number in the instantiation, it may be a argument to the
|
|
8544 ;; automatic variable instantiation program.
|
|
8545 (let* ((tpl-info (verilog-read-auto-template submod))
|
|
8546 (tpl-regexp (aref tpl-info 0)))
|
|
8547 (setq tpl-num (if (string-match tpl-regexp inst)
|
|
8548 (match-string 1 inst)
|
|
8549 "")
|
|
8550 tpl-list (aref tpl-info 1)))
|
|
8551 ;; Find submodule's signals and dump
|
|
8552 (let ((sig-list (verilog-signals-not-in
|
|
8553 (verilog-modi-get-gparams submodi)
|
|
8554 skip-pins))
|
|
8555 (vl-dir "parameter"))
|
|
8556 (when sig-list
|
|
8557 (when (not did-first) (verilog-auto-inst-first) (setq did-first t))
|
|
8558 (indent-to indent-pt)
|
|
8559 (insert "// Parameters\n") ;; Note these are searched for in verilog-read-sub-decls
|
|
8560 (mapcar (function (lambda (port)
|
|
8561 (verilog-auto-inst-port port indent-pt tpl-list tpl-num nil)))
|
|
8562 sig-list)))
|
|
8563 ;; Kill extra semi
|
|
8564 (save-excursion
|
|
8565 (cond (did-first
|
|
8566 (re-search-backward "," pt t)
|
|
8567 (delete-char 1)
|
|
8568 (insert ")")
|
|
8569 (search-forward "\n") ;; Added by inst-port
|
|
8570 (delete-backward-char 1)
|
|
8571 (if (search-forward ")" nil t) ;; From user, moved up a line
|
|
8572 (delete-backward-char 1))
|
|
8573 )))
|
|
8574 ))))
|
|
8575
|
|
8576 (defun verilog-auto-reg ()
|
|
8577 "Expand AUTOREG statements, as part of \\[verilog-auto].
|
|
8578 Make reg statements for any output that isn't already declared,
|
|
8579 and isn't a wire output from a block.
|
|
8580
|
|
8581 Limitations:
|
|
8582 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
|
|
8583
|
|
8584 This does NOT work on memories, declare those yourself.
|
|
8585
|
|
8586 An example:
|
|
8587
|
|
8588 module ex_reg (o,i)
|
|
8589 output o;
|
|
8590 input i;
|
|
8591 /*AUTOREG*/
|
|
8592 always o = i;
|
|
8593 endmodule
|
|
8594
|
|
8595 Typing \\[verilog-auto] will make this into:
|
|
8596
|
|
8597 module ex_reg (o,i)
|
|
8598 output o;
|
|
8599 input i;
|
|
8600 /*AUTOREG*/
|
|
8601 // Beginning of automatic regs (for this module's undeclared outputs)
|
|
8602 reg o;
|
|
8603 // End of automatics
|
|
8604 always o = i;
|
|
8605 endmodule"
|
|
8606 (save-excursion
|
|
8607 ;; Point must be at insertion point.
|
|
8608 (let* ((indent-pt (current-indentation))
|
|
8609 (modi (verilog-modi-current))
|
|
8610 (sig-list (verilog-signals-not-in
|
|
8611 (verilog-modi-get-outputs modi)
|
|
8612 (append (verilog-modi-get-wires modi)
|
|
8613 (verilog-modi-get-regs modi)
|
|
8614 (verilog-modi-get-assigns modi)
|
|
8615 (verilog-modi-get-consts modi)
|
|
8616 (verilog-modi-get-gparams modi)
|
|
8617 (verilog-modi-get-sub-outputs modi)
|
|
8618 (verilog-modi-get-sub-inouts modi)
|
|
8619 ))))
|
|
8620 (forward-line 1)
|
|
8621 (when sig-list
|
|
8622 (verilog-insert-indent "// Beginning of automatic regs (for this module's undeclared outputs)\n")
|
|
8623 (verilog-insert-definition sig-list "reg" indent-pt nil)
|
|
8624 (verilog-modi-cache-add-regs modi sig-list)
|
|
8625 (verilog-insert-indent "// End of automatics\n"))
|
|
8626 )))
|
|
8627
|
|
8628 (defun verilog-auto-reg-input ()
|
|
8629 "Expand AUTOREGINPUT statements, as part of \\[verilog-auto].
|
|
8630 Make reg statements instantiation inputs that aren't already declared.
|
|
8631 This is useful for making a top level shell for testing the module that is
|
|
8632 to be instantiated.
|
|
8633
|
|
8634 Limitations:
|
|
8635 This ONLY detects inputs of AUTOINSTants (see `verilog-read-sub-decls').
|
|
8636
|
|
8637 This does NOT work on memories, declare those yourself.
|
|
8638
|
|
8639 An example (see `verilog-auto-inst' for what else is going on here):
|
|
8640
|
|
8641 module ex_reg_input (o,i)
|
|
8642 output o;
|
|
8643 input i;
|
|
8644 /*AUTOREGINPUT*/
|
|
8645 inst inst (/*AUTOINST*/);
|
|
8646 endmodule
|
|
8647
|
|
8648 Typing \\[verilog-auto] will make this into:
|
|
8649
|
|
8650 module ex_reg_input (o,i)
|
|
8651 output o;
|
|
8652 input i;
|
|
8653 /*AUTOREGINPUT*/
|
|
8654 // Beginning of automatic reg inputs (for undeclared ...
|
|
8655 reg [31:0] iv; // From inst of inst.v
|
|
8656 // End of automatics
|
|
8657 inst inst (/*AUTOINST*/
|
|
8658 // Outputs
|
|
8659 .o (o[31:0]),
|
|
8660 // Inputs
|
|
8661 .iv (iv));
|
|
8662 endmodule"
|
|
8663 (save-excursion
|
|
8664 ;; Point must be at insertion point.
|
|
8665 (let* ((indent-pt (current-indentation))
|
|
8666 (modi (verilog-modi-current))
|
|
8667 (sig-list (verilog-signals-combine-bus
|
|
8668 (verilog-signals-not-in
|
|
8669 (append (verilog-modi-get-sub-inputs modi)
|
|
8670 (verilog-modi-get-sub-inouts modi))
|
|
8671 (verilog-modi-get-signals modi)
|
|
8672 ))))
|
|
8673 (forward-line 1)
|
|
8674 (when sig-list
|
|
8675 (verilog-insert-indent "// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)\n")
|
|
8676 (verilog-insert-definition sig-list "reg" indent-pt nil)
|
|
8677 (verilog-modi-cache-add-regs modi sig-list)
|
|
8678 (verilog-insert-indent "// End of automatics\n"))
|
|
8679 )))
|
|
8680
|
|
8681 (defun verilog-auto-wire ()
|
|
8682 "Expand AUTOWIRE statements, as part of \\[verilog-auto].
|
|
8683 Make wire statements for instantiations outputs that aren't
|
|
8684 already declared.
|
|
8685
|
|
8686 Limitations:
|
|
8687 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls'),
|
|
8688 and all busses must have widths, such as those from AUTOINST, or using []
|
|
8689 in AUTO_TEMPLATEs.
|
|
8690
|
|
8691 This does NOT work on memories or SystemVerilog .name connections,
|
|
8692 declare those yourself.
|
|
8693
|
|
8694 Verilog-mode will add \"Couldn't Merge\" comments to signals it cannot
|
|
8695 determine how to bus together. This occurs when you have ports with
|
|
8696 non-numeric or non-sequential bus subscripts. If Verilog-Mode
|
|
8697 mis-guessed, you'll have to declare them yourself.
|
|
8698
|
|
8699 An example (see `verilog-auto-inst' for what else is going on here):
|
|
8700
|
|
8701 module ex_wire (o,i)
|
|
8702 output o;
|
|
8703 input i;
|
|
8704 /*AUTOWIRE*/
|
|
8705 inst inst (/*AUTOINST*/);
|
|
8706 endmodule
|
|
8707
|
|
8708 Typing \\[verilog-auto] will make this into:
|
|
8709
|
|
8710 module ex_wire (o,i)
|
|
8711 output o;
|
|
8712 input i;
|
|
8713 /*AUTOWIRE*/
|
|
8714 // Beginning of automatic wires
|
|
8715 wire [31:0] ov; // From inst of inst.v
|
|
8716 // End of automatics
|
|
8717 inst inst (/*AUTOINST*/
|
|
8718 // Outputs
|
|
8719 .ov (ov[31:0]),
|
|
8720 // Inputs
|
|
8721 .i (i));
|
|
8722 wire o = | ov;
|
|
8723 endmodule"
|
|
8724 (save-excursion
|
|
8725 ;; Point must be at insertion point.
|
|
8726 (let* ((indent-pt (current-indentation))
|
|
8727 (modi (verilog-modi-current))
|
|
8728 (sig-list (verilog-signals-combine-bus
|
|
8729 (verilog-signals-not-in
|
|
8730 (append (verilog-modi-get-sub-outputs modi)
|
|
8731 (verilog-modi-get-sub-inouts modi))
|
|
8732 (verilog-modi-get-signals modi)
|
|
8733 ))))
|
|
8734 (forward-line 1)
|
|
8735 (when sig-list
|
|
8736 (verilog-insert-indent "// Beginning of automatic wires (for undeclared instantiated-module outputs)\n")
|
|
8737 (verilog-insert-definition sig-list "wire" indent-pt nil)
|
|
8738 (verilog-modi-cache-add-wires modi sig-list)
|
|
8739 (verilog-insert-indent "// End of automatics\n")
|
|
8740 (when nil ;; Too slow on huge modules, plus makes everyone's module change
|
|
8741 (beginning-of-line)
|
|
8742 (setq pnt (point))
|
|
8743 (verilog-pretty-declarations)
|
|
8744 (goto-char pnt)
|
|
8745 (verilog-pretty-expr "//")))
|
|
8746 )))
|
|
8747
|
|
8748 (defun verilog-auto-output ()
|
|
8749 "Expand AUTOOUTPUT statements, as part of \\[verilog-auto].
|
|
8750 Make output statements for any output signal from an /*AUTOINST*/ that
|
|
8751 isn't a input to another AUTOINST. This is useful for modules which
|
|
8752 only instantiate other modules.
|
|
8753
|
|
8754 Limitations:
|
|
8755 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
|
|
8756
|
|
8757 If placed inside the parenthesis of a module declaration, it creates
|
|
8758 Verilog 2001 style, else uses Verilog 1995 style.
|
|
8759
|
|
8760 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
|
|
8761 instantiation, all bets are off. (For example due to a AUTO_TEMPLATE).
|
|
8762
|
|
8763 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
|
|
8764
|
|
8765 Signals matching `verilog-auto-output-ignore-regexp' are not included.
|
|
8766
|
|
8767 An example (see `verilog-auto-inst' for what else is going on here):
|
|
8768
|
|
8769 module ex_output (ov,i)
|
|
8770 input i;
|
|
8771 /*AUTOOUTPUT*/
|
|
8772 inst inst (/*AUTOINST*/);
|
|
8773 endmodule
|
|
8774
|
|
8775 Typing \\[verilog-auto] will make this into:
|
|
8776
|
|
8777 module ex_output (ov,i)
|
|
8778 input i;
|
|
8779 /*AUTOOUTPUT*/
|
|
8780 // Beginning of automatic outputs (from unused autoinst outputs)
|
|
8781 output [31:0] ov; // From inst of inst.v
|
|
8782 // End of automatics
|
|
8783 inst inst (/*AUTOINST*/
|
|
8784 // Outputs
|
|
8785 .ov (ov[31:0]),
|
|
8786 // Inputs
|
|
8787 .i (i));
|
|
8788 endmodule"
|
|
8789 (save-excursion
|
|
8790 ;; Point must be at insertion point.
|
|
8791 (let* ((indent-pt (current-indentation))
|
|
8792 (v2k (verilog-in-paren))
|
|
8793 (modi (verilog-modi-current))
|
|
8794 (sig-list (verilog-signals-not-in
|
|
8795 (verilog-modi-get-sub-outputs modi)
|
|
8796 (append (verilog-modi-get-outputs modi)
|
|
8797 (verilog-modi-get-inouts modi)
|
|
8798 (verilog-modi-get-sub-inputs modi)
|
|
8799 (verilog-modi-get-sub-inouts modi)
|
|
8800 ))))
|
|
8801 (setq sig-list (verilog-signals-not-matching-regexp
|
|
8802 sig-list verilog-auto-output-ignore-regexp))
|
|
8803 (forward-line 1)
|
|
8804 (when v2k (verilog-repair-open-comma))
|
|
8805 (when sig-list
|
|
8806 (verilog-insert-indent "// Beginning of automatic outputs (from unused autoinst outputs)\n")
|
|
8807 (verilog-insert-definition sig-list "output" indent-pt v2k)
|
|
8808 (verilog-modi-cache-add-outputs modi sig-list)
|
|
8809 (verilog-insert-indent "// End of automatics\n"))
|
|
8810 (when v2k (verilog-repair-close-comma))
|
|
8811 )))
|
|
8812
|
|
8813 (defun verilog-auto-output-every ()
|
|
8814 "Expand AUTOOUTPUTEVERY statements, as part of \\[verilog-auto].
|
|
8815 Make output statements for any signals that aren't primary inputs or
|
|
8816 outputs already. This makes every signal in the design a output. This is
|
|
8817 useful to get Synopsys to preserve every signal in the design, since it
|
|
8818 won't optimize away the outputs.
|
|
8819
|
|
8820 An example:
|
|
8821
|
|
8822 module ex_output_every (o,i,tempa,tempb)
|
|
8823 output o;
|
|
8824 input i;
|
|
8825 /*AUTOOUTPUTEVERY*/
|
|
8826 wire tempa = i;
|
|
8827 wire tempb = tempa;
|
|
8828 wire o = tempb;
|
|
8829 endmodule
|
|
8830
|
|
8831 Typing \\[verilog-auto] will make this into:
|
|
8832
|
|
8833 module ex_output_every (o,i,tempa,tempb)
|
|
8834 output o;
|
|
8835 input i;
|
|
8836 /*AUTOOUTPUTEVERY*/
|
|
8837 // Beginning of automatic outputs (every signal)
|
|
8838 output tempb;
|
|
8839 output tempa;
|
|
8840 // End of automatics
|
|
8841 wire tempa = i;
|
|
8842 wire tempb = tempa;
|
|
8843 wire o = tempb;
|
|
8844 endmodule"
|
|
8845 (save-excursion
|
|
8846 ;;Point must be at insertion point
|
|
8847 (let* ((indent-pt (current-indentation))
|
|
8848 (v2k (verilog-in-paren))
|
|
8849 (modi (verilog-modi-current))
|
|
8850 (sig-list (verilog-signals-combine-bus
|
|
8851 (verilog-signals-not-in
|
|
8852 (verilog-modi-get-signals modi)
|
|
8853 (verilog-modi-get-ports modi)
|
|
8854 ))))
|
|
8855 (forward-line 1)
|
|
8856 (when v2k (verilog-repair-open-comma))
|
|
8857 (when sig-list
|
|
8858 (verilog-insert-indent "// Beginning of automatic outputs (every signal)\n")
|
|
8859 (verilog-insert-definition sig-list "output" indent-pt v2k)
|
|
8860 (verilog-modi-cache-add-outputs modi sig-list)
|
|
8861 (verilog-insert-indent "// End of automatics\n"))
|
|
8862 (when v2k (verilog-repair-close-comma))
|
|
8863 )))
|
|
8864
|
|
8865 (defun verilog-auto-input ()
|
|
8866 "Expand AUTOINPUT statements, as part of \\[verilog-auto].
|
|
8867 Make input statements for any input signal into an /*AUTOINST*/ that
|
|
8868 isn't declared elsewhere inside the module. This is useful for modules which
|
|
8869 only instantiate other modules.
|
|
8870
|
|
8871 Limitations:
|
|
8872 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
|
|
8873
|
|
8874 If placed inside the parenthesis of a module declaration, it creates
|
|
8875 Verilog 2001 style, else uses Verilog 1995 style.
|
|
8876
|
|
8877 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
|
|
8878 instantiation, all bets are off. (For example due to a AUTO_TEMPLATE).
|
|
8879
|
|
8880 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
|
|
8881
|
|
8882 Signals matching `verilog-auto-input-ignore-regexp' are not included.
|
|
8883
|
|
8884 An example (see `verilog-auto-inst' for what else is going on here):
|
|
8885
|
|
8886 module ex_input (ov,i)
|
|
8887 output [31:0] ov;
|
|
8888 /*AUTOINPUT*/
|
|
8889 inst inst (/*AUTOINST*/);
|
|
8890 endmodule
|
|
8891
|
|
8892 Typing \\[verilog-auto] will make this into:
|
|
8893
|
|
8894 module ex_input (ov,i)
|
|
8895 output [31:0] ov;
|
|
8896 /*AUTOINPUT*/
|
|
8897 // Beginning of automatic inputs (from unused autoinst inputs)
|
|
8898 input i; // From inst of inst.v
|
|
8899 // End of automatics
|
|
8900 inst inst (/*AUTOINST*/
|
|
8901 // Outputs
|
|
8902 .ov (ov[31:0]),
|
|
8903 // Inputs
|
|
8904 .i (i));
|
|
8905 endmodule"
|
|
8906 (save-excursion
|
|
8907 (let* ((indent-pt (current-indentation))
|
|
8908 (v2k (verilog-in-paren))
|
|
8909 (modi (verilog-modi-current))
|
|
8910 (sig-list (verilog-signals-not-in
|
|
8911 (verilog-modi-get-sub-inputs modi)
|
|
8912 (append (verilog-modi-get-inputs modi)
|
|
8913 (verilog-modi-get-inouts modi)
|
|
8914 (verilog-modi-get-wires modi)
|
|
8915 (verilog-modi-get-regs modi)
|
|
8916 (verilog-modi-get-consts modi)
|
|
8917 (verilog-modi-get-gparams modi)
|
|
8918 (verilog-modi-get-sub-outputs modi)
|
|
8919 (verilog-modi-get-sub-inouts modi)
|
|
8920 ))))
|
|
8921 (setq sig-list (verilog-signals-not-matching-regexp
|
|
8922 sig-list verilog-auto-input-ignore-regexp))
|
|
8923 (forward-line 1)
|
|
8924 (when v2k (verilog-repair-open-comma))
|
|
8925 (when sig-list
|
|
8926 (verilog-insert-indent "// Beginning of automatic inputs (from unused autoinst inputs)\n")
|
|
8927 (verilog-insert-definition sig-list "input" indent-pt v2k)
|
|
8928 (verilog-modi-cache-add-inputs modi sig-list)
|
|
8929 (verilog-insert-indent "// End of automatics\n"))
|
|
8930 (when v2k (verilog-repair-close-comma))
|
|
8931 )))
|
|
8932
|
|
8933 (defun verilog-auto-inout ()
|
|
8934 "Expand AUTOINOUT statements, as part of \\[verilog-auto].
|
|
8935 Make inout statements for any inout signal in an /*AUTOINST*/ that
|
|
8936 isn't declared elsewhere inside the module.
|
|
8937
|
|
8938 Limitations:
|
|
8939 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls').
|
|
8940
|
|
8941 If placed inside the parenthesis of a module declaration, it creates
|
|
8942 Verilog 2001 style, else uses Verilog 1995 style.
|
|
8943
|
|
8944 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's
|
|
8945 instantiation, all bets are off. (For example due to a AUTO_TEMPLATE).
|
|
8946
|
|
8947 Typedefs must match `verilog-typedef-regexp', which is disabled by default.
|
|
8948
|
|
8949 Signals matching `verilog-auto-inout-ignore-regexp' are not included.
|
|
8950
|
|
8951 An example (see `verilog-auto-inst' for what else is going on here):
|
|
8952
|
|
8953 module ex_inout (ov,i)
|
|
8954 input i;
|
|
8955 /*AUTOINOUT*/
|
|
8956 inst inst (/*AUTOINST*/);
|
|
8957 endmodule
|
|
8958
|
|
8959 Typing \\[verilog-auto] will make this into:
|
|
8960
|
|
8961 module ex_inout (ov,i)
|
|
8962 input i;
|
|
8963 /*AUTOINOUT*/
|
|
8964 // Beginning of automatic inouts (from unused autoinst inouts)
|
|
8965 inout [31:0] ov; // From inst of inst.v
|
|
8966 // End of automatics
|
|
8967 inst inst (/*AUTOINST*/
|
|
8968 // Inouts
|
|
8969 .ov (ov[31:0]),
|
|
8970 // Inputs
|
|
8971 .i (i));
|
|
8972 endmodule"
|
|
8973 (save-excursion
|
|
8974 ;; Point must be at insertion point.
|
|
8975 (let* ((indent-pt (current-indentation))
|
|
8976 (v2k (verilog-in-paren))
|
|
8977 (modi (verilog-modi-current))
|
|
8978 (sig-list (verilog-signals-not-in
|
|
8979 (verilog-modi-get-sub-inouts modi)
|
|
8980 (append (verilog-modi-get-outputs modi)
|
|
8981 (verilog-modi-get-inouts modi)
|
|
8982 (verilog-modi-get-inputs modi)
|
|
8983 (verilog-modi-get-sub-inputs modi)
|
|
8984 (verilog-modi-get-sub-outputs modi)
|
|
8985 ))))
|
|
8986 (setq sig-list (verilog-signals-not-matching-regexp
|
|
8987 sig-list verilog-auto-inout-ignore-regexp))
|
|
8988 (forward-line 1)
|
|
8989 (when v2k (verilog-repair-open-comma))
|
|
8990 (when sig-list
|
|
8991 (verilog-insert-indent "// Beginning of automatic inouts (from unused autoinst inouts)\n")
|
|
8992 (verilog-insert-definition sig-list "inout" indent-pt v2k)
|
|
8993 (verilog-modi-cache-add-inouts modi sig-list)
|
|
8994 (verilog-insert-indent "// End of automatics\n"))
|
|
8995 (when v2k (verilog-repair-close-comma))
|
|
8996 )))
|
|
8997
|
|
8998 (defun verilog-auto-inout-module ()
|
|
8999 "Expand AUTOINOUTMODULE statements, as part of \\[verilog-auto].
|
|
9000 Take input/output/inout statements from the specified module and insert
|
|
9001 into the current module. This is useful for making null templates and
|
|
9002 shell modules which need to have identical I/O with another module. Any
|
|
9003 I/O which are already defined in this module will not be redefined.
|
|
9004
|
|
9005 Limitations:
|
|
9006 If placed inside the parenthesis of a module declaration, it creates
|
|
9007 Verilog 2001 style, else uses Verilog 1995 style.
|
|
9008
|
|
9009 Concatenation and outputting partial busses is not supported.
|
|
9010
|
|
9011 Module names must be resolvable to filenames. See `verilog-auto-inst'.
|
|
9012
|
|
9013 Signals are not inserted in the same order as in the original module,
|
|
9014 though they will appear to be in the same order to a AUTOINST
|
|
9015 instantiating either module.
|
|
9016
|
|
9017 An example:
|
|
9018
|
|
9019 module ex_shell (/*AUTOARG*/)
|
|
9020 /*AUTOINOUTMODULE(\"ex_main\")*/
|
|
9021 endmodule
|
|
9022
|
|
9023 module ex_main (i,o,io)
|
|
9024 input i;
|
|
9025 output o;
|
|
9026 inout io;
|
|
9027 endmodule
|
|
9028
|
|
9029 Typing \\[verilog-auto] will make this into:
|
|
9030
|
|
9031 module ex_shell (/*AUTOARG*/i,o,io)
|
|
9032 /*AUTOINOUTMODULE(\"ex_main\")*/
|
|
9033 // Beginning of automatic in/out/inouts (from specific module)
|
|
9034 input i;
|
|
9035 output o;
|
|
9036 inout io;
|
|
9037 // End of automatics
|
|
9038 endmodule"
|
|
9039 (save-excursion
|
|
9040 (let* ((submod (car (verilog-read-auto-params 1))) submodi)
|
|
9041 ;; Lookup position, etc of co-module
|
|
9042 ;; Note this may raise an error
|
|
9043 (when (setq submodi (verilog-modi-lookup submod t))
|
|
9044 (let* ((indent-pt (current-indentation))
|
|
9045 (v2k (verilog-in-paren))
|
|
9046 (modi (verilog-modi-current))
|
|
9047 (sig-list-i (verilog-signals-not-in
|
|
9048 (verilog-modi-get-inputs submodi)
|
|
9049 (append (verilog-modi-get-inputs modi))))
|
|
9050 (sig-list-o (verilog-signals-not-in
|
|
9051 (verilog-modi-get-outputs submodi)
|
|
9052 (append (verilog-modi-get-outputs modi))))
|
|
9053 (sig-list-io (verilog-signals-not-in
|
|
9054 (verilog-modi-get-inouts submodi)
|
|
9055 (append (verilog-modi-get-inouts modi)))))
|
|
9056 (forward-line 1)
|
|
9057 (when v2k (verilog-repair-open-comma))
|
|
9058 (when (or sig-list-i sig-list-o sig-list-io)
|
|
9059 (verilog-insert-indent "// Beginning of automatic in/out/inouts (from specific module)\n")
|
|
9060 ;; Don't sort them so a upper AUTOINST will match the main module
|
|
9061 (verilog-insert-definition sig-list-o "output" indent-pt v2k t)
|
|
9062 (verilog-insert-definition sig-list-io "inout" indent-pt v2k t)
|
|
9063 (verilog-insert-definition sig-list-i "input" indent-pt v2k t)
|
|
9064 (verilog-modi-cache-add-inputs modi sig-list-i)
|
|
9065 (verilog-modi-cache-add-outputs modi sig-list-o)
|
|
9066 (verilog-modi-cache-add-inouts modi sig-list-io)
|
|
9067 (verilog-insert-indent "// End of automatics\n"))
|
|
9068 (when v2k (verilog-repair-close-comma))
|
|
9069 )))))
|
|
9070
|
|
9071 (defun verilog-auto-sense-sigs (modi presense-sigs)
|
|
9072 "Return list of signals for current AUTOSENSE block."
|
|
9073 (let* ((sigss (verilog-read-always-signals))
|
|
9074 (sig-list (verilog-signals-not-params
|
|
9075 (verilog-signals-not-in (verilog-alw-get-inputs sigss)
|
|
9076 (append (and (not verilog-auto-sense-include-inputs)
|
|
9077 (verilog-alw-get-outputs sigss))
|
|
9078 (verilog-modi-get-consts modi)
|
|
9079 (verilog-modi-get-gparams modi)
|
|
9080 presense-sigs)))))
|
|
9081 sig-list))
|
|
9082
|
|
9083 (defun verilog-auto-sense ()
|
|
9084 "Expand AUTOSENSE statements, as part of \\[verilog-auto].
|
|
9085 Replace the always (/*AUTOSENSE*/) sensitivity list (/*AS*/ for short)
|
|
9086 with one automatically derived from all inputs declared in the always
|
|
9087 statement. Signals that are generated within the same always block are NOT
|
|
9088 placed into the sensitivity list (see `verilog-auto-sense-include-inputs').
|
|
9089 Long lines are split based on the `fill-column', see \\[set-fill-column].
|
|
9090
|
|
9091 Limitations:
|
|
9092 Verilog does not allow memories (multidimensional arrays) in sensitivity
|
|
9093 lists. AUTOSENSE will thus exclude them, and add a /*memory or*/ comment.
|
|
9094
|
|
9095 Constant signals:
|
|
9096 AUTOSENSE cannot always determine if a `define is a constant or a signal
|
|
9097 (it could be in a include file for example). If a `define or other signal
|
|
9098 is put into the AUTOSENSE list and is not desired, use the AUTO_CONSTANT
|
|
9099 declaration anywhere in the module (parenthesis are required):
|
|
9100
|
|
9101 /* AUTO_CONSTANT ( `this_is_really_constant_dont_autosense_it ) */
|
|
9102
|
|
9103 Better yet, use a parameter, which will be understood to be constant
|
|
9104 automatically.
|
|
9105
|
|
9106 OOps!
|
|
9107 If AUTOSENSE makes a mistake, please report it. (First try putting
|
|
9108 a begin/end after your always!) As a workaround, if a signal that
|
|
9109 shouldn't be in the sensitivity list was, use the AUTO_CONSTANT above.
|
|
9110 If a signal should be in the sensitivity list wasn't, placing it before
|
|
9111 the /*AUTOSENSE*/ comment will prevent it from being deleted when the
|
|
9112 autos are updated (or added if it occurs there already).
|
|
9113
|
|
9114 An example:
|
|
9115
|
|
9116 always @ (/*AUTOSENSE*/) begin
|
|
9117 /* AUTO_CONSTANT (`constant) */
|
|
9118 outin = ina | inb | `constant;
|
|
9119 out = outin;
|
|
9120 end
|
|
9121
|
|
9122 Typing \\[verilog-auto] will make this into:
|
|
9123
|
|
9124 always @ (/*AUTOSENSE*/ina or inb) begin
|
|
9125 /* AUTO_CONSTANT (`constant) */
|
|
9126 outin = ina | inb | `constant;
|
|
9127 out = outin;
|
|
9128 end"
|
|
9129 (save-excursion
|
|
9130 ;; Find beginning
|
|
9131 (let* ((start-pt (save-excursion
|
|
9132 (verilog-re-search-backward "(" nil t)
|
|
9133 (point)))
|
|
9134 (indent-pt (save-excursion
|
|
9135 (or (and (goto-char start-pt) (1+ (current-column)))
|
|
9136 (current-indentation))))
|
|
9137 (modi (verilog-modi-current))
|
|
9138 (sig-memories (verilog-signals-memory
|
|
9139 (append
|
|
9140 (verilog-modi-get-regs modi)
|
|
9141 (verilog-modi-get-wires modi))))
|
|
9142 sig-list not-first presense-sigs)
|
|
9143 ;; Read signals in always, eliminate outputs from sense list
|
|
9144 (setq presense-sigs (verilog-signals-from-signame
|
|
9145 (save-excursion
|
|
9146 (verilog-read-signals start-pt (point)))))
|
|
9147 (setq sig-list (verilog-auto-sense-sigs modi presense-sigs))
|
|
9148 (when sig-memories
|
|
9149 (let ((tlen (length sig-list)))
|
|
9150 (setq sig-list (verilog-signals-not-in sig-list sig-memories))
|
|
9151 (if (not (eq tlen (length sig-list))) (insert " /*memory or*/ "))))
|
|
9152 (if (and presense-sigs ;; Add a "or" if not "(.... or /*AUTOSENSE*/"
|
|
9153 (save-excursion (goto-char (point))
|
|
9154 (verilog-re-search-backward "[a-zA-Z0-9$_.%`]+" start-pt t)
|
|
9155 (verilog-re-search-backward "\\s-" start-pt t)
|
|
9156 (while (looking-at "\\s-`endif")
|
|
9157 (verilog-re-search-backward "[a-zA-Z0-9$_.%`]+" start-pt t)
|
|
9158 (verilog-re-search-backward "\\s-" start-pt t))
|
|
9159 (not (looking-at "\\s-or\\b"))))
|
|
9160 (setq not-first t))
|
|
9161 (setq sig-list (sort sig-list `verilog-signals-sort-compare))
|
|
9162 (while sig-list
|
|
9163 (cond ((> (+ 4 (current-column) (length (verilog-sig-name (car sig-list)))) fill-column) ;+4 for width of or
|
|
9164 (insert "\n")
|
|
9165 (indent-to indent-pt)
|
|
9166 (if not-first (insert "or ")))
|
|
9167 (not-first (insert " or ")))
|
|
9168 (insert (verilog-sig-name (car sig-list)))
|
|
9169 (setq sig-list (cdr sig-list)
|
|
9170 not-first t))
|
|
9171 )))
|
|
9172
|
|
9173 (defun verilog-auto-reset ()
|
|
9174 "Expand AUTORESET statements, as part of \\[verilog-auto].
|
|
9175 Replace the /*AUTORESET*/ comment with code to initialize all
|
|
9176 registers set elsewhere in the always block.
|
|
9177
|
|
9178 Limitations:
|
|
9179 AUTORESET will not clear memories.
|
|
9180
|
|
9181 AUTORESET uses <= if there are any <= in the block, else it uses =.
|
|
9182
|
|
9183 /*AUTORESET*/ presumes that any signals mentioned between the previous
|
|
9184 begin/case/if statement and the AUTORESET comment are being reset manually
|
|
9185 and should not be automatically reset. This includes omitting any signals
|
|
9186 used on the right hand side of assignments.
|
|
9187
|
|
9188 By default, AUTORESET will include the width of the signal in the autos,
|
|
9189 this is a recent change. To control this behavior, see
|
|
9190 `verilog-auto-reset-widths'.
|
|
9191
|
|
9192 AUTORESET ties signals to deasserted, which is presumed to be zero.
|
|
9193 Signals that match `verilog-active-low-regexp' will be deasserted by tieing
|
|
9194 them to a one.
|
|
9195
|
|
9196 An example:
|
|
9197
|
|
9198 always @(posedge clk or negedge reset_l) begin
|
|
9199 if (!reset_l) begin
|
|
9200 c <= 1;
|
|
9201 /*AUTORESET*/
|
|
9202 end
|
|
9203 else begin
|
|
9204 a <= in_a;
|
|
9205 b <= in_b;
|
|
9206 c <= in_c;
|
|
9207 end
|
|
9208 end
|
|
9209
|
|
9210 Typing \\[verilog-auto] will make this into:
|
|
9211
|
|
9212 always @(posedge core_clk or negedge reset_l) begin
|
|
9213 if (!reset_l) begin
|
|
9214 c <= 1;
|
|
9215 /*AUTORESET*/
|
|
9216 // Beginning of autoreset for uninitialized flops
|
|
9217 a <= 0;
|
|
9218 b <= 0;
|
|
9219 // End of automatics
|
|
9220 end
|
|
9221 else begin
|
|
9222 a <= in_a;
|
|
9223 b <= in_b;
|
|
9224 c <= in_c;
|
|
9225 end
|
|
9226 end"
|
|
9227
|
|
9228 (interactive)
|
|
9229 (save-excursion
|
|
9230 ;; Find beginning
|
|
9231 (let* ((indent-pt (current-indentation))
|
|
9232 (modi (verilog-modi-current))
|
|
9233 (all-list (verilog-modi-get-signals modi))
|
|
9234 sigss sig-list prereset-sigs assignment-str)
|
|
9235 ;; Read signals in always, eliminate outputs from reset list
|
|
9236 (setq prereset-sigs (verilog-signals-from-signame
|
|
9237 (save-excursion
|
|
9238 (verilog-read-signals
|
|
9239 (save-excursion
|
|
9240 (verilog-re-search-backward "\\(@\\|\\<begin\\>\\|\\<if\\>\\|\\<case\\>\\)" nil t)
|
|
9241 (point))
|
|
9242 (point)))))
|
|
9243 (save-excursion
|
|
9244 (verilog-re-search-backward "@" nil t)
|
|
9245 (setq sigss (verilog-read-always-signals)))
|
|
9246 (setq assignment-str (if (verilog-alw-get-uses-delayed sigss)
|
|
9247 (concat " <= " verilog-assignment-delay)
|
|
9248 " = "))
|
|
9249 (setq sig-list (verilog-signals-not-in (verilog-alw-get-outputs sigss)
|
|
9250 prereset-sigs))
|
|
9251 (setq sig-list (sort sig-list `verilog-signals-sort-compare))
|
|
9252 (when sig-list
|
|
9253 (insert "\n");
|
|
9254 (indent-to indent-pt)
|
|
9255 (insert "// Beginning of autoreset for uninitialized flops\n");
|
|
9256 (indent-to indent-pt)
|
|
9257 (while sig-list
|
|
9258 (let ((sig (or (assoc (verilog-sig-name (car sig-list)) all-list) ;; As sig-list has no widths
|
|
9259 (car sig-list))))
|
|
9260 (insert (verilog-sig-name sig)
|
|
9261 assignment-str
|
|
9262 (verilog-sig-tieoff sig (not verilog-auto-reset-widths))
|
|
9263 ";\n")
|
|
9264 (indent-to indent-pt)
|
|
9265 (setq sig-list (cdr sig-list))))
|
|
9266 (insert "// End of automatics"))
|
|
9267 )))
|
|
9268
|
|
9269 (defun verilog-auto-tieoff ()
|
|
9270 "Expand AUTOTIEOFF statements, as part of \\[verilog-auto].
|
|
9271 Replace the /*AUTOTIEOFF*/ comment with code to wire-tie all unused output
|
|
9272 signals to deasserted.
|
|
9273
|
|
9274 /*AUTOTIEOFF*/ is used to make stub modules; modules that have the same
|
|
9275 input/output list as another module, but no internals. Specifically, it
|
|
9276 finds all outputs in the module, and if that input is not otherwise declared
|
|
9277 as a register or wire, creates a tieoff.
|
|
9278
|
|
9279 AUTORESET ties signals to deasserted, which is presumed to be zero.
|
|
9280 Signals that match `verilog-active-low-regexp' will be deasserted by tieing
|
|
9281 them to a one.
|
|
9282
|
|
9283 An example of making a stub for another module:
|
|
9284
|
|
9285 module FooStub (/*AUTOINST*/);
|
|
9286 /*AUTOINOUTMODULE(\"Foo\")*/
|
|
9287 /*AUTOTIEOFF*/
|
|
9288 // verilator lint_off UNUSED
|
|
9289 wire _unused_ok = &{1'b0,
|
|
9290 /*AUTOUNUSED*/
|
|
9291 1'b0};
|
|
9292 // verilator lint_on UNUSED
|
|
9293 endmodule
|
|
9294
|
|
9295 Typing \\[verilog-auto] will make this into:
|
|
9296
|
|
9297 module FooStub (/*AUTOINST*/...);
|
|
9298 /*AUTOINOUTMODULE(\"Foo\")*/
|
|
9299 // Beginning of autotieoff
|
|
9300 output [2:0] foo;
|
|
9301 // End of automatics
|
|
9302
|
|
9303 /*AUTOTIEOFF*/
|
|
9304 // Beginning of autotieoff
|
|
9305 wire [2:0] foo = 3'b0;
|
|
9306 // End of automatics
|
|
9307 ...
|
|
9308 endmodule"
|
|
9309 (interactive)
|
|
9310 (save-excursion
|
|
9311 ;; Find beginning
|
|
9312 (let* ((indent-pt (current-indentation))
|
|
9313 (modi (verilog-modi-current))
|
|
9314 (sig-list (verilog-signals-not-in
|
|
9315 (verilog-modi-get-outputs modi)
|
|
9316 (append (verilog-modi-get-wires modi)
|
|
9317 (verilog-modi-get-regs modi)
|
|
9318 (verilog-modi-get-assigns modi)
|
|
9319 (verilog-modi-get-consts modi)
|
|
9320 (verilog-modi-get-gparams modi)
|
|
9321 (verilog-modi-get-sub-outputs modi)
|
|
9322 (verilog-modi-get-sub-inouts modi)
|
|
9323 ))))
|
|
9324 (when sig-list
|
|
9325 (forward-line 1)
|
|
9326 (verilog-insert-indent "// Beginning of automatic tieoffs (for this module's unterminated outputs)\n")
|
|
9327 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare))
|
|
9328 (verilog-modi-cache-add-wires modi sig-list) ; Before we trash list
|
|
9329 (while sig-list
|
|
9330 (let ((sig (car sig-list)))
|
|
9331 (verilog-insert-one-definition sig "wire" indent-pt)
|
|
9332 (indent-to (max 48 (+ indent-pt 40)))
|
|
9333 (insert "= " (verilog-sig-tieoff sig)
|
|
9334 ";\n")
|
|
9335 (setq sig-list (cdr sig-list))))
|
|
9336 (verilog-insert-indent "// End of automatics\n")
|
|
9337 ))))
|
|
9338
|
|
9339 (defun verilog-auto-unused ()
|
|
9340 "Expand AUTOUNUSED statements, as part of \\[verilog-auto].
|
|
9341 Replace the /*AUTOUNUSED*/ comment with a comma separated list of all unused
|
|
9342 input and inout signals.
|
|
9343
|
|
9344 /*AUTOUNUSED*/ is used to make stub modules; modules that have the same
|
|
9345 input/output list as another module, but no internals. Specifically, it
|
|
9346 finds all inputs and inouts in the module, and if that input is not otherwise
|
|
9347 used, adds it to a comma separated list.
|
|
9348
|
|
9349 The comma separated list is intended to be used to create a _unused_ok
|
|
9350 signal. Using the exact name \"_unused_ok\" for name of the temporary
|
|
9351 signal is recommended as it will insure maximum forward compatibility, it
|
|
9352 also makes lint warnings easy to understand; ignore any unused warnings
|
|
9353 with \"unused\" in the signal name.
|
|
9354
|
|
9355 To reduce simulation time, the _unused_ok signal should be forced to a
|
|
9356 constant to prevent wiggling. The easiest thing to do is use a
|
|
9357 reduction-and with 1'b0 as shown.
|
|
9358
|
|
9359 This way all unused signals are in one place, making it convenient to add
|
|
9360 your tool's specific pragmas around the assignment to disable any unused
|
|
9361 warnings.
|
|
9362
|
|
9363 You can add signals you do not want included in AUTOUNUSED with
|
|
9364 `verilog-auto-unused-ignore-regexp'.
|
|
9365
|
|
9366 An example of making a stub for another module:
|
|
9367
|
|
9368 module FooStub (/*AUTOINST*/);
|
|
9369 /*AUTOINOUTMODULE(\"Foo\")*/
|
|
9370 /*AUTOTIEOFF*/
|
|
9371 // verilator lint_off UNUSED
|
|
9372 wire _unused_ok = &{1'b0,
|
|
9373 /*AUTOUNUSED*/
|
|
9374 1'b0};
|
|
9375 // verilator lint_on UNUSED
|
|
9376 endmodule
|
|
9377
|
|
9378 Typing \\[verilog-auto] will make this into:
|
|
9379
|
|
9380 ...
|
|
9381 // verilator lint_off UNUSED
|
|
9382 wire _unused_ok = &{1'b0,
|
|
9383 /*AUTOUNUSED*/
|
|
9384 // Beginning of automatics
|
|
9385 unused_input_a,
|
|
9386 unused_input_b,
|
|
9387 unused_input_c,
|
|
9388 // End of automatics
|
|
9389 1'b0};
|
|
9390 // verilator lint_on UNUSED
|
|
9391 endmodule"
|
|
9392 (interactive)
|
|
9393 (save-excursion
|
|
9394 ;; Find beginning
|
|
9395 (let* ((indent-pt (progn (search-backward "/*") (current-column)))
|
|
9396 (modi (verilog-modi-current))
|
|
9397 (sig-list (verilog-signals-not-in
|
|
9398 (append (verilog-modi-get-inputs modi)
|
|
9399 (verilog-modi-get-inouts modi))
|
|
9400 (append (verilog-modi-get-sub-inputs modi)
|
|
9401 (verilog-modi-get-sub-inouts modi)
|
|
9402 ))))
|
|
9403 (setq sig-list (verilog-signals-not-matching-regexp
|
|
9404 sig-list verilog-auto-unused-ignore-regexp))
|
|
9405 (when sig-list
|
|
9406 (forward-line 1)
|
|
9407 (verilog-insert-indent "// Beginning of automatic unused inputs\n")
|
|
9408 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare))
|
|
9409 (while sig-list
|
|
9410 (let ((sig (car sig-list)))
|
|
9411 (indent-to indent-pt)
|
|
9412 (insert (verilog-sig-name sig) ",\n")
|
|
9413 (setq sig-list (cdr sig-list))))
|
|
9414 (verilog-insert-indent "// End of automatics\n")
|
|
9415 ))))
|
|
9416
|
|
9417 (defun verilog-enum-ascii (signm elim-regexp)
|
|
9418 "Convert a enum name SIGNM to a ascii string for insertion.
|
|
9419 Remove user provided prefix ELIM-REGEXP."
|
|
9420 (or elim-regexp (setq elim-regexp "_ DONT MATCH IT_"))
|
|
9421 (let ((case-fold-search t))
|
|
9422 ;; All upper becomes all lower for readability
|
|
9423 (downcase (verilog-string-replace-matches elim-regexp "" nil nil signm))))
|
|
9424
|
|
9425 (defun verilog-auto-ascii-enum ()
|
|
9426 "Expand AUTOASCIIENUM statements, as part of \\[verilog-auto].
|
|
9427 Create a register to contain the ASCII decode of a enumerated signal type.
|
|
9428 This will allow trace viewers to show the ASCII name of states.
|
|
9429
|
|
9430 First, parameters are built into a enumeration using the synopsys enum
|
|
9431 comment. The comment must be between the keyword and the symbol.
|
79546
|
9432 \(Annoying, but that's what Synopsys's dc_shell FSM reader requires.)
|
79545
|
9433
|
|
9434 Next, registers which that enum applies to are also tagged with the same
|
|
9435 enum. Synopsys also suggests labeling state vectors, but `verilog-mode'
|
|
9436 doesn't care.
|
|
9437
|
|
9438 Finally, a AUTOASCIIENUM command is used.
|
|
9439
|
|
9440 The first parameter is the name of the signal to be decoded.
|
|
9441
|
|
9442 The second parameter is the name to store the ASCII code into. For the
|
|
9443 signal foo, I suggest the name _foo__ascii, where the leading _ indicates
|
|
9444 a signal that is just for simulation, and the magic characters _ascii
|
|
9445 tell viewers like Dinotrace to display in ASCII format.
|
|
9446
|
|
9447 The final optional parameter is a string which will be removed from the
|
|
9448 state names.
|
|
9449
|
|
9450 An example:
|
|
9451
|
|
9452 //== State enumeration
|
|
9453 parameter [2:0] // synopsys enum state_info
|
|
9454 SM_IDLE = 3'b000,
|
|
9455 SM_SEND = 3'b001,
|
|
9456 SM_WAIT1 = 3'b010;
|
|
9457 //== State variables
|
|
9458 reg [2:0] /* synopsys enum state_info */
|
|
9459 state_r; /* synopsys state_vector state_r */
|
|
9460 reg [2:0] /* synopsys enum state_info */
|
|
9461 state_e1;
|
|
9462
|
|
9463 //== ASCII state decoding
|
|
9464
|
|
9465 /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
|
|
9466
|
|
9467 Typing \\[verilog-auto] will make this into:
|
|
9468
|
|
9469 ... same front matter ...
|
|
9470
|
|
9471 /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/
|
|
9472 // Beginning of automatic ASCII enum decoding
|
|
9473 reg [39:0] state_ascii_r; // Decode of state_r
|
|
9474 always @(state_r) begin
|
|
9475 case ({state_r})
|
|
9476 SM_IDLE: state_ascii_r = \"idle \";
|
|
9477 SM_SEND: state_ascii_r = \"send \";
|
|
9478 SM_WAIT1: state_ascii_r = \"wait1\";
|
|
9479 default: state_ascii_r = \"%Erro\";
|
|
9480 endcase
|
|
9481 end
|
|
9482 // End of automatics"
|
|
9483 (save-excursion
|
|
9484 (let* ((params (verilog-read-auto-params 2 3))
|
|
9485 (undecode-name (nth 0 params))
|
|
9486 (ascii-name (nth 1 params))
|
|
9487 (elim-regexp (nth 2 params))
|
|
9488 ;;
|
|
9489 (indent-pt (current-indentation))
|
|
9490 (modi (verilog-modi-current))
|
|
9491 ;;
|
|
9492 (sig-list-consts (append (verilog-modi-get-consts modi)
|
|
9493 (verilog-modi-get-gparams modi)))
|
|
9494 (sig-list-all (append (verilog-modi-get-regs modi)
|
|
9495 (verilog-modi-get-outputs modi)
|
|
9496 (verilog-modi-get-inouts modi)
|
|
9497 (verilog-modi-get-inputs modi)
|
|
9498 (verilog-modi-get-wires modi)))
|
|
9499 ;;
|
|
9500 (undecode-sig (or (assoc undecode-name sig-list-all)
|
|
9501 (error "%s: Signal %s not found in design" (verilog-point-text) undecode-name)))
|
|
9502 (undecode-enum (or (verilog-sig-enum undecode-sig)
|
|
9503 (error "%s: Signal %s does not have a enum tag" (verilog-point-text) undecode-name)))
|
|
9504 ;;
|
|
9505 (enum-sigs (or (verilog-signals-matching-enum sig-list-consts undecode-enum)
|
|
9506 (error "%s: No state definitions for %s" (verilog-point-text) undecode-enum)))
|
|
9507 ;;
|
|
9508 (enum-chars 0)
|
|
9509 (ascii-chars 0))
|
|
9510 ;;
|
|
9511 ;; Find number of ascii chars needed
|
|
9512 (let ((tmp-sigs enum-sigs))
|
|
9513 (while tmp-sigs
|
|
9514 (setq enum-chars (max enum-chars (length (verilog-sig-name (car tmp-sigs))))
|
|
9515 ascii-chars (max ascii-chars (length (verilog-enum-ascii
|
|
9516 (verilog-sig-name (car tmp-sigs))
|
|
9517 elim-regexp)))
|
|
9518 tmp-sigs (cdr tmp-sigs))))
|
|
9519 ;;
|
|
9520 (forward-line 1)
|
|
9521 (verilog-insert-indent "// Beginning of automatic ASCII enum decoding\n")
|
|
9522 (let ((decode-sig-list (list (list ascii-name (format "[%d:0]" (- (* ascii-chars 8) 1))
|
|
9523 (concat "Decode of " undecode-name) nil nil))))
|
|
9524 (verilog-insert-definition decode-sig-list "reg" indent-pt nil)
|
|
9525 (verilog-modi-cache-add-regs modi decode-sig-list))
|
|
9526 ;;
|
|
9527 (verilog-insert-indent "always @(" undecode-name ") begin\n")
|
|
9528 (setq indent-pt (+ indent-pt verilog-indent-level))
|
|
9529 (indent-to indent-pt)
|
|
9530 (insert "case ({" undecode-name "})\n")
|
|
9531 (setq indent-pt (+ indent-pt verilog-case-indent))
|
|
9532 ;;
|
|
9533 (let ((tmp-sigs enum-sigs)
|
|
9534 (chrfmt (format "%%-%ds %s = \"%%-%ds\";\n" (1+ (max 8 enum-chars))
|
|
9535 ascii-name ascii-chars))
|
|
9536 (errname (substring "%Error" 0 (min 6 ascii-chars))))
|
|
9537 (while tmp-sigs
|
|
9538 (verilog-insert-indent
|
|
9539 (format chrfmt (concat (verilog-sig-name (car tmp-sigs)) ":")
|
|
9540 (verilog-enum-ascii (verilog-sig-name (car tmp-sigs))
|
|
9541 elim-regexp)))
|
|
9542 (setq tmp-sigs (cdr tmp-sigs)))
|
|
9543 (verilog-insert-indent (format chrfmt "default:" errname)))
|
|
9544 ;;
|
|
9545 (setq indent-pt (- indent-pt verilog-case-indent))
|
|
9546 (verilog-insert-indent "endcase\n")
|
|
9547 (setq indent-pt (- indent-pt verilog-indent-level))
|
|
9548 (verilog-insert-indent "end\n"
|
|
9549 "// End of automatics\n")
|
|
9550 )))
|
|
9551
|
|
9552 (defun verilog-auto-templated-rel ()
|
|
9553 "Replace Templated relative line numbers with absolute line numbers.
|
|
9554 Internal use only. This hacks around the line numbers in AUTOINST Templates
|
|
9555 being different from the final output's line numbering."
|
|
9556 (let ((templateno 0) (template-line (list 0)))
|
|
9557 ;; Find line number each template is on
|
|
9558 (goto-char (point-min))
|
|
9559 (while (search-forward "AUTO_TEMPLATE" nil t)
|
|
9560 (setq templateno (1+ templateno))
|
|
9561 (setq template-line (cons (count-lines (point-min) (point)) template-line)))
|
|
9562 (setq template-line (nreverse template-line))
|
|
9563 ;; Replace T# L# with absolute line number
|
|
9564 (goto-char (point-min))
|
|
9565 (while (re-search-forward " Templated T\\([0-9]+\\) L\\([0-9]+\\)" nil t)
|
|
9566 (replace-match (concat " Templated "
|
|
9567 (int-to-string (+ (nth (string-to-int (match-string 1))
|
|
9568 template-line)
|
|
9569 (string-to-int (match-string 2)))))
|
|
9570 t t))))
|
|
9571
|
|
9572
|
|
9573 ;;
|
|
9574 ;; Auto top level
|
|
9575 ;;
|
|
9576
|
|
9577 (defun verilog-auto (&optional inject) ; Use verilog-inject-auto instead of passing a arg
|
|
9578 "Expand AUTO statements.
|
|
9579 Look for any /*AUTO...*/ commands in the code, as used in
|
|
9580 instantiations or argument headers. Update the list of signals
|
|
9581 following the /*AUTO...*/ command.
|
|
9582
|
|
9583 Use \\[verilog-delete-auto] to remove the AUTOs.
|
|
9584
|
|
9585 Use \\[verilog-inject-auto] to insert AUTOs for the first time.
|
|
9586
|
|
9587 Use \\[verilog-faq] for a pointer to frequently asked questions.
|
|
9588
|
|
9589 The hooks `verilog-before-auto-hook' and `verilog-auto-hook' are
|
|
9590 called before and after this function, respectively.
|
|
9591
|
|
9592 For example:
|
|
9593 module (/*AUTOARG*/)
|
|
9594 /*AUTOINPUT*/
|
|
9595 /*AUTOOUTPUT*/
|
|
9596 /*AUTOWIRE*/
|
|
9597 /*AUTOREG*/
|
|
9598 somesub sub #(/*AUTOINSTPARAM*/) (/*AUTOINST*/);
|
|
9599
|
|
9600 You can also update the AUTOs from the shell using:
|
|
9601 emacs --batch <filenames.v> -f verilog-batch-auto
|
|
9602 Or fix indentation with:
|
|
9603 emacs --batch <filenames.v> -f verilog-batch-indent
|
|
9604 Likewise, you can delete or inject AUTOs with:
|
|
9605 emacs --batch <filenames.v> -f verilog-batch-delete-auto
|
|
9606 emacs --batch <filenames.v> -f verilog-batch-inject-auto
|
|
9607
|
|
9608 Using \\[describe-function], see also:
|
|
9609 `verilog-auto-arg' for AUTOARG module instantiations
|
|
9610 `verilog-auto-ascii-enum' for AUTOASCIIENUM enumeration decoding
|
|
9611 `verilog-auto-inout-module' for AUTOINOUTMODULE copying i/o from elsewhere
|
|
9612 `verilog-auto-inout' for AUTOINOUT making hierarchy inouts
|
|
9613 `verilog-auto-input' for AUTOINPUT making hierarchy inputs
|
|
9614 `verilog-auto-inst' for AUTOINST instantiation pins
|
|
9615 `verilog-auto-star' for AUTOINST .* SystemVerilog pins
|
|
9616 `verilog-auto-inst-param' for AUTOINSTPARAM instantiation params
|
|
9617 `verilog-auto-output' for AUTOOUTPUT making hierarchy outputs
|
|
9618 `verilog-auto-output-every' for AUTOOUTPUTEVERY making all outputs
|
|
9619 `verilog-auto-reg' for AUTOREG registers
|
|
9620 `verilog-auto-reg-input' for AUTOREGINPUT instantiation registers
|
|
9621 `verilog-auto-reset' for AUTORESET flop resets
|
|
9622 `verilog-auto-sense' for AUTOSENSE always sensitivity lists
|
|
9623 `verilog-auto-tieoff' for AUTOTIEOFF output tieoffs
|
|
9624 `verilog-auto-unused' for AUTOUNUSED unused inputs/inouts
|
|
9625 `verilog-auto-wire' for AUTOWIRE instantiation wires
|
|
9626
|
|
9627 `verilog-read-defines' for reading `define values
|
|
9628 `verilog-read-includes' for reading `includes
|
|
9629
|
|
9630 If you have bugs with these autos, try contacting the AUTOAUTHOR
|
|
9631 Wilson Snyder (wsnyder@wsnyder.org), and/or see http://www.veripool.com."
|
|
9632 (interactive)
|
|
9633 (unless noninteractive (message "Updating AUTOs..."))
|
|
9634 (if (featurep 'dinotrace)
|
|
9635 (dinotrace-unannotate-all))
|
|
9636 (let ((oldbuf (if (not (buffer-modified-p))
|
|
9637 (buffer-string)))
|
|
9638 ;; Before version 20, match-string with font-lock returns a
|
|
9639 ;; vector that is not equal to the string. IE if on "input"
|
|
9640 ;; nil==(equal "input" (progn (looking-at "input") (match-string 0)))
|
|
9641 (fontlocked (when (and (boundp 'font-lock-mode)
|
|
9642 font-lock-mode)
|
|
9643 (font-lock-mode nil)
|
|
9644 t)))
|
|
9645 (unwind-protect
|
|
9646 (save-excursion
|
|
9647 ;; If we're not in verilog-mode, change syntax table so parsing works right
|
|
9648 (unless (eq major-mode `verilog-mode) (verilog-mode))
|
|
9649 ;; Allow user to customize
|
|
9650 (run-hooks 'verilog-before-auto-hook)
|
|
9651 ;; Try to save the user from needing to revert-file to reread file local-variables
|
|
9652 (verilog-auto-reeval-locals)
|
|
9653 (verilog-read-auto-lisp (point-min) (point-max))
|
|
9654 (verilog-getopt-flags)
|
|
9655 ;; These two may seem obvious to do always, but on large includes it can be way too slow
|
|
9656 (when verilog-auto-read-includes
|
|
9657 (verilog-read-includes)
|
|
9658 (verilog-read-defines nil nil t))
|
|
9659 ;; This particular ordering is important
|
|
9660 ;; INST: Lower modules correct, no internal dependencies, FIRST
|
|
9661 (verilog-preserve-cache
|
|
9662 ;; Clear existing autos else we'll be screwed by existing ones
|
|
9663 (verilog-delete-auto)
|
|
9664 ;; Injection if appropriate
|
|
9665 (when inject
|
|
9666 (verilog-inject-inst)
|
|
9667 (verilog-inject-sense)
|
|
9668 (verilog-inject-arg))
|
|
9669 ;;
|
|
9670 (verilog-auto-search-do "/*AUTOINSTPARAM*/" 'verilog-auto-inst-param)
|
|
9671 (verilog-auto-search-do "/*AUTOINST*/" 'verilog-auto-inst)
|
|
9672 (verilog-auto-search-do ".*" 'verilog-auto-star)
|
|
9673 ;; Doesn't matter when done, but combine it with a common changer
|
|
9674 (verilog-auto-re-search-do "/\\*\\(AUTOSENSE\\|AS\\)\\*/" 'verilog-auto-sense)
|
|
9675 (verilog-auto-re-search-do "/\\*AUTORESET\\*/" 'verilog-auto-reset)
|
|
9676 ;; Must be done before autoin/out as creates a reg
|
|
9677 (verilog-auto-re-search-do "/\\*AUTOASCIIENUM([^)]*)\\*/" 'verilog-auto-ascii-enum)
|
|
9678 ;;
|
|
9679 ;; first in/outs from other files
|
|
9680 (verilog-auto-re-search-do "/\\*AUTOINOUTMODULE([^)]*)\\*/" 'verilog-auto-inout-module)
|
|
9681 ;; next in/outs which need previous sucked inputs first
|
|
9682 (verilog-auto-search-do "/*AUTOOUTPUT*/" 'verilog-auto-output)
|
|
9683 (verilog-auto-search-do "/*AUTOINPUT*/" 'verilog-auto-input)
|
|
9684 (verilog-auto-search-do "/*AUTOINOUT*/" 'verilog-auto-inout)
|
|
9685 ;; Then tie off those in/outs
|
|
9686 (verilog-auto-search-do "/*AUTOTIEOFF*/" 'verilog-auto-tieoff)
|
|
9687 ;; Wires/regs must be after inputs/outputs
|
|
9688 (verilog-auto-search-do "/*AUTOWIRE*/" 'verilog-auto-wire)
|
|
9689 (verilog-auto-search-do "/*AUTOREG*/" 'verilog-auto-reg)
|
|
9690 (verilog-auto-search-do "/*AUTOREGINPUT*/" 'verilog-auto-reg-input)
|
|
9691 ;; outputevery needs AUTOOUTPUTs done first
|
|
9692 (verilog-auto-search-do "/*AUTOOUTPUTEVERY*/" 'verilog-auto-output-every)
|
|
9693 ;; After we've created all new variables
|
|
9694 (verilog-auto-search-do "/*AUTOUNUSED*/" 'verilog-auto-unused)
|
|
9695 ;; Must be after all inputs outputs are generated
|
|
9696 (verilog-auto-search-do "/*AUTOARG*/" 'verilog-auto-arg)
|
|
9697 ;; Fix line numbers (comments only)
|
|
9698 (verilog-auto-templated-rel)
|
|
9699 )
|
|
9700 ;;
|
|
9701 (run-hooks 'verilog-auto-hook)
|
|
9702 ;;
|
|
9703 (set (make-local-variable 'verilog-auto-update-tick) (buffer-modified-tick))
|
|
9704 ;;
|
|
9705 ;; If end result is same as when started, clear modified flag
|
|
9706 (cond ((and oldbuf (equal oldbuf (buffer-string)))
|
|
9707 (set-buffer-modified-p nil)
|
|
9708 (unless noninteractive (message "Updating AUTOs...done (no changes)")))
|
|
9709 (t (unless noninteractive (message "Updating AUTOs...done")))))
|
|
9710 ;; Unwind forms
|
|
9711 (progn
|
|
9712 ;; Restore font-lock
|
|
9713 (when fontlocked (font-lock-mode t)))
|
|
9714 )))
|
|
9715
|
|
9716
|
|
9717 ;;
|
|
9718 ;; Skeleton based code insertion
|
|
9719 ;;
|
79546
|
9720 (defvar verilog-template-map
|
|
9721 (let ((map (make-sparse-keymap)))
|
|
9722 (define-key map "a" 'verilog-sk-always)
|
|
9723 (define-key map "b" 'verilog-sk-begin)
|
|
9724 (define-key map "c" 'verilog-sk-case)
|
|
9725 (define-key map "f" 'verilog-sk-for)
|
|
9726 (define-key map "g" 'verilog-sk-generate)
|
|
9727 (define-key map "h" 'verilog-sk-header)
|
|
9728 (define-key map "i" 'verilog-sk-initial)
|
|
9729 (define-key map "j" 'verilog-sk-fork)
|
|
9730 (define-key map "m" 'verilog-sk-module)
|
|
9731 (define-key map "p" 'verilog-sk-primitive)
|
|
9732 (define-key map "r" 'verilog-sk-repeat)
|
|
9733 (define-key map "s" 'verilog-sk-specify)
|
|
9734 (define-key map "t" 'verilog-sk-task)
|
|
9735 (define-key map "w" 'verilog-sk-while)
|
|
9736 (define-key map "x" 'verilog-sk-casex)
|
|
9737 (define-key map "z" 'verilog-sk-casez)
|
|
9738 (define-key map "?" 'verilog-sk-if)
|
|
9739 (define-key map ":" 'verilog-sk-else-if)
|
|
9740 (define-key map "/" 'verilog-sk-comment)
|
|
9741 (define-key map "A" 'verilog-sk-assign)
|
|
9742 (define-key map "F" 'verilog-sk-function)
|
|
9743 (define-key map "I" 'verilog-sk-input)
|
|
9744 (define-key map "O" 'verilog-sk-output)
|
|
9745 (define-key map "S" 'verilog-sk-state-machine)
|
|
9746 (define-key map "=" 'verilog-sk-inout)
|
|
9747 (define-key map "W" 'verilog-sk-wire)
|
|
9748 (define-key map "R" 'verilog-sk-reg)
|
|
9749 (define-key map "D" 'verilog-sk-define-signal))
|
79545
|
9750 "Keymap used in Verilog mode for smart template operations.")
|
|
9751
|
|
9752
|
|
9753 ;;
|
|
9754 ;; Place the templates into Verilog Mode. They may be inserted under any key.
|
|
9755 ;; C-c C-t will be the default. If you use templates a lot, you
|
|
9756 ;; may want to consider moving the binding to another key in your .emacs
|
|
9757 ;; file.
|
|
9758 ;;
|
|
9759 ;(define-key verilog-mode-map "\C-ct" verilog-template-map)
|
|
9760 (define-key verilog-mode-map "\C-c\C-t" verilog-template-map)
|
|
9761
|
|
9762 ;;; ---- statement skeletons ------------------------------------------
|
|
9763
|
|
9764 (define-skeleton verilog-sk-prompt-condition
|
|
9765 "Prompt for the loop condition."
|
|
9766 "[condition]: " str )
|
|
9767
|
|
9768 (define-skeleton verilog-sk-prompt-init
|
|
9769 "Prompt for the loop init statement."
|
|
9770 "[initial statement]: " str )
|
|
9771
|
|
9772 (define-skeleton verilog-sk-prompt-inc
|
|
9773 "Prompt for the loop increment statement."
|
|
9774 "[increment statement]: " str )
|
|
9775
|
|
9776 (define-skeleton verilog-sk-prompt-name
|
|
9777 "Prompt for the name of something."
|
|
9778 "[name]: " str)
|
|
9779
|
|
9780 (define-skeleton verilog-sk-prompt-clock
|
|
9781 "Prompt for the name of something."
|
|
9782 "name and edge of clock(s): " str)
|
|
9783
|
|
9784 (defvar verilog-sk-reset nil)
|
|
9785 (defun verilog-sk-prompt-reset ()
|
|
9786 "Prompt for the name of a state machine reset."
|
|
9787 (setq verilog-sk-reset (read-input "name of reset: " "rst")))
|
|
9788
|
|
9789
|
|
9790 (define-skeleton verilog-sk-prompt-state-selector
|
|
9791 "Prompt for the name of a state machine selector."
|
|
9792 "name of selector (eg {a,b,c,d}): " str )
|
|
9793
|
|
9794 (define-skeleton verilog-sk-prompt-output
|
|
9795 "Prompt for the name of something."
|
|
9796 "output: " str)
|
|
9797
|
|
9798 (define-skeleton verilog-sk-prompt-msb
|
|
9799 "Prompt for least significant bit specification."
|
|
9800 "msb:" str & ?: & (verilog-sk-prompt-lsb) | -1 )
|
|
9801
|
|
9802 (define-skeleton verilog-sk-prompt-lsb
|
|
9803 "Prompt for least significant bit specification."
|
|
9804 "lsb:" str )
|
|
9805
|
|
9806 (defvar verilog-sk-p nil)
|
|
9807 (define-skeleton verilog-sk-prompt-width
|
|
9808 "Prompt for a width specification."
|
|
9809 ()
|
|
9810 (progn
|
|
9811 (setq verilog-sk-p (point))
|
|
9812 (verilog-sk-prompt-msb)
|
|
9813 (if (> (point) verilog-sk-p) "] " " ")))
|
|
9814
|
|
9815 (defun verilog-sk-header ()
|
|
9816 "Insert a descriptive header at the top of the file."
|
|
9817 (interactive "*")
|
|
9818 (save-excursion
|
|
9819 (goto-char (point-min))
|
|
9820 (verilog-sk-header-tmpl)))
|
|
9821
|
|
9822 (define-skeleton verilog-sk-header-tmpl
|
|
9823 "Insert a comment block containing the module title, author, etc."
|
|
9824 "[Description]: "
|
|
9825 "// -*- Mode: Verilog -*-"
|
|
9826 "\n// Filename : " (buffer-name)
|
|
9827 "\n// Description : " str
|
|
9828 "\n// Author : " (user-full-name)
|
|
9829 "\n// Created On : " (current-time-string)
|
|
9830 "\n// Last Modified By: ."
|
|
9831 "\n// Last Modified On: ."
|
|
9832 "\n// Update Count : 0"
|
|
9833 "\n// Status : Unknown, Use with caution!"
|
|
9834 "\n")
|
|
9835
|
|
9836 (define-skeleton verilog-sk-module
|
|
9837 "Insert a module definition."
|
|
9838 ()
|
|
9839 > "module " (verilog-sk-prompt-name) " (/*AUTOARG*/ ) ;" \n
|
|
9840 > _ \n
|
|
9841 > (- verilog-indent-level-behavioral) "endmodule" (progn (electric-verilog-terminate-line) nil))
|
|
9842
|
|
9843 (define-skeleton verilog-sk-primitive
|
|
9844 "Insert a task definition."
|
|
9845 ()
|
|
9846 > "primitive " (verilog-sk-prompt-name) " ( " (verilog-sk-prompt-output) ("input:" ", " str ) " );"\n
|
|
9847 > _ \n
|
|
9848 > (- verilog-indent-level-behavioral) "endprimitive" (progn (electric-verilog-terminate-line) nil))
|
|
9849
|
|
9850 (define-skeleton verilog-sk-task
|
|
9851 "Insert a task definition."
|
|
9852 ()
|
|
9853 > "task " (verilog-sk-prompt-name) & ?; \n
|
|
9854 > _ \n
|
|
9855 > "begin" \n
|
|
9856 > \n
|
|
9857 > (- verilog-indent-level-behavioral) "end" \n
|
|
9858 > (- verilog-indent-level-behavioral) "endtask" (progn (electric-verilog-terminate-line) nil))
|
|
9859
|
|
9860 (define-skeleton verilog-sk-function
|
|
9861 "Insert a function definition."
|
|
9862 ()
|
|
9863 > "function [" (verilog-sk-prompt-width) | -1 (verilog-sk-prompt-name) ?; \n
|
|
9864 > _ \n
|
|
9865 > "begin" \n
|
|
9866 > \n
|
|
9867 > (- verilog-indent-level-behavioral) "end" \n
|
|
9868 > (- verilog-indent-level-behavioral) "endfunction" (progn (electric-verilog-terminate-line) nil))
|
|
9869
|
|
9870 (define-skeleton verilog-sk-always
|
|
9871 "Insert always block. Uses the minibuffer to prompt
|
|
9872 for sensitivity list."
|
|
9873 ()
|
|
9874 > "always @ ( /*AUTOSENSE*/ ) begin\n"
|
|
9875 > _ \n
|
|
9876 > (- verilog-indent-level-behavioral) "end" \n >
|
|
9877 )
|
|
9878
|
|
9879 (define-skeleton verilog-sk-initial
|
|
9880 "Insert an initial block."
|
|
9881 ()
|
|
9882 > "initial begin\n"
|
|
9883 > _ \n
|
|
9884 > (- verilog-indent-level-behavioral) "end" \n > )
|
|
9885
|
|
9886 (define-skeleton verilog-sk-specify
|
|
9887 "Insert specify block. "
|
|
9888 ()
|
|
9889 > "specify\n"
|
|
9890 > _ \n
|
|
9891 > (- verilog-indent-level-behavioral) "endspecify" \n > )
|
|
9892
|
|
9893 (define-skeleton verilog-sk-generate
|
|
9894 "Insert generate block. "
|
|
9895 ()
|
|
9896 > "generate\n"
|
|
9897 > _ \n
|
|
9898 > (- verilog-indent-level-behavioral) "endgenerate" \n > )
|
|
9899
|
|
9900 (define-skeleton verilog-sk-begin
|
|
9901 "Insert begin end block. Uses the minibuffer to prompt for name"
|
|
9902 ()
|
|
9903 > "begin" (verilog-sk-prompt-name) \n
|
|
9904 > _ \n
|
|
9905 > (- verilog-indent-level-behavioral) "end"
|
|
9906 )
|
|
9907
|
|
9908 (define-skeleton verilog-sk-fork
|
|
9909 "Insert an fork join block."
|
|
9910 ()
|
|
9911 > "fork\n"
|
|
9912 > "begin" \n
|
|
9913 > _ \n
|
|
9914 > (- verilog-indent-level-behavioral) "end" \n
|
|
9915 > "begin" \n
|
|
9916 > \n
|
|
9917 > (- verilog-indent-level-behavioral) "end" \n
|
|
9918 > (- verilog-indent-level-behavioral) "join" \n
|
|
9919 > )
|
|
9920
|
|
9921
|
|
9922 (define-skeleton verilog-sk-case
|
|
9923 "Build skeleton case statement, prompting for the selector expression,
|
|
9924 and the case items."
|
|
9925 "[selector expression]: "
|
|
9926 > "case (" str ") " \n
|
|
9927 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n )
|
|
9928 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
|
|
9929
|
|
9930 (define-skeleton verilog-sk-casex
|
|
9931 "Build skeleton casex statement, prompting for the selector expression,
|
|
9932 and the case items."
|
|
9933 "[selector expression]: "
|
|
9934 > "casex (" str ") " \n
|
|
9935 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n )
|
|
9936 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
|
|
9937
|
|
9938 (define-skeleton verilog-sk-casez
|
|
9939 "Build skeleton casez statement, prompting for the selector expression,
|
|
9940 and the case items."
|
|
9941 "[selector expression]: "
|
|
9942 > "casez (" str ") " \n
|
|
9943 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n )
|
|
9944 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil))
|
|
9945
|
|
9946 (define-skeleton verilog-sk-if
|
|
9947 "Insert a skeleton if statement."
|
|
9948 > "if (" (verilog-sk-prompt-condition) & ")" " begin" \n
|
|
9949 > _ \n
|
|
9950 > (- verilog-indent-level-behavioral) "end " \n )
|
|
9951
|
|
9952 (define-skeleton verilog-sk-else-if
|
|
9953 "Insert a skeleton else if statement."
|
|
9954 > (verilog-indent-line) "else if ("
|
|
9955 (progn (setq verilog-sk-p (point)) nil) (verilog-sk-prompt-condition) (if (> (point) verilog-sk-p) ") " -1 ) & " begin" \n
|
|
9956 > _ \n
|
|
9957 > "end" (progn (electric-verilog-terminate-line) nil))
|
|
9958
|
|
9959 (define-skeleton verilog-sk-datadef
|
|
9960 "Common routine to get data definition"
|
|
9961 ()
|
|
9962 (verilog-sk-prompt-width) | -1 ("name (RET to end):" str ", ") -2 ";" \n)
|
|
9963
|
|
9964 (define-skeleton verilog-sk-input
|
|
9965 "Insert an input definition."
|
|
9966 ()
|
|
9967 > "input [" (verilog-sk-datadef))
|
|
9968
|
|
9969 (define-skeleton verilog-sk-output
|
|
9970 "Insert an output definition."
|
|
9971 ()
|
|
9972 > "output [" (verilog-sk-datadef))
|
|
9973
|
|
9974 (define-skeleton verilog-sk-inout
|
|
9975 "Insert an inout definition."
|
|
9976 ()
|
|
9977 > "inout [" (verilog-sk-datadef))
|
|
9978
|
|
9979 (defvar verilog-sk-signal nil)
|
|
9980 (define-skeleton verilog-sk-def-reg
|
|
9981 "Insert a reg definition."
|
|
9982 ()
|
|
9983 > "reg [" (verilog-sk-prompt-width) | -1 verilog-sk-signal ";" \n (verilog-pretty-declarations) )
|
|
9984
|
|
9985 (defun verilog-sk-define-signal ()
|
|
9986 "Insert a definition of signal under point at top of module."
|
|
9987 (interactive "*")
|
|
9988 (let* (
|
|
9989 (sig-re "[a-zA-Z0-9_]*")
|
|
9990 (v1 (buffer-substring
|
|
9991 (save-excursion
|
|
9992 (skip-chars-backward sig-re)
|
|
9993 (point))
|
|
9994 (save-excursion
|
|
9995 (skip-chars-forward sig-re)
|
|
9996 (point))))
|
|
9997 )
|
|
9998 (if (not (member v1 verilog-keywords))
|
|
9999 (save-excursion
|
|
10000 (setq verilog-sk-signal v1)
|
|
10001 (verilog-beg-of-defun)
|
|
10002 (verilog-end-of-statement)
|
|
10003 (verilog-forward-syntactic-ws)
|
|
10004 (verilog-sk-def-reg)
|
|
10005 (message "signal at point is %s" v1))
|
|
10006 (message "object at point (%s) is a keyword" v1))
|
|
10007 )
|
|
10008 )
|
|
10009
|
|
10010
|
|
10011 (define-skeleton verilog-sk-wire
|
|
10012 "Insert a wire definition."
|
|
10013 ()
|
|
10014 > "wire [" (verilog-sk-datadef))
|
|
10015
|
|
10016 (define-skeleton verilog-sk-reg
|
|
10017 "Insert a reg definition."
|
|
10018 ()
|
|
10019 > "reg [" (verilog-sk-datadef))
|
|
10020
|
|
10021 (define-skeleton verilog-sk-assign
|
|
10022 "Insert a skeleton assign statement."
|
|
10023 ()
|
|
10024 > "assign " (verilog-sk-prompt-name) " = " _ ";" \n)
|
|
10025
|
|
10026 (define-skeleton verilog-sk-while
|
|
10027 "Insert a skeleton while loop statement."
|
|
10028 ()
|
|
10029 > "while (" (verilog-sk-prompt-condition) ") begin" \n
|
|
10030 > _ \n
|
|
10031 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
|
|
10032
|
|
10033 (define-skeleton verilog-sk-repeat
|
|
10034 "Insert a skeleton repeat loop statement."
|
|
10035 ()
|
|
10036 > "repeat (" (verilog-sk-prompt-condition) ") begin" \n
|
|
10037 > _ \n
|
|
10038 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
|
|
10039
|
|
10040 (define-skeleton verilog-sk-for
|
|
10041 "Insert a skeleton while loop statement."
|
|
10042 ()
|
|
10043 > "for ("
|
|
10044 (verilog-sk-prompt-init) "; "
|
|
10045 (verilog-sk-prompt-condition) "; "
|
|
10046 (verilog-sk-prompt-inc)
|
|
10047 ") begin" \n
|
|
10048 > _ \n
|
|
10049 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil))
|
|
10050
|
|
10051 (define-skeleton verilog-sk-comment
|
|
10052 "Inserts three comment lines, making a display comment."
|
|
10053 ()
|
|
10054 > "/*\n"
|
|
10055 > "* " _ \n
|
|
10056 > "*/")
|
|
10057
|
|
10058 (define-skeleton verilog-sk-state-machine
|
|
10059 "Insert a state machine definition."
|
|
10060 "Name of state variable: "
|
|
10061 '(setq input "state")
|
|
10062 > "// State registers for " str | -23 \n
|
|
10063 '(setq verilog-sk-state str)
|
|
10064 > "reg [" (verilog-sk-prompt-width) | -1 verilog-sk-state ", next_" verilog-sk-state ?; \n
|
|
10065 '(setq input nil)
|
|
10066 > \n
|
|
10067 > "// State FF for " verilog-sk-state \n
|
|
10068 > "always @ ( " (read-string "clock:" "posedge clk") " or " (verilog-sk-prompt-reset) " ) begin" \n
|
|
10069 > "if ( " verilog-sk-reset " ) " verilog-sk-state " = 0; else" \n
|
|
10070 > verilog-sk-state " = next_" verilog-sk-state ?; \n
|
|
10071 > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil)
|
|
10072 > \n
|
|
10073 > "// Next State Logic for " verilog-sk-state \n
|
|
10074 > "always @ ( /*AUTOSENSE*/ ) begin\n"
|
|
10075 > "case (" (verilog-sk-prompt-state-selector) ") " \n
|
|
10076 > ("case selector: " str ": begin" \n > "next_" verilog-sk-state " = " _ ";" \n > (- verilog-indent-level-behavioral) "end" \n )
|
|
10077 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil)
|
|
10078 > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil))
|
|
10079
|
|
10080 ;; Eliminate compile warning
|
|
10081 (eval-when-compile
|
|
10082 (if (not (boundp 'mode-popup-menu))
|
|
10083 (defvar mode-popup-menu nil "Compatibility with XEmacs.")))
|
|
10084
|
|
10085 ;; ---- add menu 'Statements' in Verilog mode (MH)
|
|
10086 (defun verilog-add-statement-menu ()
|
|
10087 "Add the menu 'Statements' to the menu bar in Verilog mode."
|
|
10088 (if (featurep 'xemacs)
|
|
10089 (progn
|
|
10090 (easy-menu-add verilog-stmt-menu)
|
|
10091 (easy-menu-add verilog-menu)
|
|
10092 (setq mode-popup-menu (cons "Verilog Mode" verilog-stmt-menu)))))
|
|
10093
|
|
10094 (add-hook 'verilog-mode-hook 'verilog-add-statement-menu)
|
|
10095
|
|
10096
|
|
10097
|
|
10098 ;;
|
|
10099 ;; Include file loading with mouse/return event
|
|
10100 ;;
|
|
10101 ;; idea & first impl.: M. Rouat (eldo-mode.el)
|
|
10102 ;; second (emacs/xemacs) impl.: G. Van der Plas (spice-mode.el)
|
|
10103
|
|
10104 (if (featurep 'xemacs)
|
|
10105 (require 'overlay)
|
|
10106 (require 'lucid)) ;; what else can we do ??
|
|
10107
|
|
10108 (defconst verilog-include-file-regexp
|
|
10109 "^`include\\s-+\"\\([^\n\"]*\\)\""
|
|
10110 "Regexp that matches the include file.")
|
|
10111
|
79546
|
10112 (defvar verilog-mode-mouse-map
|
79545
|
10113 (let ((map (make-sparse-keymap))) ; as described in info pages, make a map
|
|
10114 (set-keymap-parent map verilog-mode-map)
|
|
10115 ;; mouse button bindings
|
|
10116 (define-key map "\r" 'verilog-load-file-at-point)
|
|
10117 (if (featurep 'xemacs)
|
|
10118 (define-key map 'button2 'verilog-load-file-at-mouse);ffap-at-mouse ?
|
|
10119 (define-key map [mouse-2] 'verilog-load-file-at-mouse))
|
|
10120 (if (featurep 'xemacs)
|
|
10121 (define-key map 'Sh-button2 'mouse-yank) ; you wanna paste don't you ?
|
79546
|
10122 (define-key map [S-mouse-2] 'mouse-yank-at-click)))
|
|
10123 "Map containing mouse bindings for `verilog-mode'.")
|
|
10124
|
79545
|
10125
|
|
10126 ;; create set-extent-keymap procedure when it does not exist
|
|
10127 (eval-and-compile
|
|
10128 (unless (fboundp 'set-extent-keymap)
|
|
10129 (defun set-extent-keymap (extent keymap)
|
|
10130 "fallback version of set-extent-keymap (for emacs 2[01])"
|
|
10131 (set-extent-property extent 'local-map keymap))))
|
|
10132
|
|
10133 (defun verilog-colorize-include-files (beg end old-len)
|
|
10134 "This function colorizes included files when the mouse passes over them.
|
|
10135 Clicking on the middle-mouse button loads them in a buffer (as in dired)."
|
|
10136 (save-excursion
|
|
10137 (save-match-data
|
|
10138 (let (end-point)
|
|
10139 (goto-char end)
|
|
10140 (setq end-point (verilog-get-end-of-line))
|
|
10141 (goto-char beg)
|
|
10142 (beginning-of-line) ; scan entire line !
|
|
10143 ;; delete overlays existing on this line
|
|
10144 (let ((overlays (overlays-in (point) end-point)))
|
|
10145 (while overlays
|
|
10146 (if (and
|
|
10147 (overlay-get (car overlays) 'detachable)
|
|
10148 (overlay-get (car overlays) 'verilog-include-file))
|
|
10149 (delete-overlay (car overlays)))
|
|
10150 (setq overlays (cdr overlays)))) ; let
|
|
10151 ;; make new ones, could reuse deleted one ?
|
|
10152 (while (search-forward-regexp verilog-include-file-regexp end-point t)
|
|
10153 (let (extent)
|
|
10154 (goto-char (match-beginning 1))
|
|
10155 (or (extent-at (point) (buffer-name) 'mouse-face) ;; not yet extended
|
|
10156 (progn
|
|
10157 (setq extent (make-extent (match-beginning 1) (match-end 1)))
|
|
10158 (set-extent-property extent 'start-closed 't)
|
|
10159 (set-extent-property extent 'end-closed 't)
|
|
10160 (set-extent-property extent 'detachable 't)
|
|
10161 (set-extent-property extent 'verilog-include-file 't)
|
|
10162 (set-extent-property extent 'mouse-face 'highlight)
|
|
10163 (set-extent-keymap extent verilog-mode-mouse-map)))))))))
|
|
10164
|
|
10165
|
|
10166 (defun verilog-colorize-include-files-buffer ()
|
|
10167 "Colorize a include file."
|
|
10168 (interactive)
|
|
10169 ;; delete overlays
|
|
10170 (let ((overlays (overlays-in (point-min) (point-max))))
|
|
10171 (while overlays
|
|
10172 (if (and
|
|
10173 (overlay-get (car overlays) 'detachable)
|
|
10174 (overlay-get (car overlays) 'verilog-include-file))
|
|
10175 (delete-overlay (car overlays)))
|
|
10176 (setq overlays (cdr overlays)))) ; let
|
|
10177 ;; remake overlays
|
|
10178 (verilog-colorize-include-files (point-min) (point-max) nil))
|
|
10179
|
|
10180 ;; ffap-at-mouse isn't useful for verilog mode. It uses library paths.
|
|
10181 ;; so define this function to do more or less the same as ffap-at-mouse
|
|
10182 ;; but first resolve filename...
|
|
10183 (defun verilog-load-file-at-mouse (event)
|
|
10184 "Load file under button 2 click's EVENT.
|
|
10185 Files are checked based on `verilog-library-directories'."
|
|
10186 (interactive "@e")
|
|
10187 (save-excursion ;; implement a verilog specific ffap-at-mouse
|
|
10188 (mouse-set-point event)
|
|
10189 (beginning-of-line)
|
|
10190 (if (looking-at verilog-include-file-regexp)
|
|
10191 (if (and (car (verilog-library-filenames
|
|
10192 (match-string 1) (buffer-file-name)))
|
|
10193 (file-readable-p (car (verilog-library-filenames
|
|
10194 (match-string 1) (buffer-file-name)))))
|
|
10195 (find-file (car (verilog-library-filenames
|
|
10196 (match-string 1) (buffer-file-name))))
|
|
10197 (progn
|
|
10198 (message
|
|
10199 "File '%s' isn't readable, use shift-mouse2 to paste in this field"
|
|
10200 (match-string 1))))
|
|
10201 )))
|
|
10202
|
|
10203 ;; ffap isn't useable for verilog mode. It uses library paths.
|
|
10204 ;; so define this function to do more or less the same as ffap
|
|
10205 ;; but first resolve filename...
|
|
10206 (defun verilog-load-file-at-point ()
|
|
10207 "Load file under point.
|
|
10208 Files are checked based on `verilog-library-directories'."
|
|
10209 (interactive)
|
|
10210 (save-excursion ;; implement a verilog specific ffap
|
|
10211 (beginning-of-line)
|
|
10212 (if (looking-at verilog-include-file-regexp)
|
|
10213 (if (and
|
|
10214 (car (verilog-library-filenames
|
|
10215 (match-string 1) (buffer-file-name)))
|
|
10216 (file-readable-p (car (verilog-library-filenames
|
|
10217 (match-string 1) (buffer-file-name)))))
|
|
10218 (find-file (car (verilog-library-filenames
|
|
10219 (match-string 1) (buffer-file-name))))))
|
|
10220 ))
|
|
10221
|
|
10222
|
|
10223 ;;
|
|
10224 ;; Bug reporting
|
|
10225 ;;
|
|
10226
|
|
10227 (defun verilog-faq ()
|
|
10228 "Tell the user their current version, and where to get the FAQ etc."
|
|
10229 (interactive)
|
|
10230 (with-output-to-temp-buffer "*verilog-mode help*"
|
|
10231 (princ (format "You are using verilog-mode %s\n" verilog-mode-version))
|
|
10232 (princ "\n")
|
|
10233 (princ "For new releases, see http://www.verilog.com\n")
|
|
10234 (princ "\n")
|
|
10235 (princ "For frequently asked questions, see http://www.veripool.com/verilog-mode-faq.html\n")
|
|
10236 (princ "\n")
|
|
10237 (princ "To submit a bug, use M-x verilog-submit-bug-report\n")
|
|
10238 (princ "\n")))
|
|
10239
|
|
10240 (defun verilog-submit-bug-report ()
|
|
10241 "Submit via mail a bug report on verilog-mode.el."
|
|
10242 (interactive)
|
|
10243 (let ((reporter-prompt-for-summary-p t))
|
|
10244 (reporter-submit-bug-report
|
|
10245 "mac@verilog.com"
|
|
10246 (concat "verilog-mode v" verilog-mode-version)
|
|
10247 '(
|
|
10248 verilog-align-ifelse
|
|
10249 verilog-auto-endcomments
|
|
10250 verilog-auto-hook
|
|
10251 verilog-auto-indent-on-newline
|
|
10252 verilog-auto-inst-vector
|
|
10253 verilog-auto-inst-template-numbers
|
|
10254 verilog-auto-lineup
|
|
10255 verilog-auto-newline
|
|
10256 verilog-auto-save-policy
|
|
10257 verilog-auto-sense-defines-constant
|
|
10258 verilog-auto-sense-include-inputs
|
|
10259 verilog-before-auto-hook
|
|
10260 verilog-case-indent
|
|
10261 verilog-cexp-indent
|
|
10262 verilog-compiler
|
|
10263 verilog-coverage
|
|
10264 verilog-highlight-translate-off
|
|
10265 verilog-indent-begin-after-if
|
|
10266 verilog-indent-declaration-macros
|
|
10267 verilog-indent-level
|
|
10268 verilog-indent-level-behavioral
|
|
10269 verilog-indent-level-declaration
|
|
10270 verilog-indent-level-directive
|
|
10271 verilog-indent-level-module
|
|
10272 verilog-indent-lists
|
|
10273 verilog-library-flags
|
|
10274 verilog-library-directories
|
|
10275 verilog-library-extensions
|
|
10276 verilog-library-files
|
|
10277 verilog-linter
|
|
10278 verilog-minimum-comment-distance
|
|
10279 verilog-mode-hook
|
|
10280 verilog-simulator
|
|
10281 verilog-tab-always-indent
|
|
10282 verilog-tab-to-comment
|
|
10283 )
|
|
10284 nil nil
|
|
10285 (concat "Hi Mac,
|
|
10286
|
|
10287 I want to report a bug. I've read the `Bugs' section of `Info' on
|
|
10288 Emacs, so I know how to make a clear and unambiguous report. To get
|
|
10289 to that Info section, I typed
|
|
10290
|
|
10291 M-x info RET m " invocation-name " RET m bugs RET
|
|
10292
|
|
10293 Before I go further, I want to say that Verilog mode has changed my life.
|
|
10294 I save so much time, my files are colored nicely, my co workers respect
|
|
10295 my coding ability... until now. I'd really appreciate anything you
|
|
10296 could do to help me out with this minor deficiency in the product.
|
|
10297
|
|
10298 If you have bugs with the AUTO functions, please CC the AUTOAUTHOR Wilson
|
|
10299 Snyder (wsnyder@wsnyder.org) and/or see http://www.veripool.com.
|
|
10300 You may also want to look at the Verilog-Mode FAQ, see
|
|
10301 http://www.veripool.com/verilog-mode-faq.html.
|
|
10302
|
|
10303 To reproduce the bug, start a fresh Emacs via " invocation-name "
|
|
10304 -no-init-file -no-site-file'. In a new buffer, in verilog mode, type
|
|
10305 the code included below.
|
|
10306
|
|
10307 Given those lines, I expected [[Fill in here]] to happen;
|
|
10308 but instead, [[Fill in here]] happens!.
|
|
10309
|
|
10310 == The code: =="))))
|
|
10311
|
79546
|
10312 (provide 'verilog-mode)
|
|
10313
|
79545
|
10314 ;; Local Variables:
|
|
10315 ;; checkdoc-permit-comma-termination-flag:t
|
|
10316 ;; checkdoc-force-docstrings-flag:nil
|
|
10317 ;; End:
|
|
10318
|
|
10319 ;;; verilog-mode.el ends here
|