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annotate lisp/progmodes/verilog-mode.el @ 88071:1fcb6b1de8dc
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author | Michael Albinus <michael.albinus@gmx.de> |
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date | Tue, 29 Jan 2008 21:13:00 +0000 |
parents | 5d58981e6690 |
children | 5c60e04e322f |
rev | line source |
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79545 | 1 ;; verilog-mode.el --- major mode for editing verilog source in Emacs |
79551 | 2 |
3 ;; Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, | |
79717 | 4 ;; 2005, 2006, 2007, 2008 Free Software Foundation, Inc. |
79545 | 5 |
6 ;; Author: Michael McNamara (mac@verilog.com) | |
7 ;; http://www.verilog.com | |
8 ;; | |
9 ;; AUTO features, signal, modsig; by: Wilson Snyder | |
10 ;; (wsnyder@wsnyder.org) | |
11 ;; http://www.veripool.com | |
12 ;; Keywords: languages | |
13 | |
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14 ;; This code supports Emacs 21.1 and later |
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15 ;; And XEmacs 21.1 and later |
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16 ;; Please do not make changes that break Emacs 21. Thanks! |
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17 ;; |
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18 ;; |
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19 |
79551 | 20 ;; This file is part of GNU Emacs. |
21 | |
22 ;; GNU Emacs is free software; you can redistribute it and/or modify | |
79545 | 23 ;; it under the terms of the GNU General Public License as published by |
79551 | 24 ;; the Free Software Foundation; either version 3, or (at your option) |
25 ;; any later version. | |
26 | |
27 ;; GNU Emacs is distributed in the hope that it will be useful, | |
79545 | 28 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of |
29 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
30 ;; GNU General Public License for more details. | |
31 | |
32 ;; You should have received a copy of the GNU General Public License | |
79551 | 33 ;; along with GNU Emacs; see the file COPYING. If not, write to the |
34 ;; Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, | |
35 ;; Boston, MA 02110-1301, USA. | |
79545 | 36 |
37 ;;; Commentary: | |
38 | |
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39 ;; This mode borrows heavily from the Pascal-mode and the cc-mode of Emacs |
79545 | 40 |
41 ;; USAGE | |
42 ;; ===== | |
43 | |
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44 ;; A major mode for editing Verilog HDL source code. When you have |
79545 | 45 ;; entered Verilog mode, you may get more info by pressing C-h m. You |
46 ;; may also get online help describing various functions by: C-h f | |
47 ;; <Name of function you want described> | |
48 | |
49 ;; KNOWN BUGS / BUG REPORTS | |
50 ;; ======================= | |
51 | |
52 ;; Verilog is a rapidly evolving language, and hence this mode is | |
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53 ;; under continuous development. Hence this is beta code, and likely |
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54 ;; has bugs. Please report any and all bugs to me at mac@verilog.com. |
79545 | 55 ;; Please use verilog-submit-bug-report to submit a report; type C-c |
56 ;; C-b to invoke this and as a result I will have a much easier time | |
57 ;; of reproducing the bug you find, and hence fixing it. | |
58 | |
59 ;; INSTALLING THE MODE | |
60 ;; =================== | |
61 | |
62 ;; An older version of this mode may be already installed as a part of | |
63 ;; your environment, and one method of updating would be to update | |
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64 ;; your Emacs environment. Sometimes this is difficult for local |
79545 | 65 ;; political/control reasons, and hence you can always install a |
66 ;; private copy (or even a shared copy) which overrides the system | |
67 ;; default. | |
68 | |
69 ;; You can get step by step help in installing this file by going to | |
70 ;; <http://www.verilog.com/emacs_install.html> | |
71 | |
72 ;; The short list of installation instructions are: To set up | |
73 ;; automatic verilog mode, put this file in your load path, and put | |
74 ;; the following in code (please un comment it first!) in your | |
75 ;; .emacs, or in your site's site-load.el | |
76 | |
77 ; (autoload 'verilog-mode "verilog-mode" "Verilog mode" t ) | |
78 ; (setq auto-mode-alist (cons '("\\.v\\'" . verilog-mode) auto-mode-alist)) | |
79 ; (setq auto-mode-alist (cons '("\\.dv\\'" . verilog-mode) auto-mode-alist)) | |
80 | |
81 ;; If you want to customize Verilog mode to fit your needs better, | |
82 ;; you may add these lines (the values of the variables presented | |
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83 ;; here are the defaults). Note also that if you use an Emacs that |
79545 | 84 ;; supports custom, it's probably better to use the custom menu to |
85 ;; edit these. | |
86 ;; | |
87 ;; Be sure to examine at the help for verilog-auto, and the other | |
88 ;; verilog-auto-* functions for some major coding time savers. | |
89 ;; | |
90 ; ;; User customization for Verilog mode | |
91 ; (setq verilog-indent-level 3 | |
92 ; verilog-indent-level-module 3 | |
93 ; verilog-indent-level-declaration 3 | |
94 ; verilog-indent-level-behavioral 3 | |
95 ; verilog-indent-level-directive 1 | |
96 ; verilog-case-indent 2 | |
97 ; verilog-auto-newline t | |
98 ; verilog-auto-indent-on-newline t | |
99 ; verilog-tab-always-indent t | |
100 ; verilog-auto-endcomments t | |
101 ; verilog-minimum-comment-distance 40 | |
102 ; verilog-indent-begin-after-if t | |
103 ; verilog-auto-lineup '(all) | |
104 ; verilog-highlight-p1800-keywords nil | |
105 ; verilog-linter "my_lint_shell_command" | |
106 ; ) | |
107 | |
108 ;; | |
109 | |
110 ;;; History: | |
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111 ;; |
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112 ;; See commit history at http://www.veripool.com/verilog-mode.html |
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113 ;; (This section is required to appease checkdoc.) |
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114 |
79545 | 115 ;;; Code: |
116 | |
117 ;; This variable will always hold the version number of the mode | |
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118 (defconst verilog-mode-version "383" |
79545 | 119 "Version of this verilog mode.") |
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120 (defconst verilog-mode-release-date "2008-01-07-GNU" |
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121 "Release date of this verilog mode.") |
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122 (defconst verilog-mode-release-emacs t |
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123 "If non-nil, this version of verilog mode was released with Emacs itself.") |
79545 | 124 |
125 (defun verilog-version () | |
126 "Inform caller of the version of this file." | |
127 (interactive) | |
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128 (message "Using verilog-mode version %s" verilog-mode-version)) |
79545 | 129 |
130 ;; Insure we have certain packages, and deal with it if we don't | |
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131 ;; Be sure to note which Emacs flavor and version added each feature. |
79546 | 132 (eval-when-compile |
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133 ;; The below were disabled when GNU Emacs 22 was released; |
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134 ;; perhaps some still need to be there to support Emacs 21. |
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135 (when (featurep 'xemacs) |
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136 (condition-case nil |
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137 (require 'easymenu) |
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138 (error nil)) |
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139 (condition-case nil |
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140 (require 'regexp-opt) |
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141 (error nil)) |
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142 ;; Bug in 19.28 through 19.30 skeleton.el, not provided. |
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143 (condition-case nil |
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144 (load "skeleton") |
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145 (error nil)) |
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146 (condition-case nil |
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147 (if (fboundp 'when) |
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148 nil ;; fab |
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149 (defmacro when (cond &rest body) |
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150 (list 'if cond (cons 'progn body)))) |
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151 (error nil)) |
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152 (condition-case nil |
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153 (if (fboundp 'unless) |
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154 nil ;; fab |
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155 (defmacro unless (cond &rest body) |
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156 (cons 'if (cons cond (cons nil body))))) |
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157 (error nil)) |
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158 (condition-case nil |
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159 (if (fboundp 'store-match-data) |
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160 nil ;; fab |
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161 (defmacro store-match-data (&rest args) nil)) |
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162 (error nil)) |
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163 (condition-case nil |
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164 (if (boundp 'current-menubar) |
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165 nil ;; great |
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166 (progn |
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167 (defmacro add-submenu (&rest args) nil)) |
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168 ) |
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169 (error nil)) |
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170 (condition-case nil |
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171 (if (fboundp 'char-before) |
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172 nil ;; great |
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173 (defmacro char-before (&rest body) |
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174 (char-after (1- (point))))) |
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175 (error nil)) |
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176 (condition-case nil |
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177 (require 'custom) |
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178 (error nil)) |
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179 (condition-case nil |
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180 (if (fboundp 'match-string-no-properties) |
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181 nil ;; great |
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182 (defsubst match-string-no-properties (num &optional string) |
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183 "Return string of text matched by last search, without text properties. |
79545 | 184 NUM specifies which parenthesized expression in the last regexp. |
185 Value is nil if NUMth pair didn't match, or there were less than NUM pairs. | |
186 Zero means the entire text matched by the whole regexp or whole string. | |
187 STRING should be given if the last search was by `string-match' on STRING." | |
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188 (if (match-beginning num) |
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189 (if string |
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190 (let ((result |
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191 (substring string |
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192 (match-beginning num) (match-end num)))) |
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193 (set-text-properties 0 (length result) nil result) |
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194 result) |
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195 (buffer-substring-no-properties (match-beginning num) |
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196 (match-end num) |
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197 (current-buffer))))) |
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198 ) |
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199 (error nil)) |
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200 (if (and (featurep 'custom) (fboundp 'custom-declare-variable)) |
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201 nil ;; We've got what we needed |
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202 ;; We have the old custom-library, hack around it! |
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203 (defmacro defgroup (&rest args) nil) |
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204 (defmacro customize (&rest args) |
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205 (message |
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206 "Sorry, Customize is not available with this version of emacs")) |
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207 (defmacro defcustom (var value doc &rest args) |
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208 `(defvar ,var ,value ,doc)) |
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209 ) |
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210 (if (fboundp 'defface) |
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211 nil ; great! |
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212 (defmacro defface (var values doc &rest args) |
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213 `(make-face ,var)) |
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214 ) |
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215 |
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216 (if (and (featurep 'custom) (fboundp 'customize-group)) |
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217 nil ;; We've got what we needed |
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218 ;; We have an intermediate custom-library, hack around it! |
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219 (defmacro customize-group (var &rest args) |
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220 `(customize ,var)) |
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221 ))) |
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222 |
79545 | 223 ;; Provide a regular expression optimization routine, using regexp-opt |
224 ;; if provided by the user's elisp libraries | |
225 (eval-and-compile | |
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226 ;; The below were disabled when GNU Emacs 22 was released; |
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227 ;; perhaps some still need to be there to support Emacs 21. |
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228 (if (featurep 'xemacs) |
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229 (if (fboundp 'regexp-opt) |
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230 ;; regexp-opt is defined, does it take 3 or 2 arguments? |
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231 (if (fboundp 'function-max-args) |
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232 (let ((args (function-max-args `regexp-opt))) |
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233 (cond |
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234 ((eq args 3) ;; It takes 3 |
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235 (condition-case nil ; Hide this defun from emacses |
79545 | 236 ;with just a two input regexp |
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237 (defun verilog-regexp-opt (a b) |
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238 "Deal with differing number of required arguments for `regexp-opt'. |
79545 | 239 Call 'regexp-opt' on A and B." |
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240 (regexp-opt a b 't)) |
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241 (error nil)) |
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242 ) |
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243 ((eq args 2) ;; It takes 2 |
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244 (defun verilog-regexp-opt (a b) |
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245 "Call 'regexp-opt' on A and B." |
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246 (regexp-opt a b)) |
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247 ) |
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248 (t nil))) |
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249 ;; We can't tell; assume it takes 2 |
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250 (defun verilog-regexp-opt (a b) |
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251 "Call 'regexp-opt' on A and B." |
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252 (regexp-opt a b)) |
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253 ) |
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254 ;; There is no regexp-opt, provide our own |
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255 (defun verilog-regexp-opt (strings &optional paren shy) |
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256 (let ((open (if paren "\\(" "")) (close (if paren "\\)" ""))) |
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257 (concat open (mapconcat 'regexp-quote strings "\\|") close))) |
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258 ) |
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259 ;; Emacs. |
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260 (defalias 'verilog-regexp-opt 'regexp-opt))) |
79545 | 261 |
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262 (eval-when-compile |
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263 (defun verilog-regexp-words (a) |
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264 "Call 'regexp-opt' with word delimiters for the words A." |
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265 (concat "\\<" (verilog-regexp-opt a t) "\\>"))) |
79545 | 266 |
267 (defun verilog-customize () | |
268 "Link to customize screen for Verilog." | |
269 (interactive) | |
270 (customize-group 'verilog-mode)) | |
271 | |
272 (defun verilog-font-customize () | |
273 "Link to customize fonts used for Verilog." | |
274 (interactive) | |
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275 (if (fboundp 'customize-apropos) |
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276 (customize-apropos "font-lock-*" 'faces))) |
79545 | 277 |
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278 (defun verilog-booleanp (value) |
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279 "Return t if VALUE is boolean. |
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280 This implements GNU Emacs 22.1's `booleanp' function in earlier Emacs. |
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281 This function may be removed when Emacs 21 is no longer supported." |
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282 (or (equal value t) (equal value nil))) |
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283 |
79545 | 284 (defgroup verilog-mode nil |
285 "Facilitates easy editing of Verilog source text" | |
286 :group 'languages) | |
287 | |
288 ; (defgroup verilog-mode-fonts nil | |
289 ; "Facilitates easy customization fonts used in Verilog source text" | |
290 ; :link '(customize-apropos "font-lock-*" 'faces) | |
291 ; :group 'verilog-mode) | |
292 | |
293 (defgroup verilog-mode-indent nil | |
294 "Customize indentation and highlighting of verilog source text" | |
295 :group 'verilog-mode) | |
296 | |
297 (defgroup verilog-mode-actions nil | |
298 "Customize actions on verilog source text" | |
299 :group 'verilog-mode) | |
300 | |
301 (defgroup verilog-mode-auto nil | |
302 "Customize AUTO actions when expanding verilog source text" | |
303 :group 'verilog-mode) | |
304 | |
305 (defcustom verilog-linter | |
306 "echo 'No verilog-linter set, see \"M-x describe-variable verilog-linter\"'" | |
307 "*Unix program and arguments to call to run a lint checker on verilog source. | |
308 Depending on the `verilog-set-compile-command', this may be invoked when | |
309 you type \\[compile]. When the compile completes, \\[next-error] will take | |
310 you to the next lint error." | |
311 :type 'string | |
312 :group 'verilog-mode-actions) | |
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313 ;; We don't mark it safe, as it's used as a shell command |
79545 | 314 |
315 (defcustom verilog-coverage | |
316 "echo 'No verilog-coverage set, see \"M-x describe-variable verilog-coverage\"'" | |
317 "*Program and arguments to use to annotate for coverage verilog source. | |
318 Depending on the `verilog-set-compile-command', this may be invoked when | |
319 you type \\[compile]. When the compile completes, \\[next-error] will take | |
320 you to the next lint error." | |
321 :type 'string | |
322 :group 'verilog-mode-actions) | |
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323 ;; We don't mark it safe, as it's used as a shell command |
79545 | 324 |
325 (defcustom verilog-simulator | |
326 "echo 'No verilog-simulator set, see \"M-x describe-variable verilog-simulator\"'" | |
327 "*Program and arguments to use to interpret verilog source. | |
328 Depending on the `verilog-set-compile-command', this may be invoked when | |
329 you type \\[compile]. When the compile completes, \\[next-error] will take | |
330 you to the next lint error." | |
331 :type 'string | |
332 :group 'verilog-mode-actions) | |
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333 ;; We don't mark it safe, as it's used as a shell command |
79545 | 334 |
335 (defcustom verilog-compiler | |
336 "echo 'No verilog-compiler set, see \"M-x describe-variable verilog-compiler\"'" | |
337 "*Program and arguments to use to compile verilog source. | |
338 Depending on the `verilog-set-compile-command', this may be invoked when | |
339 you type \\[compile]. When the compile completes, \\[next-error] will take | |
340 you to the next lint error." | |
341 :type 'string | |
342 :group 'verilog-mode-actions) | |
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343 ;; We don't mark it safe, as it's used as a shell command |
79545 | 344 |
345 (defvar verilog-tool 'verilog-linter | |
346 "Which tool to use for building compiler-command. | |
347 Either nil, `verilog-linter, `verilog-coverage, `verilog-simulator, or | |
348 `verilog-compiler. Alternatively use the \"Choose Compilation Action\" | |
349 menu. See `verilog-set-compile-command' for more information.") | |
350 | |
351 (defcustom verilog-highlight-translate-off nil | |
352 "*Non-nil means background-highlight code excluded from translation. | |
353 That is, all code between \"// synopsys translate_off\" and | |
354 \"// synopsys translate_on\" is highlighted using a different background color | |
355 \(face `verilog-font-lock-translate-off-face'). | |
356 | |
357 Note: This will slow down on-the-fly fontification (and thus editing). | |
358 | |
359 Note: Activate the new setting in a Verilog buffer by re-fontifying it (menu | |
360 entry \"Fontify Buffer\"). XEmacs: turn off and on font locking." | |
361 :type 'boolean | |
362 :group 'verilog-mode-indent) | |
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363 ;; Note we don't use :safe, as that would break on Emacsen before 22.0. |
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364 (put 'verilog-highlight-translate-off 'safe-local-variable 'verilog-booleanp) |
79545 | 365 |
366 (defcustom verilog-indent-level 3 | |
367 "*Indentation of Verilog statements with respect to containing block." | |
368 :group 'verilog-mode-indent | |
369 :type 'integer) | |
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370 (put 'verilog-indent-level 'safe-local-variable 'integerp) |
79545 | 371 |
372 (defcustom verilog-indent-level-module 3 | |
373 "*Indentation of Module level Verilog statements. (eg always, initial) | |
374 Set to 0 to get initial and always statements lined up on the left side of | |
375 your screen." | |
376 :group 'verilog-mode-indent | |
377 :type 'integer) | |
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378 (put 'verilog-indent-level-module 'safe-local-variable 'integerp) |
79545 | 379 |
380 (defcustom verilog-indent-level-declaration 3 | |
381 "*Indentation of declarations with respect to containing block. | |
382 Set to 0 to get them list right under containing block." | |
383 :group 'verilog-mode-indent | |
384 :type 'integer) | |
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385 (put 'verilog-indent-level-declaration 'safe-local-variable 'integerp) |
79545 | 386 |
387 (defcustom verilog-indent-declaration-macros nil | |
388 "*How to treat macro expansions in a declaration. | |
389 If nil, indent as: | |
390 input [31:0] a; | |
391 input `CP; | |
392 output c; | |
393 If non nil, treat as: | |
394 input [31:0] a; | |
395 input `CP ; | |
396 output c;" | |
397 :group 'verilog-mode-indent | |
398 :type 'boolean) | |
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399 (put 'verilog-indent-declaration-macros 'safe-local-variable 'verilog-booleanp) |
79545 | 400 |
401 (defcustom verilog-indent-lists t | |
402 "*How to treat indenting items in a list. | |
403 If t (the default), indent as: | |
404 always @( posedge a or | |
405 reset ) begin | |
406 | |
407 If nil, treat as: | |
408 always @( posedge a or | |
409 reset ) begin" | |
410 :group 'verilog-mode-indent | |
411 :type 'boolean) | |
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412 (put 'verilog-indent-lists 'safe-local-variable 'verilog-booleanp) |
79545 | 413 |
414 (defcustom verilog-indent-level-behavioral 3 | |
415 "*Absolute indentation of first begin in a task or function block. | |
416 Set to 0 to get such code to start at the left side of the screen." | |
417 :group 'verilog-mode-indent | |
418 :type 'integer) | |
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419 (put 'verilog-indent-level-behavioral 'safe-local-variable 'integerp) |
79545 | 420 |
421 (defcustom verilog-indent-level-directive 1 | |
422 "*Indentation to add to each level of `ifdef declarations. | |
423 Set to 0 to have all directives start at the left side of the screen." | |
424 :group 'verilog-mode-indent | |
425 :type 'integer) | |
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426 (put 'verilog-indent-level-directive 'safe-local-variable 'integerp) |
79545 | 427 |
428 (defcustom verilog-cexp-indent 2 | |
429 "*Indentation of Verilog statements split across lines." | |
430 :group 'verilog-mode-indent | |
431 :type 'integer) | |
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432 (put 'verilog-cexp-indent 'safe-local-variable 'integerp) |
79545 | 433 |
434 (defcustom verilog-case-indent 2 | |
435 "*Indentation for case statements." | |
436 :group 'verilog-mode-indent | |
437 :type 'integer) | |
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438 (put 'verilog-case-indent 'safe-local-variable 'integerp) |
79545 | 439 |
440 (defcustom verilog-auto-newline t | |
441 "*True means automatically newline after semicolons." | |
442 :group 'verilog-mode-indent | |
443 :type 'boolean) | |
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444 (put 'verilog-auto-newline 'safe-local-variable 'verilog-booleanp) |
79545 | 445 |
446 (defcustom verilog-auto-indent-on-newline t | |
447 "*True means automatically indent line after newline." | |
448 :group 'verilog-mode-indent | |
449 :type 'boolean) | |
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450 (put 'verilog-auto-indent-on-newline 'safe-local-variable 'verilog-booleanp) |
79545 | 451 |
452 (defcustom verilog-tab-always-indent t | |
453 "*True means TAB should always re-indent the current line. | |
454 Nil means TAB will only reindent when at the beginning of the line." | |
455 :group 'verilog-mode-indent | |
456 :type 'boolean) | |
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457 (put 'verilog-tab-always-indent 'safe-local-variable 'verilog-booleanp) |
79545 | 458 |
459 (defcustom verilog-tab-to-comment nil | |
460 "*True means TAB moves to the right hand column in preparation for a comment." | |
461 :group 'verilog-mode-actions | |
462 :type 'boolean) | |
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463 (put 'verilog-tab-to-comment 'safe-local-variable 'verilog-booleanp) |
79545 | 464 |
465 (defcustom verilog-indent-begin-after-if t | |
466 "*If true, indent begin statements following if, else, while, for and repeat. | |
467 Otherwise, line them up." | |
468 :group 'verilog-mode-indent | |
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469 :type 'boolean) |
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470 (put 'verilog-indent-begin-after-if 'safe-local-variable 'verilog-booleanp) |
79545 | 471 |
472 | |
473 (defcustom verilog-align-ifelse nil | |
474 "*If true, align `else' under matching `if'. | |
475 Otherwise else is lined up with first character on line holding matching if." | |
476 :group 'verilog-mode-indent | |
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477 :type 'boolean) |
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478 (put 'verilog-align-ifelse 'safe-local-variable 'verilog-booleanp) |
79545 | 479 |
480 (defcustom verilog-minimum-comment-distance 10 | |
481 "*Minimum distance (in lines) between begin and end required before a comment. | |
482 Setting this variable to zero results in every end acquiring a comment; the | |
483 default avoids too many redundant comments in tight quarters" | |
484 :group 'verilog-mode-indent | |
485 :type 'integer) | |
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486 (put 'verilog-minimum-comment-distance 'safe-local-variable 'integerp) |
79545 | 487 |
488 (defcustom verilog-auto-lineup '(declaration) | |
489 "*Algorithm for lining up statements on multiple lines. | |
490 | |
491 If this list contains the symbol 'all', then all line ups described below | |
492 are done. | |
493 | |
494 If this list contains the symbol 'declaration', then declarations are lined up | |
495 with any preceding declarations, taking into account widths and the like, so | |
496 for example the code: | |
497 reg [31:0] a; | |
498 reg b; | |
499 would become | |
500 reg [31:0] a; | |
501 reg b; | |
502 | |
503 If this list contains the symbol 'assignment', then assignments are lined up | |
504 with any preceding assignments, so for example the code | |
505 a_long_variable = b + c; | |
506 d = e + f; | |
507 would become | |
508 a_long_variable = b + c; | |
509 d = e + f;" | |
510 | |
511 ;; The following is not implemented: | |
512 ;If this list contains the symbol 'case', then case items are lined up | |
513 ;with any preceding case items, so for example the code | |
514 ; case (a) begin | |
515 ; a_long_state : a = 3; | |
516 ; b: a = 4; | |
517 ; endcase | |
518 ;would become | |
519 ; case (a) begin | |
520 ; a_long_state : a = 3; | |
521 ; b : a = 4; | |
522 ; endcase | |
523 ; | |
524 | |
525 :group 'verilog-mode-indent | |
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526 :type 'list) |
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527 (put 'verilog-auto-lineup 'safe-local-variable 'listp) |
79545 | 528 |
529 (defcustom verilog-highlight-p1800-keywords nil | |
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530 "*True means highlight words newly reserved by IEEE-1800. |
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531 These will appear in `verilog-font-lock-p1800-face' in order to gently |
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532 suggest changing where these words are used as variables to something else. |
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533 Nil means highlight these words as appropriate for the SystemVerilog |
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534 IEEE-1800 standard. Note that changing this will require restarting Emacs |
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535 to see the effect as font color choices are cached by Emacs" |
79545 | 536 :group 'verilog-mode-indent |
537 :type 'boolean) | |
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538 (put 'verilog-highlight-p1800-keywords 'safe-local-variable 'verilog-booleanp) |
79545 | 539 |
540 (defcustom verilog-auto-endcomments t | |
541 "*True means insert a comment /* ... */ after 'end's. | |
542 The name of the function or case will be set between the braces." | |
543 :group 'verilog-mode-actions | |
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544 :type 'boolean) |
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545 (put 'verilog-auto-endcomments 'safe-local-variable 'verilog-booleanp) |
79545 | 546 |
547 (defcustom verilog-auto-read-includes nil | |
548 "*True means to automatically read includes before AUTOs. | |
549 This will do a `verilog-read-defines' and `verilog-read-includes' before | |
550 each AUTO expansion. This makes it easier to embed defines and includes, | |
551 but can result in very slow reading times if there are many or large | |
552 include files." | |
553 :group 'verilog-mode-actions | |
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554 :type 'boolean) |
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555 (put 'verilog-auto-read-includes 'safe-local-variable 'verilog-booleanp) |
79545 | 556 |
557 (defcustom verilog-auto-save-policy nil | |
558 "*Non-nil indicates action to take when saving a Verilog buffer with AUTOs. | |
559 A value of `force' will always do a \\[verilog-auto] automatically if | |
560 needed on every save. A value of `detect' will do \\[verilog-auto] | |
561 automatically when it thinks necessary. A value of `ask' will query the | |
562 user when it thinks updating is needed. | |
563 | |
564 You should not rely on the 'ask or 'detect policies, they are safeguards | |
565 only. They do not detect when AUTOINSTs need to be updated because a | |
566 sub-module's port list has changed." | |
567 :group 'verilog-mode-actions | |
568 :type '(choice (const nil) (const ask) (const detect) (const force))) | |
569 | |
570 (defcustom verilog-auto-star-expand t | |
571 "*Non-nil indicates to expand a SystemVerilog .* instance ports. | |
572 They will be expanded in the same way as if there was a AUTOINST in the | |
573 instantiation. See also `verilog-auto-star' and `verilog-auto-star-save'." | |
574 :group 'verilog-mode-actions | |
575 :type 'boolean) | |
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576 (put 'verilog-auto-star-expand 'safe-local-variable 'verilog-booleanp) |
79545 | 577 |
578 (defcustom verilog-auto-star-save nil | |
579 "*Non-nil indicates to save to disk SystemVerilog .* instance expansions. | |
580 Nil indicates direct connections will be removed before saving. Only | |
581 meaningful to those created due to `verilog-auto-star-expand' being set. | |
582 | |
583 Instead of setting this, you may want to use /*AUTOINST*/, which will | |
584 always be saved." | |
585 :group 'verilog-mode-actions | |
586 :type 'boolean) | |
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587 (put 'verilog-auto-star-save 'safe-local-variable 'verilog-booleanp) |
79545 | 588 |
589 (defvar verilog-auto-update-tick nil | |
590 "Modification tick at which autos were last performed.") | |
591 | |
592 (defvar verilog-auto-last-file-locals nil | |
593 "Text from file-local-variables during last evaluation.") | |
594 | |
595 (defvar verilog-error-regexp-add-didit nil) | |
596 (defvar verilog-error-regexp nil) | |
597 (setq verilog-error-regexp-add-didit nil | |
598 verilog-error-regexp | |
599 '( | |
600 ; SureLint | |
601 ;; ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 2) | |
602 ; Most SureFire tools | |
603 ("\\(WARNING\\|ERROR\\|INFO\\)[^:]*: \\([^,]+\\), \\(line \\|\\)\\([0-9]+\\):" 2 4 ) | |
604 ("\ | |
605 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\ | |
606 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 2 5) | |
607 ; xsim | |
608 ; Error! in file /homes/mac/Axis/Xsim/test.v at line 13 [OBJ_NOT_DECLARED] | |
609 ("\\(Error\\|Warning\\).*in file (\\([^ \t]+\\) at line *\\([0-9]+\\))" 2 3) | |
610 ; vcs | |
611 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 3) | |
612 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 2) | |
613 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 3) | |
614 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 2) | |
615 ; Verilator | |
616 ("%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 4) | |
617 ("%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 4) | |
618 ; vxl | |
619 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 3) | |
620 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\([0-9]+\\):.*$" 1 2) ; vxl | |
621 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+line[ \t]+\\([0-9]+\\):.*$" 1 2) | |
622 ; nc-verilog | |
623 (".*\\*[WE],[0-9A-Z]+ (\\([^ \t,]+\\),\\([0-9]+\\)|" 1 2) | |
624 ; Leda | |
625 ("In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\[\\(Warning\\|Error\\|Failure\\)\\][^\n]*" 1 2) | |
626 ) | |
627 ; "*List of regexps for verilog compilers, like verilint. See compilation-error-regexp-alist for the formatting." | |
628 ) | |
629 | |
630 (defvar verilog-error-font-lock-keywords | |
631 '( | |
632 ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 1 bold t) | |
633 ("[^\n]*\\[\\([^:]+\\):\\([0-9]+\\)\\]" 2 bold t) | |
634 | |
635 ("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 2 bold t) | |
636 ("\\(WARNING\\|ERROR\\|INFO\\): \\([^,]+\\), line \\([0-9]+\\):" 3 bold t) | |
637 | |
638 ("\ | |
639 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\ | |
640 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 bold t) | |
641 ("\ | |
642 \\([a-zA-Z]?:?[^:( \t\n]+\\)[:(][ \t]*\\([0-9]+\\)\\([) \t]\\|\ | |
643 :\\([^0-9\n]\\|\\([0-9]+:\\)\\)\\)" 1 bold t) | |
644 | |
645 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 2 bold t) | |
646 ("\\(Error\\|Warning\\):[^(]*(\\([^ \t]+\\) line *\\([0-9]+\\))" 3 bold t) | |
647 | |
648 ("%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 3 bold t) | |
649 ("%?\\(Error\\|Warning\\)\\(-[^:]+\\|\\):[\n ]*\\([^ \t:]+\\):\\([0-9]+\\):" 4 bold t) | |
650 | |
651 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t) | |
652 ("Warning:.*(port.*(\\([^ \t]+\\) line \\([0-9]+\\))" 1 bold t) | |
653 | |
654 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 2 bold t) | |
655 ("\\(Error\\|Warning\\):[\n.]*\\([^ \t]+\\) *\\([0-9]+\\):" 3 bold t) | |
656 | |
657 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 1 bold t) | |
658 ("syntax error:.*\n\\([^ \t]+\\) *\\([0-9]+\\):" 2 bold t) | |
659 ; vxl | |
660 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 bold t) | |
661 ("\\(Error\\|Warning\\)!.*\n?.*\"\\([^\"]+\\)\", \\([0-9]+\\)" 2 bold t) | |
662 | |
663 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\([0-9]+\\):.*$" 1 bold t) | |
664 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+\\([0-9]+\\):.*$" 2 bold t) | |
665 | |
666 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+line[ \t]+\\([0-9]+\\):.*$" 1 bold t) | |
667 ("([WE][0-9A-Z]+)[ \t]+\\([^ \t\n,]+\\)[, \t]+line[ \t]+\\([0-9]+\\):.*$" 2 bold t) | |
668 ; nc-verilog | |
669 (".*[WE],[0-9A-Z]+ (\\([^ \t,]+\\),\\([0-9]+\\)|" 1 bold t) | |
670 (".*[WE],[0-9A-Z]+ (\\([^ \t,]+\\),\\([0-9]+\\)|" 2 bold t) | |
671 ; Leda | |
672 ("In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\[\\(Warning\\|Error\\|Failure\\)\\][^\n]*" 1 bold t) | |
673 ("In file \\([^ \t]+\\)[ \t]+line[ \t]+\\([0-9]+\\):\n[^\n]*\n[^\n]*\n\\[\\(Warning\\|Error\\|Failure\\)\\][^\n]*" 2 bold t) | |
674 ) | |
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675 "*Keywords to also highlight in Verilog *compilation* buffers.") |
79545 | 676 |
677 (defcustom verilog-library-flags '("") | |
678 "*List of standard Verilog arguments to use for /*AUTOINST*/. | |
679 These arguments are used to find files for `verilog-auto', and match | |
680 the flags accepted by a standard Verilog-XL simulator. | |
681 | |
682 -f filename Reads more `verilog-library-flags' from the filename. | |
683 +incdir+dir Adds the directory to `verilog-library-directories'. | |
684 -Idir Adds the directory to `verilog-library-directories'. | |
685 -y dir Adds the directory to `verilog-library-directories'. | |
686 +libext+.v Adds the extensions to `verilog-library-extensions'. | |
687 -v filename Adds the filename to `verilog-library-files'. | |
688 | |
689 filename Adds the filename to `verilog-library-files'. | |
690 This is not recommended, -v is a better choice. | |
691 | |
692 You might want these defined in each file; put at the *END* of your file | |
693 something like: | |
694 | |
695 // Local Variables: | |
696 // verilog-library-flags:(\"-y dir -y otherdir\") | |
697 // End: | |
698 | |
699 Verilog-mode attempts to detect changes to this local variable, but they | |
700 are only insured to be correct when the file is first visited. Thus if you | |
701 have problems, use \\[find-alternate-file] RET to have these take effect. | |
702 | |
703 See also the variables mentioned above." | |
704 :group 'verilog-mode-auto | |
705 :type '(repeat string)) | |
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706 (put 'verilog-library-flags 'safe-local-variable 'listp) |
79545 | 707 |
708 (defcustom verilog-library-directories '(".") | |
709 "*List of directories when looking for files for /*AUTOINST*/. | |
710 The directory may be relative to the current file, or absolute. | |
711 Environment variables are also expanded in the directory names. | |
712 Having at least the current directory is a good idea. | |
713 | |
714 You might want these defined in each file; put at the *END* of your file | |
715 something like: | |
716 | |
717 // Local Variables: | |
718 // verilog-library-directories:(\".\" \"subdir\" \"subdir2\") | |
719 // End: | |
720 | |
721 Verilog-mode attempts to detect changes to this local variable, but they | |
722 are only insured to be correct when the file is first visited. Thus if you | |
723 have problems, use \\[find-alternate-file] RET to have these take effect. | |
724 | |
725 See also `verilog-library-flags', `verilog-library-files' | |
726 and `verilog-library-extensions'." | |
727 :group 'verilog-mode-auto | |
728 :type '(repeat file)) | |
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729 (put 'verilog-library-directories 'safe-local-variable 'listp) |
79545 | 730 |
731 (defcustom verilog-library-files '() | |
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732 "*List of files to search for modules. |
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733 AUTOINST will use this when it needs to resolve a module name. |
79545 | 734 This is a complete path, usually to a technology file with many standard |
735 cells defined in it. | |
736 | |
737 You might want these defined in each file; put at the *END* of your file | |
738 something like: | |
739 | |
740 // Local Variables: | |
741 // verilog-library-files:(\"/some/path/technology.v\" \"/some/path/tech2.v\") | |
742 // End: | |
743 | |
744 Verilog-mode attempts to detect changes to this local variable, but they | |
745 are only insured to be correct when the file is first visited. Thus if you | |
746 have problems, use \\[find-alternate-file] RET to have these take effect. | |
747 | |
748 See also `verilog-library-flags', `verilog-library-directories'." | |
749 :group 'verilog-mode-auto | |
750 :type '(repeat directory)) | |
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751 (put 'verilog-library-files 'safe-local-variable 'listp) |
79545 | 752 |
753 (defcustom verilog-library-extensions '(".v") | |
754 "*List of extensions to use when looking for files for /*AUTOINST*/. | |
755 See also `verilog-library-flags', `verilog-library-directories'." | |
756 :type '(repeat string) | |
757 :group 'verilog-mode-auto) | |
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758 (put 'verilog-library-extensions 'safe-local-variable 'listp) |
79545 | 759 |
760 (defcustom verilog-active-low-regexp nil | |
761 "*If set, treat signals matching this regexp as active low. | |
762 This is used for AUTORESET and AUTOTIEOFF. For proper behavior, | |
763 you will probably also need `verilog-auto-reset-widths' set." | |
764 :group 'verilog-mode-auto | |
765 :type 'string) | |
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766 (put 'verilog-active-low-regexp 'safe-local-variable 'stringp) |
79545 | 767 |
768 (defcustom verilog-auto-sense-include-inputs nil | |
769 "*If true, AUTOSENSE should include all inputs. | |
770 If nil, only inputs that are NOT output signals in the same block are | |
771 included." | |
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772 :group 'verilog-mode-auto |
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773 :type 'boolean) |
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774 (put 'verilog-auto-sense-include-inputs 'safe-local-variable 'verilog-booleanp) |
79545 | 775 |
776 (defcustom verilog-auto-sense-defines-constant nil | |
777 "*If true, AUTOSENSE should assume all defines represent constants. | |
778 When true, the defines will not be included in sensitivity lists. To | |
779 maintain compatibility with other sites, this should be set at the bottom | |
780 of each verilog file that requires it, rather than being set globally." | |
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781 :group 'verilog-mode-auto |
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782 :type 'boolean) |
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783 (put 'verilog-auto-sense-defines-constant 'safe-local-variable 'verilog-booleanp) |
79545 | 784 |
785 (defcustom verilog-auto-reset-widths t | |
786 "*If true, AUTORESET should determine the width of signals. | |
787 This is then used to set the width of the zero (32'h0 for example). This | |
788 is required by some lint tools that aren't smart enough to ignore widths of | |
789 the constant zero. This may result in ugly code when parameters determine | |
790 the MSB or LSB of a signal inside a AUTORESET." | |
791 :type 'boolean | |
792 :group 'verilog-mode-auto) | |
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793 (put 'verilog-auto-reset-widths 'safe-local-variable 'verilog-booleanp) |
79545 | 794 |
795 (defcustom verilog-assignment-delay "" | |
796 "*Text used for delays in delayed assignments. Add a trailing space if set." | |
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797 :group 'verilog-mode-auto |
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798 :type 'string) |
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799 (put 'verilog-assignment-delay 'safe-local-variable 'stringp) |
79545 | 800 |
801 (defcustom verilog-auto-inst-vector t | |
802 "*If true, when creating default ports with AUTOINST, use bus subscripts. | |
803 If nil, skip the subscript when it matches the entire bus as declared in | |
804 the module (AUTOWIRE signals always are subscripted, you must manually | |
805 declare the wire to have the subscripts removed.) Nil may speed up some | |
806 simulators, but is less general and harder to read, so avoid." | |
807 :group 'verilog-mode-auto | |
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808 :type 'boolean) |
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809 (put 'verilog-auto-inst-vector 'safe-local-variable 'verilog-booleanp) |
79545 | 810 |
811 (defcustom verilog-auto-inst-template-numbers nil | |
812 "*If true, when creating templated ports with AUTOINST, add a comment. | |
813 The comment will add the line number of the template that was used for that | |
814 port declaration. Setting this aids in debugging, but nil is suggested for | |
815 regular use to prevent large numbers of merge conflicts." | |
816 :group 'verilog-mode-auto | |
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817 :type 'boolean) |
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818 (put 'verilog-auto-inst-template-numbers 'safe-local-variable 'verilog-booleanp) |
79545 | 819 |
820 (defvar verilog-auto-inst-column 40 | |
821 "Column number for first part of auto-inst.") | |
822 | |
823 (defcustom verilog-auto-input-ignore-regexp nil | |
824 "*If set, when creating AUTOINPUT list, ignore signals matching this regexp. | |
825 See the \\[verilog-faq] for examples on using this." | |
826 :group 'verilog-mode-auto | |
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827 :type 'string) |
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828 (put 'verilog-auto-input-ignore-regexp 'safe-local-variable 'stringp) |
79545 | 829 |
830 (defcustom verilog-auto-inout-ignore-regexp nil | |
831 "*If set, when creating AUTOINOUT list, ignore signals matching this regexp. | |
832 See the \\[verilog-faq] for examples on using this." | |
833 :group 'verilog-mode-auto | |
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834 :type 'string) |
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835 (put 'verilog-auto-inout-ignore-regexp 'safe-local-variable 'stringp) |
79545 | 836 |
837 (defcustom verilog-auto-output-ignore-regexp nil | |
838 "*If set, when creating AUTOOUTPUT list, ignore signals matching this regexp. | |
839 See the \\[verilog-faq] for examples on using this." | |
840 :group 'verilog-mode-auto | |
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841 :type 'string) |
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842 (put 'verilog-auto-output-ignore-regexp 'safe-local-variable 'stringp) |
79545 | 843 |
844 (defcustom verilog-auto-unused-ignore-regexp nil | |
845 "*If set, when creating AUTOUNUSED list, ignore signals matching this regexp. | |
846 See the \\[verilog-faq] for examples on using this." | |
847 :group 'verilog-mode-auto | |
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848 :type 'string) |
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849 (put 'verilog-auto-unused-ignore-regexp 'safe-local-variable 'stringp) |
79545 | 850 |
851 (defcustom verilog-typedef-regexp nil | |
852 "*If non-nil, regular expression that matches Verilog-2001 typedef names. | |
853 For example, \"_t$\" matches typedefs named with _t, as in the C language." | |
854 :group 'verilog-mode-auto | |
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855 :type 'string) |
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856 (put 'verilog-typedef-regexp 'safe-local-variable 'stringp) |
79545 | 857 |
858 (defcustom verilog-mode-hook 'verilog-set-compile-command | |
859 "*Hook (List of functions) run after verilog mode is loaded." | |
860 :type 'hook | |
861 :group 'verilog-mode) | |
862 | |
863 (defcustom verilog-auto-hook nil | |
864 "*Hook run after `verilog-mode' updates AUTOs." | |
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865 :group 'verilog-mode-auto |
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866 :type 'hook) |
79545 | 867 |
868 (defcustom verilog-before-auto-hook nil | |
869 "*Hook run before `verilog-mode' updates AUTOs." | |
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870 :group 'verilog-mode-auto |
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871 :type 'hook) |
79545 | 872 |
873 (defcustom verilog-delete-auto-hook nil | |
874 "*Hook run after `verilog-mode' deletes AUTOs." | |
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875 :group 'verilog-mode-auto |
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876 :type 'hook) |
79545 | 877 |
878 (defcustom verilog-before-delete-auto-hook nil | |
879 "*Hook run before `verilog-mode' deletes AUTOs." | |
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880 :group 'verilog-mode-auto |
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881 :type 'hook) |
79545 | 882 |
883 (defcustom verilog-getopt-flags-hook nil | |
884 "*Hook run after `verilog-getopt-flags' determines the Verilog option lists." | |
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885 :group 'verilog-mode-auto |
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886 :type 'hook) |
79545 | 887 |
888 (defcustom verilog-before-getopt-flags-hook nil | |
889 "*Hook run before `verilog-getopt-flags' determines the Verilog option lists." | |
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890 :group 'verilog-mode-auto |
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891 :type 'hook) |
79545 | 892 |
893 (defvar verilog-imenu-generic-expression | |
894 '((nil "^\\s-*\\(\\(m\\(odule\\|acromodule\\)\\)\\|primitive\\)\\s-+\\([a-zA-Z0-9_.:]+\\)" 4) | |
895 ("*Vars*" "^\\s-*\\(reg\\|wire\\)\\s-+\\(\\|\\[[^]]+\\]\\s-+\\)\\([A-Za-z0-9_]+\\)" 3)) | |
896 "Imenu expression for Verilog-mode. See `imenu-generic-expression'.") | |
897 | |
898 ;; | |
899 ;; provide a verilog-header function. | |
900 ;; Customization variables: | |
901 ;; | |
902 (defvar verilog-date-scientific-format nil | |
903 "*If non-nil, dates are written in scientific format (e.g. 1997/09/17). | |
904 If nil, in European format (e.g. 17.09.1997). The brain-dead American | |
905 format (e.g. 09/17/1997) is not supported.") | |
906 | |
907 (defvar verilog-company nil | |
908 "*Default name of Company for verilog header. | |
909 If set will become buffer local.") | |
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910 (make-variable-buffer-local 'verilog-company) |
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911 |
79545 | 912 (defvar verilog-project nil |
913 "*Default name of Project for verilog header. | |
914 If set will become buffer local.") | |
79691
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915 (make-variable-buffer-local 'verilog-project) |
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916 |
79549
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917 (defvar verilog-mode-map |
79546 | 918 (let ((map (make-sparse-keymap))) |
919 (define-key map ";" 'electric-verilog-semi) | |
920 (define-key map [(control 59)] 'electric-verilog-semi-with-comment) | |
921 (define-key map ":" 'electric-verilog-colon) | |
922 ;;(define-key map "=" 'electric-verilog-equal) | |
923 (define-key map "\`" 'electric-verilog-tick) | |
924 (define-key map "\t" 'electric-verilog-tab) | |
925 (define-key map "\r" 'electric-verilog-terminate-line) | |
926 ;; backspace/delete key bindings | |
927 (define-key map [backspace] 'backward-delete-char-untabify) | |
928 (unless (boundp 'delete-key-deletes-forward) ; XEmacs variable | |
929 (define-key map [delete] 'delete-char) | |
930 (define-key map [(meta delete)] 'kill-word)) | |
931 (define-key map "\M-\C-b" 'electric-verilog-backward-sexp) | |
932 (define-key map "\M-\C-f" 'electric-verilog-forward-sexp) | |
933 (define-key map "\M-\r" `electric-verilog-terminate-and-indent) | |
934 (define-key map "\M-\t" 'verilog-complete-word) | |
935 (define-key map "\M-?" 'verilog-show-completions) | |
936 (define-key map "\C-c\`" 'verilog-lint-off) | |
937 (define-key map "\C-c\*" 'verilog-delete-auto-star-implicit) | |
938 (define-key map "\C-c\C-r" 'verilog-label-be) | |
939 (define-key map "\C-c\C-i" 'verilog-pretty-declarations) | |
940 (define-key map "\C-c=" 'verilog-pretty-expr) | |
941 (define-key map "\C-c\C-b" 'verilog-submit-bug-report) | |
942 (define-key map "\M-*" 'verilog-star-comment) | |
943 (define-key map "\C-c\C-c" 'verilog-comment-region) | |
944 (define-key map "\C-c\C-u" 'verilog-uncomment-region) | |
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945 (when (featurep 'xemacs) |
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946 (define-key map [(meta control h)] 'verilog-mark-defun) |
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947 (define-key map "\M-\C-a" 'verilog-beg-of-defun) |
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948 (define-key map "\M-\C-e" 'verilog-end-of-defun)) |
79546 | 949 (define-key map "\C-c\C-d" 'verilog-goto-defun) |
950 (define-key map "\C-c\C-k" 'verilog-delete-auto) | |
951 (define-key map "\C-c\C-a" 'verilog-auto) | |
952 (define-key map "\C-c\C-s" 'verilog-auto-save-compile) | |
953 (define-key map "\C-c\C-z" 'verilog-inject-auto) | |
954 (define-key map "\C-c\C-e" 'verilog-expand-vector) | |
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955 (define-key map "\C-c\C-h" 'verilog-header) |
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956 map) |
79545 | 957 "Keymap used in Verilog mode.") |
958 | |
959 ;; menus | |
960 (defvar verilog-xemacs-menu | |
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961 `("Verilog" |
79545 | 962 ("Choose Compilation Action" |
963 ["None" | |
964 (progn | |
965 (setq verilog-tool nil) | |
966 (verilog-set-compile-command)) | |
967 :style radio | |
968 :selected (equal verilog-tool nil)] | |
969 ["Lint" | |
970 (progn | |
971 (setq verilog-tool 'verilog-linter) | |
972 (verilog-set-compile-command)) | |
973 :style radio | |
974 :selected (equal verilog-tool `verilog-linter)] | |
975 ["Coverage" | |
976 (progn | |
977 (setq verilog-tool 'verilog-coverage) | |
978 (verilog-set-compile-command)) | |
979 :style radio | |
980 :selected (equal verilog-tool `verilog-coverage)] | |
981 ["Simulator" | |
982 (progn | |
983 (setq verilog-tool 'verilog-simulator) | |
984 (verilog-set-compile-command)) | |
985 :style radio | |
986 :selected (equal verilog-tool `verilog-simulator)] | |
987 ["Compiler" | |
988 (progn | |
989 (setq verilog-tool 'verilog-compiler) | |
990 (verilog-set-compile-command)) | |
991 :style radio | |
992 :selected (equal verilog-tool `verilog-compiler)] | |
993 ) | |
994 ("Move" | |
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995 ,(if (featurep 'xemacs) |
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996 (progn |
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997 ["Beginning of function" verilog-beg-of-defun t] |
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998 ["End of function" verilog-end-of-defun t] |
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999 ["Mark function" verilog-mark-defun t]) |
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1000 ["Beginning of function" beginning-of-defun t] |
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1001 ["End of function" end-of-defun t] |
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1002 ["Mark function" mark-defun t]) |
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1003 |
79545 | 1004 ["Goto function/module" verilog-goto-defun t] |
1005 ["Move to beginning of block" electric-verilog-backward-sexp t] | |
1006 ["Move to end of block" electric-verilog-forward-sexp t] | |
1007 ) | |
1008 ("Comments" | |
1009 ["Comment Region" verilog-comment-region t] | |
1010 ["UnComment Region" verilog-uncomment-region t] | |
1011 ["Multi-line comment insert" verilog-star-comment t] | |
1012 ["Lint error to comment" verilog-lint-off t] | |
1013 ) | |
1014 "----" | |
1015 ["Compile" compile t] | |
1016 ["AUTO, Save, Compile" verilog-auto-save-compile t] | |
1017 ["Next Compile Error" next-error t] | |
1018 ["Ignore Lint Warning at point" verilog-lint-off t] | |
1019 "----" | |
1020 ["Line up declarations around point" verilog-pretty-declarations t] | |
1021 ["Line up equations around point" verilog-pretty-expr t] | |
1022 ["Redo/insert comments on every end" verilog-label-be t] | |
1023 ["Expand [x:y] vector line" verilog-expand-vector t] | |
1024 ["Insert begin-end block" verilog-insert-block t] | |
1025 ["Complete word" verilog-complete-word t] | |
1026 "----" | |
1027 ["Recompute AUTOs" verilog-auto t] | |
1028 ["Kill AUTOs" verilog-delete-auto t] | |
1029 ["Inject AUTOs" verilog-inject-auto t] | |
1030 ("AUTO Help..." | |
1031 ["AUTO General" (describe-function 'verilog-auto) t] | |
1032 ["AUTO Library Flags" (describe-variable 'verilog-library-flags) t] | |
1033 ["AUTO Library Path" (describe-variable 'verilog-library-directories) t] | |
1034 ["AUTO Library Files" (describe-variable 'verilog-library-files) t] | |
1035 ["AUTO Library Extensions" (describe-variable 'verilog-library-extensions) t] | |
1036 ["AUTO `define Reading" (describe-function 'verilog-read-defines) t] | |
1037 ["AUTO `include Reading" (describe-function 'verilog-read-includes) t] | |
1038 ["AUTOARG" (describe-function 'verilog-auto-arg) t] | |
1039 ["AUTOASCIIENUM" (describe-function 'verilog-auto-ascii-enum) t] | |
1040 ["AUTOINOUTMODULE" (describe-function 'verilog-auto-inout-module) t] | |
1041 ["AUTOINOUT" (describe-function 'verilog-auto-inout) t] | |
1042 ["AUTOINPUT" (describe-function 'verilog-auto-input) t] | |
1043 ["AUTOINST" (describe-function 'verilog-auto-inst) t] | |
1044 ["AUTOINST (.*)" (describe-function 'verilog-auto-star) t] | |
1045 ["AUTOINSTPARAM" (describe-function 'verilog-auto-inst-param) t] | |
1046 ["AUTOOUTPUT" (describe-function 'verilog-auto-output) t] | |
1047 ["AUTOOUTPUTEVERY" (describe-function 'verilog-auto-output-every) t] | |
1048 ["AUTOREG" (describe-function 'verilog-auto-reg) t] | |
1049 ["AUTOREGINPUT" (describe-function 'verilog-auto-reg-input) t] | |
1050 ["AUTORESET" (describe-function 'verilog-auto-reset) t] | |
1051 ["AUTOSENSE" (describe-function 'verilog-auto-sense) t] | |
1052 ["AUTOTIEOFF" (describe-function 'verilog-auto-tieoff) t] | |
1053 ["AUTOUNUSED" (describe-function 'verilog-auto-unused) t] | |
1054 ["AUTOWIRE" (describe-function 'verilog-auto-wire) t] | |
1055 ) | |
1056 "----" | |
1057 ["Submit bug report" verilog-submit-bug-report t] | |
1058 ["Version and FAQ" verilog-faq t] | |
1059 ["Customize Verilog Mode..." verilog-customize t] | |
1060 ["Customize Verilog Fonts & Colors" verilog-font-customize t] | |
1061 ) | |
1062 "Emacs menu for VERILOG mode." | |
1063 ) | |
1064 (defvar verilog-statement-menu | |
1065 '("Statements" | |
1066 ["Header" verilog-sk-header t] | |
1067 ["Comment" verilog-sk-comment t] | |
1068 "----" | |
1069 ["Module" verilog-sk-module t] | |
1070 ["Primitive" verilog-sk-primitive t] | |
1071 "----" | |
1072 ["Input" verilog-sk-input t] | |
1073 ["Output" verilog-sk-output t] | |
1074 ["Inout" verilog-sk-inout t] | |
1075 ["Wire" verilog-sk-wire t] | |
1076 ["Reg" verilog-sk-reg t] | |
1077 ["Define thing under point as a register" verilog-sk-define-signal t] | |
1078 "----" | |
1079 ["Initial" verilog-sk-initial t] | |
1080 ["Always" verilog-sk-always t] | |
1081 ["Function" verilog-sk-function t] | |
1082 ["Task" verilog-sk-task t] | |
1083 ["Specify" verilog-sk-specify t] | |
1084 ["Generate" verilog-sk-generate t] | |
1085 "----" | |
1086 ["Begin" verilog-sk-begin t] | |
1087 ["If" verilog-sk-if t] | |
1088 ["(if) else" verilog-sk-else-if t] | |
1089 ["For" verilog-sk-for t] | |
1090 ["While" verilog-sk-while t] | |
1091 ["Fork" verilog-sk-fork t] | |
1092 ["Repeat" verilog-sk-repeat t] | |
1093 ["Case" verilog-sk-case t] | |
1094 ["Casex" verilog-sk-casex t] | |
1095 ["Casez" verilog-sk-casez t] | |
1096 ) | |
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1097 "Menu for statement templates in Verilog.") |
79545 | 1098 |
1099 (easy-menu-define verilog-menu verilog-mode-map "Menu for Verilog mode" | |
1100 verilog-xemacs-menu) | |
1101 (easy-menu-define verilog-stmt-menu verilog-mode-map "Menu for statement templates in Verilog." | |
1102 verilog-statement-menu) | |
1103 | |
1104 (defvar verilog-mode-abbrev-table nil | |
1105 "Abbrev table in use in Verilog-mode buffers.") | |
1106 | |
1107 (define-abbrev-table 'verilog-mode-abbrev-table ()) | |
1108 | |
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1109 ;; |
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1110 ;; Macros |
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1111 ;; |
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1112 |
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1113 (defsubst verilog-string-replace-matches (from-string to-string fixedcase literal string) |
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1114 "Replace occurrences of FROM-STRING with TO-STRING. |
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1115 FIXEDCASE and LITERAL as in `replace-match`. STRING is what to replace. |
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1116 The case (verilog-string-replace-matches \"o\" \"oo\" nil nil \"foobar\") |
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1117 will break, as the o's continuously replace. xa -> x works ok though." |
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1118 ;; Hopefully soon to a emacs built-in |
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1119 (let ((start 0)) |
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1120 (while (string-match from-string string start) |
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1121 (setq string (replace-match to-string fixedcase literal string) |
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1122 start (min (length string) (match-end 0)))) |
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1123 string)) |
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1124 |
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1125 (defsubst verilog-string-remove-spaces (string) |
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1126 "Remove spaces surrounding STRING." |
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1127 (save-match-data |
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1128 (setq string (verilog-string-replace-matches "^\\s-+" "" nil nil string)) |
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1129 (setq string (verilog-string-replace-matches "\\s-+$" "" nil nil string)) |
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1130 string)) |
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1131 |
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1132 (defsubst verilog-re-search-forward (REGEXP BOUND NOERROR) |
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1133 ; checkdoc-params: (REGEXP BOUND NOERROR) |
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1134 "Like `re-search-forward', but skips over match in comments or strings." |
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1135 (store-match-data '(nil nil)) |
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1136 (while (and |
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1137 (re-search-forward REGEXP BOUND NOERROR) |
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1138 (and (verilog-skip-forward-comment-or-string) |
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1139 (progn |
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1140 (store-match-data '(nil nil)) |
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1141 (if BOUND |
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1142 (< (point) BOUND) |
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1143 t))))) |
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1144 (match-end 0)) |
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1145 |
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1146 (defsubst verilog-re-search-backward (REGEXP BOUND NOERROR) |
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1147 ; checkdoc-params: (REGEXP BOUND NOERROR) |
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1148 "Like `re-search-backward', but skips over match in comments or strings." |
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1149 (store-match-data '(nil nil)) |
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1150 (while (and |
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1151 (re-search-backward REGEXP BOUND NOERROR) |
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1152 (and (verilog-skip-backward-comment-or-string) |
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1153 (progn |
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1154 (store-match-data '(nil nil)) |
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1155 (if BOUND |
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1156 (> (point) BOUND) |
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1157 t))))) |
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1158 (match-end 0)) |
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1159 |
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1160 (defsubst verilog-re-search-forward-quick (regexp bound noerror) |
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1161 "Like `verilog-re-search-forward', including use of REGEXP BOUND and NOERROR, |
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1162 but trashes match data and is faster for REGEXP that doesn't match often. |
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1163 This may at some point use text properties to ignore comments, |
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1164 so there may be a large up front penalty for the first search." |
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1165 (let (pt) |
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1166 (while (and (not pt) |
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1167 (re-search-forward regexp bound noerror)) |
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1168 (if (not (verilog-inside-comment-p)) |
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1169 (setq pt (match-end 0)))) |
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1170 pt)) |
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1171 |
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1172 (defsubst verilog-re-search-backward-quick (regexp bound noerror) |
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1173 ; checkdoc-params: (REGEXP BOUND NOERROR) |
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1174 "Like `verilog-re-search-backward', including use of REGEXP BOUND and NOERROR, |
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1175 but trashes match data and is faster for REGEXP that doesn't match often. |
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1176 This may at some point use text properties to ignore comments, |
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1177 so there may be a large up front penalty for the first search." |
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1178 (let (pt) |
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1179 (while (and (not pt) |
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1180 (re-search-backward regexp bound noerror)) |
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1181 (if (not (verilog-inside-comment-p)) |
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1182 (setq pt (match-end 0)))) |
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1183 pt)) |
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1184 |
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1185 (defsubst verilog-get-beg-of-line (&optional arg) |
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1186 (save-excursion |
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1187 (beginning-of-line arg) |
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1188 (point))) |
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1189 |
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1190 (defsubst verilog-get-end-of-line (&optional arg) |
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1191 (save-excursion |
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1192 (end-of-line arg) |
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1193 (point))) |
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1194 |
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1195 (defsubst verilog-within-string () |
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1196 (save-excursion |
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1197 (nth 3 (parse-partial-sexp (verilog-get-beg-of-line) (point))))) |
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1198 |
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1199 (defvar compile-command) |
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1200 |
79545 | 1201 ;; compilation program |
1202 (defun verilog-set-compile-command () | |
1203 "Function to compute shell command to compile verilog. | |
1204 | |
1205 This reads `verilog-tool' and sets `compile-command'. This specifies the | |
1206 program that executes when you type \\[compile] or | |
1207 \\[verilog-auto-save-compile]. | |
1208 | |
1209 By default `verilog-tool' uses a Makefile if one exists in the current | |
1210 directory. If not, it is set to the `verilog-linter', `verilog-coverage', | |
1211 `verilog-simulator', or `verilog-compiler' variables, as selected with the | |
1212 Verilog -> \"Choose Compilation Action\" menu. | |
1213 | |
1214 You should set `verilog-tool' or the other variables to the path and | |
1215 arguments for your Verilog simulator. For example: | |
1216 \"vcs -p123 -O\" | |
1217 or a string like: | |
1218 \"(cd /tmp; surecov %s)\". | |
1219 | |
1220 In the former case, the path to the current buffer is concat'ed to the | |
1221 value of `verilog-tool'; in the later, the path to the current buffer is | |
1222 substituted for the %s. | |
1223 | |
1224 Where __FILE__ appears in the string, the buffer-file-name of the current | |
1225 buffer, without the directory portion, will be substituted." | |
1226 (interactive) | |
1227 (cond | |
1228 ((or (file-exists-p "makefile") ;If there is a makefile, use it | |
1229 (file-exists-p "Makefile")) | |
1230 (make-local-variable 'compile-command) | |
1231 (setq compile-command "make ")) | |
1232 (t | |
1233 (make-local-variable 'compile-command) | |
1234 (setq compile-command | |
1235 (if verilog-tool | |
1236 (if (string-match "%s" (eval verilog-tool)) | |
1237 (format (eval verilog-tool) (or buffer-file-name "")) | |
1238 (concat (eval verilog-tool) " " (or buffer-file-name ""))) | |
1239 "")))) | |
1240 (verilog-modify-compile-command)) | |
1241 | |
1242 (defun verilog-modify-compile-command () | |
1243 "Replace meta-information in `compile-command'. | |
1244 Where __FILE__ appears in the string, the current buffer's file-name, | |
1245 without the directory portion, will be substituted." | |
1246 (when (and | |
1247 (stringp compile-command) | |
1248 (string-match "\\b__FILE__\\b" compile-command)) | |
1249 (make-local-variable 'compile-command) | |
1250 (setq compile-command | |
1251 (verilog-string-replace-matches | |
1252 "\\b__FILE__\\b" (file-name-nondirectory (buffer-file-name)) | |
1253 t t compile-command)))) | |
1254 | |
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1255 ;; Following code only gets called from compilation-mode-hook. |
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1256 (defvar compilation-error-regexp-alist) |
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1257 |
79545 | 1258 (defun verilog-error-regexp-add () |
1259 "Add the messages to the `compilation-error-regexp-alist'. | |
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1260 Called by `compilation-mode-hook'. This allows \\[next-error] to |
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1261 find the errors." |
79545 | 1262 (if (not verilog-error-regexp-add-didit) |
1263 (progn | |
1264 (setq verilog-error-regexp-add-didit t) | |
1265 (setq-default compilation-error-regexp-alist | |
1266 (append verilog-error-regexp | |
1267 (default-value 'compilation-error-regexp-alist))) | |
1268 ;; Could be buffer local at this point; maybe also in let; change all three | |
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1269 (setq compilation-error-regexp-alist |
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1270 (default-value 'compilation-error-regexp-alist)) |
79545 | 1271 (set (make-local-variable 'compilation-error-regexp-alist) |
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1272 (default-value 'compilation-error-regexp-alist))))) |
79545 | 1273 |
1274 (add-hook 'compilation-mode-hook 'verilog-error-regexp-add) | |
1275 | |
1276 (defconst verilog-directive-re | |
1277 ;; "`case" "`default" "`define" "`define" "`else" "`endfor" "`endif" | |
1278 ;; "`endprotect" "`endswitch" "`endwhile" "`for" "`format" "`if" "`ifdef" | |
1279 ;; "`ifndef" "`include" "`let" "`protect" "`switch" "`timescale" | |
1280 ;; "`time_scale" "`undef" "`while" | |
1281 "\\<`\\(case\\|def\\(ault\\|ine\\(\\)?\\)\\|e\\(lse\\|nd\\(for\\|if\\|protect\\|switch\\|while\\)\\)\\|for\\(mat\\)?\\|i\\(f\\(def\\|ndef\\)?\\|nclude\\)\\|let\\|protect\\|switch\\|time\\(_scale\\|scale\\)\\|undef\\|while\\)\\>") | |
1282 | |
1283 (defconst verilog-directive-begin | |
1284 "\\<`\\(for\\|i\\(f\\|fdef\\|fndef\\)\\|switch\\|while\\)\\>") | |
1285 | |
1286 (defconst verilog-directive-middle | |
1287 "\\<`\\(else\\|default\\|case\\)\\>") | |
1288 | |
1289 (defconst verilog-directive-end | |
1290 "`\\(endfor\\|endif\\|endswitch\\|endwhile\\)\\>") | |
1291 | |
1292 (defconst verilog-directive-re-1 | |
1293 (concat "[ \t]*" verilog-directive-re)) | |
1294 | |
1295 ;; | |
1296 ;; Regular expressions used to calculate indent, etc. | |
1297 ;; | |
1298 (defconst verilog-symbol-re "\\<[a-zA-Z_][a-zA-Z_0-9.]*\\>") | |
1299 (defconst verilog-case-re "\\(\\<case[xz]?\\>\\|\\<randcase\\>\\)") | |
1300 ;; Want to match | |
1301 ;; aa : | |
1302 ;; aa,bb : | |
1303 ;; a[34:32] : | |
1304 ;; a, | |
1305 ;; b : | |
1306 | |
1307 (defconst verilog-no-indent-begin-re | |
1308 "\\<\\(if\\|else\\|while\\|for\\|repeat\\|always\\|always_comb\\|always_ff\\|always_latch\\)\\>") | |
1309 | |
1310 (defconst verilog-ends-re | |
1311 ;; Parenthesis indicate type of keyword found | |
1312 (concat | |
1313 "\\(\\<else\\>\\)\\|" ; 1 | |
1314 "\\(\\<if\\>\\)\\|" ; 2 | |
1315 "\\(\\<end\\>\\)\\|" ; 3 | |
1316 "\\(\\<endcase\\>\\)\\|" ; 4 | |
1317 "\\(\\<endfunction\\>\\)\\|" ; 5 | |
1318 "\\(\\<endtask\\>\\)\\|" ; 6 | |
1319 "\\(\\<endspecify\\>\\)\\|" ; 7 | |
1320 "\\(\\<endtable\\>\\)\\|" ; 8 | |
1321 "\\(\\<endgenerate\\>\\)\\|" ; 9 | |
1322 "\\(\\<join\\(_any\\|_none\\)?\\>\\)\\|" ; 10 | |
1323 "\\(\\<endclass\\>\\)\\|" ; 11 | |
1324 "\\(\\<endgroup\\>\\)" ; 12 | |
1325 )) | |
1326 | |
1327 (defconst verilog-auto-end-comment-lines-re | |
1328 ;; Matches to names in this list cause auto-end-commentation | |
1329 (concat "\\(" | |
1330 verilog-directive-re "\\)\\|\\(" | |
1331 (eval-when-compile | |
1332 (verilog-regexp-words | |
1333 `( "begin" | |
1334 "else" | |
1335 "end" | |
1336 "endcase" | |
1337 "endclass" | |
1338 "endclocking" | |
1339 "endgroup" | |
1340 "endfunction" | |
1341 "endmodule" | |
1342 "endprogram" | |
1343 "endprimitive" | |
1344 "endinterface" | |
1345 "endpackage" | |
1346 "endsequence" | |
1347 "endspecify" | |
1348 "endtable" | |
1349 "endtask" | |
1350 "join" | |
1351 "join_any" | |
1352 "join_none" | |
1353 "module" | |
1354 "macromodule" | |
1355 "primitive" | |
1356 "interface" | |
1357 "package"))) | |
1358 "\\)")) | |
1359 | |
1360 ;;; NOTE: verilog-leap-to-head expects that verilog-end-block-re and | |
1361 ;;; verilog-end-block-ordered-re matches exactly the same strings. | |
1362 (defconst verilog-end-block-ordered-re | |
1363 ;; Parenthesis indicate type of keyword found | |
1364 (concat "\\(\\<endcase\\>\\)\\|" ; 1 | |
1365 "\\(\\<end\\>\\)\\|" ; 2 | |
1366 "\\(\\<end" ; 3, but not used | |
1367 "\\(" ; 4, but not used | |
1368 "\\(function\\)\\|" ; 5 | |
1369 "\\(task\\)\\|" ; 6 | |
1370 "\\(module\\)\\|" ; 7 | |
1371 "\\(primitive\\)\\|" ; 8 | |
1372 "\\(interface\\)\\|" ; 9 | |
1373 "\\(package\\)\\|" ; 10 | |
1374 "\\(class\\)\\|" ; 11 | |
1375 "\\(group\\)\\|" ; 12 | |
1376 "\\(program\\)\\|" ; 13 | |
1377 "\\(sequence\\)\\|" ; 14 | |
1378 "\\(clocking\\)\\|" ; 15 | |
1379 "\\)\\>\\)")) | |
1380 (defconst verilog-end-block-re | |
1381 (eval-when-compile | |
1382 (verilog-regexp-words | |
1383 | |
1384 `("end" ;; closes begin | |
1385 "endcase" ;; closes any of case, casex casez or randcase | |
1386 "join" "join_any" "join_none" ;; closes fork | |
1387 "endclass" | |
1388 "endtable" | |
1389 "endspecify" | |
1390 "endfunction" | |
1391 "endgenerate" | |
1392 "endtask" | |
1393 "endgroup" | |
1394 "endproperty" | |
1395 "endinterface" | |
1396 "endpackage" | |
1397 "endprogram" | |
1398 "endsequence" | |
1399 "endclocking" | |
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1400 )))) |
79545 | 1401 |
1402 | |
1403 (defconst verilog-endcomment-reason-re | |
1404 ;; Parenthesis indicate type of keyword found | |
1405 (concat | |
1406 "\\(\\<fork\\>\\)\\|" | |
1407 "\\(\\<begin\\>\\)\\|" | |
1408 "\\(\\<if\\>\\)\\|" | |
1409 "\\(\\<clocking\\>\\)\\|" | |
1410 "\\(\\<else\\>\\)\\|" | |
1411 "\\(\\<end\\>.*\\<else\\>\\)\\|" | |
1412 "\\(\\<task\\>\\)\\|" | |
1413 "\\(\\<function\\>\\)\\|" | |
1414 "\\(\\<initial\\>\\)\\|" | |
1415 "\\(\\<interface\\>\\)\\|" | |
1416 "\\(\\<package\\>\\)\\|" | |
1417 "\\(\\<final\\>\\)\\|" | |
1418 "\\(\\<always\\>\\(\[ \t\]*@\\)?\\)\\|" | |
1419 "\\(\\<always_comb\\>\\(\[ \t\]*@\\)?\\)\\|" | |
1420 "\\(\\<always_ff\\>\\(\[ \t\]*@\\)?\\)\\|" | |
1421 "\\(\\<always_latch\\>\\(\[ \t\]*@\\)?\\)\\|" | |
1422 "\\(@\\)\\|" | |
1423 "\\(\\<while\\>\\)\\|" | |
1424 "\\(\\<for\\(ever\\|each\\)?\\>\\)\\|" | |
1425 "\\(\\<repeat\\>\\)\\|\\(\\<wait\\>\\)\\|" | |
1426 "#")) | |
1427 | |
1428 (defconst verilog-named-block-re "begin[ \t]*:") | |
1429 | |
1430 ;; These words begin a block which can occur inside a module which should be indented, | |
1431 ;; and closed with the respective word from the end-block list | |
1432 | |
1433 (defconst verilog-beg-block-re | |
1434 (eval-when-compile | |
1435 (verilog-regexp-words | |
1436 `("begin" | |
1437 "case" "casex" "casez" "randcase" | |
1438 "clocking" | |
1439 "generate" | |
1440 "fork" | |
1441 "function" | |
1442 "property" | |
1443 "specify" | |
1444 "table" | |
1445 "task" | |
1446 )))) | |
1447 ;; These are the same words, in a specific order in the regular | |
1448 ;; expression so that matching will work nicely for | |
1449 ;; verilog-forward-sexp and verilog-calc-indent | |
1450 | |
1451 (defconst verilog-beg-block-re-ordered | |
1452 ( concat "\\<" | |
1453 "\\(begin\\)" ;1 | |
1454 "\\|\\(randcase\\|\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?\\)" ; 2 | |
1455 ;; "\\|\\(randcase\\|case[xz]?\\)" ; 2 | |
1456 "\\|\\(fork\\)" ;3 | |
1457 "\\|\\(class\\)" ;4 | |
1458 "\\|\\(table\\)" ;5 | |
1459 "\\|\\(specify\\)" ;6 | |
1460 "\\|\\(function\\)" ;7 | |
1461 "\\|\\(task\\)" ;8 | |
1462 "\\|\\(generate\\)" ;9 | |
1463 "\\|\\(covergroup\\)" ;10 | |
1464 "\\|\\(property\\)" ;11 | |
1465 "\\|\\(\\(rand\\)?sequence\\)" ;12 | |
1466 "\\|\\(clocking\\)" ;13 | |
1467 "\\>")) | |
1468 | |
1469 (defconst verilog-end-block-ordered-rry | |
1470 [ "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" | |
1471 "\\(\\<randcase\\>\\|\\<case[xz]?\\>\\)\\|\\(\\<endcase\\>\\)" | |
1472 "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" | |
1473 "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" | |
1474 "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" | |
1475 "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" | |
1476 "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" | |
1477 "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" | |
1478 "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" | |
1479 "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" | |
1480 "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" | |
1481 "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" | |
1482 "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)" | |
1483 ] ) | |
1484 | |
1485 (defconst verilog-nameable-item-re | |
1486 (eval-when-compile | |
1487 (verilog-regexp-words | |
1488 `("begin" | |
1489 "fork" | |
1490 "join" "join_any" "join_none" | |
1491 "end" | |
1492 "endcase" | |
1493 "endconfig" | |
1494 "endclass" | |
1495 "endclocking" | |
1496 "endfunction" | |
1497 "endgenerate" | |
1498 "endmodule" | |
1499 "endprimative" | |
1500 "endinterface" | |
1501 "endpackage" | |
1502 "endspecify" | |
1503 "endtable" | |
1504 "endtask" ) | |
1505 ))) | |
1506 | |
1507 (defconst verilog-declaration-opener | |
1508 (eval-when-compile | |
1509 (verilog-regexp-words | |
1510 `("module" "begin" "task" "function")))) | |
1511 | |
1512 (defconst verilog-declaration-prefix-re | |
1513 (eval-when-compile | |
1514 (verilog-regexp-words | |
1515 `( | |
1516 ;; port direction | |
79546 | 1517 "inout" "input" "output" "ref" |
79545 | 1518 ;; changeableness |
1519 "const" "static" "protected" "local" | |
1520 ;; parameters | |
79546 | 1521 "localparam" "parameter" "var" |
79545 | 1522 ;; type creation |
1523 "typedef" | |
1524 )))) | |
1525 (defconst verilog-declaration-core-re | |
1526 (eval-when-compile | |
1527 (verilog-regexp-words | |
1528 `( | |
1529 ;; integer_atom_type | |
1530 "byte" "shortint" "int" "longint" "integer" "time" | |
1531 ;; integer_vector_type | |
1532 "bit" "logic" "reg" | |
1533 ;; non_integer_type | |
1534 "shortreal" "real" "realtime" | |
1535 ;; net_type | |
1536 "supply0" "supply1" "tri" "triand" "trior" "trireg" "tri0" "tri1" "uwire" "wire" "wand" "wor" | |
1537 ;; misc | |
1538 "string" "event" "chandle" "virtual" "enum" "genvar" | |
1539 "struct" "union" | |
1540 ;; builtin classes | |
79546 | 1541 "mailbox" "semaphore" |
79545 | 1542 )))) |
79546 | 1543 (defconst verilog-declaration-re |
79545 | 1544 (concat "\\(" verilog-declaration-prefix-re "\\s-*\\)?" verilog-declaration-core-re)) |
1545 (defconst verilog-range-re "\\(\\[[^]]*\\]\\s-*\\)+") | |
1546 (defconst verilog-optional-signed-re "\\s-*\\(signed\\)?") | |
1547 (defconst verilog-optional-signed-range-re | |
1548 (concat | |
1549 "\\s-*\\(\\<\\(reg\\|wire\\)\\>\\s-*\\)?\\(\\<signed\\>\\s-*\\)?\\(" verilog-range-re "\\)?")) | |
1550 (defconst verilog-macroexp-re "`\\sw+") | |
1551 | |
1552 (defconst verilog-delay-re "#\\s-*\\(\\([0-9_]+\\('s?[hdxbo][0-9a-fA-F_xz]+\\)?\\)\\|\\(([^()]*)\\)\\|\\(\\sw+\\)\\)") | |
1553 (defconst verilog-declaration-re-2-no-macro | |
1554 (concat "\\s-*" verilog-declaration-re | |
1555 "\\s-*\\(\\(" verilog-optional-signed-range-re "\\)\\|\\(" verilog-delay-re "\\)" | |
1556 "\\)?")) | |
1557 (defconst verilog-declaration-re-2-macro | |
1558 (concat "\\s-*" verilog-declaration-re | |
1559 "\\s-*\\(\\(" verilog-optional-signed-range-re "\\)\\|\\(" verilog-delay-re "\\)" | |
1560 "\\|\\(" verilog-macroexp-re "\\)" | |
1561 "\\)?")) | |
1562 (defconst verilog-declaration-re-1-macro | |
1563 (concat "^" verilog-declaration-re-2-macro)) | |
1564 | |
1565 (defconst verilog-declaration-re-1-no-macro (concat "^" verilog-declaration-re-2-no-macro)) | |
1566 | |
1567 (defconst verilog-defun-re | |
1568 (eval-when-compile (verilog-regexp-words `("macromodule" "module" "class" "program" "interface" "package" "primitive" "config")))) | |
1569 (defconst verilog-end-defun-re | |
1570 (eval-when-compile (verilog-regexp-words `("endmodule" "endclass" "endprogram" "endinterface" "endpackage" "endprimitive" "endconfig")))) | |
1571 (defconst verilog-zero-indent-re | |
1572 (concat verilog-defun-re "\\|" verilog-end-defun-re)) | |
1573 | |
1574 (defconst verilog-behavioral-block-beg-re | |
1575 (concat "\\(\\<initial\\>\\|\\<final\\>\\|\\<always\\>\\|\\<always_comb\\>\\|\\<always_ff\\>\\|" | |
1576 "\\<always_latch\\>\\|\\<function\\>\\|\\<task\\>\\)")) | |
1577 | |
1578 (defconst verilog-indent-re | |
1579 (eval-when-compile | |
1580 (verilog-regexp-words | |
1581 `( | |
1582 "{" | |
1583 "always" "always_latch" "always_ff" "always_comb" | |
1584 "begin" "end" | |
1585 ; "unique" "priority" | |
1586 "case" "casex" "casez" "randcase" "endcase" | |
1587 "class" "endclass" | |
1588 "clocking" "endclocking" | |
1589 "config" "endconfig" | |
1590 "covergroup" "endgroup" | |
1591 "fork" "join" "join_any" "join_none" | |
1592 "function" "endfunction" | |
1593 "final" | |
1594 "generate" "endgenerate" | |
1595 "initial" | |
1596 "interface" "endinterface" | |
1597 "module" "macromodule" "endmodule" | |
1598 "package" "endpackage" | |
1599 "primitive" "endprimative" | |
1600 "program" "endprogram" | |
1601 "property" "endproperty" | |
1602 "sequence" "randsequence" "endsequence" | |
1603 "specify" "endspecify" | |
1604 "table" "endtable" | |
1605 "task" "endtask" | |
1606 "`case" | |
1607 "`default" | |
1608 "`define" "`undef" | |
1609 "`if" "`ifdef" "`ifndef" "`else" "`endif" | |
1610 "`while" "`endwhile" | |
1611 "`for" "`endfor" | |
1612 "`format" | |
1613 "`include" | |
1614 "`let" | |
1615 "`protect" "`endprotect" | |
1616 "`switch" "`endswitch" | |
1617 "`timescale" | |
1618 "`time_scale" | |
1619 )))) | |
1620 | |
1621 (defconst verilog-defun-level-re | |
1622 (eval-when-compile | |
1623 (verilog-regexp-words | |
1624 `( | |
1625 "module" "macromodule" "primitive" "class" "program" "initial" "final" "always" "always_comb" | |
1626 "always_ff" "always_latch" "endtask" "endfunction" "interface" "package" | |
1627 "config")))) | |
1628 | |
1629 (defconst verilog-defun-level-not-generate-re | |
1630 (eval-when-compile | |
1631 (verilog-regexp-words | |
1632 `( | |
1633 "module" "macromodule" "primitive" "class" "program" "interface" "package" "config")))) | |
1634 | |
1635 (defconst verilog-cpp-level-re | |
1636 (eval-when-compile | |
1637 (verilog-regexp-words | |
1638 `( | |
1639 "endmodule" "endprimitive" "endinterface" "endpackage" "endprogram" "endclass" | |
1640 )))) | |
1641 (defconst verilog-extended-case-re "\\(unique\\s-+\\|priority\\s-+\\)?case[xz]?") | |
1642 (defconst verilog-extended-complete-re | |
1643 (concat "\\(\\<extern\\s-+\\|\\<virtual\\s-+\\|\\<protected\\s-+\\)*\\(\\<function\\>\\|\\<task\\>\\)" | |
1644 "\\|\\(\\<typedef\\>\\s-+\\)*\\(\\<struct\\>\\|\\<union\\>\\|\\<class\\>\\)" | |
1645 "\\|" verilog-extended-case-re )) | |
1646 (defconst verilog-basic-complete-re | |
1647 (eval-when-compile | |
1648 (verilog-regexp-words | |
1649 `( | |
1650 "always" "assign" "always_latch" "always_ff" "always_comb" "constraint" | |
1651 "import" "initial" "final" "module" "macromodule" "repeat" "randcase" "while" | |
1652 "if" "for" "forever" "foreach" "else" "parameter" "do" | |
1653 )))) | |
1654 (defconst verilog-complete-reg | |
1655 (concat | |
1656 verilog-extended-complete-re | |
1657 "\\|" | |
1658 verilog-basic-complete-re)) | |
1659 | |
1660 (defconst verilog-end-statement-re | |
1661 (concat "\\(" verilog-beg-block-re "\\)\\|\\(" | |
1662 verilog-end-block-re "\\)")) | |
1663 | |
1664 (defconst verilog-endcase-re | |
1665 (concat verilog-case-re "\\|" | |
1666 "\\(endcase\\)\\|" | |
1667 verilog-defun-re | |
1668 )) | |
1669 | |
1670 (defconst verilog-exclude-str-start "/* -----\\/----- EXCLUDED -----\\/-----" | |
1671 "String used to mark beginning of excluded text.") | |
1672 (defconst verilog-exclude-str-end " -----/\\----- EXCLUDED -----/\\----- */" | |
1673 "String used to mark end of excluded text.") | |
1674 (defconst verilog-preprocessor-re | |
1675 (eval-when-compile | |
1676 (verilog-regexp-words | |
1677 `( | |
1678 "`define" "`include" "`ifdef" "`ifndef" "`if" "`endif" "`else" | |
1679 )))) | |
1680 | |
1681 (defconst verilog-keywords | |
1682 '( "`case" "`default" "`define" "`else" "`endfor" "`endif" | |
1683 "`endprotect" "`endswitch" "`endwhile" "`for" "`format" "`if" "`ifdef" | |
1684 "`ifndef" "`include" "`let" "`protect" "`switch" "`timescale" | |
1685 "`time_scale" "`undef" "`while" | |
1686 | |
1687 "after" "alias" "always" "always_comb" "always_ff" "always_latch" "and" | |
1688 "assert" "assign" "assume" "automatic" "before" "begin" "bind" | |
1689 "bins" "binsof" "bit" "break" "buf" "bufif0" "bufif1" "byte" | |
1690 "case" "casex" "casez" "cell" "chandle" "class" "clocking" "cmos" | |
1691 "config" "const" "constraint" "context" "continue" "cover" | |
1692 "covergroup" "coverpoint" "cross" "deassign" "default" "defparam" | |
1693 "design" "disable" "dist" "do" "edge" "else" "end" "endcase" | |
1694 "endclass" "endclocking" "endconfig" "endfunction" "endgenerate" | |
1695 "endgroup" "endinterface" "endmodule" "endpackage" "endprimitive" | |
1696 "endprogram" "endproperty" "endspecify" "endsequence" "endtable" | |
1697 "endtask" "enum" "event" "expect" "export" "extends" "extern" | |
1698 "final" "first_match" "for" "force" "foreach" "forever" "fork" | |
1699 "forkjoin" "function" "generate" "genvar" "highz0" "highz1" "if" | |
1700 "iff" "ifnone" "ignore_bins" "illegal_bins" "import" "incdir" | |
1701 "include" "initial" "inout" "input" "inside" "instance" "int" | |
1702 "integer" "interface" "intersect" "join" "join_any" "join_none" | |
1703 "large" "liblist" "library" "local" "localparam" "logic" | |
1704 "longint" "macromodule" "mailbox" "matches" "medium" "modport" "module" | |
1705 "nand" "negedge" "new" "nmos" "nor" "noshowcancelled" "not" | |
1706 "notif0" "notif1" "null" "or" "output" "package" "packed" | |
1707 "parameter" "pmos" "posedge" "primitive" "priority" "program" | |
1708 "property" "protected" "pull0" "pull1" "pulldown" "pullup" | |
1709 "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc" | |
1710 "randcase" "randsequence" "rcmos" "real" "realtime" "ref" "reg" | |
1711 "release" "repeat" "return" "rnmos" "rpmos" "rtran" "rtranif0" | |
1712 "rtranif1" "scalared" "semaphore" "sequence" "shortint" "shortreal" | |
1713 "showcancelled" "signed" "small" "solve" "specify" "specparam" | |
1714 "static" "string" "strong0" "strong1" "struct" "super" "supply0" | |
1715 "supply1" "table" "tagged" "task" "this" "throughout" "time" | |
1716 "timeprecision" "timeunit" "tran" "tranif0" "tranif1" "tri" | |
1717 "tri0" "tri1" "triand" "trior" "trireg" "type" "typedef" "union" | |
1718 "unique" "unsigned" "use" "uwire" "var" "vectored" "virtual" "void" | |
1719 "wait" "wait_order" "wand" "weak0" "weak1" "while" "wildcard" | |
1720 "wire" "with" "within" "wor" "xnor" "xor" | |
1721 ) | |
1722 "List of Verilog keywords.") | |
1723 | |
1724 (defconst verilog-comment-start-regexp "//\\|/\\*" | |
1725 "Dual comment value for `comment-start-regexp'.") | |
1726 | |
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1727 (defvar verilog-mode-syntax-table |
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1728 (let ((table (make-syntax-table))) |
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1729 ;; Populate the syntax TABLE. |
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1730 (modify-syntax-entry ?\\ "\\" table) |
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1731 (modify-syntax-entry ?+ "." table) |
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1732 (modify-syntax-entry ?- "." table) |
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1733 (modify-syntax-entry ?= "." table) |
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1734 (modify-syntax-entry ?% "." table) |
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1735 (modify-syntax-entry ?< "." table) |
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1736 (modify-syntax-entry ?> "." table) |
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1737 (modify-syntax-entry ?& "." table) |
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1738 (modify-syntax-entry ?| "." table) |
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1739 (modify-syntax-entry ?` "w" table) |
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1740 (modify-syntax-entry ?_ "w" table) |
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1741 (modify-syntax-entry ?\' "." table) |
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1742 |
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1743 ;; Set up TABLE to handle block and line style comments. |
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1744 (if (featurep 'xemacs) |
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1745 (progn |
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1746 ;; XEmacs (formerly Lucid) has the best implementation |
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1747 (modify-syntax-entry ?/ ". 1456" table) |
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1748 (modify-syntax-entry ?* ". 23" table) |
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1749 (modify-syntax-entry ?\n "> b" table)) |
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1750 ;; Emacs 19 does things differently, but we can work with it |
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1751 (modify-syntax-entry ?/ ". 124b" table) |
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1752 (modify-syntax-entry ?* ". 23" table) |
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1753 (modify-syntax-entry ?\n "> b" table)) |
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1754 table) |
79545 | 1755 "Syntax table used in `verilog-mode' buffers.") |
1756 | |
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1757 (defvar verilog-font-lock-keywords nil |
79545 | 1758 "Default highlighting for Verilog mode.") |
1759 | |
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1760 (defvar verilog-font-lock-keywords-1 nil |
79545 | 1761 "Subdued level highlighting for Verilog mode.") |
1762 | |
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1763 (defvar verilog-font-lock-keywords-2 nil |
79545 | 1764 "Medium level highlighting for Verilog mode. |
1765 See also `verilog-font-lock-extra-types'.") | |
1766 | |
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1767 (defvar verilog-font-lock-keywords-3 nil |
79545 | 1768 "Gaudy level highlighting for Verilog mode. |
1769 See also `verilog-font-lock-extra-types'.") | |
1770 (defvar verilog-font-lock-translate-off-face | |
1771 'verilog-font-lock-translate-off-face | |
1772 "Font to use for translated off regions.") | |
1773 (defface verilog-font-lock-translate-off-face | |
1774 '((((class color) | |
1775 (background light)) | |
1776 (:background "gray90" :italic t )) | |
1777 (((class color) | |
1778 (background dark)) | |
1779 (:background "gray10" :italic t )) | |
1780 (((class grayscale) (background light)) | |
1781 (:foreground "DimGray" :italic t)) | |
1782 (((class grayscale) (background dark)) | |
1783 (:foreground "LightGray" :italic t)) | |
1784 (t (:italis t))) | |
1785 "Font lock mode face used to background highlight translate-off regions." | |
1786 :group 'font-lock-highlighting-faces) | |
1787 | |
1788 (defvar verilog-font-lock-p1800-face | |
1789 'verilog-font-lock-p1800-face | |
1790 "Font to use for p1800 keywords.") | |
1791 (defface verilog-font-lock-p1800-face | |
1792 '((((class color) | |
1793 (background light)) | |
1794 (:foreground "DarkOrange3" :bold t )) | |
1795 (((class color) | |
1796 (background dark)) | |
1797 (:foreground "orange1" :bold t )) | |
1798 (t (:italic t))) | |
1799 "Font lock mode face used to highlight P1800 keywords." | |
1800 :group 'font-lock-highlighting-faces) | |
1801 | |
1802 (defvar verilog-font-lock-ams-face | |
1803 'verilog-font-lock-ams-face | |
1804 "Font to use for Analog/Mixed Signal keywords.") | |
1805 (defface verilog-font-lock-ams-face | |
1806 '((((class color) | |
1807 (background light)) | |
1808 (:foreground "Purple" :bold t )) | |
1809 (((class color) | |
1810 (background dark)) | |
1811 (:foreground "orange1" :bold t )) | |
1812 (t (:italic t))) | |
1813 "Font lock mode face used to highlight AMS keywords." | |
1814 :group 'font-lock-highlighting-faces) | |
1815 | |
1816 (let* ((verilog-type-font-keywords | |
1817 (eval-when-compile | |
1818 (verilog-regexp-opt | |
1819 '( | |
1820 "and" "bit" "buf" "bufif0" "bufif1" "cmos" "defparam" | |
1821 "event" "genvar" "inout" "input" "integer" "localparam" | |
1822 "logic" "mailbox" "nand" "nmos" "not" "notif0" "notif1" "or" | |
1823 "output" "parameter" "pmos" "pull0" "pull1" "pullup" | |
1824 "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran" | |
1825 "rtranif0" "rtranif1" "semaphore" "signed" "struct" "supply" | |
1826 "supply0" "supply1" "time" "tran" "tranif0" "tranif1" | |
1827 "tri" "tri0" "tri1" "triand" "trior" "trireg" "typedef" | |
1828 "uwire" "vectored" "wand" "wire" "wor" "xnor" "xor" | |
1829 ) nil ))) | |
1830 | |
1831 (verilog-pragma-keywords | |
1832 (eval-when-compile | |
1833 (verilog-regexp-opt | |
1834 '("surefire" "synopsys" "rtl_synthesis" "verilint" ) nil | |
1835 ))) | |
1836 | |
1837 (verilog-p1800-keywords | |
1838 (eval-when-compile | |
1839 (verilog-regexp-opt | |
1840 '("alias" "assert" "assume" "automatic" "before" "bind" | |
1841 "bins" "binsof" "break" "byte" "cell" "chandle" "class" | |
1842 "clocking" "config" "const" "constraint" "context" "continue" | |
1843 "cover" "covergroup" "coverpoint" "cross" "deassign" "design" | |
1844 "dist" "do" "edge" "endclass" "endclocking" "endconfig" | |
1845 "endgroup" "endprogram" "endproperty" "endsequence" "enum" | |
1846 "expect" "export" "extends" "extern" "first_match" "foreach" | |
1847 "forkjoin" "genvar" "highz0" "highz1" "ifnone" "ignore_bins" | |
1848 "illegal_bins" "import" "incdir" "include" "inside" "instance" | |
1849 "int" "intersect" "large" "liblist" "library" "local" "longint" | |
1850 "matches" "medium" "modport" "new" "noshowcancelled" "null" | |
1851 "packed" "program" "property" "protected" "pull0" "pull1" | |
1852 "pulsestyle_onevent" "pulsestyle_ondetect" "pure" "rand" "randc" | |
1853 "randcase" "randsequence" "ref" "release" "return" "scalared" | |
1854 "sequence" "shortint" "shortreal" "showcancelled" "small" "solve" | |
1855 "specparam" "static" "string" "strong0" "strong1" "struct" | |
1856 "super" "tagged" "this" "throughout" "timeprecision" "timeunit" | |
1857 "type" "union" "unsigned" "use" "var" "virtual" "void" | |
1858 "wait_order" "weak0" "weak1" "wildcard" "with" "within" | |
1859 ) nil ))) | |
1860 | |
1861 (verilog-ams-keywords | |
1862 (eval-when-compile | |
1863 (verilog-regexp-opt | |
1864 '("above" "abs" "absdelay" "acos" "acosh" "ac_stim" | |
1865 "aliasparam" "analog" "analysis" "asin" "asinh" "atan" "atan2" "atanh" | |
1866 "branch" "ceil" "connectmodule" "connectrules" "cos" "cosh" "ddt" | |
1867 "ddx" "discipline" "driver_update" "enddiscipline" "endconnectrules" | |
1868 "endnature" "endparamset" "exclude" "exp" "final_step" "flicker_noise" | |
1869 "floor" "flow" "from" "ground" "hypot" "idt" "idtmod" "inf" | |
1870 "initial_step" "laplace_nd" "laplace_np" "laplace_zd" "laplace_zp" | |
1871 "last_crossing" "limexp" "ln" "log" "max" "min" "nature" | |
1872 "net_resolution" "noise_table" "paramset" "potential" "pow" "sin" | |
1873 "sinh" "slew" "sqrt" "tan" "tanh" "timer" "transition" "white_noise" | |
1874 "wreal" "zi_nd" "zi_np" "zi_zd" ) nil ))) | |
1875 | |
1876 (verilog-font-keywords | |
1877 (eval-when-compile | |
1878 (verilog-regexp-opt | |
1879 '( | |
1880 "assign" "begin" "case" "casex" "casez" "randcase" "deassign" | |
1881 "default" "disable" "else" "end" "endcase" "endfunction" | |
1882 "endgenerate" "endinterface" "endmodule" "endprimitive" | |
1883 "endspecify" "endtable" "endtask" "final" "for" "force" "return" "break" | |
1884 "continue" "forever" "fork" "function" "generate" "if" "iff" "initial" | |
1885 "interface" "join" "join_any" "join_none" "macromodule" "module" "negedge" | |
1886 "package" "endpackage" "always" "always_comb" "always_ff" | |
1887 "always_latch" "posedge" "primitive" "priority" "release" | |
1888 "repeat" "specify" "table" "task" "unique" "wait" "while" | |
1889 "class" "program" "endclass" "endprogram" | |
1890 ) nil )))) | |
1891 | |
1892 (setq verilog-font-lock-keywords | |
1893 (list | |
1894 ;; Fontify all builtin keywords | |
1895 (concat "\\<\\(" verilog-font-keywords "\\|" | |
1896 ;; And user/system tasks and functions | |
1897 "\\$[a-zA-Z][a-zA-Z0-9_\\$]*" | |
1898 "\\)\\>") | |
1899 ;; Fontify all types | |
1900 (cons (concat "\\<\\(" verilog-type-font-keywords "\\)\\>") | |
1901 'font-lock-type-face) | |
1902 ;; Fontify IEEE-P1800 keywords appropriately | |
1903 (if verilog-highlight-p1800-keywords | |
1904 (cons (concat "\\<\\(" verilog-p1800-keywords "\\)\\>") | |
1905 'verilog-font-lock-p1800-face) | |
1906 (cons (concat "\\<\\(" verilog-p1800-keywords "\\)\\>") | |
1907 'font-lock-type-face)) | |
1908 ;; Fontify Verilog-AMS keywords | |
1909 (cons (concat "\\<\\(" verilog-ams-keywords "\\)\\>") | |
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1910 'verilog-font-lock-ams-face))) |
79545 | 1911 |
1912 (setq verilog-font-lock-keywords-1 | |
1913 (append verilog-font-lock-keywords | |
1914 (list | |
1915 ;; Fontify module definitions | |
1916 (list | |
1917 "\\<\\(\\(macro\\)?module\\|primitive\\|class\\|program\\|interface\\|package\\|task\\)\\>\\s-*\\(\\sw+\\)" | |
1918 '(1 font-lock-keyword-face) | |
1919 '(3 font-lock-function-name-face 'prepend)) | |
1920 ;; Fontify function definitions | |
1921 (list | |
1922 (concat "\\<function\\>\\s-+\\(integer\\|real\\(time\\)?\\|time\\)\\s-+\\(\\sw+\\)" ) | |
1923 '(1 font-lock-keyword-face) | |
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1924 '(3 font-lock-reference-face prepend)) |
79545 | 1925 '("\\<function\\>\\s-+\\(\\[[^]]+\\]\\)\\s-+\\(\\sw+\\)" |
1926 (1 font-lock-keyword-face) | |
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1927 (2 font-lock-reference-face append)) |
79545 | 1928 '("\\<function\\>\\s-+\\(\\sw+\\)" |
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1929 1 'font-lock-reference-face append)))) |
79545 | 1930 |
1931 (setq verilog-font-lock-keywords-2 | |
1932 (append verilog-font-lock-keywords-1 | |
1933 (list | |
1934 ;; Fontify pragmas | |
1935 (concat "\\(//\\s-*" verilog-pragma-keywords "\\s-.*\\)") | |
1936 ;; Fontify escaped names | |
1937 '("\\(\\\\\\S-*\\s-\\)" 0 font-lock-function-name-face) | |
1938 ;; Fontify macro definitions/ uses | |
1939 '("`\\s-*[A-Za-z][A-Za-z0-9_]*" 0 (if (boundp 'font-lock-preprocessor-face) | |
1940 'font-lock-preprocessor-face | |
1941 'font-lock-type-face)) | |
1942 ;; Fontify delays/numbers | |
1943 '("\\(@\\)\\|\\(#\\s-*\\(\\(\[0-9_.\]+\\('s?[hdxbo][0-9a-fA-F_xz]*\\)?\\)\\|\\(([^()]+)\\|\\sw+\\)\\)\\)" | |
1944 0 font-lock-type-face append) | |
1945 ;; Fontify instantiation names | |
1946 '("\\([A-Za-z][A-Za-z0-9_]+\\)\\s-*(" 1 font-lock-function-name-face) | |
1947 ))) | |
1948 | |
1949 (setq verilog-font-lock-keywords-3 | |
1950 (append verilog-font-lock-keywords-2 | |
1951 (when verilog-highlight-translate-off | |
1952 (list | |
1953 ;; Fontify things in translate off regions | |
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1954 '(verilog-match-translate-off |
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1955 (0 'verilog-font-lock-translate-off-face prepend)) |
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1956 ))))) |
79545 | 1957 |
1958 | |
1959 (defun verilog-inside-comment-p () | |
1960 "Check if point inside a nested comment." | |
1961 (save-excursion | |
1962 (let ((st-point (point)) hitbeg) | |
1963 (or (search-backward "//" (verilog-get-beg-of-line) t) | |
1964 (if (progn | |
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1965 ;; This is for tricky case //*, we keep searching if /* |
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1966 ;; is proceeded by // on same line. |
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1967 (while |
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1968 (and (setq hitbeg (search-backward "/*" nil t)) |
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1969 (progn |
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1970 (forward-char 1) |
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1971 (search-backward "//" (verilog-get-beg-of-line) t)))) |
79545 | 1972 hitbeg) |
1973 (not (search-forward "*/" st-point t))))))) | |
1974 | |
1975 (defun verilog-declaration-end () | |
1976 (search-forward ";")) | |
1977 | |
1978 (defun verilog-point-text (&optional pointnum) | |
1979 "Return text describing where POINTNUM or current point is (for errors). | |
1980 Use filename, if current buffer being edited shorten to just buffer name." | |
1981 (concat (or (and (equal (window-buffer (selected-window)) (current-buffer)) | |
1982 (buffer-name)) | |
1983 buffer-file-name | |
1984 (buffer-name)) | |
1985 ":" (int-to-string (count-lines (point-min) (or pointnum (point)))))) | |
1986 | |
1987 (defun electric-verilog-backward-sexp () | |
1988 "Move backward over a sexp." | |
1989 (interactive) | |
1990 ;; before that see if we are in a comment | |
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1991 (verilog-backward-sexp)) |
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1992 |
79545 | 1993 (defun electric-verilog-forward-sexp () |
1994 "Move backward over a sexp." | |
1995 (interactive) | |
1996 ;; before that see if we are in a comment | |
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1997 (verilog-forward-sexp)) |
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1998 |
79545 | 1999 ;;;used by hs-minor-mode |
2000 (defun verilog-forward-sexp-function (arg) | |
2001 (if (< arg 0) | |
2002 (verilog-backward-sexp) | |
2003 (verilog-forward-sexp))) | |
2004 | |
2005 | |
2006 (defun verilog-backward-sexp () | |
2007 (let ((reg) | |
2008 (elsec 1) | |
2009 (found nil) | |
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2010 (st (point))) |
79545 | 2011 (if (not (looking-at "\\<")) |
2012 (forward-word -1)) | |
2013 (cond | |
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2014 ((verilog-skip-backward-comment-or-string)) |
79545 | 2015 ((looking-at "\\<else\\>") |
2016 (setq reg (concat | |
2017 verilog-end-block-re | |
2018 "\\|\\(\\<else\\>\\)" | |
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2019 "\\|\\(\\<if\\>\\)")) |
79545 | 2020 (while (and (not found) |
2021 (verilog-re-search-backward reg nil 'move)) | |
2022 (cond | |
2023 ((match-end 1) ; matched verilog-end-block-re | |
2024 ; try to leap back to matching outward block by striding across | |
2025 ; indent level changing tokens then immediately | |
2026 ; previous line governs indentation. | |
2027 (verilog-leap-to-head)) | |
2028 ((match-end 2) ; else, we're in deep | |
2029 (setq elsec (1+ elsec))) | |
2030 ((match-end 3) ; found it | |
2031 (setq elsec (1- elsec)) | |
2032 (if (= 0 elsec) | |
2033 ;; Now previous line describes syntax | |
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2034 (setq found 't)))))) |
79545 | 2035 ((looking-at verilog-end-block-re) |
2036 (verilog-leap-to-head)) | |
2037 ((looking-at "\\(endmodule\\>\\)\\|\\(\\<endprimitive\\>\\)\\|\\(\\<endclass\\>\\)\\|\\(\\<endprogram\\>\\)\\|\\(\\<endinterface\\>\\)\\|\\(\\<endpackage\\>\\)") | |
2038 (cond | |
2039 ((match-end 1) | |
2040 (verilog-re-search-backward "\\<\\(macro\\)?module\\>" nil 'move)) | |
2041 ((match-end 2) | |
2042 (verilog-re-search-backward "\\<primitive\\>" nil 'move)) | |
2043 ((match-end 3) | |
2044 (verilog-re-search-backward "\\<class\\>" nil 'move)) | |
2045 ((match-end 4) | |
2046 (verilog-re-search-backward "\\<program\\>" nil 'move)) | |
2047 ((match-end 5) | |
2048 (verilog-re-search-backward "\\<interface\\>" nil 'move)) | |
2049 ((match-end 6) | |
2050 (verilog-re-search-backward "\\<package\\>" nil 'move)) | |
2051 (t | |
2052 (goto-char st) | |
2053 (backward-sexp 1)))) | |
2054 (t | |
2055 (goto-char st) | |
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2056 (backward-sexp))))) |
79545 | 2057 |
2058 (defun verilog-forward-sexp () | |
2059 (let ((reg) | |
2060 (md 2) | |
2061 (st (point))) | |
2062 (if (not (looking-at "\\<")) | |
2063 (forward-word -1)) | |
2064 (cond | |
2065 ((verilog-skip-forward-comment-or-string) | |
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2066 (verilog-forward-syntactic-ws)) |
79545 | 2067 ((looking-at verilog-beg-block-re-ordered);; begin|case|fork|class|table|specify|function|task|generate|covergroup|property|sequence|clocking |
2068 (cond | |
2069 ((match-end 1) ; end | |
2070 ;; Search forward for matching begin | |
2071 (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" )) | |
2072 ((match-end 2) ; endcase | |
2073 ;; Search forward for matching case | |
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2074 (setq reg "\\(\\<randcase\\>\\|\\(\\<unique\\>\\s-+\\|\\<priority\\>\\s-+\\)?\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" )) |
79545 | 2075 ((match-end 3) ; join |
2076 ;; Search forward for matching fork | |
2077 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" )) | |
2078 ((match-end 4) ; endclass | |
2079 ;; Search forward for matching class | |
2080 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" )) | |
2081 ((match-end 5) ; endtable | |
2082 ;; Search forward for matching table | |
2083 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" )) | |
2084 ((match-end 6) ; endspecify | |
2085 ;; Search forward for matching specify | |
2086 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" )) | |
2087 ((match-end 7) ; endfunction | |
2088 ;; Search forward for matching function | |
2089 (setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" )) | |
2090 ((match-end 8) ; endtask | |
2091 ;; Search forward for matching task | |
2092 (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" )) | |
2093 ((match-end 9) ; endgenerate | |
2094 ;; Search forward for matching generate | |
2095 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" )) | |
2096 ((match-end 10) ; endgroup | |
2097 ;; Search forward for matching covergroup | |
2098 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" )) | |
2099 ((match-end 11) ; endproperty | |
2100 ;; Search forward for matching property | |
2101 (setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" )) | |
2102 ((match-end 12) ; endsequence | |
2103 ;; Search forward for matching sequence | |
2104 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" ) | |
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2105 (setq md 3)) ; 3 to get to endsequence in the reg above |
79545 | 2106 ((match-end 13) ; endclocking |
2107 ;; Search forward for matching clocking | |
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2108 (setq reg "\\(\\<clocking\\>\\)\\|\\(\\<endclocking\\>\\)" ))) |
79545 | 2109 (if (forward-word 1) |
2110 (catch 'skip | |
2111 (let ((nest 1)) | |
2112 (while (verilog-re-search-forward reg nil 'move) | |
2113 (cond | |
2114 ((match-end md) ; the closer in reg, so we are climbing out | |
2115 (setq nest (1- nest)) | |
2116 (if (= 0 nest) ; we are out! | |
2117 (throw 'skip 1))) | |
2118 ((match-end 1) ; the opener in reg, so we are deeper now | |
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2119 (setq nest (1+ nest))))))))) |
79545 | 2120 ((looking-at (concat |
2121 "\\(\\<\\(macro\\)?module\\>\\)\\|" | |
2122 "\\(\\<primitive\\>\\)\\|" | |
2123 "\\(\\<class\\>\\)\\|" | |
2124 "\\(\\<program\\>\\)\\|" | |
2125 "\\(\\<interface\\>\\)\\|" | |
2126 "\\(\\<package\\>\\)")) | |
2127 (cond | |
2128 ((match-end 1) | |
2129 (verilog-re-search-forward "\\<endmodule\\>" nil 'move)) | |
2130 ((match-end 2) | |
2131 (verilog-re-search-forward "\\<endprimitive\\>" nil 'move)) | |
2132 ((match-end 3) | |
2133 (verilog-re-search-forward "\\<endclass\\>" nil 'move)) | |
2134 ((match-end 4) | |
2135 (verilog-re-search-forward "\\<endprogram\\>" nil 'move)) | |
2136 ((match-end 5) | |
2137 (verilog-re-search-forward "\\<endinterface\\>" nil 'move)) | |
2138 ((match-end 6) | |
2139 (verilog-re-search-forward "\\<endpackage\\>" nil 'move)) | |
2140 (t | |
2141 (goto-char st) | |
2142 (if (= (following-char) ?\) ) | |
2143 (forward-char 1) | |
2144 (forward-sexp 1))))) | |
2145 (t | |
2146 (goto-char st) | |
2147 (if (= (following-char) ?\) ) | |
2148 (forward-char 1) | |
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2149 (forward-sexp 1)))))) |
79545 | 2150 |
2151 (defun verilog-declaration-beg () | |
2152 (verilog-re-search-backward verilog-declaration-re (bobp) t)) | |
2153 | |
2154 (defun verilog-font-lock-init () | |
2155 "Initialize fontification." | |
2156 ;; highlight keywords and standardized types, attributes, enumeration | |
2157 ;; values, and subprograms | |
2158 (setq verilog-font-lock-keywords-3 | |
2159 (append verilog-font-lock-keywords-2 | |
2160 (when verilog-highlight-translate-off | |
2161 (list | |
2162 ;; Fontify things in translate off regions | |
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2163 '(verilog-match-translate-off |
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2164 (0 'verilog-font-lock-translate-off-face prepend)))))) |
79545 | 2165 (put 'verilog-mode 'font-lock-defaults |
2166 '((verilog-font-lock-keywords | |
2167 verilog-font-lock-keywords-1 | |
2168 verilog-font-lock-keywords-2 | |
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2169 verilog-font-lock-keywords-3) |
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2170 nil ; nil means highlight strings & comments as well as keywords |
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2171 nil ; nil means keywords must match case |
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2172 nil ; syntax table handled elsewhere |
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2173 ;; Function to move to beginning of reasonable region to highlight |
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2174 verilog-beg-of-defun))) |
79545 | 2175 |
2176 ;; initialize fontification for Verilog Mode | |
2177 (verilog-font-lock-init) | |
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2178 |
79545 | 2179 ;; |
2180 ;; | |
2181 ;; Mode | |
2182 ;; | |
2183 (defvar verilog-which-tool 1) | |
79546 | 2184 ;;;###autoload |
79545 | 2185 (defun verilog-mode () |
2186 "Major mode for editing Verilog code. | |
2187 \\<verilog-mode-map> | |
2188 See \\[describe-function] verilog-auto (\\[verilog-auto]) for details on how | |
2189 AUTOs can improve coding efficiency. | |
2190 | |
2191 Use \\[verilog-faq] for a pointer to frequently asked questions. | |
2192 | |
2193 NEWLINE, TAB indents for Verilog code. | |
2194 Delete converts tabs to spaces as it moves back. | |
2195 | |
2196 Supports highlighting. | |
2197 | |
2198 Turning on Verilog mode calls the value of the variable `verilog-mode-hook' | |
2199 with no args, if that value is non-nil. | |
2200 | |
2201 Variables controlling indentation/edit style: | |
2202 | |
2203 variable `verilog-indent-level' (default 3) | |
2204 Indentation of Verilog statements with respect to containing block. | |
2205 `verilog-indent-level-module' (default 3) | |
2206 Absolute indentation of Module level Verilog statements. | |
2207 Set to 0 to get initial and always statements lined up | |
2208 on the left side of your screen. | |
2209 `verilog-indent-level-declaration' (default 3) | |
2210 Indentation of declarations with respect to containing block. | |
2211 Set to 0 to get them list right under containing block. | |
2212 `verilog-indent-level-behavioral' (default 3) | |
2213 Indentation of first begin in a task or function block | |
2214 Set to 0 to get such code to lined up underneath the task or function keyword | |
2215 `verilog-indent-level-directive' (default 1) | |
2216 Indentation of `ifdef/`endif blocks | |
2217 `verilog-cexp-indent' (default 1) | |
2218 Indentation of Verilog statements broken across lines i.e.: | |
2219 if (a) | |
2220 begin | |
2221 `verilog-case-indent' (default 2) | |
2222 Indentation for case statements. | |
2223 `verilog-auto-newline' (default nil) | |
2224 Non-nil means automatically newline after semicolons and the punctuation | |
2225 mark after an end. | |
2226 `verilog-auto-indent-on-newline' (default t) | |
2227 Non-nil means automatically indent line after newline | |
2228 `verilog-tab-always-indent' (default t) | |
2229 Non-nil means TAB in Verilog mode should always reindent the current line, | |
2230 regardless of where in the line point is when the TAB command is used. | |
2231 `verilog-indent-begin-after-if' (default t) | |
2232 Non-nil means to indent begin statements following a preceding | |
2233 if, else, while, for and repeat statements, if any. otherwise, | |
2234 the begin is lined up with the preceding token. If t, you get: | |
2235 if (a) | |
2236 begin // amount of indent based on `verilog-cexp-indent' | |
2237 otherwise you get: | |
2238 if (a) | |
2239 begin | |
2240 `verilog-auto-endcomments' (default t) | |
2241 Non-nil means a comment /* ... */ is set after the ends which ends | |
2242 cases, tasks, functions and modules. | |
2243 The type and name of the object will be set between the braces. | |
2244 `verilog-minimum-comment-distance' (default 10) | |
2245 Minimum distance (in lines) between begin and end required before a comment | |
2246 will be inserted. Setting this variable to zero results in every | |
2247 end acquiring a comment; the default avoids too many redundant | |
2248 comments in tight quarters. | |
2249 `verilog-auto-lineup' (default `(all)) | |
2250 List of contexts where auto lineup of code should be done. | |
2251 | |
2252 Variables controlling other actions: | |
2253 | |
2254 `verilog-linter' (default surelint) | |
2255 Unix program to call to run the lint checker. This is the default | |
2256 command for \\[compile-command] and \\[verilog-auto-save-compile]. | |
2257 | |
2258 See \\[customize] for the complete list of variables. | |
2259 | |
2260 AUTO expansion functions are, in part: | |
2261 | |
2262 \\[verilog-auto] Expand AUTO statements. | |
2263 \\[verilog-delete-auto] Remove the AUTOs. | |
2264 \\[verilog-inject-auto] Insert AUTOs for the first time. | |
2265 | |
2266 Some other functions are: | |
2267 | |
2268 \\[verilog-complete-word] Complete word with appropriate possibilities. | |
2269 \\[verilog-mark-defun] Mark function. | |
2270 \\[verilog-beg-of-defun] Move to beginning of current function. | |
2271 \\[verilog-end-of-defun] Move to end of current function. | |
2272 \\[verilog-label-be] Label matching begin ... end, fork ... join, etc statements. | |
2273 | |
2274 \\[verilog-comment-region] Put marked area in a comment. | |
2275 \\[verilog-uncomment-region] Uncomment an area commented with \\[verilog-comment-region]. | |
2276 \\[verilog-insert-block] Insert begin ... end;. | |
2277 \\[verilog-star-comment] Insert /* ... */. | |
2278 | |
2279 \\[verilog-sk-always] Insert a always @(AS) begin .. end block. | |
2280 \\[verilog-sk-begin] Insert a begin .. end block. | |
2281 \\[verilog-sk-case] Insert a case block, prompting for details. | |
2282 \\[verilog-sk-for] Insert a for (...) begin .. end block, prompting for details. | |
2283 \\[verilog-sk-generate] Insert a generate .. endgenerate block. | |
2284 \\[verilog-sk-header] Insert a nice header block at the top of file. | |
2285 \\[verilog-sk-initial] Insert an initial begin .. end block. | |
2286 \\[verilog-sk-fork] Insert a fork begin .. end .. join block. | |
2287 \\[verilog-sk-module] Insert a module .. (/*AUTOARG*/);.. endmodule block. | |
2288 \\[verilog-sk-primitive] Insert a primitive .. (.. );.. endprimitive block. | |
2289 \\[verilog-sk-repeat] Insert a repeat (..) begin .. end block. | |
2290 \\[verilog-sk-specify] Insert a specify .. endspecify block. | |
2291 \\[verilog-sk-task] Insert a task .. begin .. end endtask block. | |
2292 \\[verilog-sk-while] Insert a while (...) begin .. end block, prompting for details. | |
2293 \\[verilog-sk-casex] Insert a casex (...) item: begin.. end endcase block, prompting for details. | |
2294 \\[verilog-sk-casez] Insert a casez (...) item: begin.. end endcase block, prompting for details. | |
2295 \\[verilog-sk-if] Insert an if (..) begin .. end block. | |
2296 \\[verilog-sk-else-if] Insert an else if (..) begin .. end block. | |
2297 \\[verilog-sk-comment] Insert a comment block. | |
2298 \\[verilog-sk-assign] Insert an assign .. = ..; statement. | |
2299 \\[verilog-sk-function] Insert a function .. begin .. end endfunction block. | |
2300 \\[verilog-sk-input] Insert an input declaration, prompting for details. | |
2301 \\[verilog-sk-output] Insert an output declaration, prompting for details. | |
2302 \\[verilog-sk-state-machine] Insert a state machine definition, prompting for details. | |
2303 \\[verilog-sk-inout] Insert an inout declaration, prompting for details. | |
2304 \\[verilog-sk-wire] Insert a wire declaration, prompting for details. | |
2305 \\[verilog-sk-reg] Insert a register declaration, prompting for details. | |
2306 \\[verilog-sk-define-signal] Define signal under point as a register at the top of the module. | |
2307 | |
2308 All key bindings can be seen in a Verilog-buffer with \\[describe-bindings]. | |
2309 Key bindings specific to `verilog-mode-map' are: | |
2310 | |
2311 \\{verilog-mode-map}" | |
2312 (interactive) | |
2313 (kill-all-local-variables) | |
2314 (use-local-map verilog-mode-map) | |
2315 (setq major-mode 'verilog-mode) | |
2316 (setq mode-name "Verilog") | |
2317 (setq local-abbrev-table verilog-mode-abbrev-table) | |
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2318 (set (make-local-variable 'beginning-of-defun-function) |
79546 | 2319 'verilog-beg-of-defun) |
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2320 (set (make-local-variable 'end-of-defun-function) |
79546 | 2321 'verilog-end-of-defun) |
79545 | 2322 (set-syntax-table verilog-mode-syntax-table) |
2323 (make-local-variable 'indent-line-function) | |
2324 (setq indent-line-function 'verilog-indent-line-relative) | |
2325 (setq comment-indent-function 'verilog-comment-indent) | |
2326 (make-local-variable 'parse-sexp-ignore-comments) | |
2327 (setq parse-sexp-ignore-comments nil) | |
2328 (make-local-variable 'comment-start) | |
2329 (make-local-variable 'comment-end) | |
2330 (make-local-variable 'comment-multi-line) | |
2331 (make-local-variable 'comment-start-skip) | |
2332 (setq comment-start "// " | |
2333 comment-end "" | |
2334 comment-start-skip "/\\*+ *\\|// *" | |
2335 comment-multi-line nil) | |
2336 ;; Set up for compilation | |
2337 (setq verilog-which-tool 1) | |
2338 (setq verilog-tool 'verilog-linter) | |
2339 (verilog-set-compile-command) | |
2340 (when (boundp 'hack-local-variables-hook) ;; Also modify any file-local-variables | |
2341 (add-hook 'hack-local-variables-hook 'verilog-modify-compile-command t)) | |
2342 | |
2343 ;; Setting up menus | |
79546 | 2344 (when (featurep 'xemacs) |
2345 (when (and current-menubar | |
2346 (not (assoc "Verilog" current-menubar))) | |
2347 ;; (set-buffer-menubar (copy-sequence current-menubar)) | |
2348 (add-submenu nil verilog-xemacs-menu) | |
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2349 (add-submenu nil verilog-stmt-menu))) |
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2350 |
79545 | 2351 ;; Stuff for GNU emacs |
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2352 (set (make-local-variable 'font-lock-defaults) |
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2353 '((verilog-font-lock-keywords verilog-font-lock-keywords-1 |
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2354 verilog-font-lock-keywords-2 |
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2355 verilog-font-lock-keywords-3) |
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2356 nil nil nil verilog-beg-of-defun)) |
79545 | 2357 ;;------------------------------------------------------------ |
2358 ;; now hook in 'verilog-colorize-include-files (eldo-mode.el&spice-mode.el) | |
2359 ;; all buffer local: | |
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2360 (when (featurep 'xemacs) |
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2361 (make-local-hook 'font-lock-mode-hook) |
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2362 (make-local-hook 'font-lock-after-fontify-buffer-hook); doesn't exist in emacs 20 |
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2363 (make-local-hook 'after-change-functions)) |
79545 | 2364 (add-hook 'font-lock-mode-hook 'verilog-colorize-include-files-buffer t t) |
2365 (add-hook 'font-lock-after-fontify-buffer-hook 'verilog-colorize-include-files-buffer t t) ; not in emacs 20 | |
2366 (add-hook 'after-change-functions 'verilog-colorize-include-files t t) | |
2367 | |
2368 ;; Tell imenu how to handle verilog. | |
2369 (make-local-variable 'imenu-generic-expression) | |
2370 (setq imenu-generic-expression verilog-imenu-generic-expression) | |
2371 ;; hideshow support | |
2372 (unless (assq 'verilog-mode hs-special-modes-alist) | |
2373 (setq hs-special-modes-alist | |
2374 (cons '(verilog-mode-mode "\\<begin\\>" "\\<end\\>" nil | |
2375 verilog-forward-sexp-function) | |
2376 hs-special-modes-alist))) | |
2377 | |
2378 ;; Stuff for autos | |
2379 (add-hook 'write-contents-hooks 'verilog-auto-save-check) ; already local | |
2380 ;; (verilog-auto-reeval-locals t) ; Save locals in case user changes them | |
2381 ;; (verilog-getopt-flags) | |
2382 (run-hooks 'verilog-mode-hook)) | |
2383 | |
2384 | |
2385 ;; | |
2386 ;; Electric functions | |
2387 ;; | |
2388 (defun electric-verilog-terminate-line (&optional arg) | |
2389 "Terminate line and indent next line. | |
2390 With optional ARG, remove existing end of line comments." | |
2391 (interactive) | |
2392 ;; before that see if we are in a comment | |
2393 (let ((state | |
2394 (save-excursion | |
2395 (parse-partial-sexp (point-min) (point))))) | |
2396 (cond | |
2397 ((nth 7 state) ; Inside // comment | |
2398 (if (eolp) | |
2399 (progn | |
2400 (delete-horizontal-space) | |
2401 (newline)) | |
2402 (progn | |
2403 (newline) | |
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2404 (insert "// ") |
79545 | 2405 (beginning-of-line))) |
2406 (verilog-indent-line)) | |
2407 ((nth 4 state) ; Inside any comment (hence /**/) | |
2408 (newline) | |
2409 (verilog-more-comment)) | |
2410 ((eolp) | |
2411 ;; First, check if current line should be indented | |
2412 (if (save-excursion | |
2413 (delete-horizontal-space) | |
2414 (beginning-of-line) | |
2415 (skip-chars-forward " \t") | |
2416 (if (looking-at verilog-auto-end-comment-lines-re) | |
2417 (let ((indent-str (verilog-indent-line))) | |
2418 ;; Maybe we should set some endcomments | |
2419 (if verilog-auto-endcomments | |
2420 (verilog-set-auto-endcomments indent-str arg)) | |
2421 (end-of-line) | |
2422 (delete-horizontal-space) | |
2423 (if arg | |
2424 () | |
2425 (newline)) | |
2426 nil) | |
2427 (progn | |
2428 (end-of-line) | |
2429 (delete-horizontal-space) | |
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2430 't))) |
79545 | 2431 ;; see if we should line up assignments |
2432 (progn | |
2433 (if (or (memq 'all verilog-auto-lineup) | |
2434 (memq 'assignments verilog-auto-lineup)) | |
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2435 (verilog-pretty-expr)) |
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2436 (newline)) |
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2437 (forward-line 1)) |
79545 | 2438 ;; Indent next line |
2439 (if verilog-auto-indent-on-newline | |
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2440 (verilog-indent-line))) |
79545 | 2441 (t |
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2442 (newline))))) |
79545 | 2443 |
2444 (defun electric-verilog-terminate-and-indent () | |
2445 "Insert a newline and indent for the next statement." | |
2446 (interactive) | |
2447 (electric-verilog-terminate-line 1)) | |
2448 | |
2449 (defun electric-verilog-semi () | |
2450 "Insert `;' character and reindent the line." | |
2451 (interactive) | |
2452 (insert last-command-char) | |
2453 | |
2454 (if (or (verilog-in-comment-or-string-p) | |
2455 (verilog-in-escaped-name-p)) | |
2456 () | |
2457 (save-excursion | |
2458 (beginning-of-line) | |
2459 (verilog-forward-ws&directives) | |
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2460 (verilog-indent-line)) |
79545 | 2461 (if (and verilog-auto-newline |
2462 (not (verilog-parenthesis-depth))) | |
2463 (electric-verilog-terminate-line)))) | |
2464 | |
2465 (defun electric-verilog-semi-with-comment () | |
2466 "Insert `;' character, reindent the line and indent for comment." | |
2467 (interactive) | |
2468 (insert "\;") | |
2469 (save-excursion | |
2470 (beginning-of-line) | |
2471 (verilog-indent-line)) | |
2472 (indent-for-comment)) | |
2473 | |
2474 (defun electric-verilog-colon () | |
2475 "Insert `:' and do all indentations except line indent on this line." | |
2476 (interactive) | |
2477 (insert last-command-char) | |
2478 ;; Do nothing if within string. | |
2479 (if (or | |
2480 (verilog-within-string) | |
2481 (not (verilog-in-case-region-p))) | |
2482 () | |
2483 (save-excursion | |
2484 (let ((p (point)) | |
2485 (lim (progn (verilog-beg-of-statement) (point)))) | |
2486 (goto-char p) | |
2487 (verilog-backward-case-item lim) | |
2488 (verilog-indent-line))) | |
2489 ;; (let ((verilog-tab-always-indent nil)) | |
2490 ;; (verilog-indent-line)) | |
2491 )) | |
2492 | |
2493 ;;(defun electric-verilog-equal () | |
2494 ;; "Insert `=', and do indentation if within block." | |
2495 ;; (interactive) | |
2496 ;; (insert last-command-char) | |
2497 ;; Could auto line up expressions, but not yet | |
2498 ;; (if (eq (car (verilog-calculate-indent)) 'block) | |
2499 ;; (let ((verilog-tab-always-indent nil)) | |
2500 ;; (verilog-indent-command))) | |
2501 ;; ) | |
2502 | |
2503 (defun electric-verilog-tick () | |
2504 "Insert back-tick, and indent to column 0 if this is a CPP directive." | |
2505 (interactive) | |
2506 (insert last-command-char) | |
2507 (save-excursion | |
2508 (if (progn | |
2509 (beginning-of-line) | |
2510 (looking-at verilog-directive-re-1)) | |
2511 (verilog-indent-line)))) | |
2512 | |
2513 (defun electric-verilog-tab () | |
2514 "Function called when TAB is pressed in Verilog mode." | |
2515 (interactive) | |
2516 ;; If verilog-tab-always-indent, indent the beginning of the line. | |
2517 (if (or verilog-tab-always-indent | |
2518 (save-excursion | |
2519 (skip-chars-backward " \t") | |
2520 (bolp))) | |
2521 (let* ((oldpnt (point)) | |
2522 (boi-point | |
2523 (save-excursion | |
2524 (beginning-of-line) | |
2525 (skip-chars-forward " \t") | |
2526 (verilog-indent-line) | |
2527 (back-to-indentation) | |
2528 (point)))) | |
2529 (if (< (point) boi-point) | |
2530 (back-to-indentation) | |
2531 (cond ((not verilog-tab-to-comment)) | |
2532 ((not (eolp)) | |
2533 (end-of-line)) | |
2534 (t | |
2535 (indent-for-comment) | |
2536 (when (and (eolp) (= oldpnt (point))) | |
2537 ; kill existing comment | |
2538 (beginning-of-line) | |
2539 (re-search-forward comment-start-skip oldpnt 'move) | |
2540 (goto-char (match-beginning 0)) | |
2541 (skip-chars-backward " \t") | |
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2542 (kill-region (point) oldpnt)))))) |
79545 | 2543 (progn (insert "\t")))) |
2544 | |
2545 | |
2546 | |
2547 ;; | |
2548 ;; Interactive functions | |
2549 ;; | |
2550 | |
2551 (defun verilog-indent-buffer () | |
2552 "Indent-region the entire buffer as Verilog code. | |
2553 To call this from the command line, see \\[verilog-batch-indent]." | |
2554 (interactive) | |
2555 (verilog-mode) | |
2556 (indent-region (point-min) (point-max) nil)) | |
2557 | |
2558 (defun verilog-insert-block () | |
2559 "Insert Verilog begin ... end; block in the code with right indentation." | |
2560 (interactive) | |
2561 (verilog-indent-line) | |
2562 (insert "begin") | |
2563 (electric-verilog-terminate-line) | |
2564 (save-excursion | |
2565 (electric-verilog-terminate-line) | |
2566 (insert "end") | |
2567 (beginning-of-line) | |
2568 (verilog-indent-line))) | |
2569 | |
2570 (defun verilog-star-comment () | |
2571 "Insert Verilog star comment at point." | |
2572 (interactive) | |
2573 (verilog-indent-line) | |
2574 (insert "/*") | |
2575 (save-excursion | |
2576 (newline) | |
2577 (insert " */")) | |
2578 (newline) | |
2579 (insert " * ")) | |
2580 | |
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2581 (defun verilog-insert-1 (fmt max) |
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2582 "Use format string FMT to insert integers 0 to MAX - 1. |
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2583 Inserts one integer per line, at the current column. Stops early |
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2584 if it reaches the end of the buffer." |
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|
2585 (let ((col (current-column)) |
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|
2586 (n 0)) |
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|
2587 (save-excursion |
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|
2588 (while (< n max) |
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|
2589 (insert (format fmt n)) |
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|
2590 (forward-line 1) |
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|
2591 ;; Note that this function does not bother to check for lines |
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2592 ;; shorter than col. |
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|
2593 (if (eobp) |
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|
2594 (setq n max) |
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|
2595 (setq n (1+ n)) |
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|
2596 (move-to-column col)))))) |
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|
2597 |
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|
2598 (defun verilog-insert-indices (max) |
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|
2599 "Insert a set of indices into a rectangle. |
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2600 The upper left corner is defined by point. Indices begin with 0 |
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|
2601 and extend to the MAX - 1. If no prefix arg is given, the user |
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2602 is prompted for a value. The indices are surrounded by square |
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|
2603 brackets \[]. For example, the following code with the point |
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|
2604 located after the first 'a' gives: |
79545 | 2605 |
2606 a = b a[ 0] = b | |
2607 a = b a[ 1] = b | |
2608 a = b a[ 2] = b | |
2609 a = b a[ 3] = b | |
2610 a = b ==> insert-indices ==> a[ 4] = b | |
2611 a = b a[ 5] = b | |
2612 a = b a[ 6] = b | |
2613 a = b a[ 7] = b | |
2614 a = b a[ 8] = b" | |
2615 | |
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2616 (interactive "NMAX: ") |
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2617 (verilog-insert-1 "[%3d]" max)) |
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|
2618 |
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2619 (defun verilog-generate-numbers (max) |
79545 | 2620 "Insert a set of generated numbers into a rectangle. |
2621 The upper left corner is defined by point. The numbers are padded to three | |
2622 digits, starting with 000 and extending to (MAX - 1). If no prefix argument | |
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|
2623 is supplied, then the user is prompted for the MAX number. Consider the |
79545 | 2624 following code fragment: |
2625 | |
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|
2626 buf buf buf buf000 |
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|
2627 buf buf buf buf001 |
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|
2628 buf buf buf buf002 |
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|
2629 buf buf buf buf003 |
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|
2630 buf buf ==> generate-numbers ==> buf buf004 |
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|
2631 buf buf buf buf005 |
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|
2632 buf buf buf buf006 |
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|
2633 buf buf buf buf007 |
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|
2634 buf buf buf buf008" |
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|
2635 |
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|
2636 (interactive "NMAX: ") |
79691
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|
2637 (verilog-insert-1 "%3.3d" max)) |
79545 | 2638 |
2639 (defun verilog-mark-defun () | |
2640 "Mark the current verilog function (or procedure). | |
2641 This puts the mark at the end, and point at the beginning." | |
2642 (interactive) | |
79810
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|
2643 (when (featurep 'xemacs) |
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|
2644 (push-mark (point)) |
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|
2645 (verilog-end-of-defun) |
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|
2646 (push-mark (point)) |
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|
2647 (verilog-beg-of-defun) |
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|
2648 (if (fboundp 'zmacs-activate-region) |
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|
2649 (zmacs-activate-region)))) |
79545 | 2650 |
2651 (defun verilog-comment-region (start end) | |
2652 ; checkdoc-params: (start end) | |
2653 "Put the region into a Verilog comment. | |
2654 The comments that are in this area are \"deformed\": | |
2655 `*)' becomes `!(*' and `}' becomes `!{'. | |
2656 These deformed comments are returned to normal if you use | |
2657 \\[verilog-uncomment-region] to undo the commenting. | |
2658 | |
2659 The commented area starts with `verilog-exclude-str-start', and ends with | |
2660 `verilog-exclude-str-end'. But if you change these variables, | |
2661 \\[verilog-uncomment-region] won't recognize the comments." | |
2662 (interactive "r") | |
2663 (save-excursion | |
2664 ;; Insert start and endcomments | |
2665 (goto-char end) | |
2666 (if (and (save-excursion (skip-chars-forward " \t") (eolp)) | |
2667 (not (save-excursion (skip-chars-backward " \t") (bolp)))) | |
2668 (forward-line 1) | |
2669 (beginning-of-line)) | |
2670 (insert verilog-exclude-str-end) | |
2671 (setq end (point)) | |
2672 (newline) | |
2673 (goto-char start) | |
2674 (beginning-of-line) | |
2675 (insert verilog-exclude-str-start) | |
2676 (newline) | |
2677 ;; Replace end-comments within commented area | |
2678 (goto-char end) | |
2679 (save-excursion | |
2680 (while (re-search-backward "\\*/" start t) | |
2681 (replace-match "*-/" t t))) | |
2682 (save-excursion | |
2683 (let ((s+1 (1+ start))) | |
2684 (while (re-search-backward "/\\*" s+1 t) | |
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|
2685 (replace-match "/-*" t t)))))) |
79545 | 2686 |
2687 (defun verilog-uncomment-region () | |
2688 "Uncomment a commented area; change deformed comments back to normal. | |
2689 This command does nothing if the pointer is not in a commented | |
2690 area. See also `verilog-comment-region'." | |
2691 (interactive) | |
2692 (save-excursion | |
2693 (let ((start (point)) | |
2694 (end (point))) | |
2695 ;; Find the boundaries of the comment | |
2696 (save-excursion | |
2697 (setq start (progn (search-backward verilog-exclude-str-start nil t) | |
2698 (point))) | |
2699 (setq end (progn (search-forward verilog-exclude-str-end nil t) | |
2700 (point)))) | |
2701 ;; Check if we're really inside a comment | |
2702 (if (or (equal start (point)) (<= end (point))) | |
2703 (message "Not standing within commented area.") | |
2704 (progn | |
2705 ;; Remove endcomment | |
2706 (goto-char end) | |
2707 (beginning-of-line) | |
2708 (let ((pos (point))) | |
2709 (end-of-line) | |
2710 (delete-region pos (1+ (point)))) | |
2711 ;; Change comments back to normal | |
2712 (save-excursion | |
2713 (while (re-search-backward "\\*-/" start t) | |
2714 (replace-match "*/" t t))) | |
2715 (save-excursion | |
2716 (while (re-search-backward "/-\\*" start t) | |
2717 (replace-match "/*" t t))) | |
2718 ;; Remove start comment | |
2719 (goto-char start) | |
2720 (beginning-of-line) | |
2721 (let ((pos (point))) | |
2722 (end-of-line) | |
2723 (delete-region pos (1+ (point))))))))) | |
2724 | |
2725 (defun verilog-beg-of-defun () | |
2726 "Move backward to the beginning of the current function or procedure." | |
2727 (interactive) | |
2728 (verilog-re-search-backward verilog-defun-re nil 'move)) | |
2729 | |
2730 (defun verilog-end-of-defun () | |
2731 "Move forward to the end of the current function or procedure." | |
2732 (interactive) | |
2733 (verilog-re-search-forward verilog-end-defun-re nil 'move)) | |
2734 | |
2735 (defun verilog-get-beg-of-defun (&optional warn) | |
2736 (save-excursion | |
2737 (cond ((verilog-re-search-forward-quick verilog-defun-re nil t) | |
2738 (point)) | |
2739 (t | |
2740 (error "%s: Can't find module beginning" (verilog-point-text)) | |
2741 (point-max))))) | |
2742 (defun verilog-get-end-of-defun (&optional warn) | |
2743 (save-excursion | |
2744 (cond ((verilog-re-search-forward-quick verilog-end-defun-re nil t) | |
2745 (point)) | |
2746 (t | |
2747 (error "%s: Can't find endmodule" (verilog-point-text)) | |
2748 (point-max))))) | |
2749 | |
2750 (defun verilog-label-be (&optional arg) | |
2751 "Label matching begin ... end, fork ... join and case ... endcase statements. | |
2752 With ARG, first kill any existing labels." | |
2753 (interactive) | |
2754 (let ((cnt 0) | |
2755 (oldpos (point)) | |
2756 (b (progn | |
2757 (verilog-beg-of-defun) | |
2758 (point-marker))) | |
2759 (e (progn | |
2760 (verilog-end-of-defun) | |
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|
2761 (point-marker)))) |
79545 | 2762 (goto-char (marker-position b)) |
2763 (if (> (- e b) 200) | |
2764 (message "Relabeling module...")) | |
2765 (while (and | |
2766 (> (marker-position e) (point)) | |
2767 (verilog-re-search-forward | |
2768 (concat | |
2769 "\\<end\\(\\(function\\)\\|\\(task\\)\\|\\(module\\)\\|\\(primitive\\)\\|\\(interface\\)\\|\\(package\\)\\|\\(case\\)\\)?\\>" | |
2770 "\\|\\(`endif\\)\\|\\(`else\\)") | |
2771 nil 'move)) | |
2772 (goto-char (match-beginning 0)) | |
2773 (let ((indent-str (verilog-indent-line))) | |
2774 (verilog-set-auto-endcomments indent-str 't) | |
2775 (end-of-line) | |
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|
2776 (delete-horizontal-space)) |
79545 | 2777 (setq cnt (1+ cnt)) |
2778 (if (= 9 (% cnt 10)) | |
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|
2779 (message "%d..." cnt))) |
79545 | 2780 (goto-char oldpos) |
2781 (if (or | |
2782 (> (- e b) 200) | |
2783 (> cnt 20)) | |
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|
2784 (message "%d lines auto commented" cnt)))) |
79545 | 2785 |
2786 (defun verilog-beg-of-statement () | |
2787 "Move backward to beginning of statement." | |
2788 (interactive) | |
2789 ;; Move back token by token until we see the end | |
2790 ;; of some ealier line. | |
2791 (while | |
2792 ;; If the current point does not begin a new | |
2793 ;; statement, as in the character ahead of us is a ';', or SOF | |
2794 ;; or the string after us unambiguosly starts a statement, | |
2795 ;; or the token before us unambiguously ends a statement, | |
2796 ;; then move back a token and test again. | |
2797 (not (or | |
2798 (bolp) | |
2799 (= (preceding-char) ?\;) | |
2800 (not (or | |
2801 (looking-at "\\<") | |
2802 (forward-word -1))) | |
2803 (and | |
2804 (looking-at verilog-extended-complete-re) | |
2805 (not (save-excursion | |
2806 (verilog-backward-token) | |
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|
2807 (looking-at verilog-extended-complete-re)))) |
79545 | 2808 (looking-at verilog-basic-complete-re) |
2809 (save-excursion | |
2810 (verilog-backward-token) | |
2811 (or | |
2812 (looking-at verilog-end-block-re) | |
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2813 (looking-at verilog-preprocessor-re))))) |
79545 | 2814 (verilog-backward-syntactic-ws) |
2815 (verilog-backward-token)) | |
2816 ;; Now point is where the previous line ended. | |
2817 (verilog-forward-syntactic-ws)) | |
2818 | |
2819 (defun verilog-beg-of-statement-1 () | |
2820 "Move backward to beginning of statement." | |
2821 (interactive) | |
2822 (let ((pt (point))) | |
2823 | |
2824 (while (and (not (looking-at verilog-complete-reg)) | |
2825 (setq pt (point)) | |
2826 (verilog-backward-token) | |
2827 (not (looking-at verilog-complete-reg)) | |
2828 (verilog-backward-syntactic-ws) | |
2829 (setq pt (point)) | |
2830 (not (bolp)) | |
2831 (not (= (preceding-char) ?\;)))) | |
2832 (goto-char pt) | |
2833 (verilog-forward-ws&directives))) | |
2834 | |
2835 (defun verilog-end-of-statement () | |
2836 "Move forward to end of current statement." | |
2837 (interactive) | |
2838 (let ((nest 0) pos) | |
2839 (or (looking-at verilog-beg-block-re) | |
2840 ;; Skip to end of statement | |
2841 (setq pos (catch 'found | |
2842 (while t | |
2843 (forward-sexp 1) | |
2844 (verilog-skip-forward-comment-or-string) | |
2845 (cond ((looking-at "[ \t]*;") | |
2846 (skip-chars-forward "^;") | |
2847 (forward-char 1) | |
2848 (throw 'found (point))) | |
2849 ((save-excursion | |
2850 (forward-sexp -1) | |
2851 (looking-at verilog-beg-block-re)) | |
2852 (goto-char (match-beginning 0)) | |
2853 (throw 'found nil)) | |
2854 ((looking-at "[ \t]*)") | |
79546 | 2855 (throw 'found (point))) |
79545 | 2856 ((eobp) |
2857 (throw 'found (point)))))))) | |
2858 (if (not pos) | |
2859 ;; Skip a whole block | |
2860 (catch 'found | |
2861 (while t | |
2862 (verilog-re-search-forward verilog-end-statement-re nil 'move) | |
2863 (setq nest (if (match-end 1) | |
2864 (1+ nest) | |
2865 (1- nest))) | |
2866 (cond ((eobp) | |
2867 (throw 'found (point))) | |
2868 ((= 0 nest) | |
2869 (throw 'found (verilog-end-of-statement)))))) | |
2870 pos))) | |
2871 | |
2872 (defun verilog-in-case-region-p () | |
2873 "Return TRUE if in a case region; | |
2874 more specifically, point @ in the line foo : @ begin" | |
2875 (interactive) | |
2876 (save-excursion | |
2877 (if (and | |
2878 (progn (verilog-forward-syntactic-ws) | |
2879 (looking-at "\\<begin\\>")) | |
2880 (progn (verilog-backward-syntactic-ws) | |
2881 (= (preceding-char) ?\:))) | |
2882 (catch 'found | |
2883 (let ((nest 1)) | |
2884 (while t | |
2885 (verilog-re-search-backward | |
2886 (concat "\\(\\<module\\>\\)\\|\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|" | |
2887 "\\(\\<endcase\\>\\)\\>") | |
2888 nil 'move) | |
2889 (cond | |
2890 ((match-end 3) | |
2891 (setq nest (1+ nest))) | |
2892 ((match-end 2) | |
2893 (if (= nest 1) | |
2894 (throw 'found 1)) | |
2895 (setq nest (1- nest))) | |
2896 (t | |
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parents:
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diff
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|
2897 (throw 'found (= nest 0))))))) |
79545 | 2898 nil))) |
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parents:
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diff
changeset
|
2899 |
79545 | 2900 (defun verilog-in-struct-region-p () |
2901 "Return TRUE if in a struct region; | |
2902 more specifically, in a list after a struct|union keyword" | |
2903 (interactive) | |
2904 (save-excursion | |
2905 (let* ((state (parse-partial-sexp (point-min) (point))) | |
2906 (depth (nth 0 state))) | |
2907 (if depth | |
2908 (progn (backward-up-list depth) | |
2909 (verilog-beg-of-statement) | |
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|
2910 (looking-at "\\<typedef\\>?\\s-*\\<struct\\|union\\>")))))) |
79545 | 2911 |
2912 (defun verilog-in-generate-region-p () | |
2913 "Return TRUE if in a generate region; | |
2914 more specifically, after a generate and before an endgenerate" | |
2915 (interactive) | |
2916 (let ((lim (save-excursion (verilog-beg-of-defun) (point))) | |
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diff
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|
2917 (nest 1)) |
79545 | 2918 (save-excursion |
2919 (while (and | |
2920 (/= nest 0) | |
2921 (verilog-re-search-backward "\\<\\(generate\\)\\|\\(endgenerate\\)\\>" lim 'move) | |
2922 (cond | |
2923 ((match-end 1) ; generate | |
2924 (setq nest (1- nest))) | |
2925 ((match-end 2) ; endgenerate | |
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parents:
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diff
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|
2926 (setq nest (1+ nest))))))) |
79545 | 2927 (= nest 0) )) ; return nest |
2928 | |
2929 (defun verilog-in-fork-region-p () | |
2930 "Return true if between a fork and join." | |
2931 (interactive) | |
2932 (let ((lim (save-excursion (verilog-beg-of-defun) (point))) | |
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diff
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|
2933 (nest 1)) |
79545 | 2934 (save-excursion |
2935 (while (and | |
2936 (/= nest 0) | |
2937 (verilog-re-search-backward "\\<\\(fork\\)\\|\\(join\\(_any\\|_none\\)?\\)\\>" lim 'move) | |
2938 (cond | |
2939 ((match-end 1) ; fork | |
2940 (setq nest (1- nest))) | |
2941 ((match-end 2) ; join | |
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parents:
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diff
changeset
|
2942 (setq nest (1+ nest))))))) |
79545 | 2943 (= nest 0) )) ; return nest |
2944 | |
2945 (defun verilog-backward-case-item (lim) | |
2946 "Skip backward to nearest enclosing case item. | |
2947 Limit search to point LIM." | |
2948 (interactive) | |
2949 (let ((str 'nil) | |
2950 (lim1 | |
2951 (progn | |
2952 (save-excursion | |
2953 (verilog-re-search-backward verilog-endcomment-reason-re | |
2954 lim 'move) | |
2955 (point))))) | |
2956 ;; Try to find the real : | |
2957 (if (save-excursion (search-backward ":" lim1 t)) | |
2958 (let ((colon 0) | |
2959 b e ) | |
2960 (while | |
2961 (and | |
2962 (< colon 1) | |
2963 (verilog-re-search-backward "\\(\\[\\)\\|\\(\\]\\)\\|\\(:\\)" | |
2964 lim1 'move)) | |
2965 (cond | |
2966 ((match-end 1) ;; [ | |
2967 (setq colon (1+ colon)) | |
2968 (if (>= colon 0) | |
2969 (error "%s: unbalanced [" (verilog-point-text)))) | |
2970 ((match-end 2) ;; ] | |
2971 (setq colon (1- colon))) | |
2972 | |
2973 ((match-end 3) ;; : | |
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parents:
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diff
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|
2974 (setq colon (1+ colon))))) |
79545 | 2975 ;; Skip back to beginning of case item |
2976 (skip-chars-backward "\t ") | |
2977 (verilog-skip-backward-comment-or-string) | |
2978 (setq e (point)) | |
2979 (setq b | |
2980 (progn | |
2981 (if | |
2982 (verilog-re-search-backward | |
2983 "\\<\\(case[zx]?\\)\\>\\|;\\|\\<end\\>" nil 'move) | |
2984 (progn | |
2985 (cond | |
2986 ((match-end 1) | |
2987 (goto-char (match-end 1)) | |
2988 (verilog-forward-ws&directives) | |
2989 (if (looking-at "(") | |
2990 (progn | |
2991 (forward-sexp) | |
2992 (verilog-forward-ws&directives))) | |
2993 (point)) | |
2994 (t | |
2995 (goto-char (match-end 0)) | |
2996 (verilog-forward-ws&directives) | |
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parents:
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diff
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|
2997 (point)))) |
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parents:
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|
2998 (error "Malformed case item")))) |
79545 | 2999 (setq str (buffer-substring b e)) |
3000 (if | |
3001 (setq e | |
3002 (string-match | |
3003 "[ \t]*\\(\\(\n\\)\\|\\(//\\)\\|\\(/\\*\\)\\)" str)) | |
3004 (setq str (concat (substring str 0 e) "..."))) | |
3005 str) | |
3006 'nil))) | |
3007 | |
3008 | |
3009 ;; | |
3010 ;; Other functions | |
3011 ;; | |
3012 | |
79554
bc59ec18d036
(verilog-kill-existing-comment, verilog-insert-date)
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parents:
79552
diff
changeset
|
3013 (defun verilog-kill-existing-comment () |
79545 | 3014 "Kill auto comment on this line." |
3015 (save-excursion | |
3016 (let* ( | |
3017 (e (progn | |
3018 (end-of-line) | |
3019 (point))) | |
3020 (b (progn | |
3021 (beginning-of-line) | |
3022 (search-forward "//" e t)))) | |
3023 (if b | |
3024 (delete-region (- b 2) e))))) | |
3025 | |
3026 (defconst verilog-directive-nest-re | |
3027 (concat "\\(`else\\>\\)\\|" | |
3028 "\\(`endif\\>\\)\\|" | |
3029 "\\(`if\\>\\)\\|" | |
3030 "\\(`ifdef\\>\\)\\|" | |
3031 "\\(`ifndef\\>\\)")) | |
3032 (defun verilog-set-auto-endcomments (indent-str kill-existing-comment) | |
3033 "Add ending comment with given INDENT-STR. | |
3034 With KILL-EXISTING-COMMENT, remove what was there before. | |
3035 Insert `// case: 7 ' or `// NAME ' on this line if appropriate. | |
3036 Insert `// case expr ' if this line ends a case block. | |
3037 Insert `// ifdef FOO ' if this line ends code conditional on FOO. | |
3038 Insert `// NAME ' if this line ends a function, task, module, primitive or interface named NAME." | |
3039 (save-excursion | |
3040 (cond | |
3041 (; Comment close preprocessor directives | |
3042 (and | |
3043 (looking-at "\\(`endif\\)\\|\\(`else\\)") | |
3044 (or kill-existing-comment | |
3045 (not (save-excursion | |
3046 (end-of-line) | |
3047 (search-backward "//" (verilog-get-beg-of-line) t))))) | |
3048 (let ((nest 1) b e | |
3049 m | |
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parents:
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diff
changeset
|
3050 (else (if (match-end 2) "!" " "))) |
79545 | 3051 (end-of-line) |
3052 (if kill-existing-comment | |
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bc59ec18d036
(verilog-kill-existing-comment, verilog-insert-date)
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parents:
79552
diff
changeset
|
3053 (verilog-kill-existing-comment)) |
79545 | 3054 (delete-horizontal-space) |
3055 (save-excursion | |
3056 (backward-sexp 1) | |
3057 (while (and (/= nest 0) | |
3058 (verilog-re-search-backward verilog-directive-nest-re nil 'move)) | |
3059 (cond | |
3060 ((match-end 1) ; `else | |
3061 (if (= nest 1) | |
3062 (setq else "!"))) | |
3063 ((match-end 2) ; `endif | |
3064 (setq nest (1+ nest))) | |
3065 ((match-end 3) ; `if | |
3066 (setq nest (1- nest))) | |
3067 ((match-end 4) ; `ifdef | |
3068 (setq nest (1- nest))) | |
3069 ((match-end 5) ; `ifndef | |
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parents:
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diff
changeset
|
3070 (setq nest (1- nest))))) |
79545 | 3071 (if (match-end 0) |
3072 (setq | |
3073 m (buffer-substring | |
3074 (match-beginning 0) | |
3075 (match-end 0)) | |
3076 b (progn | |
3077 (skip-chars-forward "^ \t") | |
3078 (verilog-forward-syntactic-ws) | |
3079 (point)) | |
3080 e (progn | |
3081 (skip-chars-forward "a-zA-Z0-9_") | |
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Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
3082 (point))))) |
79545 | 3083 (if b |
3084 (if (> (count-lines (point) b) verilog-minimum-comment-distance) | |
3085 (insert (concat " // " else m " " (buffer-substring b e)))) | |
3086 (progn | |
3087 (insert " // unmatched `else or `endif") | |
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Dan Nicolaescu <dann@ics.uci.edu>
parents:
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diff
changeset
|
3088 (ding 't))))) |
79545 | 3089 |
3090 (; Comment close case/class/function/task/module and named block | |
3091 (and (looking-at "\\<end") | |
3092 (or kill-existing-comment | |
3093 (not (save-excursion | |
3094 (end-of-line) | |
3095 (search-backward "//" (verilog-get-beg-of-line) t))))) | |
3096 (let ((type (car indent-str))) | |
3097 (unless (eq type 'declaration) | |
3098 (unless (looking-at (concat "\\(" verilog-end-block-ordered-re "\\)[ \t]*:")) ;; ignore named ends | |
3099 (if (looking-at verilog-end-block-ordered-re) | |
3100 (cond | |
3101 (;- This is a case block; search back for the start of this case | |
3102 (match-end 1) ;; of verilog-end-block-ordered-re | |
3103 | |
3104 (let ((err 't) | |
3105 (str "UNMATCHED!!")) | |
3106 (save-excursion | |
3107 (verilog-leap-to-head) | |
3108 (cond | |
3109 ((looking-at "\\<randcase\\>") | |
3110 (setq str "randcase") | |
79691
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3111 (setq err nil)) |
79545 | 3112 ((match-end 0) |
3113 (goto-char (match-end 1)) | |
3114 (if nil | |
3115 (let (s f) | |
3116 (setq s (match-beginning 1)) | |
3117 (setq f (progn (end-of-line) | |
3118 (point))) | |
3119 (setq str (buffer-substring s f))) | |
3120 (setq err nil)) | |
3121 (setq str (concat (buffer-substring (match-beginning 1) (match-end 1)) | |
3122 " " | |
3123 (verilog-get-expr)))))) | |
3124 (end-of-line) | |
3125 (if kill-existing-comment | |
79554
bc59ec18d036
(verilog-kill-existing-comment, verilog-insert-date)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79552
diff
changeset
|
3126 (verilog-kill-existing-comment)) |
79545 | 3127 (delete-horizontal-space) |
3128 (insert (concat " // " str )) | |
79691
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3129 (if err (ding 't)))) |
79545 | 3130 |
3131 (;- This is a begin..end block | |
3132 (match-end 2) ;; of verilog-end-block-ordered-re | |
3133 (let ((str " // UNMATCHED !!") | |
3134 (err 't) | |
3135 (here (point)) | |
3136 there | |
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parents:
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diff
changeset
|
3137 cntx) |
79545 | 3138 (save-excursion |
3139 (verilog-leap-to-head) | |
3140 (setq there (point)) | |
3141 (if (not (match-end 0)) | |
3142 (progn | |
3143 (goto-char here) | |
3144 (end-of-line) | |
3145 (if kill-existing-comment | |
79554
bc59ec18d036
(verilog-kill-existing-comment, verilog-insert-date)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79552
diff
changeset
|
3146 (verilog-kill-existing-comment)) |
79545 | 3147 (delete-horizontal-space) |
3148 (insert str) | |
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(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
3149 (ding 't)) |
79545 | 3150 (let ((lim |
3151 (save-excursion (verilog-beg-of-defun) (point))) | |
79799
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(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
3152 (here (point))) |
79545 | 3153 (cond |
3154 (;-- handle named block differently | |
3155 (looking-at verilog-named-block-re) | |
3156 (search-forward ":") | |
3157 (setq there (point)) | |
3158 (setq str (verilog-get-expr)) | |
3159 (setq err nil) | |
3160 (setq str (concat " // block: " str ))) | |
3161 | |
3162 ((verilog-in-case-region-p) ;-- handle case item differently | |
3163 (goto-char here) | |
3164 (setq str (verilog-backward-case-item lim)) | |
3165 (setq there (point)) | |
3166 (setq err nil) | |
3167 (setq str (concat " // case: " str ))) | |
3168 | |
3169 (;- try to find "reason" for this begin | |
3170 (cond | |
3171 (; | |
3172 (eq here (progn | |
3173 (verilog-backward-token) | |
3174 (verilog-beg-of-statement-1) | |
3175 (point))) | |
3176 (setq err nil) | |
3177 (setq str "")) | |
3178 ((looking-at verilog-endcomment-reason-re) | |
3179 (setq there (match-end 0)) | |
3180 (setq cntx (concat | |
3181 (buffer-substring (match-beginning 0) (match-end 0)) " ")) | |
3182 (cond | |
3183 (;- begin | |
3184 (match-end 2) | |
3185 (setq err nil) | |
3186 (save-excursion | |
3187 (if (and (verilog-continued-line) | |
3188 (looking-at "\\<repeat\\>\\|\\<wait\\>\\|\\<always\\>")) | |
3189 (progn | |
3190 (goto-char (match-end 0)) | |
3191 (setq there (point)) | |
3192 (setq str | |
3193 (concat " // " | |
3194 (buffer-substring (match-beginning 0) (match-end 0)) " " | |
3195 (verilog-get-expr)))) | |
3196 (setq str "")))) | |
3197 | |
3198 (;- else | |
3199 (match-end 4) | |
3200 (let ((nest 0) | |
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(top-level): Fix spacing.
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parents:
79717
diff
changeset
|
3201 ( reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)")) |
79545 | 3202 (catch 'skip |
3203 (while (verilog-re-search-backward reg nil 'move) | |
3204 (cond | |
3205 ((match-end 1) ; begin | |
3206 (setq nest (1- nest))) | |
3207 ((match-end 2) ; end | |
3208 (setq nest (1+ nest))) | |
3209 ((match-end 3) | |
3210 (if (= 0 nest) | |
3211 (progn | |
3212 (goto-char (match-end 0)) | |
3213 (setq there (point)) | |
3214 (setq err nil) | |
3215 (setq str (verilog-get-expr)) | |
3216 (setq str (concat " // else: !if" str )) | |
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57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
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diff
changeset
|
3217 (throw 'skip 1))))))))) |
79545 | 3218 |
3219 (;- end else | |
3220 (match-end 5) | |
3221 (goto-char there) | |
3222 (let ((nest 0) | |
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(top-level): Fix spacing.
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parents:
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diff
changeset
|
3223 (reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|\\(\\<if\\>\\)")) |
79545 | 3224 (catch 'skip |
3225 (while (verilog-re-search-backward reg nil 'move) | |
3226 (cond | |
3227 ((match-end 1) ; begin | |
3228 (setq nest (1- nest))) | |
3229 ((match-end 2) ; end | |
3230 (setq nest (1+ nest))) | |
3231 ((match-end 3) | |
3232 (if (= 0 nest) | |
3233 (progn | |
3234 (goto-char (match-end 0)) | |
3235 (setq there (point)) | |
3236 (setq err nil) | |
3237 (setq str (verilog-get-expr)) | |
3238 (setq str (concat " // else: !if" str )) | |
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(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
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diff
changeset
|
3239 (throw 'skip 1))))))))) |
79545 | 3240 |
3241 (;- task/function/initial et cetera | |
3242 t | |
3243 (match-end 0) | |
3244 (goto-char (match-end 0)) | |
3245 (setq there (point)) | |
3246 (setq err nil) | |
3247 (setq str (verilog-get-expr)) | |
3248 (setq str (concat " // " cntx str ))) | |
3249 | |
3250 (;-- otherwise... | |
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(top-level): Fix spacing.
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parents:
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diff
changeset
|
3251 (setq str " // auto-endcomment confused ")))) |
79545 | 3252 |
3253 ((and | |
3254 (verilog-in-case-region-p) ;-- handle case item differently | |
3255 (progn | |
3256 (setq there (point)) | |
3257 (goto-char here) | |
3258 (setq str (verilog-backward-case-item lim)))) | |
3259 (setq err nil) | |
3260 (setq str (concat " // case: " str ))) | |
3261 | |
3262 ((verilog-in-fork-region-p) | |
3263 (setq err nil) | |
3264 (setq str " // fork branch" )) | |
3265 | |
3266 ((looking-at "\\<end\\>") | |
3267 ;; HERE | |
3268 (forward-word 1) | |
3269 (verilog-forward-syntactic-ws) | |
3270 (setq err nil) | |
3271 (setq str (verilog-get-expr)) | |
3272 (setq str (concat " // " cntx str ))) | |
3273 | |
3274 )))) | |
3275 (goto-char here) | |
3276 (end-of-line) | |
3277 (if kill-existing-comment | |
79554
bc59ec18d036
(verilog-kill-existing-comment, verilog-insert-date)
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parents:
79552
diff
changeset
|
3278 (verilog-kill-existing-comment)) |
79545 | 3279 (delete-horizontal-space) |
3280 (if (or err | |
3281 (> (count-lines here there) verilog-minimum-comment-distance)) | |
3282 (insert str)) | |
3283 (if err (ding 't)) | |
3284 )))) | |
3285 (;- this is endclass, which can be nested | |
3286 (match-end 11) ;; of verilog-end-block-ordered-re | |
3287 ;;(goto-char there) | |
3288 (let ((nest 0) | |
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(top-level): Fix spacing.
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diff
changeset
|
3289 (reg "\\<\\(class\\)\\|\\(endclass\\)\\|\\(package\\|primitive\\|\\(macro\\)?module\\)\\>") |
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
3290 string) |
79545 | 3291 (save-excursion |
3292 (catch 'skip | |
3293 (while (verilog-re-search-backward reg nil 'move) | |
3294 (cond | |
3295 ((match-end 3) ; endclass | |
3296 (ding 't) | |
3297 (setq string "unmatched endclass") | |
3298 (throw 'skip 1)) | |
3299 | |
3300 ((match-end 2) ; endclass | |
3301 (setq nest (1+ nest))) | |
3302 | |
3303 ((match-end 1) ; class | |
3304 (setq nest (1- nest)) | |
3305 (if (< nest 0) | |
3306 (progn | |
3307 (goto-char (match-end 0)) | |
3308 (let (b e) | |
3309 (setq b (progn | |
3310 (skip-chars-forward "^ \t") | |
3311 (verilog-forward-ws&directives) | |
3312 (point)) | |
3313 e (progn | |
3314 (skip-chars-forward "a-zA-Z0-9_") | |
3315 (point))) | |
3316 (setq string (buffer-substring b e))) | |
3317 (throw 'skip 1)))) | |
3318 )))) | |
3319 (end-of-line) | |
79799
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
3320 (insert (concat " // " string )))) |
79545 | 3321 |
3322 (;- this is end{function,generate,task,module,primitive,table,generate} | |
3323 ;- which can not be nested. | |
3324 t | |
3325 (let (string reg (width nil)) | |
3326 (end-of-line) | |
3327 (if kill-existing-comment | |
3328 (save-match-data | |
79554
bc59ec18d036
(verilog-kill-existing-comment, verilog-insert-date)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79552
diff
changeset
|
3329 (verilog-kill-existing-comment))) |
79545 | 3330 (delete-horizontal-space) |
3331 (backward-sexp) | |
3332 (cond | |
3333 ((match-end 5) ;; of verilog-end-block-ordered-re | |
3334 (setq reg "\\(\\<function\\>\\)\\|\\(\\<\\(endfunction\\|task\\|\\(macro\\)?module\\|primitive\\)\\>\\)") | |
79799
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
3335 (setq width "\\(\\s-*\\(\\[[^]]*\\]\\)\\|\\(real\\(time\\)?\\)\\|\\(integer\\)\\|\\(time\\)\\)?")) |
79545 | 3336 ((match-end 6) ;; of verilog-end-block-ordered-re |
3337 (setq reg "\\(\\<task\\>\\)\\|\\(\\<\\(endtask\\|function\\|\\(macro\\)?module\\|primitive\\)\\>\\)")) | |
3338 ((match-end 7) ;; of verilog-end-block-ordered-re | |
3339 (setq reg "\\(\\<\\(macro\\)?module\\>\\)\\|\\<endmodule\\>")) | |
3340 ((match-end 8) ;; of verilog-end-block-ordered-re | |
3341 (setq reg "\\(\\<primitive\\>\\)\\|\\(\\<\\(endprimitive\\|package\\|interface\\|\\(macro\\)?module\\)\\>\\)")) | |
3342 ((match-end 9) ;; of verilog-end-block-ordered-re | |
3343 (setq reg "\\(\\<interface\\>\\)\\|\\(\\<\\(endinterface\\|package\\|primitive\\|\\(macro\\)?module\\)\\>\\)")) | |
3344 ((match-end 10) ;; of verilog-end-block-ordered-re | |
3345 (setq reg "\\(\\<package\\>\\)\\|\\(\\<\\(endpackage\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)")) | |
3346 ((match-end 11) ;; of verilog-end-block-ordered-re | |
3347 (setq reg "\\(\\<class\\>\\)\\|\\(\\<\\(endclass\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)")) | |
3348 ((match-end 12) ;; of verilog-end-block-ordered-re | |
3349 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<\\(endcovergroup\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)")) | |
3350 ((match-end 13) ;; of verilog-end-block-ordered-re | |
3351 (setq reg "\\(\\<program\\>\\)\\|\\(\\<\\(endprogram\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)")) | |
3352 ((match-end 14) ;; of verilog-end-block-ordered-re | |
3353 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<\\(endsequence\\|primitive\\|interface\\|\\(macro\\)?module\\)\\>\\)")) | |
3354 ((match-end 15) ;; of verilog-end-block-ordered-re | |
3355 (setq reg "\\(\\<clocking\\>\\)\\|\\<endclocking\\>")) | |
3356 | |
79799
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
3357 (t (error "Problem in verilog-set-auto-endcomments"))) |
79545 | 3358 (let (b e) |
3359 (save-excursion | |
3360 (verilog-re-search-backward reg nil 'move) | |
3361 (cond | |
3362 ((match-end 1) | |
3363 (setq b (progn | |
3364 (skip-chars-forward "^ \t") | |
3365 (verilog-forward-ws&directives) | |
3366 (if (and width (looking-at width)) | |
3367 (progn | |
3368 (goto-char (match-end 0)) | |
79799
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
3369 (verilog-forward-ws&directives))) |
79545 | 3370 (point)) |
3371 e (progn | |
3372 (skip-chars-forward "a-zA-Z0-9_") | |
3373 (point))) | |
3374 (setq string (buffer-substring b e))) | |
3375 (t | |
3376 (ding 't) | |
3377 (setq string "unmatched end(function|task|module|primitive|interface|package|class|clocking)"))))) | |
3378 (end-of-line) | |
3379 (insert (concat " // " string ))) | |
3380 )))))))))) | |
3381 | |
3382 (defun verilog-get-expr() | |
3383 "Grab expression at point, e.g, case ( a | b & (c ^d))" | |
3384 (let* ((b (progn | |
3385 (verilog-forward-syntactic-ws) | |
3386 (skip-chars-forward " \t") | |
3387 (point))) | |
3388 (e (let ((par 1)) | |
3389 (cond | |
3390 ((looking-at "@") | |
3391 (forward-char 1) | |
3392 (verilog-forward-syntactic-ws) | |
3393 (if (looking-at "(") | |
3394 (progn | |
3395 (forward-char 1) | |
3396 (while (and (/= par 0) | |
3397 (verilog-re-search-forward "\\((\\)\\|\\()\\)" nil 'move)) | |
3398 (cond | |
3399 ((match-end 1) | |
3400 (setq par (1+ par))) | |
3401 ((match-end 2) | |
3402 (setq par (1- par))))))) | |
3403 (point)) | |
3404 ((looking-at "(") | |
3405 (forward-char 1) | |
3406 (while (and (/= par 0) | |
3407 (verilog-re-search-forward "\\((\\)\\|\\()\\)" nil 'move)) | |
3408 (cond | |
3409 ((match-end 1) | |
3410 (setq par (1+ par))) | |
3411 ((match-end 2) | |
3412 (setq par (1- par))))) | |
3413 (point)) | |
3414 ((looking-at "\\[") | |
3415 (forward-char 1) | |
3416 (while (and (/= par 0) | |
3417 (verilog-re-search-forward "\\(\\[\\)\\|\\(\\]\\)" nil 'move)) | |
3418 (cond | |
3419 ((match-end 1) | |
3420 (setq par (1+ par))) | |
3421 ((match-end 2) | |
3422 (setq par (1- par))))) | |
3423 (verilog-forward-syntactic-ws) | |
3424 (skip-chars-forward "^ \t\n\f") | |
3425 (point)) | |
3426 ((looking-at "/[/\\*]") | |
3427 b) | |
3428 ('t | |
3429 (skip-chars-forward "^: \t\n\f") | |
79799
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
3430 (point))))) |
79545 | 3431 (str (buffer-substring b e))) |
3432 (if (setq e (string-match "[ \t]*\\(\\(\n\\)\\|\\(//\\)\\|\\(/\\*\\)\\)" str)) | |
3433 (setq str (concat (substring str 0 e) "..."))) | |
3434 str)) | |
3435 | |
3436 (defun verilog-expand-vector () | |
3437 "Take a signal vector on the current line and expand it to multiple lines. | |
3438 Useful for creating tri's and other expanded fields." | |
3439 (interactive) | |
3440 (verilog-expand-vector-internal "[" "]")) | |
3441 | |
3442 (defun verilog-expand-vector-internal (bra ket) | |
3443 "Given BRA, the start brace and KET, the end brace, expand one line into many lines." | |
3444 (save-excursion | |
3445 (forward-line 0) | |
3446 (let ((signal-string (buffer-substring (point) | |
3447 (progn | |
3448 (end-of-line) (point))))) | |
79691
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3449 (if (string-match |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
3450 (concat "\\(.*\\)" |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3451 (regexp-quote bra) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3452 "\\([0-9]*\\)\\(:[0-9]*\\|\\)\\(::[0-9---]*\\|\\)" |
79799
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
3453 (regexp-quote ket) |
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
3454 "\\(.*\\)$") signal-string) |
79545 | 3455 (let* ((sig-head (match-string 1 signal-string)) |
79691
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3456 (vec-start (string-to-number (match-string 2 signal-string))) |
79545 | 3457 (vec-end (if (= (match-beginning 3) (match-end 3)) |
3458 vec-start | |
79691
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3459 (string-to-number |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3460 (substring signal-string (1+ (match-beginning 3)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3461 (match-end 3))))) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3462 (vec-range |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3463 (if (= (match-beginning 4) (match-end 4)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3464 1 |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3465 (string-to-number |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3466 (substring signal-string (+ 2 (match-beginning 4)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3467 (match-end 4))))) |
79545 | 3468 (sig-tail (match-string 5 signal-string)) |
3469 vec) | |
3470 ;; Decode vectors | |
3471 (setq vec nil) | |
3472 (if (< vec-range 0) | |
3473 (let ((tmp vec-start)) | |
3474 (setq vec-start vec-end | |
3475 vec-end tmp | |
3476 vec-range (- vec-range)))) | |
3477 (if (< vec-end vec-start) | |
3478 (while (<= vec-end vec-start) | |
3479 (setq vec (append vec (list vec-start))) | |
3480 (setq vec-start (- vec-start vec-range))) | |
3481 (while (<= vec-start vec-end) | |
3482 (setq vec (append vec (list vec-start))) | |
3483 (setq vec-start (+ vec-start vec-range)))) | |
3484 ;; | |
3485 ;; Delete current line | |
3486 (delete-region (point) (progn (forward-line 0) (point))) | |
3487 ;; | |
3488 ;; Expand vector | |
3489 (while vec | |
79691
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3490 (insert (concat sig-head bra |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3491 (int-to-string (car vec)) ket sig-tail "\n")) |
79545 | 3492 (setq vec (cdr vec))) |
3493 (delete-char -1) | |
3494 ;; | |
3495 ))))) | |
3496 | |
3497 (defun verilog-strip-comments () | |
3498 "Strip all comments from the verilog code." | |
3499 (interactive) | |
3500 (goto-char (point-min)) | |
3501 (while (re-search-forward "//" nil t) | |
3502 (if (verilog-within-string) | |
3503 (re-search-forward "\"" nil t) | |
3504 (if (verilog-in-star-comment-p) | |
3505 (re-search-forward "\*/" nil t) | |
3506 (let ((bpt (- (point) 2))) | |
3507 (end-of-line) | |
3508 (delete-region bpt (point)))))) | |
3509 ;; | |
3510 (goto-char (point-min)) | |
3511 (while (re-search-forward "/\\*" nil t) | |
3512 (if (verilog-within-string) | |
3513 (re-search-forward "\"" nil t) | |
3514 (let ((bpt (- (point) 2))) | |
3515 (re-search-forward "\\*/") | |
3516 (delete-region bpt (point)))))) | |
3517 | |
3518 (defun verilog-one-line () | |
3519 "Convert structural verilog instances to occupy one line." | |
3520 (interactive) | |
3521 (goto-char (point-min)) | |
3522 (while (re-search-forward "\\([^;]\\)[ \t]*\n[ \t]*" nil t) | |
3523 (replace-match "\\1 " nil nil))) | |
3524 | |
3525 (defun verilog-linter-name () | |
3526 "Return name of linter, either surelint or verilint." | |
3527 (let ((compile-word1 (verilog-string-replace-matches "\\s .*$" "" nil nil | |
3528 compile-command)) | |
3529 (lint-word1 (verilog-string-replace-matches "\\s .*$" "" nil nil | |
3530 verilog-linter))) | |
3531 (cond ((equal compile-word1 "surelint") `surelint) | |
3532 ((equal compile-word1 "verilint") `verilint) | |
3533 ((equal lint-word1 "surelint") `surelint) | |
3534 ((equal lint-word1 "verilint") `verilint) | |
3535 (t `surelint)))) ;; back compatibility | |
3536 | |
3537 (defun verilog-lint-off () | |
3538 "Convert a Verilog linter warning line into a disable statement. | |
3539 For example: | |
3540 pci_bfm_null.v, line 46: Unused input: pci_rst_ | |
3541 becomes a comment for the appropriate tool. | |
3542 | |
3543 The first word of the `compile-command' or `verilog-linter' | |
3544 variables are used to determine which product is being used. | |
3545 | |
3546 See \\[verilog-surelint-off] and \\[verilog-verilint-off]." | |
3547 (interactive) | |
3548 (let ((linter (verilog-linter-name))) | |
3549 (cond ((equal linter `surelint) | |
3550 (verilog-surelint-off)) | |
3551 ((equal linter `verilint) | |
3552 (verilog-verilint-off)) | |
3553 (t (error "Linter name not set"))))) | |
3554 | |
79691
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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diff
changeset
|
3555 (defvar compilation-last-buffer) |
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* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
3556 |
79545 | 3557 (defun verilog-surelint-off () |
3558 "Convert a SureLint warning line into a disable statement. | |
3559 Run from Verilog source window; assumes there is a *compile* buffer | |
3560 with point set appropriately. | |
3561 | |
3562 For example: | |
3563 WARNING [STD-UDDONX]: xx.v, line 8: output out is never assigned. | |
3564 becomes: | |
3565 // surefire lint_line_off UDDONX" | |
3566 (interactive) | |
79691
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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79555
diff
changeset
|
3567 (let ((buff (if (boundp 'next-error-last-buffer) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
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changeset
|
3568 next-error-last-buffer |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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79555
diff
changeset
|
3569 compilation-last-buffer))) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
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diff
changeset
|
3570 (when (buffer-live-p buff) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
3571 ;; FIXME with-current-buffer? |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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79555
diff
changeset
|
3572 (save-excursion |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
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diff
changeset
|
3573 (switch-to-buffer buff) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
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diff
changeset
|
3574 (beginning-of-line) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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diff
changeset
|
3575 (when |
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* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
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diff
changeset
|
3576 (looking-at "\\(INFO\\|WARNING\\|ERROR\\) \\[[^-]+-\\([^]]+\\)\\]: \\([^,]+\\), line \\([0-9]+\\): \\(.*\\)$") |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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diff
changeset
|
3577 (let* ((code (match-string 2)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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diff
changeset
|
3578 (file (match-string 3)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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changeset
|
3579 (line (match-string 4)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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diff
changeset
|
3580 (buffer (get-file-buffer file)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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diff
changeset
|
3581 dir filename) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
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diff
changeset
|
3582 (unless buffer |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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changeset
|
3583 (progn |
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* progmodes/verilog-mode.el (top-level): Don't require compile.
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changeset
|
3584 (setq buffer |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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diff
changeset
|
3585 (and (file-exists-p file) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
3586 (find-file-noselect file))) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
3587 (or buffer |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
3588 (let* ((pop-up-windows t)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3589 (let ((name (expand-file-name |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
3590 (read-file-name |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3591 (format "Find this error in: (default %s) " |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3592 file) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3593 dir file t)))) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3594 (if (file-directory-p name) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3595 (setq name (expand-file-name filename name))) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3596 (setq buffer |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3597 (and (file-exists-p name) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3598 (find-file-noselect name)))))))) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3599 (switch-to-buffer buffer) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3600 (goto-line (string-to-number line)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3601 (end-of-line) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3602 (catch 'already |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3603 (cond |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3604 ((verilog-in-slash-comment-p) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3605 (re-search-backward "//") |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3606 (cond |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3607 ((looking-at "// surefire lint_off_line ") |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3608 (goto-char (match-end 0)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3609 (let ((lim (save-excursion (end-of-line) (point)))) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3610 (if (re-search-forward code lim 'move) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3611 (throw 'already t) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3612 (insert (concat " " code))))) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3613 (t |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3614 ))) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3615 ((verilog-in-star-comment-p) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3616 (re-search-backward "/\*") |
79799
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
3617 (insert (format " // surefire lint_off_line %6s" code ))) |
79691
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3618 (t |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3619 (insert (format " // surefire lint_off_line %6s" code )) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3620 ))))))))) |
79545 | 3621 |
3622 (defun verilog-verilint-off () | |
3623 "Convert a Verilint warning line into a disable statement. | |
3624 | |
3625 For example: | |
3626 (W240) pci_bfm_null.v, line 46: Unused input: pci_rst_ | |
3627 becomes: | |
3628 //Verilint 240 off // WARNING: Unused input" | |
3629 (interactive) | |
3630 (save-excursion | |
3631 (beginning-of-line) | |
3632 (when (looking-at "\\(.*\\)([WE]\\([0-9A-Z]+\\)).*,\\s +line\\s +[0-9]+:\\s +\\([^:\n]+\\):?.*$") | |
3633 (replace-match (format | |
3634 ;; %3s makes numbers 1-999 line up nicely | |
3635 "\\1//Verilint %3s off // WARNING: \\3" | |
3636 (match-string 2))) | |
3637 (beginning-of-line) | |
3638 (verilog-indent-line)))) | |
3639 | |
3640 (defun verilog-auto-save-compile () | |
3641 "Update automatics with \\[verilog-auto], save the buffer, and compile." | |
3642 (interactive) | |
3643 (verilog-auto) ; Always do it for safety | |
3644 (save-buffer) | |
3645 (compile compile-command)) | |
3646 | |
3647 | |
3648 | |
3649 ;; | |
3650 ;; Batch | |
3651 ;; | |
3652 | |
3653 (defmacro verilog-batch-error-wrapper (&rest body) | |
3654 "Execute BODY and add error prefix to any errors found. | |
3655 This lets programs calling batch mode to easily extract error messages." | |
79546 | 3656 `(condition-case err |
3657 (progn ,@body) | |
3658 (error | |
3659 (error "%%Error: %s%s" (error-message-string err) | |
3660 (if (featurep 'xemacs) "\n" ""))))) ;; xemacs forgets to add a newline | |
79545 | 3661 |
3662 (defun verilog-batch-execute-func (funref) | |
3663 "Internal processing of a batch command, running FUNREF on all command arguments." | |
3664 (verilog-batch-error-wrapper | |
3665 ;; General globals needed | |
3666 (setq make-backup-files nil) | |
3667 (setq-default make-backup-files nil) | |
3668 (setq enable-local-variables t) | |
3669 (setq enable-local-eval t) | |
3670 ;; Make sure any sub-files we read get proper mode | |
3671 (setq default-major-mode `verilog-mode) | |
3672 ;; Ditto files already read in | |
79691
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3673 (mapc (lambda (buf) |
79799
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
3674 (when (buffer-file-name buf) |
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
3675 (save-excursion |
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
3676 (set-buffer buf) |
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
3677 (verilog-mode)))) |
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
3678 (buffer-list)) |
79545 | 3679 ;; Process the files |
3680 (mapcar '(lambda (buf) | |
3681 (when (buffer-file-name buf) | |
3682 (save-excursion | |
3683 (if (not (file-exists-p (buffer-file-name buf))) | |
79691
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3684 (error |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
3685 (concat "File not found: " (buffer-file-name buf)))) |
79545 | 3686 (message (concat "Processing " (buffer-file-name buf))) |
3687 (set-buffer buf) | |
3688 (funcall funref) | |
3689 (save-buffer)))) | |
3690 (buffer-list)))) | |
3691 | |
3692 (defun verilog-batch-auto () | |
3693 "For use with --batch, perform automatic expansions as a stand-alone tool. | |
3694 This sets up the appropriate Verilog-Mode environment, updates automatics | |
3695 with \\[verilog-auto] on all command-line files, and saves the buffers. | |
3696 For proper results, multiple filenames need to be passed on the command | |
3697 line in bottom-up order." | |
3698 (unless noninteractive | |
3699 (error "Use verilog-batch-auto only with --batch")) ;; Otherwise we'd mess up buffer modes | |
3700 (verilog-batch-execute-func `verilog-auto)) | |
3701 | |
3702 (defun verilog-batch-delete-auto () | |
3703 "For use with --batch, perform automatic deletion as a stand-alone tool. | |
3704 This sets up the appropriate Verilog-Mode environment, deletes automatics | |
3705 with \\[verilog-delete-auto] on all command-line files, and saves the buffers." | |
3706 (unless noninteractive | |
3707 (error "Use verilog-batch-delete-auto only with --batch")) ;; Otherwise we'd mess up buffer modes | |
3708 (verilog-batch-execute-func `verilog-delete-auto)) | |
3709 | |
3710 (defun verilog-batch-inject-auto () | |
3711 "For use with --batch, perform automatic injection as a stand-alone tool. | |
3712 This sets up the appropriate Verilog-Mode environment, injects new automatics | |
3713 with \\[verilog-inject-auto] on all command-line files, and saves the buffers. | |
3714 For proper results, multiple filenames need to be passed on the command | |
3715 line in bottom-up order." | |
3716 (unless noninteractive | |
3717 (error "Use verilog-batch-inject-auto only with --batch")) ;; Otherwise we'd mess up buffer modes | |
3718 (verilog-batch-execute-func `verilog-inject-auto)) | |
3719 | |
3720 (defun verilog-batch-indent () | |
3721 "For use with --batch, reindent an a entire file as a stand-alone tool. | |
3722 This sets up the appropriate Verilog-Mode environment, calls | |
3723 \\[verilog-indent-buffer] on all command-line files, and saves the buffers." | |
3724 (unless noninteractive | |
3725 (error "Use verilog-batch-indent only with --batch")) ;; Otherwise we'd mess up buffer modes | |
3726 (verilog-batch-execute-func `verilog-indent-buffer)) | |
3727 | |
3728 | |
3729 ;; | |
3730 ;; Indentation | |
3731 ;; | |
3732 (defconst verilog-indent-alist | |
3733 '((block . (+ ind verilog-indent-level)) | |
3734 (case . (+ ind verilog-case-indent)) | |
3735 (cparenexp . (+ ind verilog-indent-level)) | |
3736 (cexp . (+ ind verilog-cexp-indent)) | |
3737 (defun . verilog-indent-level-module) | |
3738 (declaration . verilog-indent-level-declaration) | |
3739 (directive . (verilog-calculate-indent-directive)) | |
3740 (tf . verilog-indent-level) | |
3741 (behavioral . (+ verilog-indent-level-behavioral verilog-indent-level-module)) | |
3742 (statement . ind) | |
3743 (cpp . 0) | |
3744 (comment . (verilog-comment-indent)) | |
3745 (unknown . 3) | |
3746 (string . 0))) | |
3747 | |
3748 (defun verilog-continued-line-1 (lim) | |
3749 "Return true if this is a continued line. | |
3750 Set point to where line starts. Limit search to point LIM." | |
3751 (let ((continued 't)) | |
3752 (if (eq 0 (forward-line -1)) | |
3753 (progn | |
3754 (end-of-line) | |
3755 (verilog-backward-ws&directives lim) | |
3756 (if (bobp) | |
3757 (setq continued nil) | |
3758 (setq continued (verilog-backward-token)))) | |
3759 (setq continued nil)) | |
3760 continued)) | |
3761 | |
3762 (defun verilog-calculate-indent () | |
3763 "Calculate the indent of the current Verilog line. | |
3764 Examine previous lines. Once a line is found that is definitive as to the | |
3765 type of the current line, return that lines' indent level and its | |
3766 type. Return a list of two elements: (INDENT-TYPE INDENT-LEVEL)." | |
3767 (save-excursion | |
3768 (let* ((starting_position (point)) | |
3769 (par 0) | |
3770 (begin (looking-at "[ \t]*begin\\>")) | |
3771 (lim (save-excursion (verilog-re-search-backward "\\(\\<begin\\>\\)\\|\\(\\<module\\>\\)" nil t))) | |
3772 (type (catch 'nesting | |
3773 ;; Keep working backwards until we can figure out | |
3774 ;; what type of statement this is. | |
3775 ;; Basically we need to figure out | |
3776 ;; 1) if this is a continuation of the previous line; | |
3777 ;; 2) are we in a block scope (begin..end) | |
3778 | |
3779 ;; if we are in a comment, done. | |
3780 (if (verilog-in-star-comment-p) | |
3781 (throw 'nesting 'comment)) | |
3782 | |
3783 ;; if we have a directive, done. | |
3784 (if (save-excursion (beginning-of-line) (looking-at verilog-directive-re-1)) | |
3785 (throw 'nesting 'directive)) | |
3786 | |
3787 ;; unless we are in the newfangled coverpoint or constraint blocks | |
3788 ;; if we are in a parenthesized list, and the user likes to indent these, return. | |
3789 (if (and | |
3790 verilog-indent-lists | |
3791 (not (verilog-in-coverage)) | |
3792 (verilog-in-paren)) | |
3793 (progn (setq par 1) | |
79799
57956dd69d3f
(top-level): Fix spacing.
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parents:
79717
diff
changeset
|
3794 (throw 'nesting 'block))) |
79545 | 3795 |
3796 ;; See if we are continuing a previous line | |
3797 (while t | |
3798 ;; trap out if we crawl off the top of the buffer | |
3799 (if (bobp) (throw 'nesting 'cpp)) | |
3800 | |
3801 (if (verilog-continued-line-1 lim) | |
3802 (let ((sp (point))) | |
3803 (if (and | |
3804 (not (looking-at verilog-complete-reg)) | |
3805 (verilog-continued-line-1 lim)) | |
3806 (progn (goto-char sp) | |
3807 (throw 'nesting 'cexp)) | |
3808 | |
3809 (goto-char sp)) | |
3810 | |
3811 (if (and begin | |
3812 (not verilog-indent-begin-after-if) | |
3813 (looking-at verilog-no-indent-begin-re)) | |
3814 (progn | |
3815 (beginning-of-line) | |
3816 (skip-chars-forward " \t") | |
3817 (throw 'nesting 'statement)) | |
3818 (progn | |
3819 (throw 'nesting 'cexp)))) | |
3820 ;; not a continued line | |
3821 (goto-char starting_position)) | |
3822 | |
3823 (if (looking-at "\\<else\\>") | |
3824 ;; search back for governing if, striding across begin..end pairs | |
3825 ;; appropriately | |
3826 (let ((elsec 1)) | |
3827 (while (verilog-re-search-backward verilog-ends-re nil 'move) | |
3828 (cond | |
3829 ((match-end 1) ; else, we're in deep | |
3830 (setq elsec (1+ elsec))) | |
3831 ((match-end 2) ; if | |
3832 (setq elsec (1- elsec)) | |
3833 (if (= 0 elsec) | |
3834 (if verilog-align-ifelse | |
3835 (throw 'nesting 'statement) | |
3836 (progn ;; back up to first word on this line | |
3837 (beginning-of-line) | |
3838 (verilog-forward-syntactic-ws) | |
3839 (throw 'nesting 'statement))))) | |
3840 (t ; endblock | |
3841 ; try to leap back to matching outward block by striding across | |
3842 ; indent level changing tokens then immediately | |
3843 ; previous line governs indentation. | |
3844 (let (( reg) (nest 1)) | |
3845 ;; verilog-ends => else|if|end|join(_any|_none|)|endcase|endclass|endtable|endspecify|endfunction|endtask|endgenerate|endgroup | |
3846 (cond | |
3847 ((match-end 3) ; end | |
3848 ;; Search back for matching begin | |
3849 (setq reg "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)" )) | |
3850 ((match-end 4) ; endcase | |
3851 ;; Search back for matching case | |
3852 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" )) | |
3853 ((match-end 5) ; endfunction | |
3854 ;; Search back for matching function | |
3855 (setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" )) | |
3856 ((match-end 6) ; endtask | |
3857 ;; Search back for matching task | |
3858 (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" )) | |
3859 ((match-end 7) ; endspecify | |
3860 ;; Search back for matching specify | |
3861 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" )) | |
3862 ((match-end 8) ; endtable | |
3863 ;; Search back for matching table | |
3864 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" )) | |
3865 ((match-end 9) ; endgenerate | |
3866 ;; Search back for matching generate | |
3867 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" )) | |
3868 ((match-end 10) ; joins | |
3869 ;; Search back for matching fork | |
3870 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|none\\)?\\>\\)" )) | |
3871 ((match-end 11) ; class | |
3872 ;; Search back for matching class | |
3873 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" )) | |
3874 ((match-end 12) ; covergroup | |
3875 ;; Search back for matching covergroup | |
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57956dd69d3f
(top-level): Fix spacing.
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parents:
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diff
changeset
|
3876 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" ))) |
79545 | 3877 (catch 'skip |
3878 (while (verilog-re-search-backward reg nil 'move) | |
3879 (cond | |
3880 ((match-end 1) ; begin | |
3881 (setq nest (1- nest)) | |
3882 (if (= 0 nest) | |
3883 (throw 'skip 1))) | |
3884 ((match-end 2) ; end | |
3885 (setq nest (1+ nest))))) | |
79799
57956dd69d3f
(top-level): Fix spacing.
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parents:
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diff
changeset
|
3886 ))))))) |
57956dd69d3f
(top-level): Fix spacing.
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parents:
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diff
changeset
|
3887 (throw 'nesting (verilog-calc-1))) |
79545 | 3888 );; catch nesting |
3889 );; type | |
3890 ) | |
3891 ;; Return type of block and indent level. | |
3892 (if (not type) | |
3893 (setq type 'cpp)) | |
3894 (if (> par 0) ; Unclosed Parenthesis | |
3895 (list 'cparenexp par) | |
3896 (cond | |
3897 ((eq type 'case) | |
3898 (list type (verilog-case-indent-level))) | |
3899 ((eq type 'statement) | |
3900 (list type (current-column))) | |
3901 ((eq type 'defun) | |
3902 (list type 0)) | |
3903 (t | |
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3904 (list type (verilog-current-indent-level)))))))) |
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3905 |
79545 | 3906 (defun verilog-wai () |
3907 "Show matching nesting block for debugging." | |
3908 (interactive) | |
3909 (save-excursion | |
3910 (let ((nesting (verilog-calc-1))) | |
3911 (message "You are at nesting %s" nesting)))) | |
3912 | |
3913 (defun verilog-calc-1 () | |
3914 (catch 'nesting | |
3915 (while (verilog-re-search-backward (concat "\\({\\|}\\|" verilog-indent-re "\\)") nil 'move) | |
3916 (cond | |
3917 ((equal (char-after) ?\{) | |
3918 (if (verilog-at-constraint-p) | |
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3919 (throw 'nesting 'block))) |
79545 | 3920 ((equal (char-after) ?\}) |
3921 | |
3922 (let ((there (verilog-at-close-constraint-p))) | |
3923 (if there (goto-char there)))) | |
3924 | |
3925 ((looking-at verilog-beg-block-re-ordered) | |
3926 (cond | |
3927 ((match-end 2) ; *sigh* could be "unique case" or "priority casex" | |
3928 (let ((here (point))) | |
3929 (verilog-beg-of-statement) | |
3930 (if (looking-at verilog-extended-case-re) | |
3931 (throw 'nesting 'case) | |
3932 (goto-char here))) | |
3933 (throw 'nesting 'case)) | |
3934 | |
3935 ;; need to consider typedef struct here... | |
3936 ((looking-at "\\<class\\|struct\\|function\\|task\\|property\\>") | |
3937 ; *sigh* These words have an optional prefix: | |
3938 ; extern {virtual|protected}? function a(); | |
3939 ; assert property (p_1); | |
3940 ; typedef class foo; | |
3941 ; and we don't want to confuse this with | |
3942 ; function a(); | |
3943 ; property | |
3944 ; ... | |
3945 ; endfunction | |
3946 (let ((here (point))) | |
3947 (save-excursion | |
3948 (verilog-beg-of-statement) | |
3949 (if (= (point) here) | |
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3950 (throw 'nesting 'block))))) |
79545 | 3951 (t (throw 'nesting 'block)))) |
3952 | |
3953 ((looking-at verilog-end-block-re) | |
3954 (verilog-leap-to-head) | |
3955 (if (verilog-in-case-region-p) | |
3956 (progn | |
3957 (verilog-leap-to-case-head) | |
3958 (if (looking-at verilog-case-re) | |
3959 (throw 'nesting 'case))))) | |
3960 | |
3961 ((looking-at (if (verilog-in-generate-region-p) | |
3962 verilog-defun-level-not-generate-re | |
3963 verilog-defun-level-re)) | |
3964 (throw 'nesting 'defun)) | |
3965 | |
3966 ((looking-at verilog-cpp-level-re) | |
3967 (throw 'nesting 'cpp)) | |
3968 | |
3969 ((bobp) | |
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3970 (throw 'nesting 'cpp)))) |
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3971 (throw 'nesting 'cpp))) |
79545 | 3972 |
3973 (defun verilog-calculate-indent-directive () | |
3974 "Return indentation level for directive. | |
3975 For speed, the searcher looks at the last directive, not the indent | |
3976 of the appropriate enclosing block." | |
3977 (let ((base -1) ;; Indent of the line that determines our indentation | |
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3978 (ind 0)) ;; Relative offset caused by other directives (like `endif on same line as `else) |
79545 | 3979 ;; Start at current location, scan back for another directive |
3980 | |
3981 (save-excursion | |
3982 (beginning-of-line) | |
3983 (while (and (< base 0) | |
3984 (verilog-re-search-backward verilog-directive-re nil t)) | |
3985 (cond ((save-excursion (skip-chars-backward " \t") (bolp)) | |
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3986 (setq base (current-indentation)))) |
79545 | 3987 (cond ((and (looking-at verilog-directive-end) (< base 0)) ;; Only matters when not at BOL |
3988 (setq ind (- ind verilog-indent-level-directive))) | |
3989 ((and (looking-at verilog-directive-middle) (>= base 0)) ;; Only matters when at BOL | |
3990 (setq ind (+ ind verilog-indent-level-directive))) | |
3991 ((looking-at verilog-directive-begin) | |
3992 (setq ind (+ ind verilog-indent-level-directive))))) | |
3993 ;; Adjust indent to starting indent of critical line | |
3994 (setq ind (max 0 (+ ind base)))) | |
3995 | |
3996 (save-excursion | |
3997 (beginning-of-line) | |
3998 (skip-chars-forward " \t") | |
3999 (cond ((or (looking-at verilog-directive-middle) | |
4000 (looking-at verilog-directive-end)) | |
4001 (setq ind (max 0 (- ind verilog-indent-level-directive)))))) | |
4002 ind)) | |
4003 | |
4004 (defun verilog-leap-to-case-head () | |
4005 (let ((nest 1)) | |
4006 (while (/= 0 nest) | |
4007 (verilog-re-search-backward "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" nil 'move) | |
4008 (cond | |
4009 ((match-end 1) | |
4010 (setq nest (1- nest))) | |
4011 ((match-end 2) | |
4012 (setq nest (1+ nest))) | |
4013 ((bobp) | |
4014 (ding 't) | |
4015 (setq nest 0)))))) | |
4016 | |
4017 (defun verilog-leap-to-head () | |
4018 "Move point to the head of this block; jump from end to matching begin, | |
4019 from endcase to matching case, and so on." | |
4020 (let ((reg nil) | |
4021 snest | |
4022 (nest 1)) | |
4023 (cond | |
4024 ((looking-at "\\<end\\>") | |
4025 ;; 1: Search back for matching begin | |
4026 (setq reg (concat "\\(\\<begin\\>\\)\\|\\(\\<end\\>\\)\\|" | |
4027 "\\(\\<endcase\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" ))) | |
4028 ((looking-at "\\<endcase\\>") | |
4029 ;; 2: Search back for matching case | |
4030 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>\\)\\|\\(\\<endcase\\>\\)" )) | |
4031 ((looking-at "\\<join\\(_any\\|_none\\)?\\>") | |
4032 ;; 3: Search back for matching fork | |
4033 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" )) | |
4034 ((looking-at "\\<endclass\\>") | |
4035 ;; 4: Search back for matching class | |
4036 (setq reg "\\(\\<class\\>\\)\\|\\(\\<endclass\\>\\)" )) | |
4037 ((looking-at "\\<endtable\\>") | |
4038 ;; 5: Search back for matching table | |
4039 (setq reg "\\(\\<table\\>\\)\\|\\(\\<endtable\\>\\)" )) | |
4040 ((looking-at "\\<endspecify\\>") | |
4041 ;; 6: Search back for matching specify | |
4042 (setq reg "\\(\\<specify\\>\\)\\|\\(\\<endspecify\\>\\)" )) | |
4043 ((looking-at "\\<endfunction\\>") | |
4044 ;; 7: Search back for matching function | |
4045 (setq reg "\\(\\<function\\>\\)\\|\\(\\<endfunction\\>\\)" )) | |
4046 ((looking-at "\\<endgenerate\\>") | |
4047 ;; 8: Search back for matching generate | |
4048 (setq reg "\\(\\<generate\\>\\)\\|\\(\\<endgenerate\\>\\)" )) | |
4049 ((looking-at "\\<endtask\\>") | |
4050 ;; 9: Search back for matching task | |
4051 (setq reg "\\(\\<task\\>\\)\\|\\(\\<endtask\\>\\)" )) | |
4052 ((looking-at "\\<endgroup\\>") | |
4053 ;; 10: Search back for matching covergroup | |
4054 (setq reg "\\(\\<covergroup\\>\\)\\|\\(\\<endgroup\\>\\)" )) | |
4055 ((looking-at "\\<endproperty\\>") | |
4056 ;; 11: Search back for matching property | |
4057 (setq reg "\\(\\<property\\>\\)\\|\\(\\<endproperty\\>\\)" )) | |
4058 ((looking-at "\\<endinterface\\>") | |
4059 ;; 12: Search back for matching interface | |
4060 (setq reg "\\(\\<interface\\>\\)\\|\\(\\<endinterface\\>\\)" )) | |
4061 ((looking-at "\\<endsequence\\>") | |
4062 ;; 12: Search back for matching sequence | |
4063 (setq reg "\\(\\<\\(rand\\)?sequence\\>\\)\\|\\(\\<endsequence\\>\\)" )) | |
4064 ((looking-at "\\<endclocking\\>") | |
4065 ;; 12: Search back for matching clocking | |
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4066 (setq reg "\\(\\<clocking\\)\\|\\(\\<endclocking\\>\\)" ))) |
79545 | 4067 (if reg |
4068 (catch 'skip | |
4069 (let (sreg) | |
4070 (while (verilog-re-search-backward reg nil 'move) | |
4071 (cond | |
4072 ((match-end 1) ; begin | |
4073 (setq nest (1- nest)) | |
4074 (if (= 0 nest) | |
4075 ;; Now previous line describes syntax | |
4076 (throw 'skip 1)) | |
4077 (if (and snest | |
4078 (= snest nest)) | |
4079 (setq reg sreg))) | |
4080 ((match-end 2) ; end | |
4081 (setq nest (1+ nest))) | |
4082 ((match-end 3) | |
4083 ;; endcase, jump to case | |
4084 (setq snest nest) | |
4085 (setq nest (1+ nest)) | |
4086 (setq sreg reg) | |
4087 (setq reg "\\(\\<randcase\\>\\|\\<case[xz]?\\>[^:]\\)\\|\\(\\<endcase\\>\\)" )) | |
4088 ((match-end 4) | |
4089 ;; join, jump to fork | |
4090 (setq snest nest) | |
4091 (setq nest (1+ nest)) | |
4092 (setq sreg reg) | |
4093 (setq reg "\\(\\<fork\\>\\)\\|\\(\\<join\\(_any\\|_none\\)?\\>\\)" )) | |
4094 ))))))) | |
4095 | |
4096 (defun verilog-continued-line () | |
4097 "Return true if this is a continued line. | |
4098 Set point to where line starts" | |
4099 (let ((continued 't)) | |
4100 (if (eq 0 (forward-line -1)) | |
4101 (progn | |
4102 (end-of-line) | |
4103 (verilog-backward-ws&directives) | |
4104 (if (bobp) | |
4105 (setq continued nil) | |
4106 (while (and continued | |
4107 (save-excursion | |
4108 (skip-chars-backward " \t") | |
4109 (not (bolp)))) | |
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4110 (setq continued (verilog-backward-token))))) |
79545 | 4111 (setq continued nil)) |
4112 continued)) | |
4113 | |
4114 (defun verilog-backward-token () | |
4115 "Step backward token, returning true if we are now at an end of line token." | |
4116 (interactive) | |
4117 (verilog-backward-syntactic-ws) | |
4118 (cond | |
4119 ((bolp) | |
4120 nil) | |
4121 (;-- Anything ending in a ; is complete | |
4122 (= (preceding-char) ?\;) | |
4123 nil) | |
4124 (; If a "}" is prefixed by a ";", then this is a complete statement | |
4125 ; i.e.: constraint foo { a = b; } | |
4126 (= (preceding-char) ?\}) | |
4127 (progn | |
4128 (backward-char) | |
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4129 (verilog-at-close-constraint-p))) |
79545 | 4130 (;-- constraint foo { a = b } |
4131 ; is a complete statement. *sigh* | |
4132 (= (preceding-char) ?\{) | |
4133 (progn | |
4134 (backward-char) | |
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4135 (not (verilog-at-constraint-p)))) |
79545 | 4136 (;-- Could be 'case (foo)' or 'always @(bar)' which is complete |
4137 ; also could be simply '@(foo)' | |
4138 ; or foo u1 #(a=8) | |
4139 ; (b, ... which ISN'T complete | |
4140 ;;;; Do we need this??? | |
4141 (= (preceding-char) ?\)) | |
4142 (progn | |
4143 (backward-char) | |
4144 (backward-up-list 1) | |
4145 (verilog-backward-syntactic-ws) | |
4146 (let ((back (point))) | |
4147 (forward-word -1) | |
4148 (cond | |
4149 ((looking-at "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|case\\(\\|[xz]\\)\\|for\\(\\|each\\|ever\\)\\|i\\(f\\|nitial\\)\\|repeat\\|while\\)\\>") | |
4150 (not (looking-at "\\<randcase\\>\\|\\<case[xz]?\\>[^:]"))) | |
4151 (t | |
4152 (goto-char back) | |
4153 (cond | |
4154 ((= (preceding-char) ?\@) | |
4155 (backward-char) | |
4156 (save-excursion | |
4157 (verilog-backward-token) | |
4158 (not (looking-at "\\<\\(always\\(_latch\\|_ff\\|_comb\\)?\\|initial\\|while\\)\\>")))) | |
4159 ((= (preceding-char) ?\#) | |
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4160 (backward-char)) |
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|
4161 (t t))))))) |
79545 | 4162 |
4163 (;-- any of begin|initial|while are complete statements; 'begin : foo' is also complete | |
4164 t | |
4165 (forward-word -1) | |
4166 (cond | |
4167 ((looking-at "\\<else\\>") | |
4168 t) | |
4169 ((looking-at verilog-indent-re) | |
4170 nil) | |
4171 (t | |
4172 (let | |
4173 ((back (point))) | |
4174 (verilog-backward-syntactic-ws) | |
4175 (cond | |
4176 ((= (preceding-char) ?\:) | |
4177 (backward-char) | |
4178 (verilog-backward-syntactic-ws) | |
4179 (backward-sexp) | |
4180 (if (looking-at verilog-nameable-item-re ) | |
4181 nil | |
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4182 t)) |
79545 | 4183 ((= (preceding-char) ?\#) |
4184 (backward-char) | |
4185 t) | |
4186 ((= (preceding-char) ?\`) | |
4187 (backward-char) | |
4188 t) | |
4189 | |
4190 (t | |
4191 (goto-char back) | |
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|
4192 t)))))))) |
79545 | 4193 |
4194 (defun verilog-backward-syntactic-ws (&optional bound) | |
4195 "Backward skip over syntactic whitespace for Emacs 19. | |
4196 Optional BOUND limits search." | |
4197 (save-restriction | |
4198 (let* ((bound (or bound (point-min))) (here bound) ) | |
4199 (if (< bound (point)) | |
4200 (progn | |
4201 (narrow-to-region bound (point)) | |
4202 (while (/= here (point)) | |
4203 (setq here (point)) | |
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4204 (verilog-skip-backward-comments)))))) |
79545 | 4205 t) |
4206 | |
4207 (defun verilog-forward-syntactic-ws (&optional bound) | |
4208 "Forward skip over syntactic whitespace for Emacs 19. | |
4209 Optional BOUND limits search." | |
4210 (save-restriction | |
4211 (let* ((bound (or bound (point-max))) | |
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4212 (here bound)) |
79545 | 4213 (if (> bound (point)) |
4214 (progn | |
4215 (narrow-to-region (point) bound) | |
4216 (while (/= here (point)) | |
4217 (setq here (point)) | |
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|
4218 (forward-comment (buffer-size)))))))) |
79545 | 4219 |
4220 (defun verilog-backward-ws&directives (&optional bound) | |
4221 "Backward skip over syntactic whitespace and compiler directives for Emacs 19. | |
4222 Optional BOUND limits search." | |
4223 (save-restriction | |
4224 (let* ((bound (or bound (point-min))) | |
4225 (here bound) | |
4226 (p nil) ) | |
4227 (if (< bound (point)) | |
4228 (progn | |
4229 (let ((state | |
4230 (save-excursion | |
4231 (parse-partial-sexp (point-min) (point))))) | |
4232 (cond | |
4233 ((nth 7 state) ;; in // comment | |
4234 (verilog-re-search-backward "//" nil 'move) | |
4235 (skip-chars-backward "/")) | |
4236 ((nth 4 state) ;; in /* */ comment | |
4237 (verilog-re-search-backward "/\*" nil 'move)))) | |
4238 (narrow-to-region bound (point)) | |
4239 (while (/= here (point)) | |
4240 (setq here (point)) | |
4241 (verilog-skip-backward-comments) | |
4242 (setq p | |
4243 (save-excursion | |
4244 (beginning-of-line) | |
4245 (cond | |
4246 ((verilog-within-translate-off) | |
4247 (verilog-back-to-start-translate-off (point-min))) | |
4248 ((looking-at verilog-directive-re-1) | |
4249 (point)) | |
4250 (t | |
4251 nil)))) | |
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|
4252 (if p (goto-char p)))))))) |
79545 | 4253 |
4254 (defun verilog-forward-ws&directives (&optional bound) | |
4255 "Forward skip over syntactic whitespace and compiler directives for Emacs 19. | |
4256 Optional BOUND limits search." | |
4257 (save-restriction | |
4258 (let* ((bound (or bound (point-max))) | |
4259 (here bound) | |
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|
4260 jump) |
79545 | 4261 (if (> bound (point)) |
4262 (progn | |
4263 (let ((state | |
4264 (save-excursion | |
4265 (parse-partial-sexp (point-min) (point))))) | |
4266 (cond | |
4267 ((nth 7 state) ;; in // comment | |
4268 (verilog-re-search-forward "//" nil 'move)) | |
4269 ((nth 4 state) ;; in /* */ comment | |
4270 (verilog-re-search-forward "/\*" nil 'move)))) | |
4271 (narrow-to-region (point) bound) | |
4272 (while (/= here (point)) | |
4273 (setq here (point) | |
4274 jump nil) | |
4275 (forward-comment (buffer-size)) | |
4276 (save-excursion | |
4277 (beginning-of-line) | |
4278 (if (looking-at verilog-directive-re-1) | |
4279 (setq jump t))) | |
4280 (if jump | |
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|
4281 (beginning-of-line 2)))))))) |
79545 | 4282 |
4283 (defun verilog-in-comment-p () | |
4284 "Return true if in a star or // comment." | |
4285 (let ((state | |
4286 (save-excursion | |
4287 (parse-partial-sexp (point-min) (point))))) | |
4288 (or (nth 4 state) (nth 7 state)))) | |
4289 | |
4290 (defun verilog-in-star-comment-p () | |
4291 "Return true if in a star comment." | |
4292 (let ((state | |
4293 (save-excursion | |
4294 (parse-partial-sexp (point-min) (point))))) | |
4295 (and | |
4296 (nth 4 state) ; t if in a comment of style a // or b /**/ | |
4297 (not | |
4298 (nth 7 state) ; t if in a comment of style b /**/ | |
4299 )))) | |
4300 | |
4301 (defun verilog-in-slash-comment-p () | |
4302 "Return true if in a slash comment." | |
4303 (let ((state | |
4304 (save-excursion | |
4305 (parse-partial-sexp (point-min) (point))))) | |
4306 (nth 7 state))) | |
4307 | |
4308 (defun verilog-in-comment-or-string-p () | |
4309 "Return true if in a string or comment." | |
4310 (let ((state | |
4311 (save-excursion | |
4312 (parse-partial-sexp (point-min) (point))))) | |
4313 (or (nth 3 state) (nth 4 state) (nth 7 state)))) ; Inside string or comment) | |
4314 | |
4315 (defun verilog-in-escaped-name-p () | |
4316 "Return true if in an escaped name." | |
4317 (save-excursion | |
4318 (backward-char) | |
4319 (skip-chars-backward "^ \t\n\f") | |
4320 (if (equal (char-after (point) ) ?\\ ) | |
4321 t | |
4322 nil))) | |
4323 | |
4324 (defun verilog-in-paren () | |
4325 "Return true if in a parenthetical expression." | |
4326 (let ((state | |
4327 (save-excursion | |
4328 (parse-partial-sexp (point-min) (point))))) | |
4329 (> (nth 0 state) 0 ))) | |
4330 | |
4331 (defun verilog-in-coverage () | |
4332 "Return true if in a constraint or coverpoint expression." | |
4333 (interactive) | |
4334 (save-excursion | |
4335 (if (verilog-in-paren) | |
4336 (progn | |
4337 (backward-up-list 1) | |
4338 (verilog-at-constraint-p) | |
4339 ) | |
4340 nil))) | |
4341 (defun verilog-at-close-constraint-p () | |
4342 "If at the } that closes a constraint or covergroup, return true." | |
4343 (if (and | |
4344 (equal (char-after) ?\}) | |
4345 (verilog-in-paren)) | |
4346 | |
4347 (save-excursion | |
4348 (verilog-backward-ws&directives) | |
4349 (if (equal (char-before) ?\;) | |
4350 (point) | |
4351 nil)))) | |
4352 | |
4353 (defun verilog-at-constraint-p () | |
4354 "If at the { of a constraint or coverpoint definition, return true, moving point to constraint." | |
4355 (if (save-excursion | |
4356 (and | |
4357 (equal (char-after) ?\{) | |
4358 (forward-list) | |
4359 (progn (backward-char 1) | |
4360 (verilog-backward-ws&directives) | |
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parents:
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|
4361 (equal (char-before) ?\;)))) |
79545 | 4362 ;; maybe |
4363 (verilog-re-search-backward "\\<constraint\\|coverpoint\\|cross\\>" nil 'move) | |
4364 ;; not | |
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diff
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|
4365 nil)) |
79545 | 4366 |
4367 (defun verilog-parenthesis-depth () | |
4368 "Return non zero if in parenthetical-expression." | |
4369 (save-excursion | |
4370 (nth 1 (parse-partial-sexp (point-min) (point))))) | |
4371 | |
4372 | |
4373 (defun verilog-skip-forward-comment-or-string () | |
4374 "Return true if in a string or comment." | |
4375 (let ((state | |
4376 (save-excursion | |
4377 (parse-partial-sexp (point-min) (point))))) | |
4378 (cond | |
4379 ((nth 3 state) ;Inside string | |
4380 (goto-char (nth 3 state)) | |
4381 t) | |
4382 ((nth 7 state) ;Inside // comment | |
4383 (forward-line 1) | |
4384 t) | |
4385 ((nth 4 state) ;Inside any comment (hence /**/) | |
4386 (search-forward "*/")) | |
4387 (t | |
4388 nil)))) | |
4389 | |
4390 (defun verilog-skip-backward-comment-or-string () | |
4391 "Return true if in a string or comment." | |
4392 (let ((state | |
4393 (save-excursion | |
4394 (parse-partial-sexp (point-min) (point))))) | |
4395 (cond | |
4396 ((nth 3 state) ;Inside string | |
4397 (search-backward "\"") | |
4398 t) | |
4399 ((nth 7 state) ;Inside // comment | |
4400 (search-backward "//") | |
4401 (skip-chars-backward "/") | |
4402 t) | |
4403 ((nth 4 state) ;Inside /* */ comment | |
4404 (search-backward "/*") | |
4405 t) | |
4406 (t | |
4407 nil)))) | |
4408 | |
4409 (defun verilog-skip-backward-comments () | |
4410 "Return true if a comment was skipped." | |
4411 (let ((more t)) | |
4412 (while more | |
4413 (setq more | |
4414 (let ((state | |
4415 (save-excursion | |
4416 (parse-partial-sexp (point-min) (point))))) | |
4417 (cond | |
4418 ((nth 7 state) ;Inside // comment | |
4419 (search-backward "//") | |
4420 (skip-chars-backward "/") | |
4421 (skip-chars-backward " \t\n\f") | |
4422 t) | |
4423 ((nth 4 state) ;Inside /* */ comment | |
4424 (search-backward "/*") | |
4425 (skip-chars-backward " \t\n\f") | |
4426 t) | |
4427 ((and (not (bobp)) | |
4428 (= (char-before) ?\/) | |
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diff
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|
4429 (= (char-before (1- (point))) ?\*)) |
79545 | 4430 (goto-char (- (point) 2)) |
4431 t) | |
4432 (t | |
4433 (skip-chars-backward " \t\n\f") | |
4434 nil))))))) | |
4435 | |
4436 (defun verilog-skip-forward-comment-p () | |
4437 "If in comment, move to end and return true." | |
4438 (let (state) | |
4439 (progn | |
4440 (setq state | |
4441 (save-excursion | |
4442 (parse-partial-sexp (point-min) (point)))) | |
4443 (cond | |
4444 ((nth 3 state) | |
4445 t) | |
4446 ((nth 7 state) ;Inside // comment | |
4447 (end-of-line) | |
4448 (forward-char 1) | |
4449 t) | |
4450 ((nth 4 state) ;Inside any comment | |
4451 t) | |
4452 (t | |
4453 nil))))) | |
4454 | |
4455 (defun verilog-indent-line-relative () | |
4456 "Cheap version of indent line. | |
4457 Only look at a few lines to determine indent level." | |
4458 (interactive) | |
4459 (let ((indent-str) | |
4460 (sp (point))) | |
4461 (if (looking-at "^[ \t]*$") | |
4462 (cond ;- A blank line; No need to be too smart. | |
4463 ((bobp) | |
4464 (setq indent-str (list 'cpp 0))) | |
4465 ((verilog-continued-line) | |
4466 (let ((sp1 (point))) | |
4467 (if (verilog-continued-line) | |
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* progmodes/verilog-mode.el (top-level): Don't require compile.
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79555
diff
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|
4468 (progn |
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* progmodes/verilog-mode.el (top-level): Don't require compile.
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79555
diff
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|
4469 (goto-char sp) |
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|
4470 (setq indent-str |
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4471 (list 'statement (verilog-current-indent-level)))) |
79545 | 4472 (goto-char sp1) |
4473 (setq indent-str (list 'block (verilog-current-indent-level))))) | |
4474 (goto-char sp)) | |
4475 ((goto-char sp) | |
4476 (setq indent-str (verilog-calculate-indent)))) | |
4477 (progn (skip-chars-forward " \t") | |
4478 (setq indent-str (verilog-calculate-indent)))) | |
4479 (verilog-do-indent indent-str))) | |
4480 | |
4481 (defun verilog-indent-line () | |
4482 "Indent for special part of code." | |
4483 (verilog-do-indent (verilog-calculate-indent))) | |
4484 | |
4485 (defun verilog-do-indent (indent-str) | |
4486 (let ((type (car indent-str)) | |
4487 (ind (car (cdr indent-str)))) | |
4488 (cond | |
4489 (; handle continued exp | |
4490 (eq type 'cexp) | |
4491 (let ((here (point))) | |
4492 (verilog-backward-syntactic-ws) | |
4493 (cond | |
4494 ((or | |
4495 (= (preceding-char) ?\,) | |
4496 (= (preceding-char) ?\]) | |
4497 (save-excursion | |
4498 (verilog-beg-of-statement-1) | |
4499 (looking-at verilog-declaration-re))) | |
4500 (let* ( fst | |
4501 (val | |
4502 (save-excursion | |
4503 (backward-char 1) | |
4504 (verilog-beg-of-statement-1) | |
4505 (setq fst (point)) | |
4506 (if (looking-at verilog-declaration-re) | |
4507 (progn ;; we have multiple words | |
4508 (goto-char (match-end 0)) | |
4509 (skip-chars-forward " \t") | |
4510 (cond | |
4511 ((and verilog-indent-declaration-macros | |
4512 (= (following-char) ?\`)) | |
4513 (progn | |
4514 (forward-char 1) | |
4515 (forward-word 1) | |
4516 (skip-chars-forward " \t"))) | |
4517 ((= (following-char) ?\[) | |
4518 (progn | |
4519 (forward-char 1) | |
4520 (backward-up-list -1) | |
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4521 (skip-chars-forward " \t")))) |
79545 | 4522 (current-column)) |
4523 (progn | |
4524 (goto-char fst) | |
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4525 (+ (current-column) verilog-cexp-indent)))))) |
79545 | 4526 (goto-char here) |
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parents:
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diff
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|
4527 (indent-line-to val))) |
79545 | 4528 ((= (preceding-char) ?\) ) |
4529 (goto-char here) | |
4530 (let ((val (eval (cdr (assoc type verilog-indent-alist))))) | |
4531 (indent-line-to val))) | |
4532 (t | |
4533 (goto-char here) | |
4534 (let ((val)) | |
4535 (verilog-beg-of-statement-1) | |
4536 (if (and (< (point) here) | |
4537 (verilog-re-search-forward "=[ \\t]*" here 'move)) | |
4538 (setq val (current-column)) | |
4539 (setq val (eval (cdr (assoc type verilog-indent-alist))))) | |
4540 (goto-char here) | |
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diff
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|
4541 (indent-line-to val)))))) |
79545 | 4542 |
4543 (; handle inside parenthetical expressions | |
4544 (eq type 'cparenexp) | |
4545 (let ((val (save-excursion | |
4546 (backward-up-list 1) | |
4547 (forward-char 1) | |
4548 (skip-chars-forward " \t") | |
4549 (current-column)))) | |
4550 (indent-line-to val) | |
4551 (if (and (not (verilog-in-struct-region-p)) | |
4552 (looking-at verilog-declaration-re)) | |
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parents:
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|
4553 (verilog-indent-declaration ind)))) |
79545 | 4554 |
4555 (;-- Handle the ends | |
4556 (or | |
4557 (looking-at verilog-end-block-re ) | |
4558 (verilog-at-close-constraint-p)) | |
4559 (let ((val (if (eq type 'statement) | |
4560 (- ind verilog-indent-level) | |
4561 ind))) | |
4562 (indent-line-to val))) | |
4563 | |
4564 (;-- Case -- maybe line 'em up | |
4565 (and (eq type 'case) (not (looking-at "^[ \t]*$"))) | |
4566 (progn | |
4567 (cond | |
4568 ((looking-at "\\<endcase\\>") | |
4569 (indent-line-to ind)) | |
4570 (t | |
4571 (let ((val (eval (cdr (assoc type verilog-indent-alist))))) | |
4572 (indent-line-to val)))))) | |
4573 | |
4574 (;-- defun | |
4575 (and (eq type 'defun) | |
4576 (looking-at verilog-zero-indent-re)) | |
4577 (indent-line-to 0)) | |
4578 | |
4579 (;-- declaration | |
4580 (and (or | |
4581 (eq type 'defun) | |
4582 (eq type 'block)) | |
4583 (looking-at verilog-declaration-re)) | |
4584 (verilog-indent-declaration ind)) | |
4585 | |
4586 (;-- Everything else | |
4587 t | |
4588 (let ((val (eval (cdr (assoc type verilog-indent-alist))))) | |
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parents:
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diff
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|
4589 (indent-line-to val)))) |
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parents:
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diff
changeset
|
4590 |
79545 | 4591 (if (looking-at "[ \t]+$") |
4592 (skip-chars-forward " \t")) | |
4593 indent-str ; Return indent data | |
4594 )) | |
4595 | |
4596 (defun verilog-current-indent-level () | |
4597 "Return the indent-level the current statement has." | |
4598 (save-excursion | |
4599 (let (par-pos) | |
4600 (beginning-of-line) | |
4601 (setq par-pos (verilog-parenthesis-depth)) | |
4602 (while par-pos | |
4603 (goto-char par-pos) | |
4604 (beginning-of-line) | |
4605 (setq par-pos (verilog-parenthesis-depth))) | |
4606 (skip-chars-forward " \t") | |
4607 (current-column)))) | |
4608 | |
4609 (defun verilog-case-indent-level () | |
4610 "Return the indent-level the current statement has. | |
4611 Do not count named blocks or case-statements." | |
4612 (save-excursion | |
4613 (skip-chars-forward " \t") | |
4614 (cond | |
4615 ((looking-at verilog-named-block-re) | |
4616 (current-column)) | |
4617 ((and (not (looking-at verilog-case-re)) | |
4618 (looking-at "^[^:;]+[ \t]*:")) | |
4619 (verilog-re-search-forward ":" nil t) | |
4620 (skip-chars-forward " \t") | |
4621 (current-column)) | |
4622 (t | |
4623 (current-column))))) | |
4624 | |
4625 (defun verilog-indent-comment () | |
4626 "Indent current line as comment." | |
4627 (let* ((stcol | |
4628 (cond | |
4629 ((verilog-in-star-comment-p) | |
4630 (save-excursion | |
4631 (re-search-backward "/\\*" nil t) | |
4632 (1+(current-column)))) | |
4633 (comment-column | |
4634 comment-column ) | |
4635 (t | |
4636 (save-excursion | |
4637 (re-search-backward "//" nil t) | |
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(top-level): Fix spacing.
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parents:
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diff
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|
4638 (current-column)))))) |
79545 | 4639 (indent-line-to stcol) |
4640 stcol)) | |
4641 | |
4642 (defun verilog-more-comment () | |
4643 "Make more comment lines like the previous." | |
4644 (let* ((star 0) | |
4645 (stcol | |
4646 (cond | |
4647 ((verilog-in-star-comment-p) | |
4648 (save-excursion | |
4649 (setq star 1) | |
4650 (re-search-backward "/\\*" nil t) | |
4651 (1+(current-column)))) | |
4652 (comment-column | |
4653 comment-column ) | |
4654 (t | |
4655 (save-excursion | |
4656 (re-search-backward "//" nil t) | |
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(top-level): Fix spacing.
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diff
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|
4657 (current-column)))))) |
79545 | 4658 (progn |
4659 (indent-to stcol) | |
4660 (if (and star | |
4661 (save-excursion | |
4662 (forward-line -1) | |
4663 (skip-chars-forward " \t") | |
4664 (looking-at "\*"))) | |
4665 (insert "* "))))) | |
4666 | |
4667 (defun verilog-comment-indent (&optional arg) | |
4668 "Return the column number the line should be indented to. | |
4669 ARG is ignored, for `comment-indent-function' compatibility." | |
4670 (cond | |
4671 ((verilog-in-star-comment-p) | |
4672 (save-excursion | |
4673 (re-search-backward "/\\*" nil t) | |
4674 (1+(current-column)))) | |
4675 ( comment-column | |
4676 comment-column ) | |
4677 (t | |
4678 (save-excursion | |
4679 (re-search-backward "//" nil t) | |
4680 (current-column))))) | |
4681 | |
4682 ;; | |
4683 | |
4684 (defun verilog-pretty-declarations () | |
4685 "Line up declarations around point." | |
4686 (interactive) | |
4687 (save-excursion | |
4688 (if (progn | |
4689 (verilog-beg-of-statement-1) | |
4690 (looking-at verilog-declaration-re)) | |
4691 (let* ((m1 (make-marker)) | |
4692 (e) (r) | |
4693 (here (point)) | |
4694 ;; Start of declaration range | |
4695 (start | |
4696 (progn | |
4697 (verilog-beg-of-statement-1) | |
4698 (while (looking-at verilog-declaration-re) | |
4699 (beginning-of-line) | |
4700 (setq e (point)) | |
4701 (verilog-backward-syntactic-ws) | |
4702 (backward-char) | |
4703 (verilog-beg-of-statement-1)) ;Ack, need to grok `define | |
4704 e)) | |
4705 ;; End of declaration range | |
4706 (end | |
4707 (progn | |
4708 (goto-char here) | |
4709 (verilog-end-of-statement) | |
4710 (setq e (point)) ;Might be on last line | |
4711 (verilog-forward-syntactic-ws) | |
4712 (while (looking-at verilog-declaration-re) | |
4713 (beginning-of-line) | |
4714 (verilog-end-of-statement) | |
4715 (setq e (point)) | |
4716 (verilog-forward-syntactic-ws)) | |
4717 e)) | |
4718 (edpos (set-marker (make-marker) end)) | |
4719 (ind) | |
4720 (base-ind | |
4721 (progn | |
4722 (goto-char start) | |
4723 (verilog-do-indent (verilog-calculate-indent)) | |
4724 (verilog-forward-ws&directives) | |
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(top-level): Fix spacing.
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parents:
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diff
changeset
|
4725 (current-column)))) |
79545 | 4726 (goto-char end) |
4727 (goto-char start) | |
4728 (if (> (- end start) 100) | |
4729 (message "Lining up declarations..(please stand by)")) | |
4730 ;; Get the beginning of line indent first | |
4731 (while (progn (setq e (marker-position edpos)) | |
4732 (< (point) e)) | |
4733 (cond | |
4734 ( (save-excursion (skip-chars-backward " \t") | |
4735 (bolp)) | |
4736 (verilog-forward-ws&directives) | |
4737 (indent-line-to base-ind) | |
4738 (verilog-forward-ws&directives) | |
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(top-level): Fix spacing.
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|
4739 (verilog-re-search-forward "[ \t\n\f]" e 'move)) |
79545 | 4740 (t |
4741 (just-one-space) | |
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(top-level): Fix spacing.
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parents:
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|
4742 (verilog-re-search-forward "[ \t\n\f]" e 'move))) |
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parents:
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diff
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|
4743 ;;(forward-line) |
79545 | 4744 ) |
4745 ;; Now find biggest prefix | |
4746 (setq ind (verilog-get-lineup-indent start edpos)) | |
4747 ;; Now indent each line. | |
4748 (goto-char start) | |
4749 (while (progn (setq e (marker-position edpos)) | |
4750 (setq r (- e (point))) | |
4751 (> r 0)) | |
4752 (setq e (point)) | |
4753 (message "%d" r) | |
4754 (cond | |
4755 ((or (and verilog-indent-declaration-macros | |
4756 (looking-at verilog-declaration-re-1-macro)) | |
4757 (looking-at verilog-declaration-re-1-no-macro)) | |
4758 (let ((p (match-end 0))) | |
4759 (set-marker m1 p) | |
4760 (if (verilog-re-search-forward "[[#`]" p 'move) | |
4761 (progn | |
4762 (forward-char -1) | |
4763 (just-one-space) | |
4764 (goto-char (marker-position m1)) | |
4765 (just-one-space) | |
4766 (indent-to ind)) | |
4767 (progn | |
4768 (just-one-space) | |
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|
4769 (indent-to ind))))) |
79545 | 4770 ((verilog-continued-line-1 start) |
4771 (goto-char e) | |
4772 (indent-line-to ind)) | |
4773 (t ; Must be comment or white space | |
4774 (goto-char e) | |
4775 (verilog-forward-ws&directives) | |
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|
4776 (forward-line -1))) |
79545 | 4777 (forward-line 1)) |
4778 (message ""))))) | |
4779 | |
4780 (defun verilog-pretty-expr (&optional myre) | |
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|
4781 "Line up expressions around point, or optional regexp MYRE." |
79545 | 4782 (interactive "sRegular Expression: ((<|:)?=) ") |
4783 (save-excursion | |
4784 (if (or (eq myre nil) | |
4785 (string-equal myre "")) | |
4786 (setq myre "\\(<\\|:\\)?=")) | |
4787 ; (setq myre (concat "\\(^[^;" myre "]*\\)\\([" myre "]\\)")) | |
4788 (setq myre (concat "\\(^[^;#:?=]*\\)\\([" myre "]\\)")) | |
4789 (beginning-of-line) | |
4790 (if (and (not (looking-at (concat "^\\s-*" verilog-complete-reg))) | |
4791 (looking-at myre)) | |
4792 (let* ((here (point)) | |
4793 (e) (r) | |
4794 (start | |
4795 (progn | |
4796 (beginning-of-line) | |
4797 (setq e (point)) | |
4798 (verilog-backward-syntactic-ws) | |
4799 (beginning-of-line) | |
4800 (while (and (not (looking-at (concat "^\\s-*" verilog-complete-reg))) | |
4801 (looking-at myre) | |
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|
4802 (not (bobp))) |
79545 | 4803 (setq e (point)) |
4804 (verilog-backward-syntactic-ws) | |
4805 (beginning-of-line) | |
4806 ) ;Ack, need to grok `define | |
4807 e)) | |
4808 (end | |
4809 (progn | |
4810 (goto-char here) | |
4811 (end-of-line) | |
4812 (setq e (point)) ;Might be on last line | |
4813 (verilog-forward-syntactic-ws) | |
4814 (beginning-of-line) | |
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|
4815 (while (and (not (looking-at |
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|
4816 (concat "^\\s-*" verilog-complete-reg))) |
79545 | 4817 (looking-at myre)) |
4818 (end-of-line) | |
4819 (setq e (point)) | |
4820 (verilog-forward-syntactic-ws) | |
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|
4821 (beginning-of-line)) |
79545 | 4822 e)) |
4823 (edpos (set-marker (make-marker) end)) | |
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4824 (ind)) |
79545 | 4825 (goto-char start) |
4826 (verilog-do-indent (verilog-calculate-indent)) | |
4827 (if (> (- end start) 100) | |
4828 (message "Lining up expressions..(please stand by)")) | |
4829 | |
4830 ;; Set indent to minimum throughout region | |
4831 (while (< (point) (marker-position edpos)) | |
4832 (beginning-of-line) | |
4833 (verilog-just-one-space myre) | |
4834 (end-of-line) | |
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|
4835 (verilog-forward-syntactic-ws)) |
79545 | 4836 |
4837 ;; Now find biggest prefix | |
4838 (setq ind (verilog-get-lineup-indent-2 myre start edpos)) | |
4839 | |
4840 ;; Now indent each line. | |
4841 (goto-char start) | |
4842 (while (progn (setq e (marker-position edpos)) | |
4843 (setq r (- e (point))) | |
4844 (> r 0)) | |
4845 (setq e (point)) | |
4846 (message "%d" r) | |
4847 (cond | |
4848 ((looking-at myre) | |
4849 (goto-char (match-end 1)) | |
4850 (if (eq (char-after) ?=) | |
4851 (indent-to (1+ ind)) ; line up the = of the <= with surrounding = | |
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4852 (indent-to ind))) |
79545 | 4853 ((verilog-continued-line-1 start) |
4854 (goto-char e) | |
4855 (indent-line-to ind)) | |
4856 (t ; Must be comment or white space | |
4857 (goto-char e) | |
4858 (verilog-forward-ws&directives) | |
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4859 (forward-line -1))) |
79545 | 4860 (forward-line 1)) |
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4861 (message ""))))) |
79545 | 4862 |
4863 (defun verilog-just-one-space (myre) | |
4864 "Remove extra spaces around regular expression MYRE." | |
4865 (interactive) | |
4866 (if (and (not(looking-at verilog-complete-reg)) | |
4867 (looking-at myre)) | |
4868 (let ((p1 (match-end 1)) | |
4869 (p2 (match-end 2))) | |
4870 (progn | |
4871 (goto-char p2) | |
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4872 (if (looking-at "\\s-") (just-one-space)) |
79545 | 4873 (goto-char p1) |
4874 (forward-char -1) | |
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|
4875 (if (looking-at "\\s-") (just-one-space))))) |
79545 | 4876 (message "")) |
4877 | |
4878 (defun verilog-indent-declaration (baseind) | |
4879 "Indent current lines as declaration. | |
4880 Line up the variable names based on previous declaration's indentation. | |
4881 BASEIND is the base indent to offset everything." | |
4882 (interactive) | |
4883 (let ((pos (point-marker)) | |
4884 (lim (save-excursion | |
4885 ;; (verilog-re-search-backward verilog-declaration-opener nil 'move) | |
4886 (verilog-re-search-backward "\\(\\<begin\\>\\)\\|\\(\\<module\\>\\)\\|\\(\\<task\\>\\)" nil 'move) | |
4887 (point))) | |
4888 (ind) | |
4889 (val) | |
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|
4890 (m1 (make-marker))) |
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|
4891 (setq val |
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|
4892 (+ baseind (eval (cdr (assoc 'declaration verilog-indent-alist))))) |
79545 | 4893 (indent-line-to val) |
4894 | |
4895 ;; Use previous declaration (in this module) as template. | |
4896 (if (or (memq 'all verilog-auto-lineup) | |
4897 (memq 'declaration verilog-auto-lineup)) | |
79546 | 4898 (if (verilog-re-search-backward |
79545 | 4899 (or (and verilog-indent-declaration-macros |
4900 verilog-declaration-re-1-macro) | |
4901 verilog-declaration-re-1-no-macro) lim t) | |
4902 (progn | |
4903 (goto-char (match-end 0)) | |
4904 (skip-chars-forward " \t") | |
4905 (setq ind (current-column)) | |
4906 (goto-char pos) | |
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|
4907 (setq val |
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|
4908 (+ baseind |
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|
4909 (eval (cdr (assoc 'declaration verilog-indent-alist))))) |
79545 | 4910 (indent-line-to val) |
4911 (if (and verilog-indent-declaration-macros | |
4912 (looking-at verilog-declaration-re-2-macro)) | |
4913 (let ((p (match-end 0))) | |
4914 (set-marker m1 p) | |
4915 (if (verilog-re-search-forward "[[#`]" p 'move) | |
4916 (progn | |
4917 (forward-char -1) | |
4918 (just-one-space) | |
4919 (goto-char (marker-position m1)) | |
4920 (just-one-space) | |
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4921 (indent-to ind)) |
79545 | 4922 (if (/= (current-column) ind) |
4923 (progn | |
4924 (just-one-space) | |
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4925 (indent-to ind))))) |
79545 | 4926 (if (looking-at verilog-declaration-re-2-no-macro) |
4927 (let ((p (match-end 0))) | |
4928 (set-marker m1 p) | |
4929 (if (verilog-re-search-forward "[[`#]" p 'move) | |
4930 (progn | |
4931 (forward-char -1) | |
4932 (just-one-space) | |
4933 (goto-char (marker-position m1)) | |
4934 (just-one-space) | |
4935 (indent-to ind)) | |
4936 (if (/= (current-column) ind) | |
4937 (progn | |
4938 (just-one-space) | |
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4939 (indent-to ind)))))))))) |
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4940 (goto-char pos))) |
79545 | 4941 |
4942 (defun verilog-get-lineup-indent (b edpos) | |
4943 "Return the indent level that will line up several lines within the region. | |
4944 Region is defined by B and EDPOS." | |
4945 (save-excursion | |
4946 (let ((ind 0) e) | |
4947 (goto-char b) | |
4948 ;; Get rightmost position | |
4949 (while (progn (setq e (marker-position edpos)) | |
4950 (< (point) e)) | |
79546 | 4951 (if (verilog-re-search-forward |
79545 | 4952 (or (and verilog-indent-declaration-macros |
4953 verilog-declaration-re-1-macro) | |
4954 verilog-declaration-re-1-no-macro) e 'move) | |
4955 (progn | |
4956 (goto-char (match-end 0)) | |
4957 (verilog-backward-syntactic-ws) | |
4958 (if (> (current-column) ind) | |
4959 (setq ind (current-column))) | |
4960 (goto-char (match-end 0))))) | |
4961 (if (> ind 0) | |
4962 (1+ ind) | |
4963 ;; No lineup-string found | |
4964 (goto-char b) | |
4965 (end-of-line) | |
4966 (skip-chars-backward " \t") | |
4967 (1+ (current-column)))))) | |
4968 | |
4969 (defun verilog-get-lineup-indent-2 (myre b edpos) | |
4970 "Return the indent level that will line up several lines within the region." | |
4971 (save-excursion | |
4972 (let ((ind 0) e) | |
4973 (goto-char b) | |
4974 ;; Get rightmost position | |
4975 (while (progn (setq e (marker-position edpos)) | |
4976 (< (point) e)) | |
4977 (if (verilog-re-search-forward myre e 'move) | |
4978 (progn | |
4979 (goto-char (match-end 0)) | |
4980 (verilog-backward-syntactic-ws) | |
4981 (if (> (current-column) ind) | |
4982 (setq ind (current-column))) | |
4983 (goto-char (match-end 0))))) | |
4984 (if (> ind 0) | |
4985 (1+ ind) | |
4986 ;; No lineup-string found | |
4987 (goto-char b) | |
4988 (end-of-line) | |
4989 (skip-chars-backward " \t") | |
4990 (1+ (current-column)))))) | |
4991 | |
4992 (defun verilog-comment-depth (type val) | |
4993 "A useful mode debugging aide. TYPE and VAL are comments for insertion." | |
4994 (save-excursion | |
4995 (let | |
4996 ((b (prog2 | |
4997 (beginning-of-line) | |
4998 (point-marker) | |
4999 (end-of-line))) | |
5000 (e (point-marker))) | |
5001 (if (re-search-backward " /\\* \[#-\]# \[a-zA-Z\]+ \[0-9\]+ ## \\*/" b t) | |
5002 (progn | |
5003 (replace-match " /* -# ## */") | |
5004 (end-of-line)) | |
5005 (progn | |
5006 (end-of-line) | |
5007 (insert " /* ## ## */")))) | |
5008 (backward-char 6) | |
5009 (insert | |
5010 (format "%s %d" type val)))) | |
5011 | |
5012 ;; | |
5013 ;; | |
5014 ;; Completion | |
5015 ;; | |
5016 (defvar verilog-str nil) | |
5017 (defvar verilog-all nil) | |
5018 (defvar verilog-pred nil) | |
5019 (defvar verilog-buffer-to-use nil) | |
5020 (defvar verilog-flag nil) | |
5021 (defvar verilog-toggle-completions nil | |
5022 "*True means \\<verilog-mode-map>\\[verilog-complete-word] should try all possible completions one by one. | |
5023 Repeated use of \\[verilog-complete-word] will show you all of them. | |
5024 Normally, when there is more than one possible completion, | |
5025 it displays a list of all possible completions.") | |
5026 | |
5027 | |
5028 (defvar verilog-type-keywords | |
5029 '( | |
5030 "and" "buf" "bufif0" "bufif1" "cmos" "defparam" "inout" "input" | |
5031 "integer" "localparam" "logic" "mailbox" "nand" "nmos" "nor" "not" "notif0" | |
5032 "notif1" "or" "output" "parameter" "pmos" "pull0" "pull1" "pullup" | |
5033 "rcmos" "real" "realtime" "reg" "rnmos" "rpmos" "rtran" "rtranif0" | |
5034 "rtranif1" "semaphore" "time" "tran" "tranif0" "tranif1" "tri" "tri0" "tri1" | |
5035 "triand" "trior" "trireg" "wand" "wire" "wor" "xnor" "xor" | |
5036 ) | |
5037 "*Keywords for types used when completing a word in a declaration or parmlist. | |
5038 \(eg. integer, real, reg...)") | |
5039 | |
5040 (defvar verilog-cpp-keywords | |
5041 '("module" "macromodule" "primitive" "timescale" "define" "ifdef" "ifndef" "else" | |
5042 "endif") | |
5043 "*Keywords to complete when at first word of a line in declarative scope. | |
5044 \(eg. initial, always, begin, assign.) | |
5045 The procedures and variables defined within the Verilog program | |
5046 will be completed runtime and should not be added to this list.") | |
5047 | |
5048 (defvar verilog-defun-keywords | |
5049 (append | |
5050 '( | |
5051 "always" "always_comb" "always_ff" "always_latch" "assign" | |
5052 "begin" "end" "generate" "endgenerate" "module" "endmodule" | |
5053 "specify" "endspecify" "function" "endfunction" "initial" "final" | |
5054 "task" "endtask" "primitive" "endprimitive" | |
5055 ) | |
5056 verilog-type-keywords) | |
5057 "*Keywords to complete when at first word of a line in declarative scope. | |
5058 \(eg. initial, always, begin, assign.) | |
5059 The procedures and variables defined within the Verilog program | |
5060 will be completed runtime and should not be added to this list.") | |
5061 | |
5062 (defvar verilog-block-keywords | |
5063 '( | |
5064 "begin" "break" "case" "continue" "else" "end" "endfunction" | |
5065 "endgenerate" "endinterface" "endpackage" "endspecify" "endtask" | |
5066 "for" "fork" "if" "join" "join_any" "join_none" "repeat" "return" | |
5067 "while") | |
5068 "*Keywords to complete when at first word of a line in behavioral scope. | |
5069 \(eg. begin, if, then, else, for, fork.) | |
5070 The procedures and variables defined within the Verilog program | |
5071 will be completed runtime and should not be added to this list.") | |
5072 | |
5073 (defvar verilog-tf-keywords | |
5074 '("begin" "break" "fork" "join" "join_any" "join_none" "case" "end" "endtask" "endfunction" "if" "else" "for" "while" "repeat") | |
5075 "*Keywords to complete when at first word of a line in a task or function. | |
5076 \(eg. begin, if, then, else, for, fork.) | |
5077 The procedures and variables defined within the Verilog program | |
5078 will be completed runtime and should not be added to this list.") | |
5079 | |
5080 (defvar verilog-case-keywords | |
5081 '("begin" "fork" "join" "join_any" "join_none" "case" "end" "endcase" "if" "else" "for" "repeat") | |
5082 "*Keywords to complete when at first word of a line in case scope. | |
5083 \(eg. begin, if, then, else, for, fork.) | |
5084 The procedures and variables defined within the Verilog program | |
5085 will be completed runtime and should not be added to this list.") | |
5086 | |
5087 (defvar verilog-separator-keywords | |
5088 '("else" "then" "begin") | |
5089 "*Keywords to complete when NOT standing at the first word of a statement. | |
5090 \(eg. else, then.) | |
5091 Variables and function names defined within the | |
5092 Verilog program are completed runtime and should not be added to this list.") | |
5093 | |
5094 (defun verilog-string-diff (str1 str2) | |
5095 "Return index of first letter where STR1 and STR2 differs." | |
5096 (catch 'done | |
5097 (let ((diff 0)) | |
5098 (while t | |
5099 (if (or (> (1+ diff) (length str1)) | |
5100 (> (1+ diff) (length str2))) | |
5101 (throw 'done diff)) | |
5102 (or (equal (aref str1 diff) (aref str2 diff)) | |
5103 (throw 'done diff)) | |
5104 (setq diff (1+ diff)))))) | |
5105 | |
5106 ;; Calculate all possible completions for functions if argument is `function', | |
5107 ;; completions for procedures if argument is `procedure' or both functions and | |
5108 ;; procedures otherwise. | |
5109 | |
5110 (defun verilog-func-completion (type) | |
5111 "Build regular expression for module/task/function names. | |
5112 TYPE is 'module, 'tf for task or function, or t if unknown." | |
5113 (if (string= verilog-str "") | |
5114 (setq verilog-str "[a-zA-Z_]")) | |
5115 (let ((verilog-str (concat (cond | |
5116 ((eq type 'module) "\\<\\(module\\)\\s +") | |
5117 ((eq type 'tf) "\\<\\(task\\|function\\)\\s +") | |
5118 (t "\\<\\(task\\|function\\|module\\)\\s +")) | |
5119 "\\<\\(" verilog-str "[a-zA-Z0-9_.]*\\)\\>")) | |
5120 match) | |
5121 | |
5122 (if (not (looking-at verilog-defun-re)) | |
5123 (verilog-re-search-backward verilog-defun-re nil t)) | |
5124 (forward-char 1) | |
5125 | |
5126 ;; Search through all reachable functions | |
5127 (goto-char (point-min)) | |
5128 (while (verilog-re-search-forward verilog-str (point-max) t) | |
5129 (progn (setq match (buffer-substring (match-beginning 2) | |
5130 (match-end 2))) | |
5131 (if (or (null verilog-pred) | |
5132 (funcall verilog-pred match)) | |
5133 (setq verilog-all (cons match verilog-all))))) | |
5134 (if (match-beginning 0) | |
5135 (goto-char (match-beginning 0))))) | |
5136 | |
5137 (defun verilog-get-completion-decl (end) | |
5138 "Macro for searching through current declaration (var, type or const) | |
5139 for matches of `str' and adding the occurrence tp `all' through point END." | |
5140 (let ((re (or (and verilog-indent-declaration-macros | |
5141 verilog-declaration-re-2-macro) | |
5142 verilog-declaration-re-2-no-macro)) | |
5143 decl-end match) | |
5144 ;; Traverse lines | |
5145 (while (and (< (point) end) | |
5146 (verilog-re-search-forward re end t)) | |
5147 ;; Traverse current line | |
5148 (setq decl-end (save-excursion (verilog-declaration-end))) | |
5149 (while (and (verilog-re-search-forward verilog-symbol-re decl-end t) | |
5150 (not (match-end 1))) | |
5151 (setq match (buffer-substring (match-beginning 0) (match-end 0))) | |
5152 (if (string-match (concat "\\<" verilog-str) match) | |
5153 (if (or (null verilog-pred) | |
5154 (funcall verilog-pred match)) | |
5155 (setq verilog-all (cons match verilog-all))))) | |
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|
5156 (forward-line 1))) |
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|
5157 verilog-all) |
79545 | 5158 |
5159 (defun verilog-type-completion () | |
5160 "Calculate all possible completions for types." | |
5161 (let ((start (point)) | |
5162 goon) | |
5163 ;; Search for all reachable type declarations | |
5164 (while (or (verilog-beg-of-defun) | |
5165 (setq goon (not goon))) | |
5166 (save-excursion | |
5167 (if (and (< start (prog1 (save-excursion (verilog-end-of-defun) | |
5168 (point)) | |
5169 (forward-char 1))) | |
5170 (verilog-re-search-forward | |
5171 "\\<type\\>\\|\\<\\(begin\\|function\\|procedure\\)\\>" | |
5172 start t) | |
5173 (not (match-end 1))) | |
5174 ;; Check current type declaration | |
5175 (verilog-get-completion-decl start)))))) | |
5176 | |
5177 (defun verilog-var-completion () | |
5178 "Calculate all possible completions for variables (or constants)." | |
5179 (let ((start (point))) | |
5180 ;; Search for all reachable var declarations | |
5181 (verilog-beg-of-defun) | |
5182 (save-excursion | |
5183 ;; Check var declarations | |
5184 (verilog-get-completion-decl start)))) | |
5185 | |
5186 (defun verilog-keyword-completion (keyword-list) | |
5187 "Give list of all possible completions of keywords in KEYWORD-LIST." | |
5188 (mapcar '(lambda (s) | |
5189 (if (string-match (concat "\\<" verilog-str) s) | |
5190 (if (or (null verilog-pred) | |
5191 (funcall verilog-pred s)) | |
5192 (setq verilog-all (cons s verilog-all))))) | |
5193 keyword-list)) | |
5194 | |
5195 | |
5196 (defun verilog-completion (verilog-str verilog-pred verilog-flag) | |
5197 "Function passed to `completing-read', `try-completion' or `all-completions'. | |
5198 Called to get completion on VERILOG-STR. If VERILOG-PRED is non-nil, it | |
5199 must be a function to be called for every match to check if this should | |
5200 really be a match. If VERILOG-FLAG is t, the function returns a list of all | |
5201 possible completions. If VERILOG-FLAG is nil it returns a string, the | |
5202 longest possible completion, or t if STR is an exact match. If VERILOG-FLAG | |
5203 is 'lambda, the function returns t if STR is an exact match, nil | |
5204 otherwise." | |
5205 (save-excursion | |
5206 (let ((verilog-all nil)) | |
5207 ;; Set buffer to use for searching labels. This should be set | |
5208 ;; within functions which use verilog-completions | |
5209 (set-buffer verilog-buffer-to-use) | |
5210 | |
5211 ;; Determine what should be completed | |
5212 (let ((state (car (verilog-calculate-indent)))) | |
5213 (cond ((eq state 'defun) | |
5214 (save-excursion (verilog-var-completion)) | |
5215 (verilog-func-completion 'module) | |
5216 (verilog-keyword-completion verilog-defun-keywords)) | |
5217 | |
5218 ((eq state 'behavioral) | |
5219 (save-excursion (verilog-var-completion)) | |
5220 (verilog-func-completion 'module) | |
5221 (verilog-keyword-completion verilog-defun-keywords)) | |
5222 | |
5223 ((eq state 'block) | |
5224 (save-excursion (verilog-var-completion)) | |
5225 (verilog-func-completion 'tf) | |
5226 (verilog-keyword-completion verilog-block-keywords)) | |
5227 | |
5228 ((eq state 'case) | |
5229 (save-excursion (verilog-var-completion)) | |
5230 (verilog-func-completion 'tf) | |
5231 (verilog-keyword-completion verilog-case-keywords)) | |
5232 | |
5233 ((eq state 'tf) | |
5234 (save-excursion (verilog-var-completion)) | |
5235 (verilog-func-completion 'tf) | |
5236 (verilog-keyword-completion verilog-tf-keywords)) | |
5237 | |
5238 ((eq state 'cpp) | |
5239 (save-excursion (verilog-var-completion)) | |
5240 (verilog-keyword-completion verilog-cpp-keywords)) | |
5241 | |
5242 ((eq state 'cparenexp) | |
5243 (save-excursion (verilog-var-completion))) | |
5244 | |
5245 (t;--Anywhere else | |
5246 (save-excursion (verilog-var-completion)) | |
5247 (verilog-func-completion 'both) | |
5248 (verilog-keyword-completion verilog-separator-keywords)))) | |
5249 | |
5250 ;; Now we have built a list of all matches. Give response to caller | |
5251 (verilog-completion-response)))) | |
5252 | |
5253 (defun verilog-completion-response () | |
5254 (cond ((or (equal verilog-flag 'lambda) (null verilog-flag)) | |
5255 ;; This was not called by all-completions | |
5256 (if (null verilog-all) | |
5257 ;; Return nil if there was no matching label | |
5258 nil | |
5259 ;; Get longest string common in the labels | |
5260 (let* ((elm (cdr verilog-all)) | |
5261 (match (car verilog-all)) | |
5262 (min (length match)) | |
5263 tmp) | |
5264 (if (string= match verilog-str) | |
5265 ;; Return t if first match was an exact match | |
5266 (setq match t) | |
5267 (while (not (null elm)) | |
5268 ;; Find longest common string | |
5269 (if (< (setq tmp (verilog-string-diff match (car elm))) min) | |
5270 (progn | |
5271 (setq min tmp) | |
5272 (setq match (substring match 0 min)))) | |
5273 ;; Terminate with match=t if this is an exact match | |
5274 (if (string= (car elm) verilog-str) | |
5275 (progn | |
5276 (setq match t) | |
5277 (setq elm nil)) | |
5278 (setq elm (cdr elm))))) | |
5279 ;; If this is a test just for exact match, return nil ot t | |
5280 (if (and (equal verilog-flag 'lambda) (not (equal match 't))) | |
5281 nil | |
5282 match)))) | |
5283 ;; If flag is t, this was called by all-completions. Return | |
5284 ;; list of all possible completions | |
5285 (verilog-flag | |
5286 verilog-all))) | |
5287 | |
5288 (defvar verilog-last-word-numb 0) | |
5289 (defvar verilog-last-word-shown nil) | |
5290 (defvar verilog-last-completions nil) | |
5291 | |
5292 (defun verilog-complete-word () | |
5293 "Complete word at current point. | |
5294 \(See also `verilog-toggle-completions', `verilog-type-keywords', | |
5295 and `verilog-separator-keywords'.)" | |
5296 (interactive) | |
5297 (let* ((b (save-excursion (skip-chars-backward "a-zA-Z0-9_") (point))) | |
5298 (e (save-excursion (skip-chars-forward "a-zA-Z0-9_") (point))) | |
5299 (verilog-str (buffer-substring b e)) | |
5300 ;; The following variable is used in verilog-completion | |
5301 (verilog-buffer-to-use (current-buffer)) | |
5302 (allcomp (if (and verilog-toggle-completions | |
5303 (string= verilog-last-word-shown verilog-str)) | |
5304 verilog-last-completions | |
5305 (all-completions verilog-str 'verilog-completion))) | |
5306 (match (if verilog-toggle-completions | |
5307 "" (try-completion | |
5308 verilog-str (mapcar '(lambda (elm) | |
5309 (cons elm 0)) allcomp))))) | |
5310 ;; Delete old string | |
5311 (delete-region b e) | |
5312 | |
5313 ;; Toggle-completions inserts whole labels | |
5314 (if verilog-toggle-completions | |
5315 (progn | |
5316 ;; Update entry number in list | |
5317 (setq verilog-last-completions allcomp | |
5318 verilog-last-word-numb | |
5319 (if (>= verilog-last-word-numb (1- (length allcomp))) | |
5320 0 | |
5321 (1+ verilog-last-word-numb))) | |
5322 (setq verilog-last-word-shown (elt allcomp verilog-last-word-numb)) | |
5323 ;; Display next match or same string if no match was found | |
5324 (if (not (null allcomp)) | |
5325 (insert "" verilog-last-word-shown) | |
5326 (insert "" verilog-str) | |
5327 (message "(No match)"))) | |
5328 ;; The other form of completion does not necessarily do that. | |
5329 | |
5330 ;; Insert match if found, or the original string if no match | |
5331 (if (or (null match) (equal match 't)) | |
5332 (progn (insert "" verilog-str) | |
5333 (message "(No match)")) | |
5334 (insert "" match)) | |
5335 ;; Give message about current status of completion | |
5336 (cond ((equal match 't) | |
5337 (if (not (null (cdr allcomp))) | |
5338 (message "(Complete but not unique)") | |
5339 (message "(Sole completion)"))) | |
5340 ;; Display buffer if the current completion didn't help | |
5341 ;; on completing the label. | |
5342 ((and (not (null (cdr allcomp))) (= (length verilog-str) | |
5343 (length match))) | |
5344 (with-output-to-temp-buffer "*Completions*" | |
5345 (display-completion-list allcomp)) | |
5346 ;; Wait for a key press. Then delete *Completion* window | |
5347 (momentary-string-display "" (point)) | |
5348 (delete-window (get-buffer-window (get-buffer "*Completions*"))) | |
5349 ))))) | |
5350 | |
5351 (defun verilog-show-completions () | |
5352 "Show all possible completions at current point." | |
5353 (interactive) | |
5354 (let* ((b (save-excursion (skip-chars-backward "a-zA-Z0-9_") (point))) | |
5355 (e (save-excursion (skip-chars-forward "a-zA-Z0-9_") (point))) | |
5356 (verilog-str (buffer-substring b e)) | |
5357 ;; The following variable is used in verilog-completion | |
5358 (verilog-buffer-to-use (current-buffer)) | |
5359 (allcomp (if (and verilog-toggle-completions | |
5360 (string= verilog-last-word-shown verilog-str)) | |
5361 verilog-last-completions | |
5362 (all-completions verilog-str 'verilog-completion)))) | |
5363 ;; Show possible completions in a temporary buffer. | |
5364 (with-output-to-temp-buffer "*Completions*" | |
5365 (display-completion-list allcomp)) | |
5366 ;; Wait for a key press. Then delete *Completion* window | |
5367 (momentary-string-display "" (point)) | |
5368 (delete-window (get-buffer-window (get-buffer "*Completions*"))))) | |
5369 | |
5370 | |
5371 (defun verilog-get-default-symbol () | |
5372 "Return symbol around current point as a string." | |
5373 (save-excursion | |
5374 (buffer-substring (progn | |
5375 (skip-chars-backward " \t") | |
5376 (skip-chars-backward "a-zA-Z0-9_") | |
5377 (point)) | |
5378 (progn | |
5379 (skip-chars-forward "a-zA-Z0-9_") | |
5380 (point))))) | |
5381 | |
5382 (defun verilog-build-defun-re (str &optional arg) | |
5383 "Return function/task/module starting with STR as regular expression. | |
5384 With optional second ARG non-nil, STR is the complete name of the instruction." | |
5385 (if arg | |
5386 (concat "^\\(function\\|task\\|module\\)[ \t]+\\(" str "\\)\\>") | |
5387 (concat "^\\(function\\|task\\|module\\)[ \t]+\\(" str "[a-zA-Z0-9_]*\\)\\>"))) | |
5388 | |
5389 (defun verilog-comp-defun (verilog-str verilog-pred verilog-flag) | |
5390 "Function passed to `completing-read', `try-completion' or `all-completions'. | |
5391 Returns a completion on any function name based on VERILOG-STR prefix. If | |
5392 VERILOG-PRED is non-nil, it must be a function to be called for every match | |
5393 to check if this should really be a match. If VERILOG-FLAG is t, the | |
5394 function returns a list of all possible completions. If it is nil it | |
5395 returns a string, the longest possible completion, or t if VERILOG-STR is | |
5396 an exact match. If VERILOG-FLAG is 'lambda, the function returns t if | |
5397 VERILOG-STR is an exact match, nil otherwise." | |
5398 (save-excursion | |
5399 (let ((verilog-all nil) | |
5400 match) | |
5401 | |
5402 ;; Set buffer to use for searching labels. This should be set | |
5403 ;; within functions which use verilog-completions | |
5404 (set-buffer verilog-buffer-to-use) | |
5405 | |
5406 (let ((verilog-str verilog-str)) | |
5407 ;; Build regular expression for functions | |
5408 (if (string= verilog-str "") | |
5409 (setq verilog-str (verilog-build-defun-re "[a-zA-Z_]")) | |
5410 (setq verilog-str (verilog-build-defun-re verilog-str))) | |
5411 (goto-char (point-min)) | |
5412 | |
5413 ;; Build a list of all possible completions | |
5414 (while (verilog-re-search-forward verilog-str nil t) | |
5415 (setq match (buffer-substring (match-beginning 2) (match-end 2))) | |
5416 (if (or (null verilog-pred) | |
5417 (funcall verilog-pred match)) | |
5418 (setq verilog-all (cons match verilog-all))))) | |
5419 | |
5420 ;; Now we have built a list of all matches. Give response to caller | |
5421 (verilog-completion-response)))) | |
5422 | |
5423 (defun verilog-goto-defun () | |
5424 "Move to specified Verilog module/task/function. | |
5425 The default is a name found in the buffer around point. | |
5426 If search fails, other files are checked based on | |
5427 `verilog-library-flags'." | |
5428 (interactive) | |
5429 (let* ((default (verilog-get-default-symbol)) | |
5430 ;; The following variable is used in verilog-comp-function | |
5431 (verilog-buffer-to-use (current-buffer)) | |
5432 (label (if (not (string= default "")) | |
5433 ;; Do completion with default | |
5434 (completing-read (concat "Label: (default " default ") ") | |
5435 'verilog-comp-defun nil nil "") | |
5436 ;; There is no default value. Complete without it | |
5437 (completing-read "Label: " | |
5438 'verilog-comp-defun nil nil ""))) | |
5439 pt) | |
5440 ;; If there was no response on prompt, use default value | |
5441 (if (string= label "") | |
5442 (setq label default)) | |
5443 ;; Goto right place in buffer if label is not an empty string | |
5444 (or (string= label "") | |
5445 (progn | |
5446 (save-excursion | |
5447 (goto-char (point-min)) | |
79691
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79555
diff
changeset
|
5448 (setq pt |
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* progmodes/verilog-mode.el (top-level): Don't require compile.
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79555
diff
changeset
|
5449 (re-search-forward (verilog-build-defun-re label t) nil t))) |
79545 | 5450 (when pt |
5451 (goto-char pt) | |
5452 (beginning-of-line)) | |
5453 pt) | |
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parents:
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diff
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|
5454 (verilog-goto-defun-file label)))) |
79545 | 5455 |
5456 ;; Eliminate compile warning | |
5457 (eval-when-compile | |
5458 (if (not (boundp 'occur-pos-list)) | |
5459 (defvar occur-pos-list nil "Backward compatibility occur positions."))) | |
5460 | |
5461 (defun verilog-showscopes () | |
5462 "List all scopes in this module." | |
5463 (interactive) | |
5464 (let ((buffer (current-buffer)) | |
5465 (linenum 1) | |
5466 (nlines 0) | |
5467 (first 1) | |
5468 (prevpos (point-min)) | |
5469 (final-context-start (make-marker)) | |
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diff
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|
5470 (regexp "\\(module\\s-+\\w+\\s-*(\\)\\|\\(\\w+\\s-+\\w+\\s-*(\\)")) |
79545 | 5471 (with-output-to-temp-buffer "*Occur*" |
5472 (save-excursion | |
5473 (message (format "Searching for %s ..." regexp)) | |
5474 ;; Find next match, but give up if prev match was at end of buffer. | |
5475 (while (and (not (= prevpos (point-max))) | |
5476 (verilog-re-search-forward regexp nil t)) | |
5477 (goto-char (match-beginning 0)) | |
5478 (beginning-of-line) | |
5479 (save-match-data | |
5480 (setq linenum (+ linenum (count-lines prevpos (point))))) | |
5481 (setq prevpos (point)) | |
5482 (goto-char (match-end 0)) | |
5483 (let* ((start (save-excursion | |
5484 (goto-char (match-beginning 0)) | |
5485 (forward-line (if (< nlines 0) nlines (- nlines))) | |
5486 (point))) | |
5487 (end (save-excursion | |
5488 (goto-char (match-end 0)) | |
5489 (if (> nlines 0) | |
5490 (forward-line (1+ nlines)) | |
5491 (forward-line 1)) | |
5492 (point))) | |
5493 (tag (format "%3d" linenum)) | |
5494 (empty (make-string (length tag) ?\ )) | |
5495 tem) | |
5496 (save-excursion | |
5497 (setq tem (make-marker)) | |
5498 (set-marker tem (point)) | |
5499 (set-buffer standard-output) | |
5500 (setq occur-pos-list (cons tem occur-pos-list)) | |
5501 (or first (zerop nlines) | |
5502 (insert "--------\n")) | |
5503 (setq first nil) | |
5504 (insert-buffer-substring buffer start end) | |
5505 (backward-char (- end start)) | |
5506 (setq tem (if (< nlines 0) (- nlines) nlines)) | |
5507 (while (> tem 0) | |
5508 (insert empty ?:) | |
5509 (forward-line 1) | |
5510 (setq tem (1- tem))) | |
5511 (let ((this-linenum linenum)) | |
5512 (set-marker final-context-start | |
5513 (+ (point) (- (match-end 0) (match-beginning 0)))) | |
5514 (while (< (point) final-context-start) | |
5515 (if (null tag) | |
5516 (setq tag (format "%3d" this-linenum))) | |
5517 (insert tag ?:))))))) | |
5518 (set-buffer-modified-p nil)))) | |
5519 | |
5520 | |
5521 ;; Highlight helper functions | |
5522 (defconst verilog-directive-regexp "\\(translate\\|coverage\\|lint\\)_") | |
5523 (defun verilog-within-translate-off () | |
5524 "Return point if within translate-off region, else nil." | |
5525 (and (save-excursion | |
5526 (re-search-backward | |
5527 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "\\(on\\|off\\)\\>") | |
5528 nil t)) | |
5529 (equal "off" (match-string 2)) | |
5530 (point))) | |
5531 | |
5532 (defun verilog-start-translate-off (limit) | |
5533 "Return point before translate-off directive if before LIMIT, else nil." | |
5534 (when (re-search-forward | |
5535 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "off\\>") | |
5536 limit t) | |
5537 (match-beginning 0))) | |
5538 | |
5539 (defun verilog-back-to-start-translate-off (limit) | |
5540 "Return point before translate-off directive if before LIMIT, else nil." | |
5541 (when (re-search-backward | |
5542 (concat "//\\s-*.*\\s-*" verilog-directive-regexp "off\\>") | |
5543 limit t) | |
5544 (match-beginning 0))) | |
5545 | |
5546 (defun verilog-end-translate-off (limit) | |
5547 "Return point after translate-on directive if before LIMIT, else nil." | |
5548 | |
5549 (re-search-forward (concat | |
5550 "//\\s-*.*\\s-*" verilog-directive-regexp "on\\>") limit t)) | |
5551 | |
5552 (defun verilog-match-translate-off (limit) | |
5553 "Match a translate-off block, setting `match-data' and returning t, else nil. | |
5554 Bound search by LIMIT." | |
5555 (when (< (point) limit) | |
5556 (let ((start (or (verilog-within-translate-off) | |
5557 (verilog-start-translate-off limit))) | |
5558 (case-fold-search t)) | |
5559 (when start | |
5560 (let ((end (or (verilog-end-translate-off limit) limit))) | |
5561 (set-match-data (list start end)) | |
5562 (goto-char end)))))) | |
5563 | |
5564 (defun verilog-font-lock-match-item (limit) | |
5565 "Match, and move over, any declaration item after point. | |
5566 Bound search by LIMIT. Adapted from | |
5567 `font-lock-match-c-style-declaration-item-and-skip-to-next'." | |
5568 (condition-case nil | |
5569 (save-restriction | |
5570 (narrow-to-region (point-min) limit) | |
5571 ;; match item | |
5572 (when (looking-at "\\s-*\\([a-zA-Z]\\w*\\)") | |
5573 (save-match-data | |
5574 (goto-char (match-end 1)) | |
5575 ;; move to next item | |
5576 (if (looking-at "\\(\\s-*,\\)") | |
5577 (goto-char (match-end 1)) | |
5578 (end-of-line) t)))) | |
5579 (error nil))) | |
5580 | |
5581 | |
5582 ;; Added by Subbu Meiyappan for Header | |
5583 | |
5584 (defun verilog-header () | |
5585 "Insert a standard Verilog file header." | |
5586 (interactive) | |
5587 (let ((start (point))) | |
5588 (insert "\ | |
5589 //----------------------------------------------------------------------------- | |
5590 // Title : <title> | |
5591 // Project : <project> | |
5592 //----------------------------------------------------------------------------- | |
5593 // File : <filename> | |
5594 // Author : <author> | |
5595 // Created : <credate> | |
5596 // Last modified : <moddate> | |
5597 //----------------------------------------------------------------------------- | |
5598 // Description : | |
5599 // <description> | |
5600 //----------------------------------------------------------------------------- | |
5601 // Copyright (c) <copydate> by <company> This model is the confidential and | |
5602 // proprietary property of <company> and the possession or use of this | |
5603 // file requires a written license from <company>. | |
5604 //------------------------------------------------------------------------------ | |
5605 // Modification history : | |
5606 // <modhist> | |
5607 //----------------------------------------------------------------------------- | |
5608 | |
5609 ") | |
5610 (goto-char start) | |
5611 (search-forward "<filename>") | |
5612 (replace-match (buffer-name) t t) | |
5613 (search-forward "<author>") (replace-match "" t t) | |
5614 (insert (user-full-name)) | |
5615 (insert " <" (user-login-name) "@" (system-name) ">") | |
5616 (search-forward "<credate>") (replace-match "" t t) | |
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parents:
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diff
changeset
|
5617 (verilog-insert-date) |
79545 | 5618 (search-forward "<moddate>") (replace-match "" t t) |
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(verilog-kill-existing-comment, verilog-insert-date)
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parents:
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diff
changeset
|
5619 (verilog-insert-date) |
79545 | 5620 (search-forward "<copydate>") (replace-match "" t t) |
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bc59ec18d036
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diff
changeset
|
5621 (verilog-insert-year) |
79545 | 5622 (search-forward "<modhist>") (replace-match "" t t) |
79554
bc59ec18d036
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diff
changeset
|
5623 (verilog-insert-date) |
79545 | 5624 (insert " : created") |
5625 (goto-char start) | |
5626 (let (string) | |
5627 (setq string (read-string "title: ")) | |
5628 (search-forward "<title>") | |
5629 (replace-match string t t) | |
5630 (setq string (read-string "project: " verilog-project)) | |
5631 (setq verilog-project string) | |
5632 (search-forward "<project>") | |
5633 (replace-match string t t) | |
5634 (setq string (read-string "Company: " verilog-company)) | |
5635 (setq verilog-company string) | |
5636 (search-forward "<company>") | |
5637 (replace-match string t t) | |
5638 (search-forward "<company>") | |
5639 (replace-match string t t) | |
5640 (search-forward "<company>") | |
5641 (replace-match string t t) | |
5642 (search-backward "<description>") | |
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diff
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|
5643 (replace-match "" t t)))) |
79545 | 5644 |
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bc59ec18d036
(verilog-kill-existing-comment, verilog-insert-date)
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parents:
79552
diff
changeset
|
5645 ;; verilog-header Uses the verilog-insert-date function |
bc59ec18d036
(verilog-kill-existing-comment, verilog-insert-date)
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parents:
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diff
changeset
|
5646 |
bc59ec18d036
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parents:
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diff
changeset
|
5647 (defun verilog-insert-date () |
79545 | 5648 "Insert date from the system." |
5649 (interactive) | |
5650 (let ((timpos)) | |
5651 (setq timpos (point)) | |
5652 (if verilog-date-scientific-format | |
5653 (shell-command "date \"+@%Y/%m/%d\"" t) | |
5654 (shell-command "date \"+@%d.%m.%Y\"" t)) | |
5655 (search-forward "@") | |
5656 (delete-region timpos (point)) | |
5657 (end-of-line)) | |
5658 (delete-char 1)) | |
5659 | |
79554
bc59ec18d036
(verilog-kill-existing-comment, verilog-insert-date)
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79552
diff
changeset
|
5660 (defun verilog-insert-year () |
79545 | 5661 "Insert year from the system." |
5662 (interactive) | |
5663 (let ((timpos)) | |
5664 (setq timpos (point)) | |
5665 (shell-command "date \"+@%Y\"" t) | |
5666 (search-forward "@") | |
5667 (delete-region timpos (point)) | |
5668 (end-of-line)) | |
5669 (delete-char 1)) | |
5670 | |
5671 | |
5672 ;; | |
5673 ;; Signal list parsing | |
5674 ;; | |
5675 | |
5676 ;; Elements of a signal list | |
5677 (defsubst verilog-sig-name (sig) | |
5678 (car sig)) | |
5679 (defsubst verilog-sig-bits (sig) | |
5680 (nth 1 sig)) | |
5681 (defsubst verilog-sig-comment (sig) | |
5682 (nth 2 sig)) | |
5683 (defsubst verilog-sig-memory (sig) | |
5684 (nth 3 sig)) | |
5685 (defsubst verilog-sig-enum (sig) | |
5686 (nth 4 sig)) | |
5687 (defsubst verilog-sig-signed (sig) | |
5688 (nth 5 sig)) | |
5689 (defsubst verilog-sig-type (sig) | |
5690 (nth 6 sig)) | |
5691 (defsubst verilog-sig-multidim (sig) | |
5692 (nth 7 sig)) | |
5693 (defsubst verilog-sig-multidim-string (sig) | |
5694 (if (verilog-sig-multidim sig) | |
5695 (let ((str "") (args (verilog-sig-multidim sig))) | |
5696 (while args | |
5697 (setq str (concat str (car args))) | |
5698 (setq args (cdr args))) | |
5699 str))) | |
5700 (defsubst verilog-sig-width (sig) | |
5701 (verilog-make-width-expression (verilog-sig-bits sig))) | |
5702 | |
5703 (defsubst verilog-alw-get-inputs (sigs) | |
5704 (nth 2 sigs)) | |
5705 (defsubst verilog-alw-get-outputs (sigs) | |
5706 (nth 0 sigs)) | |
5707 (defsubst verilog-alw-get-uses-delayed (sigs) | |
5708 (nth 3 sigs)) | |
5709 | |
5710 (defun verilog-signals-not-in (in-list not-list) | |
5711 "Return list of signals in IN-LIST that aren't also in NOT-LIST, | |
5712 and also remove any duplicates in IN-LIST. | |
5713 Signals must be in standard (base vector) form." | |
5714 (let (out-list) | |
5715 (while in-list | |
5716 (if (not (or (assoc (car (car in-list)) not-list) | |
5717 (assoc (car (car in-list)) out-list))) | |
5718 (setq out-list (cons (car in-list) out-list))) | |
5719 (setq in-list (cdr in-list))) | |
5720 (nreverse out-list))) | |
5721 ;;(verilog-signals-not-in '(("A" "") ("B" "") ("DEL" "[2:3]")) '(("DEL" "") ("EXT" ""))) | |
5722 | |
5723 (defun verilog-signals-in (in-list other-list) | |
5724 "Return list of signals in IN-LIST that are also in OTHER-LIST. | |
5725 Signals must be in standard (base vector) form." | |
5726 (let (out-list) | |
5727 (while in-list | |
5728 (if (assoc (car (car in-list)) other-list) | |
5729 (setq out-list (cons (car in-list) out-list))) | |
5730 (setq in-list (cdr in-list))) | |
5731 (nreverse out-list))) | |
5732 ;;(verilog-signals-in '(("A" "") ("B" "") ("DEL" "[2:3]")) '(("DEL" "") ("EXT" ""))) | |
5733 | |
5734 (defun verilog-signals-memory (in-list) | |
5735 "Return list of signals in IN-LIST that are memoried (multidimensional)." | |
5736 (let (out-list) | |
5737 (while in-list | |
5738 (if (nth 3 (car in-list)) | |
5739 (setq out-list (cons (car in-list) out-list))) | |
5740 (setq in-list (cdr in-list))) | |
5741 out-list)) | |
5742 ;;(verilog-signals-memory '(("A" nil nil "[3:0]")) '(("B" nil nil nil))) | |
5743 | |
5744 (defun verilog-signals-sort-compare (a b) | |
5745 "Compare signal A and B for sorting." | |
5746 (string< (car a) (car b))) | |
5747 | |
5748 (defun verilog-signals-not-params (in-list) | |
5749 "Return list of signals in IN-LIST that aren't parameters or numeric constants." | |
5750 (let (out-list) | |
5751 (while in-list | |
5752 (unless (boundp (intern (concat "vh-" (car (car in-list))))) | |
5753 (setq out-list (cons (car in-list) out-list))) | |
5754 (setq in-list (cdr in-list))) | |
5755 (nreverse out-list))) | |
5756 | |
5757 (defun verilog-signals-combine-bus (in-list) | |
5758 "Return a list of signals in IN-LIST, with busses combined. | |
5759 Duplicate signals are also removed. For example A[2] and A[1] become A[2:1]." | |
5760 (let (combo buswarn | |
5761 out-list | |
5762 sig highbit lowbit ; Temp information about current signal | |
5763 sv-name sv-highbit sv-lowbit ; Details about signal we are forming | |
5764 sv-comment sv-memory sv-enum sv-signed sv-type sv-multidim sv-busstring | |
5765 bus) | |
5766 ;; Shove signals so duplicated signals will be adjacent | |
5767 (setq in-list (sort in-list `verilog-signals-sort-compare)) | |
5768 (while in-list | |
5769 (setq sig (car in-list)) | |
5770 ;; No current signal; form from existing details | |
5771 (unless sv-name | |
5772 (setq sv-name (verilog-sig-name sig) | |
5773 sv-highbit nil | |
5774 sv-busstring nil | |
5775 sv-comment (verilog-sig-comment sig) | |
5776 sv-memory (verilog-sig-memory sig) | |
5777 sv-enum (verilog-sig-enum sig) | |
5778 sv-signed (verilog-sig-signed sig) | |
5779 sv-type (verilog-sig-type sig) | |
5780 sv-multidim (verilog-sig-multidim sig) | |
5781 combo "" | |
79799
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
5782 buswarn "")) |
79545 | 5783 ;; Extract bus details |
5784 (setq bus (verilog-sig-bits sig)) | |
5785 (cond ((and bus | |
5786 (or (and (string-match "\\[\\([0-9]+\\):\\([0-9]+\\)\\]" bus) | |
79691
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
5787 (setq highbit (string-to-number (match-string 1 bus)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
5788 lowbit (string-to-number |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
5789 (match-string 2 bus)))) |
79545 | 5790 (and (string-match "\\[\\([0-9]+\\)\\]" bus) |
79691
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
5791 (setq highbit (string-to-number (match-string 1 bus)) |
79545 | 5792 lowbit highbit)))) |
5793 ;; Combine bits in bus | |
5794 (if sv-highbit | |
5795 (setq sv-highbit (max highbit sv-highbit) | |
5796 sv-lowbit (min lowbit sv-lowbit)) | |
5797 (setq sv-highbit highbit | |
5798 sv-lowbit lowbit))) | |
5799 (bus | |
5800 ;; String, probably something like `preproc:0 | |
5801 (setq sv-busstring bus))) | |
5802 ;; Peek ahead to next signal | |
5803 (setq in-list (cdr in-list)) | |
5804 (setq sig (car in-list)) | |
5805 (cond ((and sig (equal sv-name (verilog-sig-name sig))) | |
5806 ;; Combine with this signal | |
79691
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
5807 (when (and sv-busstring |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
5808 (not (equal sv-busstring (verilog-sig-bits sig)))) |
79545 | 5809 (when nil ;; Debugging |
5810 (message (concat "Warning, can't merge into single bus " | |
5811 sv-name bus | |
5812 ", the AUTOs may be wrong"))) | |
5813 (setq buswarn ", Couldn't Merge")) | |
5814 (if (verilog-sig-comment sig) (setq combo ", ...")) | |
5815 (setq sv-memory (or sv-memory (verilog-sig-memory sig)) | |
5816 sv-enum (or sv-enum (verilog-sig-enum sig)) | |
5817 sv-signed (or sv-signed (verilog-sig-signed sig)) | |
5818 sv-type (or sv-type (verilog-sig-type sig)) | |
5819 sv-multidim (or sv-multidim (verilog-sig-multidim sig)))) | |
5820 ;; Doesn't match next signal, add to queue, zero in prep for next | |
5821 ;; Note sig may also be nil for the last signal in the list | |
5822 (t | |
5823 (setq out-list | |
79691
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
5824 (cons |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
5825 (list sv-name |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
5826 (or sv-busstring |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
5827 (if sv-highbit |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
5828 (concat "[" (int-to-string sv-highbit) ":" |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79555
diff
changeset
|
5829 (int-to-string sv-lowbit) "]"))) |
79799
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
5830 (concat sv-comment combo buswarn) |
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
5831 sv-memory sv-enum sv-signed sv-type sv-multidim) |
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
5832 out-list) |
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
5833 sv-name nil)))) |
79545 | 5834 ;; |
5835 out-list)) | |
5836 | |
5837 (defun verilog-sig-tieoff (sig &optional no-width) | |
79799
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
5838 "Return tieoff expression for given SIG, with appropriate width. |
79545 | 5839 Ignore width if optional NO-WIDTH is set." |
5840 (let* ((width (if no-width nil (verilog-sig-width sig)))) | |
5841 (concat | |
5842 (if (and verilog-active-low-regexp | |
5843 (string-match verilog-active-low-regexp (verilog-sig-name sig))) | |
5844 "~" "") | |
5845 (cond ((not width) | |
5846 "0") | |
5847 ((string-match "^[0-9]+$" width) | |
5848 (concat width (if (verilog-sig-signed sig) "'sh0" "'h0"))) | |
5849 (t | |
5850 (concat "{" width "{1'b0}}")))))) | |
5851 | |
5852 ;; | |
5853 ;; Port/Wire/Etc Reading | |
5854 ;; | |
5855 | |
5856 (defun verilog-read-inst-backward-name () | |
5857 "Internal. Move point back to beginning of inst-name." | |
5858 (verilog-backward-open-paren) | |
5859 (let (done) | |
5860 (while (not done) | |
5861 (verilog-re-search-backward-quick "\\()\\|\\b[a-zA-Z0-9`_\$]\\|\\]\\)" nil nil) ; ] isn't word boundary | |
5862 (cond ((looking-at ")") | |
5863 (verilog-backward-open-paren)) | |
5864 (t (setq done t))))) | |
5865 (while (looking-at "\\]") | |
5866 (verilog-backward-open-bracket) | |
5867 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|\\]\\)" nil nil)) | |
5868 (skip-chars-backward "a-zA-Z0-9`_$")) | |
5869 | |
5870 (defun verilog-read-inst-module () | |
5871 "Return module_name when point is inside instantiation." | |
5872 (save-excursion | |
5873 (verilog-read-inst-backward-name) | |
5874 ;; Skip over instantiation name | |
5875 (verilog-re-search-backward-quick "\\(\\b[a-zA-Z0-9`_\$]\\|)\\)" nil nil) ; ) isn't word boundary | |
5876 ;; Check for parameterized instantiations | |
5877 (when (looking-at ")") | |
5878 (verilog-backward-open-paren) | |
5879 (verilog-re-search-backward-quick "\\b[a-zA-Z0-9`_\$]" nil nil)) | |
5880 (skip-chars-backward "a-zA-Z0-9'_$") | |
5881 (looking-at "[a-zA-Z0-9`_\$]+") | |
5882 ;; Important: don't use match string, this must work with emacs 19 font-lock on | |
5883 (buffer-substring-no-properties (match-beginning 0) (match-end 0)))) | |
5884 | |
5885 (defun verilog-read-inst-name () | |
5886 "Return instance_name when point is inside instantiation." | |
5887 (save-excursion | |
5888 (verilog-read-inst-backward-name) | |
5889 (looking-at "[a-zA-Z0-9`_\$]+") | |
5890 ;; Important: don't use match string, this must work with emacs 19 font-lock on | |
5891 (buffer-substring-no-properties (match-beginning 0) (match-end 0)))) | |
5892 | |
5893 (defun verilog-read-module-name () | |
5894 "Return module name when after its ( or ;." | |
5895 (save-excursion | |
5896 (re-search-backward "[(;]") | |
5897 (verilog-re-search-backward-quick "\\b[a-zA-Z0-9`_\$]" nil nil) | |
5898 (skip-chars-backward "a-zA-Z0-9`_$") | |
5899 (looking-at "[a-zA-Z0-9`_\$]+") | |
5900 ;; Important: don't use match string, this must work with emacs 19 font-lock on | |
5901 (buffer-substring-no-properties (match-beginning 0) (match-end 0)))) | |
5902 | |
5903 (defun verilog-read-auto-params (num-param &optional max-param) | |
5904 "Return parameter list inside auto. | |
5905 Optional NUM-PARAM and MAX-PARAM check for a specific number of parameters." | |
5906 (let ((olist)) | |
5907 (save-excursion | |
5908 ;; /*AUTOPUNT("parameter", "parameter")*/ | |
5909 (search-backward "(") | |
5910 (while (looking-at "(?\\s *\"\\([^\"]*\\)\"\\s *,?") | |
5911 (setq olist (cons (match-string 1) olist)) | |
5912 (goto-char (match-end 0)))) | |
5913 (or (eq nil num-param) | |
5914 (<= num-param (length olist)) | |
5915 (error "%s: Expected %d parameters" (verilog-point-text) num-param)) | |
5916 (if (eq max-param nil) (setq max-param num-param)) | |
5917 (or (eq nil max-param) | |
5918 (>= max-param (length olist)) | |
5919 (error "%s: Expected <= %d parameters" (verilog-point-text) max-param)) | |
5920 (nreverse olist))) | |
5921 | |
5922 (defun verilog-read-decls () | |
5923 "Compute signal declaration information for the current module at point. | |
5924 Return a array of [outputs inouts inputs wire reg assign const]." | |
5925 (let ((end-mod-point (or (verilog-get-end-of-defun t) (point-max))) | |
5926 (functask 0) (paren 0) (sig-paren 0) | |
5927 sigs-in sigs-out sigs-inout sigs-wire sigs-reg sigs-assign sigs-const sigs-gparam | |
5928 vec expect-signal keywd newsig rvalue enum io signed typedefed multidim) | |
5929 (save-excursion | |
5930 (verilog-beg-of-defun) | |
5931 (setq sigs-const (verilog-read-auto-constants (point) end-mod-point)) | |
5932 (while (< (point) end-mod-point) | |
5933 ;;(if dbg (setq dbg (cons (format "Pt %s Vec %s Kwd'%s'\n" (point) vec keywd) dbg))) | |
5934 (cond | |
5935 ((looking-at "//") | |
5936 (if (looking-at "[^\n]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)") | |
5937 (setq enum (match-string 1))) | |
5938 (search-forward "\n")) | |
5939 ((looking-at "/\\*") | |
5940 (forward-char 2) | |
5941 (if (looking-at "[^*]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)") | |
5942 (setq enum (match-string 1))) | |
5943 (or (search-forward "*/") | |
5944 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point)))) | |
5945 ((looking-at "(\\*") | |
5946 (forward-char 2) | |
5947 (or (looking-at "\\s-*)") ; It's a "always @ (*)" | |
5948 (search-forward "*)") | |
5949 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point)))) | |
5950 ((eq ?\" (following-char)) | |
5951 (or (re-search-forward "[^\\]\"" nil t) ;; don't forward-char first, since we look for a non backslash first | |
5952 (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point)))) | |
5953 ((eq ?\; (following-char)) | |
5954 (setq vec nil io nil expect-signal nil newsig nil paren 0 rvalue nil) | |
5955 (forward-char 1)) | |
5956 ((eq ?= (following-char)) | |
5957 (setq rvalue t newsig nil) | |
5958 (forward-char 1)) | |
5959 ((and (or rvalue sig-paren) | |
5960 (cond ((and (eq ?, (following-char)) | |
5961 (eq paren sig-paren)) | |
5962 (setq rvalue nil) | |
5963 (forward-char 1) | |
5964 t) | |
5965 ;; ,'s can occur inside {} & funcs | |
5966 ((looking-at "[{(]") | |
5967 (setq paren (1+ paren)) | |
5968 (forward-char 1) | |
5969 t) | |
5970 ((looking-at "[})]") | |
5971 (setq paren (1- paren)) | |
5972 (forward-char 1) | |
5973 (when (< paren sig-paren) | |
5974 (setq expect-signal nil)) ; ) that ends variables inside v2k arg list | |
79799
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
5975 t)))) |
79545 | 5976 ((looking-at "\\s-*\\(\\[[^]]+\\]\\)") |
5977 (goto-char (match-end 0)) | |
5978 (cond (newsig ; Memory, not just width. Patch last signal added's memory (nth 3) | |
5979 (setcar (cdr (cdr (cdr newsig))) (match-string 1))) | |
5980 (vec ;; Multidimensional | |
5981 (setq multidim (cons vec multidim)) | |
5982 (setq vec (verilog-string-replace-matches | |
5983 "\\s-+" "" nil nil (match-string 1)))) | |
5984 (t ;; Bit width | |
5985 (setq vec (verilog-string-replace-matches | |
5986 "\\s-+" "" nil nil (match-string 1)))))) | |
5987 ;; Normal or escaped identifier -- note we remember the \ if escaped | |
5988 ((looking-at "\\s-*\\([a-zA-Z0-9`_$]+\\|\\\\[^ \t\n\f]+\\)") | |
5989 (goto-char (match-end 0)) | |
5990 (setq keywd (match-string 1)) | |
5991 (when (string-match "^\\\\" keywd) | |
5992 (setq keywd (concat keywd " "))) ;; Escaped ID needs space at end | |
5993 (cond ((equal keywd "input") | |
5994 (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed nil multidim nil sig-paren paren | |
5995 expect-signal 'sigs-in io t)) | |
5996 ((equal keywd "output") | |
5997 (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed nil multidim nil sig-paren paren | |
5998 expect-signal 'sigs-out io t)) | |
5999 ((equal keywd "inout") | |
6000 (setq vec nil enum nil rvalue nil newsig nil signed nil typedefed nil multidim nil sig-paren paren | |
6001 expect-signal 'sigs-inout io t)) | |
6002 ((or (equal keywd "wire") | |
6003 (equal keywd "tri") | |
6004 (equal keywd "tri0") | |
6005 (equal keywd "tri1")) | |
6006 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren | |
6007 expect-signal 'sigs-wire))) | |
6008 ((or (equal keywd "reg") | |
6009 (equal keywd "trireg")) | |
6010 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren | |
6011 expect-signal 'sigs-reg))) | |
6012 ((equal keywd "assign") | |
6013 (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren | |
6014 expect-signal 'sigs-assign)) | |
6015 ((or (equal keywd "supply0") | |
6016 (equal keywd "supply1") | |
6017 (equal keywd "supply") | |
6018 (equal keywd "localparam")) | |
6019 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren | |
6020 expect-signal 'sigs-const))) | |
6021 ((or (equal keywd "parameter")) | |
6022 (unless io (setq vec nil enum nil rvalue nil signed nil typedefed nil multidim nil sig-paren paren | |
6023 expect-signal 'sigs-gparam))) | |
6024 ((equal keywd "signed") | |
6025 (setq signed "signed")) | |
6026 ((or (equal keywd "function") | |
6027 (equal keywd "task")) | |
6028 (setq functask (1+ functask))) | |
6029 ((or (equal keywd "endfunction") | |
6030 (equal keywd "endtask")) | |
6031 (setq functask (1- functask))) | |
6032 ((or (equal keywd "`ifdef") | |
6033 (equal keywd "`ifndef")) | |
6034 (setq rvalue t)) | |
6035 ((verilog-typedef-name-p keywd) | |
6036 (setq typedefed keywd)) | |
6037 ((and expect-signal | |
6038 (eq functask 0) | |
6039 (not rvalue) | |
6040 (eq paren sig-paren) | |
6041 (not (member keywd verilog-keywords))) | |
6042 ;; Add new signal to expect-signal's variable | |
6043 (setq newsig (list keywd vec nil nil enum signed typedefed multidim)) | |
6044 (set expect-signal (cons newsig | |
6045 (symbol-value expect-signal)))))) | |
6046 (t | |
6047 (forward-char 1))) | |
6048 (skip-syntax-forward " ")) | |
6049 ;; Return arguments | |
6050 (vector (nreverse sigs-out) | |
6051 (nreverse sigs-inout) | |
6052 (nreverse sigs-in) | |
6053 (nreverse sigs-wire) | |
6054 (nreverse sigs-reg) | |
6055 (nreverse sigs-assign) | |
6056 (nreverse sigs-const) | |
79799
57956dd69d3f
(top-level): Fix spacing.
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parents:
79717
diff
changeset
|
6057 (nreverse sigs-gparam))))) |
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(top-level): Fix spacing.
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79717
diff
changeset
|
6058 |
57956dd69d3f
(top-level): Fix spacing.
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parents:
79717
diff
changeset
|
6059 (eval-when-compile |
57956dd69d3f
(top-level): Fix spacing.
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parents:
79717
diff
changeset
|
6060 ;; Prevent compile warnings; these are let's, not globals |
57956dd69d3f
(top-level): Fix spacing.
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parents:
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diff
changeset
|
6061 ;; Do not remove the eval-when-compile |
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(top-level): Fix spacing.
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parents:
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diff
changeset
|
6062 ;; - we want a error when we are debugging this code if they are refed. |
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(top-level): Fix spacing.
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parents:
79717
diff
changeset
|
6063 (defvar sigs-in) |
57956dd69d3f
(top-level): Fix spacing.
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parents:
79717
diff
changeset
|
6064 (defvar sigs-inout) |
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(top-level): Fix spacing.
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parents:
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diff
changeset
|
6065 (defvar sigs-out)) |
79691
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* progmodes/verilog-mode.el (top-level): Don't require compile.
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79555
diff
changeset
|
6066 |
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* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
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diff
changeset
|
6067 |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
6068 (defsubst verilog-modi-get-decls (modi) |
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* progmodes/verilog-mode.el (top-level): Don't require compile.
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diff
changeset
|
6069 (verilog-modi-cache-results modi 'verilog-read-decls)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
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diff
changeset
|
6070 |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
6071 (defsubst verilog-modi-get-sub-decls (modi) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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diff
changeset
|
6072 (verilog-modi-cache-results modi 'verilog-read-sub-decls)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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79555
diff
changeset
|
6073 |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
6074 |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
6075 ;; Signal reading for given module |
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* progmodes/verilog-mode.el (top-level): Don't require compile.
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diff
changeset
|
6076 ;; Note these all take modi's - as returned from the |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
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diff
changeset
|
6077 ;; verilog-modi-current function. |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
6078 (defsubst verilog-modi-get-outputs (modi) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
6079 (aref (verilog-modi-get-decls modi) 0)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
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diff
changeset
|
6080 (defsubst verilog-modi-get-inouts (modi) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
6081 (aref (verilog-modi-get-decls modi) 1)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
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diff
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|
6082 (defsubst verilog-modi-get-inputs (modi) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
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diff
changeset
|
6083 (aref (verilog-modi-get-decls modi) 2)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
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diff
changeset
|
6084 (defsubst verilog-modi-get-wires (modi) |
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* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
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changeset
|
6085 (aref (verilog-modi-get-decls modi) 3)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
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diff
changeset
|
6086 (defsubst verilog-modi-get-regs (modi) |
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* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
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changeset
|
6087 (aref (verilog-modi-get-decls modi) 4)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
6088 (defsubst verilog-modi-get-assigns (modi) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
6089 (aref (verilog-modi-get-decls modi) 5)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
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diff
changeset
|
6090 (defsubst verilog-modi-get-consts (modi) |
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* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
6091 (aref (verilog-modi-get-decls modi) 6)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
6092 (defsubst verilog-modi-get-gparams (modi) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
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changeset
|
6093 (aref (verilog-modi-get-decls modi) 7)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
6094 (defsubst verilog-modi-get-sub-outputs (modi) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
6095 (aref (verilog-modi-get-sub-decls modi) 0)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
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diff
changeset
|
6096 (defsubst verilog-modi-get-sub-inouts (modi) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
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diff
changeset
|
6097 (aref (verilog-modi-get-sub-decls modi) 1)) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
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diff
changeset
|
6098 (defsubst verilog-modi-get-sub-inputs (modi) |
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
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diff
changeset
|
6099 (aref (verilog-modi-get-sub-decls modi) 2)) |
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* progmodes/verilog-mode.el (top-level): Don't require compile.
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diff
changeset
|
6100 |
79545 | 6101 |
6102 (defun verilog-read-sub-decls-sig (submodi comment port sig vec multidim) | |
6103 "For verilog-read-sub-decls-line, add a signal." | |
6104 (let (portdata) | |
6105 (when sig | |
6106 (setq port (verilog-symbol-detick-denumber port)) | |
6107 (setq sig (verilog-symbol-detick-denumber sig)) | |
6108 (if sig (setq sig (verilog-string-replace-matches "^[---+~!|&]+" "" nil nil sig))) | |
6109 (if vec (setq vec (verilog-symbol-detick-denumber vec))) | |
6110 (if multidim (setq multidim (mapcar `verilog-symbol-detick-denumber multidim))) | |
6111 (unless (or (not sig) | |
6112 (equal sig "")) ;; Ignore .foo(1'b1) assignments | |
6113 (cond ((setq portdata (assoc port (verilog-modi-get-inouts submodi))) | |
6114 (setq sigs-inout (cons (list sig vec (concat "To/From " comment) nil nil | |
6115 (verilog-sig-signed portdata) | |
6116 (verilog-sig-type portdata) | |
6117 multidim) | |
6118 sigs-inout))) | |
6119 ((setq portdata (assoc port (verilog-modi-get-outputs submodi))) | |
6120 (setq sigs-out (cons (list sig vec (concat "From " comment) nil nil | |
6121 (verilog-sig-signed portdata) | |
6122 (verilog-sig-type portdata) | |
6123 multidim) | |
6124 sigs-out))) | |
6125 ((setq portdata (assoc port (verilog-modi-get-inputs submodi))) | |
6126 (setq sigs-in (cons (list sig vec (concat "To " comment) nil nil | |
6127 (verilog-sig-signed portdata) | |
6128 (verilog-sig-type portdata) | |
6129 multidim) | |
6130 sigs-in))) | |
6131 ;; (t -- warning pin isn't defined.) ; Leave for lint tool | |
6132 ))))) | |
6133 | |
6134 (defun verilog-read-sub-decls-line (submodi comment) | |
6135 "For read-sub-decls, read lines of port defs until none match anymore. | |
6136 Return the list of signals found, using submodi to look up each port." | |
6137 (let (done port sig vec multidim) | |
6138 (save-excursion | |
6139 (forward-line 1) | |
6140 (while (not done) | |
6141 ;; Get port name | |
6142 (cond ((looking-at "\\s-*\\.\\s-*\\([a-zA-Z0-9`_$]*\\)\\s-*(\\s-*") | |
6143 (setq port (match-string 1)) | |
6144 (goto-char (match-end 0))) | |
6145 ((looking-at "\\s-*\\.\\s-*\\(\\\\[^ \t\n\f]*\\)\\s-*(\\s-*") | |
6146 (setq port (concat (match-string 1) " ")) ;; escaped id's need trailing space | |
6147 (goto-char (match-end 0))) | |
6148 ((looking-at "\\s-*\\.[^(]*(") | |
6149 (setq port nil) ;; skip this line | |
6150 (goto-char (match-end 0))) | |
6151 (t | |
6152 (setq port nil done t))) ;; Unknown, ignore rest of line | |
6153 ;; Get signal name | |
6154 (when port | |
6155 (setq multidim nil) | |
6156 (cond ((looking-at "\\(\\\\[^ \t\n\f]*\\)\\s-*)") | |
6157 (setq sig (concat (match-string 1) " ") ;; escaped id's need trailing space | |
6158 vec nil)) | |
6159 ; We intentionally ignore (non-escaped) signals with .s in them | |
6160 ; this prevents AUTOWIRE etc from noticing hierarchical sigs. | |
6161 ((looking-at "\\([^[({).]*\\)\\s-*)") | |
6162 (setq sig (verilog-string-remove-spaces (match-string 1)) | |
6163 vec nil)) | |
6164 ((looking-at "\\([^[({).]*\\)\\s-*\\(\\[[^]]+\\]\\)\\s-*)") | |
6165 (setq sig (verilog-string-remove-spaces (match-string 1)) | |
6166 vec (match-string 2))) | |
6167 ((looking-at "\\([^[({).]*\\)\\s-*/\\*\\(\\[[^*]+\\]\\)\\*/\\s-*)") | |
6168 (setq sig (verilog-string-remove-spaces (match-string 1)) | |
6169 vec nil) | |
6170 (let ((parse (match-string 2))) | |
6171 (while (string-match "^\\(\\[[^]]+\\]\\)\\(.*\\)$" parse) | |
6172 (when vec (setq multidim (cons vec multidim))) | |
6173 (setq vec (match-string 1 parse)) | |
6174 (setq parse (match-string 2 parse))))) | |
6175 ((looking-at "{\\(.*\\)}.*\\s-*)") | |
6176 (let ((mlst (split-string (match-string 1) ",")) | |
6177 mstr) | |
6178 (while (setq mstr (pop mlst)) | |
6179 ;;(unless noninteractive (message "sig: %s " mstr)) | |
6180 (cond | |
6181 ((string-match "\\(['`a-zA-Z0-9_$]+\\)\\s-*$" mstr) | |
6182 (setq sig (verilog-string-remove-spaces (match-string 1 mstr)) | |
6183 vec nil) | |
6184 ;;(unless noninteractive (message "concat sig1: %s %s" mstr (match-string 1 mstr))) | |
6185 ) | |
6186 ((string-match "\\([^[({).]+\\)\\s-*\\(\\[[^]]+\\]\\)\\s-*" mstr) | |
6187 (setq sig (verilog-string-remove-spaces (match-string 1 mstr)) | |
6188 vec (match-string 2 mstr)) | |
6189 ;;(unless noninteractive (message "concat sig2: '%s' '%s' '%s'" mstr (match-string 1 mstr) (match-string 2 mstr))) | |
6190 ) | |
6191 (t | |
6192 (setq sig nil))) | |
6193 ;; Process signals | |
6194 (verilog-read-sub-decls-sig submodi comment port sig vec multidim)))) | |
6195 (t | |
6196 (setq sig nil))) | |
6197 ;; Process signals | |
6198 (verilog-read-sub-decls-sig submodi comment port sig vec multidim)) | |
6199 ;; | |
6200 (forward-line 1))))) | |
6201 | |
6202 (defun verilog-read-sub-decls () | |
6203 "Internally parse signals going to modules under this module. | |
6204 Return a array of [ outputs inouts inputs ] signals for modules that are | |
6205 instantiated in this module. For example if declare A A (.B(SIG)) and SIG | |
6206 is a output, then SIG will be included in the list. | |
6207 | |
6208 This only works on instantiations created with /*AUTOINST*/ converted by | |
6209 \\[verilog-auto-inst]. Otherwise, it would have to read in the whole | |
6210 component library to determine connectivity of the design. | |
6211 | |
6212 One work around for this problem is to manually create // Inputs and // | |
6213 Outputs comments above subcell signals, for example: | |
6214 | |
6215 module1 instance1x ( | |
6216 // Outputs | |
6217 .out (out), | |
6218 // Inputs | |
6219 .in (in));" | |
6220 (save-excursion | |
6221 (let ((end-mod-point (verilog-get-end-of-defun t)) | |
6222 st-point end-inst-point | |
6223 ;; below 3 modified by verilog-read-sub-decls-line | |
6224 sigs-out sigs-inout sigs-in) | |
6225 (verilog-beg-of-defun) | |
6226 (while (re-search-forward "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-mod-point t) | |
6227 (save-excursion | |
6228 (goto-char (match-beginning 0)) | |
6229 (unless (verilog-inside-comment-p) | |
6230 ;; Attempt to snarf a comment | |
6231 (let* ((submod (verilog-read-inst-module)) | |
6232 (inst (verilog-read-inst-name)) | |
6233 (comment (concat inst " of " submod ".v")) submodi) | |
6234 (when (setq submodi (verilog-modi-lookup submod t)) | |
6235 ;; This could have used a list created by verilog-auto-inst | |
6236 ;; However I want it to be runnable even on user's manually added signals | |
6237 (verilog-backward-open-paren) | |
6238 (setq end-inst-point (save-excursion (forward-sexp 1) (point)) | |
6239 st-point (point)) | |
6240 (while (re-search-forward "\\s *(?\\s *// Outputs" end-inst-point t) | |
6241 (verilog-read-sub-decls-line submodi comment)) ;; Modifies sigs-out | |
6242 (goto-char st-point) | |
6243 (while (re-search-forward "\\s *// Inouts" end-inst-point t) | |
6244 (verilog-read-sub-decls-line submodi comment)) ;; Modifies sigs-inout | |
6245 (goto-char st-point) | |
6246 (while (re-search-forward "\\s *// Inputs" end-inst-point t) | |
6247 (verilog-read-sub-decls-line submodi comment)) ;; Modifies sigs-in | |
6248 ))))) | |
6249 ;; Combine duplicate bits | |
6250 ;;(setq rr (vector sigs-out sigs-inout sigs-in)) | |
6251 (vector (verilog-signals-combine-bus (nreverse sigs-out)) | |
6252 (verilog-signals-combine-bus (nreverse sigs-inout)) | |
6253 (verilog-signals-combine-bus (nreverse sigs-in)))))) | |
6254 | |
6255 (defun verilog-read-inst-pins () | |
6256 "Return a array of [ pins ] for the current instantiation at point. | |
6257 For example if declare A A (.B(SIG)) then B will be included in the list." | |
6258 (save-excursion | |
6259 (let ((end-mod-point (point)) ;; presume at /*AUTOINST*/ point | |
6260 pins pin) | |
6261 (verilog-backward-open-paren) | |
6262 (while (re-search-forward "\\.\\([^(,) \t\n\f]*\\)\\s-*" end-mod-point t) | |
6263 (setq pin (match-string 1)) | |
6264 (unless (verilog-inside-comment-p) | |
6265 (setq pins (cons (list pin) pins)) | |
6266 (when (looking-at "(") | |
6267 (forward-sexp 1)))) | |
6268 (vector pins)))) | |
6269 | |
6270 (defun verilog-read-arg-pins () | |
6271 "Return a array of [ pins ] for the current argument declaration at point." | |
6272 (save-excursion | |
6273 (let ((end-mod-point (point)) ;; presume at /*AUTOARG*/ point | |
6274 pins pin) | |
6275 (verilog-backward-open-paren) | |
6276 (while (re-search-forward "\\([a-zA-Z0-9$_.%`]+\\)" end-mod-point t) | |
6277 (setq pin (match-string 1)) | |
6278 (unless (verilog-inside-comment-p) | |
6279 (setq pins (cons (list pin) pins)))) | |
6280 (vector pins)))) | |
6281 | |
6282 (defun verilog-read-auto-constants (beg end-mod-point) | |
6283 "Return a list of AUTO_CONSTANTs used in the region from BEG to END-MOD-POINT." | |
6284 ;; Insert new | |
6285 (save-excursion | |
6286 (let (sig-list tpl-end-pt) | |
6287 (goto-char beg) | |
6288 (while (re-search-forward "\\<AUTO_CONSTANT" end-mod-point t) | |
6289 (if (not (looking-at "\\s *(")) | |
6290 (error "%s: Missing () after AUTO_CONSTANT" (verilog-point-text))) | |
6291 (search-forward "(" end-mod-point) | |
6292 (setq tpl-end-pt (save-excursion | |
6293 (backward-char 1) | |
6294 (forward-sexp 1) ;; Moves to paren that closes argdecl's | |
6295 (backward-char 1) | |
6296 (point))) | |
6297 (while (re-search-forward "\\s-*\\([\"a-zA-Z0-9$_.%`]+\\)\\s-*,*" tpl-end-pt t) | |
6298 (setq sig-list (cons (list (match-string 1) nil nil) sig-list)))) | |
6299 sig-list))) | |
6300 | |
6301 (defun verilog-read-auto-lisp (start end) | |
6302 "Look for and evaluate a AUTO_LISP between START and END." | |
6303 (save-excursion | |
6304 (goto-char start) | |
6305 (while (re-search-forward "\\<AUTO_LISP(" end t) | |
6306 (backward-char) | |
6307 (let* ((beg-pt (prog1 (point) | |
6308 (forward-sexp 1))) ;; Closing paren | |
6309 (end-pt (point))) | |
6310 (eval-region beg-pt end-pt nil))))) | |
6311 | |
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6312 (eval-when-compile |
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|
6313 ;; Prevent compile warnings; these are let's, not globals |
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|
6314 ;; Do not remove the eval-when-compile |
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|
6315 ;; - we want a error when we are debugging this code if they are refed. |
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|
6316 (defvar sigs-in) |
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|
6317 (defvar sigs-out) |
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|
6318 (defvar got-sig) |
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|
6319 (defvar got-rvalue) |
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6320 (defvar uses-delayed) |
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6321 (defvar vector-skip-list)) |
79545 | 6322 |
6323 (defun verilog-read-always-signals-recurse | |
6324 (exit-keywd rvalue ignore-next) | |
6325 "Recursive routine for parentheses/bracket matching. | |
6326 EXIT-KEYWD is expression to stop at, nil if top level. | |
6327 RVALUE is true if at right hand side of equal. | |
6328 IGNORE-NEXT is true to ignore next token, fake from inside case statement." | |
6329 (let* ((semi-rvalue (equal "endcase" exit-keywd)) ;; true if after a ; we are looking for rvalue | |
6330 keywd last-keywd sig-tolk sig-last-tolk gotend got-sig got-rvalue end-else-check) | |
6331 ;;(if dbg (setq dbg (concat dbg (format "Recursion %S %S %S\n" exit-keywd rvalue ignore-next)))) | |
6332 (while (not (or (eobp) gotend)) | |
6333 (cond | |
6334 ((looking-at "//") | |
6335 (search-forward "\n")) | |
6336 ((looking-at "/\\*") | |
6337 (or (search-forward "*/") | |
6338 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point)))) | |
6339 ((looking-at "(\\*") | |
6340 (or (looking-at "(\\*\\s-*)") ; It's a "always @ (*)" | |
6341 (search-forward "*)") | |
6342 (error "%s: Unmatched (* *), at char %d" (verilog-point-text) (point)))) | |
6343 (t (setq keywd (buffer-substring-no-properties | |
6344 (point) | |
6345 (save-excursion (when (eq 0 (skip-chars-forward "a-zA-Z0-9$_.%`")) | |
6346 (forward-char 1)) | |
6347 (point))) | |
6348 sig-last-tolk sig-tolk | |
6349 sig-tolk nil) | |
6350 ;;(if dbg (setq dbg (concat dbg (format "\tPt=%S %S\trv=%S in=%S ee=%S\n" (point) keywd rvalue ignore-next end-else-check)))) | |
6351 (cond | |
6352 ((equal keywd "\"") | |
6353 (or (re-search-forward "[^\\]\"" nil t) | |
6354 (error "%s: Unmatched quotes, at char %d" (verilog-point-text) (point)))) | |
6355 ;; else at top level loop, keep parsing | |
6356 ((and end-else-check (equal keywd "else")) | |
6357 ;;(if dbg (setq dbg (concat dbg (format "\tif-check-else %s\n" keywd)))) | |
6358 ;; no forward movement, want to see else in lower loop | |
6359 (setq end-else-check nil)) | |
6360 ;; End at top level loop | |
6361 ((and end-else-check (looking-at "[^ \t\n\f]")) | |
6362 ;;(if dbg (setq dbg (concat dbg (format "\tif-check-else-other %s\n" keywd)))) | |
6363 (setq gotend t)) | |
6364 ;; Final statement? | |
6365 ((and exit-keywd (equal keywd exit-keywd)) | |
6366 (setq gotend t) | |
6367 (forward-char (length keywd))) | |
6368 ;; Standard tokens... | |
6369 ((equal keywd ";") | |
6370 (setq ignore-next nil rvalue semi-rvalue) | |
6371 ;; Final statement at top level loop? | |
6372 (when (not exit-keywd) | |
6373 ;;(if dbg (setq dbg (concat dbg (format "\ttop-end-check %s\n" keywd)))) | |
6374 (setq end-else-check t)) | |
6375 (forward-char 1)) | |
6376 ((equal keywd "'") | |
6377 (if (looking-at "'s?[hdxbo][0-9a-fA-F_xz? \t]*") | |
6378 (goto-char (match-end 0)) | |
6379 (forward-char 1))) | |
6380 ((equal keywd ":") ;; Case statement, begin/end label, x?y:z | |
6381 (cond ((equal "endcase" exit-keywd) ;; case x: y=z; statement next | |
6382 (setq ignore-next nil rvalue nil)) | |
6383 ((equal "?" exit-keywd) ;; x?y:z rvalue | |
6384 ) ;; NOP | |
6385 (got-sig ;; label: statement | |
6386 (setq ignore-next nil rvalue semi-rvalue got-sig nil)) | |
6387 ((not rvalue) ;; begin label | |
6388 (setq ignore-next t rvalue nil))) | |
6389 (forward-char 1)) | |
6390 ((equal keywd "=") | |
6391 (if (eq (char-before) ?< ) | |
6392 (setq uses-delayed 1)) | |
6393 (setq ignore-next nil rvalue t) | |
6394 (forward-char 1)) | |
6395 ((equal keywd "?") | |
6396 (forward-char 1) | |
6397 (verilog-read-always-signals-recurse ":" rvalue nil)) | |
6398 ((equal keywd "[") | |
6399 (forward-char 1) | |
6400 (verilog-read-always-signals-recurse "]" t nil)) | |
6401 ((equal keywd "(") | |
6402 (forward-char 1) | |
6403 (cond (sig-last-tolk ;; Function call; zap last signal | |
6404 (setq got-sig nil))) | |
6405 (cond ((equal last-keywd "for") | |
6406 (verilog-read-always-signals-recurse ";" nil nil) | |
6407 (verilog-read-always-signals-recurse ";" t nil) | |
6408 (verilog-read-always-signals-recurse ")" nil nil)) | |
6409 (t (verilog-read-always-signals-recurse ")" t nil)))) | |
6410 ((equal keywd "begin") | |
6411 (skip-syntax-forward "w_") | |
6412 (verilog-read-always-signals-recurse "end" nil nil) | |
6413 ;;(if dbg (setq dbg (concat dbg (format "\tgot-end %s\n" exit-keywd)))) | |
6414 (setq ignore-next nil rvalue semi-rvalue) | |
6415 (if (not exit-keywd) (setq end-else-check t))) | |
6416 ((or (equal keywd "case") | |
6417 (equal keywd "casex") | |
6418 (equal keywd "casez")) | |
6419 (skip-syntax-forward "w_") | |
6420 (verilog-read-always-signals-recurse "endcase" t nil) | |
6421 (setq ignore-next nil rvalue semi-rvalue) | |
6422 (if (not exit-keywd) (setq gotend t))) ;; top level begin/end | |
6423 ((string-match "^[$`a-zA-Z_]" keywd) ;; not exactly word constituent | |
6424 (cond ((or (equal keywd "`ifdef") | |
6425 (equal keywd "`ifndef")) | |
6426 (setq ignore-next t)) | |
6427 ((or ignore-next | |
6428 (member keywd verilog-keywords) | |
6429 (string-match "^\\$" keywd)) ;; PLI task | |
6430 (setq ignore-next nil)) | |
6431 (t | |
6432 (setq keywd (verilog-symbol-detick-denumber keywd)) | |
6433 (when got-sig | |
6434 (if got-rvalue (setq sigs-in (cons got-sig sigs-in)) | |
6435 (setq sigs-out (cons got-sig sigs-out))) | |
6436 ;;(if dbg (setq dbg (concat dbg (format "\t\tgot-sig=%S rv=%S\n" got-sig got-rvalue)))) | |
6437 ) | |
6438 (setq got-rvalue rvalue | |
6439 got-sig (if (or (not keywd) | |
6440 (assoc keywd (if got-rvalue sigs-in sigs-out))) | |
6441 nil (list keywd nil nil)) | |
6442 sig-tolk t))) | |
6443 (skip-chars-forward "a-zA-Z0-9$_.%`")) | |
6444 (t | |
6445 (forward-char 1))) | |
6446 ;; End of non-comment token | |
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6447 (setq last-keywd keywd))) |
79545 | 6448 (skip-syntax-forward " ")) |
6449 ;; Append the final pending signal | |
6450 (when got-sig | |
6451 (if got-rvalue (setq sigs-in (cons got-sig sigs-in)) | |
6452 (setq sigs-out (cons got-sig sigs-out))) | |
6453 ;;(if dbg (setq dbg (concat dbg (format "\t\tgot-sig=%S rv=%S\n" got-sig got-rvalue)))) | |
6454 (setq got-sig nil)) | |
6455 ;;(if dbg (setq dbg (concat dbg (format "ENDRecursion %s\n" exit-keywd)))) | |
6456 )) | |
6457 | |
6458 (defun verilog-read-always-signals () | |
6459 "Parse always block at point and return list of (outputs inout inputs)." | |
6460 ;; Insert new | |
6461 (save-excursion | |
6462 (let* (;;(dbg "") | |
6463 sigs-in sigs-out | |
6464 uses-delayed) ;; Found signal/rvalue; push if not function | |
6465 (search-forward ")") | |
6466 (verilog-read-always-signals-recurse nil nil nil) | |
6467 ;;(if dbg (save-excursion (set-buffer (get-buffer-create "*vl-dbg*")) (delete-region (point-min) (point-max)) (insert dbg) (setq dbg ""))) | |
6468 ;; Return what was found | |
6469 (list sigs-out nil sigs-in uses-delayed)))) | |
6470 | |
6471 (defun verilog-read-instants () | |
6472 "Parse module at point and return list of ( ( file instance ) ... )." | |
6473 (verilog-beg-of-defun) | |
6474 (let* ((end-mod-point (verilog-get-end-of-defun t)) | |
6475 (state nil) | |
6476 (instants-list nil)) | |
6477 (save-excursion | |
6478 (while (< (point) end-mod-point) | |
6479 ;; Stay at level 0, no comments | |
6480 (while (progn | |
6481 (setq state (parse-partial-sexp (point) end-mod-point 0 t nil)) | |
6482 (or (> (car state) 0) ; in parens | |
6483 (nth 5 state) ; comment | |
6484 )) | |
6485 (forward-line 1)) | |
6486 (beginning-of-line) | |
6487 (if (looking-at "^\\s-*\\([a-zA-Z0-9`_$]+\\)\\s-+\\([a-zA-Z0-9`_$]+\\)\\s-*(") | |
6488 ;;(if (looking-at "^\\(.+\\)$") | |
6489 (let ((module (match-string 1)) | |
6490 (instant (match-string 2))) | |
6491 (if (not (member module verilog-keywords)) | |
6492 (setq instants-list (cons (list module instant) instants-list))))) | |
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6493 (forward-line 1))) |
79545 | 6494 instants-list)) |
6495 | |
6496 | |
6497 (defun verilog-read-auto-template (module) | |
6498 "Look for a auto_template for the instantiation of the given MODULE. | |
6499 If found returns the signal name connections. Return REGEXP and | |
6500 list of ( (signal_name connection_name)... )" | |
6501 (save-excursion | |
6502 ;; Find beginning | |
6503 (let ((tpl-regexp "\\([0-9]+\\)") | |
6504 (lineno 0) | |
6505 (templateno 0) | |
6506 tpl-sig-list tpl-wild-list tpl-end-pt rep) | |
6507 (cond ((or | |
6508 (re-search-backward (concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil t) | |
6509 (progn | |
6510 (goto-char (point-min)) | |
6511 (re-search-forward (concat "^\\s-*/?\\*?\\s-*" module "\\s-+AUTO_TEMPLATE") nil t))) | |
6512 (goto-char (match-end 0)) | |
6513 ;; Parse "REGEXP" | |
6514 ;; We reserve @"..." for future lisp expressions that evaluate once-per-AUTOINST | |
6515 (when (looking-at "\\s-*\"\\([^\"]*)\\)\"") | |
6516 (setq tpl-regexp (match-string 1)) | |
6517 (goto-char (match-end 0))) | |
6518 (search-forward "(") | |
6519 ;; Parse lines in the template | |
6520 (when verilog-auto-inst-template-numbers | |
6521 (save-excursion | |
6522 (goto-char (point-min)) | |
6523 (while (search-forward "AUTO_TEMPLATE" nil t) | |
6524 (setq templateno (1+ templateno))))) | |
6525 (setq tpl-end-pt (save-excursion | |
6526 (backward-char 1) | |
6527 (forward-sexp 1) ;; Moves to paren that closes argdecl's | |
6528 (backward-char 1) | |
6529 (point))) | |
6530 ;; | |
6531 (while (< (point) tpl-end-pt) | |
6532 (cond ((looking-at "\\s-*\\.\\([a-zA-Z0-9`_$]+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)") | |
6533 (setq tpl-sig-list (cons (list | |
6534 (match-string-no-properties 1) | |
6535 (match-string-no-properties 2) | |
6536 templateno lineno) | |
6537 tpl-sig-list)) | |
6538 (goto-char (match-end 0))) | |
6539 ;; Regexp form?? | |
6540 ((looking-at | |
6541 ;; Regexp bug in xemacs disallows ][ inside [], and wants + last | |
6542 "\\s-*\\.\\(\\([a-zA-Z0-9`_$+@^.*?|---]+\\|[][]\\|\\\\[()|]\\)+\\)\\s-*(\\(.*\\))\\s-*\\(,\\|)\\s-*;\\)") | |
6543 (setq rep (match-string-no-properties 3)) | |
6544 (goto-char (match-end 0)) | |
6545 (setq tpl-wild-list | |
6546 (cons (list | |
6547 (concat "^" | |
6548 (verilog-string-replace-matches "@" "\\\\([0-9]+\\\\)" nil nil | |
6549 (match-string 1)) | |
6550 "$") | |
6551 rep | |
6552 templateno lineno) | |
6553 tpl-wild-list))) | |
6554 ((looking-at "[ \t\f]+") | |
6555 (goto-char (match-end 0))) | |
6556 ((looking-at "\n") | |
6557 (setq lineno (1+ lineno)) | |
6558 (goto-char (match-end 0))) | |
6559 ((looking-at "//") | |
6560 (search-forward "\n")) | |
6561 ((looking-at "/\\*") | |
6562 (forward-char 2) | |
6563 (or (search-forward "*/") | |
6564 (error "%s: Unmatched /* */, at char %d" (verilog-point-text) (point)))) | |
6565 (t | |
6566 (error "%s: AUTO_TEMPLATE parsing error: %s" | |
6567 (verilog-point-text) | |
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6568 (progn (looking-at ".*$") (match-string 0)))))) |
79545 | 6569 ;; Return |
6570 (vector tpl-regexp | |
6571 (list tpl-sig-list tpl-wild-list))) | |
6572 ;; If no template found | |
6573 (t (vector tpl-regexp nil)))))) | |
6574 ;;(progn (find-file "auto-template.v") (verilog-read-auto-template "ptl_entry")) | |
6575 | |
6576 (defun verilog-set-define (defname defvalue &optional buffer enumname) | |
6577 "Set the definition DEFNAME to the DEFVALUE in the given BUFFER. | |
6578 Optionally associate it with the specified enumeration ENUMNAME." | |
6579 (save-excursion | |
6580 (set-buffer (or buffer (current-buffer))) | |
6581 (let ((mac (intern (concat "vh-" defname)))) | |
6582 ;;(message "Define %s=%s" defname defvalue) (sleep-for 1) | |
6583 ;; Need to define to a constant if no value given | |
6584 (set (make-variable-buffer-local mac) | |
6585 (if (equal defvalue "") "1" defvalue))) | |
6586 (if enumname | |
6587 (let ((enumvar (intern (concat "venum-" enumname)))) | |
6588 ;;(message "Define %s=%s" defname defvalue) (sleep-for 1) | |
6589 (make-variable-buffer-local enumvar) | |
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parents:
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|
6590 (add-to-list enumvar defname))))) |
79545 | 6591 |
6592 (defun verilog-read-defines (&optional filename recurse subcall) | |
6593 "Read `defines and parameters for the current file, or optional FILENAME. | |
6594 If the filename is provided, `verilog-library-flags' will be used to | |
6595 resolve it. If optional RECURSE is non-nil, recurse through `includes. | |
6596 | |
6597 Parameters must be simple assignments to constants, or have their own | |
6598 \"parameter\" label rather than a list of parameters. Thus: | |
6599 | |
6600 parameter X = 5, Y = 10; // Ok | |
6601 parameter X = {1'b1, 2'h2}; // Ok | |
6602 parameter X = {1'b1, 2'h2}, Y = 10; // Bad, make into 2 parameter lines | |
6603 | |
6604 Defines must be simple text substitutions, one on a line, starting | |
6605 at the beginning of the line. Any ifdefs or multiline comments around the | |
6606 define are ignored. | |
6607 | |
6608 Defines are stored inside Emacs variables using the name vh-{definename}. | |
6609 | |
6610 This function is useful for setting vh-* variables. The file variables | |
6611 feature can be used to set defines that `verilog-mode' can see; put at the | |
6612 *END* of your file something like: | |
6613 | |
6614 // Local Variables: | |
6615 // vh-macro:\"macro_definition\" | |
6616 // End: | |
6617 | |
6618 If macros are defined earlier in the same file and you want their values, | |
6619 you can read them automatically (provided `enable-local-eval' is on): | |
6620 | |
6621 // Local Variables: | |
6622 // eval:(verilog-read-defines) | |
6623 // eval:(verilog-read-defines \"group_standard_includes.v\") | |
6624 // End: | |
6625 | |
6626 Note these are only read when the file is first visited, you must use | |
6627 \\[find-alternate-file] RET to have these take effect after editing them! | |
6628 | |
6629 If you want to disable the \"Process `eval' or hook local variables\" | |
6630 warning message, you need to add to your .emacs file: | |
6631 | |
6632 (setq enable-local-eval t)" | |
6633 (let ((origbuf (current-buffer))) | |
6634 (save-excursion | |
6635 (unless subcall (verilog-getopt-flags)) | |
6636 (when filename | |
6637 (let ((fns (verilog-library-filenames filename (buffer-file-name)))) | |
6638 (if fns | |
6639 (set-buffer (find-file-noselect (car fns))) | |
6640 (error (concat (verilog-point-text) | |
6641 ": Can't find verilog-read-defines file: " filename))))) | |
6642 (when recurse | |
6643 (goto-char (point-min)) | |
6644 (while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n\f]+\\)" nil t) | |
6645 (let ((inc (verilog-string-replace-matches "\"" "" nil nil (match-string-no-properties 1)))) | |
6646 (unless (verilog-inside-comment-p) | |
6647 (verilog-read-defines inc recurse t))))) | |
6648 ;; Read `defines | |
6649 ;; note we don't use verilog-re... it's faster this way, and that | |
6650 ;; function has problems when comments are at the end of the define | |
6651 (goto-char (point-min)) | |
6652 (while (re-search-forward "^\\s-*`define\\s-+\\([a-zA-Z0-9_$]+\\)\\s-+\\(.*\\)$" nil t) | |
6653 (let ((defname (match-string-no-properties 1)) | |
6654 (defvalue (match-string-no-properties 2))) | |
6655 (setq defvalue (verilog-string-replace-matches "\\s-*/[/*].*$" "" nil nil defvalue)) | |
6656 (verilog-set-define defname defvalue origbuf))) | |
6657 ;; Hack: Read parameters | |
6658 (goto-char (point-min)) | |
6659 (while (re-search-forward | |
6660 "^\\s-*\\(parameter\\|localparam\\)\\(\\(\\s-*\\[[^]]*\\]\\|\\)\\s-+\\([a-zA-Z0-9_$]+\\)\\s-*=\\s-*\\([^;,]*\\),?\\|\\)\\s-*" nil t) | |
6661 (let ((var (match-string-no-properties 4)) | |
6662 (val (match-string-no-properties 5)) | |
6663 enumname) | |
6664 ;; The primary way of getting defines is verilog-read-decls | |
6665 ;; However, that isn't called yet for included files, so we'll add another scheme | |
6666 (if (looking-at "[^\n]*synopsys\\s +enum\\s +\\([a-zA-Z0-9_]+\\)") | |
6667 (setq enumname (match-string-no-properties 1))) | |
6668 (if var | |
6669 (verilog-set-define var val origbuf enumname)) | |
6670 (forward-comment 999) | |
6671 (while (looking-at "\\s-*,?\\s-*\\([a-zA-Z0-9_$]+\\)\\s-*=\\s-*\\([^;,]*\\),?\\s-*") | |
6672 (verilog-set-define (match-string-no-properties 1) (match-string-no-properties 2) origbuf enumname) | |
6673 (goto-char (match-end 0)) | |
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|
6674 (forward-comment 999))))))) |
79545 | 6675 |
6676 (defun verilog-read-includes () | |
6677 "Read `includes for the current file. | |
6678 This will find all of the `includes which are at the beginning of lines, | |
6679 ignoring any ifdefs or multiline comments around them. | |
6680 `verilog-read-defines' is then performed on the current and each included | |
6681 file. | |
6682 | |
6683 It is often useful put at the *END* of your file something like: | |
6684 | |
6685 // Local Variables: | |
6686 // eval:(verilog-read-defines) | |
6687 // eval:(verilog-read-includes) | |
6688 // End: | |
6689 | |
6690 Note includes are only read when the file is first visited, you must use | |
6691 \\[find-alternate-file] RET to have these take effect after editing them! | |
6692 | |
6693 It is good to get in the habit of including all needed files in each .v | |
6694 file that needs it, rather than waiting for compile time. This will aid | |
6695 this process, Verilint, and readability. To prevent defining the same | |
6696 variable over and over when many modules are compiled together, put a test | |
6697 around the inside each include file: | |
6698 | |
6699 foo.v (a include): | |
6700 `ifdef _FOO_V // include if not already included | |
6701 `else | |
6702 `define _FOO_V | |
6703 ... contents of file | |
6704 `endif // _FOO_V" | |
6705 ;;slow: (verilog-read-defines nil t)) | |
6706 (save-excursion | |
6707 (verilog-getopt-flags) | |
6708 (goto-char (point-min)) | |
6709 (while (re-search-forward "^\\s-*`include\\s-+\\([^ \t\n\f]+\\)" nil t) | |
6710 (let ((inc (verilog-string-replace-matches "\"" "" nil nil (match-string 1)))) | |
6711 (verilog-read-defines inc nil t))))) | |
6712 | |
6713 (defun verilog-read-signals (&optional start end) | |
6714 "Return a simple list of all possible signals in the file. | |
6715 Bounded by optional region from START to END. Overly aggressive but fast. | |
6716 Some macros and such are also found and included. For dinotrace.el" | |
6717 (let (sigs-all keywd) | |
6718 (progn;save-excursion | |
6719 (goto-char (or start (point-min))) | |
6720 (setq end (or end (point-max))) | |
6721 (while (re-search-forward "[\"/a-zA-Z_.%`]" end t) | |
6722 (forward-char -1) | |
6723 (cond | |
6724 ((looking-at "//") | |
6725 (search-forward "\n")) | |
6726 ((looking-at "/\\*") | |
6727 (search-forward "*/")) | |
6728 ((looking-at "(\\*") | |
6729 (or (looking-at "(\\*\\s-*)") ; It's a "always @ (*)" | |
6730 (search-forward "*)"))) | |
6731 ((eq ?\" (following-char)) | |
6732 (re-search-forward "[^\\]\"")) ;; don't forward-char first, since we look for a non backslash first | |
6733 ((looking-at "\\s-*\\([a-zA-Z0-9$_.%`]+\\)") | |
6734 (goto-char (match-end 0)) | |
6735 (setq keywd (match-string-no-properties 1)) | |
6736 (or (member keywd verilog-keywords) | |
6737 (member keywd sigs-all) | |
6738 (setq sigs-all (cons keywd sigs-all)))) | |
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6739 (t (forward-char 1)))) |
79545 | 6740 ;; Return list |
6741 sigs-all))) | |
6742 | |
6743 ;; | |
6744 ;; Argument file parsing | |
6745 ;; | |
6746 | |
6747 (defun verilog-getopt (arglist) | |
6748 "Parse -f, -v etc arguments in ARGLIST list or string." | |
6749 (unless (listp arglist) (setq arglist (list arglist))) | |
6750 (let ((space-args '()) | |
6751 arg next-param) | |
6752 ;; Split on spaces, so users can pass whole command lines | |
6753 (while arglist | |
6754 (setq arg (car arglist) | |
6755 arglist (cdr arglist)) | |
6756 (while (string-match "^\\([^ \t\n\f]+\\)[ \t\n\f]*\\(.*$\\)" arg) | |
6757 (setq space-args (append space-args | |
6758 (list (match-string-no-properties 1 arg)))) | |
6759 (setq arg (match-string 2 arg)))) | |
6760 ;; Parse arguments | |
6761 (while space-args | |
6762 (setq arg (car space-args) | |
6763 space-args (cdr space-args)) | |
6764 (cond | |
6765 ;; Need another arg | |
6766 ((equal arg "-f") | |
6767 (setq next-param arg)) | |
6768 ((equal arg "-v") | |
6769 (setq next-param arg)) | |
6770 ((equal arg "-y") | |
6771 (setq next-param arg)) | |
6772 ;; +libext+(ext1)+(ext2)... | |
6773 ((string-match "^\\+libext\\+\\(.*\\)" arg) | |
6774 (setq arg (match-string 1 arg)) | |
6775 (while (string-match "\\([^+]+\\)\\+?\\(.*\\)" arg) | |
6776 (verilog-add-list-unique `verilog-library-extensions | |
6777 (match-string 1 arg)) | |
6778 (setq arg (match-string 2 arg)))) | |
6779 ;; | |
6780 ((or (string-match "^-D\\([^+=]*\\)[+=]\\(.*\\)" arg) ;; -Ddefine=val | |
6781 (string-match "^-D\\([^+=]*\\)\\(\\)" arg) ;; -Ddefine | |
6782 (string-match "^\\+define\\([^+=]*\\)[+=]\\(.*\\)" arg) ;; +define+val | |
6783 (string-match "^\\+define\\([^+=]*\\)\\(\\)" arg)) ;; +define+define | |
6784 (verilog-set-define (match-string 1 arg) (match-string 2 arg))) | |
6785 ;; | |
6786 ((or (string-match "^\\+incdir\\+\\(.*\\)" arg) ;; +incdir+dir | |
6787 (string-match "^-I\\(.*\\)" arg)) ;; -Idir | |
6788 (verilog-add-list-unique `verilog-library-directories | |
6789 (match-string 1 arg))) | |
6790 ;; Ignore | |
6791 ((equal "+librescan" arg)) | |
6792 ((string-match "^-U\\(.*\\)" arg)) ;; -Udefine | |
6793 ;; Second parameters | |
6794 ((equal next-param "-f") | |
6795 (setq next-param nil) | |
6796 (verilog-getopt-file arg)) | |
6797 ((equal next-param "-v") | |
6798 (setq next-param nil) | |
6799 (verilog-add-list-unique `verilog-library-files arg)) | |
6800 ((equal next-param "-y") | |
6801 (setq next-param nil) | |
6802 (verilog-add-list-unique `verilog-library-directories arg)) | |
6803 ;; Filename | |
6804 ((string-match "^[^-+]" arg) | |
6805 (verilog-add-list-unique `verilog-library-files arg)) | |
6806 ;; Default - ignore; no warning | |
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6807 )))) |
79545 | 6808 ;;(verilog-getopt (list "+libext+.a+.b" "+incdir+foodir" "+define+a+aval" "-f" "otherf" "-v" "library" "-y" "dir")) |
6809 | |
6810 (defun verilog-getopt-file (filename) | |
6811 "Read verilog options from the specified FILENAME." | |
6812 (save-excursion | |
6813 (let ((fns (verilog-library-filenames filename (buffer-file-name))) | |
6814 (orig-buffer (current-buffer)) | |
6815 line) | |
6816 (if fns | |
6817 (set-buffer (find-file-noselect (car fns))) | |
6818 (error (concat (verilog-point-text) | |
6819 "Can't find verilog-getopt-file -f file: " filename))) | |
6820 (goto-char (point-min)) | |
6821 (while (not (eobp)) | |
6822 (setq line (buffer-substring (point) | |
6823 (save-excursion (end-of-line) (point)))) | |
6824 (forward-line 1) | |
6825 (when (string-match "//" line) | |
6826 (setq line (substring line 0 (match-beginning 0)))) | |
6827 (save-excursion | |
6828 (set-buffer orig-buffer) ; Variables are buffer-local, so need right context. | |
6829 (verilog-getopt line)))))) | |
6830 | |
6831 (defun verilog-getopt-flags () | |
6832 "Convert `verilog-library-flags' into standard library variables." | |
6833 ;; If the flags are local, then all the outputs should be local also | |
6834 (when (local-variable-p `verilog-library-flags (current-buffer)) | |
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6835 (mapc 'make-local-variable '(verilog-library-extensions |
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6836 verilog-library-directories |
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6837 verilog-library-files |
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6838 verilog-library-flags))) |
79545 | 6839 ;; Allow user to customize |
6840 (run-hooks 'verilog-before-getopt-flags-hook) | |
6841 ;; Process arguments | |
6842 (verilog-getopt verilog-library-flags) | |
6843 ;; Allow user to customize | |
6844 (run-hooks 'verilog-getopt-flags-hook)) | |
6845 | |
6846 (defun verilog-add-list-unique (varref object) | |
6847 "Append to VARREF list the given OBJECT, | |
6848 unless it is already a member of the variable's list" | |
6849 (unless (member object (symbol-value varref)) | |
6850 (set varref (append (symbol-value varref) (list object)))) | |
6851 varref) | |
6852 ;;(progn (setq l '()) (verilog-add-list-unique `l "a") (verilog-add-list-unique `l "a") l) | |
6853 | |
6854 | |
6855 ;; | |
6856 ;; Module name lookup | |
6857 ;; | |
6858 | |
6859 (defun verilog-module-inside-filename-p (module filename) | |
6860 "Return point if MODULE is specified inside FILENAME, else nil. | |
6861 Allows version control to check out the file if need be." | |
6862 (and (or (file-exists-p filename) | |
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6863 (and (fboundp 'vc-backend) |
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6864 (vc-backend filename))) |
79545 | 6865 (let (pt) |
6866 (save-excursion | |
6867 (set-buffer (find-file-noselect filename)) | |
6868 (goto-char (point-min)) | |
6869 (while (and | |
6870 ;; It may be tempting to look for verilog-defun-re, don't, it slows things down a lot! | |
6871 (verilog-re-search-forward-quick "\\<module\\>" nil t) | |
6872 (verilog-re-search-forward-quick "[(;]" nil t)) | |
6873 (if (equal module (verilog-read-module-name)) | |
6874 (setq pt (point)))) | |
6875 pt)))) | |
6876 | |
6877 (defun verilog-is-number (symbol) | |
6878 "Return true if SYMBOL is number-like." | |
6879 (or (string-match "^[0-9 \t:]+$" symbol) | |
6880 (string-match "^[---]*[0-9]+$" symbol) | |
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6881 (string-match "^[0-9 \t]+'s?[hdxbo][0-9a-fA-F_xz? \t]*$" symbol))) |
79545 | 6882 |
6883 (defun verilog-symbol-detick (symbol wing-it) | |
6884 "Return a expanded SYMBOL name without any defines. | |
6885 If the variable vh-{symbol} is defined, return that value. | |
6886 If undefined, and WING-IT, return just SYMBOL without the tick, else nil." | |
6887 (while (and symbol (string-match "^`" symbol)) | |
6888 (setq symbol (substring symbol 1)) | |
6889 (setq symbol | |
6890 (if (boundp (intern (concat "vh-" symbol))) | |
6891 ;; Emacs has a bug where boundp on a buffer-local | |
6892 ;; variable in only one buffer returns t in another. | |
6893 ;; This can confuse, so check for nil. | |
6894 (let ((val (eval (intern (concat "vh-" symbol))))) | |
6895 (if (eq val nil) | |
6896 (if wing-it symbol nil) | |
6897 val)) | |
6898 (if wing-it symbol nil)))) | |
6899 symbol) | |
6900 ;;(verilog-symbol-detick "`mod" nil) | |
6901 | |
6902 (defun verilog-symbol-detick-denumber (symbol) | |
6903 "Return SYMBOL with defines converted and any numbers dropped to nil." | |
6904 (when (string-match "^`" symbol) | |
6905 ;; This only will work if the define is a simple signal, not | |
6906 ;; something like a[b]. Sorry, it should be substituted into the parser | |
6907 (setq symbol | |
6908 (verilog-string-replace-matches | |
6909 "\[[^0-9: \t]+\]" "" nil nil | |
6910 (or (verilog-symbol-detick symbol nil) | |
6911 (if verilog-auto-sense-defines-constant | |
6912 "0" | |
6913 symbol))))) | |
6914 (if (verilog-is-number symbol) | |
6915 nil | |
6916 symbol)) | |
6917 | |
6918 (defun verilog-symbol-detick-text (text) | |
6919 "Return TEXT with any without any known defines. | |
6920 If the variable vh-{symbol} is defined, substitute that value." | |
6921 (let ((ok t) symbol val) | |
6922 (while (and ok (string-match "`\\([a-zA-Z0-9_]+\\)" text)) | |
6923 (setq symbol (match-string 1 text)) | |
6924 (message symbol) | |
6925 (cond ((and | |
6926 (boundp (intern (concat "vh-" symbol))) | |
6927 ;; Emacs has a bug where boundp on a buffer-local | |
6928 ;; variable in only one buffer returns t in another. | |
6929 ;; This can confuse, so check for nil. | |
6930 (setq val (eval (intern (concat "vh-" symbol))))) | |
6931 (setq text (replace-match val nil nil text))) | |
6932 (t (setq ok nil))))) | |
6933 text) | |
6934 ;;(progn (setq vh-mod "`foo" vh-foo "bar") (verilog-symbol-detick-text "bar `mod `undefed")) | |
6935 | |
6936 (defun verilog-expand-dirnames (&optional dirnames) | |
6937 "Return a list of existing directories given a list of wildcarded DIRNAMES. | |
6938 Or, just the existing dirnames themselves if there are no wildcards." | |
6939 (interactive) | |
6940 (unless dirnames (error "`verilog-library-directories' should include at least '.'")) | |
6941 (setq dirnames (reverse dirnames)) ; not nreverse | |
6942 (let ((dirlist nil) | |
6943 pattern dirfile dirfiles dirname root filename rest) | |
6944 (while dirnames | |
6945 (setq dirname (substitute-in-file-name (car dirnames)) | |
6946 dirnames (cdr dirnames)) | |
6947 (cond ((string-match (concat "^\\(\\|[/\\]*[^*?]*[/\\]\\)" ;; root | |
6948 "\\([^/\\]*[*?][^/\\]*\\)" ;; filename with *? | |
6949 "\\(.*\\)") ;; rest | |
6950 dirname) | |
6951 (setq root (match-string 1 dirname) | |
6952 filename (match-string 2 dirname) | |
6953 rest (match-string 3 dirname) | |
6954 pattern filename) | |
6955 ;; now replace those * and ? with .+ and . | |
6956 ;; use ^ and /> to get only whole file names | |
6957 ;;verilog-string-replace-matches | |
6958 (setq pattern (verilog-string-replace-matches "[*]" ".+" nil nil pattern) | |
6959 pattern (verilog-string-replace-matches "[?]" "." nil nil pattern) | |
6960 | |
6961 ;; Unfortunately allows abc/*/rtl to match abc/rtl | |
6962 ;; because abc/.. shows up in dirfiles. Solutions welcome. | |
6963 dirfiles (if (file-directory-p root) ; Ignore version control external | |
6964 (directory-files root t pattern nil))) | |
6965 (while dirfiles | |
6966 (setq dirfile (expand-file-name (concat (car dirfiles) rest)) | |
6967 dirfiles (cdr dirfiles)) | |
6968 (if (file-directory-p dirfile) | |
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6969 (setq dirlist (cons dirfile dirlist))))) |
79545 | 6970 ;; Defaults |
6971 (t | |
6972 (if (file-directory-p dirname) | |
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6973 (setq dirlist (cons dirname dirlist)))))) |
79545 | 6974 dirlist)) |
6975 ;;(verilog-expand-dirnames (list "." ".." "nonexist" "../*" "/home/wsnyder/*/v")) | |
6976 | |
6977 (defun verilog-library-filenames (filename current &optional check-ext) | |
6978 "Return a search path to find the given FILENAME name. | |
6979 Uses the CURRENT filename, `verilog-library-directories' and | |
6980 `verilog-library-extensions' variables to build the path. | |
6981 With optional CHECK-EXT also check `verilog-library-extensions'." | |
6982 (let ((ckdir (verilog-expand-dirnames verilog-library-directories)) | |
6983 fn outlist) | |
6984 (while ckdir | |
6985 (let ((ckext (if check-ext verilog-library-extensions `("")))) | |
6986 (while ckext | |
6987 (setq fn (expand-file-name | |
6988 (concat filename (car ckext)) | |
6989 (expand-file-name (car ckdir) (file-name-directory current)))) | |
6990 (if (file-exists-p fn) | |
6991 (setq outlist (cons fn outlist))) | |
6992 (setq ckext (cdr ckext)))) | |
6993 (setq ckdir (cdr ckdir))) | |
6994 (nreverse outlist))) | |
6995 | |
6996 (defun verilog-module-filenames (module current) | |
6997 "Return a search path to find the given MODULE name. | |
6998 Uses the CURRENT filename, `verilog-library-extensions', | |
6999 `verilog-library-directories' and `verilog-library-files' | |
7000 variables to build the path." | |
7001 ;; Return search locations for it | |
7002 (append (list current) ; first, current buffer | |
7003 (verilog-library-filenames module current t) | |
7004 verilog-library-files)) ; finally, any libraries | |
7005 | |
7006 ;; | |
7007 ;; Module Information | |
7008 ;; | |
7009 ;; Many of these functions work on "modi" a module information structure | |
7010 ;; A modi is: [module-name-string file-name begin-point] | |
7011 | |
7012 (defvar verilog-cache-enabled t | |
7013 "If true, enable caching of signals, etc. Set to nil for debugging to make things SLOW!") | |
7014 | |
7015 (defvar verilog-modi-cache-list nil | |
7016 "Cache of ((Module Function) Buf-Tick Buf-Modtime Func-Returns)... | |
7017 For speeding up verilog-modi-get-* commands. | |
7018 Buffer-local.") | |
7019 | |
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7020 (make-variable-buffer-local 'verilog-modi-cache-list) |
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7021 |
79545 | 7022 (defvar verilog-modi-cache-preserve-tick nil |
7023 "Modification tick after which the cache is still considered valid. | |
7024 Use verilog-preserve-cache's to set") | |
7025 (defvar verilog-modi-cache-preserve-buffer nil | |
7026 "Modification tick after which the cache is still considered valid. | |
7027 Use verilog-preserve-cache's to set") | |
7028 | |
7029 (defun verilog-modi-current () | |
7030 "Return the modi structure for the module currently at point." | |
7031 (let* (name pt) | |
7032 ;; read current module's name | |
7033 (save-excursion | |
7034 (verilog-re-search-backward-quick verilog-defun-re nil nil) | |
7035 (verilog-re-search-forward-quick "(" nil nil) | |
7036 (setq name (verilog-read-module-name)) | |
7037 (setq pt (point))) | |
7038 ;; return | |
7039 (vector name (or (buffer-file-name) (current-buffer)) pt))) | |
7040 | |
7041 (defvar verilog-modi-lookup-last-mod nil "Cache of last module looked up.") | |
7042 (defvar verilog-modi-lookup-last-modi nil "Cache of last modi returned.") | |
7043 (defvar verilog-modi-lookup-last-current nil "Cache of last `current-buffer' looked up.") | |
7044 (defvar verilog-modi-lookup-last-tick nil "Cache of last `buffer-modified-tick' looked up.") | |
7045 | |
7046 (defun verilog-modi-lookup (module allow-cache &optional ignore-error) | |
7047 "Find the file and point at which MODULE is defined. | |
7048 If ALLOW-CACHE is set, check and remember cache of previous lookups. | |
7049 Return modi if successful, else print message unless IGNORE-ERROR is true." | |
7050 (let* ((current (or (buffer-file-name) (current-buffer)))) | |
7051 (cond ((and verilog-modi-lookup-last-modi | |
7052 verilog-cache-enabled | |
7053 allow-cache | |
7054 (equal verilog-modi-lookup-last-mod module) | |
7055 (equal verilog-modi-lookup-last-current current) | |
7056 (equal verilog-modi-lookup-last-tick (buffer-modified-tick))) | |
7057 ;; ok as is | |
7058 ) | |
7059 (t (let* ((realmod (verilog-symbol-detick module t)) | |
7060 (orig-filenames (verilog-module-filenames realmod current)) | |
7061 (filenames orig-filenames) | |
7062 pt) | |
7063 (while (and filenames (not pt)) | |
7064 (if (not (setq pt (verilog-module-inside-filename-p realmod (car filenames)))) | |
7065 (setq filenames (cdr filenames)))) | |
7066 (cond (pt (setq verilog-modi-lookup-last-modi | |
7067 (vector realmod (car filenames) pt))) | |
7068 (t (setq verilog-modi-lookup-last-modi nil) | |
7069 (or ignore-error | |
7070 (error (concat (verilog-point-text) | |
7071 ": Can't locate " module " module definition" | |
7072 (if (not (equal module realmod)) | |
7073 (concat " (Expanded macro to " realmod ")") | |
7074 "") | |
7075 "\n Check the verilog-library-directories variable." | |
7076 "\n I looked in (if not listed, doesn't exist):\n\t" | |
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7077 (mapconcat 'concat orig-filenames "\n\t")))))) |
79545 | 7078 (setq verilog-modi-lookup-last-mod module |
7079 verilog-modi-lookup-last-current current | |
7080 verilog-modi-lookup-last-tick (buffer-modified-tick))))) | |
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7081 verilog-modi-lookup-last-modi)) |
79545 | 7082 |
7083 (defsubst verilog-modi-name (modi) | |
7084 (aref modi 0)) | |
7085 (defsubst verilog-modi-file-or-buffer (modi) | |
7086 (aref modi 1)) | |
7087 (defsubst verilog-modi-point (modi) | |
7088 (aref modi 2)) | |
7089 | |
7090 (defun verilog-modi-filename (modi) | |
7091 "Filename of MODI, or name of buffer if its never been saved." | |
7092 (if (bufferp (verilog-modi-file-or-buffer modi)) | |
7093 (or (buffer-file-name (verilog-modi-file-or-buffer modi)) | |
7094 (buffer-name (verilog-modi-file-or-buffer modi))) | |
7095 (verilog-modi-file-or-buffer modi))) | |
7096 | |
7097 (defun verilog-modi-goto (modi) | |
7098 "Move point/buffer to specified MODI." | |
7099 (or modi (error "Passed unfound modi to goto, check earlier")) | |
7100 (set-buffer (if (bufferp (verilog-modi-file-or-buffer modi)) | |
7101 (verilog-modi-file-or-buffer modi) | |
7102 (find-file-noselect (verilog-modi-file-or-buffer modi)))) | |
7103 (or (equal major-mode `verilog-mode) ;; Put into verilog mode to get syntax | |
7104 (verilog-mode)) | |
7105 (goto-char (verilog-modi-point modi))) | |
7106 | |
7107 (defun verilog-goto-defun-file (module) | |
7108 "Move point to the file at which a given MODULE is defined." | |
7109 (interactive "sGoto File for Module: ") | |
7110 (let* ((modi (verilog-modi-lookup module nil))) | |
7111 (when modi | |
7112 (verilog-modi-goto modi) | |
7113 (switch-to-buffer (current-buffer))))) | |
7114 | |
7115 (defun verilog-modi-cache-results (modi function) | |
7116 "Run on MODI the given FUNCTION. Locate the module in a file. | |
7117 Cache the output of function so next call may have faster access." | |
7118 (let (func-returns fass) | |
7119 (save-excursion | |
7120 (verilog-modi-goto modi) | |
7121 (if (and (setq fass (assoc (list (verilog-modi-name modi) function) | |
7122 verilog-modi-cache-list)) | |
7123 ;; Destroy caching when incorrect; Modified or file changed | |
7124 (not (and verilog-cache-enabled | |
7125 (or (equal (buffer-modified-tick) (nth 1 fass)) | |
7126 (and verilog-modi-cache-preserve-tick | |
7127 (<= verilog-modi-cache-preserve-tick (nth 1 fass)) | |
7128 (equal verilog-modi-cache-preserve-buffer (current-buffer)))) | |
7129 (equal (visited-file-modtime) (nth 2 fass))))) | |
7130 (setq verilog-modi-cache-list nil | |
7131 fass nil)) | |
7132 (cond (fass | |
7133 ;; Found | |
7134 (setq func-returns (nth 3 fass))) | |
7135 (t | |
7136 ;; Read from file | |
7137 ;; Clear then restore any hilighting to make emacs19 happy | |
7138 (let ((fontlocked (when (and (boundp 'font-lock-mode) | |
7139 font-lock-mode) | |
7140 (font-lock-mode nil) | |
7141 t))) | |
7142 (setq func-returns (funcall function)) | |
7143 (when fontlocked (font-lock-mode t))) | |
7144 ;; Cache for next time | |
7145 (setq verilog-modi-cache-list | |
7146 (cons (list (list (verilog-modi-name modi) function) | |
7147 (buffer-modified-tick) | |
7148 (visited-file-modtime) | |
7149 func-returns) | |
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|
7150 verilog-modi-cache-list))))) |
79545 | 7151 ;; |
7152 func-returns)) | |
7153 | |
7154 (defun verilog-modi-cache-add (modi function element sig-list) | |
7155 "Add function return results to the module cache. | |
7156 Update MODI's cache for given FUNCTION so that the return ELEMENT of that | |
7157 function now contains the additional SIG-LIST parameters." | |
7158 (let (fass) | |
7159 (save-excursion | |
7160 (verilog-modi-goto modi) | |
7161 (if (setq fass (assoc (list (verilog-modi-name modi) function) | |
7162 verilog-modi-cache-list)) | |
7163 (let ((func-returns (nth 3 fass))) | |
7164 (aset func-returns element | |
7165 (append sig-list (aref func-returns element)))))))) | |
7166 | |
7167 (defmacro verilog-preserve-cache (&rest body) | |
7168 "Execute the BODY forms, allowing cache preservation within BODY. | |
7169 This means that changes to the buffer will not result in the cache being | |
7170 flushed. If the changes affect the modsig state, they must call the | |
7171 modsig-cache-add-* function, else the results of later calls may be | |
7172 incorrect. Without this, changes are assumed to be adding/removing signals | |
7173 and invalidating the cache." | |
7174 `(let ((verilog-modi-cache-preserve-tick (buffer-modified-tick)) | |
7175 (verilog-modi-cache-preserve-buffer (current-buffer))) | |
7176 (progn ,@body))) | |
7177 | |
7178 | |
7179 (defun verilog-signals-matching-enum (in-list enum) | |
7180 "Return all signals in IN-LIST matching the given ENUM." | |
7181 (let (out-list) | |
7182 (while in-list | |
7183 (if (equal (verilog-sig-enum (car in-list)) enum) | |
7184 (setq out-list (cons (car in-list) out-list))) | |
7185 (setq in-list (cdr in-list))) | |
7186 ;; New scheme | |
7187 (let* ((enumvar (intern (concat "venum-" enum))) | |
7188 (enumlist (and (boundp enumvar) (eval enumvar)))) | |
7189 (while enumlist | |
7190 (add-to-list 'out-list (list (car enumlist))) | |
7191 (setq enumlist (cdr enumlist)))) | |
7192 (nreverse out-list))) | |
7193 | |
7194 (defun verilog-signals-not-matching-regexp (in-list regexp) | |
7195 "Return all signals in IN-LIST not matching the given REGEXP, if non-nil." | |
7196 (if (not regexp) | |
7197 in-list | |
7198 (let (out-list) | |
7199 (while in-list | |
7200 (if (not (string-match regexp (verilog-sig-name (car in-list)))) | |
7201 (setq out-list (cons (car in-list) out-list))) | |
7202 (setq in-list (cdr in-list))) | |
7203 (nreverse out-list)))) | |
7204 | |
7205 ;; Combined | |
7206 (defun verilog-modi-get-signals (modi) | |
7207 (append | |
7208 (verilog-modi-get-outputs modi) | |
7209 (verilog-modi-get-inouts modi) | |
7210 (verilog-modi-get-inputs modi) | |
7211 (verilog-modi-get-wires modi) | |
7212 (verilog-modi-get-regs modi) | |
7213 (verilog-modi-get-assigns modi) | |
7214 (verilog-modi-get-consts modi) | |
7215 (verilog-modi-get-gparams modi))) | |
7216 | |
7217 (defun verilog-modi-get-ports (modi) | |
7218 (append | |
7219 (verilog-modi-get-outputs modi) | |
7220 (verilog-modi-get-inouts modi) | |
7221 (verilog-modi-get-inputs modi))) | |
7222 | |
7223 (defsubst verilog-modi-cache-add-outputs (modi sig-list) | |
7224 (verilog-modi-cache-add modi 'verilog-read-decls 0 sig-list)) | |
7225 (defsubst verilog-modi-cache-add-inouts (modi sig-list) | |
7226 (verilog-modi-cache-add modi 'verilog-read-decls 1 sig-list)) | |
7227 (defsubst verilog-modi-cache-add-inputs (modi sig-list) | |
7228 (verilog-modi-cache-add modi 'verilog-read-decls 2 sig-list)) | |
7229 (defsubst verilog-modi-cache-add-wires (modi sig-list) | |
7230 (verilog-modi-cache-add modi 'verilog-read-decls 3 sig-list)) | |
7231 (defsubst verilog-modi-cache-add-regs (modi sig-list) | |
7232 (verilog-modi-cache-add modi 'verilog-read-decls 4 sig-list)) | |
7233 | |
7234 (defun verilog-signals-from-signame (signame-list) | |
7235 "Return signals in standard form from SIGNAME-LIST, a simple list of signal names." | |
7236 (mapcar (function (lambda (name) (list name nil nil))) | |
7237 signame-list)) | |
7238 | |
7239 ;; | |
7240 ;; Auto creation utilities | |
7241 ;; | |
7242 | |
7243 (defun verilog-auto-search-do (search-for func) | |
7244 "Search for the given auto text SEARCH-FOR, and perform FUNC where it occurs." | |
7245 (goto-char (point-min)) | |
7246 (while (search-forward search-for nil t) | |
7247 (if (not (save-excursion | |
7248 (goto-char (match-beginning 0)) | |
7249 (verilog-inside-comment-p))) | |
7250 (funcall func)))) | |
7251 | |
7252 (defun verilog-auto-re-search-do (search-for func) | |
7253 "Search for the given auto text SEARCH-FOR, and perform FUNC where it occurs." | |
7254 (goto-char (point-min)) | |
7255 (while (re-search-forward search-for nil t) | |
7256 (if (not (save-excursion | |
7257 (goto-char (match-beginning 0)) | |
7258 (verilog-inside-comment-p))) | |
7259 (funcall func)))) | |
7260 | |
7261 (defun verilog-insert-one-definition (sig type indent-pt) | |
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7262 "Print out a definition for SIG of the given TYPE, |
79545 | 7263 with appropriate INDENT-PT indentation." |
7264 (indent-to indent-pt) | |
7265 (insert type) | |
7266 (when (verilog-sig-signed sig) | |
7267 (insert " " (verilog-sig-signed sig))) | |
7268 (when (verilog-sig-multidim sig) | |
7269 (insert " " (verilog-sig-multidim-string sig))) | |
7270 (when (verilog-sig-bits sig) | |
7271 (insert " " (verilog-sig-bits sig))) | |
7272 (indent-to (max 24 (+ indent-pt 16))) | |
7273 (unless (= (char-syntax (preceding-char)) ?\ ) | |
7274 (insert " ")) ; Need space between "]name" if indent-to did nothing | |
7275 (insert (verilog-sig-name sig))) | |
7276 | |
7277 (defun verilog-insert-definition (sigs direction indent-pt v2k &optional dont-sort) | |
7278 "Print out a definition for a list of SIGS of the given DIRECTION, | |
7279 with appropriate INDENT-PT indentation. If V2K, use Verilog 2001 I/O | |
7280 format. Sort unless DONT-SORT. DIRECTION is normally wire/reg/output." | |
7281 (or dont-sort | |
7282 (setq sigs (sort (copy-alist sigs) `verilog-signals-sort-compare))) | |
7283 (while sigs | |
7284 (let ((sig (car sigs))) | |
7285 (verilog-insert-one-definition | |
7286 sig | |
7287 ;; Want "type x" or "output type x", not "wire type x" | |
7288 (cond ((verilog-sig-type sig) | |
7289 (concat | |
7290 (if (not (equal direction "wire")) | |
7291 (concat direction " ")) | |
7292 (verilog-sig-type sig))) | |
7293 (t direction)) | |
7294 indent-pt) | |
7295 (insert (if v2k "," ";")) | |
7296 (if (or (not (verilog-sig-comment sig)) | |
7297 (equal "" (verilog-sig-comment sig))) | |
7298 (insert "\n") | |
7299 (indent-to (max 48 (+ indent-pt 40))) | |
7300 (insert (concat "// " (verilog-sig-comment sig) "\n"))) | |
7301 (setq sigs (cdr sigs))))) | |
7302 | |
7303 (eval-when-compile | |
7304 (if (not (boundp 'indent-pt)) | |
7305 (defvar indent-pt nil "Local used by insert-indent"))) | |
7306 | |
7307 (defun verilog-insert-indent (&rest stuff) | |
7308 "Indent to position stored in local `indent-pt' variable, then insert STUFF. | |
7309 Presumes that any newlines end a list element." | |
7310 (let ((need-indent t)) | |
7311 (while stuff | |
7312 (if need-indent (indent-to indent-pt)) | |
7313 (setq need-indent nil) | |
7314 (insert (car stuff)) | |
7315 (setq need-indent (string-match "\n$" (car stuff)) | |
7316 stuff (cdr stuff))))) | |
7317 ;;(let ((indent-pt 10)) (verilog-insert-indent "hello\n" "addon" "there\n")) | |
7318 | |
7319 (defun verilog-repair-open-comma () | |
7320 "If backwards-from-point is other than a open parenthesis insert comma." | |
7321 (save-excursion | |
7322 (verilog-backward-syntactic-ws) | |
7323 (when (save-excursion | |
7324 (backward-char 1) | |
7325 (and (not (looking-at "[(,]")) | |
7326 (progn | |
7327 (verilog-re-search-backward "[(`]" nil t) | |
7328 (looking-at "(")))) | |
7329 (insert ",")))) | |
7330 | |
7331 (defun verilog-repair-close-comma () | |
7332 "If point is at a comma followed by a close parenthesis, fix it. | |
7333 This repairs those mis-inserted by a AUTOARG." | |
7334 ;; It would be much nicer if Verilog allowed extra commas like Perl does! | |
7335 (save-excursion | |
7336 (verilog-forward-close-paren) | |
7337 (backward-char 1) | |
7338 (verilog-backward-syntactic-ws) | |
7339 (backward-char 1) | |
7340 (when (looking-at ",") | |
7341 (delete-char 1)))) | |
7342 | |
7343 (defun verilog-get-list (start end) | |
7344 "Return the elements of a comma separated list between START and END." | |
7345 (interactive) | |
7346 (let ((my-list (list)) | |
7347 my-string) | |
7348 (save-excursion | |
7349 (while (< (point) end) | |
7350 (when (re-search-forward "\\([^,{]+\\)" end t) | |
7351 (setq my-string (verilog-string-remove-spaces (match-string 1))) | |
7352 (setq my-list (nconc my-list (list my-string) )) | |
7353 (goto-char (match-end 0)))) | |
7354 my-list))) | |
7355 | |
7356 (defun verilog-make-width-expression (range-exp) | |
7357 "Return an expression calculating the length of a range [x:y] in RANGE-EXP." | |
7358 ;; strip off the [] | |
7359 (cond ((not range-exp) | |
7360 "1") | |
7361 (t | |
7362 (if (string-match "^\\[\\(.*\\)\\]$" range-exp) | |
7363 (setq range-exp (match-string 1 range-exp))) | |
7364 (cond ((not range-exp) | |
7365 "1") | |
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|
7366 ((string-match "^\\s *\\([0-9]+\\)\\s *:\\s *\\([0-9]+\\)\\s *$" |
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79555
diff
changeset
|
7367 range-exp) |
d3e3c91e18f6
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79555
diff
changeset
|
7368 (int-to-string |
d3e3c91e18f6
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79555
diff
changeset
|
7369 (1+ (abs (- (string-to-number (match-string 1 range-exp)) |
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79555
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changeset
|
7370 (string-to-number (match-string 2 range-exp))))))) |
79545 | 7371 ((string-match "^\\(.*\\)\\s *:\\s *\\(.*\\)\\s *$" range-exp) |
79691
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parents:
79555
diff
changeset
|
7372 (concat "(1+(" (match-string 1 range-exp) ")" |
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79717
diff
changeset
|
7373 (if (equal "0" (match-string 2 range-exp)) |
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parents:
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diff
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|
7374 "" ;; Don't bother with -(0) |
79545 | 7375 (concat "-(" (match-string 2 range-exp) ")")) |
7376 ")")) | |
7377 (t nil))))) | |
7378 ;;(verilog-make-width-expression "`A:`B") | |
7379 | |
7380 (defun verilog-typedef-name-p (variable-name) | |
7381 "Return true if the VARIABLE-NAME is a type definition." | |
7382 (when verilog-typedef-regexp | |
7383 (string-match verilog-typedef-regexp variable-name))) | |
7384 | |
7385 ;; | |
7386 ;; Auto deletion | |
7387 ;; | |
7388 | |
7389 (defun verilog-delete-autos-lined () | |
7390 "Delete autos that occupy multiple lines, between begin and end comments." | |
7391 (let ((pt (point))) | |
7392 (forward-line 1) | |
7393 (when (and | |
7394 (looking-at "\\s-*// Beginning") | |
7395 (search-forward "// End of automatic" nil t)) | |
7396 ;; End exists | |
7397 (end-of-line) | |
7398 (delete-region pt (point)) | |
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changeset
|
7399 (forward-line 1)))) |
79545 | 7400 |
7401 (defun verilog-forward-close-paren () | |
7402 "Find the close parenthesis that match the current point, | |
7403 ignore other close parenthesis with matching open parens" | |
7404 (let ((parens 1)) | |
7405 (while (> parens 0) | |
7406 (unless (verilog-re-search-forward-quick "[()]" nil t) | |
7407 (error "%s: Mismatching ()" (verilog-point-text))) | |
7408 (cond ((= (preceding-char) ?\( ) | |
7409 (setq parens (1+ parens))) | |
7410 ((= (preceding-char) ?\) ) | |
7411 (setq parens (1- parens))))))) | |
7412 | |
7413 (defun verilog-backward-open-paren () | |
7414 "Find the open parenthesis that match the current point, | |
7415 ignore other open parenthesis with matching close parens" | |
7416 (let ((parens 1)) | |
7417 (while (> parens 0) | |
7418 (unless (verilog-re-search-backward-quick "[()]" nil t) | |
7419 (error "%s: Mismatching ()" (verilog-point-text))) | |
7420 (cond ((= (following-char) ?\) ) | |
7421 (setq parens (1+ parens))) | |
7422 ((= (following-char) ?\( ) | |
7423 (setq parens (1- parens))))))) | |
7424 | |
7425 (defun verilog-backward-open-bracket () | |
7426 "Find the open bracket that match the current point, | |
7427 ignore other open bracket with matching close bracket" | |
7428 (let ((parens 1)) | |
7429 (while (> parens 0) | |
7430 (unless (verilog-re-search-backward-quick "[][]" nil t) | |
7431 (error "%s: Mismatching []" (verilog-point-text))) | |
7432 (cond ((= (following-char) ?\] ) | |
7433 (setq parens (1+ parens))) | |
7434 ((= (following-char) ?\[ ) | |
7435 (setq parens (1- parens))))))) | |
7436 | |
7437 (defun verilog-delete-to-paren () | |
7438 "Delete the automatic inst/sense/arg created by autos. | |
7439 Deletion stops at the matching end parenthesis." | |
7440 (delete-region (point) | |
7441 (save-excursion | |
7442 (verilog-backward-open-paren) | |
7443 (forward-sexp 1) ;; Moves to paren that closes argdecl's | |
7444 (backward-char 1) | |
7445 (point)))) | |
7446 | |
7447 (defun verilog-auto-star-safe () | |
7448 "Return if a .* AUTOINST is safe to delete or expand. | |
7449 It was created by the AUTOS themselves, or by the user." | |
7450 (and verilog-auto-star-expand | |
7451 (looking-at "[ \t\n\f,]*\\([)]\\|// \\(Outputs\\|Inouts\\|Inputs\\)\\)"))) | |
7452 | |
7453 (defun verilog-delete-auto-star-all () | |
7454 "Delete a .* AUTOINST, if it is safe." | |
7455 (when (verilog-auto-star-safe) | |
7456 (verilog-delete-to-paren))) | |
7457 | |
7458 (defun verilog-delete-auto-star-implicit () | |
7459 "Delete all .* implicit connections created by `verilog-auto-star'. | |
7460 This function will be called automatically at save unless | |
7461 `verilog-auto-star-save' is set, any non-templated expanded pins will be | |
7462 removed." | |
7463 (interactive) | |
7464 (let (paren-pt indent have-close-paren) | |
7465 (save-excursion | |
7466 (goto-char (point-min)) | |
7467 ;; We need to match these even outside of comments. | |
7468 ;; For reasonable performance, we don't check if inside comments, sorry. | |
7469 (while (re-search-forward "// Implicit \\.\\*" nil t) | |
7470 (setq paren-pt (point)) | |
7471 (beginning-of-line) | |
7472 (setq have-close-paren | |
7473 (save-excursion | |
7474 (when (search-forward ");" paren-pt t) | |
7475 (setq indent (current-indentation)) | |
7476 t))) | |
7477 (delete-region (point) (+ 1 paren-pt)) ; Nuke line incl CR | |
7478 (when have-close-paren | |
7479 ;; Delete extra commentary | |
7480 (save-excursion | |
7481 (while (progn | |
7482 (forward-line -1) | |
7483 (looking-at "\\s *//\\s *\\(Outputs\\|Inouts\\|Inputs\\)\n")) | |
7484 (delete-region (match-beginning 0) (match-end 0)))) | |
7485 ;; If it is simple, we can put the ); on the same line as the last text | |
7486 (let ((rtn-pt (point))) | |
7487 (save-excursion | |
7488 (while (progn (backward-char 1) | |
7489 (looking-at "[ \t\n\f]"))) | |
7490 (when (looking-at ",") | |
7491 (delete-region (+ 1 (point)) rtn-pt)))) | |
7492 (when (bolp) | |
7493 (indent-to indent)) | |
7494 (insert ");\n") | |
7495 ;; Still need to kill final comma - always is one as we put one after the .* | |
7496 (re-search-backward ",") | |
7497 (delete-char 1)))))) | |
7498 | |
7499 (defun verilog-delete-auto () | |
7500 "Delete the automatic outputs, regs, and wires created by \\[verilog-auto]. | |
7501 Use \\[verilog-auto] to re-insert the updated AUTOs. | |
7502 | |
7503 The hooks `verilog-before-delete-auto-hook' and `verilog-delete-auto-hook' are | |
7504 called before and after this function, respectively." | |
7505 (interactive) | |
7506 (save-excursion | |
7507 (if (buffer-file-name) | |
7508 (find-file-noselect (buffer-file-name))) ;; To check we have latest version | |
7509 ;; Allow user to customize | |
7510 (run-hooks 'verilog-before-delete-auto-hook) | |
7511 | |
7512 ;; Remove those that have multi-line insertions | |
7513 (verilog-auto-re-search-do "/\\*AUTO\\(OUTPUTEVERY\\|CONCATCOMMENT\\|WIRE\\|REG\\|DEFINEVALUE\\|REGINPUT\\|INPUT\\|OUTPUT\\|INOUT\\|RESET\\|TIEOFF\\|UNUSED\\)\\*/" | |
7514 'verilog-delete-autos-lined) | |
7515 ;; Remove those that have multi-line insertions with parameters | |
7516 (verilog-auto-re-search-do "/\\*AUTO\\(INOUTMODULE\\|ASCIIENUM\\)([^)]*)\\*/" | |
7517 'verilog-delete-autos-lined) | |
7518 ;; Remove those that are in parenthesis | |
7519 (verilog-auto-re-search-do "/\\*\\(AS\\|AUTO\\(ARG\\|CONCATWIDTH\\|INST\\|INSTPARAM\\|SENSE\\)\\)\\*/" | |
7520 'verilog-delete-to-paren) | |
7521 ;; Do .* instantiations, but avoid removing any user pins by looking for our magic comments | |
7522 (verilog-auto-re-search-do "\\.\\*" | |
7523 'verilog-delete-auto-star-all) | |
7524 ;; Remove template comments ... anywhere in case was pasted after AUTOINST removed | |
7525 (goto-char (point-min)) | |
7526 (while (re-search-forward "\\s-*// \\(Templated\\|Implicit \\.\\*\\)[ \tLT0-9]*$" nil t) | |
7527 (replace-match "")) | |
7528 | |
7529 ;; Final customize | |
7530 (run-hooks 'verilog-delete-auto-hook))) | |
7531 | |
7532 ;; | |
7533 ;; Auto inject | |
7534 ;; | |
7535 | |
7536 (defun verilog-inject-auto () | |
7537 "Examine legacy non-AUTO code and insert AUTOs in appropriate places. | |
7538 | |
7539 Any always @ blocks with sensitivity lists that match computed lists will | |
7540 be replaced with /*AS*/ comments. | |
7541 | |
7542 Any cells will get /*AUTOINST*/ added to the end of the pin list. Pins with | |
7543 have identical names will be deleted. | |
7544 | |
7545 Argument lists will not be deleted, /*AUTOARG*/ will only be inserted to | |
7546 support adding new ports. You may wish to delete older ports yourself. | |
7547 | |
7548 For example: | |
7549 | |
7550 module ex_inject (i, o); | |
7551 input i; | |
7552 input j; | |
7553 output o; | |
7554 always @ (i or j) | |
7555 o = i | j; | |
7556 cell cell (.foobar(baz), | |
7557 .j(j)); | |
7558 endmodule | |
7559 | |
7560 Typing \\[verilog-inject-auto] will make this into: | |
7561 | |
7562 module ex_inject (i, o/*AUTOARG*/ | |
7563 // Inputs | |
7564 j); | |
7565 input i; | |
7566 output o; | |
7567 always @ (/*AS*/i or j) | |
7568 o = i | j; | |
7569 cell cell (.foobar(baz), | |
7570 /*AUTOINST*/ | |
7571 // Outputs | |
7572 .j(j)); | |
7573 endmodule" | |
7574 (interactive) | |
7575 (verilog-auto t)) | |
7576 | |
7577 (defun verilog-inject-arg () | |
7578 "Inject AUTOARG into new code. See `verilog-inject-auto'." | |
7579 ;; Presume one module per file. | |
7580 (save-excursion | |
7581 (goto-char (point-min)) | |
7582 (while (verilog-re-search-forward-quick "\\<module\\>" nil t) | |
7583 (let ((endmodp (save-excursion | |
7584 (verilog-re-search-forward-quick "\\<endmodule\\>" nil t) | |
7585 (point)))) | |
7586 ;; See if there's already a comment .. inside a comment so not verilog-re-search | |
7587 (when (not (re-search-forward "/\\*AUTOARG\\*/" endmodp t)) | |
7588 (verilog-re-search-forward-quick ";" nil t) | |
7589 (backward-char 1) | |
7590 (verilog-backward-syntactic-ws) | |
7591 (backward-char 1) ; Moves to paren that closes argdecl's | |
7592 (when (looking-at ")") | |
7593 (insert "/*AUTOARG*/"))))))) | |
7594 | |
7595 (defun verilog-inject-sense () | |
7596 "Inject AUTOSENSE into new code. See `verilog-inject-auto'." | |
7597 (save-excursion | |
7598 (goto-char (point-min)) | |
7599 (while (verilog-re-search-forward-quick "\\<always\\s *@\\s *(" nil t) | |
7600 (let ((start-pt (point)) | |
7601 (modi (verilog-modi-current)) | |
7602 pre-sigs | |
7603 got-sigs) | |
7604 (backward-char 1) | |
7605 (forward-sexp 1) | |
7606 (backward-char 1) ;; End ) | |
7607 (when (not (verilog-re-search-backward "/\\*\\(AUTOSENSE\\|AS\\)\\*/" start-pt t)) | |
7608 (setq pre-sigs (verilog-signals-from-signame | |
7609 (verilog-read-signals start-pt (point))) | |
7610 got-sigs (verilog-auto-sense-sigs modi nil)) | |
7611 (when (not (or (verilog-signals-not-in pre-sigs got-sigs) ; Both are equal? | |
7612 (verilog-signals-not-in got-sigs pre-sigs))) | |
7613 (delete-region start-pt (point)) | |
7614 (insert "/*AS*/"))))))) | |
7615 | |
7616 (defun verilog-inject-inst () | |
7617 "Inject AUTOINST into new code. See `verilog-inject-auto'." | |
7618 (save-excursion | |
7619 (goto-char (point-min)) | |
7620 ;; It's hard to distinguish modules; we'll instead search for pins. | |
7621 (while (verilog-re-search-forward-quick "\\.\\s *[a-zA-Z0-9`_\$]+\\s *(\\s *[a-zA-Z0-9`_\$]+\\s *)" nil t) | |
7622 (verilog-backward-open-paren) ;; Inst start | |
7623 (cond | |
7624 ((= (preceding-char) ?\#) ;; #(...) parameter section, not pin. Skip. | |
7625 (forward-char 1) | |
7626 (verilog-forward-close-paren)) ;; Parameters done | |
7627 (t | |
7628 (forward-char 1) | |
7629 (let ((indent-pt (+ (current-column))) | |
7630 (end-pt (save-excursion (verilog-forward-close-paren) (point)))) | |
7631 (cond ((verilog-re-search-forward "\\(/\\*AUTOINST\\*/\\|\\.\\*\\)" end-pt t) | |
7632 (goto-char end-pt)) ;; Already there, continue search with next instance | |
7633 (t | |
7634 ;; Delete identical interconnect | |
7635 (let ((case-fold-search nil)) ;; So we don't convert upper-to-lower, etc | |
7636 (while (verilog-re-search-forward "\\.\\s *\\([a-zA-Z0-9`_\$]+\\)*\\s *(\\s *\\1\\s *)\\s *" end-pt t) | |
7637 (delete-region (match-beginning 0) (match-end 0)) | |
7638 (setq end-pt (- end-pt (- (match-end 0) (match-beginning 0)))) ;; Keep it correct | |
7639 (while (or (looking-at "[ \t\n\f,]+") | |
7640 (looking-at "//[^\n]*")) | |
7641 (delete-region (match-beginning 0) (match-end 0)) | |
7642 (setq end-pt (- end-pt (- (match-end 0) (match-beginning 0))))))) | |
7643 (verilog-forward-close-paren) | |
7644 (backward-char 1) | |
7645 ;; Not verilog-re-search, as we don't want to strip comments | |
7646 (while (re-search-backward "[ \t\n\f]+" (- (point) 1) t) | |
7647 (delete-region (match-beginning 0) (match-end 0))) | |
7648 (insert "\n") | |
7649 (indent-to indent-pt) | |
7650 (insert "/*AUTOINST*/"))))))))) | |
7651 | |
7652 ;; | |
7653 ;; Auto save | |
7654 ;; | |
7655 | |
7656 (defun verilog-auto-save-check () | |
7657 "On saving see if we need auto update." | |
7658 (cond ((not verilog-auto-save-policy)) ; disabled | |
7659 ((not (save-excursion | |
7660 (save-match-data | |
7661 (let ((case-fold-search nil)) | |
7662 (goto-char (point-min)) | |
7663 (re-search-forward "AUTO" nil t)))))) | |
7664 ((eq verilog-auto-save-policy 'force) | |
7665 (verilog-auto)) | |
7666 ((not (buffer-modified-p))) | |
7667 ((eq verilog-auto-update-tick (buffer-modified-tick))) ; up-to-date | |
7668 ((eq verilog-auto-save-policy 'detect) | |
7669 (verilog-auto)) | |
7670 (t | |
7671 (when (yes-or-no-p "AUTO statements not recomputed, do it now? ") | |
7672 (verilog-auto)) | |
7673 ;; Don't ask again if didn't update | |
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diff
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|
7674 (set (make-local-variable 'verilog-auto-update-tick) (buffer-modified-tick)))) |
79545 | 7675 (when (not verilog-auto-star-save) |
7676 (verilog-delete-auto-star-implicit)) | |
7677 nil) ;; Always return nil -- we don't write the file ourselves | |
7678 | |
7679 (defun verilog-auto-read-locals () | |
7680 "Return file local variable segment at bottom of file." | |
7681 (save-excursion | |
7682 (goto-char (point-max)) | |
7683 (if (re-search-backward "Local Variables:" nil t) | |
7684 (buffer-substring-no-properties (point) (point-max)) | |
7685 ""))) | |
7686 | |
7687 (defun verilog-auto-reeval-locals (&optional force) | |
7688 "Read file local variable segment at bottom of file if it has changed. | |
7689 If FORCE, always reread it." | |
79691
d3e3c91e18f6
* progmodes/verilog-mode.el (top-level): Don't require compile.
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parents:
79555
diff
changeset
|
7690 (make-local-variable 'verilog-auto-last-file-locals) |
79545 | 7691 (let ((curlocal (verilog-auto-read-locals))) |
7692 (when (or force (not (equal verilog-auto-last-file-locals curlocal))) | |
7693 (setq verilog-auto-last-file-locals curlocal) | |
7694 ;; Note this may cause this function to be recursively invoked. | |
7695 ;; The above when statement will prevent it from recursing forever. | |
7696 (hack-local-variables) | |
7697 t))) | |
7698 | |
7699 ;; | |
7700 ;; Auto creation | |
7701 ;; | |
7702 | |
7703 (defun verilog-auto-arg-ports (sigs message indent-pt) | |
7704 "Print a list of ports for a AUTOINST. | |
7705 Takes SIGS list, adds MESSAGE to front and inserts each at INDENT-PT." | |
7706 (when sigs | |
7707 (insert "\n") | |
7708 (indent-to indent-pt) | |
7709 (insert message) | |
7710 (insert "\n") | |
7711 (let ((space "")) | |
7712 (indent-to indent-pt) | |
7713 (while sigs | |
7714 (cond ((> (+ 2 (current-column) (length (verilog-sig-name (car sigs)))) fill-column) | |
7715 (insert "\n") | |
7716 (indent-to indent-pt)) | |
7717 (t (insert space))) | |
7718 (insert (verilog-sig-name (car sigs)) ",") | |
7719 (setq sigs (cdr sigs) | |
7720 space " "))))) | |
7721 | |
7722 (defun verilog-auto-arg () | |
7723 "Expand AUTOARG statements. | |
7724 Replace the argument declarations at the beginning of the | |
7725 module with ones automatically derived from input and output | |
7726 statements. This can be dangerous if the module is instantiated | |
7727 using position-based connections, so use only name-based when | |
7728 instantiating the resulting module. Long lines are split based | |
7729 on the `fill-column', see \\[set-fill-column]. | |
7730 | |
7731 Limitations: | |
7732 Concatenation and outputting partial busses is not supported. | |
7733 | |
7734 Typedefs must match `verilog-typedef-regexp', which is disabled by default. | |
7735 | |
7736 For example: | |
7737 | |
7738 module ex_arg (/*AUTOARG*/); | |
7739 input i; | |
7740 output o; | |
7741 endmodule | |
7742 | |
7743 Typing \\[verilog-auto] will make this into: | |
7744 | |
7745 module ex_arg (/*AUTOARG*/ | |
7746 // Outputs | |
7747 o, | |
7748 // Inputs | |
7749 i | |
7750 ); | |
7751 input i; | |
7752 output o; | |
7753 endmodule | |
7754 | |
7755 Any ports declared between the ( and /*AUTOARG*/ are presumed to be | |
7756 predeclared and are not redeclared by AUTOARG. AUTOARG will make a | |
7757 conservative guess on adding a comma for the first signal, if you have any | |
7758 ifdefs or complicated expressions before the AUTOARG you will need to | |
7759 choose the comma yourself. | |
7760 | |
7761 Avoid declaring ports manually, as it makes code harder to maintain." | |
7762 (save-excursion | |
7763 (let ((modi (verilog-modi-current)) | |
7764 (skip-pins (aref (verilog-read-arg-pins) 0))) | |
7765 (verilog-repair-open-comma) | |
7766 (verilog-auto-arg-ports (verilog-signals-not-in | |
7767 (verilog-modi-get-outputs modi) | |
7768 skip-pins) | |
7769 "// Outputs" | |
7770 verilog-indent-level-declaration) | |
7771 (verilog-auto-arg-ports (verilog-signals-not-in | |
7772 (verilog-modi-get-inouts modi) | |
7773 skip-pins) | |
7774 "// Inouts" | |
7775 verilog-indent-level-declaration) | |
7776 (verilog-auto-arg-ports (verilog-signals-not-in | |
7777 (verilog-modi-get-inputs modi) | |
7778 skip-pins) | |
7779 "// Inputs" | |
7780 verilog-indent-level-declaration) | |
7781 (verilog-repair-close-comma) | |
7782 (unless (eq (char-before) ?/ ) | |
7783 (insert "\n")) | |
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parents:
79717
diff
changeset
|
7784 (indent-to verilog-indent-level-declaration)))) |
79545 | 7785 |
7786 (defun verilog-auto-inst-port-map (port-st) | |
7787 nil) | |
7788 | |
7789 (defvar vl-cell-type nil "See `verilog-auto-inst'.") ; Prevent compile warning | |
7790 (defvar vl-cell-name nil "See `verilog-auto-inst'.") ; Prevent compile warning | |
7791 (defvar vl-name nil "See `verilog-auto-inst'.") ; Prevent compile warning | |
7792 (defvar vl-width nil "See `verilog-auto-inst'.") ; Prevent compile warning | |
7793 (defvar vl-dir nil "See `verilog-auto-inst'.") ; Prevent compile warning | |
7794 | |
7795 (defun verilog-auto-inst-port (port-st indent-pt tpl-list tpl-num for-star) | |
7796 "Print out a instantiation connection for this PORT-ST. | |
7797 Insert to INDENT-PT, use template TPL-LIST. | |
7798 @ are instantiation numbers, replaced with TPL-NUM. | |
79799
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parents:
79717
diff
changeset
|
7799 @\"(expression @)\" are evaluated, with @ as a variable. |
57956dd69d3f
(top-level): Fix spacing.
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parents:
79717
diff
changeset
|
7800 If FOR-STAR add comment it is a .* expansion." |
79545 | 7801 (let* ((port (verilog-sig-name port-st)) |
7802 (tpl-ass (or (assoc port (car tpl-list)) | |
7803 (verilog-auto-inst-port-map port-st))) | |
7804 ;; vl-* are documented for user use | |
7805 (vl-name (verilog-sig-name port-st)) | |
7806 (vl-width (verilog-sig-width port-st)) | |
7807 (vl-bits (if (or verilog-auto-inst-vector | |
7808 (not (assoc port vector-skip-list)) | |
7809 (not (equal (verilog-sig-bits port-st) | |
7810 (verilog-sig-bits (assoc port vector-skip-list))))) | |
7811 (or (verilog-sig-bits port-st) "") | |
7812 "")) | |
7813 ;; Default if not found | |
7814 (tpl-net (if (verilog-sig-multidim port-st) | |
7815 (concat port "/*" (verilog-sig-multidim-string port-st) | |
7816 vl-bits "*/") | |
7817 (concat port vl-bits))) | |
7818 (case-fold-search nil)) | |
7819 ;; Find template | |
7820 (cond (tpl-ass ; Template of exact port name | |
7821 (setq tpl-net (nth 1 tpl-ass))) | |
7822 ((nth 1 tpl-list) ; Wildcards in template, search them | |
7823 (let ((wildcards (nth 1 tpl-list))) | |
7824 (while wildcards | |
7825 (when (string-match (nth 0 (car wildcards)) port) | |
7826 (setq tpl-ass (car wildcards) ; so allow @ parsing | |
7827 tpl-net (replace-match (nth 1 (car wildcards)) | |
7828 t nil port))) | |
7829 (setq wildcards (cdr wildcards)))))) | |
7830 ;; Parse Templated variable | |
7831 (when tpl-ass | |
7832 ;; Evaluate @"(lispcode)" | |
7833 (when (string-match "@\".*[^\\]\"" tpl-net) | |
7834 (while (string-match "@\"\\(\\([^\\\"]*\\(\\\\.\\)*\\)*\\)\"" tpl-net) | |
7835 (setq tpl-net | |
7836 (concat | |
7837 (substring tpl-net 0 (match-beginning 0)) | |
7838 (save-match-data | |
7839 (let* ((expr (match-string 1 tpl-net)) | |
7840 (value | |
7841 (progn | |
7842 (setq expr (verilog-string-replace-matches "\\\\\"" "\"" nil nil expr)) | |
7843 (setq expr (verilog-string-replace-matches "@" tpl-num nil nil expr)) | |
7844 (prin1 (eval (car (read-from-string expr))) | |
7845 (lambda (ch) ()))))) | |
7846 (if (numberp value) (setq value (number-to-string value))) | |
79799
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
7847 value)) |
79545 | 7848 (substring tpl-net (match-end 0)))))) |
7849 ;; Replace @ and [] magic variables in final output | |
7850 (setq tpl-net (verilog-string-replace-matches "@" tpl-num nil nil tpl-net)) | |
79799
57956dd69d3f
(top-level): Fix spacing.
Dan Nicolaescu <dann@ics.uci.edu>
parents:
79717
diff
changeset
|
7851 (setq tpl-net (verilog-string-replace-matches "\\[\\]" vl-bits nil nil tpl-net))) |
79545 | 7852 (indent-to indent-pt) |
7853 (insert "." port) | |
7854 (indent-to verilog-auto-inst-column) | |
7855 (insert "(" tpl-net "),") | |
7856 (cond (tpl-ass | |
7857 (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16) | |
7858 verilog-auto-inst-column)) | |
7859 (insert " // Templated") | |
7860 (when verilog-auto-inst-template-numbers | |
7861 (insert " T" (int-to-string (nth 2 tpl-ass)) | |
7862 " L" (int-to-string (nth 3 tpl-ass))))) | |
7863 (for-star | |
7864 (indent-to (+ (if (< verilog-auto-inst-column 48) 24 16) | |
7865 verilog-auto-inst-column)) | |
7866 (insert " // Implicit .\*"))) ;For some reason the . or * must be escaped... | |
7867 (insert "\n"))) | |
7868 ;;(verilog-auto-inst-port (list "foo" "[5:0]") 10 (list (list "foo" "a@\"(% (+ @ 1) 4)\"a")) "3") | |
7869 ;;(x "incom[@\"(+ (* 8 @) 7)\":@\"(* 8 @)\"]") | |
7870 ;;(x ".out (outgo[@\"(concat (+ (* 8 @) 7) \\\":\\\" ( * 8 @))\"]));") | |
7871 | |
7872 (defun verilog-auto-inst-first () | |
7873 "Insert , etc before first ever port in this instant, as part of \\[verilog-auto-inst]." | |
7874 ;; Do we need a trailing comma? | |
7875 ;; There maybe a ifdef or something similar before us. What a mess. Thus | |
7876 ;; to avoid trouble we only insert on preceeding ) or *. | |
7877 ;; Insert first port on new line | |
7878 (insert "\n") ;; Must insert before search, so point will move forward if insert comma | |
7879 (save-excursion | |
7880 (verilog-re-search-backward "[^ \t\n\f]" nil nil) | |
7881 (when (looking-at ")\\|\\*") ;; Generally don't insert, unless we are fairly sure | |
7882 (forward-char 1) | |
7883 (insert ",")))) | |
7884 | |
7885 (defun verilog-auto-star () | |
7886 "Expand SystemVerilog .* pins, as part of \\[verilog-auto]. | |
7887 | |
7888 If `verilog-auto-star-expand' is set, .* pins are treated if they were | |
7889 AUTOINST statements, otherwise they are ignored. For safety, Verilog-Mode | |
7890 will also ignore any .* that are not last in your pin list (this prevents | |
7891 it from deleting pins following the .* when it expands the AUTOINST.) | |
7892 | |
7893 On writing your file, unless `verilog-auto-star-save' is set, any | |
7894 non-templated expanded pins will be removed. You may do this at any time | |
7895 with \\[verilog-delete-auto-star-implicit]. | |
7896 | |
7897 If you are converting a module to use .* for the first time, you may wish | |
7898 to use \\[verilog-inject-auto] and then replace the created AUTOINST with .*. | |
7899 | |
7900 See `verilog-auto-inst' for examples, templates, and more information." | |
7901 (when (verilog-auto-star-safe) | |
7902 (verilog-auto-inst))) | |
7903 | |
7904 (defun verilog-auto-inst () | |
7905 "Expand AUTOINST statements, as part of \\[verilog-auto]. | |
7906 Replace the pin connections to an instantiation with ones | |
7907 automatically derived from the module header of the instantiated netlist. | |
7908 | |
7909 If `verilog-auto-star-expand' is set, also expand SystemVerilog .* ports, | |
7910 and delete them before saving unless `verilog-auto-star-save' is set. | |
7911 See `verilog-auto-star' for more information. | |
7912 | |
7913 Limitations: | |
7914 Module names must be resolvable to filenames by adding a | |
7915 `verilog-library-extensions', and being found in the same directory, or | |
7916 by changing the variable `verilog-library-flags' or | |
7917 `verilog-library-directories'. Macros `modname are translated through the | |
7918 vh-{name} Emacs variable, if that is not found, it just ignores the `. | |
7919 | |
7920 In templates you must have one signal per line, ending in a ), or ));, | |
7921 and have proper () nesting, including a final ); to end the template. | |
7922 | |
7923 Typedefs must match `verilog-typedef-regexp', which is disabled by default. | |
7924 | |
7925 SystemVerilog multidimmensional input/output has only experimental support. | |
7926 | |
7927 For example, first take the submodule inst.v: | |
7928 | |
7929 module inst (o,i) | |
7930 output [31:0] o; | |
7931 input i; | |
7932 wire [31:0] o = {32{i}}; | |
7933 endmodule | |
7934 | |
7935 This is then used in a upper level module: | |
7936 | |
7937 module ex_inst (o,i) | |
7938 output o; | |
7939 input i; | |
7940 inst inst (/*AUTOINST*/); | |
7941 endmodule | |
7942 | |
7943 Typing \\[verilog-auto] will make this into: | |
7944 | |
7945 module ex_inst (o,i) | |
7946 output o; | |
7947 input i; | |
7948 inst inst (/*AUTOINST*/ | |
7949 // Outputs | |
7950 .ov (ov[31:0]), | |
7951 // Inputs | |
7952 .i (i)); | |
7953 endmodule | |
7954 | |
7955 Where the list of inputs and outputs came from the inst module. | |
7956 | |
7957 Exceptions: | |
7958 | |
7959 Unless you are instantiating a module multiple times, or the module is | |
7960 something trivial like a adder, DO NOT CHANGE SIGNAL NAMES ACROSS HIERARCHY. | |
7961 It just makes for unmaintainable code. To sanitize signal names, try | |
7962 vrename from http://www.veripool.com | |
7963 | |
7964 When you need to violate this suggestion there are two ways to list | |
7965 exceptions, placing them before the AUTOINST, or using templates. | |
7966 | |
7967 Any ports defined before the /*AUTOINST*/ are not included in the list of | |
7968 automatics. This is similar to making a template as described below, but | |
7969 is restricted to simple connections just like you normally make. Also note | |
7970 that any signals before the AUTOINST will only be picked up by AUTOWIRE if | |
7971 you have the appropriate // Input or // Output comment, and exactly the | |
7972 same line formatting as AUTOINST itself uses. | |
7973 | |
7974 inst inst (// Inputs | |
7975 .i (my_i_dont_mess_with_it), | |
7976 /*AUTOINST*/ | |
7977 // Outputs | |
7978 .ov (ov[31:0])); | |
7979 | |
7980 | |
7981 Templates: | |
7982 | |
7983 For multiple instantiations based upon a single template, create a | |
7984 commented out template: | |
7985 | |
7986 /* instantiating_module_name AUTO_TEMPLATE ( | |
7987 .sig3 (sigz[]), | |
7988 ); | |
7989 */ | |
7990 | |
7991 Templates go ABOVE the instantiation(s). When a instantiation is | |
7992 expanded `verilog-mode' simply searches up for the closest template. | |
7993 Thus you can have multiple templates for the same module, just alternate | |
7994 between the template for a instantiation and the instantiation itself. | |
7995 | |
7996 The module name must be the same as the name of the module in the | |
7997 instantiation name, and the code \"AUTO_TEMPLATE\" must be in these exact | |
7998 words and capitalized. Only signals that must be different for each | |
7999 instantiation need to be listed. | |
8000 | |
8001 Inside a template, a [] in a connection name (with nothing else inside | |
8002 the brackets) will be replaced by the same bus subscript as it is being | |
8003 connected to, or the [] will be removed if it is a single bit signal. | |
8004 Generally it is a good idea to do this for all connections in a template, | |
8005 as then they will work for any width signal, and with AUTOWIRE. See | |
8006 PTL_BUS becoming PTL_BUSNEW below. | |
8007 | |
8008 If you have a complicated template, set `verilog-auto-inst-template-numbers' | |
8009 to see which regexps are matching. Don't leave that mode set after | |
8010 debugging is completed though, it will result in lots of extra differences | |
8011 and merge conflicts. | |
8012 | |
8013 For example: | |
8014 | |
8015 /* psm_mas AUTO_TEMPLATE ( | |
8016 .ptl_bus (ptl_busnew[]), | |
8017 ); | |
8018 */ | |
8019 psm_mas ms2m (/*AUTOINST*/); | |
8020 | |
8021 Typing \\[verilog-auto] will make this into: | |
8022 | |
8023 psm_mas ms2m (/*AUTOINST*/ | |
8024 // Outputs | |
8025 .NotInTemplate (NotInTemplate), | |
8026 .ptl_bus (ptl_busnew[3:0]), // Templated | |
8027 .... | |
8028 | |
8029 @ Templates: | |
8030 | |
8031 It is common to instantiate a cell multiple times, so templates make it | |
8032 trivial to substitute part of the cell name into the connection name. | |
8033 | |
8034 /* cell_type AUTO_TEMPLATE <optional \"REGEXP\"> ( | |
8035 .sig1 (sigx[@]), | |
8036 .sig2 (sigy[@\"(% (+ 1 @) 4)\"]), | |
8037 ); | |
8038 */ | |
8039 | |
8040 If no regular expression is provided immediately after the AUTO_TEMPLATE | |
8041 keyword, then the @ character in any connection names will be replaced | |
8042 with the instantiation number; the first digits found in the cell's | |
8043 instantiation name. | |
8044 | |
8045 If a regular expression is provided, the @ character will be replaced | |
8046 with the first \(\) grouping that matches against the cell name. Using a | |
8047 regexp of \"\\([0-9]+\\)\" provides identical values for @ as when no | |
8048 regexp is provided. If you use multiple layers of parenthesis, | |
8049 \"test\\([^0-9]+\\)_\\([0-9]+\\)\" would replace @ with non-number | |
8050 characters after test and before _, whereas | |
8051 \"\\(test\\([a-z]+\\)_\\([0-9]+\\)\\)\" would replace @ with the entire | |
8052 match. | |
8053 | |
8054 For example: | |
8055 | |
8056 /* psm_mas AUTO_TEMPLATE ( | |
8057 .ptl_mapvalidx (ptl_mapvalid[@]), | |
8058 .ptl_mapvalidp1x (ptl_mapvalid[@\"(% (+ 1 @) 4)\"]), | |
8059 ); | |
8060 */ | |
8061 psm_mas ms2m (/*AUTOINST*/); | |
8062 | |
8063 Typing \\[verilog-auto] will make this into: | |
8064 | |
8065 psm_mas ms2m (/*AUTOINST*/ | |
8066 // Outputs | |
8067 .ptl_mapvalidx (ptl_mapvalid[2]), | |
8068 .ptl_mapvalidp1x (ptl_mapvalid[3])); | |
8069 | |
8070 Note the @ character was replaced with the 2 from \"ms2m\". | |
8071 | |
8072 Alternatively, using a regular expression for @: | |
8073 | |
8074 /* psm_mas AUTO_TEMPLATE \"_\\([a-z]+\\)\" ( | |
8075 .ptl_mapvalidx (@_ptl_mapvalid), | |
8076 .ptl_mapvalidp1x (ptl_mapvalid_@), | |
8077 ); | |
8078 */ | |
8079 psm_mas ms2_FOO (/*AUTOINST*/); | |
8080 psm_mas ms2_BAR (/*AUTOINST*/); | |
8081 | |
8082 Typing \\[verilog-auto] will make this into: | |
8083 | |
8084 psm_mas ms2_FOO (/*AUTOINST*/ | |
8085 // Outputs | |
8086 .ptl_mapvalidx (FOO_ptl_mapvalid), | |
8087 .ptl_mapvalidp1x (ptl_mapvalid_FOO)); | |
8088 psm_mas ms2_BAR (/*AUTOINST*/ | |
8089 // Outputs | |
8090 .ptl_mapvalidx (BAR_ptl_mapvalid), | |
8091 .ptl_mapvalidp1x (ptl_mapvalid_BAR)); | |
8092 | |
8093 | |
8094 Regexp Templates: | |
8095 | |
8096 A template entry of the form | |
8097 | |
8098 .pci_req\\([0-9]+\\)_l (pci_req_jtag_[\\1]), | |
8099 | |
8100 will apply a Emacs style regular expression search for any port beginning | |
8101 in pci_req followed by numbers and ending in _l and connecting that to | |
8102 the pci_req_jtag_[] net, with the bus subscript coming from what matches | |
8103 inside the first set of \\( \\). Thus pci_req2_l becomes pci_req_jtag_[2]. | |
8104 | |
8105 Since \\([0-9]+\\) is so common and ugly to read, a @ in the port name | |
8106 does the same thing. (Note a @ in the connection/replacement text is | |
8107 completely different -- still use \\1 there!) Thus this is the same as | |
8108 the above template: | |
8109 | |
8110 .pci_req@_l (pci_req_jtag_[\\1]), | |
8111 | |
8112 Here's another example to remove the _l, useful when naming conventions | |
8113 specify _ alone to mean active low. Note the use of [] to keep the bus | |
8114 subscript: | |
8115 | |
8116 .\\(.*\\)_l (\\1_[]), | |
8117 | |
8118 Lisp Templates: | |
8119 | |
8120 First any regular expression template is expanded. | |
8121 | |
8122 If the syntax @\"( ... )\" is found in a connection, the expression in | |
8123 quotes will be evaluated as a Lisp expression, with @ replaced by the | |
8124 instantiation number. The MAPVALIDP1X example above would put @+1 modulo | |
8125 4 into the brackets. Quote all double-quotes inside the expression with | |
8126 a leading backslash (\\\"). There are special variables defined that are | |
8127 useful in these Lisp functions: | |
8128 | |
8129 vl-name Name portion of the input/output port | |
8130 vl-bits Bus bits portion of the input/output port ('[2:0]') | |
8131 vl-width Width of the input/output port ('3' for [2:0]) | |
8132 May be a (...) expression if bits isn't a constant. | |
8133 vl-dir Direction of the pin input/output/inout. | |
8134 vl-cell-type Module name/type of the cell ('psm_mas') | |
8135 vl-cell-name Instance name of the cell ('ms2m') | |
8136 | |
8137 Normal Lisp variables may be used in expressions. See | |
8138 `verilog-read-defines' which can set vh-{definename} variables for use | |
8139 here. Also, any comments of the form: | |
8140 | |
8141 /*AUTO_LISP(setq foo 1)*/ | |
8142 | |
8143 will evaluate any Lisp expression inside the parenthesis between the | |
8144 beginning of the buffer and the point of the AUTOINST. This allows | |
8145 functions to be defined or variables to be changed between instantiations. | |
8146 | |
8147 Note that when using lisp expressions errors may occur when @ is not a | |
8148 number, you may need to use the standard Emacs Lisp functions | |
8149 `number-to-string' and `string-to-number'. | |
8150 | |
8151 After the evaluation is completed, @ substitution and [] substitution | |
8152 occur." | |
8153 (save-excursion | |
8154 ;; Find beginning | |
8155 (let* ((pt (point)) | |
8156 (for-star (save-excursion (backward-char 2) (looking-at "\\.\\*"))) | |
8157 (indent-pt (save-excursion (verilog-backward-open-paren) | |
8158 (1+ (current-column)))) | |
8159 (verilog-auto-inst-column (max verilog-auto-inst-column | |
8160 (+ 16 (* 8 (/ (+ indent-pt 7) 8))))) | |
8161 (modi (verilog-modi-current)) | |
8162 (vector-skip-list (unless verilog-auto-inst-vector | |
8163 (verilog-modi-get-signals modi))) | |
8164 submod submodi inst skip-pins tpl-list tpl-num did-first) | |
8165 ;; Find module name that is instantiated | |
8166 (setq submod (verilog-read-inst-module) | |
8167 inst (verilog-read-inst-name) | |
8168 vl-cell-type submod | |
8169 vl-cell-name inst | |
8170 skip-pins (aref (verilog-read-inst-pins) 0)) | |
8171 | |
8172 ;; Parse any AUTO_LISP() before here | |
8173 (verilog-read-auto-lisp (point-min) pt) | |
8174 | |
8175 ;; Lookup position, etc of submodule | |
8176 ;; Note this may raise an error | |
8177 (when (setq submodi (verilog-modi-lookup submod t)) | |
8178 ;; If there's a number in the instantiation, it may be a argument to the | |
8179 ;; automatic variable instantiation program. | |
8180 (let* ((tpl-info (verilog-read-auto-template submod)) | |
8181 (tpl-regexp (aref tpl-info 0))) | |
8182 (setq tpl-num (if (string-match tpl-regexp inst) | |
8183 (match-string 1 inst) | |
8184 "") | |
8185 tpl-list (aref tpl-info 1))) | |
8186 ;; Find submodule's signals and dump | |
8187 (let ((sig-list (verilog-signals-not-in | |
8188 (verilog-modi-get-outputs submodi) | |
8189 skip-pins)) | |
8190 (vl-dir "output")) | |
8191 (when sig-list | |
8192 (when (not did-first) (verilog-auto-inst-first) (setq did-first t)) | |
8193 (indent-to indent-pt) | |
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8194 ;; Note these are searched for in verilog-read-sub-decls. |
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8195 (insert "// Outputs\n") |
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8196 (mapc (lambda (port) |
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8197 (verilog-auto-inst-port port indent-pt |
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8198 tpl-list tpl-num for-star)) |
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8199 sig-list))) |
79545 | 8200 (let ((sig-list (verilog-signals-not-in |
8201 (verilog-modi-get-inouts submodi) | |
8202 skip-pins)) | |
8203 (vl-dir "inout")) | |
8204 (when sig-list | |
8205 (when (not did-first) (verilog-auto-inst-first) (setq did-first t)) | |
8206 (indent-to indent-pt) | |
8207 (insert "// Inouts\n") | |
79691
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8208 (mapc (lambda (port) |
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8209 (verilog-auto-inst-port port indent-pt |
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|
8210 tpl-list tpl-num for-star)) |
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8211 sig-list))) |
79545 | 8212 (let ((sig-list (verilog-signals-not-in |
8213 (verilog-modi-get-inputs submodi) | |
8214 skip-pins)) | |
8215 (vl-dir "input")) | |
8216 (when sig-list | |
8217 (when (not did-first) (verilog-auto-inst-first) (setq did-first t)) | |
8218 (indent-to indent-pt) | |
8219 (insert "// Inputs\n") | |
79691
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8220 (mapc (lambda (port) |
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8221 (verilog-auto-inst-port port indent-pt |
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8222 tpl-list tpl-num for-star)) |
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|
8223 sig-list))) |
79545 | 8224 ;; Kill extra semi |
8225 (save-excursion | |
8226 (cond (did-first | |
8227 (re-search-backward "," pt t) | |
8228 (delete-char 1) | |
8229 (insert ");") | |
8230 (search-forward "\n") ;; Added by inst-port | |
8231 (delete-backward-char 1) | |
8232 (if (search-forward ")" nil t) ;; From user, moved up a line | |
8233 (delete-backward-char 1)) | |
8234 (if (search-forward ";" nil t) ;; Don't error if user had syntax error and forgot it | |
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8235 (delete-backward-char 1))))))))) |
79545 | 8236 |
8237 (defun verilog-auto-inst-param () | |
8238 "Expand AUTOINSTPARAM statements, as part of \\[verilog-auto]. | |
8239 Replace the parameter connections to an instantiation with ones | |
8240 automatically derived from the module header of the instantiated netlist. | |
8241 | |
8242 See \\[verilog-auto-inst] for limitations, and templates to customize the | |
8243 output. | |
8244 | |
8245 For example, first take the submodule inst.v: | |
8246 | |
8247 module inst (o,i) | |
8248 parameter PAR; | |
8249 endmodule | |
8250 | |
8251 This is then used in a upper level module: | |
8252 | |
8253 module ex_inst (o,i) | |
8254 parameter PAR; | |
8255 inst #(/*AUTOINSTPARAM*/) | |
8256 inst (/*AUTOINST*/); | |
8257 endmodule | |
8258 | |
8259 Typing \\[verilog-auto] will make this into: | |
8260 | |
8261 module ex_inst (o,i) | |
8262 output o; | |
8263 input i; | |
8264 inst (/*AUTOINSTPARAM*/ | |
8265 // Parameters | |
8266 .PAR (PAR)); | |
8267 inst (/*AUTOINST*/); | |
8268 endmodule | |
8269 | |
8270 Where the list of parameter connections come from the inst module. | |
8271 | |
8272 Templates: | |
8273 | |
8274 You can customize the parameter connections using AUTO_TEMPLATEs, | |
8275 just as you would with \\[verilog-auto-inst]." | |
8276 (save-excursion | |
8277 ;; Find beginning | |
8278 (let* ((pt (point)) | |
8279 (indent-pt (save-excursion (verilog-backward-open-paren) | |
8280 (1+ (current-column)))) | |
8281 (verilog-auto-inst-column (max verilog-auto-inst-column | |
8282 (+ 16 (* 8 (/ (+ indent-pt 7) 8))))) | |
8283 (modi (verilog-modi-current)) | |
8284 (vector-skip-list (unless verilog-auto-inst-vector | |
8285 (verilog-modi-get-signals modi))) | |
8286 submod submodi inst skip-pins tpl-list tpl-num did-first) | |
8287 ;; Find module name that is instantiated | |
8288 (setq submod (save-excursion | |
8289 ;; Get to the point where AUTOINST normally is to read the module | |
8290 (verilog-re-search-forward-quick "[(;]" nil nil) | |
8291 (verilog-read-inst-module)) | |
8292 inst (save-excursion | |
8293 ;; Get to the point where AUTOINST normally is to read the module | |
8294 (verilog-re-search-forward-quick "[(;]" nil nil) | |
8295 (verilog-read-inst-name)) | |
8296 vl-cell-type submod | |
8297 vl-cell-name inst | |
8298 skip-pins (aref (verilog-read-inst-pins) 0)) | |
8299 | |
8300 ;; Parse any AUTO_LISP() before here | |
8301 (verilog-read-auto-lisp (point-min) pt) | |
8302 | |
8303 ;; Lookup position, etc of submodule | |
8304 ;; Note this may raise an error | |
8305 (when (setq submodi (verilog-modi-lookup submod t)) | |
8306 ;; If there's a number in the instantiation, it may be a argument to the | |
8307 ;; automatic variable instantiation program. | |
8308 (let* ((tpl-info (verilog-read-auto-template submod)) | |
8309 (tpl-regexp (aref tpl-info 0))) | |
8310 (setq tpl-num (if (string-match tpl-regexp inst) | |
8311 (match-string 1 inst) | |
8312 "") | |
8313 tpl-list (aref tpl-info 1))) | |
8314 ;; Find submodule's signals and dump | |
8315 (let ((sig-list (verilog-signals-not-in | |
8316 (verilog-modi-get-gparams submodi) | |
8317 skip-pins)) | |
8318 (vl-dir "parameter")) | |
8319 (when sig-list | |
8320 (when (not did-first) (verilog-auto-inst-first) (setq did-first t)) | |
8321 (indent-to indent-pt) | |
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|
8322 ;; Note these are searched for in verilog-read-sub-decls. |
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|
8323 (insert "// Parameters\n") |
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|
8324 (mapc (lambda (port) |
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|
8325 (verilog-auto-inst-port port indent-pt |
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|
8326 tpl-list tpl-num nil)) |
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|
8327 sig-list))) |
79545 | 8328 ;; Kill extra semi |
8329 (save-excursion | |
8330 (cond (did-first | |
8331 (re-search-backward "," pt t) | |
8332 (delete-char 1) | |
8333 (insert ")") | |
8334 (search-forward "\n") ;; Added by inst-port | |
8335 (delete-backward-char 1) | |
8336 (if (search-forward ")" nil t) ;; From user, moved up a line | |
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|
8337 (delete-backward-char 1))))))))) |
79545 | 8338 |
8339 (defun verilog-auto-reg () | |
8340 "Expand AUTOREG statements, as part of \\[verilog-auto]. | |
8341 Make reg statements for any output that isn't already declared, | |
8342 and isn't a wire output from a block. | |
8343 | |
8344 Limitations: | |
8345 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls'). | |
8346 | |
8347 This does NOT work on memories, declare those yourself. | |
8348 | |
8349 An example: | |
8350 | |
8351 module ex_reg (o,i) | |
8352 output o; | |
8353 input i; | |
8354 /*AUTOREG*/ | |
8355 always o = i; | |
8356 endmodule | |
8357 | |
8358 Typing \\[verilog-auto] will make this into: | |
8359 | |
8360 module ex_reg (o,i) | |
8361 output o; | |
8362 input i; | |
8363 /*AUTOREG*/ | |
8364 // Beginning of automatic regs (for this module's undeclared outputs) | |
8365 reg o; | |
8366 // End of automatics | |
8367 always o = i; | |
8368 endmodule" | |
8369 (save-excursion | |
8370 ;; Point must be at insertion point. | |
8371 (let* ((indent-pt (current-indentation)) | |
8372 (modi (verilog-modi-current)) | |
8373 (sig-list (verilog-signals-not-in | |
8374 (verilog-modi-get-outputs modi) | |
8375 (append (verilog-modi-get-wires modi) | |
8376 (verilog-modi-get-regs modi) | |
8377 (verilog-modi-get-assigns modi) | |
8378 (verilog-modi-get-consts modi) | |
8379 (verilog-modi-get-gparams modi) | |
8380 (verilog-modi-get-sub-outputs modi) | |
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8381 (verilog-modi-get-sub-inouts modi))))) |
79545 | 8382 (forward-line 1) |
8383 (when sig-list | |
8384 (verilog-insert-indent "// Beginning of automatic regs (for this module's undeclared outputs)\n") | |
8385 (verilog-insert-definition sig-list "reg" indent-pt nil) | |
8386 (verilog-modi-cache-add-regs modi sig-list) | |
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8387 (verilog-insert-indent "// End of automatics\n"))))) |
79545 | 8388 |
8389 (defun verilog-auto-reg-input () | |
8390 "Expand AUTOREGINPUT statements, as part of \\[verilog-auto]. | |
8391 Make reg statements instantiation inputs that aren't already declared. | |
8392 This is useful for making a top level shell for testing the module that is | |
8393 to be instantiated. | |
8394 | |
8395 Limitations: | |
8396 This ONLY detects inputs of AUTOINSTants (see `verilog-read-sub-decls'). | |
8397 | |
8398 This does NOT work on memories, declare those yourself. | |
8399 | |
8400 An example (see `verilog-auto-inst' for what else is going on here): | |
8401 | |
8402 module ex_reg_input (o,i) | |
8403 output o; | |
8404 input i; | |
8405 /*AUTOREGINPUT*/ | |
8406 inst inst (/*AUTOINST*/); | |
8407 endmodule | |
8408 | |
8409 Typing \\[verilog-auto] will make this into: | |
8410 | |
8411 module ex_reg_input (o,i) | |
8412 output o; | |
8413 input i; | |
8414 /*AUTOREGINPUT*/ | |
8415 // Beginning of automatic reg inputs (for undeclared ... | |
8416 reg [31:0] iv; // From inst of inst.v | |
8417 // End of automatics | |
8418 inst inst (/*AUTOINST*/ | |
8419 // Outputs | |
8420 .o (o[31:0]), | |
8421 // Inputs | |
8422 .iv (iv)); | |
8423 endmodule" | |
8424 (save-excursion | |
8425 ;; Point must be at insertion point. | |
8426 (let* ((indent-pt (current-indentation)) | |
8427 (modi (verilog-modi-current)) | |
8428 (sig-list (verilog-signals-combine-bus | |
8429 (verilog-signals-not-in | |
8430 (append (verilog-modi-get-sub-inputs modi) | |
8431 (verilog-modi-get-sub-inouts modi)) | |
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8432 (verilog-modi-get-signals modi))))) |
79545 | 8433 (forward-line 1) |
8434 (when sig-list | |
8435 (verilog-insert-indent "// Beginning of automatic reg inputs (for undeclared instantiated-module inputs)\n") | |
8436 (verilog-insert-definition sig-list "reg" indent-pt nil) | |
8437 (verilog-modi-cache-add-regs modi sig-list) | |
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8438 (verilog-insert-indent "// End of automatics\n"))))) |
79545 | 8439 |
8440 (defun verilog-auto-wire () | |
8441 "Expand AUTOWIRE statements, as part of \\[verilog-auto]. | |
8442 Make wire statements for instantiations outputs that aren't | |
8443 already declared. | |
8444 | |
8445 Limitations: | |
8446 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls'), | |
8447 and all busses must have widths, such as those from AUTOINST, or using [] | |
8448 in AUTO_TEMPLATEs. | |
8449 | |
8450 This does NOT work on memories or SystemVerilog .name connections, | |
8451 declare those yourself. | |
8452 | |
8453 Verilog-mode will add \"Couldn't Merge\" comments to signals it cannot | |
8454 determine how to bus together. This occurs when you have ports with | |
8455 non-numeric or non-sequential bus subscripts. If Verilog-Mode | |
8456 mis-guessed, you'll have to declare them yourself. | |
8457 | |
8458 An example (see `verilog-auto-inst' for what else is going on here): | |
8459 | |
8460 module ex_wire (o,i) | |
8461 output o; | |
8462 input i; | |
8463 /*AUTOWIRE*/ | |
8464 inst inst (/*AUTOINST*/); | |
8465 endmodule | |
8466 | |
8467 Typing \\[verilog-auto] will make this into: | |
8468 | |
8469 module ex_wire (o,i) | |
8470 output o; | |
8471 input i; | |
8472 /*AUTOWIRE*/ | |
8473 // Beginning of automatic wires | |
8474 wire [31:0] ov; // From inst of inst.v | |
8475 // End of automatics | |
8476 inst inst (/*AUTOINST*/ | |
8477 // Outputs | |
8478 .ov (ov[31:0]), | |
8479 // Inputs | |
8480 .i (i)); | |
8481 wire o = | ov; | |
8482 endmodule" | |
8483 (save-excursion | |
8484 ;; Point must be at insertion point. | |
8485 (let* ((indent-pt (current-indentation)) | |
8486 (modi (verilog-modi-current)) | |
8487 (sig-list (verilog-signals-combine-bus | |
8488 (verilog-signals-not-in | |
8489 (append (verilog-modi-get-sub-outputs modi) | |
8490 (verilog-modi-get-sub-inouts modi)) | |
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8491 (verilog-modi-get-signals modi))))) |
79545 | 8492 (forward-line 1) |
8493 (when sig-list | |
8494 (verilog-insert-indent "// Beginning of automatic wires (for undeclared instantiated-module outputs)\n") | |
8495 (verilog-insert-definition sig-list "wire" indent-pt nil) | |
8496 (verilog-modi-cache-add-wires modi sig-list) | |
8497 (verilog-insert-indent "// End of automatics\n") | |
8498 (when nil ;; Too slow on huge modules, plus makes everyone's module change | |
8499 (beginning-of-line) | |
8500 (setq pnt (point)) | |
8501 (verilog-pretty-declarations) | |
8502 (goto-char pnt) | |
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8503 (verilog-pretty-expr "//")))))) |
79545 | 8504 |
8505 (defun verilog-auto-output () | |
8506 "Expand AUTOOUTPUT statements, as part of \\[verilog-auto]. | |
8507 Make output statements for any output signal from an /*AUTOINST*/ that | |
8508 isn't a input to another AUTOINST. This is useful for modules which | |
8509 only instantiate other modules. | |
8510 | |
8511 Limitations: | |
8512 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls'). | |
8513 | |
8514 If placed inside the parenthesis of a module declaration, it creates | |
8515 Verilog 2001 style, else uses Verilog 1995 style. | |
8516 | |
8517 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's | |
8518 instantiation, all bets are off. (For example due to a AUTO_TEMPLATE). | |
8519 | |
8520 Typedefs must match `verilog-typedef-regexp', which is disabled by default. | |
8521 | |
8522 Signals matching `verilog-auto-output-ignore-regexp' are not included. | |
8523 | |
8524 An example (see `verilog-auto-inst' for what else is going on here): | |
8525 | |
8526 module ex_output (ov,i) | |
8527 input i; | |
8528 /*AUTOOUTPUT*/ | |
8529 inst inst (/*AUTOINST*/); | |
8530 endmodule | |
8531 | |
8532 Typing \\[verilog-auto] will make this into: | |
8533 | |
8534 module ex_output (ov,i) | |
8535 input i; | |
8536 /*AUTOOUTPUT*/ | |
8537 // Beginning of automatic outputs (from unused autoinst outputs) | |
8538 output [31:0] ov; // From inst of inst.v | |
8539 // End of automatics | |
8540 inst inst (/*AUTOINST*/ | |
8541 // Outputs | |
8542 .ov (ov[31:0]), | |
8543 // Inputs | |
8544 .i (i)); | |
8545 endmodule" | |
8546 (save-excursion | |
8547 ;; Point must be at insertion point. | |
8548 (let* ((indent-pt (current-indentation)) | |
8549 (v2k (verilog-in-paren)) | |
8550 (modi (verilog-modi-current)) | |
8551 (sig-list (verilog-signals-not-in | |
8552 (verilog-modi-get-sub-outputs modi) | |
8553 (append (verilog-modi-get-outputs modi) | |
8554 (verilog-modi-get-inouts modi) | |
8555 (verilog-modi-get-sub-inputs modi) | |
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8556 (verilog-modi-get-sub-inouts modi))))) |
79545 | 8557 (setq sig-list (verilog-signals-not-matching-regexp |
8558 sig-list verilog-auto-output-ignore-regexp)) | |
8559 (forward-line 1) | |
8560 (when v2k (verilog-repair-open-comma)) | |
8561 (when sig-list | |
8562 (verilog-insert-indent "// Beginning of automatic outputs (from unused autoinst outputs)\n") | |
8563 (verilog-insert-definition sig-list "output" indent-pt v2k) | |
8564 (verilog-modi-cache-add-outputs modi sig-list) | |
8565 (verilog-insert-indent "// End of automatics\n")) | |
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8566 (when v2k (verilog-repair-close-comma))))) |
79545 | 8567 |
8568 (defun verilog-auto-output-every () | |
8569 "Expand AUTOOUTPUTEVERY statements, as part of \\[verilog-auto]. | |
8570 Make output statements for any signals that aren't primary inputs or | |
8571 outputs already. This makes every signal in the design a output. This is | |
8572 useful to get Synopsys to preserve every signal in the design, since it | |
8573 won't optimize away the outputs. | |
8574 | |
8575 An example: | |
8576 | |
8577 module ex_output_every (o,i,tempa,tempb) | |
8578 output o; | |
8579 input i; | |
8580 /*AUTOOUTPUTEVERY*/ | |
8581 wire tempa = i; | |
8582 wire tempb = tempa; | |
8583 wire o = tempb; | |
8584 endmodule | |
8585 | |
8586 Typing \\[verilog-auto] will make this into: | |
8587 | |
8588 module ex_output_every (o,i,tempa,tempb) | |
8589 output o; | |
8590 input i; | |
8591 /*AUTOOUTPUTEVERY*/ | |
8592 // Beginning of automatic outputs (every signal) | |
8593 output tempb; | |
8594 output tempa; | |
8595 // End of automatics | |
8596 wire tempa = i; | |
8597 wire tempb = tempa; | |
8598 wire o = tempb; | |
8599 endmodule" | |
8600 (save-excursion | |
8601 ;;Point must be at insertion point | |
8602 (let* ((indent-pt (current-indentation)) | |
8603 (v2k (verilog-in-paren)) | |
8604 (modi (verilog-modi-current)) | |
8605 (sig-list (verilog-signals-combine-bus | |
8606 (verilog-signals-not-in | |
8607 (verilog-modi-get-signals modi) | |
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8608 (verilog-modi-get-ports modi))))) |
79545 | 8609 (forward-line 1) |
8610 (when v2k (verilog-repair-open-comma)) | |
8611 (when sig-list | |
8612 (verilog-insert-indent "// Beginning of automatic outputs (every signal)\n") | |
8613 (verilog-insert-definition sig-list "output" indent-pt v2k) | |
8614 (verilog-modi-cache-add-outputs modi sig-list) | |
8615 (verilog-insert-indent "// End of automatics\n")) | |
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8616 (when v2k (verilog-repair-close-comma))))) |
79545 | 8617 |
8618 (defun verilog-auto-input () | |
8619 "Expand AUTOINPUT statements, as part of \\[verilog-auto]. | |
8620 Make input statements for any input signal into an /*AUTOINST*/ that | |
8621 isn't declared elsewhere inside the module. This is useful for modules which | |
8622 only instantiate other modules. | |
8623 | |
8624 Limitations: | |
8625 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls'). | |
8626 | |
8627 If placed inside the parenthesis of a module declaration, it creates | |
8628 Verilog 2001 style, else uses Verilog 1995 style. | |
8629 | |
8630 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's | |
8631 instantiation, all bets are off. (For example due to a AUTO_TEMPLATE). | |
8632 | |
8633 Typedefs must match `verilog-typedef-regexp', which is disabled by default. | |
8634 | |
8635 Signals matching `verilog-auto-input-ignore-regexp' are not included. | |
8636 | |
8637 An example (see `verilog-auto-inst' for what else is going on here): | |
8638 | |
8639 module ex_input (ov,i) | |
8640 output [31:0] ov; | |
8641 /*AUTOINPUT*/ | |
8642 inst inst (/*AUTOINST*/); | |
8643 endmodule | |
8644 | |
8645 Typing \\[verilog-auto] will make this into: | |
8646 | |
8647 module ex_input (ov,i) | |
8648 output [31:0] ov; | |
8649 /*AUTOINPUT*/ | |
8650 // Beginning of automatic inputs (from unused autoinst inputs) | |
8651 input i; // From inst of inst.v | |
8652 // End of automatics | |
8653 inst inst (/*AUTOINST*/ | |
8654 // Outputs | |
8655 .ov (ov[31:0]), | |
8656 // Inputs | |
8657 .i (i)); | |
8658 endmodule" | |
8659 (save-excursion | |
8660 (let* ((indent-pt (current-indentation)) | |
8661 (v2k (verilog-in-paren)) | |
8662 (modi (verilog-modi-current)) | |
8663 (sig-list (verilog-signals-not-in | |
8664 (verilog-modi-get-sub-inputs modi) | |
8665 (append (verilog-modi-get-inputs modi) | |
8666 (verilog-modi-get-inouts modi) | |
8667 (verilog-modi-get-wires modi) | |
8668 (verilog-modi-get-regs modi) | |
8669 (verilog-modi-get-consts modi) | |
8670 (verilog-modi-get-gparams modi) | |
8671 (verilog-modi-get-sub-outputs modi) | |
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8672 (verilog-modi-get-sub-inouts modi))))) |
79545 | 8673 (setq sig-list (verilog-signals-not-matching-regexp |
8674 sig-list verilog-auto-input-ignore-regexp)) | |
8675 (forward-line 1) | |
8676 (when v2k (verilog-repair-open-comma)) | |
8677 (when sig-list | |
8678 (verilog-insert-indent "// Beginning of automatic inputs (from unused autoinst inputs)\n") | |
8679 (verilog-insert-definition sig-list "input" indent-pt v2k) | |
8680 (verilog-modi-cache-add-inputs modi sig-list) | |
8681 (verilog-insert-indent "// End of automatics\n")) | |
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|
8682 (when v2k (verilog-repair-close-comma))))) |
79545 | 8683 |
8684 (defun verilog-auto-inout () | |
8685 "Expand AUTOINOUT statements, as part of \\[verilog-auto]. | |
8686 Make inout statements for any inout signal in an /*AUTOINST*/ that | |
8687 isn't declared elsewhere inside the module. | |
8688 | |
8689 Limitations: | |
8690 This ONLY detects outputs of AUTOINSTants (see `verilog-read-sub-decls'). | |
8691 | |
8692 If placed inside the parenthesis of a module declaration, it creates | |
8693 Verilog 2001 style, else uses Verilog 1995 style. | |
8694 | |
8695 If any concatenation, or bit-subscripts are missing in the AUTOINSTant's | |
8696 instantiation, all bets are off. (For example due to a AUTO_TEMPLATE). | |
8697 | |
8698 Typedefs must match `verilog-typedef-regexp', which is disabled by default. | |
8699 | |
8700 Signals matching `verilog-auto-inout-ignore-regexp' are not included. | |
8701 | |
8702 An example (see `verilog-auto-inst' for what else is going on here): | |
8703 | |
8704 module ex_inout (ov,i) | |
8705 input i; | |
8706 /*AUTOINOUT*/ | |
8707 inst inst (/*AUTOINST*/); | |
8708 endmodule | |
8709 | |
8710 Typing \\[verilog-auto] will make this into: | |
8711 | |
8712 module ex_inout (ov,i) | |
8713 input i; | |
8714 /*AUTOINOUT*/ | |
8715 // Beginning of automatic inouts (from unused autoinst inouts) | |
8716 inout [31:0] ov; // From inst of inst.v | |
8717 // End of automatics | |
8718 inst inst (/*AUTOINST*/ | |
8719 // Inouts | |
8720 .ov (ov[31:0]), | |
8721 // Inputs | |
8722 .i (i)); | |
8723 endmodule" | |
8724 (save-excursion | |
8725 ;; Point must be at insertion point. | |
8726 (let* ((indent-pt (current-indentation)) | |
8727 (v2k (verilog-in-paren)) | |
8728 (modi (verilog-modi-current)) | |
8729 (sig-list (verilog-signals-not-in | |
8730 (verilog-modi-get-sub-inouts modi) | |
8731 (append (verilog-modi-get-outputs modi) | |
8732 (verilog-modi-get-inouts modi) | |
8733 (verilog-modi-get-inputs modi) | |
8734 (verilog-modi-get-sub-inputs modi) | |
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8735 (verilog-modi-get-sub-outputs modi))))) |
79545 | 8736 (setq sig-list (verilog-signals-not-matching-regexp |
8737 sig-list verilog-auto-inout-ignore-regexp)) | |
8738 (forward-line 1) | |
8739 (when v2k (verilog-repair-open-comma)) | |
8740 (when sig-list | |
8741 (verilog-insert-indent "// Beginning of automatic inouts (from unused autoinst inouts)\n") | |
8742 (verilog-insert-definition sig-list "inout" indent-pt v2k) | |
8743 (verilog-modi-cache-add-inouts modi sig-list) | |
8744 (verilog-insert-indent "// End of automatics\n")) | |
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|
8745 (when v2k (verilog-repair-close-comma))))) |
79545 | 8746 |
8747 (defun verilog-auto-inout-module () | |
8748 "Expand AUTOINOUTMODULE statements, as part of \\[verilog-auto]. | |
8749 Take input/output/inout statements from the specified module and insert | |
8750 into the current module. This is useful for making null templates and | |
8751 shell modules which need to have identical I/O with another module. Any | |
8752 I/O which are already defined in this module will not be redefined. | |
8753 | |
8754 Limitations: | |
8755 If placed inside the parenthesis of a module declaration, it creates | |
8756 Verilog 2001 style, else uses Verilog 1995 style. | |
8757 | |
8758 Concatenation and outputting partial busses is not supported. | |
8759 | |
8760 Module names must be resolvable to filenames. See `verilog-auto-inst'. | |
8761 | |
8762 Signals are not inserted in the same order as in the original module, | |
8763 though they will appear to be in the same order to a AUTOINST | |
8764 instantiating either module. | |
8765 | |
8766 An example: | |
8767 | |
8768 module ex_shell (/*AUTOARG*/) | |
8769 /*AUTOINOUTMODULE(\"ex_main\")*/ | |
8770 endmodule | |
8771 | |
8772 module ex_main (i,o,io) | |
8773 input i; | |
8774 output o; | |
8775 inout io; | |
8776 endmodule | |
8777 | |
8778 Typing \\[verilog-auto] will make this into: | |
8779 | |
8780 module ex_shell (/*AUTOARG*/i,o,io) | |
8781 /*AUTOINOUTMODULE(\"ex_main\")*/ | |
8782 // Beginning of automatic in/out/inouts (from specific module) | |
8783 input i; | |
8784 output o; | |
8785 inout io; | |
8786 // End of automatics | |
8787 endmodule" | |
8788 (save-excursion | |
8789 (let* ((submod (car (verilog-read-auto-params 1))) submodi) | |
8790 ;; Lookup position, etc of co-module | |
8791 ;; Note this may raise an error | |
8792 (when (setq submodi (verilog-modi-lookup submod t)) | |
8793 (let* ((indent-pt (current-indentation)) | |
8794 (v2k (verilog-in-paren)) | |
8795 (modi (verilog-modi-current)) | |
8796 (sig-list-i (verilog-signals-not-in | |
8797 (verilog-modi-get-inputs submodi) | |
8798 (append (verilog-modi-get-inputs modi)))) | |
8799 (sig-list-o (verilog-signals-not-in | |
8800 (verilog-modi-get-outputs submodi) | |
8801 (append (verilog-modi-get-outputs modi)))) | |
8802 (sig-list-io (verilog-signals-not-in | |
8803 (verilog-modi-get-inouts submodi) | |
8804 (append (verilog-modi-get-inouts modi))))) | |
8805 (forward-line 1) | |
8806 (when v2k (verilog-repair-open-comma)) | |
8807 (when (or sig-list-i sig-list-o sig-list-io) | |
8808 (verilog-insert-indent "// Beginning of automatic in/out/inouts (from specific module)\n") | |
8809 ;; Don't sort them so a upper AUTOINST will match the main module | |
8810 (verilog-insert-definition sig-list-o "output" indent-pt v2k t) | |
8811 (verilog-insert-definition sig-list-io "inout" indent-pt v2k t) | |
8812 (verilog-insert-definition sig-list-i "input" indent-pt v2k t) | |
8813 (verilog-modi-cache-add-inputs modi sig-list-i) | |
8814 (verilog-modi-cache-add-outputs modi sig-list-o) | |
8815 (verilog-modi-cache-add-inouts modi sig-list-io) | |
8816 (verilog-insert-indent "// End of automatics\n")) | |
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8817 (when v2k (verilog-repair-close-comma))))))) |
79545 | 8818 |
8819 (defun verilog-auto-sense-sigs (modi presense-sigs) | |
8820 "Return list of signals for current AUTOSENSE block." | |
8821 (let* ((sigss (verilog-read-always-signals)) | |
8822 (sig-list (verilog-signals-not-params | |
8823 (verilog-signals-not-in (verilog-alw-get-inputs sigss) | |
8824 (append (and (not verilog-auto-sense-include-inputs) | |
8825 (verilog-alw-get-outputs sigss)) | |
8826 (verilog-modi-get-consts modi) | |
8827 (verilog-modi-get-gparams modi) | |
8828 presense-sigs))))) | |
8829 sig-list)) | |
8830 | |
8831 (defun verilog-auto-sense () | |
8832 "Expand AUTOSENSE statements, as part of \\[verilog-auto]. | |
8833 Replace the always (/*AUTOSENSE*/) sensitivity list (/*AS*/ for short) | |
8834 with one automatically derived from all inputs declared in the always | |
8835 statement. Signals that are generated within the same always block are NOT | |
8836 placed into the sensitivity list (see `verilog-auto-sense-include-inputs'). | |
8837 Long lines are split based on the `fill-column', see \\[set-fill-column]. | |
8838 | |
8839 Limitations: | |
8840 Verilog does not allow memories (multidimensional arrays) in sensitivity | |
8841 lists. AUTOSENSE will thus exclude them, and add a /*memory or*/ comment. | |
8842 | |
8843 Constant signals: | |
8844 AUTOSENSE cannot always determine if a `define is a constant or a signal | |
8845 (it could be in a include file for example). If a `define or other signal | |
8846 is put into the AUTOSENSE list and is not desired, use the AUTO_CONSTANT | |
8847 declaration anywhere in the module (parenthesis are required): | |
8848 | |
8849 /* AUTO_CONSTANT ( `this_is_really_constant_dont_autosense_it ) */ | |
8850 | |
8851 Better yet, use a parameter, which will be understood to be constant | |
8852 automatically. | |
8853 | |
8854 OOps! | |
8855 If AUTOSENSE makes a mistake, please report it. (First try putting | |
8856 a begin/end after your always!) As a workaround, if a signal that | |
8857 shouldn't be in the sensitivity list was, use the AUTO_CONSTANT above. | |
8858 If a signal should be in the sensitivity list wasn't, placing it before | |
8859 the /*AUTOSENSE*/ comment will prevent it from being deleted when the | |
8860 autos are updated (or added if it occurs there already). | |
8861 | |
8862 An example: | |
8863 | |
8864 always @ (/*AUTOSENSE*/) begin | |
8865 /* AUTO_CONSTANT (`constant) */ | |
8866 outin = ina | inb | `constant; | |
8867 out = outin; | |
8868 end | |
8869 | |
8870 Typing \\[verilog-auto] will make this into: | |
8871 | |
8872 always @ (/*AUTOSENSE*/ina or inb) begin | |
8873 /* AUTO_CONSTANT (`constant) */ | |
8874 outin = ina | inb | `constant; | |
8875 out = outin; | |
8876 end" | |
8877 (save-excursion | |
8878 ;; Find beginning | |
8879 (let* ((start-pt (save-excursion | |
8880 (verilog-re-search-backward "(" nil t) | |
8881 (point))) | |
8882 (indent-pt (save-excursion | |
8883 (or (and (goto-char start-pt) (1+ (current-column))) | |
8884 (current-indentation)))) | |
8885 (modi (verilog-modi-current)) | |
8886 (sig-memories (verilog-signals-memory | |
8887 (append | |
8888 (verilog-modi-get-regs modi) | |
8889 (verilog-modi-get-wires modi)))) | |
8890 sig-list not-first presense-sigs) | |
8891 ;; Read signals in always, eliminate outputs from sense list | |
8892 (setq presense-sigs (verilog-signals-from-signame | |
8893 (save-excursion | |
8894 (verilog-read-signals start-pt (point))))) | |
8895 (setq sig-list (verilog-auto-sense-sigs modi presense-sigs)) | |
8896 (when sig-memories | |
8897 (let ((tlen (length sig-list))) | |
8898 (setq sig-list (verilog-signals-not-in sig-list sig-memories)) | |
8899 (if (not (eq tlen (length sig-list))) (insert " /*memory or*/ ")))) | |
8900 (if (and presense-sigs ;; Add a "or" if not "(.... or /*AUTOSENSE*/" | |
8901 (save-excursion (goto-char (point)) | |
8902 (verilog-re-search-backward "[a-zA-Z0-9$_.%`]+" start-pt t) | |
8903 (verilog-re-search-backward "\\s-" start-pt t) | |
8904 (while (looking-at "\\s-`endif") | |
8905 (verilog-re-search-backward "[a-zA-Z0-9$_.%`]+" start-pt t) | |
8906 (verilog-re-search-backward "\\s-" start-pt t)) | |
8907 (not (looking-at "\\s-or\\b")))) | |
8908 (setq not-first t)) | |
8909 (setq sig-list (sort sig-list `verilog-signals-sort-compare)) | |
8910 (while sig-list | |
8911 (cond ((> (+ 4 (current-column) (length (verilog-sig-name (car sig-list)))) fill-column) ;+4 for width of or | |
8912 (insert "\n") | |
8913 (indent-to indent-pt) | |
8914 (if not-first (insert "or "))) | |
8915 (not-first (insert " or "))) | |
8916 (insert (verilog-sig-name (car sig-list))) | |
8917 (setq sig-list (cdr sig-list) | |
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|
8918 not-first t))))) |
79545 | 8919 |
8920 (defun verilog-auto-reset () | |
8921 "Expand AUTORESET statements, as part of \\[verilog-auto]. | |
8922 Replace the /*AUTORESET*/ comment with code to initialize all | |
8923 registers set elsewhere in the always block. | |
8924 | |
8925 Limitations: | |
8926 AUTORESET will not clear memories. | |
8927 | |
8928 AUTORESET uses <= if there are any <= in the block, else it uses =. | |
8929 | |
8930 /*AUTORESET*/ presumes that any signals mentioned between the previous | |
8931 begin/case/if statement and the AUTORESET comment are being reset manually | |
8932 and should not be automatically reset. This includes omitting any signals | |
8933 used on the right hand side of assignments. | |
8934 | |
8935 By default, AUTORESET will include the width of the signal in the autos, | |
8936 this is a recent change. To control this behavior, see | |
8937 `verilog-auto-reset-widths'. | |
8938 | |
8939 AUTORESET ties signals to deasserted, which is presumed to be zero. | |
8940 Signals that match `verilog-active-low-regexp' will be deasserted by tieing | |
8941 them to a one. | |
8942 | |
8943 An example: | |
8944 | |
8945 always @(posedge clk or negedge reset_l) begin | |
8946 if (!reset_l) begin | |
8947 c <= 1; | |
8948 /*AUTORESET*/ | |
8949 end | |
8950 else begin | |
8951 a <= in_a; | |
8952 b <= in_b; | |
8953 c <= in_c; | |
8954 end | |
8955 end | |
8956 | |
8957 Typing \\[verilog-auto] will make this into: | |
8958 | |
8959 always @(posedge core_clk or negedge reset_l) begin | |
8960 if (!reset_l) begin | |
8961 c <= 1; | |
8962 /*AUTORESET*/ | |
8963 // Beginning of autoreset for uninitialized flops | |
8964 a <= 0; | |
8965 b <= 0; | |
8966 // End of automatics | |
8967 end | |
8968 else begin | |
8969 a <= in_a; | |
8970 b <= in_b; | |
8971 c <= in_c; | |
8972 end | |
8973 end" | |
8974 | |
8975 (interactive) | |
8976 (save-excursion | |
8977 ;; Find beginning | |
8978 (let* ((indent-pt (current-indentation)) | |
8979 (modi (verilog-modi-current)) | |
8980 (all-list (verilog-modi-get-signals modi)) | |
8981 sigss sig-list prereset-sigs assignment-str) | |
8982 ;; Read signals in always, eliminate outputs from reset list | |
8983 (setq prereset-sigs (verilog-signals-from-signame | |
8984 (save-excursion | |
8985 (verilog-read-signals | |
8986 (save-excursion | |
8987 (verilog-re-search-backward "\\(@\\|\\<begin\\>\\|\\<if\\>\\|\\<case\\>\\)" nil t) | |
8988 (point)) | |
8989 (point))))) | |
8990 (save-excursion | |
8991 (verilog-re-search-backward "@" nil t) | |
8992 (setq sigss (verilog-read-always-signals))) | |
8993 (setq assignment-str (if (verilog-alw-get-uses-delayed sigss) | |
8994 (concat " <= " verilog-assignment-delay) | |
8995 " = ")) | |
8996 (setq sig-list (verilog-signals-not-in (verilog-alw-get-outputs sigss) | |
8997 prereset-sigs)) | |
8998 (setq sig-list (sort sig-list `verilog-signals-sort-compare)) | |
8999 (when sig-list | |
9000 (insert "\n"); | |
9001 (indent-to indent-pt) | |
9002 (insert "// Beginning of autoreset for uninitialized flops\n"); | |
9003 (indent-to indent-pt) | |
9004 (while sig-list | |
9005 (let ((sig (or (assoc (verilog-sig-name (car sig-list)) all-list) ;; As sig-list has no widths | |
9006 (car sig-list)))) | |
9007 (insert (verilog-sig-name sig) | |
9008 assignment-str | |
9009 (verilog-sig-tieoff sig (not verilog-auto-reset-widths)) | |
9010 ";\n") | |
9011 (indent-to indent-pt) | |
9012 (setq sig-list (cdr sig-list)))) | |
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|
9013 (insert "// End of automatics"))))) |
79545 | 9014 |
9015 (defun verilog-auto-tieoff () | |
9016 "Expand AUTOTIEOFF statements, as part of \\[verilog-auto]. | |
9017 Replace the /*AUTOTIEOFF*/ comment with code to wire-tie all unused output | |
9018 signals to deasserted. | |
9019 | |
9020 /*AUTOTIEOFF*/ is used to make stub modules; modules that have the same | |
9021 input/output list as another module, but no internals. Specifically, it | |
9022 finds all outputs in the module, and if that input is not otherwise declared | |
9023 as a register or wire, creates a tieoff. | |
9024 | |
9025 AUTORESET ties signals to deasserted, which is presumed to be zero. | |
9026 Signals that match `verilog-active-low-regexp' will be deasserted by tieing | |
9027 them to a one. | |
9028 | |
9029 An example of making a stub for another module: | |
9030 | |
9031 module FooStub (/*AUTOINST*/); | |
9032 /*AUTOINOUTMODULE(\"Foo\")*/ | |
9033 /*AUTOTIEOFF*/ | |
9034 // verilator lint_off UNUSED | |
9035 wire _unused_ok = &{1'b0, | |
9036 /*AUTOUNUSED*/ | |
9037 1'b0}; | |
9038 // verilator lint_on UNUSED | |
9039 endmodule | |
9040 | |
9041 Typing \\[verilog-auto] will make this into: | |
9042 | |
9043 module FooStub (/*AUTOINST*/...); | |
9044 /*AUTOINOUTMODULE(\"Foo\")*/ | |
9045 // Beginning of autotieoff | |
9046 output [2:0] foo; | |
9047 // End of automatics | |
9048 | |
9049 /*AUTOTIEOFF*/ | |
9050 // Beginning of autotieoff | |
9051 wire [2:0] foo = 3'b0; | |
9052 // End of automatics | |
9053 ... | |
9054 endmodule" | |
9055 (interactive) | |
9056 (save-excursion | |
9057 ;; Find beginning | |
9058 (let* ((indent-pt (current-indentation)) | |
9059 (modi (verilog-modi-current)) | |
9060 (sig-list (verilog-signals-not-in | |
9061 (verilog-modi-get-outputs modi) | |
9062 (append (verilog-modi-get-wires modi) | |
9063 (verilog-modi-get-regs modi) | |
9064 (verilog-modi-get-assigns modi) | |
9065 (verilog-modi-get-consts modi) | |
9066 (verilog-modi-get-gparams modi) | |
9067 (verilog-modi-get-sub-outputs modi) | |
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diff
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|
9068 (verilog-modi-get-sub-inouts modi))))) |
79545 | 9069 (when sig-list |
9070 (forward-line 1) | |
9071 (verilog-insert-indent "// Beginning of automatic tieoffs (for this module's unterminated outputs)\n") | |
9072 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare)) | |
9073 (verilog-modi-cache-add-wires modi sig-list) ; Before we trash list | |
9074 (while sig-list | |
9075 (let ((sig (car sig-list))) | |
9076 (verilog-insert-one-definition sig "wire" indent-pt) | |
9077 (indent-to (max 48 (+ indent-pt 40))) | |
9078 (insert "= " (verilog-sig-tieoff sig) | |
9079 ";\n") | |
9080 (setq sig-list (cdr sig-list)))) | |
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|
9081 (verilog-insert-indent "// End of automatics\n"))))) |
79545 | 9082 |
9083 (defun verilog-auto-unused () | |
9084 "Expand AUTOUNUSED statements, as part of \\[verilog-auto]. | |
9085 Replace the /*AUTOUNUSED*/ comment with a comma separated list of all unused | |
9086 input and inout signals. | |
9087 | |
9088 /*AUTOUNUSED*/ is used to make stub modules; modules that have the same | |
9089 input/output list as another module, but no internals. Specifically, it | |
9090 finds all inputs and inouts in the module, and if that input is not otherwise | |
9091 used, adds it to a comma separated list. | |
9092 | |
9093 The comma separated list is intended to be used to create a _unused_ok | |
9094 signal. Using the exact name \"_unused_ok\" for name of the temporary | |
9095 signal is recommended as it will insure maximum forward compatibility, it | |
9096 also makes lint warnings easy to understand; ignore any unused warnings | |
9097 with \"unused\" in the signal name. | |
9098 | |
9099 To reduce simulation time, the _unused_ok signal should be forced to a | |
9100 constant to prevent wiggling. The easiest thing to do is use a | |
9101 reduction-and with 1'b0 as shown. | |
9102 | |
9103 This way all unused signals are in one place, making it convenient to add | |
9104 your tool's specific pragmas around the assignment to disable any unused | |
9105 warnings. | |
9106 | |
9107 You can add signals you do not want included in AUTOUNUSED with | |
9108 `verilog-auto-unused-ignore-regexp'. | |
9109 | |
9110 An example of making a stub for another module: | |
9111 | |
9112 module FooStub (/*AUTOINST*/); | |
9113 /*AUTOINOUTMODULE(\"Foo\")*/ | |
9114 /*AUTOTIEOFF*/ | |
9115 // verilator lint_off UNUSED | |
9116 wire _unused_ok = &{1'b0, | |
9117 /*AUTOUNUSED*/ | |
9118 1'b0}; | |
9119 // verilator lint_on UNUSED | |
9120 endmodule | |
9121 | |
9122 Typing \\[verilog-auto] will make this into: | |
9123 | |
9124 ... | |
9125 // verilator lint_off UNUSED | |
9126 wire _unused_ok = &{1'b0, | |
9127 /*AUTOUNUSED*/ | |
9128 // Beginning of automatics | |
9129 unused_input_a, | |
9130 unused_input_b, | |
9131 unused_input_c, | |
9132 // End of automatics | |
9133 1'b0}; | |
9134 // verilator lint_on UNUSED | |
9135 endmodule" | |
9136 (interactive) | |
9137 (save-excursion | |
9138 ;; Find beginning | |
9139 (let* ((indent-pt (progn (search-backward "/*") (current-column))) | |
9140 (modi (verilog-modi-current)) | |
9141 (sig-list (verilog-signals-not-in | |
9142 (append (verilog-modi-get-inputs modi) | |
9143 (verilog-modi-get-inouts modi)) | |
9144 (append (verilog-modi-get-sub-inputs modi) | |
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|
9145 (verilog-modi-get-sub-inouts modi))))) |
79545 | 9146 (setq sig-list (verilog-signals-not-matching-regexp |
9147 sig-list verilog-auto-unused-ignore-regexp)) | |
9148 (when sig-list | |
9149 (forward-line 1) | |
9150 (verilog-insert-indent "// Beginning of automatic unused inputs\n") | |
9151 (setq sig-list (sort (copy-alist sig-list) `verilog-signals-sort-compare)) | |
9152 (while sig-list | |
9153 (let ((sig (car sig-list))) | |
9154 (indent-to indent-pt) | |
9155 (insert (verilog-sig-name sig) ",\n") | |
9156 (setq sig-list (cdr sig-list)))) | |
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|
9157 (verilog-insert-indent "// End of automatics\n"))))) |
79545 | 9158 |
9159 (defun verilog-enum-ascii (signm elim-regexp) | |
9160 "Convert a enum name SIGNM to a ascii string for insertion. | |
9161 Remove user provided prefix ELIM-REGEXP." | |
9162 (or elim-regexp (setq elim-regexp "_ DONT MATCH IT_")) | |
9163 (let ((case-fold-search t)) | |
9164 ;; All upper becomes all lower for readability | |
9165 (downcase (verilog-string-replace-matches elim-regexp "" nil nil signm)))) | |
9166 | |
9167 (defun verilog-auto-ascii-enum () | |
9168 "Expand AUTOASCIIENUM statements, as part of \\[verilog-auto]. | |
9169 Create a register to contain the ASCII decode of a enumerated signal type. | |
9170 This will allow trace viewers to show the ASCII name of states. | |
9171 | |
9172 First, parameters are built into a enumeration using the synopsys enum | |
9173 comment. The comment must be between the keyword and the symbol. | |
79546 | 9174 \(Annoying, but that's what Synopsys's dc_shell FSM reader requires.) |
79545 | 9175 |
9176 Next, registers which that enum applies to are also tagged with the same | |
9177 enum. Synopsys also suggests labeling state vectors, but `verilog-mode' | |
9178 doesn't care. | |
9179 | |
9180 Finally, a AUTOASCIIENUM command is used. | |
9181 | |
9182 The first parameter is the name of the signal to be decoded. | |
9183 | |
9184 The second parameter is the name to store the ASCII code into. For the | |
9185 signal foo, I suggest the name _foo__ascii, where the leading _ indicates | |
9186 a signal that is just for simulation, and the magic characters _ascii | |
9187 tell viewers like Dinotrace to display in ASCII format. | |
9188 | |
9189 The final optional parameter is a string which will be removed from the | |
9190 state names. | |
9191 | |
9192 An example: | |
9193 | |
9194 //== State enumeration | |
9195 parameter [2:0] // synopsys enum state_info | |
9196 SM_IDLE = 3'b000, | |
9197 SM_SEND = 3'b001, | |
9198 SM_WAIT1 = 3'b010; | |
9199 //== State variables | |
9200 reg [2:0] /* synopsys enum state_info */ | |
9201 state_r; /* synopsys state_vector state_r */ | |
9202 reg [2:0] /* synopsys enum state_info */ | |
9203 state_e1; | |
9204 | |
9205 //== ASCII state decoding | |
9206 | |
9207 /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/ | |
9208 | |
9209 Typing \\[verilog-auto] will make this into: | |
9210 | |
9211 ... same front matter ... | |
9212 | |
9213 /*AUTOASCIIENUM(\"state_r\", \"state_ascii_r\", \"SM_\")*/ | |
9214 // Beginning of automatic ASCII enum decoding | |
9215 reg [39:0] state_ascii_r; // Decode of state_r | |
9216 always @(state_r) begin | |
9217 case ({state_r}) | |
9218 SM_IDLE: state_ascii_r = \"idle \"; | |
9219 SM_SEND: state_ascii_r = \"send \"; | |
9220 SM_WAIT1: state_ascii_r = \"wait1\"; | |
9221 default: state_ascii_r = \"%Erro\"; | |
9222 endcase | |
9223 end | |
9224 // End of automatics" | |
9225 (save-excursion | |
9226 (let* ((params (verilog-read-auto-params 2 3)) | |
9227 (undecode-name (nth 0 params)) | |
9228 (ascii-name (nth 1 params)) | |
9229 (elim-regexp (nth 2 params)) | |
9230 ;; | |
9231 (indent-pt (current-indentation)) | |
9232 (modi (verilog-modi-current)) | |
9233 ;; | |
9234 (sig-list-consts (append (verilog-modi-get-consts modi) | |
9235 (verilog-modi-get-gparams modi))) | |
9236 (sig-list-all (append (verilog-modi-get-regs modi) | |
9237 (verilog-modi-get-outputs modi) | |
9238 (verilog-modi-get-inouts modi) | |
9239 (verilog-modi-get-inputs modi) | |
9240 (verilog-modi-get-wires modi))) | |
9241 ;; | |
9242 (undecode-sig (or (assoc undecode-name sig-list-all) | |
9243 (error "%s: Signal %s not found in design" (verilog-point-text) undecode-name))) | |
9244 (undecode-enum (or (verilog-sig-enum undecode-sig) | |
9245 (error "%s: Signal %s does not have a enum tag" (verilog-point-text) undecode-name))) | |
9246 ;; | |
9247 (enum-sigs (or (verilog-signals-matching-enum sig-list-consts undecode-enum) | |
9248 (error "%s: No state definitions for %s" (verilog-point-text) undecode-enum))) | |
9249 ;; | |
9250 (enum-chars 0) | |
9251 (ascii-chars 0)) | |
9252 ;; | |
9253 ;; Find number of ascii chars needed | |
9254 (let ((tmp-sigs enum-sigs)) | |
9255 (while tmp-sigs | |
9256 (setq enum-chars (max enum-chars (length (verilog-sig-name (car tmp-sigs)))) | |
9257 ascii-chars (max ascii-chars (length (verilog-enum-ascii | |
9258 (verilog-sig-name (car tmp-sigs)) | |
9259 elim-regexp))) | |
9260 tmp-sigs (cdr tmp-sigs)))) | |
9261 ;; | |
9262 (forward-line 1) | |
9263 (verilog-insert-indent "// Beginning of automatic ASCII enum decoding\n") | |
9264 (let ((decode-sig-list (list (list ascii-name (format "[%d:0]" (- (* ascii-chars 8) 1)) | |
9265 (concat "Decode of " undecode-name) nil nil)))) | |
9266 (verilog-insert-definition decode-sig-list "reg" indent-pt nil) | |
9267 (verilog-modi-cache-add-regs modi decode-sig-list)) | |
9268 ;; | |
9269 (verilog-insert-indent "always @(" undecode-name ") begin\n") | |
9270 (setq indent-pt (+ indent-pt verilog-indent-level)) | |
9271 (indent-to indent-pt) | |
9272 (insert "case ({" undecode-name "})\n") | |
9273 (setq indent-pt (+ indent-pt verilog-case-indent)) | |
9274 ;; | |
9275 (let ((tmp-sigs enum-sigs) | |
9276 (chrfmt (format "%%-%ds %s = \"%%-%ds\";\n" (1+ (max 8 enum-chars)) | |
9277 ascii-name ascii-chars)) | |
9278 (errname (substring "%Error" 0 (min 6 ascii-chars)))) | |
9279 (while tmp-sigs | |
9280 (verilog-insert-indent | |
9281 (format chrfmt (concat (verilog-sig-name (car tmp-sigs)) ":") | |
9282 (verilog-enum-ascii (verilog-sig-name (car tmp-sigs)) | |
9283 elim-regexp))) | |
9284 (setq tmp-sigs (cdr tmp-sigs))) | |
9285 (verilog-insert-indent (format chrfmt "default:" errname))) | |
9286 ;; | |
9287 (setq indent-pt (- indent-pt verilog-case-indent)) | |
9288 (verilog-insert-indent "endcase\n") | |
9289 (setq indent-pt (- indent-pt verilog-indent-level)) | |
9290 (verilog-insert-indent "end\n" | |
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diff
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|
9291 "// End of automatics\n")))) |
79545 | 9292 |
9293 (defun verilog-auto-templated-rel () | |
9294 "Replace Templated relative line numbers with absolute line numbers. | |
9295 Internal use only. This hacks around the line numbers in AUTOINST Templates | |
9296 being different from the final output's line numbering." | |
9297 (let ((templateno 0) (template-line (list 0))) | |
9298 ;; Find line number each template is on | |
9299 (goto-char (point-min)) | |
9300 (while (search-forward "AUTO_TEMPLATE" nil t) | |
9301 (setq templateno (1+ templateno)) | |
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changeset
|
9302 (setq template-line |
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9303 (cons (count-lines (point-min) (point)) template-line))) |
79545 | 9304 (setq template-line (nreverse template-line)) |
9305 ;; Replace T# L# with absolute line number | |
9306 (goto-char (point-min)) | |
9307 (while (re-search-forward " Templated T\\([0-9]+\\) L\\([0-9]+\\)" nil t) | |
79691
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9308 (replace-match |
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9309 (concat " Templated " |
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9310 (int-to-string (+ (nth (string-to-number (match-string 1)) |
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9311 template-line) |
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9312 (string-to-number (match-string 2))))) |
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9313 t t)))) |
79545 | 9314 |
9315 | |
9316 ;; | |
9317 ;; Auto top level | |
9318 ;; | |
9319 | |
9320 (defun verilog-auto (&optional inject) ; Use verilog-inject-auto instead of passing a arg | |
9321 "Expand AUTO statements. | |
9322 Look for any /*AUTO...*/ commands in the code, as used in | |
9323 instantiations or argument headers. Update the list of signals | |
9324 following the /*AUTO...*/ command. | |
9325 | |
9326 Use \\[verilog-delete-auto] to remove the AUTOs. | |
9327 | |
9328 Use \\[verilog-inject-auto] to insert AUTOs for the first time. | |
9329 | |
9330 Use \\[verilog-faq] for a pointer to frequently asked questions. | |
9331 | |
9332 The hooks `verilog-before-auto-hook' and `verilog-auto-hook' are | |
9333 called before and after this function, respectively. | |
9334 | |
9335 For example: | |
9336 module (/*AUTOARG*/) | |
9337 /*AUTOINPUT*/ | |
9338 /*AUTOOUTPUT*/ | |
9339 /*AUTOWIRE*/ | |
9340 /*AUTOREG*/ | |
9341 somesub sub #(/*AUTOINSTPARAM*/) (/*AUTOINST*/); | |
9342 | |
9343 You can also update the AUTOs from the shell using: | |
9344 emacs --batch <filenames.v> -f verilog-batch-auto | |
9345 Or fix indentation with: | |
9346 emacs --batch <filenames.v> -f verilog-batch-indent | |
9347 Likewise, you can delete or inject AUTOs with: | |
9348 emacs --batch <filenames.v> -f verilog-batch-delete-auto | |
9349 emacs --batch <filenames.v> -f verilog-batch-inject-auto | |
9350 | |
9351 Using \\[describe-function], see also: | |
9352 `verilog-auto-arg' for AUTOARG module instantiations | |
9353 `verilog-auto-ascii-enum' for AUTOASCIIENUM enumeration decoding | |
9354 `verilog-auto-inout-module' for AUTOINOUTMODULE copying i/o from elsewhere | |
9355 `verilog-auto-inout' for AUTOINOUT making hierarchy inouts | |
9356 `verilog-auto-input' for AUTOINPUT making hierarchy inputs | |
9357 `verilog-auto-inst' for AUTOINST instantiation pins | |
9358 `verilog-auto-star' for AUTOINST .* SystemVerilog pins | |
9359 `verilog-auto-inst-param' for AUTOINSTPARAM instantiation params | |
9360 `verilog-auto-output' for AUTOOUTPUT making hierarchy outputs | |
9361 `verilog-auto-output-every' for AUTOOUTPUTEVERY making all outputs | |
9362 `verilog-auto-reg' for AUTOREG registers | |
9363 `verilog-auto-reg-input' for AUTOREGINPUT instantiation registers | |
9364 `verilog-auto-reset' for AUTORESET flop resets | |
9365 `verilog-auto-sense' for AUTOSENSE always sensitivity lists | |
9366 `verilog-auto-tieoff' for AUTOTIEOFF output tieoffs | |
9367 `verilog-auto-unused' for AUTOUNUSED unused inputs/inouts | |
9368 `verilog-auto-wire' for AUTOWIRE instantiation wires | |
9369 | |
9370 `verilog-read-defines' for reading `define values | |
9371 `verilog-read-includes' for reading `includes | |
9372 | |
9373 If you have bugs with these autos, try contacting the AUTOAUTHOR | |
9374 Wilson Snyder (wsnyder@wsnyder.org), and/or see http://www.veripool.com." | |
9375 (interactive) | |
9376 (unless noninteractive (message "Updating AUTOs...")) | |
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9377 (if (fboundp 'dinotrace-unannotate-all) |
79545 | 9378 (dinotrace-unannotate-all)) |
9379 (let ((oldbuf (if (not (buffer-modified-p)) | |
9380 (buffer-string))) | |
9381 ;; Before version 20, match-string with font-lock returns a | |
9382 ;; vector that is not equal to the string. IE if on "input" | |
9383 ;; nil==(equal "input" (progn (looking-at "input") (match-string 0))) | |
9384 (fontlocked (when (and (boundp 'font-lock-mode) | |
9385 font-lock-mode) | |
9386 (font-lock-mode nil) | |
9387 t))) | |
9388 (unwind-protect | |
9389 (save-excursion | |
9390 ;; If we're not in verilog-mode, change syntax table so parsing works right | |
9391 (unless (eq major-mode `verilog-mode) (verilog-mode)) | |
9392 ;; Allow user to customize | |
9393 (run-hooks 'verilog-before-auto-hook) | |
9394 ;; Try to save the user from needing to revert-file to reread file local-variables | |
9395 (verilog-auto-reeval-locals) | |
9396 (verilog-read-auto-lisp (point-min) (point-max)) | |
9397 (verilog-getopt-flags) | |
9398 ;; These two may seem obvious to do always, but on large includes it can be way too slow | |
9399 (when verilog-auto-read-includes | |
9400 (verilog-read-includes) | |
9401 (verilog-read-defines nil nil t)) | |
9402 ;; This particular ordering is important | |
9403 ;; INST: Lower modules correct, no internal dependencies, FIRST | |
9404 (verilog-preserve-cache | |
9405 ;; Clear existing autos else we'll be screwed by existing ones | |
9406 (verilog-delete-auto) | |
9407 ;; Injection if appropriate | |
9408 (when inject | |
9409 (verilog-inject-inst) | |
9410 (verilog-inject-sense) | |
9411 (verilog-inject-arg)) | |
9412 ;; | |
9413 (verilog-auto-search-do "/*AUTOINSTPARAM*/" 'verilog-auto-inst-param) | |
9414 (verilog-auto-search-do "/*AUTOINST*/" 'verilog-auto-inst) | |
9415 (verilog-auto-search-do ".*" 'verilog-auto-star) | |
9416 ;; Doesn't matter when done, but combine it with a common changer | |
9417 (verilog-auto-re-search-do "/\\*\\(AUTOSENSE\\|AS\\)\\*/" 'verilog-auto-sense) | |
9418 (verilog-auto-re-search-do "/\\*AUTORESET\\*/" 'verilog-auto-reset) | |
9419 ;; Must be done before autoin/out as creates a reg | |
9420 (verilog-auto-re-search-do "/\\*AUTOASCIIENUM([^)]*)\\*/" 'verilog-auto-ascii-enum) | |
9421 ;; | |
9422 ;; first in/outs from other files | |
9423 (verilog-auto-re-search-do "/\\*AUTOINOUTMODULE([^)]*)\\*/" 'verilog-auto-inout-module) | |
9424 ;; next in/outs which need previous sucked inputs first | |
9425 (verilog-auto-search-do "/*AUTOOUTPUT*/" 'verilog-auto-output) | |
9426 (verilog-auto-search-do "/*AUTOINPUT*/" 'verilog-auto-input) | |
9427 (verilog-auto-search-do "/*AUTOINOUT*/" 'verilog-auto-inout) | |
9428 ;; Then tie off those in/outs | |
9429 (verilog-auto-search-do "/*AUTOTIEOFF*/" 'verilog-auto-tieoff) | |
9430 ;; Wires/regs must be after inputs/outputs | |
9431 (verilog-auto-search-do "/*AUTOWIRE*/" 'verilog-auto-wire) | |
9432 (verilog-auto-search-do "/*AUTOREG*/" 'verilog-auto-reg) | |
9433 (verilog-auto-search-do "/*AUTOREGINPUT*/" 'verilog-auto-reg-input) | |
9434 ;; outputevery needs AUTOOUTPUTs done first | |
9435 (verilog-auto-search-do "/*AUTOOUTPUTEVERY*/" 'verilog-auto-output-every) | |
9436 ;; After we've created all new variables | |
9437 (verilog-auto-search-do "/*AUTOUNUSED*/" 'verilog-auto-unused) | |
9438 ;; Must be after all inputs outputs are generated | |
9439 (verilog-auto-search-do "/*AUTOARG*/" 'verilog-auto-arg) | |
9440 ;; Fix line numbers (comments only) | |
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9441 (verilog-auto-templated-rel)) |
79545 | 9442 ;; |
9443 (run-hooks 'verilog-auto-hook) | |
9444 ;; | |
9445 (set (make-local-variable 'verilog-auto-update-tick) (buffer-modified-tick)) | |
9446 ;; | |
9447 ;; If end result is same as when started, clear modified flag | |
9448 (cond ((and oldbuf (equal oldbuf (buffer-string))) | |
9449 (set-buffer-modified-p nil) | |
9450 (unless noninteractive (message "Updating AUTOs...done (no changes)"))) | |
9451 (t (unless noninteractive (message "Updating AUTOs...done"))))) | |
9452 ;; Unwind forms | |
9453 (progn | |
9454 ;; Restore font-lock | |
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9455 (when fontlocked (font-lock-mode t)))))) |
79545 | 9456 |
9457 | |
9458 ;; | |
9459 ;; Skeleton based code insertion | |
9460 ;; | |
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9461 (defvar verilog-template-map |
79546 | 9462 (let ((map (make-sparse-keymap))) |
9463 (define-key map "a" 'verilog-sk-always) | |
9464 (define-key map "b" 'verilog-sk-begin) | |
9465 (define-key map "c" 'verilog-sk-case) | |
9466 (define-key map "f" 'verilog-sk-for) | |
9467 (define-key map "g" 'verilog-sk-generate) | |
9468 (define-key map "h" 'verilog-sk-header) | |
9469 (define-key map "i" 'verilog-sk-initial) | |
9470 (define-key map "j" 'verilog-sk-fork) | |
9471 (define-key map "m" 'verilog-sk-module) | |
9472 (define-key map "p" 'verilog-sk-primitive) | |
9473 (define-key map "r" 'verilog-sk-repeat) | |
9474 (define-key map "s" 'verilog-sk-specify) | |
9475 (define-key map "t" 'verilog-sk-task) | |
9476 (define-key map "w" 'verilog-sk-while) | |
9477 (define-key map "x" 'verilog-sk-casex) | |
9478 (define-key map "z" 'verilog-sk-casez) | |
9479 (define-key map "?" 'verilog-sk-if) | |
9480 (define-key map ":" 'verilog-sk-else-if) | |
9481 (define-key map "/" 'verilog-sk-comment) | |
9482 (define-key map "A" 'verilog-sk-assign) | |
9483 (define-key map "F" 'verilog-sk-function) | |
9484 (define-key map "I" 'verilog-sk-input) | |
9485 (define-key map "O" 'verilog-sk-output) | |
9486 (define-key map "S" 'verilog-sk-state-machine) | |
9487 (define-key map "=" 'verilog-sk-inout) | |
9488 (define-key map "W" 'verilog-sk-wire) | |
9489 (define-key map "R" 'verilog-sk-reg) | |
79550
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9490 (define-key map "D" 'verilog-sk-define-signal) |
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|
9491 map) |
79545 | 9492 "Keymap used in Verilog mode for smart template operations.") |
9493 | |
9494 | |
9495 ;; | |
9496 ;; Place the templates into Verilog Mode. They may be inserted under any key. | |
9497 ;; C-c C-t will be the default. If you use templates a lot, you | |
9498 ;; may want to consider moving the binding to another key in your .emacs | |
9499 ;; file. | |
9500 ;; | |
9501 ;(define-key verilog-mode-map "\C-ct" verilog-template-map) | |
9502 (define-key verilog-mode-map "\C-c\C-t" verilog-template-map) | |
9503 | |
9504 ;;; ---- statement skeletons ------------------------------------------ | |
9505 | |
9506 (define-skeleton verilog-sk-prompt-condition | |
9507 "Prompt for the loop condition." | |
9508 "[condition]: " str ) | |
9509 | |
9510 (define-skeleton verilog-sk-prompt-init | |
9511 "Prompt for the loop init statement." | |
9512 "[initial statement]: " str ) | |
9513 | |
9514 (define-skeleton verilog-sk-prompt-inc | |
9515 "Prompt for the loop increment statement." | |
9516 "[increment statement]: " str ) | |
9517 | |
9518 (define-skeleton verilog-sk-prompt-name | |
9519 "Prompt for the name of something." | |
9520 "[name]: " str) | |
9521 | |
9522 (define-skeleton verilog-sk-prompt-clock | |
9523 "Prompt for the name of something." | |
9524 "name and edge of clock(s): " str) | |
9525 | |
9526 (defvar verilog-sk-reset nil) | |
9527 (defun verilog-sk-prompt-reset () | |
9528 "Prompt for the name of a state machine reset." | |
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9529 (setq verilog-sk-reset (read-string "name of reset: " "rst"))) |
79545 | 9530 |
9531 | |
9532 (define-skeleton verilog-sk-prompt-state-selector | |
9533 "Prompt for the name of a state machine selector." | |
9534 "name of selector (eg {a,b,c,d}): " str ) | |
9535 | |
9536 (define-skeleton verilog-sk-prompt-output | |
9537 "Prompt for the name of something." | |
9538 "output: " str) | |
9539 | |
9540 (define-skeleton verilog-sk-prompt-msb | |
9541 "Prompt for least significant bit specification." | |
9542 "msb:" str & ?: & (verilog-sk-prompt-lsb) | -1 ) | |
9543 | |
9544 (define-skeleton verilog-sk-prompt-lsb | |
9545 "Prompt for least significant bit specification." | |
9546 "lsb:" str ) | |
9547 | |
9548 (defvar verilog-sk-p nil) | |
9549 (define-skeleton verilog-sk-prompt-width | |
9550 "Prompt for a width specification." | |
9551 () | |
9552 (progn | |
9553 (setq verilog-sk-p (point)) | |
9554 (verilog-sk-prompt-msb) | |
9555 (if (> (point) verilog-sk-p) "] " " "))) | |
9556 | |
9557 (defun verilog-sk-header () | |
9558 "Insert a descriptive header at the top of the file." | |
9559 (interactive "*") | |
9560 (save-excursion | |
9561 (goto-char (point-min)) | |
9562 (verilog-sk-header-tmpl))) | |
9563 | |
9564 (define-skeleton verilog-sk-header-tmpl | |
9565 "Insert a comment block containing the module title, author, etc." | |
9566 "[Description]: " | |
9567 "// -*- Mode: Verilog -*-" | |
9568 "\n// Filename : " (buffer-name) | |
9569 "\n// Description : " str | |
9570 "\n// Author : " (user-full-name) | |
9571 "\n// Created On : " (current-time-string) | |
9572 "\n// Last Modified By: ." | |
9573 "\n// Last Modified On: ." | |
9574 "\n// Update Count : 0" | |
9575 "\n// Status : Unknown, Use with caution!" | |
9576 "\n") | |
9577 | |
9578 (define-skeleton verilog-sk-module | |
9579 "Insert a module definition." | |
9580 () | |
9581 > "module " (verilog-sk-prompt-name) " (/*AUTOARG*/ ) ;" \n | |
9582 > _ \n | |
9583 > (- verilog-indent-level-behavioral) "endmodule" (progn (electric-verilog-terminate-line) nil)) | |
9584 | |
9585 (define-skeleton verilog-sk-primitive | |
9586 "Insert a task definition." | |
9587 () | |
9588 > "primitive " (verilog-sk-prompt-name) " ( " (verilog-sk-prompt-output) ("input:" ", " str ) " );"\n | |
9589 > _ \n | |
9590 > (- verilog-indent-level-behavioral) "endprimitive" (progn (electric-verilog-terminate-line) nil)) | |
9591 | |
9592 (define-skeleton verilog-sk-task | |
9593 "Insert a task definition." | |
9594 () | |
9595 > "task " (verilog-sk-prompt-name) & ?; \n | |
9596 > _ \n | |
9597 > "begin" \n | |
9598 > \n | |
9599 > (- verilog-indent-level-behavioral) "end" \n | |
9600 > (- verilog-indent-level-behavioral) "endtask" (progn (electric-verilog-terminate-line) nil)) | |
9601 | |
9602 (define-skeleton verilog-sk-function | |
9603 "Insert a function definition." | |
9604 () | |
9605 > "function [" (verilog-sk-prompt-width) | -1 (verilog-sk-prompt-name) ?; \n | |
9606 > _ \n | |
9607 > "begin" \n | |
9608 > \n | |
9609 > (- verilog-indent-level-behavioral) "end" \n | |
9610 > (- verilog-indent-level-behavioral) "endfunction" (progn (electric-verilog-terminate-line) nil)) | |
9611 | |
9612 (define-skeleton verilog-sk-always | |
9613 "Insert always block. Uses the minibuffer to prompt | |
9614 for sensitivity list." | |
9615 () | |
9616 > "always @ ( /*AUTOSENSE*/ ) begin\n" | |
9617 > _ \n | |
9618 > (- verilog-indent-level-behavioral) "end" \n > | |
9619 ) | |
9620 | |
9621 (define-skeleton verilog-sk-initial | |
9622 "Insert an initial block." | |
9623 () | |
9624 > "initial begin\n" | |
9625 > _ \n | |
9626 > (- verilog-indent-level-behavioral) "end" \n > ) | |
9627 | |
9628 (define-skeleton verilog-sk-specify | |
9629 "Insert specify block. " | |
9630 () | |
9631 > "specify\n" | |
9632 > _ \n | |
9633 > (- verilog-indent-level-behavioral) "endspecify" \n > ) | |
9634 | |
9635 (define-skeleton verilog-sk-generate | |
9636 "Insert generate block. " | |
9637 () | |
9638 > "generate\n" | |
9639 > _ \n | |
9640 > (- verilog-indent-level-behavioral) "endgenerate" \n > ) | |
9641 | |
9642 (define-skeleton verilog-sk-begin | |
9643 "Insert begin end block. Uses the minibuffer to prompt for name" | |
9644 () | |
9645 > "begin" (verilog-sk-prompt-name) \n | |
9646 > _ \n | |
9647 > (- verilog-indent-level-behavioral) "end" | |
9648 ) | |
9649 | |
9650 (define-skeleton verilog-sk-fork | |
9651 "Insert an fork join block." | |
9652 () | |
9653 > "fork\n" | |
9654 > "begin" \n | |
9655 > _ \n | |
9656 > (- verilog-indent-level-behavioral) "end" \n | |
9657 > "begin" \n | |
9658 > \n | |
9659 > (- verilog-indent-level-behavioral) "end" \n | |
9660 > (- verilog-indent-level-behavioral) "join" \n | |
9661 > ) | |
9662 | |
9663 | |
9664 (define-skeleton verilog-sk-case | |
9665 "Build skeleton case statement, prompting for the selector expression, | |
9666 and the case items." | |
9667 "[selector expression]: " | |
9668 > "case (" str ") " \n | |
9669 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n ) | |
9670 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil)) | |
9671 | |
9672 (define-skeleton verilog-sk-casex | |
9673 "Build skeleton casex statement, prompting for the selector expression, | |
9674 and the case items." | |
9675 "[selector expression]: " | |
9676 > "casex (" str ") " \n | |
9677 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n ) | |
9678 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil)) | |
9679 | |
9680 (define-skeleton verilog-sk-casez | |
9681 "Build skeleton casez statement, prompting for the selector expression, | |
9682 and the case items." | |
9683 "[selector expression]: " | |
9684 > "casez (" str ") " \n | |
9685 > ("case selector: " str ": begin" \n > _ \n > (- verilog-indent-level-behavioral) "end" \n ) | |
9686 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil)) | |
9687 | |
9688 (define-skeleton verilog-sk-if | |
9689 "Insert a skeleton if statement." | |
9690 > "if (" (verilog-sk-prompt-condition) & ")" " begin" \n | |
9691 > _ \n | |
9692 > (- verilog-indent-level-behavioral) "end " \n ) | |
9693 | |
9694 (define-skeleton verilog-sk-else-if | |
9695 "Insert a skeleton else if statement." | |
9696 > (verilog-indent-line) "else if (" | |
9697 (progn (setq verilog-sk-p (point)) nil) (verilog-sk-prompt-condition) (if (> (point) verilog-sk-p) ") " -1 ) & " begin" \n | |
9698 > _ \n | |
9699 > "end" (progn (electric-verilog-terminate-line) nil)) | |
9700 | |
9701 (define-skeleton verilog-sk-datadef | |
9702 "Common routine to get data definition" | |
9703 () | |
9704 (verilog-sk-prompt-width) | -1 ("name (RET to end):" str ", ") -2 ";" \n) | |
9705 | |
9706 (define-skeleton verilog-sk-input | |
9707 "Insert an input definition." | |
9708 () | |
9709 > "input [" (verilog-sk-datadef)) | |
9710 | |
9711 (define-skeleton verilog-sk-output | |
9712 "Insert an output definition." | |
9713 () | |
9714 > "output [" (verilog-sk-datadef)) | |
9715 | |
9716 (define-skeleton verilog-sk-inout | |
9717 "Insert an inout definition." | |
9718 () | |
9719 > "inout [" (verilog-sk-datadef)) | |
9720 | |
9721 (defvar verilog-sk-signal nil) | |
9722 (define-skeleton verilog-sk-def-reg | |
9723 "Insert a reg definition." | |
9724 () | |
9725 > "reg [" (verilog-sk-prompt-width) | -1 verilog-sk-signal ";" \n (verilog-pretty-declarations) ) | |
9726 | |
9727 (defun verilog-sk-define-signal () | |
9728 "Insert a definition of signal under point at top of module." | |
9729 (interactive "*") | |
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9730 (let* ((sig-re "[a-zA-Z0-9_]*") |
79545 | 9731 (v1 (buffer-substring |
9732 (save-excursion | |
9733 (skip-chars-backward sig-re) | |
9734 (point)) | |
9735 (save-excursion | |
9736 (skip-chars-forward sig-re) | |
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|
9737 (point))))) |
79545 | 9738 (if (not (member v1 verilog-keywords)) |
9739 (save-excursion | |
9740 (setq verilog-sk-signal v1) | |
9741 (verilog-beg-of-defun) | |
9742 (verilog-end-of-statement) | |
9743 (verilog-forward-syntactic-ws) | |
9744 (verilog-sk-def-reg) | |
9745 (message "signal at point is %s" v1)) | |
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9746 (message "object at point (%s) is a keyword" v1)))) |
79545 | 9747 |
9748 (define-skeleton verilog-sk-wire | |
9749 "Insert a wire definition." | |
9750 () | |
9751 > "wire [" (verilog-sk-datadef)) | |
9752 | |
9753 (define-skeleton verilog-sk-reg | |
9754 "Insert a reg definition." | |
9755 () | |
9756 > "reg [" (verilog-sk-datadef)) | |
9757 | |
9758 (define-skeleton verilog-sk-assign | |
9759 "Insert a skeleton assign statement." | |
9760 () | |
9761 > "assign " (verilog-sk-prompt-name) " = " _ ";" \n) | |
9762 | |
9763 (define-skeleton verilog-sk-while | |
9764 "Insert a skeleton while loop statement." | |
9765 () | |
9766 > "while (" (verilog-sk-prompt-condition) ") begin" \n | |
9767 > _ \n | |
9768 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil)) | |
9769 | |
9770 (define-skeleton verilog-sk-repeat | |
9771 "Insert a skeleton repeat loop statement." | |
9772 () | |
9773 > "repeat (" (verilog-sk-prompt-condition) ") begin" \n | |
9774 > _ \n | |
9775 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil)) | |
9776 | |
9777 (define-skeleton verilog-sk-for | |
9778 "Insert a skeleton while loop statement." | |
9779 () | |
9780 > "for (" | |
9781 (verilog-sk-prompt-init) "; " | |
9782 (verilog-sk-prompt-condition) "; " | |
9783 (verilog-sk-prompt-inc) | |
9784 ") begin" \n | |
9785 > _ \n | |
9786 > (- verilog-indent-level-behavioral) "end " (progn (electric-verilog-terminate-line) nil)) | |
9787 | |
9788 (define-skeleton verilog-sk-comment | |
9789 "Inserts three comment lines, making a display comment." | |
9790 () | |
9791 > "/*\n" | |
9792 > "* " _ \n | |
9793 > "*/") | |
9794 | |
9795 (define-skeleton verilog-sk-state-machine | |
9796 "Insert a state machine definition." | |
9797 "Name of state variable: " | |
9798 '(setq input "state") | |
9799 > "// State registers for " str | -23 \n | |
9800 '(setq verilog-sk-state str) | |
9801 > "reg [" (verilog-sk-prompt-width) | -1 verilog-sk-state ", next_" verilog-sk-state ?; \n | |
9802 '(setq input nil) | |
9803 > \n | |
9804 > "// State FF for " verilog-sk-state \n | |
9805 > "always @ ( " (read-string "clock:" "posedge clk") " or " (verilog-sk-prompt-reset) " ) begin" \n | |
9806 > "if ( " verilog-sk-reset " ) " verilog-sk-state " = 0; else" \n | |
9807 > verilog-sk-state " = next_" verilog-sk-state ?; \n | |
9808 > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil) | |
9809 > \n | |
9810 > "// Next State Logic for " verilog-sk-state \n | |
9811 > "always @ ( /*AUTOSENSE*/ ) begin\n" | |
9812 > "case (" (verilog-sk-prompt-state-selector) ") " \n | |
9813 > ("case selector: " str ": begin" \n > "next_" verilog-sk-state " = " _ ";" \n > (- verilog-indent-level-behavioral) "end" \n ) | |
9814 resume: > (- verilog-case-indent) "endcase" (progn (electric-verilog-terminate-line) nil) | |
9815 > (- verilog-indent-level-behavioral) "end" (progn (electric-verilog-terminate-line) nil)) | |
9816 | |
9817 ;; Eliminate compile warning | |
9818 (eval-when-compile | |
9819 (if (not (boundp 'mode-popup-menu)) | |
9820 (defvar mode-popup-menu nil "Compatibility with XEmacs."))) | |
9821 | |
9822 ;; ---- add menu 'Statements' in Verilog mode (MH) | |
9823 (defun verilog-add-statement-menu () | |
9824 "Add the menu 'Statements' to the menu bar in Verilog mode." | |
9825 (if (featurep 'xemacs) | |
9826 (progn | |
9827 (easy-menu-add verilog-stmt-menu) | |
9828 (easy-menu-add verilog-menu) | |
9829 (setq mode-popup-menu (cons "Verilog Mode" verilog-stmt-menu))))) | |
9830 | |
9831 (add-hook 'verilog-mode-hook 'verilog-add-statement-menu) | |
9832 | |
9833 | |
9834 | |
9835 ;; | |
9836 ;; Include file loading with mouse/return event | |
9837 ;; | |
9838 ;; idea & first impl.: M. Rouat (eldo-mode.el) | |
9839 ;; second (emacs/xemacs) impl.: G. Van der Plas (spice-mode.el) | |
9840 | |
9841 (if (featurep 'xemacs) | |
9842 (require 'overlay) | |
9843 (require 'lucid)) ;; what else can we do ?? | |
9844 | |
9845 (defconst verilog-include-file-regexp | |
9846 "^`include\\s-+\"\\([^\n\"]*\\)\"" | |
9847 "Regexp that matches the include file.") | |
9848 | |
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9849 (defvar verilog-mode-mouse-map |
79545 | 9850 (let ((map (make-sparse-keymap))) ; as described in info pages, make a map |
9851 (set-keymap-parent map verilog-mode-map) | |
9852 ;; mouse button bindings | |
9853 (define-key map "\r" 'verilog-load-file-at-point) | |
9854 (if (featurep 'xemacs) | |
9855 (define-key map 'button2 'verilog-load-file-at-mouse);ffap-at-mouse ? | |
9856 (define-key map [mouse-2] 'verilog-load-file-at-mouse)) | |
9857 (if (featurep 'xemacs) | |
9858 (define-key map 'Sh-button2 'mouse-yank) ; you wanna paste don't you ? | |
79550
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* progmodes/verilog-mode.el (verilog-mode-map)
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79549
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changeset
|
9859 (define-key map [S-mouse-2] 'mouse-yank-at-click)) |
7f3b93a179a2
* progmodes/verilog-mode.el (verilog-mode-map)
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9860 map) |
79546 | 9861 "Map containing mouse bindings for `verilog-mode'.") |
9862 | |
79545 | 9863 |
9864 (defun verilog-colorize-include-files (beg end old-len) | |
9865 "This function colorizes included files when the mouse passes over them. | |
9866 Clicking on the middle-mouse button loads them in a buffer (as in dired)." | |
9867 (save-excursion | |
9868 (save-match-data | |
9869 (let (end-point) | |
9870 (goto-char end) | |
9871 (setq end-point (verilog-get-end-of-line)) | |
9872 (goto-char beg) | |
9873 (beginning-of-line) ; scan entire line ! | |
9874 ;; delete overlays existing on this line | |
9875 (let ((overlays (overlays-in (point) end-point))) | |
9876 (while overlays | |
9877 (if (and | |
9878 (overlay-get (car overlays) 'detachable) | |
9879 (overlay-get (car overlays) 'verilog-include-file)) | |
9880 (delete-overlay (car overlays))) | |
9881 (setq overlays (cdr overlays)))) ; let | |
9882 ;; make new ones, could reuse deleted one ? | |
9883 (while (search-forward-regexp verilog-include-file-regexp end-point t) | |
79550
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* progmodes/verilog-mode.el (verilog-mode-map)
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|
9884 (let (ov) |
79545 | 9885 (goto-char (match-beginning 1)) |
79550
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* progmodes/verilog-mode.el (verilog-mode-map)
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|
9886 (setq ov (make-overlay (match-beginning 1) (match-end 1))) |
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* progmodes/verilog-mode.el (verilog-mode-map)
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|
9887 (overlay-put ov 'start-closed 't) |
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* progmodes/verilog-mode.el (verilog-mode-map)
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79549
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changeset
|
9888 (overlay-put ov 'end-closed 't) |
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* progmodes/verilog-mode.el (verilog-mode-map)
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diff
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|
9889 (overlay-put ov 'evaporate 't) |
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* progmodes/verilog-mode.el (verilog-mode-map)
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|
9890 (overlay-put ov 'verilog-include-file 't) |
7f3b93a179a2
* progmodes/verilog-mode.el (verilog-mode-map)
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79549
diff
changeset
|
9891 (overlay-put ov 'mouse-face 'highlight) |
7f3b93a179a2
* progmodes/verilog-mode.el (verilog-mode-map)
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diff
changeset
|
9892 (overlay-put ov 'local-map verilog-mode-mouse-map))))))) |
79545 | 9893 |
9894 | |
9895 (defun verilog-colorize-include-files-buffer () | |
9896 "Colorize a include file." | |
9897 (interactive) | |
9898 ;; delete overlays | |
9899 (let ((overlays (overlays-in (point-min) (point-max)))) | |
9900 (while overlays | |
9901 (if (and | |
9902 (overlay-get (car overlays) 'detachable) | |
9903 (overlay-get (car overlays) 'verilog-include-file)) | |
9904 (delete-overlay (car overlays))) | |
9905 (setq overlays (cdr overlays)))) ; let | |
9906 ;; remake overlays | |
9907 (verilog-colorize-include-files (point-min) (point-max) nil)) | |
9908 | |
9909 ;; ffap-at-mouse isn't useful for verilog mode. It uses library paths. | |
9910 ;; so define this function to do more or less the same as ffap-at-mouse | |
9911 ;; but first resolve filename... | |
9912 (defun verilog-load-file-at-mouse (event) | |
9913 "Load file under button 2 click's EVENT. | |
9914 Files are checked based on `verilog-library-directories'." | |
9915 (interactive "@e") | |
9916 (save-excursion ;; implement a verilog specific ffap-at-mouse | |
9917 (mouse-set-point event) | |
9918 (beginning-of-line) | |
9919 (if (looking-at verilog-include-file-regexp) | |
9920 (if (and (car (verilog-library-filenames | |
9921 (match-string 1) (buffer-file-name))) | |
9922 (file-readable-p (car (verilog-library-filenames | |
9923 (match-string 1) (buffer-file-name))))) | |
9924 (find-file (car (verilog-library-filenames | |
9925 (match-string 1) (buffer-file-name)))) | |
9926 (progn | |
9927 (message | |
9928 "File '%s' isn't readable, use shift-mouse2 to paste in this field" | |
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9929 (match-string 1))))))) |
79545 | 9930 |
9931 ;; ffap isn't useable for verilog mode. It uses library paths. | |
9932 ;; so define this function to do more or less the same as ffap | |
9933 ;; but first resolve filename... | |
9934 (defun verilog-load-file-at-point () | |
9935 "Load file under point. | |
9936 Files are checked based on `verilog-library-directories'." | |
9937 (interactive) | |
9938 (save-excursion ;; implement a verilog specific ffap | |
9939 (beginning-of-line) | |
9940 (if (looking-at verilog-include-file-regexp) | |
9941 (if (and | |
9942 (car (verilog-library-filenames | |
9943 (match-string 1) (buffer-file-name))) | |
9944 (file-readable-p (car (verilog-library-filenames | |
9945 (match-string 1) (buffer-file-name))))) | |
9946 (find-file (car (verilog-library-filenames | |
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9947 (match-string 1) (buffer-file-name)))))))) |
79545 | 9948 |
9949 | |
9950 ;; | |
9951 ;; Bug reporting | |
9952 ;; | |
9953 | |
9954 (defun verilog-faq () | |
9955 "Tell the user their current version, and where to get the FAQ etc." | |
9956 (interactive) | |
9957 (with-output-to-temp-buffer "*verilog-mode help*" | |
9958 (princ (format "You are using verilog-mode %s\n" verilog-mode-version)) | |
9959 (princ "\n") | |
9960 (princ "For new releases, see http://www.verilog.com\n") | |
9961 (princ "\n") | |
9962 (princ "For frequently asked questions, see http://www.veripool.com/verilog-mode-faq.html\n") | |
9963 (princ "\n") | |
9964 (princ "To submit a bug, use M-x verilog-submit-bug-report\n") | |
9965 (princ "\n"))) | |
9966 | |
79691
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* progmodes/verilog-mode.el (top-level): Don't require compile.
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79555
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changeset
|
9967 (autoload 'reporter-submit-bug-report "reporter") |
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|
9968 (defvar reporter-prompt-for-summary-p) |
79691
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9969 |
79545 | 9970 (defun verilog-submit-bug-report () |
9971 "Submit via mail a bug report on verilog-mode.el." | |
9972 (interactive) | |
9973 (let ((reporter-prompt-for-summary-p t)) | |
9974 (reporter-submit-bug-report | |
9975 "mac@verilog.com" | |
9976 (concat "verilog-mode v" verilog-mode-version) | |
9977 '( | |
9978 verilog-align-ifelse | |
9979 verilog-auto-endcomments | |
9980 verilog-auto-hook | |
9981 verilog-auto-indent-on-newline | |
9982 verilog-auto-inst-vector | |
9983 verilog-auto-inst-template-numbers | |
9984 verilog-auto-lineup | |
9985 verilog-auto-newline | |
9986 verilog-auto-save-policy | |
9987 verilog-auto-sense-defines-constant | |
9988 verilog-auto-sense-include-inputs | |
9989 verilog-before-auto-hook | |
9990 verilog-case-indent | |
9991 verilog-cexp-indent | |
9992 verilog-compiler | |
9993 verilog-coverage | |
9994 verilog-highlight-translate-off | |
9995 verilog-indent-begin-after-if | |
9996 verilog-indent-declaration-macros | |
9997 verilog-indent-level | |
9998 verilog-indent-level-behavioral | |
9999 verilog-indent-level-declaration | |
10000 verilog-indent-level-directive | |
10001 verilog-indent-level-module | |
10002 verilog-indent-lists | |
10003 verilog-library-flags | |
10004 verilog-library-directories | |
10005 verilog-library-extensions | |
10006 verilog-library-files | |
10007 verilog-linter | |
10008 verilog-minimum-comment-distance | |
10009 verilog-mode-hook | |
10010 verilog-simulator | |
10011 verilog-tab-always-indent | |
10012 verilog-tab-to-comment | |
10013 ) | |
10014 nil nil | |
10015 (concat "Hi Mac, | |
10016 | |
10017 I want to report a bug. I've read the `Bugs' section of `Info' on | |
10018 Emacs, so I know how to make a clear and unambiguous report. To get | |
10019 to that Info section, I typed | |
10020 | |
10021 M-x info RET m " invocation-name " RET m bugs RET | |
10022 | |
10023 Before I go further, I want to say that Verilog mode has changed my life. | |
10024 I save so much time, my files are colored nicely, my co workers respect | |
10025 my coding ability... until now. I'd really appreciate anything you | |
10026 could do to help me out with this minor deficiency in the product. | |
10027 | |
10028 If you have bugs with the AUTO functions, please CC the AUTOAUTHOR Wilson | |
10029 Snyder (wsnyder@wsnyder.org) and/or see http://www.veripool.com. | |
10030 You may also want to look at the Verilog-Mode FAQ, see | |
10031 http://www.veripool.com/verilog-mode-faq.html. | |
10032 | |
10033 To reproduce the bug, start a fresh Emacs via " invocation-name " | |
10034 -no-init-file -no-site-file'. In a new buffer, in verilog mode, type | |
10035 the code included below. | |
10036 | |
10037 Given those lines, I expected [[Fill in here]] to happen; | |
10038 but instead, [[Fill in here]] happens!. | |
10039 | |
10040 == The code: ==")))) | |
10041 | |
79546 | 10042 (provide 'verilog-mode) |
10043 | |
79545 | 10044 ;; Local Variables: |
10045 ;; checkdoc-permit-comma-termination-flag:t | |
10046 ;; checkdoc-force-docstrings-flag:nil | |
10047 ;; End: | |
10048 | |
79552 | 10049 ;; arch-tag: 87923725-57b3-41b5-9494-be21118c6a6f |
79545 | 10050 ;;; verilog-mode.el ends here |