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10153
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1 /*
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2 * ARM NEON optimised MDCT
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3 * Copyright (c) 2009 Mans Rullgard <mans@mansr.com>
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4 *
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5 * This file is part of FFmpeg.
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6 *
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7 * FFmpeg is free software; you can redistribute it and/or
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8 * modify it under the terms of the GNU Lesser General Public
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9 * License as published by the Free Software Foundation; either
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10 * version 2.1 of the License, or (at your option) any later version.
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11 *
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12 * FFmpeg is distributed in the hope that it will be useful,
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13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 * Lesser General Public License for more details.
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16 *
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17 * You should have received a copy of the GNU Lesser General Public
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18 * License along with FFmpeg; if not, write to the Free Software
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19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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20 */
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21
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22 #include "asm.S"
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23
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24 .fpu neon
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25 .text
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26
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27 function ff_imdct_half_neon, export=1
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28 push {r4-r8,lr}
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29
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30 mov r12, #1
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31 ldr lr, [r0, #4] @ nbits
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32 ldr r4, [r0, #8] @ tcos
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33 ldr r5, [r0, #12] @ tsin
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34 ldr r3, [r0, #24] @ revtab
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35 lsl r12, r12, lr @ n = 1 << nbits
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36 lsr lr, r12, #2 @ n4 = n >> 2
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37 add r7, r2, r12, lsl #1
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38 mov r12, #-16
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39 sub r7, r7, #16
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40
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10160
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41 vld2.32 {d16-d17},[r7,:128],r12 @ d16=x,n1 d17=x,n0
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42 vld2.32 {d0-d1}, [r2,:128]! @ d0 =m0,x d1 =m1,x
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43 vrev64.32 d17, d17
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10153
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44 vld1.32 {d2}, [r4,:64]! @ d2=c0,c1
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10160
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45 vmul.f32 d6, d17, d2
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10153
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46 vld1.32 {d3}, [r5,:64]! @ d3=s0,s1
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47 vmul.f32 d7, d0, d2
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48 1:
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49 subs lr, lr, #2
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50 ldr r6, [r3], #4
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51 vmul.f32 d4, d0, d3
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10160
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52 vmul.f32 d5, d17, d3
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10153
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53 vsub.f32 d4, d6, d4
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54 vadd.f32 d5, d5, d7
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10172
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55 uxth r8, r6, ror #16
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56 uxth r6, r6
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57 add r8, r1, r8, lsl #3
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58 add r6, r1, r6, lsl #3
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10153
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59 beq 1f
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10160
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60 vld2.32 {d16-d17},[r7,:128],r12
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61 vld2.32 {d0-d1}, [r2,:128]!
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62 vrev64.32 d17, d17
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10153
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63 vld1.32 {d2}, [r4,:64]!
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10160
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64 vmul.f32 d6, d17, d2
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10153
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65 vld1.32 {d3}, [r5,:64]!
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66 vmul.f32 d7, d0, d2
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67 vst2.32 {d4[0],d5[0]}, [r6,:64]
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68 vst2.32 {d4[1],d5[1]}, [r8,:64]
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69 b 1b
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70 1:
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71 vst2.32 {d4[0],d5[0]}, [r6,:64]
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72 vst2.32 {d4[1],d5[1]}, [r8,:64]
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73
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74 mov r4, r0
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75 mov r6, r1
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76 add r0, r0, #16
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77 bl ff_fft_calc_neon
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78
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79 mov r12, #1
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80 ldr lr, [r4, #4] @ nbits
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81 ldr r5, [r4, #12] @ tsin
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82 ldr r4, [r4, #8] @ tcos
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83 lsl r12, r12, lr @ n = 1 << nbits
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84 lsr lr, r12, #3 @ n8 = n >> 3
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85
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86 add r4, r4, lr, lsl #2
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87 add r5, r5, lr, lsl #2
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88 add r6, r6, lr, lsl #3
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89 sub r1, r4, #8
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90 sub r2, r5, #8
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91 sub r3, r6, #16
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92
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93 mov r7, #-16
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94 mov r12, #-8
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95 mov r8, r6
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96 mov r0, r3
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97
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10160
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98 vld2.32 {d0-d1}, [r3,:128], r7 @ d0 =i1,r1 d1 =i0,r0
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99 vld2.32 {d20-d21},[r6,:128]! @ d20=i2,r2 d21=i3,r3
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10153
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100 vld1.32 {d18}, [r2,:64], r12 @ d18=s1,s0
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101 1:
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102 subs lr, lr, #2
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103 vmul.f32 d7, d0, d18
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104 vld1.32 {d19}, [r5,:64]! @ d19=s2,s3
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105 vmul.f32 d4, d1, d18
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106 vld1.32 {d16}, [r1,:64], r12 @ d16=c1,c0
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107 vmul.f32 d5, d21, d19
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108 vld1.32 {d17}, [r4,:64]! @ d17=c2,c3
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109 vmul.f32 d6, d20, d19
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110 vmul.f32 d22, d1, d16
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111 vmul.f32 d23, d21, d17
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112 vmul.f32 d24, d0, d16
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113 vmul.f32 d25, d20, d17
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114 vadd.f32 d7, d7, d22
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115 vadd.f32 d6, d6, d23
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116 vsub.f32 d4, d4, d24
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117 vsub.f32 d5, d5, d25
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118 beq 1f
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10160
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119 vld2.32 {d0-d1}, [r3,:128], r7
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120 vld2.32 {d20-d21},[r6,:128]!
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10153
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121 vld1.32 {d18}, [r2,:64], r12
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122 vrev64.32 q3, q3
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10160
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123 vst2.32 {d4,d6}, [r0,:128], r7
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124 vst2.32 {d5,d7}, [r8,:128]!
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10153
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125 b 1b
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126 1:
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127 vrev64.32 q3, q3
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10160
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128 vst2.32 {d4,d6}, [r0,:128]
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129 vst2.32 {d5,d7}, [r8,:128]
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10153
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130
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131 pop {r4-r8,pc}
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132 .endfunc
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133
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134 function ff_imdct_calc_neon, export=1
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135 push {r4-r6,lr}
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136
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137 ldr r3, [r0, #4]
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138 mov r4, #1
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139 mov r5, r1
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140 lsl r4, r4, r3
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141 add r1, r1, r4
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142
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143 bl ff_imdct_half_neon
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144
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145 add r0, r5, r4, lsl #2
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146 add r1, r5, r4, lsl #1
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147 sub r0, r0, #8
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148 sub r2, r1, #16
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149 mov r3, #-16
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150 mov r6, #-8
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151 vmov.i32 d30, #1<<31
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152 1:
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153 vld1.32 {d0-d1}, [r2,:128], r3
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154 pld [r0, #-16]
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155 vrev64.32 q0, q0
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156 vld1.32 {d2-d3}, [r1,:128]!
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157 veor d4, d1, d30
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158 pld [r2, #-16]
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159 vrev64.32 q1, q1
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160 veor d5, d0, d30
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161 vst1.32 {d2}, [r0,:64], r6
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162 vst1.32 {d3}, [r0,:64], r6
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163 vst1.32 {d4-d5}, [r5,:128]!
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164 subs r4, r4, #16
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165 bgt 1b
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166
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167 pop {r4-r6,pc}
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168 .endfunc
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10162
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169
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170 function ff_mdct_calc_neon, export=1
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171 push {r4-r10,lr}
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172
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173 mov r12, #1
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174 ldr lr, [r0, #4] @ nbits
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175 ldr r4, [r0, #8] @ tcos
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176 ldr r5, [r0, #12] @ tsin
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177 ldr r3, [r0, #24] @ revtab
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178 lsl lr, r12, lr @ n = 1 << nbits
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179 add r7, r2, lr @ in4u
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180 sub r9, r7, #16 @ in4d
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181 add r2, r7, lr, lsl #1 @ in3u
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182 add r8, r9, lr, lsl #1 @ in3d
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183 mov r12, #-16
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184
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185 vld2.32 {d16,d18},[r9,:128],r12 @ x,x in4d1,in4d0
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186 vld2.32 {d17,d19},[r8,:128],r12 @ x,x in3d1,in3d0
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187 vld2.32 {d20,d21},[r7,:128]! @ in4u0,in4u1 x,x
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188 vrev64.32 q9, q9 @ in4d0,in4d1 in3d0,in3d1
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189 vld2.32 {d0, d1}, [r2,:128]! @ in3u0,in3u1 x,x
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190 vsub.f32 d20, d18, d20 @ in4d-in4u I
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191 vld1.32 {d2}, [r4,:64]! @ c0,c1
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192 vadd.f32 d0, d0, d19 @ in3u+in3d -R
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193 vld1.32 {d3}, [r5,:64]! @ s0,s1
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194 1:
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195 vmul.f32 d7, d20, d3 @ I*s
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196 vmul.f32 d6, d0, d2 @ -R*c
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197 ldr r6, [r3], #4
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198 vmul.f32 d4, d0, d3 @ -R*s
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199 vmul.f32 d5, d20, d2 @ I*c
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200 subs lr, lr, #16
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201 vsub.f32 d6, d6, d7 @ -R*c-I*s
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202 vadd.f32 d7, d4, d5 @ -R*s+I*c
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10172
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203 uxth r10, r6, ror #16
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204 uxth r6, r6
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205 add r10, r1, r10, lsl #3
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206 add r6, r1, r6, lsl #3
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10162
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207 beq 1f
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208 vld2.32 {d16,d18},[r9,:128],r12 @ x,x in4d1,in4d0
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209 vld2.32 {d17,d19},[r8,:128],r12 @ x,x in3d1,in3d0
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210 vneg.f32 d7, d7 @ R*s-I*c
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211 vld2.32 {d20,d21},[r7,:128]! @ in4u0,in4u1 x,x
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212 vrev64.32 q9, q9 @ in4d0,in4d1 in3d0,in3d1
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213 vld2.32 {d0, d1}, [r2,:128]! @ in3u0,in3u1 x,x
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214 vsub.f32 d20, d18, d20 @ in4d-in4u I
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215 vld1.32 {d2}, [r4,:64]! @ c0,c1
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216 vadd.f32 d0, d0, d19 @ in3u+in3d -R
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217 vld1.32 {d3}, [r5,:64]! @ s0,s1
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218 vst2.32 {d6[0],d7[0]}, [r6,:64]
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219 vst2.32 {d6[1],d7[1]}, [r10,:64]
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220 b 1b
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221 1:
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222 vneg.f32 d7, d7 @ R*s-I*c
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223 vst2.32 {d6[0],d7[0]}, [r6,:64]
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224 vst2.32 {d6[1],d7[1]}, [r10,:64]
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225
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226 mov r12, #1
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227 ldr lr, [r0, #4] @ nbits
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228 lsl lr, r12, lr @ n = 1 << nbits
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229 sub r8, r2, #16 @ in1d
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230 add r2, r9, #16 @ in0u
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231 sub r9, r7, #16 @ in2d
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232 mov r12, #-16
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233
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234 vld2.32 {d16,d18},[r9,:128],r12 @ x,x in2d1,in2d0
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235 vld2.32 {d17,d19},[r8,:128],r12 @ x,x in1d1,in1d0
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236 vld2.32 {d20,d21},[r7,:128]! @ in2u0,in2u1 x,x
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237 vrev64.32 q9, q9 @ in2d0,in2d1 in1d0,in1d1
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238 vld2.32 {d0, d1}, [r2,:128]! @ in0u0,in0u1 x,x
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239 vsub.f32 d0, d0, d18 @ in0u-in2d R
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240 vld1.32 {d2}, [r4,:64]! @ c0,c1
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241 vadd.f32 d20, d20, d19 @ in2u+in1d -I
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242 vld1.32 {d3}, [r5,:64]! @ s0,s1
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243 1:
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244 vmul.f32 d6, d0, d2 @ R*c
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245 vmul.f32 d7, d20, d3 @ -I*s
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246 ldr r6, [r3], #4
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247 vmul.f32 d4, d0, d3 @ R*s
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248 vmul.f32 d5, d20, d2 @ I*c
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249 subs lr, lr, #16
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250 vsub.f32 d6, d7, d6 @ I*s-R*c
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251 vadd.f32 d7, d4, d5 @ R*s-I*c
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10172
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252 uxth r10, r6, ror #16
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253 uxth r6, r6
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254 add r10, r1, r10, lsl #3
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255 add r6, r1, r6, lsl #3
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10162
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256 beq 1f
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257 vld2.32 {d16,d18},[r9,:128],r12 @ x,x in2d1,in2d0
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258 vld2.32 {d17,d19},[r8,:128],r12 @ x,x in1d1,in1d0
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259 vld2.32 {d20,d21},[r7,:128]! @ in2u0,in2u1 x,x
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260 vrev64.32 q9, q9 @ in2d0,in2d1 in1d0,in1d1
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261 vld2.32 {d0, d1}, [r2,:128]! @ in0u0,in0u1 x,x
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262 vsub.f32 d0, d0, d18 @ in0u-in2d R
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263 vld1.32 {d2}, [r4,:64]! @ c0,c1
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264 vadd.f32 d20, d20, d19 @ in2u+in1d -I
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265 vld1.32 {d3}, [r5,:64]! @ s0,s1
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266 vst2.32 {d6[0],d7[0]}, [r6,:64]
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267 vst2.32 {d6[1],d7[1]}, [r10,:64]
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268 b 1b
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269 1:
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270 vst2.32 {d6[0],d7[0]}, [r6,:64]
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271 vst2.32 {d6[1],d7[1]}, [r10,:64]
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272
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273 mov r4, r0
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274 mov r6, r1
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275 add r0, r0, #16
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276 bl ff_fft_calc_neon
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277
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278 mov r12, #1
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279 ldr lr, [r4, #4] @ nbits
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280 ldr r5, [r4, #12] @ tsin
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281 ldr r4, [r4, #8] @ tcos
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282 lsl r12, r12, lr @ n = 1 << nbits
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283 lsr lr, r12, #3 @ n8 = n >> 3
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284
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285 add r4, r4, lr, lsl #2
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286 add r5, r5, lr, lsl #2
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287 add r6, r6, lr, lsl #3
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288 sub r1, r4, #8
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289 sub r2, r5, #8
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290 sub r3, r6, #16
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291
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292 mov r7, #-16
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293 mov r12, #-8
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294 mov r8, r6
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295 mov r0, r3
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296
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297 vld2.32 {d0-d1}, [r3,:128], r7 @ d0 =r1,i1 d1 =r0,i0
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298 vld2.32 {d20-d21},[r6,:128]! @ d20=r2,i2 d21=r3,i3
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299 vld1.32 {d18}, [r2,:64], r12 @ d18=s1,s0
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300 1:
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301 subs lr, lr, #2
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302 vmul.f32 d7, d0, d18 @ r1*s1,r0*s0
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303 vld1.32 {d19}, [r5,:64]! @ s2,s3
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304 vmul.f32 d4, d1, d18 @ i1*s1,i0*s0
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305 vld1.32 {d16}, [r1,:64], r12 @ c1,c0
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306 vmul.f32 d5, d21, d19 @ i2*s2,i3*s3
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307 vld1.32 {d17}, [r4,:64]! @ c2,c3
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308 vmul.f32 d6, d20, d19 @ r2*s2,r3*s3
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309 vmul.f32 d24, d0, d16 @ r1*c1,r0*c0
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310 vmul.f32 d25, d20, d17 @ r2*c2,r3*c3
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311 vmul.f32 d22, d21, d17 @ i2*c2,i3*c3
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312 vmul.f32 d23, d1, d16 @ i1*c1,i0*c0
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313 vadd.f32 d4, d4, d24 @ i1*s1+r1*c1,i0*s0+r0*c0
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314 vadd.f32 d5, d5, d25 @ i2*s2+r2*c2,i3*s3+r3*c3
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315 vsub.f32 d6, d22, d6 @ i2*c2-r2*s2,i3*c3-r3*s3
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316 vsub.f32 d7, d23, d7 @ i1*c1-r1*s1,i0*c0-r0*s0
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317 vneg.f32 q2, q2
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318 beq 1f
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319 vld2.32 {d0-d1}, [r3,:128], r7
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320 vld2.32 {d20-d21},[r6,:128]!
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321 vld1.32 {d18}, [r2,:64], r12
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322 vrev64.32 q3, q3
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323 vst2.32 {d4,d6}, [r0,:128], r7
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324 vst2.32 {d5,d7}, [r8,:128]!
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325 b 1b
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326 1:
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327 vrev64.32 q3, q3
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328 vst2.32 {d4,d6}, [r0,:128]
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329 vst2.32 {d5,d7}, [r8,:128]
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330
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331 pop {r4-r10,pc}
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332 .endfunc
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