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10153
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1 /*
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2 * ARM NEON optimised MDCT
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3 * Copyright (c) 2009 Mans Rullgard <mans@mansr.com>
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4 *
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5 * This file is part of FFmpeg.
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6 *
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7 * FFmpeg is free software; you can redistribute it and/or
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8 * modify it under the terms of the GNU Lesser General Public
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9 * License as published by the Free Software Foundation; either
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10 * version 2.1 of the License, or (at your option) any later version.
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11 *
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12 * FFmpeg is distributed in the hope that it will be useful,
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13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 * Lesser General Public License for more details.
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16 *
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17 * You should have received a copy of the GNU Lesser General Public
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18 * License along with FFmpeg; if not, write to the Free Software
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19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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20 */
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21
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22 #include "asm.S"
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23
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24 .fpu neon
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25 .text
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26
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27 function ff_imdct_half_neon, export=1
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28 push {r4-r8,lr}
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29
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30 mov r12, #1
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31 ldr lr, [r0, #4] @ nbits
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32 ldr r4, [r0, #8] @ tcos
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33 ldr r5, [r0, #12] @ tsin
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34 ldr r3, [r0, #24] @ revtab
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35 lsl r12, r12, lr @ n = 1 << nbits
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36 lsr lr, r12, #2 @ n4 = n >> 2
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37 add r7, r2, r12, lsl #1
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38 mov r12, #-16
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39 sub r7, r7, #16
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40
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41 vld1.32 {d16-d17},[r7,:128],r12 @ d16=x,n1 d17=x,n0
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42 vld1.32 {d0-d1}, [r2,:128]! @ d0 =m0,x d1 =m1,x
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43 vld1.32 {d2}, [r4,:64]! @ d2=c0,c1
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44 vld1.32 {d3}, [r5,:64]! @ d3=s0,s1
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45 vuzp.32 d17, d16
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46 vuzp.32 d0, d1
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47 vmul.f32 d6, d16, d2
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48 vmul.f32 d7, d0, d2
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49 1:
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50 subs lr, lr, #2
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51 ldr r6, [r3], #4
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52 vmul.f32 d4, d0, d3
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53 vmul.f32 d5, d16, d3
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54 vsub.f32 d4, d6, d4
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55 vadd.f32 d5, d5, d7
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56 uxtah r8, r1, r6, ror #16
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57 uxtah r6, r1, r6
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58 beq 1f
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59 vld1.32 {d16-d17},[r7,:128],r12
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60 vld1.32 {d0-d1}, [r2,:128]!
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61 vuzp.32 d17, d16
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62 vld1.32 {d2}, [r4,:64]!
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63 vuzp.32 d0, d1
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64 vmul.f32 d6, d16, d2
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65 vld1.32 {d3}, [r5,:64]!
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66 vmul.f32 d7, d0, d2
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67 vst2.32 {d4[0],d5[0]}, [r6,:64]
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68 vst2.32 {d4[1],d5[1]}, [r8,:64]
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69 b 1b
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70 1:
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71 vst2.32 {d4[0],d5[0]}, [r6,:64]
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72 vst2.32 {d4[1],d5[1]}, [r8,:64]
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73
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74 mov r4, r0
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75 mov r6, r1
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76 add r0, r0, #16
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77 bl ff_fft_calc_neon
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78
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79 mov r12, #1
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80 ldr lr, [r4, #4] @ nbits
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81 ldr r5, [r4, #12] @ tsin
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82 ldr r4, [r4, #8] @ tcos
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83 lsl r12, r12, lr @ n = 1 << nbits
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84 lsr lr, r12, #3 @ n8 = n >> 3
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85
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86 add r4, r4, lr, lsl #2
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87 add r5, r5, lr, lsl #2
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88 add r6, r6, lr, lsl #3
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89 sub r1, r4, #8
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90 sub r2, r5, #8
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91 sub r3, r6, #16
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92
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93 mov r7, #-16
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94 mov r12, #-8
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95 mov r8, r6
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96 mov r0, r3
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97
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98 vld1.32 {d0-d1}, [r3,:128], r7 @ d0 =i1,r1 d1 =i0,r0
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99 vld1.32 {d20-d21},[r6,:128]! @ d20=i2,r2 d21=i3,r3
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100 vld1.32 {d18}, [r2,:64], r12 @ d18=s1,s0
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101 vuzp.32 d20, d21
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102 vuzp.32 d0, d1
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103 1:
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104 subs lr, lr, #2
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105 vmul.f32 d7, d0, d18
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106 vld1.32 {d19}, [r5,:64]! @ d19=s2,s3
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107 vmul.f32 d4, d1, d18
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108 vld1.32 {d16}, [r1,:64], r12 @ d16=c1,c0
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109 vmul.f32 d5, d21, d19
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110 vld1.32 {d17}, [r4,:64]! @ d17=c2,c3
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111 vmul.f32 d6, d20, d19
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112 vmul.f32 d22, d1, d16
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113 vmul.f32 d23, d21, d17
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114 vmul.f32 d24, d0, d16
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115 vmul.f32 d25, d20, d17
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116 vadd.f32 d7, d7, d22
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117 vadd.f32 d6, d6, d23
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118 vsub.f32 d4, d4, d24
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119 vsub.f32 d5, d5, d25
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120 beq 1f
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121 vld1.32 {d0-d1}, [r3,:128], r7
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122 vld1.32 {d20-d21},[r6,:128]!
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123 vld1.32 {d18}, [r2,:64], r12
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124 vuzp.32 d20, d21
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125 vuzp.32 d0, d1
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126 vrev64.32 q3, q3
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127 vtrn.32 d4, d6
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128 vtrn.32 d5, d7
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129 vswp d5, d6
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130 vst1.32 {d4-d5}, [r0,:128], r7
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131 vst1.32 {d6-d7}, [r8,:128]!
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132 b 1b
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133 1:
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134 vrev64.32 q3, q3
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135 vtrn.32 d4, d6
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136 vtrn.32 d5, d7
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137 vswp d5, d6
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138 vst1.32 {d4-d5}, [r0,:128]
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139 vst1.32 {d6-d7}, [r8,:128]
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140
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141 pop {r4-r8,pc}
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142 .endfunc
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143
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144 function ff_imdct_calc_neon, export=1
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145 push {r4-r6,lr}
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146
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147 ldr r3, [r0, #4]
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148 mov r4, #1
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149 mov r5, r1
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150 lsl r4, r4, r3
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151 add r1, r1, r4
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152
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153 bl ff_imdct_half_neon
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154
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155 add r0, r5, r4, lsl #2
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156 add r1, r5, r4, lsl #1
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157 sub r0, r0, #8
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158 sub r2, r1, #16
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159 mov r3, #-16
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160 mov r6, #-8
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161 vmov.i32 d30, #1<<31
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162 1:
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163 vld1.32 {d0-d1}, [r2,:128], r3
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164 pld [r0, #-16]
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165 vrev64.32 q0, q0
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166 vld1.32 {d2-d3}, [r1,:128]!
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167 veor d4, d1, d30
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168 pld [r2, #-16]
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169 vrev64.32 q1, q1
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170 veor d5, d0, d30
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171 vst1.32 {d2}, [r0,:64], r6
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172 vst1.32 {d3}, [r0,:64], r6
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173 vst1.32 {d4-d5}, [r5,:128]!
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174 subs r4, r4, #16
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175 bgt 1b
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176
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177 pop {r4-r6,pc}
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178 .endfunc
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