Mercurial > libavcodec.hg
annotate ppc/dsputil_ppc.c @ 1015:35cf2f4a0f8c libavcodec
PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
author | michaelni |
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date | Sun, 19 Jan 2003 19:00:45 +0000 |
parents | 3b7cc8e4b83f |
children | 9cc1031e1864 |
rev | line source |
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1 /* |
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2 * Copyright (c) 2002 Brian Foley |
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3 * Copyright (c) 2002 Dieter Shirley |
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4 * |
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5 * This library is free software; you can redistribute it and/or |
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6 * modify it under the terms of the GNU Lesser General Public |
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7 * License as published by the Free Software Foundation; either |
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8 * version 2 of the License, or (at your option) any later version. |
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9 * |
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10 * This library is distributed in the hope that it will be useful, |
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11 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
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13 * Lesser General Public License for more details. |
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14 * |
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15 * You should have received a copy of the GNU Lesser General Public |
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16 * License along with this library; if not, write to the Free Software |
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17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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18 */ |
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19 |
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20 #include "../dsputil.h" |
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21 |
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22 #include "dsputil_ppc.h" |
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23 |
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24 #ifdef HAVE_ALTIVEC |
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25 #include "dsputil_altivec.h" |
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26 #endif |
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27 |
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28 int mm_flags = 0; |
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29 |
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30 int mm_support(void) |
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31 { |
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32 int result = 0; |
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33 #if HAVE_ALTIVEC |
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34 if (has_altivec()) { |
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35 result |= MM_ALTIVEC; |
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36 } |
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37 #endif /* result */ |
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38 return result; |
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39 } |
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40 |
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41 #ifdef POWERPC_TBL_PERFORMANCE_REPORT |
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42 unsigned long long perfdata[powerpc_perf_total][powerpc_data_total]; |
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43 /* list below must match enum in dsputil_altivec.h */ |
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44 static unsigned char* perfname[] = { |
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45 "fft_calc_altivec", |
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46 "gmc1_altivec", |
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47 "dct_unquantize_h263_altivec", |
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48 "idct_add_altivec", |
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49 "idct_put_altivec", |
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50 "put_pixels_clamped_altivec", |
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51 "put_pixels16_altivec", |
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52 "avg_pixels16_altivec", |
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53 "avg_pixels8_altivec", |
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54 "put_pixels8_xy2_altivec", |
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55 "clear_blocks_dcbz32_ppc" |
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56 }; |
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57 #ifdef POWERPC_PERF_USE_PMC |
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58 unsigned long long perfdata_miss[powerpc_perf_total][powerpc_data_total]; |
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59 #endif |
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60 #include <stdio.h> |
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61 #endif |
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62 |
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63 #ifdef POWERPC_TBL_PERFORMANCE_REPORT |
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64 void powerpc_display_perf_report(void) |
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65 { |
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66 int i; |
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67 #ifndef POWERPC_PERF_USE_PMC |
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68 fprintf(stderr, "AltiVec performance report\n Values are from the Time Base register, and represent 4 bus cycles.\n"); |
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69 #else /* POWERPC_PERF_USE_PMC */ |
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70 fprintf(stderr, "AltiVec performance report\n Values are from the PMC registers, and represent whatever the registers are set to record.\n"); |
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71 #endif /* POWERPC_PERF_USE_PMC */ |
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72 for(i = 0 ; i < powerpc_perf_total ; i++) |
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73 { |
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74 if (perfdata[i][powerpc_data_num] != (unsigned long long)0) |
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75 fprintf(stderr, " Function \"%s\" (pmc1):\n\tmin: %llu\n\tmax: %llu\n\tavg: %1.2lf (%llu)\n", |
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76 perfname[i], |
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77 perfdata[i][powerpc_data_min], |
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78 perfdata[i][powerpc_data_max], |
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79 (double)perfdata[i][powerpc_data_sum] / |
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80 (double)perfdata[i][powerpc_data_num], |
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81 perfdata[i][powerpc_data_num]); |
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82 #ifdef POWERPC_PERF_USE_PMC |
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83 if (perfdata_miss[i][powerpc_data_num] != (unsigned long long)0) |
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84 fprintf(stderr, " Function \"%s\" (pmc2):\n\tmin: %llu\n\tmax: %llu\n\tavg: %1.2lf (%llu)\n", |
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85 perfname[i], |
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86 perfdata_miss[i][powerpc_data_min], |
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87 perfdata_miss[i][powerpc_data_max], |
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88 (double)perfdata_miss[i][powerpc_data_sum] / |
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89 (double)perfdata_miss[i][powerpc_data_num], |
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90 perfdata_miss[i][powerpc_data_num]); |
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91 #endif |
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92 } |
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93 } |
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94 #endif /* POWERPC_TBL_PERFORMANCE_REPORT */ |
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95 |
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96 /* ***** WARNING ***** WARNING ***** WARNING ***** */ |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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97 /* |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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98 clear_blocks_dcbz32_ppc will not work properly |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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99 on PowerPC processors with a cache line size |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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100 not equal to 32 bytes. |
35cf2f4a0f8c
PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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101 Fortunately all processor used by Apple up to |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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102 at least the 7450 (aka second generation G4) |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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103 use 32 bytes cache line. |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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104 This is due to the use of the 'dcbz' instruction. |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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105 It simply clear to zero a single cache line, |
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106 so you need to know the cache line size to use it ! |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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107 It's absurd, but it's fast... |
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108 */ |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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109 void clear_blocks_dcbz32_ppc(DCTELEM *blocks) |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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110 { |
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111 POWERPC_TBL_DECLARE(powerpc_clear_blocks_dcbz32, 1); |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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112 register int misal = ((unsigned long)blocks & 0x00000010); |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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113 register int i = 0; |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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114 POWERPC_TBL_START_COUNT(powerpc_clear_blocks_dcbz32, 1); |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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115 #if 1 |
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116 if (misal) { |
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117 ((unsigned long*)blocks)[0] = 0L; |
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118 ((unsigned long*)blocks)[1] = 0L; |
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119 ((unsigned long*)blocks)[2] = 0L; |
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120 ((unsigned long*)blocks)[3] = 0L; |
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121 vec_st((vector short)(0), 0, blocks); |
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122 i += 16; |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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123 } |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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124 for ( ; i < sizeof(DCTELEM)*6*64 ; i += 32) { |
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125 asm volatile("dcbz %0,%1" : : "r" (blocks), "r" (i) : "memory"); |
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126 } |
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127 if (misal) { |
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128 ((unsigned long*)blocks)[188] = 0L; |
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129 ((unsigned long*)blocks)[189] = 0L; |
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130 ((unsigned long*)blocks)[190] = 0L; |
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131 ((unsigned long*)blocks)[191] = 0L; |
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132 i += 16; |
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133 } |
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134 #else |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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135 memset(blocks, 0, sizeof(DCTELEM)*6*64); |
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136 #endif |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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137 POWERPC_TBL_STOP_COUNT(powerpc_clear_blocks_dcbz32, 1); |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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138 } |
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139 |
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140 /* check dcbz report how many bytes are set to 0 by dcbz */ |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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141 long check_dcbz_effect(void) |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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142 { |
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143 register char *fakedata = (char*)malloc(1024); |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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144 register char *fakedata_middle; |
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145 register long zero = 0; |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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146 register long i = 0; |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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147 long count = 0; |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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148 |
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149 if (fakedata == NULL) |
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150 { |
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151 return 0L; |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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152 } |
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153 |
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154 |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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155 fakedata_middle = (fakedata + 512); |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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156 |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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157 memset(fakedata, 0xFF, 1024); |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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158 |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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159 asm volatile("dcbz %0, %1" : : "r" (fakedata_middle), "r" (zero)); |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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160 |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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161 for (i = 0; i < 1024 ; i ++) |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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162 { |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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163 if (fakedata[i] == (char)0) |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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164 count++; |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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165 } |
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166 |
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167 free(fakedata); |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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168 |
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169 return count; |
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170 } |
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171 |
856
3c6df37177dd
* using DSPContext - so each codec could use its local (sub)set of CPU extension
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172 void dsputil_init_ppc(DSPContext* c, unsigned mask) |
638
0012f75c92bb
altivec build tidyup patch by (Brian Foley <bfoley at compsoc dot nuigalway dot ie>)
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173 { |
828
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Altivec Patch (Mark III) by (Dieter Shirley <dieters at schemasoft dot com>)
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174 // Common optimisations whether Altivec or not |
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Altivec Patch (Mark III) by (Dieter Shirley <dieters at schemasoft dot com>)
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175 |
1015
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176 switch (check_dcbz_effect()) { |
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177 case 32: |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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178 c->clear_blocks = clear_blocks_dcbz32_ppc; |
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179 break; |
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PPC perf, PPC clear_block, AltiVec put_pixels8_xy2 patch by (Romain Dolbeau <dolbeau at irisa dot fr>)
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180 default: |
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181 break; |
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182 } |
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183 |
638
0012f75c92bb
altivec build tidyup patch by (Brian Foley <bfoley at compsoc dot nuigalway dot ie>)
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|
184 #if HAVE_ALTIVEC |
0012f75c92bb
altivec build tidyup patch by (Brian Foley <bfoley at compsoc dot nuigalway dot ie>)
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185 if (has_altivec()) { |
894
a408778eff87
altivec accelerated v-resample patch by (Brian Foley <bfoley at compsoc dot nuigalway dot ie>)
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186 mm_flags |= MM_ALTIVEC; |
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altivec accelerated v-resample patch by (Brian Foley <bfoley at compsoc dot nuigalway dot ie>)
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187 |
828
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Altivec Patch (Mark III) by (Dieter Shirley <dieters at schemasoft dot com>)
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188 // Altivec specific optimisations |
878
6ea69518e5f7
altivec optimizations patch by (Brian Foley <bfoley at compsoc dot nuigalway dot ie>)
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189 c->pix_abs16x16_x2 = pix_abs16x16_x2_altivec; |
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altivec optimizations patch by (Brian Foley <bfoley at compsoc dot nuigalway dot ie>)
michaelni
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190 c->pix_abs16x16_y2 = pix_abs16x16_y2_altivec; |
884 | 191 c->pix_abs16x16_xy2 = pix_abs16x16_xy2_altivec; |
192 c->pix_abs16x16 = pix_abs16x16_altivec; | |
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193 c->pix_abs8x8 = pix_abs8x8_altivec; |
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194 c->sad[0]= sad16x16_altivec; |
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195 c->sad[1]= sad8x8_altivec; |
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196 c->pix_norm1 = pix_norm1_altivec; |
981 | 197 c->sse[1]= sse8_altivec; |
198 c->sse[0]= sse16_altivec; | |
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199 c->pix_sum = pix_sum_altivec; |
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200 c->diff_pixels = diff_pixels_altivec; |
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201 c->get_pixels = get_pixels_altivec; |
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202 // next two disabled as they're untested. |
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203 #if 0 |
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204 c->add_bytes= add_bytes_altivec; |
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205 c->put_pixels_clamped = put_pixels_clamped_altivec; |
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206 #endif |
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207 c->put_pixels_tab[0][0] = put_pixels16_altivec; |
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208 c->avg_pixels_tab[0][0] = avg_pixels16_altivec; |
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209 // next one disabled as it's untested. |
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210 #if 0 |
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211 c->avg_pixels_tab[1][0] = avg_pixels8_altivec; |
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212 #endif |
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213 c->put_pixels_tab[1][3] = put_pixels8_xy2_altivec; |
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214 |
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215 c->gmc1 = gmc1_altivec; |
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216 |
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217 #ifdef POWERPC_TBL_PERFORMANCE_REPORT |
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218 { |
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219 int i; |
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220 for (i = 0 ; i < powerpc_perf_total ; i++) |
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221 { |
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222 perfdata[i][powerpc_data_min] = 0xFFFFFFFFFFFFFFFF; |
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223 perfdata[i][powerpc_data_max] = 0x0000000000000000; |
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224 perfdata[i][powerpc_data_sum] = 0x0000000000000000; |
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225 perfdata[i][powerpc_data_num] = 0x0000000000000000; |
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226 #ifdef POWERPC_PERF_USE_PMC |
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227 perfdata_miss[i][powerpc_data_min] = 0xFFFFFFFFFFFFFFFF; |
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228 perfdata_miss[i][powerpc_data_max] = 0x0000000000000000; |
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229 perfdata_miss[i][powerpc_data_sum] = 0x0000000000000000; |
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230 perfdata_miss[i][powerpc_data_num] = 0x0000000000000000; |
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231 #endif |
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232 } |
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233 } |
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234 #endif |
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235 } else |
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236 #endif |
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237 { |
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238 // Non-AltiVec PPC optimisations |
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239 |
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240 // ... pending ... |
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241 } |
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242 } |