annotate arm/dsputil_neon_s.S @ 8933:678fc8612787 libavcodec

Improve grammar: "X next after Y" -> "next X after Y".
author stefano
date Sun, 15 Feb 2009 20:45:10 +0000
parents 24a7b5d0eb27
children 9ea1ea6db616
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6bdd6dfc3574 ARM: NEON optimised put_pixels functions
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1 /*
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2 * ARM NEON optimised DSP functions
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3 * Copyright (c) 2008 Mans Rullgard <mans@mansr.com>
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4 *
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5 * This file is part of FFmpeg.
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6 *
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7 * FFmpeg is free software; you can redistribute it and/or
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8 * modify it under the terms of the GNU Lesser General Public
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9 * License as published by the Free Software Foundation; either
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10 * version 2.1 of the License, or (at your option) any later version.
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11 *
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12 * FFmpeg is distributed in the hope that it will be useful,
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13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 * Lesser General Public License for more details.
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16 *
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17 * You should have received a copy of the GNU Lesser General Public
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18 * License along with FFmpeg; if not, write to the Free Software
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19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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20 */
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21
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22 #include "asm.S"
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23
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24 preserve8
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25 .fpu neon
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26 .text
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27
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28 .macro pixels16 avg=0
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29 .if \avg
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30 mov ip, r0
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31 .endif
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32 1: vld1.64 {d0, d1}, [r1], r2
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33 vld1.64 {d2, d3}, [r1], r2
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34 vld1.64 {d4, d5}, [r1], r2
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35 pld [r1, r2, lsl #2]
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36 vld1.64 {d6, d7}, [r1], r2
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37 pld [r1]
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38 pld [r1, r2]
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39 pld [r1, r2, lsl #1]
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40 .if \avg
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41 vld1.64 {d16,d17}, [ip], r2
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42 vrhadd.u8 q0, q0, q8
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43 vld1.64 {d18,d19}, [ip], r2
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44 vrhadd.u8 q1, q1, q9
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45 vld1.64 {d20,d21}, [ip], r2
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46 vrhadd.u8 q2, q2, q10
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47 vld1.64 {d22,d23}, [ip], r2
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48 vrhadd.u8 q3, q3, q11
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49 .endif
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50 subs r3, r3, #4
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51 vst1.64 {d0, d1}, [r0,:128], r2
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52 vst1.64 {d2, d3}, [r0,:128], r2
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53 vst1.64 {d4, d5}, [r0,:128], r2
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54 vst1.64 {d6, d7}, [r0,:128], r2
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55 bne 1b
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56 bx lr
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57 .endm
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58
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59 .macro pixels16_x2 vhadd=vrhadd.u8
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60 1: vld1.64 {d0-d2}, [r1], r2
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61 vld1.64 {d4-d6}, [r1], r2
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62 pld [r1]
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63 pld [r1, r2]
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64 subs r3, r3, #2
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65 vext.8 q1, q0, q1, #1
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66 \vhadd q0, q0, q1
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67 vext.8 q3, q2, q3, #1
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68 \vhadd q2, q2, q3
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69 vst1.64 {d0, d1}, [r0,:128], r2
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70 vst1.64 {d4, d5}, [r0,:128], r2
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71 bne 1b
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72 bx lr
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73 .endm
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74
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75 .macro pixels16_y2 vhadd=vrhadd.u8
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76 push {lr}
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77 add ip, r1, r2
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78 lsl lr, r2, #1
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79 vld1.64 {d0, d1}, [r1], lr
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80 vld1.64 {d2, d3}, [ip], lr
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81 1: subs r3, r3, #2
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82 \vhadd q2, q0, q1
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83 vld1.64 {d0, d1}, [r1], lr
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84 \vhadd q3, q0, q1
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85 vld1.64 {d2, d3}, [ip], lr
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86 pld [r1]
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87 pld [ip]
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88 vst1.64 {d4, d5}, [r0,:128], r2
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89 vst1.64 {d6, d7}, [r0,:128], r2
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90 bne 1b
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91 pop {pc}
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92 .endm
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93
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94 .macro pixels16_xy2 vshrn=vrshrn.u16 no_rnd=0
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95 push {lr}
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96 lsl lr, r2, #1
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97 add ip, r1, r2
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98 vld1.64 {d0-d2}, [r1], lr
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99 vld1.64 {d4-d6}, [ip], lr
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100 .if \no_rnd
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101 vmov.i16 q13, #1
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102 .endif
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103 pld [r1]
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104 pld [ip]
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105 vext.8 q1, q0, q1, #1
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106 vext.8 q3, q2, q3, #1
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107 vaddl.u8 q8, d0, d2
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108 vaddl.u8 q10, d1, d3
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109 vaddl.u8 q9, d4, d6
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110 vaddl.u8 q11, d5, d7
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111 1: subs r3, r3, #2
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112 vld1.64 {d0-d2}, [r1], lr
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113 vadd.u16 q12, q8, q9
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114 pld [r1]
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115 .if \no_rnd
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116 vadd.u16 q12, q12, q13
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117 .endif
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118 vext.8 q15, q0, q1, #1
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119 vadd.u16 q1 , q10, q11
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120 \vshrn d28, q12, #2
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121 .if \no_rnd
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122 vadd.u16 q1, q1, q13
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123 .endif
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124 \vshrn d29, q1, #2
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125 vaddl.u8 q8, d0, d30
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126 vld1.64 {d2-d4}, [ip], lr
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127 vaddl.u8 q10, d1, d31
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128 vst1.64 {d28,d29}, [r0,:128], r2
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129 vadd.u16 q12, q8, q9
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130 pld [ip]
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131 .if \no_rnd
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132 vadd.u16 q12, q12, q13
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133 .endif
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134 vext.8 q2, q1, q2, #1
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135 vadd.u16 q0, q10, q11
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136 \vshrn d30, q12, #2
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137 .if \no_rnd
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138 vadd.u16 q0, q0, q13
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139 .endif
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140 \vshrn d31, q0, #2
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141 vaddl.u8 q9, d2, d4
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142 vaddl.u8 q11, d3, d5
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143 vst1.64 {d30,d31}, [r0,:128], r2
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144 bgt 1b
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145 pop {pc}
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146 .endm
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147
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148 .macro pixels8
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149 1: vld1.64 {d0}, [r1], r2
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150 vld1.64 {d1}, [r1], r2
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151 vld1.64 {d2}, [r1], r2
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152 pld [r1, r2, lsl #2]
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153 vld1.64 {d3}, [r1], r2
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154 pld [r1]
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155 pld [r1, r2]
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156 pld [r1, r2, lsl #1]
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157 subs r3, r3, #4
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158 vst1.64 {d0}, [r0,:64], r2
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159 vst1.64 {d1}, [r0,:64], r2
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160 vst1.64 {d2}, [r0,:64], r2
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161 vst1.64 {d3}, [r0,:64], r2
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162 bne 1b
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163 bx lr
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164 .endm
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165
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166 .macro pixels8_x2 vhadd=vrhadd.u8
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167 1: vld1.64 {d0, d1}, [r1], r2
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168 vext.8 d1, d0, d1, #1
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169 vld1.64 {d2, d3}, [r1], r2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
170 vext.8 d3, d2, d3, #1
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
171 pld [r1]
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
172 pld [r1, r2]
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
173 subs r3, r3, #2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
174 vswp d1, d2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
175 \vhadd q0, q0, q1
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
176 vst1.64 {d0}, [r0,:64], r2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
177 vst1.64 {d1}, [r0,:64], r2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
178 bne 1b
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
179 bx lr
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
180 .endm
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
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181
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
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diff changeset
182 .macro pixels8_y2 vhadd=vrhadd.u8
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
183 push {lr}
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
184 add ip, r1, r2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
185 lsl lr, r2, #1
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
186 vld1.64 {d0}, [r1], lr
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
187 vld1.64 {d1}, [ip], lr
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
188 1: subs r3, r3, #2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
189 \vhadd d4, d0, d1
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
190 vld1.64 {d0}, [r1], lr
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
191 \vhadd d5, d0, d1
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
192 vld1.64 {d1}, [ip], lr
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
193 pld [r1]
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
194 pld [ip]
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
195 vst1.64 {d4}, [r0,:64], r2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
196 vst1.64 {d5}, [r0,:64], r2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
197 bne 1b
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
198 pop {pc}
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
199 .endm
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
200
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
201 .macro pixels8_xy2 vshrn=vrshrn.u16 no_rnd=0
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
202 push {lr}
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
203 lsl lr, r2, #1
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
204 add ip, r1, r2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
205 vld1.64 {d0, d1}, [r1], lr
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
206 vld1.64 {d2, d3}, [ip], lr
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
207 .if \no_rnd
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
208 vmov.i16 q11, #1
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
209 .endif
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
210 pld [r1]
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
211 pld [ip]
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
212 vext.8 d4, d0, d1, #1
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
213 vext.8 d6, d2, d3, #1
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
214 vaddl.u8 q8, d0, d4
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
215 vaddl.u8 q9, d2, d6
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
216 1: subs r3, r3, #2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
217 vld1.64 {d0, d1}, [r1], lr
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
218 pld [r1]
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
219 vadd.u16 q10, q8, q9
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
220 vext.8 d4, d0, d1, #1
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
221 .if \no_rnd
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
222 vadd.u16 q10, q10, q11
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
223 .endif
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
224 vaddl.u8 q8, d0, d4
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
225 \vshrn d5, q10, #2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
226 vld1.64 {d2, d3}, [ip], lr
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
227 vadd.u16 q10, q8, q9
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
228 pld [ip]
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
229 .if \no_rnd
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
230 vadd.u16 q10, q10, q11
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
231 .endif
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
232 vst1.64 {d5}, [r0,:64], r2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
233 \vshrn d7, q10, #2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
234 vext.8 d6, d2, d3, #1
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
235 vaddl.u8 q9, d2, d6
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
236 vst1.64 {d7}, [r0,:64], r2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
237 bgt 1b
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
238 pop {pc}
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
239 .endm
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
240
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
241 .macro pixfunc pfx name suf rnd_op args:vararg
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
242 function ff_\pfx\name\suf\()_neon, export=1
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
243 \name \rnd_op \args
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
244 .endfunc
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
245 .endm
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
246
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
247 .macro pixfunc2 pfx name args:vararg
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
248 pixfunc \pfx \name
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
249 pixfunc \pfx \name \args
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
250 .endm
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
251
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
252 function ff_put_h264_qpel16_mc00_neon, export=1
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
253 mov r3, #16
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
254 .endfunc
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
255
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
256 pixfunc put_ pixels16
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
257 pixfunc2 put_ pixels16_x2, _no_rnd, vhadd.u8
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
258 pixfunc2 put_ pixels16_y2, _no_rnd, vhadd.u8
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
259 pixfunc2 put_ pixels16_xy2, _no_rnd, vshrn.u16, 1
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
260
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
261 function ff_avg_h264_qpel16_mc00_neon, export=1
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
262 mov r3, #16
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
263 .endfunc
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
264
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
265 pixfunc avg_ pixels16,, 1
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
266
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
267 function ff_put_h264_qpel8_mc00_neon, export=1
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
268 mov r3, #8
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
269 .endfunc
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
270
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
271 pixfunc put_ pixels8
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
272 pixfunc2 put_ pixels8_x2, _no_rnd, vhadd.u8
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
273 pixfunc2 put_ pixels8_y2, _no_rnd, vhadd.u8
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
274 pixfunc2 put_ pixels8_xy2, _no_rnd, vshrn.u16, 1
8492
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
275
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
276 function ff_float_to_int16_neon, export=1
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
277 subs r2, r2, #8
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
278 vld1.64 {d0-d1}, [r1,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
279 vcvt.s32.f32 q8, q0, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
280 vld1.64 {d2-d3}, [r1,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
281 vcvt.s32.f32 q9, q1, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
282 beq 3f
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
283 bics ip, r2, #15
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
284 beq 2f
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
285 1: subs ip, ip, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
286 vshrn.s32 d4, q8, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
287 vld1.64 {d0-d1}, [r1,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
288 vcvt.s32.f32 q0, q0, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
289 vshrn.s32 d5, q9, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
290 vld1.64 {d2-d3}, [r1,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
291 vcvt.s32.f32 q1, q1, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
292 vshrn.s32 d6, q0, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
293 vst1.64 {d4-d5}, [r0,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
294 vshrn.s32 d7, q1, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
295 vld1.64 {d16-d17},[r1,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
296 vcvt.s32.f32 q8, q8, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
297 vld1.64 {d18-d19},[r1,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
298 vcvt.s32.f32 q9, q9, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
299 vst1.64 {d6-d7}, [r0,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
300 bne 1b
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
301 ands r2, r2, #15
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
302 beq 3f
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
303 2: vld1.64 {d0-d1}, [r1,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
304 vshrn.s32 d4, q8, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
305 vcvt.s32.f32 q0, q0, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
306 vld1.64 {d2-d3}, [r1,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
307 vshrn.s32 d5, q9, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
308 vcvt.s32.f32 q1, q1, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
309 vshrn.s32 d6, q0, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
310 vst1.64 {d4-d5}, [r0,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
311 vshrn.s32 d7, q1, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
312 vst1.64 {d6-d7}, [r0,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
313 bx lr
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
314 3: vshrn.s32 d4, q8, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
315 vshrn.s32 d5, q9, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
316 vst1.64 {d4-d5}, [r0,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
317 bx lr
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
318 .endfunc
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
319
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
320 function ff_float_to_int16_interleave_neon, export=1
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
321 cmp r3, #2
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
322 ldrlt r1, [r1]
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
323 blt ff_float_to_int16_neon
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
324 bne 4f
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
325
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
326 ldr r3, [r1]
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
327 ldr r1, [r1, #4]
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
328
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
329 subs r2, r2, #8
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
330 vld1.64 {d0-d1}, [r3,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
331 vcvt.s32.f32 q8, q0, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
332 vld1.64 {d2-d3}, [r3,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
333 vcvt.s32.f32 q9, q1, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
334 vld1.64 {d20-d21},[r1,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
335 vcvt.s32.f32 q10, q10, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
336 vld1.64 {d22-d23},[r1,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
337 vcvt.s32.f32 q11, q11, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
338 beq 3f
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
339 bics ip, r2, #15
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
340 beq 2f
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
341 1: subs ip, ip, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
342 vld1.64 {d0-d1}, [r3,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
343 vcvt.s32.f32 q0, q0, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
344 vsri.32 q10, q8, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
345 vld1.64 {d2-d3}, [r3,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
346 vcvt.s32.f32 q1, q1, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
347 vld1.64 {d24-d25},[r1,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
348 vcvt.s32.f32 q12, q12, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
349 vld1.64 {d26-d27},[r1,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
350 vsri.32 q11, q9, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
351 vst1.64 {d20-d21},[r0,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
352 vcvt.s32.f32 q13, q13, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
353 vst1.64 {d22-d23},[r0,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
354 vsri.32 q12, q0, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
355 vld1.64 {d16-d17},[r3,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
356 vsri.32 q13, q1, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
357 vst1.64 {d24-d25},[r0,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
358 vcvt.s32.f32 q8, q8, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
359 vld1.64 {d18-d19},[r3,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
360 vcvt.s32.f32 q9, q9, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
361 vld1.64 {d20-d21},[r1,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
362 vcvt.s32.f32 q10, q10, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
363 vld1.64 {d22-d23},[r1,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
364 vcvt.s32.f32 q11, q11, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
365 vst1.64 {d26-d27},[r0,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
366 bne 1b
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
367 ands r2, r2, #15
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
368 beq 3f
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
369 2: vsri.32 q10, q8, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
370 vld1.64 {d0-d1}, [r3,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
371 vcvt.s32.f32 q0, q0, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
372 vld1.64 {d2-d3}, [r3,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
373 vcvt.s32.f32 q1, q1, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
374 vld1.64 {d24-d25},[r1,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
375 vcvt.s32.f32 q12, q12, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
376 vsri.32 q11, q9, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
377 vld1.64 {d26-d27},[r1,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
378 vcvt.s32.f32 q13, q13, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
379 vst1.64 {d20-d21},[r0,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
380 vsri.32 q12, q0, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
381 vst1.64 {d22-d23},[r0,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
382 vsri.32 q13, q1, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
383 vst1.64 {d24-d27},[r0,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
384 bx lr
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
385 3: vsri.32 q10, q8, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
386 vsri.32 q11, q9, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
387 vst1.64 {d20-d23},[r0,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
388 bx lr
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
389
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
390 4: push {r4-r8,lr}
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
391 cmp r3, #4
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
392 lsl ip, r3, #1
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
393 blt 4f
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
394
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
395 @ 4 channels
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
396 5: ldmia r1!, {r4-r7}
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
397 mov lr, r2
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
398 mov r8, r0
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
399 vld1.64 {d16-d17},[r4,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
400 vcvt.s32.f32 q8, q8, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
401 vld1.64 {d18-d19},[r5,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
402 vcvt.s32.f32 q9, q9, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
403 vld1.64 {d20-d21},[r6,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
404 vcvt.s32.f32 q10, q10, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
405 vld1.64 {d22-d23},[r7,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
406 vcvt.s32.f32 q11, q11, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
407 6: subs lr, lr, #8
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
408 vld1.64 {d0-d1}, [r4,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
409 vcvt.s32.f32 q0, q0, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
410 vsri.32 q9, q8, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
411 vld1.64 {d2-d3}, [r5,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
412 vcvt.s32.f32 q1, q1, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
413 vsri.32 q11, q10, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
414 vld1.64 {d4-d5}, [r6,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
415 vcvt.s32.f32 q2, q2, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
416 vzip.32 d18, d22
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
417 vld1.64 {d6-d7}, [r7,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
418 vcvt.s32.f32 q3, q3, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
419 vzip.32 d19, d23
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
420 vst1.64 {d18}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
421 vsri.32 q1, q0, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
422 vst1.64 {d22}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
423 vsri.32 q3, q2, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
424 vst1.64 {d19}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
425 vzip.32 d2, d6
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
426 vst1.64 {d23}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
427 vzip.32 d3, d7
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
428 beq 7f
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
429 vld1.64 {d16-d17},[r4,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
430 vcvt.s32.f32 q8, q8, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
431 vst1.64 {d2}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
432 vld1.64 {d18-d19},[r5,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
433 vcvt.s32.f32 q9, q9, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
434 vst1.64 {d6}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
435 vld1.64 {d20-d21},[r6,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
436 vcvt.s32.f32 q10, q10, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
437 vst1.64 {d3}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
438 vld1.64 {d22-d23},[r7,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
439 vcvt.s32.f32 q11, q11, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
440 vst1.64 {d7}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
441 b 6b
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
442 7: vst1.64 {d2}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
443 vst1.64 {d6}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
444 vst1.64 {d3}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
445 vst1.64 {d7}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
446 subs r3, r3, #4
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
447 popeq {r4-r8,pc}
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
448 cmp r3, #4
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
449 add r0, r0, #8
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
450 bge 5b
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
451
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
452 @ 2 channels
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
453 4: cmp r3, #2
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
454 blt 4f
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
455 ldmia r1!, {r4-r5}
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
456 mov lr, r2
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
457 mov r8, r0
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
458 tst lr, #8
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
459 vld1.64 {d16-d17},[r4,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
460 vcvt.s32.f32 q8, q8, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
461 vld1.64 {d18-d19},[r5,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
462 vcvt.s32.f32 q9, q9, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
463 vld1.64 {d20-d21},[r4,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
464 vcvt.s32.f32 q10, q10, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
465 vld1.64 {d22-d23},[r5,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
466 vcvt.s32.f32 q11, q11, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
467 beq 6f
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
468 subs lr, lr, #8
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
469 beq 7f
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
470 vsri.32 d18, d16, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
471 vsri.32 d19, d17, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
472 vld1.64 {d16-d17},[r4,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
473 vcvt.s32.f32 q8, q8, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
474 vst1.32 {d18[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
475 vsri.32 d22, d20, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
476 vst1.32 {d18[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
477 vsri.32 d23, d21, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
478 vst1.32 {d19[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
479 vst1.32 {d19[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
480 vld1.64 {d18-d19},[r5,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
481 vcvt.s32.f32 q9, q9, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
482 vst1.32 {d22[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
483 vst1.32 {d22[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
484 vld1.64 {d20-d21},[r4,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
485 vcvt.s32.f32 q10, q10, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
486 vst1.32 {d23[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
487 vst1.32 {d23[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
488 vld1.64 {d22-d23},[r5,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
489 vcvt.s32.f32 q11, q11, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
490 6: subs lr, lr, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
491 vld1.64 {d0-d1}, [r4,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
492 vcvt.s32.f32 q0, q0, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
493 vsri.32 d18, d16, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
494 vld1.64 {d2-d3}, [r5,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
495 vcvt.s32.f32 q1, q1, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
496 vsri.32 d19, d17, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
497 vld1.64 {d4-d5}, [r4,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
498 vcvt.s32.f32 q2, q2, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
499 vld1.64 {d6-d7}, [r5,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
500 vcvt.s32.f32 q3, q3, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
501 vst1.32 {d18[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
502 vsri.32 d22, d20, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
503 vst1.32 {d18[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
504 vsri.32 d23, d21, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
505 vst1.32 {d19[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
506 vsri.32 d2, d0, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
507 vst1.32 {d19[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
508 vsri.32 d3, d1, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
509 vst1.32 {d22[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
510 vsri.32 d6, d4, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
511 vst1.32 {d22[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
512 vsri.32 d7, d5, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
513 vst1.32 {d23[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
514 vst1.32 {d23[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
515 beq 6f
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
516 vld1.64 {d16-d17},[r4,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
517 vcvt.s32.f32 q8, q8, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
518 vst1.32 {d2[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
519 vst1.32 {d2[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
520 vld1.64 {d18-d19},[r5,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
521 vcvt.s32.f32 q9, q9, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
522 vst1.32 {d3[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
523 vst1.32 {d3[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
524 vld1.64 {d20-d21},[r4,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
525 vcvt.s32.f32 q10, q10, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
526 vst1.32 {d6[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
527 vst1.32 {d6[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
528 vld1.64 {d22-d23},[r5,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
529 vcvt.s32.f32 q11, q11, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
530 vst1.32 {d7[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
531 vst1.32 {d7[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
532 bgt 6b
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
533 6: vst1.32 {d2[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
534 vst1.32 {d2[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
535 vst1.32 {d3[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
536 vst1.32 {d3[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
537 vst1.32 {d6[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
538 vst1.32 {d6[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
539 vst1.32 {d7[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
540 vst1.32 {d7[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
541 b 8f
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
542 7: vsri.32 d18, d16, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
543 vsri.32 d19, d17, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
544 vst1.32 {d18[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
545 vsri.32 d22, d20, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
546 vst1.32 {d18[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
547 vsri.32 d23, d21, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
548 vst1.32 {d19[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
549 vst1.32 {d19[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
550 vst1.32 {d22[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
551 vst1.32 {d22[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
552 vst1.32 {d23[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
553 vst1.32 {d23[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
554 8: subs r3, r3, #2
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
555 add r0, r0, #4
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
556 popeq {r4-r8,pc}
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
557
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
558 @ 1 channel
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
559 4: ldr r4, [r1],#4
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
560 tst r2, #8
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
561 mov lr, r2
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
562 mov r5, r0
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
563 vld1.64 {d0-d1}, [r4,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
564 vcvt.s32.f32 q0, q0, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
565 vld1.64 {d2-d3}, [r4,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
566 vcvt.s32.f32 q1, q1, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
567 bne 8f
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
568 6: subs lr, lr, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
569 vld1.64 {d4-d5}, [r4,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
570 vcvt.s32.f32 q2, q2, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
571 vld1.64 {d6-d7}, [r4,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
572 vcvt.s32.f32 q3, q3, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
573 vst1.16 {d0[1]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
574 vst1.16 {d0[3]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
575 vst1.16 {d1[1]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
576 vst1.16 {d1[3]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
577 vst1.16 {d2[1]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
578 vst1.16 {d2[3]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
579 vst1.16 {d3[1]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
580 vst1.16 {d3[3]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
581 beq 7f
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
582 vld1.64 {d0-d1}, [r4,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
583 vcvt.s32.f32 q0, q0, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
584 vld1.64 {d2-d3}, [r4,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
585 vcvt.s32.f32 q1, q1, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
586 7: vst1.16 {d4[1]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
587 vst1.16 {d4[3]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
588 vst1.16 {d5[1]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
589 vst1.16 {d5[3]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
590 vst1.16 {d6[1]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
591 vst1.16 {d6[3]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
592 vst1.16 {d7[1]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
593 vst1.16 {d7[3]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
594 bgt 6b
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
595 pop {r4-r8,pc}
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
596 8: subs lr, lr, #8
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
597 vst1.16 {d0[1]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
598 vst1.16 {d0[3]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
599 vst1.16 {d1[1]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
600 vst1.16 {d1[3]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
601 vst1.16 {d2[1]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
602 vst1.16 {d2[3]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
603 vst1.16 {d3[1]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
604 vst1.16 {d3[3]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
605 popeq {r4-r8,pc}
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
606 vld1.64 {d0-d1}, [r4,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
607 vcvt.s32.f32 q0, q0, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
608 vld1.64 {d2-d3}, [r4,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
609 vcvt.s32.f32 q1, q1, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
610 b 6b
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
611 .endfunc
8697
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
612
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
613 function ff_vector_fmul_neon, export=1
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
614 mov r3, r0
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
615 subs r2, r2, #8
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
616 vld1.64 {d0-d3}, [r0,:128]!
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
617 vld1.64 {d4-d7}, [r1,:128]!
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
618 vmul.f32 q8, q0, q2
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
619 vmul.f32 q9, q1, q3
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
620 beq 3f
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
621 bics ip, r2, #15
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
622 beq 2f
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
623 1: subs ip, ip, #16
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
624 vld1.64 {d0-d1}, [r0,:128]!
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
625 vld1.64 {d4-d5}, [r1,:128]!
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
626 vmul.f32 q10, q0, q2
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
627 vld1.64 {d2-d3}, [r0,:128]!
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
628 vld1.64 {d6-d7}, [r1,:128]!
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
629 vmul.f32 q11, q1, q3
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
630 vst1.64 {d16-d19},[r3,:128]!
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
631 vld1.64 {d0-d1}, [r0,:128]!
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
632 vld1.64 {d4-d5}, [r1,:128]!
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
633 vmul.f32 q8, q0, q2
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
634 vld1.64 {d2-d3}, [r0,:128]!
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
635 vld1.64 {d6-d7}, [r1,:128]!
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
636 vmul.f32 q9, q1, q3
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
637 vst1.64 {d20-d23},[r3,:128]!
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
638 bne 1b
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
639 ands r2, r2, #15
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
640 beq 3f
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
641 2: vld1.64 {d0-d1}, [r0,:128]!
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
642 vld1.64 {d4-d5}, [r1,:128]!
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
643 vst1.64 {d16-d17},[r3,:128]!
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
644 vmul.f32 q8, q0, q2
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
645 vld1.64 {d2-d3}, [r0,:128]!
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
646 vld1.64 {d6-d7}, [r1,:128]!
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
647 vst1.64 {d18-d19},[r3,:128]!
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
648 vmul.f32 q9, q1, q3
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
649 3: vst1.64 {d16-d19},[r3,:128]!
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
650 bx lr
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
651 .endfunc
8698
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
652
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
653 function ff_vector_fmul_window_neon, export=1
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
654 vld1.32 {d16[],d17[]}, [sp,:32]
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
655 push {r4,r5,lr}
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
656 ldr lr, [sp, #16]
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
657 sub r2, r2, #8
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
658 sub r5, lr, #2
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
659 add r2, r2, r5, lsl #2
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
660 add r4, r3, r5, lsl #3
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
661 add ip, r0, r5, lsl #3
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
662 mov r5, #-16
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
663 vld1.64 {d0,d1}, [r1,:128]!
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
664 vld1.64 {d2,d3}, [r2,:128], r5
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
665 vld1.64 {d4,d5}, [r3,:128]!
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
666 vld1.64 {d6,d7}, [r4,:128], r5
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
667 1: subs lr, lr, #4
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
668 vmov q11, q8
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
669 vmla.f32 d22, d0, d4
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
670 vmov q10, q8
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
671 vmla.f32 d23, d1, d5
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
672 vrev64.32 q3, q3
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
673 vmla.f32 d20, d0, d7
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
674 vrev64.32 q1, q1
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
675 vmla.f32 d21, d1, d6
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
676 beq 2f
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
677 vmla.f32 d22, d3, d7
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
678 vld1.64 {d0,d1}, [r1,:128]!
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
679 vmla.f32 d23, d2, d6
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
680 vld1.64 {d18,d19},[r2,:128], r5
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
681 vmls.f32 d20, d3, d4
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
682 vld1.64 {d24,d25},[r3,:128]!
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
683 vmls.f32 d21, d2, d5
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
684 vld1.64 {d6,d7}, [r4,:128], r5
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
685 vmov q1, q9
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
686 vrev64.32 q11, q11
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
687 vmov q2, q12
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
688 vswp d22, d23
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
689 vst1.64 {d20,d21},[r0,:128]!
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
690 vst1.64 {d22,d23},[ip,:128], r5
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
691 b 1b
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
692 2: vmla.f32 d22, d3, d7
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
693 vmla.f32 d23, d2, d6
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
694 vmls.f32 d20, d3, d4
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
695 vmls.f32 d21, d2, d5
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
696 vrev64.32 q11, q11
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
697 vswp d22, d23
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
698 vst1.64 {d20,d21},[r0,:128]!
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
699 vst1.64 {d22,d23},[ip,:128], r5
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
700 pop {r4,r5,pc}
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
701 .endfunc