annotate arm/fft_neon.S @ 10153:7a63015e4627 libavcodec

ARM: NEON optimised FFT and MDCT Vorbis and AC3 ~3x faster. Parts by Naotoshi Nojiri, naonoj gmail
author mru
date Thu, 10 Sep 2009 08:50:03 +0000
parents
children eda985c53dba
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
10153
7a63015e4627 ARM: NEON optimised FFT and MDCT
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1 /*
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2 * ARM NEON optimised FFT
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3 *
7a63015e4627 ARM: NEON optimised FFT and MDCT
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4 * Copyright (c) 2009 Mans Rullgard <mans@mansr.com>
7a63015e4627 ARM: NEON optimised FFT and MDCT
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5 * Copyright (c) 2009 Naotoshi Nojiri
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6 *
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7 * This file is part of FFmpeg.
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8 *
7a63015e4627 ARM: NEON optimised FFT and MDCT
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9 * FFmpeg is free software; you can redistribute it and/or
7a63015e4627 ARM: NEON optimised FFT and MDCT
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10 * modify it under the terms of the GNU Lesser General Public
7a63015e4627 ARM: NEON optimised FFT and MDCT
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11 * License as published by the Free Software Foundation; either
7a63015e4627 ARM: NEON optimised FFT and MDCT
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12 * version 2.1 of the License, or (at your option) any later version.
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13 *
7a63015e4627 ARM: NEON optimised FFT and MDCT
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14 * FFmpeg is distributed in the hope that it will be useful,
7a63015e4627 ARM: NEON optimised FFT and MDCT
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15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7a63015e4627 ARM: NEON optimised FFT and MDCT
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16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
7a63015e4627 ARM: NEON optimised FFT and MDCT
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17 * Lesser General Public License for more details.
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18 *
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19 * You should have received a copy of the GNU Lesser General Public
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20 * License along with FFmpeg; if not, write to the Free Software
7a63015e4627 ARM: NEON optimised FFT and MDCT
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21 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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22 */
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23
7a63015e4627 ARM: NEON optimised FFT and MDCT
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24 #include "asm.S"
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25
7a63015e4627 ARM: NEON optimised FFT and MDCT
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26 #define M_SQRT1_2 0.70710678118654752440
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27
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28 .text
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29
7a63015e4627 ARM: NEON optimised FFT and MDCT
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30 function fft4_neon
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31 vld1.32 {d0-d3}, [r0,:128]
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32
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33 vext.32 q8, q1, q1, #1 @ i2,r3 d3=i3,r2
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34 vsub.f32 d6, d0, d1 @ r0-r1,i0-i1
7a63015e4627 ARM: NEON optimised FFT and MDCT
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35 vsub.f32 d7, d16, d17 @ r3-r2,i2-i3
7a63015e4627 ARM: NEON optimised FFT and MDCT
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36 vadd.f32 d4, d0, d1 @ r0+r1,i0+i1
7a63015e4627 ARM: NEON optimised FFT and MDCT
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37 vadd.f32 d5, d2, d3 @ i2+i3,r2+r3
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38 vadd.f32 d1, d6, d7
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39 vsub.f32 d3, d6, d7
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40 vadd.f32 d0, d4, d5
7a63015e4627 ARM: NEON optimised FFT and MDCT
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41 vsub.f32 d2, d4, d5
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42
7a63015e4627 ARM: NEON optimised FFT and MDCT
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43 vst1.32 {d0-d3}, [r0,:128]
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44
7a63015e4627 ARM: NEON optimised FFT and MDCT
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45 bx lr
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46 .endfunc
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47
7a63015e4627 ARM: NEON optimised FFT and MDCT
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48 function fft8_neon
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49 mov r1, r0
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50 vld1.32 {d0-d3}, [r1,:128]!
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51 vld1.32 {d16-d19}, [r1,:128]
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52
7a63015e4627 ARM: NEON optimised FFT and MDCT
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53 movw r2, #0x04f3 @ sqrt(1/2)
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54 movt r2, #0x3f35
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55 eor r3, r2, #1<<31
7a63015e4627 ARM: NEON optimised FFT and MDCT
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56 vdup.32 d31, r2
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57
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58 vext.32 q11, q1, q1, #1 @ i2,r3,i3,r2
7a63015e4627 ARM: NEON optimised FFT and MDCT
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59 vadd.f32 d4, d16, d17 @ r4+r5,i4+i5
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60 vmov d28, r3, r2
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61 vadd.f32 d5, d18, d19 @ r6+r7,i6+i7
7a63015e4627 ARM: NEON optimised FFT and MDCT
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62 vsub.f32 d17, d16, d17 @ r4-r5,i4-i5
7a63015e4627 ARM: NEON optimised FFT and MDCT
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63 vsub.f32 d19, d18, d19 @ r6-r7,i6-i7
7a63015e4627 ARM: NEON optimised FFT and MDCT
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64 vrev64.32 d29, d28
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65 vadd.f32 d20, d0, d1 @ r0+r1,i0+i1
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66 vadd.f32 d21, d2, d3 @ r2+r3,i2+i3
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67 vmul.f32 d26, d17, d28 @ -a2r*w,a2i*w
7a63015e4627 ARM: NEON optimised FFT and MDCT
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68 vext.32 q3, q2, q2, #1
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69 vmul.f32 d27, d19, d29 @ a3r*w,-a3i*w
7a63015e4627 ARM: NEON optimised FFT and MDCT
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70 vsub.f32 d23, d22, d23 @ i2-i3,r3-r2
7a63015e4627 ARM: NEON optimised FFT and MDCT
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71 vsub.f32 d22, d0, d1 @ r0-r1,i0-i1
7a63015e4627 ARM: NEON optimised FFT and MDCT
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72 vmul.f32 d24, d17, d31 @ a2r*w,a2i*w
7a63015e4627 ARM: NEON optimised FFT and MDCT
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73 vmul.f32 d25, d19, d31 @ a3r*w,a3i*w
7a63015e4627 ARM: NEON optimised FFT and MDCT
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74 vadd.f32 d0, d20, d21
7a63015e4627 ARM: NEON optimised FFT and MDCT
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75 vsub.f32 d2, d20, d21
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76 vadd.f32 d1, d22, d23
7a63015e4627 ARM: NEON optimised FFT and MDCT
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77 vrev64.32 q13, q13
7a63015e4627 ARM: NEON optimised FFT and MDCT
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78 vsub.f32 d3, d22, d23
7a63015e4627 ARM: NEON optimised FFT and MDCT
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79 vsub.f32 d6, d6, d7
7a63015e4627 ARM: NEON optimised FFT and MDCT
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80 vadd.f32 d24, d24, d26 @ a2r+a2i,a2i-a2r t1,t2
7a63015e4627 ARM: NEON optimised FFT and MDCT
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81 vadd.f32 d25, d25, d27 @ a3r-a3i,a3i+a3r t5,t6
7a63015e4627 ARM: NEON optimised FFT and MDCT
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82 vadd.f32 d7, d4, d5
7a63015e4627 ARM: NEON optimised FFT and MDCT
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83 vsub.f32 d18, d2, d6
7a63015e4627 ARM: NEON optimised FFT and MDCT
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84 vext.32 q13, q12, q12, #1
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85 vadd.f32 d2, d2, d6
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86 vsub.f32 d16, d0, d7
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87 vadd.f32 d5, d25, d24
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88 vsub.f32 d4, d26, d27
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89 vadd.f32 d0, d0, d7
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90 vsub.f32 d17, d1, d5
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91 vsub.f32 d19, d3, d4
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92 vadd.f32 d3, d3, d4
7a63015e4627 ARM: NEON optimised FFT and MDCT
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93 vadd.f32 d1, d1, d5
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94
7a63015e4627 ARM: NEON optimised FFT and MDCT
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95 vst1.32 {d16-d19}, [r1,:128]
7a63015e4627 ARM: NEON optimised FFT and MDCT
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96 vst1.32 {d0-d3}, [r0,:128]
7a63015e4627 ARM: NEON optimised FFT and MDCT
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97
7a63015e4627 ARM: NEON optimised FFT and MDCT
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98 bx lr
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99 .endfunc
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100
7a63015e4627 ARM: NEON optimised FFT and MDCT
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101 function fft16_neon
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102 movrel r1, mppm
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103 vld1.32 {d16-d19}, [r0,:128]! @ q8{r0,i0,r1,i1} q9{r2,i2,r3,i3}
7a63015e4627 ARM: NEON optimised FFT and MDCT
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104 pld [r0, #32]
7a63015e4627 ARM: NEON optimised FFT and MDCT
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105 vld1.32 {d2-d3}, [r1,:128]
7a63015e4627 ARM: NEON optimised FFT and MDCT
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106 vext.32 q13, q9, q9, #1
7a63015e4627 ARM: NEON optimised FFT and MDCT
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107 vld1.32 {d22-d25}, [r0,:128]! @ q11{r4,i4,r5,i5} q12{r6,i5,r7,i7}
7a63015e4627 ARM: NEON optimised FFT and MDCT
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108 vadd.f32 d4, d16, d17
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109 vsub.f32 d5, d16, d17
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110 vadd.f32 d18, d18, d19
7a63015e4627 ARM: NEON optimised FFT and MDCT
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111 vsub.f32 d19, d26, d27
7a63015e4627 ARM: NEON optimised FFT and MDCT
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112
7a63015e4627 ARM: NEON optimised FFT and MDCT
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113 vadd.f32 d20, d22, d23
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114 vsub.f32 d22, d22, d23
7a63015e4627 ARM: NEON optimised FFT and MDCT
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115 vsub.f32 d23, d24, d25
7a63015e4627 ARM: NEON optimised FFT and MDCT
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116 vadd.f32 q8, q2, q9 @ {r0,i0,r1,i1}
7a63015e4627 ARM: NEON optimised FFT and MDCT
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117 vadd.f32 d21, d24, d25
7a63015e4627 ARM: NEON optimised FFT and MDCT
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118 vmul.f32 d24, d22, d2
7a63015e4627 ARM: NEON optimised FFT and MDCT
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119 vsub.f32 q9, q2, q9 @ {r2,i2,r3,i3}
7a63015e4627 ARM: NEON optimised FFT and MDCT
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120 vmul.f32 d25, d23, d3
7a63015e4627 ARM: NEON optimised FFT and MDCT
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diff changeset
121 vuzp.32 d16, d17 @ {r0,r1,i0,i1}
7a63015e4627 ARM: NEON optimised FFT and MDCT
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diff changeset
122 vmul.f32 q1, q11, d2[1]
7a63015e4627 ARM: NEON optimised FFT and MDCT
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123 vuzp.32 d18, d19 @ {r2,r3,i2,i3}
7a63015e4627 ARM: NEON optimised FFT and MDCT
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diff changeset
124 vrev64.32 q12, q12
7a63015e4627 ARM: NEON optimised FFT and MDCT
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125 vadd.f32 q11, q12, q1 @ {t1a,t2a,t5,t6}
7a63015e4627 ARM: NEON optimised FFT and MDCT
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126 vld1.32 {d24-d27}, [r0,:128]! @ q12{r8,i8,r9,i9} q13{r10,i10,r11,i11}
7a63015e4627 ARM: NEON optimised FFT and MDCT
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127 vzip.32 q10, q11
7a63015e4627 ARM: NEON optimised FFT and MDCT
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128 vld1.32 {d28-d31}, [r0,:128] @ q14{r12,i12,r13,i13} q15{r14,i14,r15,i15}
7a63015e4627 ARM: NEON optimised FFT and MDCT
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129 vadd.f32 d0, d22, d20
7a63015e4627 ARM: NEON optimised FFT and MDCT
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130 vadd.f32 d1, d21, d23
7a63015e4627 ARM: NEON optimised FFT and MDCT
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131 vsub.f32 d2, d21, d23
7a63015e4627 ARM: NEON optimised FFT and MDCT
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132 vsub.f32 d3, d22, d20
7a63015e4627 ARM: NEON optimised FFT and MDCT
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133 sub r0, r0, #96
7a63015e4627 ARM: NEON optimised FFT and MDCT
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134 vext.32 q13, q13, q13, #1
7a63015e4627 ARM: NEON optimised FFT and MDCT
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135 vsub.f32 q10, q8, q0 @ {r4,r5,i4,i5}
7a63015e4627 ARM: NEON optimised FFT and MDCT
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136 vadd.f32 q8, q8, q0 @ {r0,r1,i0,i1}
7a63015e4627 ARM: NEON optimised FFT and MDCT
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137 vext.32 q15, q15, q15, #1
7a63015e4627 ARM: NEON optimised FFT and MDCT
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138 vsub.f32 q11, q9, q1 @ {r6,r7,i6,i7}
7a63015e4627 ARM: NEON optimised FFT and MDCT
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diff changeset
139 vswp d25, d26 @ q12{r8,i8,i10,r11} q13{r9,i9,i11,r10}
7a63015e4627 ARM: NEON optimised FFT and MDCT
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diff changeset
140 vadd.f32 q9, q9, q1 @ {r2,r3,i2,i3}
7a63015e4627 ARM: NEON optimised FFT and MDCT
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diff changeset
141 vswp d29, d30 @ q14{r12,i12,i14,r15} q15{r13,i13,i15,r14}
7a63015e4627 ARM: NEON optimised FFT and MDCT
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142 vadd.f32 q0, q12, q13 @ {t1,t2,t5,t6}
7a63015e4627 ARM: NEON optimised FFT and MDCT
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143 vadd.f32 q1, q14, q15 @ {t1a,t2a,t5a,t6a}
7a63015e4627 ARM: NEON optimised FFT and MDCT
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144 movrel r2, ff_cos_16
7a63015e4627 ARM: NEON optimised FFT and MDCT
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145 vsub.f32 q13, q12, q13 @ {t3,t4,t7,t8}
7a63015e4627 ARM: NEON optimised FFT and MDCT
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diff changeset
146 vrev64.32 d1, d1
7a63015e4627 ARM: NEON optimised FFT and MDCT
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diff changeset
147 vsub.f32 q15, q14, q15 @ {t3a,t4a,t7a,t8a}
7a63015e4627 ARM: NEON optimised FFT and MDCT
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148 vrev64.32 d3, d3
7a63015e4627 ARM: NEON optimised FFT and MDCT
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149 movrel r3, pmmp
7a63015e4627 ARM: NEON optimised FFT and MDCT
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150 vswp d1, d26 @ q0{t1,t2,t3,t4} q13{t6,t5,t7,t8}
7a63015e4627 ARM: NEON optimised FFT and MDCT
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151 vswp d3, d30 @ q1{t1a,t2a,t3a,t4a} q15{t6a,t5a,t7a,t8a}
7a63015e4627 ARM: NEON optimised FFT and MDCT
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diff changeset
152 vadd.f32 q12, q0, q13 @ {r8,i8,r9,i9}
7a63015e4627 ARM: NEON optimised FFT and MDCT
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153 vadd.f32 q14, q1, q15 @ {r12,i12,r13,i13}
7a63015e4627 ARM: NEON optimised FFT and MDCT
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154 vld1.32 {d4-d5}, [r2,:64]
7a63015e4627 ARM: NEON optimised FFT and MDCT
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155 vsub.f32 q13, q0, q13 @ {r10,i10,r11,i11}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
156 vsub.f32 q15, q1, q15 @ {r14,i14,r15,i15}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
157 vswp d25, d28 @ q12{r8,i8,r12,i12} q14{r9,i9,r13,i13}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
158 vld1.32 {d6-d7}, [r3,:128]
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
159 vrev64.32 q1, q14
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
160 vmul.f32 q14, q14, d4[1]
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
161 vmul.f32 q1, q1, q3
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
162 vmla.f32 q14, q1, d5[1] @ {t1a,t2a,t5a,t6a}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
163 vswp d27, d30 @ q13{r10,i10,r14,i14} q15{r11,i11,r15,i15}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
164 vzip.32 q12, q14
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
165 vadd.f32 d0, d28, d24
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
166 vadd.f32 d1, d25, d29
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
167 vsub.f32 d2, d25, d29
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
168 vsub.f32 d3, d28, d24
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
169 vsub.f32 q12, q8, q0 @ {r8,r9,i8,i9}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
170 vadd.f32 q8, q8, q0 @ {r0,r1,i0,i1}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
171 vsub.f32 q14, q10, q1 @ {r12,r13,i12,i13}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
172 mov r1, #32
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
173 vadd.f32 q10, q10, q1 @ {r4,r5,i4,i5}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
174 vrev64.32 q0, q13
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
175 vmul.f32 q13, q13, d5[0]
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
176 vrev64.32 q1, q15
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
177 vmul.f32 q15, q15, d5[1]
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
178 vst2.32 {d16-d17},[r0,:128], r1
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
179 vmul.f32 q0, q0, q3
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
180 vst2.32 {d20-d21},[r0,:128], r1
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
181 vmul.f32 q1, q1, q3
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
182 vmla.f32 q13, q0, d5[0] @ {t1,t2,t5,t6}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
183 vmla.f32 q15, q1, d4[1] @ {t1a,t2a,t5a,t6a}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
184 vst2.32 {d24-d25},[r0,:128], r1
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
185 vst2.32 {d28-d29},[r0,:128]
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
186 vzip.32 q13, q15
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
187 sub r0, r0, #80
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
188 vadd.f32 d0, d30, d26
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
189 vadd.f32 d1, d27, d31
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
190 vsub.f32 d2, d27, d31
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
191 vsub.f32 d3, d30, d26
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
192 vsub.f32 q13, q9, q0 @ {r10,r11,i10,i11}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
193 vadd.f32 q9, q9, q0 @ {r2,r3,i2,i3}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
194 vsub.f32 q15, q11, q1 @ {r14,r15,i14,i15}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
195 vadd.f32 q11, q11, q1 @ {r6,r7,i6,i7}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
196 vst2.32 {d18-d19},[r0,:128], r1
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
197 vst2.32 {d22-d23},[r0,:128], r1
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
198 vst2.32 {d26-d27},[r0,:128], r1
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
199 vst2.32 {d30-d31},[r0,:128]
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
200 bx lr
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
201 .endfunc
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
202
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
203 function fft_pass_neon
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
204 push {r4-r6,lr}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
205 mov r6, r2 @ n
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
206 lsl r5, r2, #3 @ 2 * n * sizeof FFTSample
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
207 lsl r4, r2, #4 @ 2 * n * sizeof FFTComplex
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
208 lsl r2, r2, #5 @ 4 * n * sizeof FFTComplex
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
209 add r3, r2, r4
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
210 add r4, r4, r0 @ &z[o1]
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
211 add r2, r2, r0 @ &z[o2]
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
212 add r3, r3, r0 @ &z[o3]
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
213 vld1.32 {d20-d21},[r2,:128] @ {z[o2],z[o2+1]}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
214 movrel r12, pmmp
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
215 vld1.32 {d22-d23},[r3,:128] @ {z[o3],z[o3+1]}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
216 add r5, r5, r1 @ wim
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
217 vld1.32 {d6-d7}, [r12,:128] @ pmmp
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
218 vswp d21, d22
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
219 vld1.32 {d4}, [r1,:64]! @ {wre[0],wre[1]}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
220 sub r5, r5, #4 @ wim--
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
221 vrev64.32 q1, q11
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
222 vmul.f32 q11, q11, d4[1]
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
223 vmul.f32 q1, q1, q3
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
224 vld1.32 {d5[0]}, [r5,:32] @ d5[0] = wim[-1]
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
225 vmla.f32 q11, q1, d5[0] @ {t1a,t2a,t5a,t6a}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
226 vld2.32 {d16-d17},[r0,:128] @ {z[0],z[1]}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
227 sub r6, r6, #1 @ n--
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
228 vld2.32 {d18-d19},[r4,:128] @ {z[o1],z[o1+1]}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
229 vzip.32 q10, q11
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
230 vadd.f32 d0, d22, d20
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
231 vadd.f32 d1, d21, d23
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
232 vsub.f32 d2, d21, d23
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
233 vsub.f32 d3, d22, d20
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
234 vsub.f32 q10, q8, q0
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
235 vadd.f32 q8, q8, q0
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
236 vsub.f32 q11, q9, q1
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
237 vadd.f32 q9, q9, q1
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
238 vst2.32 {d20-d21},[r2,:128]! @ {z[o2],z[o2+1]}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
239 vst2.32 {d16-d17},[r0,:128]! @ {z[0],z[1]}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
240 vst2.32 {d22-d23},[r3,:128]! @ {z[o3],z[o3+1]}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
241 vst2.32 {d18-d19},[r4,:128]! @ {z[o1],z[o1+1]}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
242 sub r5, r5, #8 @ wim -= 2
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
243 1:
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
244 vld1.32 {d20-d21},[r2,:128] @ {z[o2],z[o2+1]}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
245 vld1.32 {d22-d23},[r3,:128] @ {z[o3],z[o3+1]}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
246 vswp d21, d22
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
247 vld1.32 {d4}, [r1]! @ {wre[0],wre[1]}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
248 vrev64.32 q0, q10
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
249 vmul.f32 q10, q10, d4[0]
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
250 vrev64.32 q1, q11
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
251 vmul.f32 q11, q11, d4[1]
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
252 vld1.32 {d5}, [r5] @ {wim[-1],wim[0]}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
253 vmul.f32 q0, q0, q3
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
254 sub r5, r5, #8 @ wim -= 2
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
255 vmul.f32 q1, q1, q3
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
256 vmla.f32 q10, q0, d5[1] @ {t1,t2,t5,t6}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
257 vmla.f32 q11, q1, d5[0] @ {t1a,t2a,t5a,t6a}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
258 vld2.32 {d16-d17},[r0,:128] @ {z[0],z[1]}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
259 subs r6, r6, #1 @ n--
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
260 vld2.32 {d18-d19},[r4,:128] @ {z[o1],z[o1+1]}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
261 vzip.32 q10, q11
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
262 vadd.f32 d0, d22, d20
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
263 vadd.f32 d1, d21, d23
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
264 vsub.f32 d2, d21, d23
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
265 vsub.f32 d3, d22, d20
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
266 vsub.f32 q10, q8, q0
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
267 vadd.f32 q8, q8, q0
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
268 vsub.f32 q11, q9, q1
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
269 vadd.f32 q9, q9, q1
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
270 vst2.32 {d20-d21}, [r2,:128]! @ {z[o2],z[o2+1]}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
271 vst2.32 {d16-d17}, [r0,:128]! @ {z[0],z[1]}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
272 vst2.32 {d22-d23}, [r3,:128]! @ {z[o3],z[o3+1]}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
273 vst2.32 {d18-d19}, [r4,:128]! @ {z[o1],z[o1+1]}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
274 bne 1b
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
275
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
276 pop {r4-r6,pc}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
277 .endfunc
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
278
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
279 .macro def_fft n, n2, n4
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
280 .align 6
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
281 function fft\n\()_neon
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
282 push {r4, lr}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
283 mov r4, r0
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
284 bl fft\n2\()_neon
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
285 add r0, r4, #\n4*2*8
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
286 bl fft\n4\()_neon
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
287 add r0, r4, #\n4*3*8
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
288 bl fft\n4\()_neon
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
289 mov r0, r4
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
290 pop {r4, lr}
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
291 movrel r1, ff_cos_\n
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
292 mov r2, #\n4/2
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
293 b fft_pass_neon
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
294 .endfunc
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
295 .endm
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
296
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
297 def_fft 32, 16, 8
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
298 def_fft 64, 32, 16
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
299 def_fft 128, 64, 32
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
300 def_fft 256, 128, 64
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
301 def_fft 512, 256, 128
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
302 def_fft 1024, 512, 256
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
303 def_fft 2048, 1024, 512
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
304 def_fft 4096, 2048, 1024
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
305 def_fft 8192, 4096, 2048
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
306 def_fft 16384, 8192, 4096
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
307 def_fft 32768, 16384, 8192
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
308 def_fft 65536, 32768, 16384
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
309
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
310 function ff_fft_calc_neon, export=1
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
311 ldr r2, [r0]
7a63015e4627 ARM: NEON optimised FFT and MDCT
mru
parents:
diff changeset
312 sub r2, r2, #2
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313 movrel r3, fft_tab_neon
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314 ldr r3, [r3, r2, lsl #2]
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315 mov r0, r1
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316 bx r3
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317 .endfunc
7a63015e4627 ARM: NEON optimised FFT and MDCT
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318
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319 function ff_fft_permute_neon, export=1
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320 push {r4,lr}
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321 mov r12, #1
7a63015e4627 ARM: NEON optimised FFT and MDCT
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322 ldr r2, [r0] @ nbits
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323 ldr r3, [r0, #20] @ tmp_buf
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324 ldr r0, [r0, #8] @ revtab
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325 lsl r12, r12, r2
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326 mov r2, r12
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327 1:
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328 vld1.32 {d0-d1}, [r1,:128]!
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329 ldr r4, [r0], #4
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330 uxtah lr, r3, r4
7a63015e4627 ARM: NEON optimised FFT and MDCT
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331 uxtah r4, r3, r4, ror #16
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332 vst1.32 {d0}, [lr,:64]
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333 vst1.32 {d1}, [r4,:64]
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334 subs r12, r12, #2
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335 bgt 1b
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336
7a63015e4627 ARM: NEON optimised FFT and MDCT
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337 sub r1, r1, r2, lsl #3
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338 1:
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339 vld1.32 {d0-d3}, [r3,:128]!
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340 vst1.32 {d0-d3}, [r1,:128]!
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341 subs r2, r2, #4
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342 bgt 1b
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343
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344 pop {r4,pc}
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345 .endfunc
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346
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347 .section .rodata
7a63015e4627 ARM: NEON optimised FFT and MDCT
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348 .align 4
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349 fft_tab_neon:
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350 .word fft4_neon
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351 .word fft8_neon
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352 .word fft16_neon
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353 .word fft32_neon
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354 .word fft64_neon
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355 .word fft128_neon
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356 .word fft256_neon
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357 .word fft512_neon
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358 .word fft1024_neon
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359 .word fft2048_neon
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360 .word fft4096_neon
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361 .word fft8192_neon
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362 .word fft16384_neon
7a63015e4627 ARM: NEON optimised FFT and MDCT
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363 .word fft32768_neon
7a63015e4627 ARM: NEON optimised FFT and MDCT
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364 .word fft65536_neon
7a63015e4627 ARM: NEON optimised FFT and MDCT
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365 .size fft_tab_neon, . - fft_tab_neon
7a63015e4627 ARM: NEON optimised FFT and MDCT
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366
7a63015e4627 ARM: NEON optimised FFT and MDCT
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367 .align 4
7a63015e4627 ARM: NEON optimised FFT and MDCT
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368 pmmp: .float +1.0, -1.0, -1.0, +1.0
7a63015e4627 ARM: NEON optimised FFT and MDCT
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369 mppm: .float -M_SQRT1_2, M_SQRT1_2, M_SQRT1_2, -M_SQRT1_2