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1 /* mmx.h
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2
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3 MultiMedia eXtensions GCC interface library for IA32.
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4
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5 To use this library, simply include this header file
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6 and compile with GCC. You MUST have inlining enabled
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7 in order for mmx_ok() to work; this can be done by
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8 simply using -O on the GCC command line.
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9
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10 Compiling with -DMMX_TRACE will cause detailed trace
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11 output to be sent to stderr for each mmx operation.
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12 This adds lots of code, and obviously slows execution to
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13 a crawl, but can be very useful for debugging.
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14
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15 THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
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16 EXPRESS OR IMPLIED WARRANTIES, INCLUDING, WITHOUT
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17 LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY
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18 AND FITNESS FOR ANY PARTICULAR PURPOSE.
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19
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20 1997-99 by H. Dietz and R. Fisher
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21
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22 Notes:
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23 It appears that the latest gas has the pand problem fixed, therefore
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24 I'll undefine BROKEN_PAND by default.
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25 */
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26
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27 #ifndef _MMX_H
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28 #define _MMX_H
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29
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30
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31 /* Warning: at this writing, the version of GAS packaged
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32 with most Linux distributions does not handle the
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33 parallel AND operation mnemonic correctly. If the
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34 symbol BROKEN_PAND is defined, a slower alternative
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35 coding will be used. If execution of mmxtest results
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36 in an illegal instruction fault, define this symbol.
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37 */
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38 #undef BROKEN_PAND
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39
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40
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41 /* The type of an value that fits in an MMX register
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42 (note that long long constant values MUST be suffixed
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43 by LL and unsigned long long values by ULL, lest
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44 they be truncated by the compiler)
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45 */
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46 typedef union {
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47 long long q; /* Quadword (64-bit) value */
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48 unsigned long long uq; /* Unsigned Quadword */
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49 int d[2]; /* 2 Doubleword (32-bit) values */
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50 unsigned int ud[2]; /* 2 Unsigned Doubleword */
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51 short w[4]; /* 4 Word (16-bit) values */
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52 unsigned short uw[4]; /* 4 Unsigned Word */
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53 char b[8]; /* 8 Byte (8-bit) values */
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54 unsigned char ub[8]; /* 8 Unsigned Byte */
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55 float s[2]; /* Single-precision (32-bit) value */
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56 } __attribute__ ((aligned (8))) mmx_t; /* On an 8-byte (64-bit) boundary */
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57
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58
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59 /* Helper functions for the instruction macros that follow...
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60 (note that memory-to-register, m2r, instructions are nearly
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61 as efficient as register-to-register, r2r, instructions;
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62 however, memory-to-memory instructions are really simulated
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63 as a convenience, and are only 1/3 as efficient)
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64 */
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65 #ifdef MMX_TRACE
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66
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67 /* Include the stuff for printing a trace to stderr...
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68 */
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69
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70 #include <stdio.h>
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71
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72 #define mmx_i2r(op, imm, reg) \
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73 { \
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74 mmx_t mmx_trace; \
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75 mmx_trace.uq = (imm); \
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76 fprintf(stderr, #op "_i2r(" #imm "=0x%08x%08x, ", \
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77 mmx_trace.d[1], mmx_trace.d[0]); \
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78 __asm__ __volatile__ ("movq %%" #reg ", %0" \
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79 : "=X" (mmx_trace) \
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80 : /* nothing */ ); \
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81 fprintf(stderr, #reg "=0x%08x%08x) => ", \
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82 mmx_trace.d[1], mmx_trace.d[0]); \
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83 __asm__ __volatile__ (#op " %0, %%" #reg \
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84 : /* nothing */ \
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85 : "X" (imm)); \
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86 __asm__ __volatile__ ("movq %%" #reg ", %0" \
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87 : "=X" (mmx_trace) \
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88 : /* nothing */ ); \
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89 fprintf(stderr, #reg "=0x%08x%08x\n", \
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90 mmx_trace.d[1], mmx_trace.d[0]); \
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91 }
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92
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93 #define mmx_m2r(op, mem, reg) \
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94 { \
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95 mmx_t mmx_trace; \
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96 mmx_trace = (mem); \
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97 fprintf(stderr, #op "_m2r(" #mem "=0x%08x%08x, ", \
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98 mmx_trace.d[1], mmx_trace.d[0]); \
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99 __asm__ __volatile__ ("movq %%" #reg ", %0" \
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100 : "=X" (mmx_trace) \
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101 : /* nothing */ ); \
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102 fprintf(stderr, #reg "=0x%08x%08x) => ", \
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103 mmx_trace.d[1], mmx_trace.d[0]); \
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104 __asm__ __volatile__ (#op " %0, %%" #reg \
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105 : /* nothing */ \
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106 : "X" (mem)); \
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107 __asm__ __volatile__ ("movq %%" #reg ", %0" \
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108 : "=X" (mmx_trace) \
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109 : /* nothing */ ); \
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110 fprintf(stderr, #reg "=0x%08x%08x\n", \
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111 mmx_trace.d[1], mmx_trace.d[0]); \
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112 }
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113
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114 #define mmx_r2m(op, reg, mem) \
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115 { \
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116 mmx_t mmx_trace; \
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117 __asm__ __volatile__ ("movq %%" #reg ", %0" \
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118 : "=X" (mmx_trace) \
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119 : /* nothing */ ); \
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120 fprintf(stderr, #op "_r2m(" #reg "=0x%08x%08x, ", \
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121 mmx_trace.d[1], mmx_trace.d[0]); \
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122 mmx_trace = (mem); \
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123 fprintf(stderr, #mem "=0x%08x%08x) => ", \
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124 mmx_trace.d[1], mmx_trace.d[0]); \
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125 __asm__ __volatile__ (#op " %%" #reg ", %0" \
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126 : "=X" (mem) \
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127 : /* nothing */ ); \
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128 mmx_trace = (mem); \
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129 fprintf(stderr, #mem "=0x%08x%08x\n", \
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130 mmx_trace.d[1], mmx_trace.d[0]); \
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131 }
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132
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133 #define mmx_r2r(op, regs, regd) \
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134 { \
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135 mmx_t mmx_trace; \
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136 __asm__ __volatile__ ("movq %%" #regs ", %0" \
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137 : "=X" (mmx_trace) \
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138 : /* nothing */ ); \
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139 fprintf(stderr, #op "_r2r(" #regs "=0x%08x%08x, ", \
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140 mmx_trace.d[1], mmx_trace.d[0]); \
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141 __asm__ __volatile__ ("movq %%" #regd ", %0" \
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142 : "=X" (mmx_trace) \
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143 : /* nothing */ ); \
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144 fprintf(stderr, #regd "=0x%08x%08x) => ", \
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145 mmx_trace.d[1], mmx_trace.d[0]); \
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146 __asm__ __volatile__ (#op " %" #regs ", %" #regd); \
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147 __asm__ __volatile__ ("movq %%" #regd ", %0" \
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148 : "=X" (mmx_trace) \
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149 : /* nothing */ ); \
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150 fprintf(stderr, #regd "=0x%08x%08x\n", \
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151 mmx_trace.d[1], mmx_trace.d[0]); \
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152 }
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153
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154 #define mmx_m2m(op, mems, memd) \
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155 { \
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156 mmx_t mmx_trace; \
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157 mmx_trace = (mems); \
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158 fprintf(stderr, #op "_m2m(" #mems "=0x%08x%08x, ", \
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159 mmx_trace.d[1], mmx_trace.d[0]); \
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160 mmx_trace = (memd); \
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161 fprintf(stderr, #memd "=0x%08x%08x) => ", \
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162 mmx_trace.d[1], mmx_trace.d[0]); \
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163 __asm__ __volatile__ ("movq %0, %%mm0\n\t" \
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164 #op " %1, %%mm0\n\t" \
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165 "movq %%mm0, %0" \
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166 : "=X" (memd) \
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167 : "X" (mems)); \
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168 mmx_trace = (memd); \
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169 fprintf(stderr, #memd "=0x%08x%08x\n", \
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170 mmx_trace.d[1], mmx_trace.d[0]); \
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171 }
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172
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173 #else
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174
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175 /* These macros are a lot simpler without the tracing...
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176 */
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177
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178 #define mmx_i2r(op, imm, reg) \
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179 __asm__ __volatile__ (#op " %0, %%" #reg \
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180 : /* nothing */ \
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181 : "i" (imm) )
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182
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183 #define mmx_m2r(op, mem, reg) \
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184 __asm__ __volatile__ (#op " %0, %%" #reg \
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185 : /* nothing */ \
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186 : "m" (mem))
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187
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188 #define mmx_r2m(op, reg, mem) \
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189 __asm__ __volatile__ (#op " %%" #reg ", %0" \
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190 : "=m" (mem) \
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191 : /* nothing */ )
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192
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193 #define mmx_r2r(op, regs, regd) \
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194 __asm__ __volatile__ (#op " %" #regs ", %" #regd)
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195
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196 #define mmx_m2m(op, mems, memd) \
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197 __asm__ __volatile__ ("movq %0, %%mm0\n\t" \
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198 #op " %1, %%mm0\n\t" \
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199 "movq %%mm0, %0" \
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200 : "=m" (memd) \
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201 : "m" (mems))
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202
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203 #endif
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204
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205
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206 /* 1x64 MOVe Quadword
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207 (this is both a load and a store...
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208 in fact, it is the only way to store)
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209 */
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210 #define movq_m2r(var, reg) mmx_m2r(movq, var, reg)
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211 #define movq_r2m(reg, var) mmx_r2m(movq, reg, var)
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212 #define movq_r2r(regs, regd) mmx_r2r(movq, regs, regd)
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213 #define movq(vars, vard) \
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214 __asm__ __volatile__ ("movq %1, %%mm0\n\t" \
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215 "movq %%mm0, %0" \
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216 : "=X" (vard) \
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217 : "X" (vars))
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218
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219
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220 /* 1x32 MOVe Doubleword
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221 (like movq, this is both load and store...
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222 but is most useful for moving things between
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223 mmx registers and ordinary registers)
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224 */
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225 #define movd_m2r(var, reg) mmx_m2r(movd, var, reg)
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226 #define movd_r2m(reg, var) mmx_r2m(movd, reg, var)
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227 #define movd_r2r(regs, regd) mmx_r2r(movd, regs, regd)
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228 #define movd(vars, vard) \
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229 __asm__ __volatile__ ("movd %1, %%mm0\n\t" \
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230 "movd %%mm0, %0" \
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231 : "=X" (vard) \
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232 : "X" (vars))
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233
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234
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235 /* 2x32, 4x16, and 8x8 Parallel ADDs
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236 */
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237 #define paddd_m2r(var, reg) mmx_m2r(paddd, var, reg)
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238 #define paddd_r2r(regs, regd) mmx_r2r(paddd, regs, regd)
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239 #define paddd(vars, vard) mmx_m2m(paddd, vars, vard)
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240
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241 #define paddw_m2r(var, reg) mmx_m2r(paddw, var, reg)
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242 #define paddw_r2r(regs, regd) mmx_r2r(paddw, regs, regd)
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243 #define paddw(vars, vard) mmx_m2m(paddw, vars, vard)
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244
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245 #define paddb_m2r(var, reg) mmx_m2r(paddb, var, reg)
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246 #define paddb_r2r(regs, regd) mmx_r2r(paddb, regs, regd)
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247 #define paddb(vars, vard) mmx_m2m(paddb, vars, vard)
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248
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249
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250 /* 4x16 and 8x8 Parallel ADDs using Saturation arithmetic
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251 */
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252 #define paddsw_m2r(var, reg) mmx_m2r(paddsw, var, reg)
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253 #define paddsw_r2r(regs, regd) mmx_r2r(paddsw, regs, regd)
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254 #define paddsw(vars, vard) mmx_m2m(paddsw, vars, vard)
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255
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256 #define paddsb_m2r(var, reg) mmx_m2r(paddsb, var, reg)
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257 #define paddsb_r2r(regs, regd) mmx_r2r(paddsb, regs, regd)
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258 #define paddsb(vars, vard) mmx_m2m(paddsb, vars, vard)
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259
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260
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261 /* 4x16 and 8x8 Parallel ADDs using Unsigned Saturation arithmetic
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262 */
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263 #define paddusw_m2r(var, reg) mmx_m2r(paddusw, var, reg)
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264 #define paddusw_r2r(regs, regd) mmx_r2r(paddusw, regs, regd)
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265 #define paddusw(vars, vard) mmx_m2m(paddusw, vars, vard)
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266
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267 #define paddusb_m2r(var, reg) mmx_m2r(paddusb, var, reg)
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268 #define paddusb_r2r(regs, regd) mmx_r2r(paddusb, regs, regd)
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269 #define paddusb(vars, vard) mmx_m2m(paddusb, vars, vard)
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270
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271
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272 /* 2x32, 4x16, and 8x8 Parallel SUBs
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273 */
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274 #define psubd_m2r(var, reg) mmx_m2r(psubd, var, reg)
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275 #define psubd_r2r(regs, regd) mmx_r2r(psubd, regs, regd)
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276 #define psubd(vars, vard) mmx_m2m(psubd, vars, vard)
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277
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278 #define psubw_m2r(var, reg) mmx_m2r(psubw, var, reg)
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279 #define psubw_r2r(regs, regd) mmx_r2r(psubw, regs, regd)
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280 #define psubw(vars, vard) mmx_m2m(psubw, vars, vard)
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281
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282 #define psubb_m2r(var, reg) mmx_m2r(psubb, var, reg)
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283 #define psubb_r2r(regs, regd) mmx_r2r(psubb, regs, regd)
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284 #define psubb(vars, vard) mmx_m2m(psubb, vars, vard)
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285
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286
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287 /* 4x16 and 8x8 Parallel SUBs using Saturation arithmetic
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288 */
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289 #define psubsw_m2r(var, reg) mmx_m2r(psubsw, var, reg)
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290 #define psubsw_r2r(regs, regd) mmx_r2r(psubsw, regs, regd)
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291 #define psubsw(vars, vard) mmx_m2m(psubsw, vars, vard)
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292
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293 #define psubsb_m2r(var, reg) mmx_m2r(psubsb, var, reg)
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294 #define psubsb_r2r(regs, regd) mmx_r2r(psubsb, regs, regd)
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295 #define psubsb(vars, vard) mmx_m2m(psubsb, vars, vard)
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296
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297
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298 /* 4x16 and 8x8 Parallel SUBs using Unsigned Saturation arithmetic
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299 */
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300 #define psubusw_m2r(var, reg) mmx_m2r(psubusw, var, reg)
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301 #define psubusw_r2r(regs, regd) mmx_r2r(psubusw, regs, regd)
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302 #define psubusw(vars, vard) mmx_m2m(psubusw, vars, vard)
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303
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304 #define psubusb_m2r(var, reg) mmx_m2r(psubusb, var, reg)
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305 #define psubusb_r2r(regs, regd) mmx_r2r(psubusb, regs, regd)
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306 #define psubusb(vars, vard) mmx_m2m(psubusb, vars, vard)
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307
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308
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309 /* 4x16 Parallel MULs giving Low 4x16 portions of results
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310 */
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311 #define pmullw_m2r(var, reg) mmx_m2r(pmullw, var, reg)
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312 #define pmullw_r2r(regs, regd) mmx_r2r(pmullw, regs, regd)
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313 #define pmullw(vars, vard) mmx_m2m(pmullw, vars, vard)
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314
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315
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316 /* 4x16 Parallel MULs giving High 4x16 portions of results
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317 */
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318 #define pmulhw_m2r(var, reg) mmx_m2r(pmulhw, var, reg)
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319 #define pmulhw_r2r(regs, regd) mmx_r2r(pmulhw, regs, regd)
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320 #define pmulhw(vars, vard) mmx_m2m(pmulhw, vars, vard)
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321
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322
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323 /* 4x16->2x32 Parallel Mul-ADD
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324 (muls like pmullw, then adds adjacent 16-bit fields
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325 in the multiply result to make the final 2x32 result)
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326 */
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327 #define pmaddwd_m2r(var, reg) mmx_m2r(pmaddwd, var, reg)
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328 #define pmaddwd_r2r(regs, regd) mmx_r2r(pmaddwd, regs, regd)
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329 #define pmaddwd(vars, vard) mmx_m2m(pmaddwd, vars, vard)
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330
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331
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332 /* 1x64 bitwise AND
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333 */
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334 #ifdef BROKEN_PAND
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335 #define pand_m2r(var, reg) \
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336 { \
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337 mmx_m2r(pandn, (mmx_t) -1LL, reg); \
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338 mmx_m2r(pandn, var, reg); \
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339 }
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340 #define pand_r2r(regs, regd) \
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341 { \
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342 mmx_m2r(pandn, (mmx_t) -1LL, regd); \
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343 mmx_r2r(pandn, regs, regd) \
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344 }
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345 #define pand(vars, vard) \
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346 { \
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347 movq_m2r(vard, mm0); \
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348 mmx_m2r(pandn, (mmx_t) -1LL, mm0); \
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349 mmx_m2r(pandn, vars, mm0); \
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350 movq_r2m(mm0, vard); \
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351 }
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352 #else
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353 #define pand_m2r(var, reg) mmx_m2r(pand, var, reg)
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354 #define pand_r2r(regs, regd) mmx_r2r(pand, regs, regd)
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355 #define pand(vars, vard) mmx_m2m(pand, vars, vard)
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356 #endif
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357
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358
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359 /* 1x64 bitwise AND with Not the destination
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360 */
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361 #define pandn_m2r(var, reg) mmx_m2r(pandn, var, reg)
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362 #define pandn_r2r(regs, regd) mmx_r2r(pandn, regs, regd)
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363 #define pandn(vars, vard) mmx_m2m(pandn, vars, vard)
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364
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365
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366 /* 1x64 bitwise OR
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367 */
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368 #define por_m2r(var, reg) mmx_m2r(por, var, reg)
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369 #define por_r2r(regs, regd) mmx_r2r(por, regs, regd)
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370 #define por(vars, vard) mmx_m2m(por, vars, vard)
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371
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372
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373 /* 1x64 bitwise eXclusive OR
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374 */
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375 #define pxor_m2r(var, reg) mmx_m2r(pxor, var, reg)
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376 #define pxor_r2r(regs, regd) mmx_r2r(pxor, regs, regd)
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377 #define pxor(vars, vard) mmx_m2m(pxor, vars, vard)
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378
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379
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380 /* 2x32, 4x16, and 8x8 Parallel CoMPare for EQuality
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381 (resulting fields are either 0 or -1)
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382 */
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383 #define pcmpeqd_m2r(var, reg) mmx_m2r(pcmpeqd, var, reg)
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384 #define pcmpeqd_r2r(regs, regd) mmx_r2r(pcmpeqd, regs, regd)
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385 #define pcmpeqd(vars, vard) mmx_m2m(pcmpeqd, vars, vard)
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386
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387 #define pcmpeqw_m2r(var, reg) mmx_m2r(pcmpeqw, var, reg)
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388 #define pcmpeqw_r2r(regs, regd) mmx_r2r(pcmpeqw, regs, regd)
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389 #define pcmpeqw(vars, vard) mmx_m2m(pcmpeqw, vars, vard)
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390
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391 #define pcmpeqb_m2r(var, reg) mmx_m2r(pcmpeqb, var, reg)
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392 #define pcmpeqb_r2r(regs, regd) mmx_r2r(pcmpeqb, regs, regd)
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393 #define pcmpeqb(vars, vard) mmx_m2m(pcmpeqb, vars, vard)
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394
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395
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396 /* 2x32, 4x16, and 8x8 Parallel CoMPare for Greater Than
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397 (resulting fields are either 0 or -1)
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398 */
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399 #define pcmpgtd_m2r(var, reg) mmx_m2r(pcmpgtd, var, reg)
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400 #define pcmpgtd_r2r(regs, regd) mmx_r2r(pcmpgtd, regs, regd)
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401 #define pcmpgtd(vars, vard) mmx_m2m(pcmpgtd, vars, vard)
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402
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403 #define pcmpgtw_m2r(var, reg) mmx_m2r(pcmpgtw, var, reg)
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404 #define pcmpgtw_r2r(regs, regd) mmx_r2r(pcmpgtw, regs, regd)
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405 #define pcmpgtw(vars, vard) mmx_m2m(pcmpgtw, vars, vard)
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406
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407 #define pcmpgtb_m2r(var, reg) mmx_m2r(pcmpgtb, var, reg)
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408 #define pcmpgtb_r2r(regs, regd) mmx_r2r(pcmpgtb, regs, regd)
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409 #define pcmpgtb(vars, vard) mmx_m2m(pcmpgtb, vars, vard)
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410
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411
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412 /* 1x64, 2x32, and 4x16 Parallel Shift Left Logical
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413 */
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414 #define psllq_i2r(imm, reg) mmx_i2r(psllq, imm, reg)
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415 #define psllq_m2r(var, reg) mmx_m2r(psllq, var, reg)
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416 #define psllq_r2r(regs, regd) mmx_r2r(psllq, regs, regd)
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417 #define psllq(vars, vard) mmx_m2m(psllq, vars, vard)
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418
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419 #define pslld_i2r(imm, reg) mmx_i2r(pslld, imm, reg)
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420 #define pslld_m2r(var, reg) mmx_m2r(pslld, var, reg)
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421 #define pslld_r2r(regs, regd) mmx_r2r(pslld, regs, regd)
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422 #define pslld(vars, vard) mmx_m2m(pslld, vars, vard)
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423
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424 #define psllw_i2r(imm, reg) mmx_i2r(psllw, imm, reg)
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425 #define psllw_m2r(var, reg) mmx_m2r(psllw, var, reg)
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426 #define psllw_r2r(regs, regd) mmx_r2r(psllw, regs, regd)
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427 #define psllw(vars, vard) mmx_m2m(psllw, vars, vard)
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428
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429
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430 /* 1x64, 2x32, and 4x16 Parallel Shift Right Logical
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431 */
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432 #define psrlq_i2r(imm, reg) mmx_i2r(psrlq, imm, reg)
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433 #define psrlq_m2r(var, reg) mmx_m2r(psrlq, var, reg)
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434 #define psrlq_r2r(regs, regd) mmx_r2r(psrlq, regs, regd)
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435 #define psrlq(vars, vard) mmx_m2m(psrlq, vars, vard)
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436
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437 #define psrld_i2r(imm, reg) mmx_i2r(psrld, imm, reg)
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438 #define psrld_m2r(var, reg) mmx_m2r(psrld, var, reg)
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439 #define psrld_r2r(regs, regd) mmx_r2r(psrld, regs, regd)
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440 #define psrld(vars, vard) mmx_m2m(psrld, vars, vard)
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441
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442 #define psrlw_i2r(imm, reg) mmx_i2r(psrlw, imm, reg)
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443 #define psrlw_m2r(var, reg) mmx_m2r(psrlw, var, reg)
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444 #define psrlw_r2r(regs, regd) mmx_r2r(psrlw, regs, regd)
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445 #define psrlw(vars, vard) mmx_m2m(psrlw, vars, vard)
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446
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447
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448 /* 2x32 and 4x16 Parallel Shift Right Arithmetic
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449 */
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450 #define psrad_i2r(imm, reg) mmx_i2r(psrad, imm, reg)
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451 #define psrad_m2r(var, reg) mmx_m2r(psrad, var, reg)
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452 #define psrad_r2r(regs, regd) mmx_r2r(psrad, regs, regd)
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453 #define psrad(vars, vard) mmx_m2m(psrad, vars, vard)
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454
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455 #define psraw_i2r(imm, reg) mmx_i2r(psraw, imm, reg)
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456 #define psraw_m2r(var, reg) mmx_m2r(psraw, var, reg)
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457 #define psraw_r2r(regs, regd) mmx_r2r(psraw, regs, regd)
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458 #define psraw(vars, vard) mmx_m2m(psraw, vars, vard)
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459
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460
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461 /* 2x32->4x16 and 4x16->8x8 PACK and Signed Saturate
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462 (packs source and dest fields into dest in that order)
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463 */
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464 #define packssdw_m2r(var, reg) mmx_m2r(packssdw, var, reg)
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465 #define packssdw_r2r(regs, regd) mmx_r2r(packssdw, regs, regd)
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466 #define packssdw(vars, vard) mmx_m2m(packssdw, vars, vard)
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467
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468 #define packsswb_m2r(var, reg) mmx_m2r(packsswb, var, reg)
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469 #define packsswb_r2r(regs, regd) mmx_r2r(packsswb, regs, regd)
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470 #define packsswb(vars, vard) mmx_m2m(packsswb, vars, vard)
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471
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472
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473 /* 4x16->8x8 PACK and Unsigned Saturate
|
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474 (packs source and dest fields into dest in that order)
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475 */
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476 #define packuswb_m2r(var, reg) mmx_m2r(packuswb, var, reg)
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477 #define packuswb_r2r(regs, regd) mmx_r2r(packuswb, regs, regd)
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478 #define packuswb(vars, vard) mmx_m2m(packuswb, vars, vard)
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479
|
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480
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481 /* 2x32->1x64, 4x16->2x32, and 8x8->4x16 UNPaCK Low
|
|
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482 (interleaves low half of dest with low half of source
|
|
|
483 as padding in each result field)
|
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484 */
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485 #define punpckldq_m2r(var, reg) mmx_m2r(punpckldq, var, reg)
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486 #define punpckldq_r2r(regs, regd) mmx_r2r(punpckldq, regs, regd)
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487 #define punpckldq(vars, vard) mmx_m2m(punpckldq, vars, vard)
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488
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489 #define punpcklwd_m2r(var, reg) mmx_m2r(punpcklwd, var, reg)
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490 #define punpcklwd_r2r(regs, regd) mmx_r2r(punpcklwd, regs, regd)
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491 #define punpcklwd(vars, vard) mmx_m2m(punpcklwd, vars, vard)
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492
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493 #define punpcklbw_m2r(var, reg) mmx_m2r(punpcklbw, var, reg)
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494 #define punpcklbw_r2r(regs, regd) mmx_r2r(punpcklbw, regs, regd)
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495 #define punpcklbw(vars, vard) mmx_m2m(punpcklbw, vars, vard)
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496
|
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497
|
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498 /* 2x32->1x64, 4x16->2x32, and 8x8->4x16 UNPaCK High
|
|
|
499 (interleaves high half of dest with high half of source
|
|
|
500 as padding in each result field)
|
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501 */
|
|
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502 #define punpckhdq_m2r(var, reg) mmx_m2r(punpckhdq, var, reg)
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503 #define punpckhdq_r2r(regs, regd) mmx_r2r(punpckhdq, regs, regd)
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504 #define punpckhdq(vars, vard) mmx_m2m(punpckhdq, vars, vard)
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505
|
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506 #define punpckhwd_m2r(var, reg) mmx_m2r(punpckhwd, var, reg)
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507 #define punpckhwd_r2r(regs, regd) mmx_r2r(punpckhwd, regs, regd)
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508 #define punpckhwd(vars, vard) mmx_m2m(punpckhwd, vars, vard)
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509
|
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|
510 #define punpckhbw_m2r(var, reg) mmx_m2r(punpckhbw, var, reg)
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511 #define punpckhbw_r2r(regs, regd) mmx_r2r(punpckhbw, regs, regd)
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512 #define punpckhbw(vars, vard) mmx_m2m(punpckhbw, vars, vard)
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513
|
|
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514
|
|
|
515 /* Empty MMx State
|
|
|
516 (used to clean-up when going from mmx to float use
|
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|
517 of the registers that are shared by both; note that
|
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|
518 there is no float-to-mmx operation needed, because
|
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|
519 only the float tag word info is corruptible)
|
|
|
520 */
|
|
|
521 #ifdef MMX_TRACE
|
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522
|
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|
523 #define emms() \
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|
524 { \
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|
525 fprintf(stderr, "emms()\n"); \
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|
526 __asm__ __volatile__ ("emms"); \
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|
|
527 }
|
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528
|
|
|
529 #else
|
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530
|
|
|
531 #define emms() __asm__ __volatile__ ("emms")
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532
|
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|
533 #endif
|
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534
|
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535 #endif
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536
|
