annotate arm/dsputil_neon.S @ 11509:9adad5749f23 libavcodec

Reinitialize the h264 decoder context on every valid aspect ratio change, not only size changes. Patch by Janusz Krzysztofik foo=zyszt <jkr$foo@tis.icnet.pl>.
author stefano
date Thu, 18 Mar 2010 23:36:54 +0000
parents 361a5fcb4393
children 659f16d04776
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1 /*
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2 * ARM NEON optimised DSP functions
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3 * Copyright (c) 2008 Mans Rullgard <mans@mansr.com>
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4 *
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5 * This file is part of FFmpeg.
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6 *
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7 * FFmpeg is free software; you can redistribute it and/or
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8 * modify it under the terms of the GNU Lesser General Public
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9 * License as published by the Free Software Foundation; either
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10 * version 2.1 of the License, or (at your option) any later version.
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11 *
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12 * FFmpeg is distributed in the hope that it will be useful,
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13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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15 * Lesser General Public License for more details.
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16 *
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17 * You should have received a copy of the GNU Lesser General Public
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18 * License along with FFmpeg; if not, write to the Free Software
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19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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20 */
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21
10046
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
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22 #include "config.h"
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23 #include "asm.S"
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24
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
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25 preserve8
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
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26 .text
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27
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
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28 .macro pixels16 avg=0
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29 .if \avg
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30 mov ip, r0
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31 .endif
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32 1: vld1.64 {d0, d1}, [r1], r2
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33 vld1.64 {d2, d3}, [r1], r2
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34 vld1.64 {d4, d5}, [r1], r2
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35 pld [r1, r2, lsl #2]
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36 vld1.64 {d6, d7}, [r1], r2
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37 pld [r1]
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38 pld [r1, r2]
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39 pld [r1, r2, lsl #1]
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40 .if \avg
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93c20dd3da43 Add guaranteed alignment for loading dest pixels in avg_pixels16_neon
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41 vld1.64 {d16,d17}, [ip,:128], r2
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42 vrhadd.u8 q0, q0, q8
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43 vld1.64 {d18,d19}, [ip,:128], r2
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6bdd6dfc3574 ARM: NEON optimised put_pixels functions
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44 vrhadd.u8 q1, q1, q9
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93c20dd3da43 Add guaranteed alignment for loading dest pixels in avg_pixels16_neon
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45 vld1.64 {d20,d21}, [ip,:128], r2
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46 vrhadd.u8 q2, q2, q10
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47 vld1.64 {d22,d23}, [ip,:128], r2
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48 vrhadd.u8 q3, q3, q11
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49 .endif
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50 subs r3, r3, #4
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51 vst1.64 {d0, d1}, [r0,:128], r2
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52 vst1.64 {d2, d3}, [r0,:128], r2
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53 vst1.64 {d4, d5}, [r0,:128], r2
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54 vst1.64 {d6, d7}, [r0,:128], r2
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55 bne 1b
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56 bx lr
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57 .endm
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58
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
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59 .macro pixels16_x2 vhadd=vrhadd.u8
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60 1: vld1.64 {d0-d2}, [r1], r2
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61 vld1.64 {d4-d6}, [r1], r2
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62 pld [r1]
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63 pld [r1, r2]
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64 subs r3, r3, #2
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65 vext.8 q1, q0, q1, #1
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66 \vhadd q0, q0, q1
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67 vext.8 q3, q2, q3, #1
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68 \vhadd q2, q2, q3
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69 vst1.64 {d0, d1}, [r0,:128], r2
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70 vst1.64 {d4, d5}, [r0,:128], r2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
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71 bne 1b
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72 bx lr
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73 .endm
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74
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75 .macro pixels16_y2 vhadd=vrhadd.u8
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76 vld1.64 {d0, d1}, [r1], r2
2b3b9358bee7 ARM: Use fewer register in NEON put_pixels _y2 and _xy2
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parents: 9580
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77 vld1.64 {d2, d3}, [r1], r2
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78 1: subs r3, r3, #2
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79 \vhadd q2, q0, q1
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80 vld1.64 {d0, d1}, [r1], r2
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81 \vhadd q3, q0, q1
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2b3b9358bee7 ARM: Use fewer register in NEON put_pixels _y2 and _xy2
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82 vld1.64 {d2, d3}, [r1], r2
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83 pld [r1]
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84 pld [r1, r2]
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85 vst1.64 {d4, d5}, [r0,:128], r2
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86 vst1.64 {d6, d7}, [r0,:128], r2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
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87 bne 1b
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88 bx lr
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89 .endm
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
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90
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
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91 .macro pixels16_xy2 vshrn=vrshrn.u16 no_rnd=0
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92 vld1.64 {d0-d2}, [r1], r2
2b3b9358bee7 ARM: Use fewer register in NEON put_pixels _y2 and _xy2
conrad
parents: 9580
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93 vld1.64 {d4-d6}, [r1], r2
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94 .if \no_rnd
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95 vmov.i16 q13, #1
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96 .endif
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97 pld [r1]
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98 pld [r1, r2]
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99 vext.8 q1, q0, q1, #1
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
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100 vext.8 q3, q2, q3, #1
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
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101 vaddl.u8 q8, d0, d2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
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102 vaddl.u8 q10, d1, d3
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
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103 vaddl.u8 q9, d4, d6
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
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104 vaddl.u8 q11, d5, d7
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
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105 1: subs r3, r3, #2
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2b3b9358bee7 ARM: Use fewer register in NEON put_pixels _y2 and _xy2
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106 vld1.64 {d0-d2}, [r1], r2
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107 vadd.u16 q12, q8, q9
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
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108 pld [r1]
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109 .if \no_rnd
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110 vadd.u16 q12, q12, q13
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111 .endif
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112 vext.8 q15, q0, q1, #1
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113 vadd.u16 q1 , q10, q11
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114 \vshrn d28, q12, #2
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115 .if \no_rnd
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116 vadd.u16 q1, q1, q13
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117 .endif
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
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118 \vshrn d29, q1, #2
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119 vaddl.u8 q8, d0, d30
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2b3b9358bee7 ARM: Use fewer register in NEON put_pixels _y2 and _xy2
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120 vld1.64 {d2-d4}, [r1], r2
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121 vaddl.u8 q10, d1, d31
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122 vst1.64 {d28,d29}, [r0,:128], r2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
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123 vadd.u16 q12, q8, q9
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2b3b9358bee7 ARM: Use fewer register in NEON put_pixels _y2 and _xy2
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124 pld [r1, r2]
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125 .if \no_rnd
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126 vadd.u16 q12, q12, q13
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127 .endif
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128 vext.8 q2, q1, q2, #1
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
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129 vadd.u16 q0, q10, q11
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
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130 \vshrn d30, q12, #2
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131 .if \no_rnd
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
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132 vadd.u16 q0, q0, q13
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
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133 .endif
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
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134 \vshrn d31, q0, #2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
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135 vaddl.u8 q9, d2, d4
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
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136 vaddl.u8 q11, d3, d5
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
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137 vst1.64 {d30,d31}, [r0,:128], r2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
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138 bgt 1b
9581
2b3b9358bee7 ARM: Use fewer register in NEON put_pixels _y2 and _xy2
conrad
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139 bx lr
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140 .endm
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141
10375
199949177888 ARM: NEON avg_pixels8 and avg_h264_qpel8_mc00
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142 .macro pixels8 avg=0
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143 1: vld1.64 {d0}, [r1], r2
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144 vld1.64 {d1}, [r1], r2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
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145 vld1.64 {d2}, [r1], r2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
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146 pld [r1, r2, lsl #2]
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
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147 vld1.64 {d3}, [r1], r2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
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148 pld [r1]
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
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149 pld [r1, r2]
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
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150 pld [r1, r2, lsl #1]
10375
199949177888 ARM: NEON avg_pixels8 and avg_h264_qpel8_mc00
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151 .if \avg
199949177888 ARM: NEON avg_pixels8 and avg_h264_qpel8_mc00
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152 vld1.64 {d4}, [r0,:64], r2
199949177888 ARM: NEON avg_pixels8 and avg_h264_qpel8_mc00
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153 vrhadd.u8 d0, d0, d4
199949177888 ARM: NEON avg_pixels8 and avg_h264_qpel8_mc00
mru
parents: 10360
diff changeset
154 vld1.64 {d5}, [r0,:64], r2
199949177888 ARM: NEON avg_pixels8 and avg_h264_qpel8_mc00
mru
parents: 10360
diff changeset
155 vrhadd.u8 d1, d1, d5
199949177888 ARM: NEON avg_pixels8 and avg_h264_qpel8_mc00
mru
parents: 10360
diff changeset
156 vld1.64 {d6}, [r0,:64], r2
199949177888 ARM: NEON avg_pixels8 and avg_h264_qpel8_mc00
mru
parents: 10360
diff changeset
157 vrhadd.u8 d2, d2, d6
199949177888 ARM: NEON avg_pixels8 and avg_h264_qpel8_mc00
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parents: 10360
diff changeset
158 vld1.64 {d7}, [r0,:64], r2
199949177888 ARM: NEON avg_pixels8 and avg_h264_qpel8_mc00
mru
parents: 10360
diff changeset
159 vrhadd.u8 d3, d3, d7
199949177888 ARM: NEON avg_pixels8 and avg_h264_qpel8_mc00
mru
parents: 10360
diff changeset
160 sub r0, r0, r2, lsl #2
199949177888 ARM: NEON avg_pixels8 and avg_h264_qpel8_mc00
mru
parents: 10360
diff changeset
161 .endif
8334
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
162 subs r3, r3, #4
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
163 vst1.64 {d0}, [r0,:64], r2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
164 vst1.64 {d1}, [r0,:64], r2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
165 vst1.64 {d2}, [r0,:64], r2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
166 vst1.64 {d3}, [r0,:64], r2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
167 bne 1b
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
168 bx lr
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
169 .endm
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
170
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
171 .macro pixels8_x2 vhadd=vrhadd.u8
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
172 1: vld1.64 {d0, d1}, [r1], r2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
173 vext.8 d1, d0, d1, #1
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
174 vld1.64 {d2, d3}, [r1], r2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
175 vext.8 d3, d2, d3, #1
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
176 pld [r1]
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
177 pld [r1, r2]
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
178 subs r3, r3, #2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
179 vswp d1, d2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
180 \vhadd q0, q0, q1
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
181 vst1.64 {d0}, [r0,:64], r2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
182 vst1.64 {d1}, [r0,:64], r2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
183 bne 1b
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
184 bx lr
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
185 .endm
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
186
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
187 .macro pixels8_y2 vhadd=vrhadd.u8
9581
2b3b9358bee7 ARM: Use fewer register in NEON put_pixels _y2 and _xy2
conrad
parents: 9580
diff changeset
188 vld1.64 {d0}, [r1], r2
2b3b9358bee7 ARM: Use fewer register in NEON put_pixels _y2 and _xy2
conrad
parents: 9580
diff changeset
189 vld1.64 {d1}, [r1], r2
8334
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
190 1: subs r3, r3, #2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
191 \vhadd d4, d0, d1
9581
2b3b9358bee7 ARM: Use fewer register in NEON put_pixels _y2 and _xy2
conrad
parents: 9580
diff changeset
192 vld1.64 {d0}, [r1], r2
8334
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
193 \vhadd d5, d0, d1
9581
2b3b9358bee7 ARM: Use fewer register in NEON put_pixels _y2 and _xy2
conrad
parents: 9580
diff changeset
194 vld1.64 {d1}, [r1], r2
8334
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
195 pld [r1]
9581
2b3b9358bee7 ARM: Use fewer register in NEON put_pixels _y2 and _xy2
conrad
parents: 9580
diff changeset
196 pld [r1, r2]
8334
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
197 vst1.64 {d4}, [r0,:64], r2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
198 vst1.64 {d5}, [r0,:64], r2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
199 bne 1b
9581
2b3b9358bee7 ARM: Use fewer register in NEON put_pixels _y2 and _xy2
conrad
parents: 9580
diff changeset
200 bx lr
8334
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
201 .endm
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
202
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
203 .macro pixels8_xy2 vshrn=vrshrn.u16 no_rnd=0
9581
2b3b9358bee7 ARM: Use fewer register in NEON put_pixels _y2 and _xy2
conrad
parents: 9580
diff changeset
204 vld1.64 {d0, d1}, [r1], r2
2b3b9358bee7 ARM: Use fewer register in NEON put_pixels _y2 and _xy2
conrad
parents: 9580
diff changeset
205 vld1.64 {d2, d3}, [r1], r2
8334
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
206 .if \no_rnd
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
207 vmov.i16 q11, #1
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
208 .endif
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
209 pld [r1]
9581
2b3b9358bee7 ARM: Use fewer register in NEON put_pixels _y2 and _xy2
conrad
parents: 9580
diff changeset
210 pld [r1, r2]
8334
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
211 vext.8 d4, d0, d1, #1
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
212 vext.8 d6, d2, d3, #1
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
213 vaddl.u8 q8, d0, d4
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
214 vaddl.u8 q9, d2, d6
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
215 1: subs r3, r3, #2
9581
2b3b9358bee7 ARM: Use fewer register in NEON put_pixels _y2 and _xy2
conrad
parents: 9580
diff changeset
216 vld1.64 {d0, d1}, [r1], r2
8334
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
217 pld [r1]
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
218 vadd.u16 q10, q8, q9
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
219 vext.8 d4, d0, d1, #1
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
220 .if \no_rnd
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
221 vadd.u16 q10, q10, q11
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
222 .endif
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
223 vaddl.u8 q8, d0, d4
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
224 \vshrn d5, q10, #2
9581
2b3b9358bee7 ARM: Use fewer register in NEON put_pixels _y2 and _xy2
conrad
parents: 9580
diff changeset
225 vld1.64 {d2, d3}, [r1], r2
8334
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
226 vadd.u16 q10, q8, q9
9581
2b3b9358bee7 ARM: Use fewer register in NEON put_pixels _y2 and _xy2
conrad
parents: 9580
diff changeset
227 pld [r1, r2]
8334
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
228 .if \no_rnd
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
229 vadd.u16 q10, q10, q11
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
230 .endif
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
231 vst1.64 {d5}, [r0,:64], r2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
232 \vshrn d7, q10, #2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
233 vext.8 d6, d2, d3, #1
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
234 vaddl.u8 q9, d2, d6
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
235 vst1.64 {d7}, [r0,:64], r2
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
236 bgt 1b
9581
2b3b9358bee7 ARM: Use fewer register in NEON put_pixels _y2 and _xy2
conrad
parents: 9580
diff changeset
237 bx lr
8334
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
238 .endm
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
239
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
240 .macro pixfunc pfx name suf rnd_op args:vararg
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
241 function ff_\pfx\name\suf\()_neon, export=1
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
242 \name \rnd_op \args
11443
361a5fcb4393 ARM: set size of asm functions in object files
mru
parents: 10376
diff changeset
243 endfunc
8334
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
244 .endm
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
245
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
246 .macro pixfunc2 pfx name args:vararg
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
247 pixfunc \pfx \name
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
248 pixfunc \pfx \name \args
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
249 .endm
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
250
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
251 function ff_put_h264_qpel16_mc00_neon, export=1
10376
5c5b864d66e1 ARM: whitespace cosmetics
mru
parents: 10375
diff changeset
252 mov r3, #16
11443
361a5fcb4393 ARM: set size of asm functions in object files
mru
parents: 10376
diff changeset
253 endfunc
8334
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
254
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
255 pixfunc put_ pixels16
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
256 pixfunc2 put_ pixels16_x2, _no_rnd, vhadd.u8
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
257 pixfunc2 put_ pixels16_y2, _no_rnd, vhadd.u8
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
258 pixfunc2 put_ pixels16_xy2, _no_rnd, vshrn.u16, 1
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
259
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
260 function ff_avg_h264_qpel16_mc00_neon, export=1
10376
5c5b864d66e1 ARM: whitespace cosmetics
mru
parents: 10375
diff changeset
261 mov r3, #16
11443
361a5fcb4393 ARM: set size of asm functions in object files
mru
parents: 10376
diff changeset
262 endfunc
8334
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
263
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
264 pixfunc avg_ pixels16,, 1
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
265
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
266 function ff_put_h264_qpel8_mc00_neon, export=1
10376
5c5b864d66e1 ARM: whitespace cosmetics
mru
parents: 10375
diff changeset
267 mov r3, #8
11443
361a5fcb4393 ARM: set size of asm functions in object files
mru
parents: 10376
diff changeset
268 endfunc
8334
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
269
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
270 pixfunc put_ pixels8
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
271 pixfunc2 put_ pixels8_x2, _no_rnd, vhadd.u8
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
272 pixfunc2 put_ pixels8_y2, _no_rnd, vhadd.u8
6bdd6dfc3574 ARM: NEON optimised put_pixels functions
mru
parents:
diff changeset
273 pixfunc2 put_ pixels8_xy2, _no_rnd, vshrn.u16, 1
8492
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
274
10375
199949177888 ARM: NEON avg_pixels8 and avg_h264_qpel8_mc00
mru
parents: 10360
diff changeset
275 function ff_avg_h264_qpel8_mc00_neon, export=1
199949177888 ARM: NEON avg_pixels8 and avg_h264_qpel8_mc00
mru
parents: 10360
diff changeset
276 mov r3, #8
11443
361a5fcb4393 ARM: set size of asm functions in object files
mru
parents: 10376
diff changeset
277 endfunc
10375
199949177888 ARM: NEON avg_pixels8 and avg_h264_qpel8_mc00
mru
parents: 10360
diff changeset
278
199949177888 ARM: NEON avg_pixels8 and avg_h264_qpel8_mc00
mru
parents: 10360
diff changeset
279 pixfunc avg_ pixels8,, 1
199949177888 ARM: NEON avg_pixels8 and avg_h264_qpel8_mc00
mru
parents: 10360
diff changeset
280
9580
51e8f5ab8f1e ARM: NEON put_pixels_clamped
conrad
parents: 9451
diff changeset
281 function ff_put_pixels_clamped_neon, export=1
51e8f5ab8f1e ARM: NEON put_pixels_clamped
conrad
parents: 9451
diff changeset
282 vld1.64 {d16-d19}, [r0,:128]!
51e8f5ab8f1e ARM: NEON put_pixels_clamped
conrad
parents: 9451
diff changeset
283 vqmovun.s16 d0, q8
51e8f5ab8f1e ARM: NEON put_pixels_clamped
conrad
parents: 9451
diff changeset
284 vld1.64 {d20-d23}, [r0,:128]!
51e8f5ab8f1e ARM: NEON put_pixels_clamped
conrad
parents: 9451
diff changeset
285 vqmovun.s16 d1, q9
51e8f5ab8f1e ARM: NEON put_pixels_clamped
conrad
parents: 9451
diff changeset
286 vld1.64 {d24-d27}, [r0,:128]!
51e8f5ab8f1e ARM: NEON put_pixels_clamped
conrad
parents: 9451
diff changeset
287 vqmovun.s16 d2, q10
51e8f5ab8f1e ARM: NEON put_pixels_clamped
conrad
parents: 9451
diff changeset
288 vld1.64 {d28-d31}, [r0,:128]!
51e8f5ab8f1e ARM: NEON put_pixels_clamped
conrad
parents: 9451
diff changeset
289 vqmovun.s16 d3, q11
51e8f5ab8f1e ARM: NEON put_pixels_clamped
conrad
parents: 9451
diff changeset
290 vst1.64 {d0}, [r1,:64], r2
51e8f5ab8f1e ARM: NEON put_pixels_clamped
conrad
parents: 9451
diff changeset
291 vqmovun.s16 d4, q12
51e8f5ab8f1e ARM: NEON put_pixels_clamped
conrad
parents: 9451
diff changeset
292 vst1.64 {d1}, [r1,:64], r2
51e8f5ab8f1e ARM: NEON put_pixels_clamped
conrad
parents: 9451
diff changeset
293 vqmovun.s16 d5, q13
51e8f5ab8f1e ARM: NEON put_pixels_clamped
conrad
parents: 9451
diff changeset
294 vst1.64 {d2}, [r1,:64], r2
51e8f5ab8f1e ARM: NEON put_pixels_clamped
conrad
parents: 9451
diff changeset
295 vqmovun.s16 d6, q14
51e8f5ab8f1e ARM: NEON put_pixels_clamped
conrad
parents: 9451
diff changeset
296 vst1.64 {d3}, [r1,:64], r2
51e8f5ab8f1e ARM: NEON put_pixels_clamped
conrad
parents: 9451
diff changeset
297 vqmovun.s16 d7, q15
51e8f5ab8f1e ARM: NEON put_pixels_clamped
conrad
parents: 9451
diff changeset
298 vst1.64 {d4}, [r1,:64], r2
51e8f5ab8f1e ARM: NEON put_pixels_clamped
conrad
parents: 9451
diff changeset
299 vst1.64 {d5}, [r1,:64], r2
51e8f5ab8f1e ARM: NEON put_pixels_clamped
conrad
parents: 9451
diff changeset
300 vst1.64 {d6}, [r1,:64], r2
51e8f5ab8f1e ARM: NEON put_pixels_clamped
conrad
parents: 9451
diff changeset
301 vst1.64 {d7}, [r1,:64], r2
51e8f5ab8f1e ARM: NEON put_pixels_clamped
conrad
parents: 9451
diff changeset
302 bx lr
11443
361a5fcb4393 ARM: set size of asm functions in object files
mru
parents: 10376
diff changeset
303 endfunc
9580
51e8f5ab8f1e ARM: NEON put_pixels_clamped
conrad
parents: 9451
diff changeset
304
9345
e0a7a6338526 ARM: NEON optimized put_signed_pixels_clamped
conrad
parents: 9344
diff changeset
305 function ff_put_signed_pixels_clamped_neon, export=1
e0a7a6338526 ARM: NEON optimized put_signed_pixels_clamped
conrad
parents: 9344
diff changeset
306 vmov.u8 d31, #128
e0a7a6338526 ARM: NEON optimized put_signed_pixels_clamped
conrad
parents: 9344
diff changeset
307 vld1.64 {d16-d17}, [r0,:128]!
e0a7a6338526 ARM: NEON optimized put_signed_pixels_clamped
conrad
parents: 9344
diff changeset
308 vqmovn.s16 d0, q8
e0a7a6338526 ARM: NEON optimized put_signed_pixels_clamped
conrad
parents: 9344
diff changeset
309 vld1.64 {d18-d19}, [r0,:128]!
e0a7a6338526 ARM: NEON optimized put_signed_pixels_clamped
conrad
parents: 9344
diff changeset
310 vqmovn.s16 d1, q9
e0a7a6338526 ARM: NEON optimized put_signed_pixels_clamped
conrad
parents: 9344
diff changeset
311 vld1.64 {d16-d17}, [r0,:128]!
e0a7a6338526 ARM: NEON optimized put_signed_pixels_clamped
conrad
parents: 9344
diff changeset
312 vqmovn.s16 d2, q8
e0a7a6338526 ARM: NEON optimized put_signed_pixels_clamped
conrad
parents: 9344
diff changeset
313 vld1.64 {d18-d19}, [r0,:128]!
e0a7a6338526 ARM: NEON optimized put_signed_pixels_clamped
conrad
parents: 9344
diff changeset
314 vadd.u8 d0, d0, d31
e0a7a6338526 ARM: NEON optimized put_signed_pixels_clamped
conrad
parents: 9344
diff changeset
315 vld1.64 {d20-d21}, [r0,:128]!
e0a7a6338526 ARM: NEON optimized put_signed_pixels_clamped
conrad
parents: 9344
diff changeset
316 vadd.u8 d1, d1, d31
e0a7a6338526 ARM: NEON optimized put_signed_pixels_clamped
conrad
parents: 9344
diff changeset
317 vld1.64 {d22-d23}, [r0,:128]!
e0a7a6338526 ARM: NEON optimized put_signed_pixels_clamped
conrad
parents: 9344
diff changeset
318 vadd.u8 d2, d2, d31
e0a7a6338526 ARM: NEON optimized put_signed_pixels_clamped
conrad
parents: 9344
diff changeset
319 vst1.64 {d0}, [r1,:64], r2
e0a7a6338526 ARM: NEON optimized put_signed_pixels_clamped
conrad
parents: 9344
diff changeset
320 vqmovn.s16 d3, q9
e0a7a6338526 ARM: NEON optimized put_signed_pixels_clamped
conrad
parents: 9344
diff changeset
321 vst1.64 {d1}, [r1,:64], r2
e0a7a6338526 ARM: NEON optimized put_signed_pixels_clamped
conrad
parents: 9344
diff changeset
322 vqmovn.s16 d4, q10
e0a7a6338526 ARM: NEON optimized put_signed_pixels_clamped
conrad
parents: 9344
diff changeset
323 vst1.64 {d2}, [r1,:64], r2
e0a7a6338526 ARM: NEON optimized put_signed_pixels_clamped
conrad
parents: 9344
diff changeset
324 vqmovn.s16 d5, q11
e0a7a6338526 ARM: NEON optimized put_signed_pixels_clamped
conrad
parents: 9344
diff changeset
325 vld1.64 {d24-d25}, [r0,:128]!
e0a7a6338526 ARM: NEON optimized put_signed_pixels_clamped
conrad
parents: 9344
diff changeset
326 vadd.u8 d3, d3, d31
e0a7a6338526 ARM: NEON optimized put_signed_pixels_clamped
conrad
parents: 9344
diff changeset
327 vld1.64 {d26-d27}, [r0,:128]!
e0a7a6338526 ARM: NEON optimized put_signed_pixels_clamped
conrad
parents: 9344
diff changeset
328 vadd.u8 d4, d4, d31
e0a7a6338526 ARM: NEON optimized put_signed_pixels_clamped
conrad
parents: 9344
diff changeset
329 vadd.u8 d5, d5, d31
e0a7a6338526 ARM: NEON optimized put_signed_pixels_clamped
conrad
parents: 9344
diff changeset
330 vst1.64 {d3}, [r1,:64], r2
e0a7a6338526 ARM: NEON optimized put_signed_pixels_clamped
conrad
parents: 9344
diff changeset
331 vqmovn.s16 d6, q12
e0a7a6338526 ARM: NEON optimized put_signed_pixels_clamped
conrad
parents: 9344
diff changeset
332 vst1.64 {d4}, [r1,:64], r2
e0a7a6338526 ARM: NEON optimized put_signed_pixels_clamped
conrad
parents: 9344
diff changeset
333 vqmovn.s16 d7, q13
e0a7a6338526 ARM: NEON optimized put_signed_pixels_clamped
conrad
parents: 9344
diff changeset
334 vst1.64 {d5}, [r1,:64], r2
e0a7a6338526 ARM: NEON optimized put_signed_pixels_clamped
conrad
parents: 9344
diff changeset
335 vadd.u8 d6, d6, d31
e0a7a6338526 ARM: NEON optimized put_signed_pixels_clamped
conrad
parents: 9344
diff changeset
336 vadd.u8 d7, d7, d31
e0a7a6338526 ARM: NEON optimized put_signed_pixels_clamped
conrad
parents: 9344
diff changeset
337 vst1.64 {d6}, [r1,:64], r2
e0a7a6338526 ARM: NEON optimized put_signed_pixels_clamped
conrad
parents: 9344
diff changeset
338 vst1.64 {d7}, [r1,:64], r2
e0a7a6338526 ARM: NEON optimized put_signed_pixels_clamped
conrad
parents: 9344
diff changeset
339 bx lr
11443
361a5fcb4393 ARM: set size of asm functions in object files
mru
parents: 10376
diff changeset
340 endfunc
9345
e0a7a6338526 ARM: NEON optimized put_signed_pixels_clamped
conrad
parents: 9344
diff changeset
341
9344
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
342 function ff_add_pixels_clamped_neon, export=1
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
343 mov r3, r1
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
344 vld1.64 {d16}, [r1,:64], r2
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
345 vld1.64 {d0-d1}, [r0,:128]!
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
346 vaddw.u8 q0, q0, d16
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
347 vld1.64 {d17}, [r1,:64], r2
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
348 vld1.64 {d2-d3}, [r0,:128]!
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
349 vqmovun.s16 d0, q0
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
350 vld1.64 {d18}, [r1,:64], r2
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
351 vaddw.u8 q1, q1, d17
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
352 vld1.64 {d4-d5}, [r0,:128]!
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
353 vaddw.u8 q2, q2, d18
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
354 vst1.64 {d0}, [r3,:64], r2
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
355 vqmovun.s16 d2, q1
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
356 vld1.64 {d19}, [r1,:64], r2
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
357 vld1.64 {d6-d7}, [r0,:128]!
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
358 vaddw.u8 q3, q3, d19
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
359 vqmovun.s16 d4, q2
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
360 vst1.64 {d2}, [r3,:64], r2
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
361 vld1.64 {d16}, [r1,:64], r2
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
362 vqmovun.s16 d6, q3
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
363 vld1.64 {d0-d1}, [r0,:128]!
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
364 vaddw.u8 q0, q0, d16
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
365 vst1.64 {d4}, [r3,:64], r2
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
366 vld1.64 {d17}, [r1,:64], r2
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
367 vld1.64 {d2-d3}, [r0,:128]!
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
368 vaddw.u8 q1, q1, d17
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
369 vst1.64 {d6}, [r3,:64], r2
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
370 vqmovun.s16 d0, q0
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
371 vld1.64 {d18}, [r1,:64], r2
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
372 vld1.64 {d4-d5}, [r0,:128]!
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
373 vaddw.u8 q2, q2, d18
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
374 vst1.64 {d0}, [r3,:64], r2
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
375 vqmovun.s16 d2, q1
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
376 vld1.64 {d19}, [r1,:64], r2
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
377 vqmovun.s16 d4, q2
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
378 vld1.64 {d6-d7}, [r0,:128]!
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
379 vaddw.u8 q3, q3, d19
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
380 vst1.64 {d2}, [r3,:64], r2
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
381 vqmovun.s16 d6, q3
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
382 vst1.64 {d4}, [r3,:64], r2
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
383 vst1.64 {d6}, [r3,:64], r2
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
384 bx lr
11443
361a5fcb4393 ARM: set size of asm functions in object files
mru
parents: 10376
diff changeset
385 endfunc
9344
9ea1ea6db616 ARM: NEON optimised add_pixels_clamped
mru
parents: 8698
diff changeset
386
8492
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
387 function ff_float_to_int16_neon, export=1
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
388 subs r2, r2, #8
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
389 vld1.64 {d0-d1}, [r1,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
390 vcvt.s32.f32 q8, q0, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
391 vld1.64 {d2-d3}, [r1,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
392 vcvt.s32.f32 q9, q1, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
393 beq 3f
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
394 bics ip, r2, #15
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
395 beq 2f
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
396 1: subs ip, ip, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
397 vshrn.s32 d4, q8, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
398 vld1.64 {d0-d1}, [r1,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
399 vcvt.s32.f32 q0, q0, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
400 vshrn.s32 d5, q9, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
401 vld1.64 {d2-d3}, [r1,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
402 vcvt.s32.f32 q1, q1, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
403 vshrn.s32 d6, q0, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
404 vst1.64 {d4-d5}, [r0,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
405 vshrn.s32 d7, q1, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
406 vld1.64 {d16-d17},[r1,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
407 vcvt.s32.f32 q8, q8, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
408 vld1.64 {d18-d19},[r1,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
409 vcvt.s32.f32 q9, q9, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
410 vst1.64 {d6-d7}, [r0,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
411 bne 1b
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
412 ands r2, r2, #15
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
413 beq 3f
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
414 2: vld1.64 {d0-d1}, [r1,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
415 vshrn.s32 d4, q8, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
416 vcvt.s32.f32 q0, q0, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
417 vld1.64 {d2-d3}, [r1,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
418 vshrn.s32 d5, q9, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
419 vcvt.s32.f32 q1, q1, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
420 vshrn.s32 d6, q0, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
421 vst1.64 {d4-d5}, [r0,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
422 vshrn.s32 d7, q1, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
423 vst1.64 {d6-d7}, [r0,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
424 bx lr
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
425 3: vshrn.s32 d4, q8, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
426 vshrn.s32 d5, q9, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
427 vst1.64 {d4-d5}, [r0,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
428 bx lr
11443
361a5fcb4393 ARM: set size of asm functions in object files
mru
parents: 10376
diff changeset
429 endfunc
8492
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
430
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
431 function ff_float_to_int16_interleave_neon, export=1
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
432 cmp r3, #2
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
433 ldrlt r1, [r1]
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
434 blt ff_float_to_int16_neon
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
435 bne 4f
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
436
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
437 ldr r3, [r1]
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
438 ldr r1, [r1, #4]
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
439
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
440 subs r2, r2, #8
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
441 vld1.64 {d0-d1}, [r3,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
442 vcvt.s32.f32 q8, q0, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
443 vld1.64 {d2-d3}, [r3,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
444 vcvt.s32.f32 q9, q1, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
445 vld1.64 {d20-d21},[r1,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
446 vcvt.s32.f32 q10, q10, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
447 vld1.64 {d22-d23},[r1,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
448 vcvt.s32.f32 q11, q11, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
449 beq 3f
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
450 bics ip, r2, #15
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
451 beq 2f
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
452 1: subs ip, ip, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
453 vld1.64 {d0-d1}, [r3,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
454 vcvt.s32.f32 q0, q0, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
455 vsri.32 q10, q8, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
456 vld1.64 {d2-d3}, [r3,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
457 vcvt.s32.f32 q1, q1, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
458 vld1.64 {d24-d25},[r1,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
459 vcvt.s32.f32 q12, q12, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
460 vld1.64 {d26-d27},[r1,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
461 vsri.32 q11, q9, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
462 vst1.64 {d20-d21},[r0,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
463 vcvt.s32.f32 q13, q13, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
464 vst1.64 {d22-d23},[r0,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
465 vsri.32 q12, q0, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
466 vld1.64 {d16-d17},[r3,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
467 vsri.32 q13, q1, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
468 vst1.64 {d24-d25},[r0,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
469 vcvt.s32.f32 q8, q8, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
470 vld1.64 {d18-d19},[r3,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
471 vcvt.s32.f32 q9, q9, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
472 vld1.64 {d20-d21},[r1,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
473 vcvt.s32.f32 q10, q10, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
474 vld1.64 {d22-d23},[r1,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
475 vcvt.s32.f32 q11, q11, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
476 vst1.64 {d26-d27},[r0,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
477 bne 1b
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
478 ands r2, r2, #15
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
479 beq 3f
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
480 2: vsri.32 q10, q8, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
481 vld1.64 {d0-d1}, [r3,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
482 vcvt.s32.f32 q0, q0, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
483 vld1.64 {d2-d3}, [r3,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
484 vcvt.s32.f32 q1, q1, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
485 vld1.64 {d24-d25},[r1,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
486 vcvt.s32.f32 q12, q12, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
487 vsri.32 q11, q9, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
488 vld1.64 {d26-d27},[r1,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
489 vcvt.s32.f32 q13, q13, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
490 vst1.64 {d20-d21},[r0,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
491 vsri.32 q12, q0, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
492 vst1.64 {d22-d23},[r0,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
493 vsri.32 q13, q1, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
494 vst1.64 {d24-d27},[r0,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
495 bx lr
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
496 3: vsri.32 q10, q8, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
497 vsri.32 q11, q9, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
498 vst1.64 {d20-d23},[r0,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
499 bx lr
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
500
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
501 4: push {r4-r8,lr}
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
502 cmp r3, #4
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
503 lsl ip, r3, #1
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
504 blt 4f
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
505
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
506 @ 4 channels
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
507 5: ldmia r1!, {r4-r7}
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
508 mov lr, r2
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
509 mov r8, r0
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
510 vld1.64 {d16-d17},[r4,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
511 vcvt.s32.f32 q8, q8, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
512 vld1.64 {d18-d19},[r5,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
513 vcvt.s32.f32 q9, q9, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
514 vld1.64 {d20-d21},[r6,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
515 vcvt.s32.f32 q10, q10, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
516 vld1.64 {d22-d23},[r7,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
517 vcvt.s32.f32 q11, q11, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
518 6: subs lr, lr, #8
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
519 vld1.64 {d0-d1}, [r4,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
520 vcvt.s32.f32 q0, q0, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
521 vsri.32 q9, q8, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
522 vld1.64 {d2-d3}, [r5,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
523 vcvt.s32.f32 q1, q1, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
524 vsri.32 q11, q10, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
525 vld1.64 {d4-d5}, [r6,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
526 vcvt.s32.f32 q2, q2, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
527 vzip.32 d18, d22
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
528 vld1.64 {d6-d7}, [r7,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
529 vcvt.s32.f32 q3, q3, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
530 vzip.32 d19, d23
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
531 vst1.64 {d18}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
532 vsri.32 q1, q0, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
533 vst1.64 {d22}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
534 vsri.32 q3, q2, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
535 vst1.64 {d19}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
536 vzip.32 d2, d6
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
537 vst1.64 {d23}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
538 vzip.32 d3, d7
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
539 beq 7f
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
540 vld1.64 {d16-d17},[r4,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
541 vcvt.s32.f32 q8, q8, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
542 vst1.64 {d2}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
543 vld1.64 {d18-d19},[r5,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
544 vcvt.s32.f32 q9, q9, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
545 vst1.64 {d6}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
546 vld1.64 {d20-d21},[r6,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
547 vcvt.s32.f32 q10, q10, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
548 vst1.64 {d3}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
549 vld1.64 {d22-d23},[r7,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
550 vcvt.s32.f32 q11, q11, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
551 vst1.64 {d7}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
552 b 6b
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
553 7: vst1.64 {d2}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
554 vst1.64 {d6}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
555 vst1.64 {d3}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
556 vst1.64 {d7}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
557 subs r3, r3, #4
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
558 popeq {r4-r8,pc}
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
559 cmp r3, #4
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
560 add r0, r0, #8
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
561 bge 5b
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
562
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
563 @ 2 channels
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
564 4: cmp r3, #2
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
565 blt 4f
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
566 ldmia r1!, {r4-r5}
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
567 mov lr, r2
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
568 mov r8, r0
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
569 tst lr, #8
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
570 vld1.64 {d16-d17},[r4,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
571 vcvt.s32.f32 q8, q8, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
572 vld1.64 {d18-d19},[r5,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
573 vcvt.s32.f32 q9, q9, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
574 vld1.64 {d20-d21},[r4,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
575 vcvt.s32.f32 q10, q10, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
576 vld1.64 {d22-d23},[r5,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
577 vcvt.s32.f32 q11, q11, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
578 beq 6f
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
579 subs lr, lr, #8
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
580 beq 7f
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
581 vsri.32 d18, d16, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
582 vsri.32 d19, d17, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
583 vld1.64 {d16-d17},[r4,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
584 vcvt.s32.f32 q8, q8, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
585 vst1.32 {d18[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
586 vsri.32 d22, d20, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
587 vst1.32 {d18[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
588 vsri.32 d23, d21, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
589 vst1.32 {d19[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
590 vst1.32 {d19[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
591 vld1.64 {d18-d19},[r5,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
592 vcvt.s32.f32 q9, q9, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
593 vst1.32 {d22[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
594 vst1.32 {d22[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
595 vld1.64 {d20-d21},[r4,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
596 vcvt.s32.f32 q10, q10, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
597 vst1.32 {d23[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
598 vst1.32 {d23[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
599 vld1.64 {d22-d23},[r5,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
600 vcvt.s32.f32 q11, q11, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
601 6: subs lr, lr, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
602 vld1.64 {d0-d1}, [r4,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
603 vcvt.s32.f32 q0, q0, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
604 vsri.32 d18, d16, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
605 vld1.64 {d2-d3}, [r5,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
606 vcvt.s32.f32 q1, q1, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
607 vsri.32 d19, d17, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
608 vld1.64 {d4-d5}, [r4,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
609 vcvt.s32.f32 q2, q2, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
610 vld1.64 {d6-d7}, [r5,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
611 vcvt.s32.f32 q3, q3, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
612 vst1.32 {d18[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
613 vsri.32 d22, d20, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
614 vst1.32 {d18[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
615 vsri.32 d23, d21, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
616 vst1.32 {d19[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
617 vsri.32 d2, d0, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
618 vst1.32 {d19[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
619 vsri.32 d3, d1, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
620 vst1.32 {d22[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
621 vsri.32 d6, d4, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
622 vst1.32 {d22[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
623 vsri.32 d7, d5, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
624 vst1.32 {d23[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
625 vst1.32 {d23[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
626 beq 6f
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
627 vld1.64 {d16-d17},[r4,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
628 vcvt.s32.f32 q8, q8, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
629 vst1.32 {d2[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
630 vst1.32 {d2[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
631 vld1.64 {d18-d19},[r5,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
632 vcvt.s32.f32 q9, q9, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
633 vst1.32 {d3[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
634 vst1.32 {d3[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
635 vld1.64 {d20-d21},[r4,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
636 vcvt.s32.f32 q10, q10, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
637 vst1.32 {d6[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
638 vst1.32 {d6[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
639 vld1.64 {d22-d23},[r5,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
640 vcvt.s32.f32 q11, q11, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
641 vst1.32 {d7[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
642 vst1.32 {d7[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
643 bgt 6b
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
644 6: vst1.32 {d2[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
645 vst1.32 {d2[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
646 vst1.32 {d3[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
647 vst1.32 {d3[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
648 vst1.32 {d6[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
649 vst1.32 {d6[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
650 vst1.32 {d7[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
651 vst1.32 {d7[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
652 b 8f
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
653 7: vsri.32 d18, d16, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
654 vsri.32 d19, d17, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
655 vst1.32 {d18[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
656 vsri.32 d22, d20, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
657 vst1.32 {d18[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
658 vsri.32 d23, d21, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
659 vst1.32 {d19[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
660 vst1.32 {d19[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
661 vst1.32 {d22[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
662 vst1.32 {d22[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
663 vst1.32 {d23[0]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
664 vst1.32 {d23[1]}, [r8], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
665 8: subs r3, r3, #2
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
666 add r0, r0, #4
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
667 popeq {r4-r8,pc}
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
668
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
669 @ 1 channel
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
670 4: ldr r4, [r1],#4
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
671 tst r2, #8
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
672 mov lr, r2
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
673 mov r5, r0
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
674 vld1.64 {d0-d1}, [r4,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
675 vcvt.s32.f32 q0, q0, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
676 vld1.64 {d2-d3}, [r4,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
677 vcvt.s32.f32 q1, q1, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
678 bne 8f
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
679 6: subs lr, lr, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
680 vld1.64 {d4-d5}, [r4,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
681 vcvt.s32.f32 q2, q2, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
682 vld1.64 {d6-d7}, [r4,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
683 vcvt.s32.f32 q3, q3, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
684 vst1.16 {d0[1]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
685 vst1.16 {d0[3]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
686 vst1.16 {d1[1]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
687 vst1.16 {d1[3]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
688 vst1.16 {d2[1]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
689 vst1.16 {d2[3]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
690 vst1.16 {d3[1]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
691 vst1.16 {d3[3]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
692 beq 7f
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
693 vld1.64 {d0-d1}, [r4,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
694 vcvt.s32.f32 q0, q0, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
695 vld1.64 {d2-d3}, [r4,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
696 vcvt.s32.f32 q1, q1, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
697 7: vst1.16 {d4[1]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
698 vst1.16 {d4[3]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
699 vst1.16 {d5[1]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
700 vst1.16 {d5[3]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
701 vst1.16 {d6[1]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
702 vst1.16 {d6[3]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
703 vst1.16 {d7[1]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
704 vst1.16 {d7[3]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
705 bgt 6b
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
706 pop {r4-r8,pc}
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
707 8: subs lr, lr, #8
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
708 vst1.16 {d0[1]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
709 vst1.16 {d0[3]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
710 vst1.16 {d1[1]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
711 vst1.16 {d1[3]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
712 vst1.16 {d2[1]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
713 vst1.16 {d2[3]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
714 vst1.16 {d3[1]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
715 vst1.16 {d3[3]}, [r5,:16], ip
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
716 popeq {r4-r8,pc}
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
717 vld1.64 {d0-d1}, [r4,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
718 vcvt.s32.f32 q0, q0, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
719 vld1.64 {d2-d3}, [r4,:128]!
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
720 vcvt.s32.f32 q1, q1, #16
639169d7fad5 ARM: NEON optimised float_to_int16
mru
parents: 8359
diff changeset
721 b 6b
11443
361a5fcb4393 ARM: set size of asm functions in object files
mru
parents: 10376
diff changeset
722 endfunc
8697
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
723
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
724 function ff_vector_fmul_neon, export=1
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
725 mov r3, r0
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
726 subs r2, r2, #8
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
727 vld1.64 {d0-d3}, [r0,:128]!
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
728 vld1.64 {d4-d7}, [r1,:128]!
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
729 vmul.f32 q8, q0, q2
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
730 vmul.f32 q9, q1, q3
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
731 beq 3f
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
732 bics ip, r2, #15
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
733 beq 2f
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
734 1: subs ip, ip, #16
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
735 vld1.64 {d0-d1}, [r0,:128]!
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
736 vld1.64 {d4-d5}, [r1,:128]!
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
737 vmul.f32 q10, q0, q2
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
738 vld1.64 {d2-d3}, [r0,:128]!
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
739 vld1.64 {d6-d7}, [r1,:128]!
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
740 vmul.f32 q11, q1, q3
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
741 vst1.64 {d16-d19},[r3,:128]!
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
742 vld1.64 {d0-d1}, [r0,:128]!
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
743 vld1.64 {d4-d5}, [r1,:128]!
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
744 vmul.f32 q8, q0, q2
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
745 vld1.64 {d2-d3}, [r0,:128]!
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
746 vld1.64 {d6-d7}, [r1,:128]!
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
747 vmul.f32 q9, q1, q3
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
748 vst1.64 {d20-d23},[r3,:128]!
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
749 bne 1b
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
750 ands r2, r2, #15
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
751 beq 3f
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
752 2: vld1.64 {d0-d1}, [r0,:128]!
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
753 vld1.64 {d4-d5}, [r1,:128]!
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
754 vst1.64 {d16-d17},[r3,:128]!
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
755 vmul.f32 q8, q0, q2
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
756 vld1.64 {d2-d3}, [r0,:128]!
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
757 vld1.64 {d6-d7}, [r1,:128]!
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
758 vst1.64 {d18-d19},[r3,:128]!
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
759 vmul.f32 q9, q1, q3
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
760 3: vst1.64 {d16-d19},[r3,:128]!
307b176f91e7 ARM: NEON optimised vector_fmul
mru
parents: 8492
diff changeset
761 bx lr
11443
361a5fcb4393 ARM: set size of asm functions in object files
mru
parents: 10376
diff changeset
762 endfunc
8698
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
763
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
764 function ff_vector_fmul_window_neon, export=1
9969
5cca2790d582 ARM: handle VFP register arguments in ff_vector_fmul_window_neon()
mru
parents: 9581
diff changeset
765 VFP vdup.32 q8, d0[0]
5cca2790d582 ARM: handle VFP register arguments in ff_vector_fmul_window_neon()
mru
parents: 9581
diff changeset
766 NOVFP vld1.32 {d16[],d17[]}, [sp,:32]
8698
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
767 push {r4,r5,lr}
9969
5cca2790d582 ARM: handle VFP register arguments in ff_vector_fmul_window_neon()
mru
parents: 9581
diff changeset
768 VFP ldr lr, [sp, #12]
5cca2790d582 ARM: handle VFP register arguments in ff_vector_fmul_window_neon()
mru
parents: 9581
diff changeset
769 NOVFP ldr lr, [sp, #16]
8698
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
770 sub r2, r2, #8
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
771 sub r5, lr, #2
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
772 add r2, r2, r5, lsl #2
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
773 add r4, r3, r5, lsl #3
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
774 add ip, r0, r5, lsl #3
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
775 mov r5, #-16
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
776 vld1.64 {d0,d1}, [r1,:128]!
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
777 vld1.64 {d2,d3}, [r2,:128], r5
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
778 vld1.64 {d4,d5}, [r3,:128]!
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
779 vld1.64 {d6,d7}, [r4,:128], r5
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
780 1: subs lr, lr, #4
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
781 vmov q11, q8
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
782 vmla.f32 d22, d0, d4
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
783 vmov q10, q8
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
784 vmla.f32 d23, d1, d5
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
785 vrev64.32 q3, q3
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
786 vmla.f32 d20, d0, d7
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
787 vrev64.32 q1, q1
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
788 vmla.f32 d21, d1, d6
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
789 beq 2f
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
790 vmla.f32 d22, d3, d7
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
791 vld1.64 {d0,d1}, [r1,:128]!
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
792 vmla.f32 d23, d2, d6
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
793 vld1.64 {d18,d19},[r2,:128], r5
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
794 vmls.f32 d20, d3, d4
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
795 vld1.64 {d24,d25},[r3,:128]!
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
796 vmls.f32 d21, d2, d5
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
797 vld1.64 {d6,d7}, [r4,:128], r5
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
798 vmov q1, q9
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
799 vrev64.32 q11, q11
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
800 vmov q2, q12
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
801 vswp d22, d23
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
802 vst1.64 {d20,d21},[r0,:128]!
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
803 vst1.64 {d22,d23},[ip,:128], r5
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
804 b 1b
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
805 2: vmla.f32 d22, d3, d7
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
806 vmla.f32 d23, d2, d6
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
807 vmls.f32 d20, d3, d4
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
808 vmls.f32 d21, d2, d5
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
809 vrev64.32 q11, q11
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
810 vswp d22, d23
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
811 vst1.64 {d20,d21},[r0,:128]!
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
812 vst1.64 {d22,d23},[ip,:128], r5
24a7b5d0eb27 ARM: NEON optimised vector_fmul_window
mru
parents: 8697
diff changeset
813 pop {r4,r5,pc}
11443
361a5fcb4393 ARM: set size of asm functions in object files
mru
parents: 10376
diff changeset
814 endfunc
10046
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
815
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
816 #if CONFIG_VORBIS_DECODER
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
817 function ff_vorbis_inverse_coupling_neon, export=1
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
818 vmov.i32 q10, #1<<31
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
819 subs r2, r2, #4
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
820 mov r3, r0
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
821 mov r12, r1
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
822 beq 3f
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
823
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
824 vld1.32 {d24-d25},[r1,:128]!
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
825 vld1.32 {d22-d23},[r0,:128]!
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
826 vcle.s32 q8, q12, #0
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
827 vand q9, q11, q10
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
828 veor q12, q12, q9
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
829 vand q2, q12, q8
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
830 vbic q3, q12, q8
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
831 vadd.f32 q12, q11, q2
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
832 vsub.f32 q11, q11, q3
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
833 1: vld1.32 {d2-d3}, [r1,:128]!
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
834 vld1.32 {d0-d1}, [r0,:128]!
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
835 vcle.s32 q8, q1, #0
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
836 vand q9, q0, q10
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
837 veor q1, q1, q9
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
838 vst1.32 {d24-d25},[r3, :128]!
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
839 vst1.32 {d22-d23},[r12,:128]!
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
840 vand q2, q1, q8
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
841 vbic q3, q1, q8
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
842 vadd.f32 q1, q0, q2
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
843 vsub.f32 q0, q0, q3
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
844 subs r2, r2, #8
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
845 ble 2f
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
846 vld1.32 {d24-d25},[r1,:128]!
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
847 vld1.32 {d22-d23},[r0,:128]!
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
848 vcle.s32 q8, q12, #0
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
849 vand q9, q11, q10
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
850 veor q12, q12, q9
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
851 vst1.32 {d2-d3}, [r3, :128]!
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
852 vst1.32 {d0-d1}, [r12,:128]!
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
853 vand q2, q12, q8
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
854 vbic q3, q12, q8
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
855 vadd.f32 q12, q11, q2
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
856 vsub.f32 q11, q11, q3
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
857 b 1b
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
858
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
859 2: vst1.32 {d2-d3}, [r3, :128]!
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
860 vst1.32 {d0-d1}, [r12,:128]!
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
861 bxlt lr
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
862
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
863 3: vld1.32 {d2-d3}, [r1,:128]
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
864 vld1.32 {d0-d1}, [r0,:128]
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
865 vcle.s32 q8, q1, #0
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
866 vand q9, q0, q10
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
867 veor q1, q1, q9
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
868 vand q2, q1, q8
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
869 vbic q3, q1, q8
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
870 vadd.f32 q1, q0, q2
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
871 vsub.f32 q0, q0, q3
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
872 vst1.32 {d2-d3}, [r0,:128]!
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
873 vst1.32 {d0-d1}, [r1,:128]!
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
874 bx lr
11443
361a5fcb4393 ARM: set size of asm functions in object files
mru
parents: 10376
diff changeset
875 endfunc
10046
1e651d94b35f ARM: NEON optimised vorbis_inverse_coupling
mru
parents: 9969
diff changeset
876 #endif
10221
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
877
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
878 function ff_vector_fmul_scalar_neon, export=1
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
879 VFP len .req r2
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
880 NOVFP len .req r3
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
881 VFP vdup.32 q8, d0[0]
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
882 NOVFP vdup.32 q8, r2
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
883 bics r12, len, #15
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
884 beq 3f
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
885 vld1.32 {q0},[r1,:128]!
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
886 vld1.32 {q1},[r1,:128]!
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
887 1: vmul.f32 q0, q0, q8
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
888 vld1.32 {q2},[r1,:128]!
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
889 vmul.f32 q1, q1, q8
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
890 vld1.32 {q3},[r1,:128]!
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
891 vmul.f32 q2, q2, q8
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
892 vst1.32 {q0},[r0,:128]!
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
893 vmul.f32 q3, q3, q8
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
894 vst1.32 {q1},[r0,:128]!
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
895 subs r12, r12, #16
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
896 beq 2f
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
897 vld1.32 {q0},[r1,:128]!
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
898 vst1.32 {q2},[r0,:128]!
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
899 vld1.32 {q1},[r1,:128]!
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
900 vst1.32 {q3},[r0,:128]!
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
901 b 1b
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
902 2: vst1.32 {q2},[r0,:128]!
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
903 vst1.32 {q3},[r0,:128]!
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
904 ands len, len, #15
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
905 bxeq lr
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
906 3: vld1.32 {q0},[r1,:128]!
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
907 vmul.f32 q0, q0, q8
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
908 vst1.32 {q0},[r0,:128]!
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
909 subs len, len, #4
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
910 bgt 3b
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
911 bx lr
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
912 .unreq len
11443
361a5fcb4393 ARM: set size of asm functions in object files
mru
parents: 10376
diff changeset
913 endfunc
10221
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
914
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
915 function ff_vector_fmul_sv_scalar_2_neon, export=1
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
916 VFP vdup.32 d16, d0[0]
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
917 NOVFP vdup.32 d16, r3
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
918 NOVFP ldr r3, [sp]
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
919 vld1.32 {d0},[r1,:64]!
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
920 vld1.32 {d1},[r1,:64]!
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
921 1: subs r3, r3, #4
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
922 vmul.f32 d4, d0, d16
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
923 vmul.f32 d5, d1, d16
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
924 ldr r12, [r2], #4
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
925 vld1.32 {d2},[r12,:64]
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
926 ldr r12, [r2], #4
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
927 vld1.32 {d3},[r12,:64]
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
928 vmul.f32 d4, d4, d2
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
929 vmul.f32 d5, d5, d3
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
930 beq 2f
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
931 vld1.32 {d0},[r1,:64]!
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
932 vld1.32 {d1},[r1,:64]!
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
933 vst1.32 {d4},[r0,:64]!
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
934 vst1.32 {d5},[r0,:64]!
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
935 b 1b
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
936 2: vst1.32 {d4},[r0,:64]!
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
937 vst1.32 {d5},[r0,:64]!
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
938 bx lr
11443
361a5fcb4393 ARM: set size of asm functions in object files
mru
parents: 10376
diff changeset
939 endfunc
10221
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
940
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
941 function ff_vector_fmul_sv_scalar_4_neon, export=1
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
942 VFP vdup.32 q10, d0[0]
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
943 NOVFP vdup.32 q10, r3
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
944 NOVFP ldr r3, [sp]
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
945 push {lr}
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
946 bics lr, r3, #7
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
947 beq 3f
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
948 vld1.32 {q0},[r1,:128]!
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
949 vld1.32 {q2},[r1,:128]!
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
950 1: ldr r12, [r2], #4
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
951 vld1.32 {q1},[r12,:128]
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
952 ldr r12, [r2], #4
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
953 vld1.32 {q3},[r12,:128]
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
954 vmul.f32 q8, q0, q10
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
955 vmul.f32 q8, q8, q1
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
956 vmul.f32 q9, q2, q10
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
957 vmul.f32 q9, q9, q3
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
958 subs lr, lr, #8
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
959 beq 2f
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
960 vld1.32 {q0},[r1,:128]!
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
961 vld1.32 {q2},[r1,:128]!
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
962 vst1.32 {q8},[r0,:128]!
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
963 vst1.32 {q9},[r0,:128]!
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
964 b 1b
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
965 2: vst1.32 {q8},[r0,:128]!
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
966 vst1.32 {q9},[r0,:128]!
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
967 ands r3, r3, #7
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
968 popeq {pc}
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
969 3: vld1.32 {q0},[r1,:128]!
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
970 ldr r12, [r2], #4
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
971 vld1.32 {q1},[r12,:128]
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
972 vmul.f32 q0, q0, q10
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
973 vmul.f32 q0, q0, q1
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
974 vst1.32 {q0},[r0,:128]!
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
975 subs r3, r3, #4
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
976 bgt 3b
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
977 pop {pc}
11443
361a5fcb4393 ARM: set size of asm functions in object files
mru
parents: 10376
diff changeset
978 endfunc
10221
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
979
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
980 function ff_sv_fmul_scalar_2_neon, export=1
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
981 VFP len .req r2
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
982 NOVFP len .req r3
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
983 VFP vdup.32 q8, d0[0]
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
984 NOVFP vdup.32 q8, r2
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
985 ldr r12, [r1], #4
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
986 vld1.32 {d0},[r12,:64]
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
987 ldr r12, [r1], #4
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
988 vld1.32 {d1},[r12,:64]
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
989 1: vmul.f32 q1, q0, q8
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
990 subs len, len, #4
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
991 beq 2f
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
992 ldr r12, [r1], #4
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
993 vld1.32 {d0},[r12,:64]
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
994 ldr r12, [r1], #4
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
995 vld1.32 {d1},[r12,:64]
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
996 vst1.32 {q1},[r0,:128]!
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
997 b 1b
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
998 2: vst1.32 {q1},[r0,:128]!
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
999 bx lr
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
1000 .unreq len
11443
361a5fcb4393 ARM: set size of asm functions in object files
mru
parents: 10376
diff changeset
1001 endfunc
10221
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
1002
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
1003 function ff_sv_fmul_scalar_4_neon, export=1
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
1004 VFP len .req r2
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
1005 NOVFP len .req r3
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
1006 VFP vdup.32 q8, d0[0]
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
1007 NOVFP vdup.32 q8, r2
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
1008 1: ldr r12, [r1], #4
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
1009 vld1.32 {q0},[r12,:128]
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
1010 vmul.f32 q0, q0, q8
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
1011 vst1.32 {q0},[r0,:128]!
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
1012 subs len, len, #4
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
1013 bgt 1b
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
1014 bx lr
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
1015 .unreq len
11443
361a5fcb4393 ARM: set size of asm functions in object files
mru
parents: 10376
diff changeset
1016 endfunc
10221
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
1017
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
1018 function ff_butterflies_float_neon, export=1
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
1019 1: vld1.32 {q0},[r0,:128]
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
1020 vld1.32 {q1},[r1,:128]
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
1021 vsub.f32 q2, q0, q1
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
1022 vadd.f32 q1, q0, q1
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
1023 vst1.32 {q2},[r1,:128]!
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
1024 vst1.32 {q1},[r0,:128]!
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
1025 subs r2, r2, #4
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
1026 bgt 1b
2791393081ff ARM: NEON optimisations for some dsputil functions
mru
parents: 10047
diff changeset
1027 bx lr
11443
361a5fcb4393 ARM: set size of asm functions in object files
mru
parents: 10376
diff changeset
1028 endfunc
10228
b783894a1c62 ARM: NEON optimised scalarproduct_float
mru
parents: 10221
diff changeset
1029
b783894a1c62 ARM: NEON optimised scalarproduct_float
mru
parents: 10221
diff changeset
1030 function ff_scalarproduct_float_neon, export=1
b783894a1c62 ARM: NEON optimised scalarproduct_float
mru
parents: 10221
diff changeset
1031 vmov.f32 q2, #0.0
b783894a1c62 ARM: NEON optimised scalarproduct_float
mru
parents: 10221
diff changeset
1032 1: vld1.32 {q0},[r0,:128]!
b783894a1c62 ARM: NEON optimised scalarproduct_float
mru
parents: 10221
diff changeset
1033 vld1.32 {q1},[r1,:128]!
b783894a1c62 ARM: NEON optimised scalarproduct_float
mru
parents: 10221
diff changeset
1034 vmla.f32 q2, q0, q1
b783894a1c62 ARM: NEON optimised scalarproduct_float
mru
parents: 10221
diff changeset
1035 subs r2, r2, #4
b783894a1c62 ARM: NEON optimised scalarproduct_float
mru
parents: 10221
diff changeset
1036 bgt 1b
b783894a1c62 ARM: NEON optimised scalarproduct_float
mru
parents: 10221
diff changeset
1037 vadd.f32 d0, d4, d5
b783894a1c62 ARM: NEON optimised scalarproduct_float
mru
parents: 10221
diff changeset
1038 vpadd.f32 d0, d0, d0
b783894a1c62 ARM: NEON optimised scalarproduct_float
mru
parents: 10221
diff changeset
1039 NOVFP vmov.32 r0, d0[0]
b783894a1c62 ARM: NEON optimised scalarproduct_float
mru
parents: 10221
diff changeset
1040 bx lr
11443
361a5fcb4393 ARM: set size of asm functions in object files
mru
parents: 10376
diff changeset
1041 endfunc
10253
64dd9515b93b ARM: NEON optimised int32_to_float_fmul_scalar
mru
parents: 10228
diff changeset
1042
64dd9515b93b ARM: NEON optimised int32_to_float_fmul_scalar
mru
parents: 10228
diff changeset
1043 function ff_int32_to_float_fmul_scalar_neon, export=1
64dd9515b93b ARM: NEON optimised int32_to_float_fmul_scalar
mru
parents: 10228
diff changeset
1044 VFP vdup.32 q0, d0[0]
64dd9515b93b ARM: NEON optimised int32_to_float_fmul_scalar
mru
parents: 10228
diff changeset
1045 VFP len .req r2
64dd9515b93b ARM: NEON optimised int32_to_float_fmul_scalar
mru
parents: 10228
diff changeset
1046 NOVFP vdup.32 q0, r2
64dd9515b93b ARM: NEON optimised int32_to_float_fmul_scalar
mru
parents: 10228
diff changeset
1047 NOVFP len .req r3
64dd9515b93b ARM: NEON optimised int32_to_float_fmul_scalar
mru
parents: 10228
diff changeset
1048
64dd9515b93b ARM: NEON optimised int32_to_float_fmul_scalar
mru
parents: 10228
diff changeset
1049 vld1.32 {q1},[r1,:128]!
64dd9515b93b ARM: NEON optimised int32_to_float_fmul_scalar
mru
parents: 10228
diff changeset
1050 vcvt.f32.s32 q3, q1
64dd9515b93b ARM: NEON optimised int32_to_float_fmul_scalar
mru
parents: 10228
diff changeset
1051 vld1.32 {q2},[r1,:128]!
64dd9515b93b ARM: NEON optimised int32_to_float_fmul_scalar
mru
parents: 10228
diff changeset
1052 vcvt.f32.s32 q8, q2
64dd9515b93b ARM: NEON optimised int32_to_float_fmul_scalar
mru
parents: 10228
diff changeset
1053 1: subs len, len, #8
64dd9515b93b ARM: NEON optimised int32_to_float_fmul_scalar
mru
parents: 10228
diff changeset
1054 pld [r1, #16]
64dd9515b93b ARM: NEON optimised int32_to_float_fmul_scalar
mru
parents: 10228
diff changeset
1055 vmul.f32 q9, q3, q0
64dd9515b93b ARM: NEON optimised int32_to_float_fmul_scalar
mru
parents: 10228
diff changeset
1056 vmul.f32 q10, q8, q0
64dd9515b93b ARM: NEON optimised int32_to_float_fmul_scalar
mru
parents: 10228
diff changeset
1057 beq 2f
64dd9515b93b ARM: NEON optimised int32_to_float_fmul_scalar
mru
parents: 10228
diff changeset
1058 vld1.32 {q1},[r1,:128]!
64dd9515b93b ARM: NEON optimised int32_to_float_fmul_scalar
mru
parents: 10228
diff changeset
1059 vcvt.f32.s32 q3, q1
64dd9515b93b ARM: NEON optimised int32_to_float_fmul_scalar
mru
parents: 10228
diff changeset
1060 vld1.32 {q2},[r1,:128]!
64dd9515b93b ARM: NEON optimised int32_to_float_fmul_scalar
mru
parents: 10228
diff changeset
1061 vcvt.f32.s32 q8, q2
64dd9515b93b ARM: NEON optimised int32_to_float_fmul_scalar
mru
parents: 10228
diff changeset
1062 vst1.32 {q9}, [r0,:128]!
64dd9515b93b ARM: NEON optimised int32_to_float_fmul_scalar
mru
parents: 10228
diff changeset
1063 vst1.32 {q10},[r0,:128]!
64dd9515b93b ARM: NEON optimised int32_to_float_fmul_scalar
mru
parents: 10228
diff changeset
1064 b 1b
64dd9515b93b ARM: NEON optimised int32_to_float_fmul_scalar
mru
parents: 10228
diff changeset
1065 2: vst1.32 {q9}, [r0,:128]!
64dd9515b93b ARM: NEON optimised int32_to_float_fmul_scalar
mru
parents: 10228
diff changeset
1066 vst1.32 {q10},[r0,:128]!
64dd9515b93b ARM: NEON optimised int32_to_float_fmul_scalar
mru
parents: 10228
diff changeset
1067 bx lr
64dd9515b93b ARM: NEON optimised int32_to_float_fmul_scalar
mru
parents: 10228
diff changeset
1068 .unreq len
11443
361a5fcb4393 ARM: set size of asm functions in object files
mru
parents: 10376
diff changeset
1069 endfunc
10274
bcf5c5551b3c ARM: NEON optimised vector_fmul_reverse
mru
parents: 10253
diff changeset
1070
bcf5c5551b3c ARM: NEON optimised vector_fmul_reverse
mru
parents: 10253
diff changeset
1071 function ff_vector_fmul_reverse_neon, export=1
bcf5c5551b3c ARM: NEON optimised vector_fmul_reverse
mru
parents: 10253
diff changeset
1072 add r2, r2, r3, lsl #2
bcf5c5551b3c ARM: NEON optimised vector_fmul_reverse
mru
parents: 10253
diff changeset
1073 sub r2, r2, #32
bcf5c5551b3c ARM: NEON optimised vector_fmul_reverse
mru
parents: 10253
diff changeset
1074 mov r12, #-32
bcf5c5551b3c ARM: NEON optimised vector_fmul_reverse
mru
parents: 10253
diff changeset
1075 vld1.32 {q0-q1}, [r1,:128]!
bcf5c5551b3c ARM: NEON optimised vector_fmul_reverse
mru
parents: 10253
diff changeset
1076 vld1.32 {q2-q3}, [r2,:128], r12
bcf5c5551b3c ARM: NEON optimised vector_fmul_reverse
mru
parents: 10253
diff changeset
1077 1: pld [r1, #32]
bcf5c5551b3c ARM: NEON optimised vector_fmul_reverse
mru
parents: 10253
diff changeset
1078 vrev64.32 q3, q3
bcf5c5551b3c ARM: NEON optimised vector_fmul_reverse
mru
parents: 10253
diff changeset
1079 vmul.f32 d16, d0, d7
bcf5c5551b3c ARM: NEON optimised vector_fmul_reverse
mru
parents: 10253
diff changeset
1080 vmul.f32 d17, d1, d6
bcf5c5551b3c ARM: NEON optimised vector_fmul_reverse
mru
parents: 10253
diff changeset
1081 pld [r2, #-32]
bcf5c5551b3c ARM: NEON optimised vector_fmul_reverse
mru
parents: 10253
diff changeset
1082 vrev64.32 q2, q2
bcf5c5551b3c ARM: NEON optimised vector_fmul_reverse
mru
parents: 10253
diff changeset
1083 vmul.f32 d18, d2, d5
bcf5c5551b3c ARM: NEON optimised vector_fmul_reverse
mru
parents: 10253
diff changeset
1084 vmul.f32 d19, d3, d4
bcf5c5551b3c ARM: NEON optimised vector_fmul_reverse
mru
parents: 10253
diff changeset
1085 subs r3, r3, #8
bcf5c5551b3c ARM: NEON optimised vector_fmul_reverse
mru
parents: 10253
diff changeset
1086 beq 2f
bcf5c5551b3c ARM: NEON optimised vector_fmul_reverse
mru
parents: 10253
diff changeset
1087 vld1.32 {q0-q1}, [r1,:128]!
bcf5c5551b3c ARM: NEON optimised vector_fmul_reverse
mru
parents: 10253
diff changeset
1088 vld1.32 {q2-q3}, [r2,:128], r12
bcf5c5551b3c ARM: NEON optimised vector_fmul_reverse
mru
parents: 10253
diff changeset
1089 vst1.32 {q8-q9}, [r0,:128]!
bcf5c5551b3c ARM: NEON optimised vector_fmul_reverse
mru
parents: 10253
diff changeset
1090 b 1b
bcf5c5551b3c ARM: NEON optimised vector_fmul_reverse
mru
parents: 10253
diff changeset
1091 2: vst1.32 {q8-q9}, [r0,:128]!
bcf5c5551b3c ARM: NEON optimised vector_fmul_reverse
mru
parents: 10253
diff changeset
1092 bx lr
11443
361a5fcb4393 ARM: set size of asm functions in object files
mru
parents: 10376
diff changeset
1093 endfunc
10276
06d4e87718b1 ARM: NEON optimised vector_clipf
mru
parents: 10274
diff changeset
1094
10302
6db89678b326 ARM: NEON optimised vector_fmul_add
mru
parents: 10276
diff changeset
1095 function ff_vector_fmul_add_neon, export=1
6db89678b326 ARM: NEON optimised vector_fmul_add
mru
parents: 10276
diff changeset
1096 ldr r12, [sp]
6db89678b326 ARM: NEON optimised vector_fmul_add
mru
parents: 10276
diff changeset
1097 vld1.32 {q0-q1}, [r1,:128]!
6db89678b326 ARM: NEON optimised vector_fmul_add
mru
parents: 10276
diff changeset
1098 vld1.32 {q8-q9}, [r2,:128]!
6db89678b326 ARM: NEON optimised vector_fmul_add
mru
parents: 10276
diff changeset
1099 vld1.32 {q2-q3}, [r3,:128]!
6db89678b326 ARM: NEON optimised vector_fmul_add
mru
parents: 10276
diff changeset
1100 vmul.f32 q10, q0, q8
6db89678b326 ARM: NEON optimised vector_fmul_add
mru
parents: 10276
diff changeset
1101 vmul.f32 q11, q1, q9
6db89678b326 ARM: NEON optimised vector_fmul_add
mru
parents: 10276
diff changeset
1102 1: vadd.f32 q12, q2, q10
6db89678b326 ARM: NEON optimised vector_fmul_add
mru
parents: 10276
diff changeset
1103 vadd.f32 q13, q3, q11
6db89678b326 ARM: NEON optimised vector_fmul_add
mru
parents: 10276
diff changeset
1104 pld [r1, #16]
6db89678b326 ARM: NEON optimised vector_fmul_add
mru
parents: 10276
diff changeset
1105 pld [r2, #16]
6db89678b326 ARM: NEON optimised vector_fmul_add
mru
parents: 10276
diff changeset
1106 pld [r3, #16]
6db89678b326 ARM: NEON optimised vector_fmul_add
mru
parents: 10276
diff changeset
1107 subs r12, r12, #8
6db89678b326 ARM: NEON optimised vector_fmul_add
mru
parents: 10276
diff changeset
1108 beq 2f
6db89678b326 ARM: NEON optimised vector_fmul_add
mru
parents: 10276
diff changeset
1109 vld1.32 {q0}, [r1,:128]!
6db89678b326 ARM: NEON optimised vector_fmul_add
mru
parents: 10276
diff changeset
1110 vld1.32 {q8}, [r2,:128]!
6db89678b326 ARM: NEON optimised vector_fmul_add
mru
parents: 10276
diff changeset
1111 vmul.f32 q10, q0, q8
6db89678b326 ARM: NEON optimised vector_fmul_add
mru
parents: 10276
diff changeset
1112 vld1.32 {q1}, [r1,:128]!
6db89678b326 ARM: NEON optimised vector_fmul_add
mru
parents: 10276
diff changeset
1113 vld1.32 {q9}, [r2,:128]!
6db89678b326 ARM: NEON optimised vector_fmul_add
mru
parents: 10276
diff changeset
1114 vmul.f32 q11, q1, q9
6db89678b326 ARM: NEON optimised vector_fmul_add
mru
parents: 10276
diff changeset
1115 vld1.32 {q2-q3}, [r3,:128]!
6db89678b326 ARM: NEON optimised vector_fmul_add
mru
parents: 10276
diff changeset
1116 vst1.32 {q12-q13},[r0,:128]!
6db89678b326 ARM: NEON optimised vector_fmul_add
mru
parents: 10276
diff changeset
1117 b 1b
6db89678b326 ARM: NEON optimised vector_fmul_add
mru
parents: 10276
diff changeset
1118 2: vst1.32 {q12-q13},[r0,:128]!
6db89678b326 ARM: NEON optimised vector_fmul_add
mru
parents: 10276
diff changeset
1119 bx lr
11443
361a5fcb4393 ARM: set size of asm functions in object files
mru
parents: 10376
diff changeset
1120 endfunc
10302
6db89678b326 ARM: NEON optimised vector_fmul_add
mru
parents: 10276
diff changeset
1121
10276
06d4e87718b1 ARM: NEON optimised vector_clipf
mru
parents: 10274
diff changeset
1122 function ff_vector_clipf_neon, export=1
06d4e87718b1 ARM: NEON optimised vector_clipf
mru
parents: 10274
diff changeset
1123 VFP vdup.32 q1, d0[1]
06d4e87718b1 ARM: NEON optimised vector_clipf
mru
parents: 10274
diff changeset
1124 VFP vdup.32 q0, d0[0]
06d4e87718b1 ARM: NEON optimised vector_clipf
mru
parents: 10274
diff changeset
1125 NOVFP vdup.32 q0, r2
06d4e87718b1 ARM: NEON optimised vector_clipf
mru
parents: 10274
diff changeset
1126 NOVFP vdup.32 q1, r3
06d4e87718b1 ARM: NEON optimised vector_clipf
mru
parents: 10274
diff changeset
1127 NOVFP ldr r2, [sp]
06d4e87718b1 ARM: NEON optimised vector_clipf
mru
parents: 10274
diff changeset
1128 vld1.f32 {q2},[r1,:128]!
06d4e87718b1 ARM: NEON optimised vector_clipf
mru
parents: 10274
diff changeset
1129 vmin.f32 q10, q2, q1
06d4e87718b1 ARM: NEON optimised vector_clipf
mru
parents: 10274
diff changeset
1130 vld1.f32 {q3},[r1,:128]!
06d4e87718b1 ARM: NEON optimised vector_clipf
mru
parents: 10274
diff changeset
1131 vmin.f32 q11, q3, q1
06d4e87718b1 ARM: NEON optimised vector_clipf
mru
parents: 10274
diff changeset
1132 1: vmax.f32 q8, q10, q0
06d4e87718b1 ARM: NEON optimised vector_clipf
mru
parents: 10274
diff changeset
1133 vmax.f32 q9, q11, q0
06d4e87718b1 ARM: NEON optimised vector_clipf
mru
parents: 10274
diff changeset
1134 subs r2, r2, #8
06d4e87718b1 ARM: NEON optimised vector_clipf
mru
parents: 10274
diff changeset
1135 beq 2f
06d4e87718b1 ARM: NEON optimised vector_clipf
mru
parents: 10274
diff changeset
1136 vld1.f32 {q2},[r1,:128]!
06d4e87718b1 ARM: NEON optimised vector_clipf
mru
parents: 10274
diff changeset
1137 vmin.f32 q10, q2, q1
06d4e87718b1 ARM: NEON optimised vector_clipf
mru
parents: 10274
diff changeset
1138 vld1.f32 {q3},[r1,:128]!
06d4e87718b1 ARM: NEON optimised vector_clipf
mru
parents: 10274
diff changeset
1139 vmin.f32 q11, q3, q1
06d4e87718b1 ARM: NEON optimised vector_clipf
mru
parents: 10274
diff changeset
1140 vst1.f32 {q8},[r0,:128]!
06d4e87718b1 ARM: NEON optimised vector_clipf
mru
parents: 10274
diff changeset
1141 vst1.f32 {q9},[r0,:128]!
06d4e87718b1 ARM: NEON optimised vector_clipf
mru
parents: 10274
diff changeset
1142 b 1b
06d4e87718b1 ARM: NEON optimised vector_clipf
mru
parents: 10274
diff changeset
1143 2: vst1.f32 {q8},[r0,:128]!
06d4e87718b1 ARM: NEON optimised vector_clipf
mru
parents: 10274
diff changeset
1144 vst1.f32 {q9},[r0,:128]!
06d4e87718b1 ARM: NEON optimised vector_clipf
mru
parents: 10274
diff changeset
1145 bx lr
11443
361a5fcb4393 ARM: set size of asm functions in object files
mru
parents: 10376
diff changeset
1146 endfunc