annotate i386/mmx.h @ 2299:eb0c851db536 libavcodec

xvid fake divx version workaround
author michael
date Fri, 15 Oct 2004 11:48:50 +0000
parents 15cfba1b97b5
children e04773e8b253
Ignore whitespace changes - Everywhere: Within whitespace: At end of lines:
rev   line source
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
1 /*
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
2 * mmx.h
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
3 * Copyright (C) 1997-2001 H. Dietz and R. Fisher
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
4 */
434
d34dde800cca * avoids double inclusion of this header
kabi
parents: 31
diff changeset
5 #ifndef AVCODEC_I386MMX_H
d34dde800cca * avoids double inclusion of this header
kabi
parents: 31
diff changeset
6 #define AVCODEC_I386MMX_H
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
7
2293
15cfba1b97b5 adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64 patch by (Aurelien Jacobs <aurel at gnuage dot org>)
michael
parents: 1971
diff changeset
8 #ifdef ARCH_X86_64
15cfba1b97b5 adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64 patch by (Aurelien Jacobs <aurel at gnuage dot org>)
michael
parents: 1971
diff changeset
9 # define REG_a "rax"
15cfba1b97b5 adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64 patch by (Aurelien Jacobs <aurel at gnuage dot org>)
michael
parents: 1971
diff changeset
10 #else
15cfba1b97b5 adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64 patch by (Aurelien Jacobs <aurel at gnuage dot org>)
michael
parents: 1971
diff changeset
11 # define REG_a "eax"
15cfba1b97b5 adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64 patch by (Aurelien Jacobs <aurel at gnuage dot org>)
michael
parents: 1971
diff changeset
12 #endif
15cfba1b97b5 adapting existing mmx/mmx2/sse/3dnow optimizations so they work on x86_64 patch by (Aurelien Jacobs <aurel at gnuage dot org>)
michael
parents: 1971
diff changeset
13
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
14 /*
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
15 * The type of an value that fits in an MMX register (note that long
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
16 * long constant values MUST be suffixed by LL and unsigned long long
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
17 * values by ULL, lest they be truncated by the compiler)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
18 */
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
19
986e461dc072 Initial revision
glantau
parents:
diff changeset
20 typedef union {
986e461dc072 Initial revision
glantau
parents:
diff changeset
21 long long q; /* Quadword (64-bit) value */
986e461dc072 Initial revision
glantau
parents:
diff changeset
22 unsigned long long uq; /* Unsigned Quadword */
986e461dc072 Initial revision
glantau
parents:
diff changeset
23 int d[2]; /* 2 Doubleword (32-bit) values */
986e461dc072 Initial revision
glantau
parents:
diff changeset
24 unsigned int ud[2]; /* 2 Unsigned Doubleword */
986e461dc072 Initial revision
glantau
parents:
diff changeset
25 short w[4]; /* 4 Word (16-bit) values */
986e461dc072 Initial revision
glantau
parents:
diff changeset
26 unsigned short uw[4]; /* 4 Unsigned Word */
986e461dc072 Initial revision
glantau
parents:
diff changeset
27 char b[8]; /* 8 Byte (8-bit) values */
986e461dc072 Initial revision
glantau
parents:
diff changeset
28 unsigned char ub[8]; /* 8 Unsigned Byte */
986e461dc072 Initial revision
glantau
parents:
diff changeset
29 float s[2]; /* Single-precision (32-bit) value */
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
30 } mmx_t; /* On an 8-byte (64-bit) boundary */
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
31
986e461dc072 Initial revision
glantau
parents:
diff changeset
32
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
33 #define mmx_i2r(op,imm,reg) \
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
34 __asm__ __volatile__ (#op " %0, %%" #reg \
986e461dc072 Initial revision
glantau
parents:
diff changeset
35 : /* nothing */ \
986e461dc072 Initial revision
glantau
parents:
diff changeset
36 : "i" (imm) )
986e461dc072 Initial revision
glantau
parents:
diff changeset
37
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
38 #define mmx_m2r(op,mem,reg) \
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
39 __asm__ __volatile__ (#op " %0, %%" #reg \
986e461dc072 Initial revision
glantau
parents:
diff changeset
40 : /* nothing */ \
986e461dc072 Initial revision
glantau
parents:
diff changeset
41 : "m" (mem))
986e461dc072 Initial revision
glantau
parents:
diff changeset
42
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
43 #define mmx_r2m(op,reg,mem) \
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
44 __asm__ __volatile__ (#op " %%" #reg ", %0" \
986e461dc072 Initial revision
glantau
parents:
diff changeset
45 : "=m" (mem) \
986e461dc072 Initial revision
glantau
parents:
diff changeset
46 : /* nothing */ )
986e461dc072 Initial revision
glantau
parents:
diff changeset
47
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
48 #define mmx_r2r(op,regs,regd) \
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
49 __asm__ __volatile__ (#op " %" #regs ", %" #regd)
986e461dc072 Initial revision
glantau
parents:
diff changeset
50
986e461dc072 Initial revision
glantau
parents:
diff changeset
51
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
52 #define emms() __asm__ __volatile__ ("emms")
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
53
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
54 #define movd_m2r(var,reg) mmx_m2r (movd, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
55 #define movd_r2m(reg,var) mmx_r2m (movd, reg, var)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
56 #define movd_r2r(regs,regd) mmx_r2r (movd, regs, regd)
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
57
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
58 #define movq_m2r(var,reg) mmx_m2r (movq, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
59 #define movq_r2m(reg,var) mmx_r2m (movq, reg, var)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
60 #define movq_r2r(regs,regd) mmx_r2r (movq, regs, regd)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
61
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
62 #define packssdw_m2r(var,reg) mmx_m2r (packssdw, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
63 #define packssdw_r2r(regs,regd) mmx_r2r (packssdw, regs, regd)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
64 #define packsswb_m2r(var,reg) mmx_m2r (packsswb, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
65 #define packsswb_r2r(regs,regd) mmx_r2r (packsswb, regs, regd)
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
66
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
67 #define packuswb_m2r(var,reg) mmx_m2r (packuswb, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
68 #define packuswb_r2r(regs,regd) mmx_r2r (packuswb, regs, regd)
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
69
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
70 #define paddb_m2r(var,reg) mmx_m2r (paddb, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
71 #define paddb_r2r(regs,regd) mmx_r2r (paddb, regs, regd)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
72 #define paddd_m2r(var,reg) mmx_m2r (paddd, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
73 #define paddd_r2r(regs,regd) mmx_r2r (paddd, regs, regd)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
74 #define paddw_m2r(var,reg) mmx_m2r (paddw, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
75 #define paddw_r2r(regs,regd) mmx_r2r (paddw, regs, regd)
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
76
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
77 #define paddsb_m2r(var,reg) mmx_m2r (paddsb, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
78 #define paddsb_r2r(regs,regd) mmx_r2r (paddsb, regs, regd)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
79 #define paddsw_m2r(var,reg) mmx_m2r (paddsw, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
80 #define paddsw_r2r(regs,regd) mmx_r2r (paddsw, regs, regd)
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
81
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
82 #define paddusb_m2r(var,reg) mmx_m2r (paddusb, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
83 #define paddusb_r2r(regs,regd) mmx_r2r (paddusb, regs, regd)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
84 #define paddusw_m2r(var,reg) mmx_m2r (paddusw, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
85 #define paddusw_r2r(regs,regd) mmx_r2r (paddusw, regs, regd)
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
86
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
87 #define pand_m2r(var,reg) mmx_m2r (pand, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
88 #define pand_r2r(regs,regd) mmx_r2r (pand, regs, regd)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
89
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
90 #define pandn_m2r(var,reg) mmx_m2r (pandn, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
91 #define pandn_r2r(regs,regd) mmx_r2r (pandn, regs, regd)
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
92
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
93 #define pcmpeqb_m2r(var,reg) mmx_m2r (pcmpeqb, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
94 #define pcmpeqb_r2r(regs,regd) mmx_r2r (pcmpeqb, regs, regd)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
95 #define pcmpeqd_m2r(var,reg) mmx_m2r (pcmpeqd, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
96 #define pcmpeqd_r2r(regs,regd) mmx_r2r (pcmpeqd, regs, regd)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
97 #define pcmpeqw_m2r(var,reg) mmx_m2r (pcmpeqw, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
98 #define pcmpeqw_r2r(regs,regd) mmx_r2r (pcmpeqw, regs, regd)
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
99
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
100 #define pcmpgtb_m2r(var,reg) mmx_m2r (pcmpgtb, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
101 #define pcmpgtb_r2r(regs,regd) mmx_r2r (pcmpgtb, regs, regd)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
102 #define pcmpgtd_m2r(var,reg) mmx_m2r (pcmpgtd, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
103 #define pcmpgtd_r2r(regs,regd) mmx_r2r (pcmpgtd, regs, regd)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
104 #define pcmpgtw_m2r(var,reg) mmx_m2r (pcmpgtw, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
105 #define pcmpgtw_r2r(regs,regd) mmx_r2r (pcmpgtw, regs, regd)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
106
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
107 #define pmaddwd_m2r(var,reg) mmx_m2r (pmaddwd, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
108 #define pmaddwd_r2r(regs,regd) mmx_r2r (pmaddwd, regs, regd)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
109
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
110 #define pmulhw_m2r(var,reg) mmx_m2r (pmulhw, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
111 #define pmulhw_r2r(regs,regd) mmx_r2r (pmulhw, regs, regd)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
112
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
113 #define pmullw_m2r(var,reg) mmx_m2r (pmullw, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
114 #define pmullw_r2r(regs,regd) mmx_r2r (pmullw, regs, regd)
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
115
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
116 #define por_m2r(var,reg) mmx_m2r (por, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
117 #define por_r2r(regs,regd) mmx_r2r (por, regs, regd)
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
118
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
119 #define pslld_i2r(imm,reg) mmx_i2r (pslld, imm, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
120 #define pslld_m2r(var,reg) mmx_m2r (pslld, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
121 #define pslld_r2r(regs,regd) mmx_r2r (pslld, regs, regd)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
122 #define psllq_i2r(imm,reg) mmx_i2r (psllq, imm, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
123 #define psllq_m2r(var,reg) mmx_m2r (psllq, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
124 #define psllq_r2r(regs,regd) mmx_r2r (psllq, regs, regd)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
125 #define psllw_i2r(imm,reg) mmx_i2r (psllw, imm, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
126 #define psllw_m2r(var,reg) mmx_m2r (psllw, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
127 #define psllw_r2r(regs,regd) mmx_r2r (psllw, regs, regd)
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
128
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
129 #define psrad_i2r(imm,reg) mmx_i2r (psrad, imm, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
130 #define psrad_m2r(var,reg) mmx_m2r (psrad, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
131 #define psrad_r2r(regs,regd) mmx_r2r (psrad, regs, regd)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
132 #define psraw_i2r(imm,reg) mmx_i2r (psraw, imm, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
133 #define psraw_m2r(var,reg) mmx_m2r (psraw, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
134 #define psraw_r2r(regs,regd) mmx_r2r (psraw, regs, regd)
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
135
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
136 #define psrld_i2r(imm,reg) mmx_i2r (psrld, imm, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
137 #define psrld_m2r(var,reg) mmx_m2r (psrld, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
138 #define psrld_r2r(regs,regd) mmx_r2r (psrld, regs, regd)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
139 #define psrlq_i2r(imm,reg) mmx_i2r (psrlq, imm, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
140 #define psrlq_m2r(var,reg) mmx_m2r (psrlq, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
141 #define psrlq_r2r(regs,regd) mmx_r2r (psrlq, regs, regd)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
142 #define psrlw_i2r(imm,reg) mmx_i2r (psrlw, imm, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
143 #define psrlw_m2r(var,reg) mmx_m2r (psrlw, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
144 #define psrlw_r2r(regs,regd) mmx_r2r (psrlw, regs, regd)
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
145
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
146 #define psubb_m2r(var,reg) mmx_m2r (psubb, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
147 #define psubb_r2r(regs,regd) mmx_r2r (psubb, regs, regd)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
148 #define psubd_m2r(var,reg) mmx_m2r (psubd, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
149 #define psubd_r2r(regs,regd) mmx_r2r (psubd, regs, regd)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
150 #define psubw_m2r(var,reg) mmx_m2r (psubw, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
151 #define psubw_r2r(regs,regd) mmx_r2r (psubw, regs, regd)
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
152
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
153 #define psubsb_m2r(var,reg) mmx_m2r (psubsb, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
154 #define psubsb_r2r(regs,regd) mmx_r2r (psubsb, regs, regd)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
155 #define psubsw_m2r(var,reg) mmx_m2r (psubsw, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
156 #define psubsw_r2r(regs,regd) mmx_r2r (psubsw, regs, regd)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
157
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
158 #define psubusb_m2r(var,reg) mmx_m2r (psubusb, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
159 #define psubusb_r2r(regs,regd) mmx_r2r (psubusb, regs, regd)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
160 #define psubusw_m2r(var,reg) mmx_m2r (psubusw, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
161 #define psubusw_r2r(regs,regd) mmx_r2r (psubusw, regs, regd)
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
162
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
163 #define punpckhbw_m2r(var,reg) mmx_m2r (punpckhbw, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
164 #define punpckhbw_r2r(regs,regd) mmx_r2r (punpckhbw, regs, regd)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
165 #define punpckhdq_m2r(var,reg) mmx_m2r (punpckhdq, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
166 #define punpckhdq_r2r(regs,regd) mmx_r2r (punpckhdq, regs, regd)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
167 #define punpckhwd_m2r(var,reg) mmx_m2r (punpckhwd, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
168 #define punpckhwd_r2r(regs,regd) mmx_r2r (punpckhwd, regs, regd)
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
169
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
170 #define punpcklbw_m2r(var,reg) mmx_m2r (punpcklbw, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
171 #define punpcklbw_r2r(regs,regd) mmx_r2r (punpcklbw, regs, regd)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
172 #define punpckldq_m2r(var,reg) mmx_m2r (punpckldq, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
173 #define punpckldq_r2r(regs,regd) mmx_r2r (punpckldq, regs, regd)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
174 #define punpcklwd_m2r(var,reg) mmx_m2r (punpcklwd, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
175 #define punpcklwd_r2r(regs,regd) mmx_r2r (punpcklwd, regs, regd)
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
176
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
177 #define pxor_m2r(var,reg) mmx_m2r (pxor, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
178 #define pxor_r2r(regs,regd) mmx_r2r (pxor, regs, regd)
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
179
986e461dc072 Initial revision
glantau
parents:
diff changeset
180
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
181 /* 3DNOW extensions */
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
182
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
183 #define pavgusb_m2r(var,reg) mmx_m2r (pavgusb, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
184 #define pavgusb_r2r(regs,regd) mmx_r2r (pavgusb, regs, regd)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
185
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
186
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
187 /* AMD MMX extensions - also available in intel SSE */
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
188
986e461dc072 Initial revision
glantau
parents:
diff changeset
189
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
190 #define mmx_m2ri(op,mem,reg,imm) \
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
191 __asm__ __volatile__ (#op " %1, %0, %%" #reg \
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
192 : /* nothing */ \
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
193 : "X" (mem), "X" (imm))
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
194 #define mmx_r2ri(op,regs,regd,imm) \
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
195 __asm__ __volatile__ (#op " %0, %%" #regs ", %%" #regd \
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
196 : /* nothing */ \
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
197 : "X" (imm) )
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
198
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
199 #define mmx_fetch(mem,hint) \
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
200 __asm__ __volatile__ ("prefetch" #hint " %0" \
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
201 : /* nothing */ \
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
202 : "X" (mem))
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
203
986e461dc072 Initial revision
glantau
parents:
diff changeset
204
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
205 #define maskmovq(regs,maskreg) mmx_r2ri (maskmovq, regs, maskreg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
206
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
207 #define movntq_r2m(mmreg,var) mmx_r2m (movntq, mmreg, var)
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
208
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
209 #define pavgb_m2r(var,reg) mmx_m2r (pavgb, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
210 #define pavgb_r2r(regs,regd) mmx_r2r (pavgb, regs, regd)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
211 #define pavgw_m2r(var,reg) mmx_m2r (pavgw, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
212 #define pavgw_r2r(regs,regd) mmx_r2r (pavgw, regs, regd)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
213
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
214 #define pextrw_r2r(mmreg,reg,imm) mmx_r2ri (pextrw, mmreg, reg, imm)
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
215
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
216 #define pinsrw_r2r(reg,mmreg,imm) mmx_r2ri (pinsrw, reg, mmreg, imm)
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
217
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
218 #define pmaxsw_m2r(var,reg) mmx_m2r (pmaxsw, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
219 #define pmaxsw_r2r(regs,regd) mmx_r2r (pmaxsw, regs, regd)
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
220
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
221 #define pmaxub_m2r(var,reg) mmx_m2r (pmaxub, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
222 #define pmaxub_r2r(regs,regd) mmx_r2r (pmaxub, regs, regd)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
223
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
224 #define pminsw_m2r(var,reg) mmx_m2r (pminsw, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
225 #define pminsw_r2r(regs,regd) mmx_r2r (pminsw, regs, regd)
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
226
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
227 #define pminub_m2r(var,reg) mmx_m2r (pminub, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
228 #define pminub_r2r(regs,regd) mmx_r2r (pminub, regs, regd)
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
229
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
230 #define pmovmskb(mmreg,reg) \
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
231 __asm__ __volatile__ ("movmskps %" #mmreg ", %" #reg)
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
232
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
233 #define pmulhuw_m2r(var,reg) mmx_m2r (pmulhuw, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
234 #define pmulhuw_r2r(regs,regd) mmx_r2r (pmulhuw, regs, regd)
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
235
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
236 #define prefetcht0(mem) mmx_fetch (mem, t0)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
237 #define prefetcht1(mem) mmx_fetch (mem, t1)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
238 #define prefetcht2(mem) mmx_fetch (mem, t2)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
239 #define prefetchnta(mem) mmx_fetch (mem, nta)
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
240
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
241 #define psadbw_m2r(var,reg) mmx_m2r (psadbw, var, reg)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
242 #define psadbw_r2r(regs,regd) mmx_r2r (psadbw, regs, regd)
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
243
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
244 #define pshufw_m2r(var,reg,imm) mmx_m2ri(pshufw, var, reg, imm)
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
245 #define pshufw_r2r(regs,regd,imm) mmx_r2ri(pshufw, regs, regd, imm)
0
986e461dc072 Initial revision
glantau
parents:
diff changeset
246
31
e4b7c3e5e527 updated mmx macros
glantau
parents: 0
diff changeset
247 #define sfence() __asm__ __volatile__ ("sfence\n\t")
434
d34dde800cca * avoids double inclusion of this header
kabi
parents: 31
diff changeset
248
1971
39f2ba94e09b add selected SSE2 ASM macros
melanson
parents: 434
diff changeset
249 /* SSE2 */
39f2ba94e09b add selected SSE2 ASM macros
melanson
parents: 434
diff changeset
250 #define pshufhw_m2r(var,reg,imm) mmx_m2ri(pshufhw, var, reg, imm)
39f2ba94e09b add selected SSE2 ASM macros
melanson
parents: 434
diff changeset
251 #define pshufhw_r2r(regs,regd,imm) mmx_r2ri(pshufhw, regs, regd, imm)
39f2ba94e09b add selected SSE2 ASM macros
melanson
parents: 434
diff changeset
252 #define pshuflw_m2r(var,reg,imm) mmx_m2ri(pshuflw, var, reg, imm)
39f2ba94e09b add selected SSE2 ASM macros
melanson
parents: 434
diff changeset
253 #define pshuflw_r2r(regs,regd,imm) mmx_r2ri(pshuflw, regs, regd, imm)
39f2ba94e09b add selected SSE2 ASM macros
melanson
parents: 434
diff changeset
254
39f2ba94e09b add selected SSE2 ASM macros
melanson
parents: 434
diff changeset
255 #define pshufd_r2r(regs,regd,imm) mmx_r2ri(pshufd, regs, regd, imm)
39f2ba94e09b add selected SSE2 ASM macros
melanson
parents: 434
diff changeset
256
39f2ba94e09b add selected SSE2 ASM macros
melanson
parents: 434
diff changeset
257 #define movdqa_m2r(var,reg) mmx_m2r (movdqa, var, reg)
39f2ba94e09b add selected SSE2 ASM macros
melanson
parents: 434
diff changeset
258 #define movdqa_r2m(reg,var) mmx_r2m (movdqa, reg, var)
39f2ba94e09b add selected SSE2 ASM macros
melanson
parents: 434
diff changeset
259 #define movdqa_r2r(regs,regd) mmx_r2r (movdqa, regs, regd)
39f2ba94e09b add selected SSE2 ASM macros
melanson
parents: 434
diff changeset
260 #define movdqu_m2r(var,reg) mmx_m2r (movdqu, var, reg)
39f2ba94e09b add selected SSE2 ASM macros
melanson
parents: 434
diff changeset
261 #define movdqu_r2m(reg,var) mmx_r2m (movdqu, reg, var)
39f2ba94e09b add selected SSE2 ASM macros
melanson
parents: 434
diff changeset
262 #define movdqu_r2r(regs,regd) mmx_r2r (movdqu, regs, regd)
39f2ba94e09b add selected SSE2 ASM macros
melanson
parents: 434
diff changeset
263
39f2ba94e09b add selected SSE2 ASM macros
melanson
parents: 434
diff changeset
264 #define pmullw_r2m(reg,var) mmx_r2m (pmullw, reg, var)
39f2ba94e09b add selected SSE2 ASM macros
melanson
parents: 434
diff changeset
265
39f2ba94e09b add selected SSE2 ASM macros
melanson
parents: 434
diff changeset
266 #define pslldq_i2r(imm,reg) mmx_i2r (pslldq, imm, reg)
39f2ba94e09b add selected SSE2 ASM macros
melanson
parents: 434
diff changeset
267 #define psrldq_i2r(imm,reg) mmx_i2r (psrldq, imm, reg)
39f2ba94e09b add selected SSE2 ASM macros
melanson
parents: 434
diff changeset
268
39f2ba94e09b add selected SSE2 ASM macros
melanson
parents: 434
diff changeset
269 #define punpcklqdq_r2r(regs,regd) mmx_r2r (punpcklqdq, regs, regd)
39f2ba94e09b add selected SSE2 ASM macros
melanson
parents: 434
diff changeset
270 #define punpckhqdq_r2r(regs,regd) mmx_r2r (punpckhqdq, regs, regd)
39f2ba94e09b add selected SSE2 ASM macros
melanson
parents: 434
diff changeset
271
39f2ba94e09b add selected SSE2 ASM macros
melanson
parents: 434
diff changeset
272
434
d34dde800cca * avoids double inclusion of this header
kabi
parents: 31
diff changeset
273 #endif /* AVCODEC_I386MMX_H */