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changeset 467:4472cc562ee9 libavutil

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typo fixes
author diego
date Wed, 12 Mar 2008 23:58:46 +0000
parents f4fd038fcb58
children b76b4c3a5dde
files mem.c
diffstat 1 files changed, 1 insertions(+), 1 deletions(-) [+]
line wrap: on
line diff
--- a/mem.c	Mon Mar 10 18:42:09 2008 +0000
+++ b/mem.c	Wed Mar 12 23:58:46 2008 +0000
@@ -72,7 +72,7 @@
         Because some CPUs need alignment, for example SSE2 on P4, & most RISC CPUs
         it will just trigger an exception and the unaligned load will be done in the
         exception handler or it will just segfault (SSE2 on P4)
-        Why not larger? because i did not see a difference in benchmarks ...
+        Why not larger? Because I did not see a difference in benchmarks ...
      */
      /* benchmarks with p3
         memalign(64)+1          3071,3051,3032