Mercurial > mplayer.hg
annotate vidix/savage_regs.h @ 25221:00fff9a3b735
Make all vf_info_t structs const
author | reimar |
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date | Sun, 02 Dec 2007 14:57:15 +0000 |
parents | 88bed2131f19 |
children | af2aadfbabc3 |
rev | line source |
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22850 | 1 /* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/savage/savage_regs.h,v 1.10 2001/11/04 22:17:48 alanh Exp $ */ |
2 | |
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3 #ifndef SAVAGE_REGS_H |
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4 #define SAVAGE_REGS_H |
22850 | 5 |
6 /* These are here until xf86PciInfo.h is updated. */ | |
7 | |
8 #ifndef PCI_CHIP_S3TWISTER_P | |
9 #define PCI_CHIP_S3TWISTER_P 0x8d01 | |
10 #endif | |
11 #ifndef PCI_CHIP_S3TWISTER_K | |
12 #define PCI_CHIP_S3TWISTER_K 0x8d02 | |
13 #endif | |
14 #ifndef PCI_CHIP_SUPSAV_MX128 | |
15 #define PCI_CHIP_SUPSAV_MX128 0x8c22 | |
16 #define PCI_CHIP_SUPSAV_MX64 0x8c24 | |
17 #define PCI_CHIP_SUPSAV_MX64C 0x8c26 | |
18 #define PCI_CHIP_SUPSAV_IX128SDR 0x8c2a | |
19 #define PCI_CHIP_SUPSAV_IX128DDR 0x8c2b | |
20 #define PCI_CHIP_SUPSAV_IX64SDR 0x8c2c | |
21 #define PCI_CHIP_SUPSAV_IX64DDR 0x8c2d | |
22 #define PCI_CHIP_SUPSAV_IXCSDR 0x8c2e | |
23 #define PCI_CHIP_SUPSAV_IXCDDR 0x8c2f | |
24 #endif | |
25 #ifndef PCI_CHIP_PROSAVAGE_DDR | |
26 #define PCI_CHIP_PROSAVAGE_DDR 0x8d03 | |
27 #define PCI_CHIP_PROSAVAGE_DDRK 0x8d04 | |
28 #endif | |
29 | |
30 #define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX)) | |
31 | |
32 #define S3_SAVAGE4_SERIES(chip) ((chip==S3_SAVAGE4) || (chip==S3_PROSAVAGE)) | |
33 | |
34 #define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE)) | |
35 | |
36 #define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000)) | |
37 | |
38 | |
39 /* Chip tags. These are used to group the adapters into | |
40 * related families. | |
41 */ | |
42 | |
43 | |
44 enum S3CHIPTAGS { | |
45 S3_UNKNOWN = 0, | |
46 S3_SAVAGE3D, | |
47 S3_SAVAGE_MX, | |
48 S3_SAVAGE4, | |
49 S3_PROSAVAGE, | |
50 S3_SUPERSAVAGE, | |
51 S3_SAVAGE2000, | |
52 S3_LAST | |
53 }; | |
54 | |
55 typedef struct { | |
56 unsigned int mode, refresh; | |
57 unsigned char SR08, SR0E, SR0F; | |
58 unsigned char SR10, SR11, SR12, SR13, SR15, SR18, SR1B, SR29, SR30; | |
59 unsigned char SR54[8]; | |
60 unsigned char Clock; | |
61 unsigned char CR31, CR32, CR33, CR34, CR36, CR3A, CR3B, CR3C; | |
62 unsigned char CR40, CR41, CR42, CR43, CR45; | |
63 unsigned char CR50, CR51, CR53, CR55, CR58, CR5B, CR5D, CR5E; | |
64 unsigned char CR60, CR63, CR65, CR66, CR67, CR68, CR69, CR6D, CR6F; | |
65 unsigned char CR86, CR88; | |
66 unsigned char CR90, CR91, CRB0; | |
67 unsigned int STREAMS[22]; /* yuck, streams regs */ | |
68 unsigned int MMPR0, MMPR1, MMPR2, MMPR3; | |
69 } SavageRegRec, *SavageRegPtr; | |
70 | |
71 | |
72 | |
73 #define BIOS_BSIZE 1024 | |
74 #define BIOS_BASE 0xc0000 | |
75 | |
76 #define SAVAGE_NEWMMIO_REGBASE_S3 0x1000000 /* 16MB */ | |
77 #define SAVAGE_NEWMMIO_REGBASE_S4 0x0000000 | |
78 #define SAVAGE_NEWMMIO_REGSIZE 0x0080000 /* 512kb */ | |
79 #define SAVAGE_NEWMMIO_VGABASE 0x8000 | |
80 | |
81 #define BASE_FREQ 14.31818 | |
82 | |
83 #define FIFO_CONTROL_REG 0x8200 | |
84 #define MIU_CONTROL_REG 0x8204 | |
85 #define STREAMS_TIMEOUT_REG 0x8208 | |
86 #define MISC_TIMEOUT_REG 0x820c | |
87 | |
88 /* Stream Processor 1 */ | |
89 | |
90 /* Primary Stream 1 Frame Buffer Address 0 */ | |
91 #define PRI_STREAM_FBUF_ADDR0 0x81c0 | |
92 /* Primary Stream 1 Frame Buffer Address 0 */ | |
93 #define PRI_STREAM_FBUF_ADDR1 0x81c4 | |
94 /* Primary Stream 1 Stride */ | |
95 #define PRI_STREAM_STRIDE 0x81c8 | |
96 /* Primary Stream 1 Frame Buffer Size */ | |
97 #define PRI_STREAM_BUFFERSIZE 0x8214 | |
98 | |
99 /* Secondary stream 1 Color/Chroma Key Control */ | |
100 #define SEC_STREAM_CKEY_LOW 0x8184 | |
101 /* Secondary stream 1 Chroma Key Upper Bound */ | |
102 #define SEC_STREAM_CKEY_UPPER 0x8194 | |
103 /* Blend Control of Secondary Stream 1 & 2 */ | |
104 #define BLEND_CONTROL 0x8190 | |
105 /* Secondary Stream 1 Color conversion/Adjustment 1 */ | |
106 #define SEC_STREAM_COLOR_CONVERT1 0x8198 | |
107 /* Secondary Stream 1 Color conversion/Adjustment 2 */ | |
108 #define SEC_STREAM_COLOR_CONVERT2 0x819c | |
109 /* Secondary Stream 1 Color conversion/Adjustment 3 */ | |
110 #define SEC_STREAM_COLOR_CONVERT3 0x81e4 | |
111 /* Secondary Stream 1 Horizontal Scaling */ | |
112 #define SEC_STREAM_HSCALING 0x81a0 | |
113 /* Secondary Stream 1 Frame Buffer Size */ | |
114 #define SEC_STREAM_BUFFERSIZE 0x81a8 | |
115 /* Secondary Stream 1 Horizontal Scaling Normalization (2K only) */ | |
116 #define SEC_STREAM_HSCALE_NORMALIZE 0x81ac | |
117 /* Secondary Stream 1 Horizontal Scaling */ | |
118 #define SEC_STREAM_VSCALING 0x81e8 | |
119 /* Secondary Stream 1 Frame Buffer Address 0 */ | |
120 #define SEC_STREAM_FBUF_ADDR0 0x81d0 | |
121 /* Secondary Stream 1 Frame Buffer Address 1 */ | |
122 #define SEC_STREAM_FBUF_ADDR1 0x81d4 | |
123 /* Secondary Stream 1 Frame Buffer Address 2 */ | |
124 #define SEC_STREAM_FBUF_ADDR2 0x81ec | |
125 /* Secondary Stream 1 Stride */ | |
126 #define SEC_STREAM_STRIDE 0x81d8 | |
127 /* Secondary Stream 1 Window Start Coordinates */ | |
128 #define SEC_STREAM_WINDOW_START 0x81f8 | |
129 /* Secondary Stream 1 Window Size */ | |
130 #define SEC_STREAM_WINDOW_SZ 0x81fc | |
131 /* Secondary Streams Tile Offset */ | |
132 #define SEC_STREAM_TILE_OFF 0x821c | |
133 /* Secondary Stream 1 Opaque Overlay Control */ | |
134 #define SEC_STREAM_OPAQUE_OVERLAY 0x81dc | |
135 | |
136 | |
137 /* Stream Processor 2 */ | |
138 | |
139 /* Primary Stream 2 Frame Buffer Address 0 */ | |
140 #define PRI_STREAM2_FBUF_ADDR0 0x81b0 | |
141 /* Primary Stream 2 Frame Buffer Address 1 */ | |
142 #define PRI_STREAM2_FBUF_ADDR1 0x81b4 | |
143 /* Primary Stream 2 Stride */ | |
144 #define PRI_STREAM2_STRIDE 0x81b8 | |
145 /* Primary Stream 2 Frame Buffer Size */ | |
146 #define PRI_STREAM2_BUFFERSIZE 0x8218 | |
147 | |
148 /* Secondary Stream 2 Color/Chroma Key Control */ | |
149 #define SEC_STREAM2_CKEY_LOW 0x8188 | |
150 /* Secondary Stream 2 Chroma Key Upper Bound */ | |
151 #define SEC_STREAM2_CKEY_UPPER 0x818c | |
152 /* Secondary Stream 2 Horizontal Scaling */ | |
153 #define SEC_STREAM2_HSCALING 0x81a4 | |
154 /* Secondary Stream 2 Horizontal Scaling */ | |
155 #define SEC_STREAM2_VSCALING 0x8204 | |
156 /* Secondary Stream 2 Frame Buffer Size */ | |
157 #define SEC_STREAM2_BUFFERSIZE 0x81ac | |
158 /* Secondary Stream 2 Frame Buffer Address 0 */ | |
159 #define SEC_STREAM2_FBUF_ADDR0 0x81bc | |
160 /* Secondary Stream 2 Frame Buffer Address 1 */ | |
161 #define SEC_STREAM2_FBUF_ADDR1 0x81e0 | |
162 /* Secondary Stream 2 Frame Buffer Address 2 */ | |
163 #define SEC_STREAM2_FBUF_ADDR2 0x8208 | |
164 /* Multiple Buffer/LPB and Secondary Stream 2 Stride */ | |
165 #define SEC_STREAM2_STRIDE_LPB 0x81cc | |
166 /* Secondary Stream 2 Color conversion/Adjustment 1 */ | |
167 #define SEC_STREAM2_COLOR_CONVERT1 0x81f0 | |
168 /* Secondary Stream 2 Color conversion/Adjustment 2 */ | |
169 #define SEC_STREAM2_COLOR_CONVERT2 0x81f4 | |
170 /* Secondary Stream 2 Color conversion/Adjustment 3 */ | |
171 #define SEC_STREAM2_COLOR_CONVERT3 0x8200 | |
172 /* Secondary Stream 2 Window Start Coordinates */ | |
173 #define SEC_STREAM2_WINDOW_START 0x820c | |
174 /* Secondary Stream 2 Window Size */ | |
175 #define SEC_STREAM2_WINDOW_SZ 0x8210 | |
176 /* Secondary Stream 2 Opaque Overlay Control */ | |
177 #define SEC_STREAM2_OPAQUE_OVERLAY 0x8180 | |
178 | |
179 | |
180 /* savage 2000 */ | |
181 #define SEC_STREAM_COLOR_CONVERT0_2000 0x8198 | |
182 #define SEC_STREAM_COLOR_CONVERT1_2000 0x819c | |
183 #define SEC_STREAM_COLOR_CONVERT2_2000 0x81e0 | |
184 #define SEC_STREAM_COLOR_CONVERT3_2000 0x81e4 | |
185 | |
186 #define SUBSYS_STAT_REG 0x8504 | |
187 | |
188 #define SRC_BASE 0xa4d4 | |
189 #define DEST_BASE 0xa4d8 | |
190 #define CLIP_L_R 0xa4dc | |
191 #define CLIP_T_B 0xa4e0 | |
192 #define DEST_SRC_STR 0xa4e4 | |
193 #define MONO_PAT_0 0xa4e8 | |
194 #define MONO_PAT_1 0xa4ec | |
195 | |
196 /* Constants for CR69. */ | |
197 | |
198 #define CRT_ACTIVE 0x01 | |
199 #define LCD_ACTIVE 0x02 | |
200 #define TV_ACTIVE 0x04 | |
201 #define CRT_ATTACHED 0x10 | |
202 #define LCD_ATTACHED 0x20 | |
203 #define TV_ATTACHED 0x40 | |
204 | |
205 | |
206 /* | |
207 * reads from SUBSYS_STAT | |
208 */ | |
209 #define STATUS_WORD0 (INREG(0x48C00)) | |
210 #define ALT_STATUS_WORD0 (INREG(0x48C60)) | |
211 #define MAXLOOP 0xffffff | |
212 #define IN_SUBSYS_STAT() (INREG(SUBSYS_STAT_REG)) | |
213 | |
214 #define MAXFIFO 0x7f00 | |
215 | |
216 /* | |
217 * NOTE: don't remove 'VGAIN8(vgaCRIndex);'. | |
218 * If not present it will cause lockups on Savage4. | |
219 * Ask S3, why. | |
220 */ | |
221 /*#define VerticalRetraceWait() \ | |
222 { \ | |
223 VGAIN8(0x3d0+4); \ | |
224 VGAOUT8(0x3d0+4, 0x17); \ | |
225 if (VGAIN8(0x3d0+5) & 0x80) { \ | |
226 while ((VGAIN8(0x3d0 + 0x0a) & 0x08) == 0x08) ; \ | |
227 while ((VGAIN8(0x3d0 + 0x0a) & 0x08) == 0x00) ; \ | |
228 } \ | |
229 } | |
230 */ | |
231 | |
232 #define VerticalRetraceWait() \ | |
233 do { \ | |
234 VGAIN8(0x3d4); \ | |
235 VGAOUT8(0x3d4, 0x17); \ | |
236 if (VGAIN8(0x3d5) & 0x80) { \ | |
237 int i = 0x10000; \ | |
238 while ((VGAIN8(0x3da) & 0x08) == 0x08 && i--) ; \ | |
239 i = 0x10000; \ | |
240 while ((VGAIN8(0x3da) & 0x08) == 0x00 && i--) ; \ | |
241 } \ | |
242 } while (0) | |
243 | |
244 | |
245 #define I2C_REG 0xa0 | |
246 #define InI2CREG(a) \ | |
247 { \ | |
248 VGAOUT8(0x3d0 + 4, I2C_REG); \ | |
249 a = VGAIN8(0x3d0 + 5); \ | |
250 } | |
251 | |
252 #define OutI2CREG(a) \ | |
253 { \ | |
254 VGAOUT8(0x3d0 + 4, I2C_REG); \ | |
255 VGAOUT8(0x3d0 + 5, a); \ | |
256 } | |
257 | |
258 #define HZEXP_COMP_1 0x54 | |
259 #define HZEXP_BORDER 0x58 | |
260 #define HZEXP_FACTOR_IGA1 0x59 | |
261 | |
262 #define VTEXP_COMP_1 0x56 | |
263 #define VTEXP_BORDER 0x5a | |
264 #define VTEXP_FACTOR_IGA1 0x5b | |
265 | |
266 #define EC1_CENTER_ON 0x10 | |
267 #define EC1_EXPAND_ON 0x0c | |
268 | |
269 #define MODE_24 24 | |
270 | |
271 #if (MODE_24 == 32) | |
272 # define BYTES_PP24 4 | |
273 #else | |
274 # define BYTES_PP24 3 | |
275 #endif | |
276 | |
277 #define OVERLAY_DEPTH 16 | |
278 | |
279 #define STREAMS_MODE32 0x7 | |
280 #define STREAMS_MODE24 0x6 | |
281 #define STREAMS_MODE16 0x5 /* @@@ */ | |
282 | |
283 | |
284 #define DEPTH_BPP(depth) (depth == 24 ? (BYTES_PP24 << 3) : (depth + 7) & ~0x7) | |
285 #define DEPTH_2ND(depth) (depth > 8 ? depth\ | |
286 : OVERLAY_DEPTH) | |
287 #define SSTREAMS_MODE(bpp) (bpp > 16 ? (bpp > 24 ? STREAMS_MODE32 :\ | |
288 STREAMS_MODE24) : STREAMS_MODE16) | |
289 | |
290 #define HSCALING_Shift 0 | |
291 #define HSCALING_Mask (((1L << 16)-1) << HSCALING_Shift) | |
292 #define HSCALING(w0,w1) ((((unsigned int)(((double)w0/(double)w1) * (1 << 15))) \ | |
293 << HSCALING_Shift) \ | |
294 & HSCALING_Mask) | |
295 | |
296 #define VSCALING_Shift 0 | |
297 #define VSCALING_Mask (((1L << 20)-1) << VSCALING_Shift) | |
298 #define VSCALING(h0,h1) ((((unsigned int) (((double)h0/(double)h1) * (1 << 15))) \ | |
299 << VSCALING_Shift) \ | |
300 & VSCALING_Mask) | |
301 | |
302 | |
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303 #endif /* SAVAGE_REGS_H */ |