Mercurial > mplayer.hg
changeset 22850:9a1e26fef45b
Move driver files directly into the vidix directory.
| author | diego |
|---|---|
| date | Sun, 01 Apr 2007 00:02:43 +0000 |
| parents | bddb09395c3e |
| children | e878a71cb27f |
| files | vidix/Makefile vidix/cyberblade_regs.h vidix/cyberblade_vid.c vidix/drivers/cyberblade_regs.h vidix/drivers/cyberblade_vid.c vidix/drivers/mach64.h vidix/drivers/mach64_vid.c vidix/drivers/mga_vid.c vidix/drivers/nvidia_vid.c vidix/drivers/pm3_regs.h vidix/drivers/pm3_vid.c vidix/drivers/radeon.h vidix/drivers/radeon_vid.c vidix/drivers/savage_regs.h vidix/drivers/savage_vid.c vidix/drivers/sis_bridge.c vidix/drivers/sis_defs.h vidix/drivers/sis_regs.h vidix/drivers/sis_vid.c vidix/drivers/unichrome_regs.h vidix/drivers/unichrome_vid.c vidix/mach64.h vidix/mach64_vid.c vidix/mga_vid.c vidix/nvidia_vid.c vidix/pm3_regs.h vidix/pm3_vid.c vidix/radeon.h vidix/radeon_vid.c vidix/savage_regs.h vidix/savage_vid.c vidix/sis_bridge.c vidix/sis_defs.h vidix/sis_regs.h vidix/sis_vid.c vidix/unichrome_regs.h vidix/unichrome_vid.c |
| diffstat | 37 files changed, 18817 insertions(+), 18820 deletions(-) [+] |
line wrap: on
line diff
--- a/vidix/Makefile Sat Mar 31 23:48:48 2007 +0000 +++ b/vidix/Makefile Sun Apr 01 00:02:43 2007 +0000 @@ -3,18 +3,15 @@ LIBNAME_MPLAYER = libvidix.a SRCS_MPLAYER = vidixlib.c \ - $(wildcard drivers/*.c) + $(wildcard *.c) -OBJS_MPLAYER = drivers/mga_crtc2_vid.o \ - drivers/rage128_vid.o \ +OBJS_MPLAYER = mga_crtc2_vid.o \ + rage128_vid.o \ include ../mpcommon.mak -drivers/mga_crtc2_vid.o: drivers/mga_vid.c +mga_crtc2_vid.o: mga_vid.c $(CC) -c $(CFLAGS) -DCRTC2 -o $@ $< -drivers/rage128_vid.o: drivers/radeon_vid.c +rage128_vid.o: radeon_vid.c $(CC) -c $(CFLAGS) -DRAGE128 -o $@ $< - -clean:: - rm -f drivers/*.o drivers/*~
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/vidix/cyberblade_regs.h Sun Apr 01 00:02:43 2007 +0000 @@ -0,0 +1,136 @@ +/* + * Copyright 1992-2000 by Alan Hourihane, Wigan, England. + * + * Permission to use, copy, modify, distribute, and sell this software and its + * documentation for any purpose is hereby granted without fee, provided that + * the above copyright notice appear in all copies and that both that + * copyright notice and this permission notice appear in supporting + * documentation, and that the name of Alan Hourihane not be used in + * advertising or publicity pertaining to distribution of the software without + * specific, written prior permission. Alan Hourihane makes no representations + * about the suitability of this software for any purpose. It is provided + * "as is" without express or implied warranty. + * + * ALAN HOURIHANE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, + * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO + * EVENT SHALL ALAN HOURIHANE BE LIABLE FOR ANY SPECIAL, INDIRECT OR + * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, + * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER + * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR + * PERFORMANCE OF THIS SOFTWARE. + * + * Author: Alan Hourihane, alanh@fairlite.demon.co.uk + */ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/trident/trident_regs.h,v 1.22 2002/01/11 13:06:30 alanh Exp $ */ + +#define DEBUG 1 + +#define NTSC 14.31818 +#define PAL 17.73448 + +/* General Registers */ +#define SPR 0x1F /* Software Programming Register (videoram) */ + +/* 3C4 */ +#define RevisionID 0x09 +#define ConfPort1 0x0C +#define ConfPort2 0x0C +#define NewMode2 0x0D +#define OldMode2 0x00 /* Should be 0x0D - dealt with in trident_dac.c */ +#define OldMode1 0x0E +#define NewMode1 0x0E +#define Protection 0x11 +#define MCLKLow 0x16 +#define MCLKHigh 0x17 +#define ClockLow 0x18 +#define ClockHigh 0x19 +#define SSetup 0x20 +#define SKey 0x37 +#define SPKey 0x57 + +/* 3x4 */ +#define Offset 0x13 +#define Underline 0x14 +#define CRTCMode 0x17 +#define CRTCModuleTest 0x1E +#define FIFOControl 0x20 +#define LinearAddReg 0x21 +#define DRAMTiming 0x23 +#define New32 0x23 +#define RAMDACTiming 0x25 +#define CRTHiOrd 0x27 +#define AddColReg 0x29 +#define InterfaceSel 0x2A +#define HorizOverflow 0x2B +#define GETest 0x2D +#define Performance 0x2F +#define GraphEngReg 0x36 +#define I2C 0x37 +#define PixelBusReg 0x38 +#define PCIReg 0x39 +#define DRAMControl 0x3A +#define MiscContReg 0x3C +#define CursorXLow 0x40 +#define CursorXHigh 0x41 +#define CursorYLow 0x42 +#define CursorYHigh 0x43 +#define CursorLocLow 0x44 +#define CursorLocHigh 0x45 +#define CursorXOffset 0x46 +#define CursorYOffset 0x47 +#define CursorFG1 0x48 +#define CursorFG2 0x49 +#define CursorFG3 0x4A +#define CursorFG4 0x4B +#define CursorBG1 0x4C +#define CursorBG2 0x4D +#define CursorBG3 0x4E +#define CursorBG4 0x4F +#define CursorControl 0x50 +#define PCIRetry 0x55 +#define PreEndControl 0x56 +#define PreEndFetch 0x57 +#define PCIMaster 0x60 +#define Enhancement0 0x62 +#define NewEDO 0x64 + +/* --- Additions by AMR for Vidix support --- */ +#define VideoWin1_HScale 0x80 +#define VideoWin1_VScale 0x82 +#define VideoWin1_Start 0x86 +#define VideoWin1_Stop 0x8a +#define Video_Flags 0x8e +#define VideoWin1_Y_BPR 0x90 +#define VideoWin1_Y_Offset 0x92 +#define Video_LineBufferThreshold 0x95 +#define Video_LineBufferLevel 0x96 +#define Video_Flags2 0x97 +/* --- */ + +#define TVinterface 0xC0 +#define TVMode 0xC1 +#define ClockControl 0xCF + + +/* 3CE */ +#define MiscExtFunc 0x0F +#define MiscIntContReg 0x2F +#define CyberControl 0x30 +#define CyberEnhance 0x31 +#define FPConfig 0x33 +#define VertStretch 0x52 +#define HorStretch 0x53 +#define BiosMode 0x5c +#define BiosNewMode1 0x5a +#define BiosNewMode2 0x5c +#define BiosReg 0x5d + +/* --- IO Macros by AMR --- */ + +#define CRINB(reg) (OUTPORT8(0x3d4,reg), INPORT8(0x3d5)) +#define SRINB(reg) (OUTPORT8(0x3c4,reg), INPORT8(0x3c5)) +#define CROUTB(reg,val) (OUTPORT8(0x3d4,reg), OUTPORT8(0x3d5,val)) +#define SROUTB(reg,val) (OUTPORT8(0x3c4,reg), OUTPORT8(0x3c5,val)) + +/* --- */ +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/vidix/cyberblade_vid.c Sun Apr 01 00:02:43 2007 +0000 @@ -0,0 +1,647 @@ +/* + Driver for CyberBlade/i1 - Version 0.1.4 + + Copyright (C) 2002 by Alastair M. Robinson. + Official homepage: http://www.blackfiveservices.co.uk/EPIAVidix.shtml + + Based on Permedia 3 driver by Måns Rullgård + + Thanks to Gilles Frattini for bugfixes + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Changes: + 18/01/03 + MMIO is no longer used, sidestepping cache issues on EPIA-800 + TV-Out modes are now better supported - this should be the end + of the magenta stripes :) + Brightness/Contrast controls disabled for the time being - they were + seriously degrading picture quality, especially with TV-Out. + + To Do: + Implement Hue/Saturation controls + Support / Test multiple frames + Test colour-key code more extensively +*/ + +#include <errno.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <inttypes.h> +#include <unistd.h> + +#include "vidix.h" +#include "fourcc.h" +#include "../libdha/libdha.h" +#include "../libdha/pci_ids.h" +#include "../libdha/pci_names.h" +#include "../config.h" + +#include "cyberblade_regs.h" + +pciinfo_t pci_info; + +char save_colourkey[6]; +char *cyberblade_mem; + +#ifdef DEBUG_LOGFILE +FILE *logfile=0; +#define LOGWRITE(x) {if(logfile) fprintf(logfile,x);} +#else +#define LOGWRITE(x) +#endif + +/* Helper functions for reading registers. */ + +static int CRINW(int reg) +{ + int result; + result=CRINB(reg); + result|=CRINB(reg+1)<<8; + return(result); +} + +static void CROUTW(int reg,int val) +{ + CROUTB(reg,val&255); + CROUTB(reg+1,(val>>8)&255); +} + +static int SRINW(int reg) +{ + int result; + result=SRINB(reg); + result|=SRINB(reg+1)<<8; + return(result); +} + +static void SROUTW(int reg,int val) +{ + SROUTB(reg,val&255); + SROUTB(reg+1,(val>>8)&255); +} + +void DumpRegisters(void) +{ + int reg,val; +#ifdef DEBUG_LOGFILE + if(logfile) + { + LOGWRITE("CRTC Register Dump:\n") + for(reg=0;reg<256;++reg) + { + val=CRINB(reg); + fprintf(logfile,"CR0x%2x: 0x%2x\n",reg,val); + } + LOGWRITE("SR Register Dump:\n") + for(reg=0;reg<256;++reg) + { + val=SRINB(reg); + fprintf(logfile,"SR0x%2x: 0x%2x\n",reg,val); + } + } +#endif +} +/* --- */ + +static vidix_capability_t cyberblade_cap = +{ + "Trident CyberBlade i1 driver", + "Alastair M. Robinson <blackfive@fakenhamweb.co.uk>", + TYPE_OUTPUT, + { 0, 0, 0, 0 }, + 1024, + 1024, + 4, + 4, + -1, + FLAG_UPSCALER|FLAG_DOWNSCALER, + VENDOR_TRIDENT, + -1, + { 0, 0, 0, 0 } +}; + + +unsigned int vixGetVersion(void) +{ + return(VIDIX_VERSION); +} + + +static unsigned short cyberblade_card_ids[] = +{ + DEVICE_TRIDENT_CYBERBLADE_I7, + DEVICE_TRIDENT_CYBERBLADE_I7D, + DEVICE_TRIDENT_CYBERBLADE_I1, + DEVICE_TRIDENT_CYBERBLADE_I12, + DEVICE_TRIDENT_CYBERBLADE_I13, + DEVICE_TRIDENT_CYBERBLADE_XPAI1 +}; + + +static int find_chip(unsigned chip_id) +{ + unsigned i; + for(i = 0;i < sizeof(cyberblade_card_ids)/sizeof(unsigned short);i++) + { + if(chip_id == cyberblade_card_ids[i]) return i; + } + return -1; +} + +int vixProbe(int verbose, int force) +{ + pciinfo_t lst[MAX_PCI_DEVICES]; + unsigned i,num_pci; + int err; + err = pci_scan(lst,&num_pci); + if(err) + { + printf("[cyberblade] Error occurred during pci scan: %s\n",strerror(err)); + return err; + } + else + { + err = ENXIO; + for(i=0; i < num_pci; i++) + { + if(lst[i].vendor == VENDOR_TRIDENT) + { + int idx; + const char *dname; + idx = find_chip(lst[i].device); + if(idx == -1) + continue; + dname = pci_device_name(VENDOR_TRIDENT, lst[i].device); + dname = dname ? dname : "Unknown chip"; + printf("[cyberblade] Found chip: %s\n", dname); + if ((lst[i].command & PCI_COMMAND_IO) == 0) + { + printf("[cyberblade] Device is disabled, ignoring\n"); + continue; + } + cyberblade_cap.device_id = lst[i].device; + err = 0; + memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); + break; + } + } + } + + if(err && verbose) printf("[cyberblade] Can't find chip\n"); + return err; +} + + +int vixInit(void) +{ + cyberblade_mem = map_phys_mem(pci_info.base0, 0x800000); + enable_app_io(); + save_colourkey[0]=SRINB(0x50); + save_colourkey[1]=SRINB(0x51); + save_colourkey[2]=SRINB(0x52); + save_colourkey[3]=SRINB(0x54); + save_colourkey[4]=SRINB(0x55); + save_colourkey[5]=SRINB(0x56); +#ifdef DEBUG_LOGFILE + logfile=fopen("/tmp/cyberblade_vidix.log","w"); +#endif + return 0; +} + +void vixDestroy(void) +{ + int protect; +#ifdef DEBUG_LOGFILE + if(logfile) + fclose(logfile); +#endif + protect=SRINB(0x11); + SROUTB(0x11, 0x92); + CROUTB(0x8E, 0xc4); /* Disable overlay */ + SROUTB(0x50,save_colourkey[0]); + SROUTB(0x51,save_colourkey[1]); + SROUTB(0x52,save_colourkey[2]); + SROUTB(0x54,save_colourkey[3]); + SROUTB(0x55,save_colourkey[4]); + SROUTB(0x56,save_colourkey[5]); + SROUTB(0x11, protect); + disable_app_io(); + unmap_phys_mem(cyberblade_mem, 0x800000); +} + + +int vixGetCapability(vidix_capability_t *to) +{ + memcpy(to, &cyberblade_cap, sizeof(vidix_capability_t)); + return 0; +} + + +static int is_supported_fourcc(uint32_t fourcc) +{ + switch(fourcc) + { + case IMGFMT_YUY2: + case IMGFMT_YV12: + case IMGFMT_I420: + case IMGFMT_YVU9: + case IMGFMT_BGR16: + return 1; + default: + return 0; + } +} + +int vixQueryFourcc(vidix_fourcc_t *to) +{ + if(is_supported_fourcc(to->fourcc)) + { + to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | + VID_DEPTH_4BPP | VID_DEPTH_8BPP | + VID_DEPTH_12BPP| VID_DEPTH_15BPP| + VID_DEPTH_16BPP| VID_DEPTH_24BPP| + VID_DEPTH_32BPP; + to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; + return 0; + } + else + to->depth = to->flags = 0; + return ENOSYS; +} + + +static int frames[VID_PLAY_MAXFRAMES]; + +static vidix_grkey_t cyberblade_grkey; + +int vixGetGrKeys(vidix_grkey_t *grkey) +{ + memcpy(grkey, &cyberblade_grkey, sizeof(vidix_grkey_t)); + return(0); +} + +int vixSetGrKeys(const vidix_grkey_t *grkey) +{ + int pixfmt=CRINB(0x38); + int protect; + memcpy(&cyberblade_grkey, grkey, sizeof(vidix_grkey_t)); + + protect=SRINB(0x11); + SROUTB(0x11, 0x92); + + if(pixfmt&0x28) /* 32 or 24 bpp */ + { + SROUTB(0x50, cyberblade_grkey.ckey.blue); /* Colour Key */ + SROUTB(0x51, cyberblade_grkey.ckey.green); /* Colour Key */ + SROUTB(0x52, cyberblade_grkey.ckey.red); /* Colour Key */ + SROUTB(0x54, 0xff); /* Colour Key Mask */ + SROUTB(0x55, 0xff); /* Colour Key Mask */ + SROUTB(0x56, 0xff); /* Colour Key Mask */ + } + else + { + int tmp=((cyberblade_grkey.ckey.blue & 0xF8)>>3) + | ((cyberblade_grkey.ckey.green & 0xfc)<<3) + | ((cyberblade_grkey.ckey.red & 0xf8)<<8); + SROUTB(0x50, tmp&0xff); /* Colour Key */ + SROUTB(0x51, (tmp>>8)&0xff); /* Colour Key */ + SROUTB(0x52, 0); /* Colour Key */ + SROUTB(0x54, 0xff); /* Colour Key Mask */ + SROUTB(0x55, 0xff); /* Colour Key Mask */ + SROUTB(0x56, 0x00); /* Colour Key Mask */ + } + SROUTB(0x11,protect); + return(0); +} + + +vidix_video_eq_t equal = +{ + VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION | VEQ_CAP_HUE, + 300, 100, 0, 0, 0, 0, 0, 0 +}; + +int vixPlaybackGetEq( vidix_video_eq_t * eq) +{ + memcpy(eq,&equal,sizeof(vidix_video_eq_t)); + return 0; +} + +int vixPlaybackSetEq( const vidix_video_eq_t * eq) +{ + int br,sat,cr,protect; + if(eq->cap & VEQ_CAP_BRIGHTNESS) equal.brightness = eq->brightness; + if(eq->cap & VEQ_CAP_CONTRAST) equal.contrast = eq->contrast; + if(eq->cap & VEQ_CAP_SATURATION) equal.saturation = eq->saturation; + if(eq->cap & VEQ_CAP_HUE) equal.hue = eq->hue; + if(eq->cap & VEQ_CAP_RGB_INTENSITY) + { + equal.red_intensity = eq->red_intensity; + equal.green_intensity = eq->green_intensity; + equal.blue_intensity = eq->blue_intensity; + } + equal.flags = eq->flags; + + cr = (equal.contrast) * 31 / 2000; cr+=16; + if (cr < 0) cr = 0; if(cr > 7) cr = 7; + cr=cr<<4 | cr; + + br = (equal.brightness+1000) * 63 / 2000; + if (br < 0) br = 0; if(br > 63) br = 63; + if(br>32) br-=32; else br+=32; + + sat = (equal.saturation + 1000) * 16 / 2000; + if (sat < 0) sat = 0; if(sat > 31) sat = 31; + + protect=SRINB(0x11); + SROUTB(0x11, 0x92); + + SROUTB(0xBC,cr); + SROUTW(0xB0,(br<<10)|4); + + SROUTB(0x11, protect); + + return 0; +} + + +static int YOffs,UOffs,VOffs; + +int vixConfigPlayback(vidix_playback_t *info) +{ + int shrink, zoom; + int src_w, drw_w; + int src_h, drw_h; + int hscale,vscale; + long base0; + int y_pitch, uv_pitch; + int protect=0; + int layout=0; + unsigned int i; + + if(!is_supported_fourcc(info->fourcc)) + return -1; + + src_w = info->src.w; + src_h = info->src.h; + + drw_w = info->dest.w; + drw_h = info->dest.h; + + switch(info->fourcc) + { + case IMGFMT_YUY2: + case IMGFMT_BGR16: + y_pitch = (src_w*2 + 15) & ~15; + uv_pitch = 0; + YOffs=VOffs=UOffs=info->offset.y = info->offset.v = info->offset.u = 0; + info->frame_size = y_pitch*src_h; + layout=0x0; /* packed */ + break; + case IMGFMT_YV12: + case IMGFMT_I420: + y_pitch = (src_w+15) & ~15; + uv_pitch = ((src_w/2)+7) & ~7; + YOffs=info->offset.y = 0; + VOffs=info->offset.v = y_pitch*src_h; + UOffs=info->offset.u = info->offset.v+(uv_pitch)*(src_h/2); + info->frame_size = y_pitch*src_h + 2*uv_pitch*(src_h/2); + layout=0x1; /* planar, 4:1:1 */ + break; + case IMGFMT_YVU9: + y_pitch = (src_w+15) & ~15; + uv_pitch = ((src_w/4)+3) & ~3; + YOffs=info->offset.y = 0; + VOffs=info->offset.v = y_pitch*src_h; + UOffs=info->offset.u = info->offset.v+(uv_pitch)*(src_h/4); + info->frame_size = y_pitch*src_h + 2*uv_pitch*(src_h/4); + layout=0x51; /* planar, 16:1:1 */ + break; + } + + /* Assume we have 2 MB to play with */ + info->num_frames = 0x200000 / info->frame_size; + if(info->num_frames > VID_PLAY_MAXFRAMES) + info->num_frames = VID_PLAY_MAXFRAMES; + + /* Start at 6 MB. Let's hope it's not in use. */ + base0 = 0x600000; + info->dga_addr = cyberblade_mem + base0; + + info->dest.pitch.y = 16; + info->dest.pitch.u = 16; + info->dest.pitch.v = 16; + + for(i = 0; i < info->num_frames; i++) + { + info->offsets[i] = info->frame_size * i; + frames[i] = base0+info->offsets[i]; + } + + OUTPORT8(0x3d4,0x39); + OUTPORT8(0x3d5,INPORT(0x3d5)|1); + + SRINB(0x0b); /* Select new mode */ + + /* Unprotect hardware registers... */ + protect=SRINB(0x11); + SROUTB(0x11, 0x92); + + SROUTB(0x57, 0xc0); /* Playback key function */ + SROUTB(0x21, 0x34); /* Signature control */ + SROUTB(0x37, 0x30); /* Video key mode */ + + vixSetGrKeys(&cyberblade_grkey); + + /* compute_scale_factor(&src_w, &drw_w, &shrink, &zoom); */ + { + int HTotal,VTotal,HSync,VSync,Overflow,HDisp,VDisp; + int HWinStart,VWinStart; + int tx1,ty1,tx2,ty2; + + HTotal=CRINB(0x00); + HSync=CRINB(0x04); + VTotal=CRINB(0x06); + VSync=CRINB(0x10); + Overflow=CRINB(0x07); + HTotal <<=3; + HSync <<=3; + VTotal |= (Overflow & 1) <<8; + VTotal |= (Overflow & 0x20) <<4; + VTotal +=4; + VSync |= (Overflow & 4) <<6; + VSync |= (Overflow & 0x80) <<2; + + if(CRINB(0xd1)&0x80) + { + int TVHTotal,TVVTotal,TVHSyncStart,TVVSyncStart,TVOverflow; + LOGWRITE("[cyberblade] Using TV-CRTC\n"); + + HDisp=(1+CRINB(0x01))*8; + VDisp=1+CRINB(0x12); + Overflow=CRINB(0x07); + VDisp |= (Overflow & 2) <<7; + VDisp |= (Overflow & 0x40) << 3; + + TVHTotal=CRINB(0xe0)*8; + TVVTotal=CRINB(0xe6); + TVOverflow=CRINB(0xe7); + if(TVOverflow&0x20) TVVTotal|=512; + if(TVOverflow&0x01) TVVTotal|=256; + TVHTotal+=40; TVVTotal+=2; + + TVHSyncStart=CRINB(0xe4)*8; + TVVSyncStart=CRINB(0xf0); + if(TVOverflow&0x80) TVVSyncStart|=512; + if(TVOverflow&0x04) TVVSyncStart|=256; + + HWinStart=(TVHTotal-HDisp)&15; + HWinStart|=(HTotal-HDisp)&15; + HWinStart+=(TVHTotal-TVHSyncStart)-49; + } + else + { + LOGWRITE("[cyberblade] Using Standard CRTC\n"); + HWinStart=(HTotal-HSync)+15; + } + VWinStart=(VTotal-VSync)-8; + + printf("[cyberblade] HTotal: 0x%x, HSStart: 0x%x\n",HTotal,HSync); + printf(" VTotal: 0x%x, VStart: 0x%x\n",VTotal,VSync); + tx1=HWinStart+info->dest.x; + ty1=VWinStart+info->dest.y; + tx2=tx1+info->dest.w; + ty2=ty1+info->dest.h; + + CROUTW(0x86,tx1); + CROUTW(0x88,ty1); + CROUTW(0x8a,tx2); + CROUTW(0x8c,ty2+3); + } + + if(src_w==drw_w) + hscale=0; + else if(src_w<drw_w) + { + hscale=((src_w<<10)/(drw_w-2)) & 0x1fff; + } + else + { + hscale=0x8000 | ((((src_w/drw_w)-1)&7)<<10) | (((drw_w<<10)/src_w) & 0x3ff); + } + + vscale=(src_h<<10)/(drw_h); + if(drw_h<src_h) + vscale=0x8000|((drw_h<<10)/(src_h)); + + /* Write scale factors to hardware */ + + CROUTW(0x80,hscale); /* Horizontal Scale */ + CROUTW(0x82,vscale); /* Vertical Scale */ + + /* Now set the start address and data layout */ + { + int lb = (y_pitch+2) >> 2; + CROUTB(0x95, ((lb & 0x100)>>1) | 0x08 ); /* Linebuffer level bit 8 & threshold */ + CROUTB(0x96, (lb & 0xFF)); /* Linebuffer level */ + + CROUTB(0x97, 0x00); /* VDE Flags */ + CROUTB(0xBA, 0x00); /* Chroma key */ + CROUTB(0xBB, 0x00); /* Chroma key */ + CROUTB(0xBC, 0xFF); /* Chroma key */ + CROUTB(0xBD, 0xFF); /* Chroma key */ + CROUTB(0xBE, 0x04); /* Capture control */ + + if(src_w > 384) + layout|=4; /* 2x line buffers */ + SROUTB(0x97, layout); + + CROUTW(0x90,y_pitch); /* Y Bytes per row */ + SROUTW(0x9A,uv_pitch); /* UV Bytes per row */ + + switch(info->fourcc) + { + case IMGFMT_BGR16: + CROUTB(0x8F, 0x24); /* VDE Flags - Edge Recovery & CSC Bypass */ + CROUTB(0xBF, 0x02); /* Video format - RGB16 */ + SROUTB(0xBE, 0x0); /* HSCB disabled */ + break; + default: + CROUTB(0x8F, 0x20); /* VDE Flags - Edge Recovery */ + CROUTB(0xBF, 0x00); /* Video format - YUV */ + SROUTB(0xBE, 0x00); /* HSCB disable - was 0x03*/ + break; + } + + CROUTB(0x92, ((base0+info->offset.y) >> 3) &0xff); /* Lower 8 bits of start address */ + CROUTB(0x93, ((base0+info->offset.y) >> 11) &0xff); /* Mid 8 bits of start address */ + CROUTB(0x94, ((base0+info->offset.y) >> 19) &0xf); /* Upper 4 bits of start address */ + SROUTB(0x80, ((base0+info->offset.v) >> 3) &0xff); /* Lower 8 bits of start address */ + SROUTB(0x81, ((base0+info->offset.v) >> 11) &0xff); /* Mid 8 bits of start address */ + SROUTB(0x82, ((base0+info->offset.v) >> 19) &0xf); /* Upper 4 bits of start address */ + SROUTB(0x83, ((base0+info->offset.u) >> 3) &0xff); /* Lower 8 bits of start address */ + SROUTB(0x84, ((base0+info->offset.u) >> 11) &0xff); /* Mid 8 bits of start address */ + SROUTB(0x85, ((base0+info->offset.u) >> 19) &0xf); /* Upper 4 bits of start address */ + } + + vixPlaybackSetEq(&equal); + + /* Protect hardware registers again */ + SROUTB(0x11, protect); + return 0; +} + + +int vixPlaybackOn(void) +{ + LOGWRITE("Enable overlay\n"); + CROUTB(0x8E, 0xd4); /* VDE Flags*/ + + return 0; +} + + +int vixPlaybackOff(void) +{ + LOGWRITE("Disable overlay\n"); + CROUTB(0x8E, 0xc4); /* VDE Flags*/ + + return 0; +} + + +int vixPlaybackFrameSelect(unsigned int frame) +{ + int protect; + LOGWRITE("Frame select\n"); + protect=SRINB(0x11); + SROUTB(0x11, 0x92); + /* Set overlay address to that of selected frame */ + CROUTB(0x92, ((frames[frame]+YOffs) >> 3) &0xff); /* Lower 8 bits of start address */ + CROUTB(0x93, ((frames[frame]+YOffs) >> 11) &0xff); /* Mid 8 bits of start address */ + CROUTB(0x94, ((frames[frame]+YOffs) >> 19) &0xf); /* Upper 4 bits of start address */ + SROUTB(0x80, ((frames[frame]+VOffs) >> 3) &0xff); /* Lower 8 bits of start address */ + SROUTB(0x81, ((frames[frame]+VOffs) >> 11) &0xff); /* Mid 8 bits of start address */ + SROUTB(0x82, ((frames[frame]+VOffs) >> 19) &0xf); /* Upper 4 bits of start address */ + SROUTB(0x83, ((frames[frame]+UOffs) >> 3) &0xff); /* Lower 8 bits of start address */ + SROUTB(0x84, ((frames[frame]+UOffs) >> 11) &0xff); /* Mid 8 bits of start address */ + SROUTB(0x85, ((frames[frame]+UOffs) >> 19) &0xf); /* Upper 4 bits of start address */ + SROUTB(0x11, protect); + return 0; +} + +
--- a/vidix/drivers/cyberblade_regs.h Sat Mar 31 23:48:48 2007 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,136 +0,0 @@ -/* - * Copyright 1992-2000 by Alan Hourihane, Wigan, England. - * - * Permission to use, copy, modify, distribute, and sell this software and its - * documentation for any purpose is hereby granted without fee, provided that - * the above copyright notice appear in all copies and that both that - * copyright notice and this permission notice appear in supporting - * documentation, and that the name of Alan Hourihane not be used in - * advertising or publicity pertaining to distribution of the software without - * specific, written prior permission. Alan Hourihane makes no representations - * about the suitability of this software for any purpose. It is provided - * "as is" without express or implied warranty. - * - * ALAN HOURIHANE DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, - * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO - * EVENT SHALL ALAN HOURIHANE BE LIABLE FOR ANY SPECIAL, INDIRECT OR - * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, - * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER - * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR - * PERFORMANCE OF THIS SOFTWARE. - * - * Author: Alan Hourihane, alanh@fairlite.demon.co.uk - */ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/trident/trident_regs.h,v 1.22 2002/01/11 13:06:30 alanh Exp $ */ - -#define DEBUG 1 - -#define NTSC 14.31818 -#define PAL 17.73448 - -/* General Registers */ -#define SPR 0x1F /* Software Programming Register (videoram) */ - -/* 3C4 */ -#define RevisionID 0x09 -#define ConfPort1 0x0C -#define ConfPort2 0x0C -#define NewMode2 0x0D -#define OldMode2 0x00 /* Should be 0x0D - dealt with in trident_dac.c */ -#define OldMode1 0x0E -#define NewMode1 0x0E -#define Protection 0x11 -#define MCLKLow 0x16 -#define MCLKHigh 0x17 -#define ClockLow 0x18 -#define ClockHigh 0x19 -#define SSetup 0x20 -#define SKey 0x37 -#define SPKey 0x57 - -/* 3x4 */ -#define Offset 0x13 -#define Underline 0x14 -#define CRTCMode 0x17 -#define CRTCModuleTest 0x1E -#define FIFOControl 0x20 -#define LinearAddReg 0x21 -#define DRAMTiming 0x23 -#define New32 0x23 -#define RAMDACTiming 0x25 -#define CRTHiOrd 0x27 -#define AddColReg 0x29 -#define InterfaceSel 0x2A -#define HorizOverflow 0x2B -#define GETest 0x2D -#define Performance 0x2F -#define GraphEngReg 0x36 -#define I2C 0x37 -#define PixelBusReg 0x38 -#define PCIReg 0x39 -#define DRAMControl 0x3A -#define MiscContReg 0x3C -#define CursorXLow 0x40 -#define CursorXHigh 0x41 -#define CursorYLow 0x42 -#define CursorYHigh 0x43 -#define CursorLocLow 0x44 -#define CursorLocHigh 0x45 -#define CursorXOffset 0x46 -#define CursorYOffset 0x47 -#define CursorFG1 0x48 -#define CursorFG2 0x49 -#define CursorFG3 0x4A -#define CursorFG4 0x4B -#define CursorBG1 0x4C -#define CursorBG2 0x4D -#define CursorBG3 0x4E -#define CursorBG4 0x4F -#define CursorControl 0x50 -#define PCIRetry 0x55 -#define PreEndControl 0x56 -#define PreEndFetch 0x57 -#define PCIMaster 0x60 -#define Enhancement0 0x62 -#define NewEDO 0x64 - -/* --- Additions by AMR for Vidix support --- */ -#define VideoWin1_HScale 0x80 -#define VideoWin1_VScale 0x82 -#define VideoWin1_Start 0x86 -#define VideoWin1_Stop 0x8a -#define Video_Flags 0x8e -#define VideoWin1_Y_BPR 0x90 -#define VideoWin1_Y_Offset 0x92 -#define Video_LineBufferThreshold 0x95 -#define Video_LineBufferLevel 0x96 -#define Video_Flags2 0x97 -/* --- */ - -#define TVinterface 0xC0 -#define TVMode 0xC1 -#define ClockControl 0xCF - - -/* 3CE */ -#define MiscExtFunc 0x0F -#define MiscIntContReg 0x2F -#define CyberControl 0x30 -#define CyberEnhance 0x31 -#define FPConfig 0x33 -#define VertStretch 0x52 -#define HorStretch 0x53 -#define BiosMode 0x5c -#define BiosNewMode1 0x5a -#define BiosNewMode2 0x5c -#define BiosReg 0x5d - -/* --- IO Macros by AMR --- */ - -#define CRINB(reg) (OUTPORT8(0x3d4,reg), INPORT8(0x3d5)) -#define SRINB(reg) (OUTPORT8(0x3c4,reg), INPORT8(0x3c5)) -#define CROUTB(reg,val) (OUTPORT8(0x3d4,reg), OUTPORT8(0x3d5,val)) -#define SROUTB(reg,val) (OUTPORT8(0x3c4,reg), OUTPORT8(0x3c5,val)) - -/* --- */ -
--- a/vidix/drivers/cyberblade_vid.c Sat Mar 31 23:48:48 2007 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,647 +0,0 @@ -/* - Driver for CyberBlade/i1 - Version 0.1.4 - - Copyright (C) 2002 by Alastair M. Robinson. - Official homepage: http://www.blackfiveservices.co.uk/EPIAVidix.shtml - - Based on Permedia 3 driver by Måns Rullgård - - Thanks to Gilles Frattini for bugfixes - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - - Changes: - 18/01/03 - MMIO is no longer used, sidestepping cache issues on EPIA-800 - TV-Out modes are now better supported - this should be the end - of the magenta stripes :) - Brightness/Contrast controls disabled for the time being - they were - seriously degrading picture quality, especially with TV-Out. - - To Do: - Implement Hue/Saturation controls - Support / Test multiple frames - Test colour-key code more extensively -*/ - -#include <errno.h> -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include <inttypes.h> -#include <unistd.h> - -#include "../vidix.h" -#include "../fourcc.h" -#include "../../libdha/libdha.h" -#include "../../libdha/pci_ids.h" -#include "../../libdha/pci_names.h" -#include "../../config.h" - -#include "cyberblade_regs.h" - -pciinfo_t pci_info; - -char save_colourkey[6]; -char *cyberblade_mem; - -#ifdef DEBUG_LOGFILE -FILE *logfile=0; -#define LOGWRITE(x) {if(logfile) fprintf(logfile,x);} -#else -#define LOGWRITE(x) -#endif - -/* Helper functions for reading registers. */ - -static int CRINW(int reg) -{ - int result; - result=CRINB(reg); - result|=CRINB(reg+1)<<8; - return(result); -} - -static void CROUTW(int reg,int val) -{ - CROUTB(reg,val&255); - CROUTB(reg+1,(val>>8)&255); -} - -static int SRINW(int reg) -{ - int result; - result=SRINB(reg); - result|=SRINB(reg+1)<<8; - return(result); -} - -static void SROUTW(int reg,int val) -{ - SROUTB(reg,val&255); - SROUTB(reg+1,(val>>8)&255); -} - -void DumpRegisters(void) -{ - int reg,val; -#ifdef DEBUG_LOGFILE - if(logfile) - { - LOGWRITE("CRTC Register Dump:\n") - for(reg=0;reg<256;++reg) - { - val=CRINB(reg); - fprintf(logfile,"CR0x%2x: 0x%2x\n",reg,val); - } - LOGWRITE("SR Register Dump:\n") - for(reg=0;reg<256;++reg) - { - val=SRINB(reg); - fprintf(logfile,"SR0x%2x: 0x%2x\n",reg,val); - } - } -#endif -} -/* --- */ - -static vidix_capability_t cyberblade_cap = -{ - "Trident CyberBlade i1 driver", - "Alastair M. Robinson <blackfive@fakenhamweb.co.uk>", - TYPE_OUTPUT, - { 0, 0, 0, 0 }, - 1024, - 1024, - 4, - 4, - -1, - FLAG_UPSCALER|FLAG_DOWNSCALER, - VENDOR_TRIDENT, - -1, - { 0, 0, 0, 0 } -}; - - -unsigned int vixGetVersion(void) -{ - return(VIDIX_VERSION); -} - - -static unsigned short cyberblade_card_ids[] = -{ - DEVICE_TRIDENT_CYBERBLADE_I7, - DEVICE_TRIDENT_CYBERBLADE_I7D, - DEVICE_TRIDENT_CYBERBLADE_I1, - DEVICE_TRIDENT_CYBERBLADE_I12, - DEVICE_TRIDENT_CYBERBLADE_I13, - DEVICE_TRIDENT_CYBERBLADE_XPAI1 -}; - - -static int find_chip(unsigned chip_id) -{ - unsigned i; - for(i = 0;i < sizeof(cyberblade_card_ids)/sizeof(unsigned short);i++) - { - if(chip_id == cyberblade_card_ids[i]) return i; - } - return -1; -} - -int vixProbe(int verbose, int force) -{ - pciinfo_t lst[MAX_PCI_DEVICES]; - unsigned i,num_pci; - int err; - err = pci_scan(lst,&num_pci); - if(err) - { - printf("[cyberblade] Error occurred during pci scan: %s\n",strerror(err)); - return err; - } - else - { - err = ENXIO; - for(i=0; i < num_pci; i++) - { - if(lst[i].vendor == VENDOR_TRIDENT) - { - int idx; - const char *dname; - idx = find_chip(lst[i].device); - if(idx == -1) - continue; - dname = pci_device_name(VENDOR_TRIDENT, lst[i].device); - dname = dname ? dname : "Unknown chip"; - printf("[cyberblade] Found chip: %s\n", dname); - if ((lst[i].command & PCI_COMMAND_IO) == 0) - { - printf("[cyberblade] Device is disabled, ignoring\n"); - continue; - } - cyberblade_cap.device_id = lst[i].device; - err = 0; - memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); - break; - } - } - } - - if(err && verbose) printf("[cyberblade] Can't find chip\n"); - return err; -} - - -int vixInit(void) -{ - cyberblade_mem = map_phys_mem(pci_info.base0, 0x800000); - enable_app_io(); - save_colourkey[0]=SRINB(0x50); - save_colourkey[1]=SRINB(0x51); - save_colourkey[2]=SRINB(0x52); - save_colourkey[3]=SRINB(0x54); - save_colourkey[4]=SRINB(0x55); - save_colourkey[5]=SRINB(0x56); -#ifdef DEBUG_LOGFILE - logfile=fopen("/tmp/cyberblade_vidix.log","w"); -#endif - return 0; -} - -void vixDestroy(void) -{ - int protect; -#ifdef DEBUG_LOGFILE - if(logfile) - fclose(logfile); -#endif - protect=SRINB(0x11); - SROUTB(0x11, 0x92); - CROUTB(0x8E, 0xc4); /* Disable overlay */ - SROUTB(0x50,save_colourkey[0]); - SROUTB(0x51,save_colourkey[1]); - SROUTB(0x52,save_colourkey[2]); - SROUTB(0x54,save_colourkey[3]); - SROUTB(0x55,save_colourkey[4]); - SROUTB(0x56,save_colourkey[5]); - SROUTB(0x11, protect); - disable_app_io(); - unmap_phys_mem(cyberblade_mem, 0x800000); -} - - -int vixGetCapability(vidix_capability_t *to) -{ - memcpy(to, &cyberblade_cap, sizeof(vidix_capability_t)); - return 0; -} - - -static int is_supported_fourcc(uint32_t fourcc) -{ - switch(fourcc) - { - case IMGFMT_YUY2: - case IMGFMT_YV12: - case IMGFMT_I420: - case IMGFMT_YVU9: - case IMGFMT_BGR16: - return 1; - default: - return 0; - } -} - -int vixQueryFourcc(vidix_fourcc_t *to) -{ - if(is_supported_fourcc(to->fourcc)) - { - to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | - VID_DEPTH_4BPP | VID_DEPTH_8BPP | - VID_DEPTH_12BPP| VID_DEPTH_15BPP| - VID_DEPTH_16BPP| VID_DEPTH_24BPP| - VID_DEPTH_32BPP; - to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; - return 0; - } - else - to->depth = to->flags = 0; - return ENOSYS; -} - - -static int frames[VID_PLAY_MAXFRAMES]; - -static vidix_grkey_t cyberblade_grkey; - -int vixGetGrKeys(vidix_grkey_t *grkey) -{ - memcpy(grkey, &cyberblade_grkey, sizeof(vidix_grkey_t)); - return(0); -} - -int vixSetGrKeys(const vidix_grkey_t *grkey) -{ - int pixfmt=CRINB(0x38); - int protect; - memcpy(&cyberblade_grkey, grkey, sizeof(vidix_grkey_t)); - - protect=SRINB(0x11); - SROUTB(0x11, 0x92); - - if(pixfmt&0x28) /* 32 or 24 bpp */ - { - SROUTB(0x50, cyberblade_grkey.ckey.blue); /* Colour Key */ - SROUTB(0x51, cyberblade_grkey.ckey.green); /* Colour Key */ - SROUTB(0x52, cyberblade_grkey.ckey.red); /* Colour Key */ - SROUTB(0x54, 0xff); /* Colour Key Mask */ - SROUTB(0x55, 0xff); /* Colour Key Mask */ - SROUTB(0x56, 0xff); /* Colour Key Mask */ - } - else - { - int tmp=((cyberblade_grkey.ckey.blue & 0xF8)>>3) - | ((cyberblade_grkey.ckey.green & 0xfc)<<3) - | ((cyberblade_grkey.ckey.red & 0xf8)<<8); - SROUTB(0x50, tmp&0xff); /* Colour Key */ - SROUTB(0x51, (tmp>>8)&0xff); /* Colour Key */ - SROUTB(0x52, 0); /* Colour Key */ - SROUTB(0x54, 0xff); /* Colour Key Mask */ - SROUTB(0x55, 0xff); /* Colour Key Mask */ - SROUTB(0x56, 0x00); /* Colour Key Mask */ - } - SROUTB(0x11,protect); - return(0); -} - - -vidix_video_eq_t equal = -{ - VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION | VEQ_CAP_HUE, - 300, 100, 0, 0, 0, 0, 0, 0 -}; - -int vixPlaybackGetEq( vidix_video_eq_t * eq) -{ - memcpy(eq,&equal,sizeof(vidix_video_eq_t)); - return 0; -} - -int vixPlaybackSetEq( const vidix_video_eq_t * eq) -{ - int br,sat,cr,protect; - if(eq->cap & VEQ_CAP_BRIGHTNESS) equal.brightness = eq->brightness; - if(eq->cap & VEQ_CAP_CONTRAST) equal.contrast = eq->contrast; - if(eq->cap & VEQ_CAP_SATURATION) equal.saturation = eq->saturation; - if(eq->cap & VEQ_CAP_HUE) equal.hue = eq->hue; - if(eq->cap & VEQ_CAP_RGB_INTENSITY) - { - equal.red_intensity = eq->red_intensity; - equal.green_intensity = eq->green_intensity; - equal.blue_intensity = eq->blue_intensity; - } - equal.flags = eq->flags; - - cr = (equal.contrast) * 31 / 2000; cr+=16; - if (cr < 0) cr = 0; if(cr > 7) cr = 7; - cr=cr<<4 | cr; - - br = (equal.brightness+1000) * 63 / 2000; - if (br < 0) br = 0; if(br > 63) br = 63; - if(br>32) br-=32; else br+=32; - - sat = (equal.saturation + 1000) * 16 / 2000; - if (sat < 0) sat = 0; if(sat > 31) sat = 31; - - protect=SRINB(0x11); - SROUTB(0x11, 0x92); - - SROUTB(0xBC,cr); - SROUTW(0xB0,(br<<10)|4); - - SROUTB(0x11, protect); - - return 0; -} - - -static int YOffs,UOffs,VOffs; - -int vixConfigPlayback(vidix_playback_t *info) -{ - int shrink, zoom; - int src_w, drw_w; - int src_h, drw_h; - int hscale,vscale; - long base0; - int y_pitch, uv_pitch; - int protect=0; - int layout=0; - unsigned int i; - - if(!is_supported_fourcc(info->fourcc)) - return -1; - - src_w = info->src.w; - src_h = info->src.h; - - drw_w = info->dest.w; - drw_h = info->dest.h; - - switch(info->fourcc) - { - case IMGFMT_YUY2: - case IMGFMT_BGR16: - y_pitch = (src_w*2 + 15) & ~15; - uv_pitch = 0; - YOffs=VOffs=UOffs=info->offset.y = info->offset.v = info->offset.u = 0; - info->frame_size = y_pitch*src_h; - layout=0x0; /* packed */ - break; - case IMGFMT_YV12: - case IMGFMT_I420: - y_pitch = (src_w+15) & ~15; - uv_pitch = ((src_w/2)+7) & ~7; - YOffs=info->offset.y = 0; - VOffs=info->offset.v = y_pitch*src_h; - UOffs=info->offset.u = info->offset.v+(uv_pitch)*(src_h/2); - info->frame_size = y_pitch*src_h + 2*uv_pitch*(src_h/2); - layout=0x1; /* planar, 4:1:1 */ - break; - case IMGFMT_YVU9: - y_pitch = (src_w+15) & ~15; - uv_pitch = ((src_w/4)+3) & ~3; - YOffs=info->offset.y = 0; - VOffs=info->offset.v = y_pitch*src_h; - UOffs=info->offset.u = info->offset.v+(uv_pitch)*(src_h/4); - info->frame_size = y_pitch*src_h + 2*uv_pitch*(src_h/4); - layout=0x51; /* planar, 16:1:1 */ - break; - } - - /* Assume we have 2 MB to play with */ - info->num_frames = 0x200000 / info->frame_size; - if(info->num_frames > VID_PLAY_MAXFRAMES) - info->num_frames = VID_PLAY_MAXFRAMES; - - /* Start at 6 MB. Let's hope it's not in use. */ - base0 = 0x600000; - info->dga_addr = cyberblade_mem + base0; - - info->dest.pitch.y = 16; - info->dest.pitch.u = 16; - info->dest.pitch.v = 16; - - for(i = 0; i < info->num_frames; i++) - { - info->offsets[i] = info->frame_size * i; - frames[i] = base0+info->offsets[i]; - } - - OUTPORT8(0x3d4,0x39); - OUTPORT8(0x3d5,INPORT(0x3d5)|1); - - SRINB(0x0b); /* Select new mode */ - - /* Unprotect hardware registers... */ - protect=SRINB(0x11); - SROUTB(0x11, 0x92); - - SROUTB(0x57, 0xc0); /* Playback key function */ - SROUTB(0x21, 0x34); /* Signature control */ - SROUTB(0x37, 0x30); /* Video key mode */ - - vixSetGrKeys(&cyberblade_grkey); - - /* compute_scale_factor(&src_w, &drw_w, &shrink, &zoom); */ - { - int HTotal,VTotal,HSync,VSync,Overflow,HDisp,VDisp; - int HWinStart,VWinStart; - int tx1,ty1,tx2,ty2; - - HTotal=CRINB(0x00); - HSync=CRINB(0x04); - VTotal=CRINB(0x06); - VSync=CRINB(0x10); - Overflow=CRINB(0x07); - HTotal <<=3; - HSync <<=3; - VTotal |= (Overflow & 1) <<8; - VTotal |= (Overflow & 0x20) <<4; - VTotal +=4; - VSync |= (Overflow & 4) <<6; - VSync |= (Overflow & 0x80) <<2; - - if(CRINB(0xd1)&0x80) - { - int TVHTotal,TVVTotal,TVHSyncStart,TVVSyncStart,TVOverflow; - LOGWRITE("[cyberblade] Using TV-CRTC\n"); - - HDisp=(1+CRINB(0x01))*8; - VDisp=1+CRINB(0x12); - Overflow=CRINB(0x07); - VDisp |= (Overflow & 2) <<7; - VDisp |= (Overflow & 0x40) << 3; - - TVHTotal=CRINB(0xe0)*8; - TVVTotal=CRINB(0xe6); - TVOverflow=CRINB(0xe7); - if(TVOverflow&0x20) TVVTotal|=512; - if(TVOverflow&0x01) TVVTotal|=256; - TVHTotal+=40; TVVTotal+=2; - - TVHSyncStart=CRINB(0xe4)*8; - TVVSyncStart=CRINB(0xf0); - if(TVOverflow&0x80) TVVSyncStart|=512; - if(TVOverflow&0x04) TVVSyncStart|=256; - - HWinStart=(TVHTotal-HDisp)&15; - HWinStart|=(HTotal-HDisp)&15; - HWinStart+=(TVHTotal-TVHSyncStart)-49; - } - else - { - LOGWRITE("[cyberblade] Using Standard CRTC\n"); - HWinStart=(HTotal-HSync)+15; - } - VWinStart=(VTotal-VSync)-8; - - printf("[cyberblade] HTotal: 0x%x, HSStart: 0x%x\n",HTotal,HSync); - printf(" VTotal: 0x%x, VStart: 0x%x\n",VTotal,VSync); - tx1=HWinStart+info->dest.x; - ty1=VWinStart+info->dest.y; - tx2=tx1+info->dest.w; - ty2=ty1+info->dest.h; - - CROUTW(0x86,tx1); - CROUTW(0x88,ty1); - CROUTW(0x8a,tx2); - CROUTW(0x8c,ty2+3); - } - - if(src_w==drw_w) - hscale=0; - else if(src_w<drw_w) - { - hscale=((src_w<<10)/(drw_w-2)) & 0x1fff; - } - else - { - hscale=0x8000 | ((((src_w/drw_w)-1)&7)<<10) | (((drw_w<<10)/src_w) & 0x3ff); - } - - vscale=(src_h<<10)/(drw_h); - if(drw_h<src_h) - vscale=0x8000|((drw_h<<10)/(src_h)); - - /* Write scale factors to hardware */ - - CROUTW(0x80,hscale); /* Horizontal Scale */ - CROUTW(0x82,vscale); /* Vertical Scale */ - - /* Now set the start address and data layout */ - { - int lb = (y_pitch+2) >> 2; - CROUTB(0x95, ((lb & 0x100)>>1) | 0x08 ); /* Linebuffer level bit 8 & threshold */ - CROUTB(0x96, (lb & 0xFF)); /* Linebuffer level */ - - CROUTB(0x97, 0x00); /* VDE Flags */ - CROUTB(0xBA, 0x00); /* Chroma key */ - CROUTB(0xBB, 0x00); /* Chroma key */ - CROUTB(0xBC, 0xFF); /* Chroma key */ - CROUTB(0xBD, 0xFF); /* Chroma key */ - CROUTB(0xBE, 0x04); /* Capture control */ - - if(src_w > 384) - layout|=4; /* 2x line buffers */ - SROUTB(0x97, layout); - - CROUTW(0x90,y_pitch); /* Y Bytes per row */ - SROUTW(0x9A,uv_pitch); /* UV Bytes per row */ - - switch(info->fourcc) - { - case IMGFMT_BGR16: - CROUTB(0x8F, 0x24); /* VDE Flags - Edge Recovery & CSC Bypass */ - CROUTB(0xBF, 0x02); /* Video format - RGB16 */ - SROUTB(0xBE, 0x0); /* HSCB disabled */ - break; - default: - CROUTB(0x8F, 0x20); /* VDE Flags - Edge Recovery */ - CROUTB(0xBF, 0x00); /* Video format - YUV */ - SROUTB(0xBE, 0x00); /* HSCB disable - was 0x03*/ - break; - } - - CROUTB(0x92, ((base0+info->offset.y) >> 3) &0xff); /* Lower 8 bits of start address */ - CROUTB(0x93, ((base0+info->offset.y) >> 11) &0xff); /* Mid 8 bits of start address */ - CROUTB(0x94, ((base0+info->offset.y) >> 19) &0xf); /* Upper 4 bits of start address */ - SROUTB(0x80, ((base0+info->offset.v) >> 3) &0xff); /* Lower 8 bits of start address */ - SROUTB(0x81, ((base0+info->offset.v) >> 11) &0xff); /* Mid 8 bits of start address */ - SROUTB(0x82, ((base0+info->offset.v) >> 19) &0xf); /* Upper 4 bits of start address */ - SROUTB(0x83, ((base0+info->offset.u) >> 3) &0xff); /* Lower 8 bits of start address */ - SROUTB(0x84, ((base0+info->offset.u) >> 11) &0xff); /* Mid 8 bits of start address */ - SROUTB(0x85, ((base0+info->offset.u) >> 19) &0xf); /* Upper 4 bits of start address */ - } - - vixPlaybackSetEq(&equal); - - /* Protect hardware registers again */ - SROUTB(0x11, protect); - return 0; -} - - -int vixPlaybackOn(void) -{ - LOGWRITE("Enable overlay\n"); - CROUTB(0x8E, 0xd4); /* VDE Flags*/ - - return 0; -} - - -int vixPlaybackOff(void) -{ - LOGWRITE("Disable overlay\n"); - CROUTB(0x8E, 0xc4); /* VDE Flags*/ - - return 0; -} - - -int vixPlaybackFrameSelect(unsigned int frame) -{ - int protect; - LOGWRITE("Frame select\n"); - protect=SRINB(0x11); - SROUTB(0x11, 0x92); - /* Set overlay address to that of selected frame */ - CROUTB(0x92, ((frames[frame]+YOffs) >> 3) &0xff); /* Lower 8 bits of start address */ - CROUTB(0x93, ((frames[frame]+YOffs) >> 11) &0xff); /* Mid 8 bits of start address */ - CROUTB(0x94, ((frames[frame]+YOffs) >> 19) &0xf); /* Upper 4 bits of start address */ - SROUTB(0x80, ((frames[frame]+VOffs) >> 3) &0xff); /* Lower 8 bits of start address */ - SROUTB(0x81, ((frames[frame]+VOffs) >> 11) &0xff); /* Mid 8 bits of start address */ - SROUTB(0x82, ((frames[frame]+VOffs) >> 19) &0xf); /* Upper 4 bits of start address */ - SROUTB(0x83, ((frames[frame]+UOffs) >> 3) &0xff); /* Lower 8 bits of start address */ - SROUTB(0x84, ((frames[frame]+UOffs) >> 11) &0xff); /* Mid 8 bits of start address */ - SROUTB(0x85, ((frames[frame]+UOffs) >> 19) &0xf); /* Upper 4 bits of start address */ - SROUTB(0x11, protect); - return 0; -} - -
--- a/vidix/drivers/mach64.h Sat Mar 31 23:48:48 2007 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,2481 +0,0 @@ -/* - * mach64.h - * This software has been released under the terms of the GNU Public - * license. See http://www.gnu.org/copyleft/gpl.html for details. - * - * It's based on radeonfb, X11, GATOS sources -*/ - -#ifndef __MACH64_INCLUDED -#define __MACH64_INCLUDED 1 - -/* Note: this model of accessing to IO space is based on MMIO technology. -This means that this sources don't support ISA and VLB cards */ -#define BlockIOTag(val) (val) -#define IOPortTag(sparce,val) (val) - -/* MDA/[M]CGA/EGA/VGA I/O ports */ -#define GENVS 0x0102u /* Write (and Read on uC only) */ - -#define R_GENLPS 0x03b9u /* Read */ - -#define GENHP 0x03bfu - -#define ATTRX 0x03c0u -#define ATTRD 0x03c1u -#define GENS0 0x03c2u /* Read */ -#define GENMO 0x03c2u /* Write */ -#define GENENB 0x03c3u /* Read */ -#define SEQX 0x03c4u -#define SEQD 0x03c5u -#define VGA_DAC_MASK 0x03c6u -#define VGA_DAC_READ 0x03c7u -#define VGA_DAC_WRITE 0x03c8u -#define VGA_DAC_DATA 0x03c9u -#define R_GENFC 0x03cau /* Read */ -/* ? 0x03cbu */ -#define R_GENMO 0x03ccu /* Read */ -/* ? 0x03cdu */ -#define GRAX 0x03ceu -#define GRAD 0x03cfu - -#define GENB 0x03d9u - -#define GENLPS 0x03dcu /* Write */ -#define KCX 0x03ddu -#define KCD 0x03deu - -#define GENENA 0x46e8u /* Write */ - -/* I/O port base numbers */ -#define MonochromeIOBase 0x03b0u -#define ColourIOBase 0x03d0u - -/* Other MDA/[M]CGA/EGA/VGA I/O ports */ -/* ?(_IOBase) ((_IOBase) + 0x00u) */ /* CRTX synonym */ -/* ?(_IOBase) ((_IOBase) + 0x01u) */ /* CRTD synonym */ -/* ?(_IOBase) ((_IOBase) + 0x02u) */ /* CRTX synonym */ -/* ?(_IOBase) ((_IOBase) + 0x03u) */ /* CRTD synonym */ -#define CRTX(_IOBase) ((_IOBase) + 0x04u) -#define CRTD(_IOBase) ((_IOBase) + 0x05u) -/* ?(_IOBase) ((_IOBase) + 0x06u) */ -/* ?(_IOBase) ((_IOBase) + 0x07u) */ -#define GENMC(_IOBase) ((_IOBase) + 0x08u) -/* ?(_IOBase) ((_IOBase) + 0x09u) */ /* R_GENLPS/GENB */ -#define GENS1(_IOBase) ((_IOBase) + 0x0au) /* Read */ -#define GENFC(_IOBase) ((_IOBase) + 0x0au) /* Write */ -#define GENLPC(_IOBase) ((_IOBase) + 0x0bu) -/* ?(_IOBase) ((_IOBase) + 0x0cu) */ /* /GENLPS */ -/* ?(_IOBase) ((_IOBase) + 0x0du) */ /* /KCX */ -/* ?(_IOBase) ((_IOBase) + 0x0eu) */ /* /KCD */ -/* ?(_IOBase) ((_IOBase) + 0x0fu) */ /* GENHP/ */ - -/* 8514/A VESA approved register definitions */ -#define DISP_STAT 0x02e8u /* Read */ -#define SENSE 0x0001u /* Presumably belong here */ -#define VBLANK 0x0002u -#define HORTOG 0x0004u -#define H_TOTAL 0x02e8u /* Write */ -#define IBM_DAC_MASK 0x02eau -#define IBM_DAC_READ 0x02ebu -#define IBM_DAC_WRITE 0x02ecu -#define IBM_DAC_DATA 0x02edu -#define H_DISP 0x06e8u /* Write */ -#define H_SYNC_STRT 0x0ae8u /* Write */ -#define H_SYNC_WID 0x0ee8u /* Write */ -#define HSYNCPOL_POS 0x0000u -#define HSYNCPOL_NEG 0x0020u -#define H_POLARITY_POS HSYNCPOL_POS /* Sigh */ -#define H_POLARITY_NEG HSYNCPOL_NEG /* Sigh */ -#define V_TOTAL 0x12e8u /* Write */ -#define V_DISP 0x16e8u /* Write */ -#define V_SYNC_STRT 0x1ae8u /* Write */ -#define V_SYNC_WID 0x1ee8u /* Write */ -#define VSYNCPOL_POS 0x0000u -#define VSYNCPOL_NEG 0x0020u -#define V_POLARITY_POS VSYNCPOL_POS /* Sigh */ -#define V_POLARITY_NEG VSYNCPOL_NEG /* Sigh */ -#define DISP_CNTL 0x22e8u /* Write */ -#define ODDBNKENAB 0x0001u -#define MEMCFG_2 0x0000u -#define MEMCFG_4 0x0002u -#define MEMCFG_6 0x0004u -#define MEMCFG_8 0x0006u -#define DBLSCAN 0x0008u -#define INTERLACE 0x0010u -#define DISPEN_NC 0x0000u -#define DISPEN_ENAB 0x0020u -#define DISPEN_DISAB 0x0040u -#define R_H_TOTAL 0x26e8u /* Read */ -/* ? 0x2ae8u */ -/* ? 0x2ee8u */ -/* ? 0x32e8u */ -/* ? 0x36e8u */ -/* ? 0x3ae8u */ -/* ? 0x3ee8u */ -#define SUBSYS_STAT 0x42e8u /* Read */ -#define VBLNKFLG 0x0001u -#define PICKFLAG 0x0002u -#define INVALIDIO 0x0004u -#define GPIDLE 0x0008u -#define MONITORID_MASK 0x0070u -/* MONITORID_? 0x0000u */ -#define MONITORID_8507 0x0010u -#define MONITORID_8514 0x0020u -/* MONITORID_? 0x0030u */ -/* MONITORID_? 0x0040u */ -#define MONITORID_8503 0x0050u -#define MONITORID_8512 0x0060u -#define MONITORID_8513 0x0060u -#define MONITORID_NONE 0x0070u -#define _8PLANE 0x0080u -#define SUBSYS_CNTL 0x42e8u /* Write */ -#define RVBLNKFLG 0x0001u -#define RPICKFLAG 0x0002u -#define RINVALIDIO 0x0004u -#define RGPIDLE 0x0008u -#define IVBLNKFLG 0x0100u -#define IPICKFLAG 0x0200u -#define IINVALIDIO 0x0400u -#define IGPIDLE 0x0800u -#define CHPTEST_NC 0x0000u -#define CHPTEST_NORMAL 0x1000u -#define CHPTEST_ENAB 0x2000u -#define GPCTRL_NC 0x0000u -#define GPCTRL_ENAB 0x4000u -#define GPCTRL_RESET 0x8000u -#define ROM_PAGE_SEL 0x46e8u /* Write */ -#define ADVFUNC_CNTL 0x4ae8u /* Write */ -#define DISABPASSTHRU 0x0001u -#define CLOKSEL 0x0004u -/* ? 0x4ee8u */ -#define EXT_CONFIG_0 0x52e8u /* C & T 82C480 */ -#define EXT_CONFIG_1 0x56e8u /* C & T 82C480 */ -#define EXT_CONFIG_2 0x5ae8u /* C & T 82C480 */ -#define EXT_CONFIG_3 0x5ee8u /* C & T 82C480 */ -/* ? 0x62e8u */ -/* ? 0x66e8u */ -/* ? 0x6ae8u */ -/* ? 0x6ee8u */ -/* ? 0x72e8u */ -/* ? 0x76e8u */ -/* ? 0x7ae8u */ -/* ? 0x7ee8u */ -#define CUR_Y 0x82e8u -#define CUR_X 0x86e8u -#define DESTY_AXSTP 0x8ae8u /* Write */ -#define DESTX_DIASTP 0x8ee8u /* Write */ -#define ERR_TERM 0x92e8u -#define MAJ_AXIS_PCNT 0x96e8u /* Write */ -#define GP_STAT 0x9ae8u /* Read */ -#define GE_STAT 0x9ae8u /* Alias */ -#define DATARDY 0x0100u -#define DATA_READY DATARDY /* Alias */ -#define GPBUSY 0x0200u -#define CMD 0x9ae8u /* Write */ -#define WRTDATA 0x0001u -#define PLANAR 0x0002u -#define LASTPIX 0x0004u -#define LINETYPE 0x0008u -#define DRAW 0x0010u -#define INC_X 0x0020u -#define YMAJAXIS 0x0040u -#define INC_Y 0x0080u -#define PCDATA 0x0100u -#define _16BIT 0x0200u -#define CMD_NOP 0x0000u -#define CMD_OP_MSK 0xf000u -#define BYTSEQ 0x1000u -#define CMD_LINE 0x2000u -#define CMD_RECT 0x4000u -#define CMD_RECTV1 0x6000u -#define CMD_RECTV2 0x8000u -#define CMD_LINEAF 0xa000u -#define CMD_BITBLT 0xc000u -#define SHORT_STROKE 0x9ee8u /* Write */ -#define SSVDRAW 0x0010u -#define VECDIR_000 0x0000u -#define VECDIR_045 0x0020u -#define VECDIR_090 0x0040u -#define VECDIR_135 0x0060u -#define VECDIR_180 0x0080u -#define VECDIR_225 0x00a0u -#define VECDIR_270 0x00c0u -#define VECDIR_315 0x00e0u -#define BKGD_COLOR 0xa2e8u /* Write */ -#define FRGD_COLOR 0xa6e8u /* Write */ -#define WRT_MASK 0xaae8u /* Write */ -#define RD_MASK 0xaee8u /* Write */ -#define COLOR_CMP 0xb2e8u /* Write */ -#define BKGD_MIX 0xb6e8u /* Write */ -/* 0x001fu See MIX_* definitions below */ -#define BSS_BKGDCOL 0x0000u -#define BSS_FRGDCOL 0x0020u -#define BSS_PCDATA 0x0040u -#define BSS_BITBLT 0x0060u -#define FRGD_MIX 0xbae8u /* Write */ -/* 0x001fu See MIX_* definitions below */ -#define FSS_BKGDCOL 0x0000u -#define FSS_FRGDCOL 0x0020u -#define FSS_PCDATA 0x0040u -#define FSS_BITBLT 0x0060u -#define MULTIFUNC_CNTL 0xbee8u /* Write */ -#define MIN_AXIS_PCNT 0x0000u -#define SCISSORS_T 0x1000u -#define SCISSORS_L 0x2000u -#define SCISSORS_B 0x3000u -#define SCISSORS_R 0x4000u -#define M32_MEM_CNTL 0x5000u -#define HORCFG_4 0x0000u -#define HORCFG_5 0x0001u -#define HORCFG_8 0x0002u -#define HORCFG_10 0x0003u -#define VRTCFG_2 0x0000u -#define VRTCFG_4 0x0004u -#define VRTCFG_6 0x0008u -#define VRTCFG_8 0x000cu -#define BUFSWP 0x0010u -#define PATTERN_L 0x8000u -#define PATTERN_H 0x9000u -#define PIX_CNTL 0xa000u -#define PLANEMODE 0x0004u -#define COLCMPOP_F 0x0000u -#define COLCMPOP_T 0x0008u -#define COLCMPOP_GE 0x0010u -#define COLCMPOP_LT 0x0018u -#define COLCMPOP_NE 0x0020u -#define COLCMPOP_EQ 0x0028u -#define COLCMPOP_LE 0x0030u -#define COLCMPOP_GT 0x0038u -#define MIXSEL_FRGDMIX 0x0000u -#define MIXSEL_PATT 0x0040u -#define MIXSEL_EXPPC 0x0080u -#define MIXSEL_EXPBLT 0x00c0u -/* ? 0xc2e8u */ -/* ? 0xc6e8u */ -/* ? 0xcae8u */ -/* ? 0xcee8u */ -/* ? 0xd2e8u */ -/* ? 0xd6e8u */ -/* ? 0xdae8u */ -/* ? 0xdee8u */ -#define PIX_TRANS 0xe2e8u -/* ? 0xe6e8u */ -/* ? 0xeae8u */ -/* ? 0xeee8u */ -/* ? 0xf2e8u */ -/* ? 0xf6e8u */ -/* ? 0xfae8u */ -/* ? 0xfee8u */ - -/* ATI Mach8 & Mach32 register definitions */ -#define OVERSCAN_COLOR_8 0x02eeu /* Write */ /* Mach32 */ -#define OVERSCAN_BLUE_24 0x02efu /* Write */ /* Mach32 */ -#define OVERSCAN_GREEN_24 0x06eeu /* Write */ /* Mach32 */ -#define OVERSCAN_RED_24 0x06efu /* Write */ /* Mach32 */ -#define CURSOR_OFFSET_LO 0x0aeeu /* Write */ /* Mach32 */ -#define CURSOR_OFFSET_HI 0x0eeeu /* Write */ /* Mach32 */ -#define CONFIG_STATUS_1 0x12eeu /* Read */ -#define CLK_MODE 0x0001u /* Mach8 */ -#define BUS_16 0x0002u /* Mach8 */ -#define MC_BUS 0x0004u /* Mach8 */ -#define EEPROM_ENA 0x0008u /* Mach8 */ -#define DRAM_ENA 0x0010u /* Mach8 */ -#define MEM_INSTALLED 0x0060u /* Mach8 */ -#define ROM_ENA 0x0080u /* Mach8 */ -#define ROM_PAGE_ENA 0x0100u /* Mach8 */ -#define ROM_LOCATION 0xfe00u /* Mach8 */ -#define _8514_ONLY 0x0001u /* Mach32 */ -#define BUS_TYPE 0x000eu /* Mach32 */ -#define ISA_16_BIT 0x0000u /* Mach32 */ -#define EISA 0x0002u /* Mach32 */ -#define MICRO_C_16_BIT 0x0004u /* Mach32 */ -#define MICRO_C_8_BIT 0x0006u /* Mach32 */ -#define LOCAL_386SX 0x0008u /* Mach32 */ -#define LOCAL_386DX 0x000au /* Mach32 */ -#define LOCAL_486 0x000cu /* Mach32 */ -#define PCI 0x000eu /* Mach32 */ -#define MEM_TYPE 0x0070u /* Mach32 */ -#define CHIP_DIS 0x0080u /* Mach32 */ -#define TST_VCTR_ENA 0x0100u /* Mach32 */ -#define DACTYPE 0x0e00u /* Mach32 */ -#define MC_ADR_DECODE 0x1000u /* Mach32 */ -#define CARD_ID 0xe000u /* Mach32 */ -#define HORZ_CURSOR_POSN 0x12eeu /* Write */ /* Mach32 */ -#define CONFIG_STATUS_2 0x16eeu /* Read */ -#define SHARE_CLOCK 0x0001u /* Mach8 */ -#define HIRES_BOOT 0x0002u /* Mach8 */ -#define EPROM_16_ENA 0x0004u /* Mach8 */ -#define WRITE_PER_BIT 0x0008u /* Mach8 */ -#define FLASH_ENA 0x0010u /* Mach8 */ -#define SLOW_SEQ_EN 0x0001u /* Mach32 */ -#define MEM_ADDR_DIS 0x0002u /* Mach32 */ -#define ISA_16_ENA 0x0004u /* Mach32 */ -#define KOR_TXT_MODE_ENA 0x0008u /* Mach32 */ -#define LOCAL_BUS_SUPPORT 0x0030u /* Mach32 */ -#define LOCAL_BUS_CONFIG_2 0x0040u /* Mach32 */ -#define LOCAL_BUS_RD_DLY_ENA 0x0080u /* Mach32 */ -#define LOCAL_DAC_EN 0x0100u /* Mach32 */ -#define LOCAL_RDY_EN 0x0200u /* Mach32 */ -#define EEPROM_ADR_SEL 0x0400u /* Mach32 */ -#define GE_STRAP_SEL 0x0800u /* Mach32 */ -#define VESA_RDY 0x1000u /* Mach32 */ -#define Z4GB 0x2000u /* Mach32 */ -#define LOC2_MDRAM 0x4000u /* Mach32 */ -#define VERT_CURSOR_POSN 0x16eeu /* Write */ /* Mach32 */ -#define FIFO_TEST_DATA 0x1aeeu /* Read */ /* Mach32 */ -#define CURSOR_COLOR_0 0x1aeeu /* Write */ /* Mach32 */ -#define CURSOR_COLOR_1 0x1aefu /* Write */ /* Mach32 */ -#define HORZ_CURSOR_OFFSET 0x1eeeu /* Write */ /* Mach32 */ -#define VERT_CURSOR_OFFSET 0x1eefu /* Write */ /* Mach32 */ -#define PCI_CNTL 0x22eeu /* Mach32-PCI */ -#define CRT_PITCH 0x26eeu /* Write */ -#define CRT_OFFSET_LO 0x2aeeu /* Write */ -#define CRT_OFFSET_HI 0x2eeeu /* Write */ -#define LOCAL_CNTL 0x32eeu /* Mach32 */ -#define FIFO_OPT 0x36eeu /* Write */ /* Mach8 */ -#define MISC_OPTIONS 0x36eeu /* Mach32 */ -#define W_STATE_ENA 0x0000u /* Mach32 */ -#define HOST_8_ENA 0x0001u /* Mach32 */ -#define MEM_SIZE_ALIAS 0x000cu /* Mach32 */ -#define MEM_SIZE_512K 0x0000u /* Mach32 */ -#define MEM_SIZE_1M 0x0004u /* Mach32 */ -#define MEM_SIZE_2M 0x0008u /* Mach32 */ -#define MEM_SIZE_4M 0x000cu /* Mach32 */ -#define DISABLE_VGA 0x0010u /* Mach32 */ -#define _16_BIT_IO 0x0020u /* Mach32 */ -#define DISABLE_DAC 0x0040u /* Mach32 */ -#define DLY_LATCH_ENA 0x0080u /* Mach32 */ -#define TEST_MODE 0x0100u /* Mach32 */ -#define BLK_WR_ENA 0x0400u /* Mach32 */ -#define _64_DRAW_ENA 0x0800u /* Mach32 */ -#define FIFO_TEST_TAG 0x3aeeu /* Read */ /* Mach32 */ -#define EXT_CURSOR_COLOR_0 0x3aeeu /* Write */ /* Mach32 */ -#define EXT_CURSOR_COLOR_1 0x3eeeu /* Write */ /* Mach32 */ -#define MEM_BNDRY 0x42eeu /* Mach32 */ -#define MEM_PAGE_BNDRY 0x000fu /* Mach32 */ -#define MEM_BNDRY_ENA 0x0010u /* Mach32 */ -#define SHADOW_CTL 0x46eeu /* Write */ -#define CLOCK_SEL 0x4aeeu -/* DISABPASSTHRU 0x0001u See ADVFUNC_CNTL */ -#define VFIFO_DEPTH_1 0x0100u /* Mach32 */ -#define VFIFO_DEPTH_2 0x0200u /* Mach32 */ -#define VFIFO_DEPTH_3 0x0300u /* Mach32 */ -#define VFIFO_DEPTH_4 0x0400u /* Mach32 */ -#define VFIFO_DEPTH_5 0x0500u /* Mach32 */ -#define VFIFO_DEPTH_6 0x0600u /* Mach32 */ -#define VFIFO_DEPTH_7 0x0700u /* Mach32 */ -#define VFIFO_DEPTH_8 0x0800u /* Mach32 */ -#define VFIFO_DEPTH_9 0x0900u /* Mach32 */ -#define VFIFO_DEPTH_A 0x0a00u /* Mach32 */ -#define VFIFO_DEPTH_B 0x0b00u /* Mach32 */ -#define VFIFO_DEPTH_C 0x0c00u /* Mach32 */ -#define VFIFO_DEPTH_D 0x0d00u /* Mach32 */ -#define VFIFO_DEPTH_E 0x0e00u /* Mach32 */ -#define VFIFO_DEPTH_F 0x0f00u /* Mach32 */ -#define COMPOSITE_SYNC 0x1000u -/* ? 0x4eeeu */ -#define ROM_ADDR_1 0x52eeu -#define BIOS_BASE_SEGMENT 0x007fu /* Mach32 */ -/* ? 0xff80u */ /* Mach32 */ -#define ROM_ADDR_2 0x56eeu /* Sick ... */ -#define SHADOW_SET 0x5aeeu /* Write */ -#define MEM_CFG 0x5eeeu /* Mach32 */ -#define MEM_APERT_SEL 0x0003u /* Mach32 */ -#define MEM_APERT_PAGE 0x000cu /* Mach32 */ -#define MEM_APERT_LOC 0xfff0u /* Mach32 */ -#define EXT_GE_STATUS 0x62eeu /* Read */ /* Mach32 */ -#define HORZ_OVERSCAN 0x62eeu /* Write */ /* Mach32 */ -#define VERT_OVERSCAN 0x66eeu /* Write */ /* Mach32 */ -#define MAX_WAITSTATES 0x6aeeu -#define GE_OFFSET_LO 0x6eeeu /* Write */ -#define BOUNDS_LEFT 0x72eeu /* Read */ -#define GE_OFFSET_HI 0x72eeu /* Write */ -#define BOUNDS_TOP 0x76eeu /* Read */ -#define GE_PITCH 0x76eeu /* Write */ -#define BOUNDS_RIGHT 0x7aeeu /* Read */ -#define EXT_GE_CONFIG 0x7aeeu /* Write */ /* Mach32 */ -#define MONITOR_ALIAS 0x0007u /* Mach32 */ -/* MONITOR_? 0x0000u */ /* Mach32 */ -#define MONITOR_8507 0x0001u /* Mach32 */ -#define MONITOR_8514 0x0002u /* Mach32 */ -/* MONITOR_? 0x0003u */ /* Mach32 */ -/* MONITOR_? 0x0004u */ /* Mach32 */ -#define MONITOR_8503 0x0005u /* Mach32 */ -#define MONITOR_8512 0x0006u /* Mach32 */ -#define MONITOR_8513 0x0006u /* Mach32 */ -#define MONITOR_NONE 0x0007u /* Mach32 */ -#define ALIAS_ENA 0x0008u /* Mach32 */ -#define PIXEL_WIDTH_4 0x0000u /* Mach32 */ -#define PIXEL_WIDTH_8 0x0010u /* Mach32 */ -#define PIXEL_WIDTH_16 0x0020u /* Mach32 */ -#define PIXEL_WIDTH_24 0x0030u /* Mach32 */ -#define RGB16_555 0x0000u /* Mach32 */ -#define RGB16_565 0x0040u /* Mach32 */ -#define RGB16_655 0x0080u /* Mach32 */ -#define RGB16_664 0x00c0u /* Mach32 */ -#define MULTIPLEX_PIXELS 0x0100u /* Mach32 */ -#define RGB24 0x0000u /* Mach32 */ -#define RGBx24 0x0200u /* Mach32 */ -#define BGR24 0x0400u /* Mach32 */ -#define xBGR24 0x0600u /* Mach32 */ -#define DAC_8_BIT_EN 0x4000u /* Mach32 */ -#define ORDER_16BPP_565 RGB16_565 /* Mach32 */ -#define BOUNDS_BOTTOM 0x7eeeu /* Read */ -#define MISC_CNTL 0x7eeeu /* Write */ /* Mach32 */ -#define PATT_DATA_INDEX 0x82eeu -/* ? 0x86eeu */ -/* ? 0x8aeeu */ -#define R_EXT_GE_CONFIG 0x8eeeu /* Read */ /* Mach32 */ -#define PATT_DATA 0x8eeeu /* Write */ -#define R_MISC_CNTL 0x92eeu /* Read */ /* Mach32 */ -#define BRES_COUNT 0x96eeu -#define EXT_FIFO_STATUS 0x9aeeu /* Read */ -#define LINEDRAW_INDEX 0x9aeeu /* Write */ -/* ? 0x9eeeu */ -#define LINEDRAW_OPT 0xa2eeu -#define BOUNDS_RESET 0x0100u -#define CLIP_MODE_0 0x0000u /* Clip exception disabled */ -#define CLIP_MODE_1 0x0200u /* Line segments */ -#define CLIP_MODE_2 0x0400u /* Polygon boundary lines */ -#define CLIP_MODE_3 0x0600u /* Patterned lines */ -#define DEST_X_START 0xa6eeu /* Write */ -#define DEST_X_END 0xaaeeu /* Write */ -#define DEST_Y_END 0xaeeeu /* Write */ -#define R_H_TOTAL_DISP 0xb2eeu /* Read */ /* Mach32 */ -#define SRC_X_STRT 0xb2eeu /* Write */ -#define R_H_SYNC_STRT 0xb6eeu /* Read */ /* Mach32 */ -#define ALU_BG_FN 0xb6eeu /* Write */ -#define R_H_SYNC_WID 0xbaeeu /* Read */ /* Mach32 */ -#define ALU_FG_FN 0xbaeeu /* Write */ -#define SRC_X_END 0xbeeeu /* Write */ -#define R_V_TOTAL 0xc2eeu /* Read */ -#define SRC_Y_DIR 0xc2eeu /* Write */ -#define R_V_DISP 0xc6eeu /* Read */ /* Mach32 */ -#define EXT_SHORT_STROKE 0xc6eeu /* Write */ -#define R_V_SYNC_STRT 0xcaeeu /* Read */ /* Mach32 */ -#define SCAN_X 0xcaeeu /* Write */ -#define VERT_LINE_CNTR 0xceeeu /* Read */ /* Mach32 */ -#define DP_CONFIG 0xceeeu /* Write */ -#define READ_WRITE 0x0001u -#define DATA_WIDTH 0x0200u -#define DATA_ORDER 0x1000u -#define FG_COLOR_SRC_FG 0x2000u -#define FG_COLOR_SRC_BLIT 0x6000u -#define R_V_SYNC_WID 0xd2eeu /* Read */ -#define PATT_LENGTH 0xd2eeu /* Write */ -#define PATT_INDEX 0xd6eeu /* Write */ -#define READ_SRC_X 0xdaeeu /* Read */ /* Mach32 */ -#define EXT_SCISSOR_L 0xdaeeu /* Write */ -#define READ_SRC_Y 0xdeeeu /* Read */ /* Mach32 */ -#define EXT_SCISSOR_T 0xdeeeu /* Write */ -#define EXT_SCISSOR_R 0xe2eeu /* Write */ -#define EXT_SCISSOR_B 0xe6eeu /* Write */ -/* ? 0xeaeeu */ -#define DEST_COMP_FN 0xeeeeu /* Write */ -#define DEST_COLOR_CMP_MASK 0xf2eeu /* Write */ /* Mach32 */ -/* ? 0xf6eeu */ -#define CHIP_ID 0xfaeeu /* Read */ /* Mach32 */ -#define CHIP_CODE_0 0x001fu /* Mach32 */ -#define CHIP_CODE_1 0x03e0u /* Mach32 */ -#define CHIP_CLASS 0x0c00u /* Mach32 */ -#define CHIP_REV 0xf000u /* Mach32 */ -#define LINEDRAW 0xfeeeu /* Write */ - -/* ATI Mach64 register definitions */ -#define CRTC_H_TOTAL_DISP IOPortTag(0x00u, 0x00u) -#define CRTC_H_TOTAL 0x000001fful -/* ? 0x0000fe00ul */ -#define CRTC_H_DISP 0x01ff0000ul -/* ? 0xfe000000ul */ -#define CRTC_H_SYNC_STRT_WID IOPortTag(0x01u, 0x01u) -#define CRTC_H_SYNC_STRT 0x000000fful -#define CRTC_H_SYNC_DLY 0x00000700ul -/* ? 0x00000800ul */ -#define CRTC_H_SYNC_STRT_HI 0x00001000ul -/* ? 0x0000e000ul */ -#define CRTC_H_SYNC_WID 0x001f0000ul -#define CRTC_H_SYNC_POL 0x00200000ul -/* ? 0xffc00000ul */ -#define CRTC_V_TOTAL_DISP IOPortTag(0x02u, 0x02u) -#define CRTC_V_TOTAL 0x000007fful -/* ? 0x0000f800ul */ -#define CRTC_V_DISP 0x07ff0000ul -/* ? 0xf8000000ul */ -#define CRTC_V_SYNC_STRT_WID IOPortTag(0x03u, 0x03u) -#define CRTC_V_SYNC_STRT 0x000007fful -/* ? 0x0000f800ul */ -#define CRTC_V_SYNC_WID 0x001f0000ul -#define CRTC_V_SYNC_POL 0x00200000ul -/* ? 0xffc00000ul */ -#define CRTC_VLINE_CRNT_VLINE IOPortTag(0x04u, 0x04u) -#define CRTC_VLINE 0x000007fful -/* ? 0x0000f800ul */ -#define CRTC_CRNT_VLINE 0x07ff0000ul -/* ? 0xf8000000ul */ -#define CRTC_OFF_PITCH IOPortTag(0x05u, 0x05u) -#define CRTC_OFFSET 0x000ffffful -#define CRTC_OFFSET_VGA 0x0003fffful -#define CRTC_OFFSET_LOCK 0x00100000ul /* XC/XL */ -/* ? 0x00200000ul */ -#define CRTC_PITCH 0xffc00000ul -#define CRTC_INT_CNTL IOPortTag(0x06u, 0x06u) -#define CRTC_VBLANK 0x00000001ul -#define CRTC_VBLANK_INT_EN 0x00000002ul -#define CRTC_VBLANK_INT 0x00000004ul -#define CRTC_VLINE_INT_EN 0x00000008ul -#define CRTC_VLINE_INT 0x00000010ul -#define CRTC_VLINE_SYNC 0x00000020ul -#define CRTC_FRAME 0x00000040ul -#define CRTC_SNAPSHOT_INT_EN 0x00000080ul /* GTPro */ -#define CRTC_SNAPSHOT_INT 0x00000100ul /* GTPro */ -#define CRTC_I2C_INT_EN 0x00000200ul /* GTPro */ -#define CRTC_I2C_INT 0x00000400ul /* GTPro */ -#define CRTC2_VBLANK 0x00000800ul /* LTPro */ -#define CRTC2_VBLANK_INT_EN 0x00001000ul /* LTPro */ -#define CRTC2_VBLANK_INT 0x00002000ul /* LTPro */ -#define CRTC2_VLINE_INT_EN 0x00004000ul /* LTPro */ -#define CRTC2_VLINE_INT 0x00008000ul /* LTPro */ -#define CRTC_CAPBUF0_INT_EN 0x00010000ul /* VT/GT */ -#define CRTC_CAPBUF0_INT 0x00020000ul /* VT/GT */ -#define CRTC_CAPBUF1_INT_EN 0x00040000ul /* VT/GT */ -#define CRTC_CAPBUF1_INT 0x00080000ul /* VT/GT */ -#define CRTC_OVERLAY_EOF_INT_EN 0x00100000ul /* VT/GT */ -#define CRTC_OVERLAY_EOF_INT 0x00200000ul /* VT/GT */ -#define CRTC_ONESHOT_CAP_INT_EN 0x00400000ul /* VT/GT */ -#define CRTC_ONESHOT_CAP_INT 0x00800000ul /* VT/GT */ -#define CRTC_BUSMASTER_EOL_INT_EN 0x01000000ul /* VTB/GTB/LT */ -#define CRTC_BUSMASTER_EOL_INT 0x02000000ul /* VTB/GTB/LT */ -#define CRTC_GP_INT_EN 0x04000000ul /* VTB/GTB/LT */ -#define CRTC_GP_INT 0x08000000ul /* VTB/GTB/LT */ -#define CRTC2_VLINE_SYNC 0x10000000ul /* LTPro */ -#define CRTC_SNAPSHOT2_INT_EN 0x20000000ul /* LTPro */ -#define CRTC_SNAPSHOT2_INT 0x40000000ul /* LTPro */ -#define CRTC_VBLANK_BIT2_INT 0x80000000ul /* GTPro */ -#define CRTC_INT_ENS /* *** UPDATE ME *** */ \ - ( \ - CRTC_VBLANK_INT_EN | \ - CRTC_VLINE_INT_EN | \ - CRTC_SNAPSHOT_INT_EN | \ - CRTC_I2C_INT_EN | \ - CRTC2_VBLANK_INT_EN | \ - CRTC2_VLINE_INT_EN | \ - CRTC_CAPBUF0_INT_EN | \ - CRTC_CAPBUF1_INT_EN | \ - CRTC_OVERLAY_EOF_INT_EN | \ - CRTC_ONESHOT_CAP_INT_EN | \ - CRTC_BUSMASTER_EOL_INT_EN | \ - CRTC_GP_INT_EN | \ - CRTC_SNAPSHOT2_INT_EN | \ - 0 \ - ) -#define CRTC_INT_ACKS /* *** UPDATE ME *** */ \ - ( \ - CRTC_VBLANK_INT | \ - CRTC_VLINE_INT | \ - CRTC_SNAPSHOT_INT | \ - CRTC_I2C_INT | \ - CRTC2_VBLANK_INT | \ - CRTC2_VLINE_INT | \ - CRTC_CAPBUF0_INT | \ - CRTC_CAPBUF1_INT | \ - CRTC_OVERLAY_EOF_INT | \ - CRTC_ONESHOT_CAP_INT | \ - CRTC_BUSMASTER_EOL_INT | \ - CRTC_GP_INT | \ - CRTC_SNAPSHOT2_INT | \ - CRTC_VBLANK_BIT2_INT | \ - 0 \ - ) -#define CRTC_GEN_CNTL IOPortTag(0x07u, 0x07u) -#define CRTC_DBL_SCAN_EN 0x00000001ul -#define CRTC_INTERLACE_EN 0x00000002ul -#define CRTC_HSYNC_DIS 0x00000004ul -#define CRTC_VSYNC_DIS 0x00000008ul -#define CRTC_CSYNC_EN 0x00000010ul -#define CRTC_PIX_BY_2_EN 0x00000020ul -#define CRTC2_DBL_SCAN_EN 0x00000020ul /* LTPro */ -#define CRTC_DISPLAY_DIS 0x00000040ul -#define CRTC_VGA_XOVERSCAN 0x00000080ul -#define CRTC_PIX_WIDTH 0x00000700ul -#define CRTC_BYTE_PIX_ORDER 0x00000800ul -#define CRTC_VSYNC_INT_EN 0x00001000ul /* XC/XL */ -#define CRTC_VSYNC_INT 0x00002000ul /* XC/XL */ -#define CRTC_FIFO_OVERFILL 0x0000c000ul /* VT/GT */ -#define CRTC2_VSYNC_INT_EN 0x00004000ul /* XC/XL */ -#define CRTC2_VSYNC_INT 0x00008000ul /* XC/XL */ -#define CRTC_FIFO_LWM 0x000f0000ul -#define CRTC_HVSYNC_IO_DRIVE 0x00010000ul /* XC/XL */ -#define CRTC2_PIX_WIDTH 0x000e0000ul /* LTPro */ -#define CRTC_VGA_128KAP_PAGING 0x00100000ul /* VT/GT */ -#define CRTC_DISPREQ_ONLY 0x00200000ul /* VT/GT */ -#define CRTC_VFC_SYNC_TRISTATE 0x00200000ul /* VTB/GTB/LT */ -#define CRTC2_EN 0x00200000ul /* LTPro */ -#define CRTC_LOCK_REGS 0x00400000ul /* VT/GT */ -#define CRTC_SYNC_TRISTATE 0x00800000ul /* VT/GT */ -#define CRTC_EXT_DISP_EN 0x01000000ul -#define CRTC_EN 0x02000000ul -#define CRTC_DISP_REQ_EN 0x04000000ul -#define CRTC_VGA_LINEAR 0x08000000ul -#define CRTC_VSYNC_FALL_EDGE 0x10000000ul -#define CRTC_VGA_TEXT_132 0x20000000ul -#define CRTC_CNT_EN 0x40000000ul -#define CRTC_CUR_B_TEST 0x80000000ul -#define CRTC_INT_ENS_X /* *** UPDATE ME *** */ \ - ( \ - CRTC_VSYNC_INT_EN | \ - CRTC2_VSYNC_INT_EN | \ - 0 \ - ) -#define CRTC_INT_ACKS_X /* *** UPDATE ME *** */ \ - ( \ - CRTC_VSYNC_INT | \ - CRTC2_VSYNC_INT | \ - 0 \ - ) -#define DSP_CONFIG BlockIOTag(0x08u) /* VTB/GTB/LT */ -#define DSP_XCLKS_PER_QW 0x00003ffful -/* ? 0x00004000ul */ -#define DSP_FLUSH_WB 0x00008000ul -#define DSP_LOOP_LATENCY 0x000f0000ul -#define DSP_PRECISION 0x00700000ul -/* ? 0xff800000ul */ -#define DSP_ON_OFF BlockIOTag(0x09u) /* VTB/GTB/LT */ -#define DSP_OFF 0x000007fful -/* ? 0x0000f800ul */ -#define DSP_ON 0x07ff0000ul -/* ? 0xf8000000ul */ -#define TIMER_CONFIG BlockIOTag(0x0au) /* VTB/GTB/LT */ -#define MEM_BUF_CNTL BlockIOTag(0x0bu) /* VTB/GTB/LT */ -#define SHARED_CNTL BlockIOTag(0x0cu) /* VTB/GTB/LT */ -#define SHARED_MEM_CONFIG BlockIOTag(0x0du) /* VTB/GTB/LT */ -#define MEM_ADDR_CONFIG BlockIOTag(0x0du) /* GTPro */ -#define SHARED_CNTL_CTD BlockIOTag(0x0eu) /* CTD */ -/* ? 0x00fffffful */ -#define CTD_FIFO5 0x01000000ul -/* ? 0xfe000000ul */ -#define CRT_TRAP BlockIOTag(0x0eu) /* VTB/GTB/LT */ -#define DSTN_CONTROL BlockIOTag(0x0fu) /* LT */ -#define I2C_CNTL_0 BlockIOTag(0x0fu) /* GTPro */ -#define OVR_CLR IOPortTag(0x08u, 0x10u) -#define OVR_CLR_8 0x000000fful -#define OVR_CLR_B 0x0000ff00ul -#define OVR_CLR_G 0x00ff0000ul -#define OVR_CLR_R 0xff000000ul -#define OVR_WID_LEFT_RIGHT IOPortTag(0x09u, 0x11u) -#define OVR_WID_LEFT 0x0000003ful /* 0x0f on <LT */ -/* ? 0x0000ffc0ul */ -#define OVR_WID_RIGHT 0x003f0000ul /* 0x0f0000 on <LT */ -/* ? 0xffc00000ul */ -#define OVR_WID_TOP_BOTTOM IOPortTag(0x0au, 0x12u) -#define OVR_WID_TOP 0x000001fful /* 0x00ff on <LT */ -/* ? 0x0000fe00ul */ -#define OVR_WID_BOTTOM 0x01ff0000ul /* 0x00ff0000 on <LT */ -/* ? 0xfe000000ul */ -#define VGA_DSP_CONFIG BlockIOTag(0x13u) /* VTB/GTB/LT */ -#define VGA_DSP_XCLKS_PER_QW DSP_XCLKS_PER_QW -/* ? 0x000fc000ul */ -#define VGA_DSP_PREC_PCLKBY2 0x00700000ul -/* ? 0x00800000ul */ -#define VGA_DSP_PREC_PCLK 0x07000000ul -/* ? 0xf8000000ul */ -#define VGA_DSP_ON_OFF BlockIOTag(0x14u) /* VTB/GTB/LT */ -#define VGA_DSP_OFF DSP_OFF -/* ? 0x0000f800ul */ -#define VGA_DSP_ON DSP_ON -/* ? 0xf8000000ul */ -#define DSP2_CONFIG BlockIOTag(0x15u) /* LTPro */ -#define DSP2_ON_OFF BlockIOTag(0x16u) /* LTPro */ -#define EXT_CRTC_GEN_CNTL BlockIOTag(0x17u) /* VT-A4 (W) */ -#define CRTC2_OFF_PITCH BlockIOTag(0x17u) /* LTPro */ -#define CUR_CLR0 IOPortTag(0x0bu, 0x18u) -#define CUR_CLR1 IOPortTag(0x0cu, 0x19u) -/* These are for both CUR_CLR0 and CUR_CLR1 */ -#define CUR_CLR_I 0x000000fful -#define CUR_CLR_B 0x0000ff00ul -#define CUR_CLR_G 0x00ff0000ul -#define CUR_CLR_R 0xff000000ul -#define CUR_CLR (CUR_CLR_R | CUR_CLR_G | CUR_CLR_B) -#define CUR_OFFSET IOPortTag(0x0du, 0x1au) -#define CUR_HORZ_VERT_POSN IOPortTag(0x0eu, 0x1bu) -#define CUR_HORZ_POSN 0x000007fful -/* ? 0x0000f800ul */ -#define CUR_VERT_POSN 0x07ff0000ul -/* ? 0xf8000000ul */ -#define CUR_HORZ_VERT_OFF IOPortTag(0x0fu, 0x1cu) -#define CUR_HORZ_OFF 0x0000007ful -/* ? 0x0000ff80ul */ -#define CUR_VERT_OFF 0x007f0000ul -/* ? 0xff800000ul */ -#define CONFIG_PANEL BlockIOTag(0x1du) /* LT */ -#define PANEL_FORMAT 0x00000007ul -/* ? 0x00000008ul */ -#define PANEL_TYPE 0x000000f0ul -#define NO_OF_GREY 0x00000700ul -#define MOD_GEN 0x00001800ul -#define EXT_LVDS_CLK 0x00001800ul /* LTPro */ -#define BLINK_RATE 0x00006000ul -#define BLINK_RATE_PRO 0x00002000ul /* LTPro */ -#define DONT_SHADOW_HEND 0x00004000ul /* LTPro */ -#define DONT_USE_F32KHZ 0x00008000ul -#define LCD_IO_DRIVE 0x00008000ul /* XC/XL */ -#define FP_POL 0x00010000ul -#define LP_POL 0x00020000ul -#define DTMG_POL 0x00040000ul -#define SCK_POL 0x00080000ul -#define DITHER_SEL 0x00300000ul -#define INVERSE_VIDEO_EN 0x00400000ul -#define BL_CLK_SEL 0x01800000ul -#define BL_LEVEL 0x0e000000ul -#define BL_CLK_SEL_PRO 0x00800000ul /* LTPro */ -#define BL_LEVEL_PRO 0x03000000ul /* LTPro */ -#define BIAS_LEVEL_PRO 0x0c000000ul /* LTPro */ -#define HSYNC_DELAY 0xf0000000ul -#define TV_OUT_INDEX BlockIOTag(0x1du) /* LTPro */ -#define TV_REG_INDEX 0x000000fful -#define TV_ON 0x00000100ul -/* ? 0xfffffe00ul */ -#define GP_IO IOPortTag(0x1eu, 0x1eu) /* VT/GT */ -#define GP_IO_CNTL BlockIOTag(0x1fu) /* VT/GT */ -#define HW_DEBUG BlockIOTag(0x1fu) /* VTB/GTB/LT */ -#define FAST_SRCCOPY_DIS 0x00000001ul -#define BYPASS_SUBPIC_DBF 0x00000001ul /* XL/XC */ -#define SRC_AUTONA_FIX_DIS 0x00000002ul -#define SYNC_PD_EN 0x00000002ul /* Mobility */ -#define DISP_QW_FIX_DIS 0x00000004ul -#define GUIDST_WB_EXP_DIS 0x00000008ul -#define CYC_ALL_FIX_DIS 0x00000008ul /* GTPro */ -#define AGPPLL_FIX_EN 0x00000008ul /* Mobility */ -#define SRC_AUTONA_ALWAYS_EN 0x00000010ul -#define GUI_BEATS_HOST_P 0x00000010ul /* GTPro */ -#define DRV_CNTL_DQMB_WEB 0x00000020ul -#define FAST_FILL_SCISSOR_DIS 0x00000020ul /* GT2c/VT4 */ -#define INTER_BLIT_FIX_DIS 0x00000020ul /* GTPro */ -#define DRV_CNTL_MA 0x00000040ul -#define AUTO_BLKWRT_COLOR_DIS 0x00000040ul /* GT2c/VT4 */ -#define INTER_PRIM_DIS 0x00000040ul /* GTPro */ -#define DRV_CNTL_MD 0x00000080ul -#define CHG_DEV_ID 0x00000100ul -#define SRC_TRACK_DST_FIX_DIS 0x00000200ul -#define HCLK_FB_SKEW 0x00000380ul /* GT2c/VT4 */ -#define SRC_TRACK_DST_FIX_DIS_P 0x00000080ul /* GTPro */ -#define AUTO_BLKWRT_COLOR_DIS_P 0x00000100ul /* GTPro */ -#define INTER_LINE_OVERLAP_DIS 0x00000200ul /* GTPro */ -#define MEM_OE_PULLBACK 0x00000400ul -#define DBL_BUFFER_EN 0x00000400ul /* GTPro */ -#define MEM_WE_FIX_DIS 0x00000800ul -#define MEM_OE_PULLBACK_B 0x00000800ul /* GT2c/VT4 */ -#define CMDFIFO_SIZE_DIS_P 0x00000800ul /* GTPro */ -#define RD_EN_FIX_DIS 0x00001000ul -#define MEM_WE_FIX_DIS_B 0x00001000ul -#define AUTO_FF_DIS 0x00001000ul /* GTPro */ -#define CMDFIFO_SIZE_DIS 0x00002000ul /* GT2c/VT4 */ -#define AUTO_BLKWRT_DIS 0x00002000ul /* GTPro */ -#define GUI_BEATS_HOST 0x00004000ul /* GT2c/VT4 */ -#define ORED_INVLD_RB_CACHE 0x00004000ul /* GTPro */ -#define BLOCK_DBL_BUF 0x00008000ul /* GTPro */ -#define R2W_TURNAROUND_DELAY 0x00020000ul /* GT2c/VT4 */ -#define ENA_32BIT_DATA_BUS 0x00040000ul /* GT2c/VT4 */ -#define HCLK_FB_SKEW_P 0x00070000ul /* GTPro */ -#define ENA_FLASH_ROM 0x00080000ul /* GT2c/VT4 */ -#define DISABLE_SWITCH_FIX 0x00080000ul /* GTPro */ -#define MCLK_START_EN 0x00080000ul /* LTPro */ -#define SEL_VBLANK_BDL_BUF 0x00100000ul /* GTPro */ -#define CMDFIFO_64EN 0x00200000ul /* GTPro */ -#define BM_FIX_DIS 0x00400000ul /* GTPro */ -#define Z_SWITCH_EN 0x00800000ul /* LTPro */ -#define FLUSH_HOST_WB 0x01000000ul /* GTPro */ -#define HW_DEBUG_WRITE_MSK_FIX_DIS 0x02000000ul /* LTPro */ -#define Z_NO_WRITE_EN 0x04000000ul /* LTPro */ -#define DISABLE_PCLK_RESET_P 0x08000000ul /* LTPro */ -#define PM_D3_SUPPORT_ENABLE_P 0x10000000ul /* LTPro */ -#define STARTCYCLE_FIX_ENABLE 0x20000000ul /* LTPro */ -#define DONT_RST_CHAREN 0x20000000ul /* XL/XC */ -#define C3_FIX_ENABLE 0x40000000ul /* LTPro */ -#define BM_HOSTRA_EN 0x40000000ul /* XL/XC */ -#define PKGBGAb 0x80000000ul /* XL/XC */ -#define AUTOEXP_HORZ_FIX 0x80000000ul /* Mobility */ -#define SCRATCH_REG0 IOPortTag(0x10u, 0x20u) -#define SCRATCH_REG1 IOPortTag(0x11u, 0x21u) -/* BIOS_BASE_SEGMENT 0x0000007ful */ /* As above */ -/* ? 0x00000f80ul */ -#define BIOS_INIT_DAC_SUBTYPE 0x0000f000ul -/* ? 0xffff0000ul */ -#define SCRATCH_REG2 BlockIOTag(0x22u) /* LT */ -#define SCRATCH_REG3 BlockIOTag(0x23u) /* GTPro */ -#define CLOCK_CNTL IOPortTag(0x12u, 0x24u) -#define CLOCK_BIT 0x00000004ul /* For ICS2595 */ -#define CLOCK_PULSE 0x00000008ul /* For ICS2595 */ -#define CLOCK_SELECT 0x0000000ful -#define CLOCK_DIVIDER 0x00000030ul -#define CLOCK_STROBE 0x00000040ul -#define CLOCK_DATA 0x00000080ul -/* ? 0x00000100ul */ -#define PLL_WR_EN 0x00000200ul /* For internal PLL */ -#define PLL_ADDR 0x0000fc00ul /* For internal PLL */ -#define PLL_DATA 0x00ff0000ul /* For internal PLL */ -/* ? 0xff000000ul */ -#define CONFIG_STAT64_1 BlockIOTag(0x25u) /* GTPro */ -#define CFG_SUBSYS_DEV_ID 0x000000fful -#define CFG_SUBSYS_VEN_ID 0x00ffff00ul -/* ? 0x1f000000ul */ -#define CFG_DIMM_TYPE 0xe0000000ul -#define CFG_PCI_SUBSYS_DEV_ID 0x0000fffful /* XC/XL */ -#define CFG_PCI_SUBSYS_VEN_ID 0xffff0000ul /* XC/XL */ -#define CONFIG_STAT64_2 BlockIOTag(0x26u) /* GTPro */ -#define CFG_DIMM_TYPE_3 0x00000001ul -/* ? 0x0000001eul */ -#define CFG_ROMWRTEN 0x00000020ul -#define CFG_AGPVCOGAIN 0x000000c0ul -#define CFG_PCI_TYPE 0x00000100ul -#define CFG_AGPSKEW 0x00000e00ul -#define CFG_X1CLKSKEW 0x00007000ul -#define CFG_PANEL_ID_P 0x000f8000ul /* LTPro */ -/* ? 0x00100000ul */ -#define CFG_PREFETCH_EN 0x00200000ul -#define CFG_ID_DISABLE 0x00400000ul -#define CFG_PRE_TESTEN 0x00800000ul -/* ? 0x01000000ul */ -#define CFG_PCI5VEN 0x02000000ul /* LTPro */ -#define CFG_VGA_DISABLE 0x04000000ul -#define CFG_ENINTB 0x08000000ul -/* ? 0x10000000ul */ -#define CFG_ROM_REMAP_2 0x20000000ul -#define CFG_IDSEL 0x40000000ul -/* ? 0x80000000ul */ -#define TV_OUT_DATA BlockIOTag(0x27u) /* LTPro */ -#define BUS_CNTL IOPortTag(0x13u, 0x28u) -# define BUS_WS 0x0000000ful -# define BUS_DBL_RESYNC 0x00000001ul /* VTB/GTB/LT */ -# define BUS_MSTR_RESET 0x00000002ul /* VTB/GTB/LT */ -# define BUS_FLUSH_BUF 0x00000004ul /* VTB/GTB/LT */ -# define BUS_STOP_REQ_DIS 0x00000008ul /* VTB/GTB/LT */ -# define BUS_ROM_WS 0x000000f0ul -# define BUS_APER_REG_DIS 0x00000010ul /* VTB/GTB/LT */ -# define BUS_EXTRA_PIPE_DIS 0x00000020ul /* VTB/GTB/LT */ -# define BUS_MASTER_DIS 0x00000040ul /* VTB/GTB/LT */ -# define BUS_ROM_WRT_EN 0x00000080ul /* GTPro */ -# define BUS_ROM_PAGE 0x00000f00ul -# define BUS_MINOR_REV_ID 0x00000700ul /* LTPro */ -# define BUS_EXT_REG_EN 0x08000000ul -/* First silicom - Prototype (A11) 0x00000000ul */ -/* Metal mask spin (A12 & A13) 0x00000100ul */ -/* All layer spin (A21) 0x00000200ul */ -/* Fast metal spin (A22) - Prod. 0x00000300ul */ -/* All layer spin (A31) 0x00000700ul */ -/* ? 0x00000800ul */ /* LTPro */ -#define BUS_CHIP_HIDDEN_REV 0x00000300ul /* XC/XL */ -/* ? 0x00001c00ul */ /* XC/XL */ -#define BUS_ROM_DIS 0x00001000ul -#define BUS_IO_16_EN 0x00002000ul /* GX */ -#define BUS_PCI_READ_RETRY_EN 0x00002000ul /* VTB/GTB/LT */ -#define BUS_DAC_SNOOP_EN 0x00004000ul -#define BUS_PCI_RETRY_EN 0x00008000ul /* VT/GT */ -#define BUS_PCI_WRT_RETRY_EN 0x00008000ul /* VTB/GTB/LT */ -#define BUS_FIFO_WS 0x000f0000ul -#define BUS_RETRY_WS 0x000f0000ul /* VTB/GTB/LT */ -#define BUS_FIFO_ERR_INT_EN 0x00100000ul -#define BUS_MSTR_RD_MULT 0x00100000ul /* VTB/GTB/LT */ -#define BUS_FIFO_ERR_INT 0x00200000ul -#define BUS_MSTR_RD_LINE 0x00200000ul /* VTB/GTB/LT */ -#define BUS_HOST_ERR_INT_EN 0x00400000ul -#define BUS_SUSPEND 0x00400000ul /* GTPro */ -#define BUS_HOST_ERR_INT 0x00800000ul -#define BUS_LAT16X 0x00800000ul /* GTPro */ -#define BUS_PCI_DAC_WS 0x07000000ul -#define BUS_RD_DISCARD_EN 0x01000000ul /* VTB/GTB/LT */ -#define BUS_RD_ABORT_EN 0x02000000ul /* VTB/GTB/LT */ -#define BUS_MSTR_WS 0x04000000ul /* VTB/GTB/LT */ -#define BUS_PCI_DAC_DLY 0x08000000ul -#define BUS_EXT_REG_EN 0x08000000ul /* VT/GT */ -#define BUS_PCI_MEMW_WS 0x10000000ul -#define BUS_MSTR_DISCONNECT_EN 0x10000000ul /* VTB/GTB/LT */ -#define BUS_PCI_BURST_DEC 0x20000000ul /* GX/CX */ -#define BUS_BURST 0x20000000ul /* 264xT */ -#define BUS_WRT_BURST 0x20000000ul /* VTB/GTB/LT */ -#define BUS_RDY_READ_DLY 0xc0000000ul -#define BUS_READ_BURST 0x40000000ul /* VTB/GTB/LT */ -#define BUS_RDY_READ_DLY_B 0x80000000ul /* VTB/GTB/LT */ -#define LCD_INDEX BlockIOTag(0x29u) /* LTPro */ -#define LCD_REG_INDEX 0x0000003ful -/* ? 0x000000c0ul */ -#define LCD_DISPLAY_DIS 0x00000100ul -#define LCD_SRC_SEL 0x00000200ul -#define LCD_SRC_SEL_CRTC1 0x00000000ul -#define LCD_SRC_SEL_CRTC2 0x00000200ul -#define LCD_CRTC2_DISPLAY_DIS 0x00000400ul -#define LCD_GUI_ACTIVE 0x00000800ul /* XC/XL */ -/* ? 0x00fff000ul */ -#define LCD_MONDET_SENSE 0x01000000ul /* XC/XL */ -#define LCD_MONDET_INT_POL 0x02000000ul /* XC/XL */ -#define LCD_MONDET_INT_EN 0x04000000ul /* XC/XL */ -#define LCD_MONDET_INT 0x08000000ul /* XC/XL */ -#define LCD_MONDET_EN 0x10000000ul /* XC/XL */ -#define LCD_EN_PL 0x20000000ul /* XC/XL */ -/* ? 0xc0000000ul */ -#define HFB_PITCH_ADDR BlockIOTag(0x2au) /* LT */ -#define LCD_DATA BlockIOTag(0x2au) /* LTPro */ -#define EXT_MEM_CNTL BlockIOTag(0x2bu) /* VTB/GTB/LT */ -#define MEM_CNTL IOPortTag(0x14u, 0x2cu) -#define CTL_MEM_SIZE 0x00000007ul -/* ? 0x00000008ul */ -#define CTL_MEM_REFRESH 0x00000078ul /* VT/GT */ -#define CTL_MEM_SIZEB 0x0000000ful /* VTB/GTB/LT */ -#define CTL_MEM_RD_LATCH_EN 0x00000010ul -#define CTL_MEM_RD_LATCH_DLY 0x00000020ul -#define CTL_MEM_LATENCY 0x00000030ul /* VTB/GTB/LT */ -#define CTL_MEM_SD_LATCH_EN 0x00000040ul -#define CTL_MEM_SD_LATCH_DLY 0x00000080ul -#define CTL_MEM_LATCH 0x000000c0ul /* VTB/GTB/LT */ -#define CTL_MEM_WDOE_CNTL 0x000000c0ul /* XC/XL */ -#define CTL_MEM_FULL_PLS 0x00000100ul -#define CTL_MEM_CYC_LNTH_AUX 0x00000180ul /* VT/GT */ -#define CTL_MEM_TRP 0x00000300ul /* VTB/GTB/LT */ -#define CTL_MEM_CYC_LNTH 0x00000600ul -#define CTL_MEM_REFRESH_RATE 0x00001800ul /* 264xT */ -#define CTL_MEM_TRCD 0x00000c00ul /* VTB/GTB/LT */ -#define CTL_MEM_WR_RDY_SEL 0x00000800ul /* GX/CX */ -#define CTL_MEM_EXT_RMW_CYC_EN 0x00001000ul /* GX/CX */ -#define CTL_MEM_TCRD 0x00001000ul /* VTB/GTB/LT */ -#define CTL_MEM_DLL_RESET 0x00002000ul /* VT/GT */ -#define CTL_MEM_TR2W 0x00002000ul /* GTPro */ -#define CTL_MEM_ACTV_PRE 0x0000c000ul /* VT/GT */ -#define CTL_MEM_CAS_PHASE 0x00004000ul /* GTPro */ -#define CTL_MEM_OE_PULLBACK 0x00008000ul /* GTPro */ -#define CTL_MEM_TWR 0x0000c000ul /* XC/XL */ -#define CTL_MEM_BNDRY 0x00030000ul -#define CTL_MEM_BNDRY_0K 0x00000000ul -#define CTL_MEM_BNDRY_256K 0x00010000ul -#define CTL_MEM_BNDRY_512K 0x00020000ul -#define CTL_MEM_BNDRY_1024K 0x00030000ul -#define CTL_MEM_DLL_GAIN_CNTL 0x00030000ul /* VT/GT */ -#define CTL_MEM_BNDRY_EN 0x00040000ul -#define CTL_MEM_SDRAM_RESET 0x00040000ul /* VT/GT */ -#define CTL_MEM_TRAS 0x00070000ul /* VTB/GTB/LT */ -#define CTL_MEM_TILE_SELECT 0x00180000ul /* VT/GT */ -#define CTL_MEM_REFRESH_DIS 0x00080000ul /* VTB/GTB/LT */ -#define CTL_MEM_LOW_LATENCY_MODE 0x00200000ul /* VT/GT */ -#define CTL_MEM_CDE_PULLBACK 0x00400000ul /* VT/GT */ -#define CTL_MEM_REFRESH_RATE_B 0x00f00000ul /* VTB/GTB/LT */ -#define CTL_MEM_PIX_WIDTH 0x07000000ul -#define CTL_MEM_LOWER_APER_ENDIAN 0x03000000ul /* VTB/GTB/LT */ -#define CTL_MEM_OE_SELECT 0x18000000ul /* VT/GT */ -#define CTL_MEM_UPPER_APER_ENDIAN 0x0c000000ul /* VTB/GTB/LT */ -/* ? 0xe0000000ul */ -#define CTL_MEM_PAGE_SIZE 0x30000000ul /* VTB/GTB/LT */ -#define MEM_VGA_WP_SEL IOPortTag(0x15u, 0x2du) -#define MEM_VGA_WPS0 0x0000fffful -#define MEM_VGA_WPS1 0xffff0000ul -#define MEM_VGA_RP_SEL IOPortTag(0x16u, 0x2eu) -#define MEM_VGA_RPS0 0x0000fffful -#define MEM_VGA_RPS1 0xffff0000ul -#define LT_GIO BlockIOTag(0x2fu) /* LT */ -#define I2C_CNTL_1 BlockIOTag(0x2fu) /* GTPro */ -#define DAC_REGS IOPortTag(0x17u, 0x30u) /* 4 separate bytes */ -#define M64_DAC_WRITE (DAC_REGS + 0) -#define M64_DAC_DATA (DAC_REGS + 1) -#define M64_DAC_MASK (DAC_REGS + 2) -#define M64_DAC_READ (DAC_REGS + 3) -#define DAC_CNTL IOPortTag(0x18u, 0x31u) -#define DAC_EXT_SEL 0x00000003ul -#define DAC_EXT_SEL_RS2 0x000000001ul -#define DAC_EXT_SEL_RS3 0x000000002ul -#define DAC_RANGE_CTL 0x00000003ul /* VTB/GTB/LT */ -#define DAC_BLANKING 0x00000004ul /* 264xT */ -#define DAC_CMP_DIS 0x00000008ul /* 264xT */ -#define DAC1_CLK_SEL 0x00000010ul /* LTPro */ -#define DAC_PALETTE_ACCESS_CNTL 0x00000020ul /* LTPro */ -#define DAC_PALETTE2_SNOOP_EN 0x00000040ul /* LTPro */ -#define DAC_CMP_OUTPUT 0x00000080ul /* 264xT */ -#define DAC_8BIT_EN 0x00000100ul -#define DAC_PIX_DLY 0x00000600ul -#define DAC_DIRECT 0x00000400ul /* VTB/GTB/LT */ -#define DAC_BLANK_ADJ 0x00001800ul -#define DAC_PAL_CLK_SEL 0x00000800ul /* VTB/GTB/LT */ -#define DAC_CRT_SENSE 0x00000800ul /* XC/XL */ -#define DAC_CRT_DETECTION_ON 0x00001000ul /* XC/XL */ -#define DAC_VGA_ADR_EN 0x00002000ul -#define DAC_FEA_CON_EN 0x00004000ul /* 264xT */ -#define DAC_PDMN 0x00008000ul /* 264xT */ -#define DAC_TYPE 0x00070000ul -/* ? 0x00f80000ul */ -#define DAC_MON_ID_STATE0 0x01000000ul /* GX-E+/CX */ -#define DAC_GIO_STATE_1 0x01000000ul /* 264xT */ -#define DAC_MON_ID_STATE1 0x02000000ul /* GX-E+/CX */ -#define DAC_GIO_STATE_0 0x02000000ul /* 264xT */ -#define DAC_MON_ID_STATE2 0x04000000ul /* GX-E+/CX */ -#define DAC_GIO_STATE_4 0x04000000ul /* 264xT */ -#define DAC_MON_ID_DIR0 0x08000000ul /* GX-E+/CX */ -#define DAC_GIO_DIR_1 0x08000000ul /* 264xT */ -#define DAC_MON_ID_DIR1 0x10000000ul /* GX-E+/CX */ -#define DAC_GIO_DIR_0 0x10000000ul /* 264xT */ -#define DAC_MON_ID_DIR2 0x20000000ul /* GX-E+/CX */ -#define DAC_GIO_DIR_4 0x20000000ul /* 264xT */ -#define DAC_MAN_CMP_STATE 0x40000000ul /* GX-E+ */ -#define DAC_RW_WS 0x80000000ul /* VT/GT */ -#define HORZ_STRETCHING BlockIOTag(0x32u) /* LT */ -#define HORZ_STRETCH_BLEND 0x00000ffful -#define HORZ_STRETCH_RATIO 0x0000fffful -#define HORZ_STRETCH_LOOP 0x00070000ul -#define HORZ_STRETCH_LOOP09 0x00000000ul -#define HORZ_STRETCH_LOOP11 0x00010000ul -#define HORZ_STRETCH_LOOP12 0x00020000ul -#define HORZ_STRETCH_LOOP14 0x00030000ul -#define HORZ_STRETCH_LOOP15 0x00040000ul -/* ? 0x00050000ul */ -/* ? 0x00060000ul */ -/* ? 0x00070000ul */ -/* ? 0x00080000ul */ -#define HORZ_PANEL_SIZE 0x0ff00000ul /* XC/XL */ -/* ? 0x10000000ul */ -#define AUTO_HORZ_RATIO 0x20000000ul /* XC/XL */ -#define HORZ_STRETCH_MODE 0x40000000ul -#define HORZ_STRETCH_EN 0x80000000ul -#define EXT_DAC_REGS BlockIOTag(0x32u) /* GTPro */ -#define VERT_STRETCHING BlockIOTag(0x33u) /* LT */ -#define VERT_STRETCH_RATIO0 0x000003fful -#define VERT_STRETCH_RATIO1 0x000ffc00ul -#define VERT_STRETCH_RATIO2 0x3ff00000ul -#define VERT_STRETCH_USE0 0x40000000ul -#define VERT_STRETCH_EN 0x80000000ul -#define GEN_TEST_CNTL IOPortTag(0x19u, 0x34u) -#define GEN_EE_DATA_OUT 0x00000001ul /* GX/CX */ -#define GEN_GIO2_DATA_OUT 0x00000001ul /* 264xT */ -#define GEN_EE_CLOCK 0x00000002ul /* GX/CX */ -/* ? 0x00000002ul */ /* 264xT */ -#define GEN_EE_CHIP_SEL 0x00000004ul /* GX/CX */ -#define GEN_GIO3_DATA_OUT 0x00000004ul /* 264xT */ -#define GEN_EE_DATA_IN 0x00000008ul /* GX/CX */ -#define GEN_GIO2_DATA_IN 0x00000008ul /* 264xT */ -#define GEN_EE_EN 0x00000010ul /* GX/CX */ -#define GEN_GIO2_ENABLE 0x00000010ul /* 264xT */ -#define GEN_ICON2_ENABLE 0x00000010ul /* XC/XL */ -#define GEN_OVR_OUTPUT_EN 0x00000020ul /* GX/CX */ -#define GEN_GIO2_WRITE 0x00000020ul /* 264xT */ -#define GEN_CUR2_ENABLE 0x00000020ul /* XC/XL */ -#define GEN_OVR_POLARITY 0x00000040ul /* GX/CX */ -#define GEN_ICON_ENABLE 0x00000040ul /* XC/XL */ -#define GEN_CUR_EN 0x00000080ul -#define GEN_GUI_EN 0x00000100ul /* GX/CX */ -#define GEN_GUI_RESETB 0x00000100ul /* 264xT */ -#define GEN_BLOCK_WR_EN 0x00000200ul /* GX */ -/* ? 0x00000200ul */ /* CX/264xT */ -#define GEN_SOFT_RESET 0x00000200ul /* VTB/GTB/LT */ -#define GEN_MEM_TRISTATE 0x00000400ul /* GTPro */ -/* ? 0x00000800ul */ -#define GEN_TEST_VECT_MODE 0x00003000ul /* VT/GT */ -/* ? 0x0000c000ul */ -#define GEN_TEST_FIFO_EN 0x00010000ul /* GX/CX */ -#define GEN_TEST_GUI_REGS_EN 0x00020000ul /* GX/CX */ -#define GEN_TEST_VECT_EN 0x00040000ul /* GX/CX */ -#define GEN_TEST_CRC_STR 0x00080000ul /* GX-C/-D */ -/* ? 0x00080000ul */ /* GX-E+/CX */ -#define GEN_TEST_MODE_T 0x000f0000ul /* 264xT */ -#define GEN_TEST_MODE 0x00700000ul /* GX/CX */ -#define GEN_TEST_CNT_EN 0x00100000ul /* 264xT */ -#define GEN_TEST_CRC_EN 0x00200000ul /* 264xT */ -/* ? 0x00400000ul */ /* 264xT */ -/* ? 0x00800000ul */ -#define GEN_TEST_MEM_WR 0x01000000ul /* GX-C/-D */ -#define GEN_TEST_MEM_STROBE 0x02000000ul /* GX-C/-D */ -#define GEN_TEST_DST_SS_EN 0x04000000ul /* GX/CX */ -#define GEN_TEST_DST_SS_STROBE 0x08000000ul /* GX/CX */ -#define GEN_TEST_SRC_SS_EN 0x10000000ul /* GX/CX */ -#define GEN_TEST_SRC_SS_STROBE 0x20000000ul /* GX/CX */ -#define GEN_TEST_CNT_VALUE 0x3f000000ul /* 264xT */ -#define GEN_TEST_CC_EN 0x40000000ul /* GX/CX */ -#define GEN_TEST_CC_STROBE 0x80000000ul /* GX/CX */ -/* ? 0xc0000000ul */ /* 264xT */ -#define GEN_DEBUG_MODE 0xff000000ul /* VTB/GTB/LT */ -#define LCD_GEN_CTRL BlockIOTag(0x35u) /* LT */ -#define CRT_ON 0x00000001ul -#define LCD_ON 0x00000002ul -#define HORZ_DIVBY2_EN 0x00000004ul -#define DONT_DS_ICON 0x00000008ul -#define LOCK_8DOT 0x00000010ul -#define ICON_ENABLE 0x00000020ul -#define DONT_SHADOW_VPAR 0x00000040ul -#define V2CLK_PM_EN 0x00000080ul -#define RST_FM 0x00000100ul -#define DISABLE_PCLK_RESET 0x00000200ul /* XC/XL */ -#define DIS_HOR_CRT_DIVBY2 0x00000400ul -#define SCLK_SEL 0x00000800ul -#define SCLK_DELAY 0x0000f000ul -#define TVCLK_PM_EN 0x00010000ul -#define VCLK_DAC_PM_EN 0x00020000ul -#define VCLK_LCD_OFF 0x00040000ul -#define SELECT_WAIT_4MS 0x00080000ul -#define XTALIN_PM_EN 0x00080000ul /* XC/XL */ -#define V2CLK_DAC_PM_EN 0x00100000ul -#define LVDS_EN 0x00200000ul -#define LVDS_PLL_EN 0x00400000ul -#define LVDS_PLL_RESET 0x00800000ul -#define LVDS_RESERVED_BITS 0x07000000ul -#define CRTC_RW_SELECT 0x08000000ul /* LTPro */ -#define USE_SHADOWED_VEND 0x10000000ul -#define USE_SHADOWED_ROWCUR 0x20000000ul -#define SHADOW_EN 0x40000000ul -#define SHADOW_RW_EN 0x80000000ul -#define CUSTOM_MACRO_CNTL BlockIOTag(0x35u) /* GTPro */ -#define POWER_MANAGEMENT BlockIOTag(0x36u) /* LT */ -#define PWR_MGT_ON 0x00000001ul -#define PWR_MGT_MODE 0x00000006ul -#define AUTO_PWRUP_EN 0x00000008ul -#define ACTIVITY_PIN_ON 0x00000010ul -#define STANDBY_POL 0x00000020ul -#define SUSPEND_POL 0x00000040ul -#define SELF_REFRESH 0x00000080ul -#define ACTIVITY_PIN_EN 0x00000100ul -#define KEYBD_SNOOP 0x00000200ul -#define USE_F32KHZ 0x00000400ul /* LTPro */ -#define DONT_USE_XTALIN 0x00000400ul /* XC/XL */ -#define TRISTATE_MEM_EN 0x00000800ul /* LTPro */ -#define LCDENG_TEST_MODE 0x0000f000ul -#define STANDBY_COUNT 0x000f0000ul -#define SUSPEND_COUNT 0x00f00000ul -#define BAISON 0x01000000ul -#define BLON 0x02000000ul -#define DIGON 0x04000000ul -#define PM_D3_SUPPORT_ENABLE 0x08000000ul /* XC/XL */ -#define STANDBY_NOW 0x10000000ul -#define SUSPEND_NOW 0x20000000ul -#define PWR_MGT_STATUS 0xc0000000ul -#define CONFIG_CNTL IOPortTag(0x1au, 0x37u) -#define CFG_MEM_AP_SIZE 0x00000003ul -#define CFG_MEM_VGA_AP_EN 0x00000004ul -/* ? 0x00000008ul */ -#define CFG_MEM_AP_LOC 0x00003ff0ul -/* ? 0x0000c000ul */ -#define CFG_CARD_ID 0x00070000ul -#define CFG_VGA_DIS 0x00080000ul -/* ? 0x00f00000ul */ -#define CFG_CDE_WINDOW 0x3f000000ul /* VT/GT */ -/* ? 0xc0000000ul */ -#define CONFIG_CHIP_ID IOPortTag(0x1bu, 0x38u) /* Read */ -#define CFG_CHIP_TYPE0 0x000000fful -#define CFG_CHIP_TYPE1 0x0000ff00ul -#define CFG_CHIP_TYPE 0x0000fffful -#define CFG_CHIP_CLASS 0x00ff0000ul -#define CFG_CHIP_REV 0xff000000ul -#define CFG_CHIP_VERSION 0x07000000ul /* 264xT */ -#define CFG_CHIP_FOUNDRY 0x38000000ul /* 264xT */ -#define CFG_CHIP_REVISION 0xc0000000ul /* 264xT */ -#define CONFIG_STATUS64_0 IOPortTag(0x1cu, 0x39u) /* Read (R/W (264xT)) */ -#define CFG_BUS_TYPE 0x00000007ul /* GX/CX */ -#define CFG_MEM_TYPE_T 0x00000007ul /* 264xT */ -#define CFG_MEM_TYPE 0x00000038ul /* GX/CX */ -#define CFG_DUAL_CAS_EN_T 0x00000008ul /* 264xT */ -#define CFG_ROM_128K_EN 0x00000008ul /* VTB/GTB/LT */ -#define CFG_ROM_REMAP 0x00000008ul /* GTPro */ -#define CFG_VGA_EN_T 0x00000010ul /* VT/GT */ -#define CFG_CLOCK_EN 0x00000020ul /* 264xT */ -#define CFG_DUAL_CAS_EN 0x00000040ul /* GX/CX */ -#define CFG_VMC_SENSE 0x00000040ul /* VT/GT */ -#define CFG_SHARED_MEM_EN 0x00000040ul /* VTB/GTB/LT */ -#define CFG_LOCAL_BUS_OPTION 0x00000180ul /* GX/CX */ -#define CFG_VFC_SENSE 0x00000080ul /* VT/GT */ -#define CFG_INIT_DAC_TYPE 0x00000e00ul /* GX/CX */ -#define CFG_INIT_CARD_ID 0x00007000ul /* GX-C/-D */ -#define CFG_BLK_WR_SIZE 0x00001000ul /* GX-E+ */ -#define CFG_INT_QSF_EN 0x00002000ul /* GX-E+ */ -/* ? 0x00004000ul */ /* GX-E+ */ -/* ? 0x00007000ul */ /* CX */ -#define CFG_TRI_BUF_DIS 0x00008000ul /* GX/CX */ -#define CFG_BOARD_ID 0x0000ff00ul /* VT/GT */ -#define CFG_EXT_RAM_ADDR 0x003f0000ul /* GX/CX */ -#define CFG_PANEL_ID 0x001f0000ul /* LT */ -#define CFG_MACROVISION_EN 0x00200000ul /* GTPro */ -#define CFG_ROM_DIS 0x00400000ul /* GX/CX */ -#define CFG_PCI33EN 0x00400000ul /* GTPro */ -#define CFG_VGA_EN 0x00800000ul /* GX/CX */ -#define CFG_FULLAGP 0x00800000ul /* GTPro */ -#define CFG_ARITHMOS_ENABLE 0x00800000ul /* XC/XL */ -#define CFG_LOCAL_BUS_CFG 0x01000000ul /* GX/CX */ -#define CFG_CHIP_EN 0x02000000ul /* GX/CX */ -#define CFG_LOCAL_READ_DLY_DIS 0x04000000ul /* GX/CX */ -#define CFG_ROM_OPTION 0x08000000ul /* GX/CX */ -#define CFG_BUS_OPTION 0x10000000ul /* GX/CX */ -#define CFG_LOCAL_DAC_WR_EN 0x20000000ul /* GX/CX */ -#define CFG_VLB_RDY_DIS 0x40000000ul /* GX/CX */ -#define CFG_AP_4GBYTE_DIS 0x80000000ul /* GX/CX */ -#define CONFIG_STATUS64_1 IOPortTag(0x1du, 0x3au) /* Read */ -#define CFG_PCI_DAC_CFG 0x00000001ul /* GX/CX */ -/* ? 0x0000001eul */ /* GX/CX */ -#define CFG_1C8_IO_SEL 0x00000020ul /* GX/CX */ -/* ? 0xffffffc0ul */ /* GX/CX */ -#define CRC_SIG 0xfffffffful /* 264xT */ -#define MPP_CONFIG BlockIOTag(0x3bu) /* VTB/GTB/LT */ -#define MPP_STROBE_CONFIG BlockIOTag(0x3cu) /* VTB/GTB/LT */ -#define MPP_ADDR BlockIOTag(0x3du) /* VTB/GTB/LT */ -#define MPP_DATA BlockIOTag(0x3eu) /* VTB/GTB/LT */ -#define TVO_CNTL BlockIOTag(0x3fu) /* VTB/GTB/LT */ -/* GP_IO IOPortTag(0x1eu, 0x1eu) */ /* See above */ -/* CRTC_H_TOTAL_DISP IOPortTag(0x1fu, 0x00u) */ /* Duplicate */ -#define DST_OFF_PITCH BlockIOTag(0x40u) -#define DST_OFFSET 0x000ffffful -/* ? 0x00300000ul */ -#define DST_PITCH 0xffc00000ul -#define DST_X BlockIOTag(0x41u) -#define DST_Y BlockIOTag(0x42u) -#define DST_Y_X BlockIOTag(0x43u) -#define DST_WIDTH BlockIOTag(0x44u) -#define DST_HEIGHT BlockIOTag(0x45u) -#define DST_HEIGHT_WIDTH BlockIOTag(0x46u) -#define DST_X_WIDTH BlockIOTag(0x47u) -#define DST_BRES_LNTH BlockIOTag(0x48u) -#define DST_BRES_ERR BlockIOTag(0x49u) -#define DST_BRES_INC BlockIOTag(0x4au) -#define DST_BRES_DEC BlockIOTag(0x4bu) -#define DST_CNTL BlockIOTag(0x4cu) -#define DST_X_DIR 0x00000001ul -#define DST_Y_DIR 0x00000002ul -#define DST_Y_MAJOR 0x00000004ul -#define DST_X_TILE 0x00000008ul -#define DST_Y_TILE 0x00000010ul -#define DST_LAST_PEL 0x00000020ul -#define DST_POLYGON_EN 0x00000040ul -#define DST_24_ROT_EN 0x00000080ul -#define DST_24_ROT 0x00000700ul -#define DST_BRES_SIGN 0x00000800ul /* GX/CX */ -#define DST_BRES_ZERO 0x00000800ul /* CT */ -#define DST_POLYGON_RTEDGE_DIS 0x00001000ul /* CT */ -#define TRAIL_X_DIR 0x00002000ul /* GT */ -#define TRAP_FILL_DIR 0x00004000ul /* GT */ -#define TRAIL_BRES_SIGN 0x00008000ul /* GT */ -/* ? 0x00010000ul */ -#define BRES_SIGN_AUTO 0x00020000ul /* GT */ -/* ? 0x00040000ul */ -#define ALPHA_OVERLAP_ENB 0x00080000ul /* GTPro */ -#define SUB_PIX_ON 0x00100000ul /* GTPro */ -/* ? 0xffe00000ul */ -/* DST_Y_X BlockIOTag(0x4du) */ /* Duplicate */ -#define TRAIL_BRES_ERR BlockIOTag(0x4eu) /* GT */ -#define TRAIL_BRES_INC BlockIOTag(0x4fu) /* GT */ -#define TRAIL_BRES_DEC BlockIOTag(0x50u) /* GT */ -#define LEAD_BRES_LNTH BlockIOTag(0x51u) /* GT */ -#define Z_OFF_PITCH BlockIOTag(0x52u) /* GT */ -#define Z_CNTL BlockIOTag(0x53u) /* GT */ -#define ALPHA_TST_CNTL BlockIOTag(0x54u) /* GTPro */ -/* ? BlockIOTag(0x55u) */ -#define SECONDARY_STW_EXP BlockIOTag(0x56u) /* GTPro */ -#define SECONDARY_S_X_INC BlockIOTag(0x57u) /* GTPro */ -#define SECONDARY_S_Y_INC BlockIOTag(0x58u) /* GTPro */ -#define SECONDARY_S_START BlockIOTag(0x59u) /* GTPro */ -#define SECONDARY_W_X_INC BlockIOTag(0x5au) /* GTPro */ -#define SECONDARY_W_Y_INC BlockIOTag(0x5bu) /* GTPro */ -#define SECONDARY_W_START BlockIOTag(0x5cu) /* GTPro */ -#define SECONDARY_T_X_INC BlockIOTag(0x5du) /* GTPro */ -#define SECONDARY_T_Y_INC BlockIOTag(0x5eu) /* GTPro */ -#define SECONDARY_T_START BlockIOTag(0x5fu) /* GTPro */ -#define SRC_OFF_PITCH BlockIOTag(0x60u) -#define SRC_OFFSET 0x000ffffful -/* ? 0x00300000ul */ -#define SRC_PITCH 0xffc00000ul -#define SRC_X BlockIOTag(0x61u) -#define SRC_Y BlockIOTag(0x62u) -#define SRC_Y_X BlockIOTag(0x63u) -#define SRC_WIDTH1 BlockIOTag(0x64u) -#define SRC_HEIGHT1 BlockIOTag(0x65u) -#define SRC_HEIGHT1_WIDTH1 BlockIOTag(0x66u) -#define SRC_X_START BlockIOTag(0x67u) -#define SRC_Y_START BlockIOTag(0x68u) -#define SRC_Y_X_START BlockIOTag(0x69u) -#define SRC_WIDTH2 BlockIOTag(0x6au) -#define SRC_HEIGHT2 BlockIOTag(0x6bu) -#define SRC_HEIGHT2_WIDTH2 BlockIOTag(0x6cu) -#define SRC_CNTL BlockIOTag(0x6du) -# define SRC_PATT_EN 0x00000001ul -# define SRC_PATT_ROT_EN 0x00000002ul -# define SRC_LINEAR_EN 0x00000004ul -# define SRC_BYTE_ALIGN 0x00000008ul -# define SRC_LINE_X_DIR 0x00000010ul -# define SRC_8X8X8_BRUSH 0x00000020ul /* VTB/GTB */ -# define FAST_FILL_EN 0x00000040ul /* VTB/GTB */ -# define SRC_TRACK_DST 0x00000080ul /* VTB/GTB */ -# define BUS_MASTER_EN 0x00000100ul /* VTB/GTB */ -# define BUS_MASTER_SYNC 0x00000200ul /* VTB/GTB */ -# define BUS_MASTER_OP 0x00000c00ul /* VTB/GTB */ -# define BM_OP_FRAME_TO_SYSTEM (0 << 10) -# define BM_OP_SYSTEM_TO_FRAME (1 << 10) -# define BM_OP_REG_TO_SYSTEM (2 << 10) -# define BM_OP_SYSTEM_TO_REG (3 << 10) -# define SRC_8X8X8_BRUSH_LOADED 0x00001000ul /* VTB/GTB */ -# define COLOR_REG_WRITE_EN 0x00002000ul /* VTB/GTB */ -# define BLOCK_WRITE_EN 0x00004000ul /* VTB/GTB */ -/* ? 0xffff8000ul */ -/* ? BlockIOTag(0x6eu) */ -/* ? BlockIOTag(0x6fu) */ -#define SCALE_Y_OFF BlockIOTag(0x70u) /* GT */ -#define SCALE_OFF BlockIOTag(0x70u) /* GTPro */ -#define SECONDARY_SCALE_OFF BlockIOTag(0x70u) /* GTPro */ -#define TEX_0_OFF BlockIOTag(0x70u) /* GT */ -#define TEX_1_OFF BlockIOTag(0x71u) /* GT */ -#define TEX_2_OFF BlockIOTag(0x72u) /* GT */ -#define TEX_3_OFF BlockIOTag(0x73u) /* GT */ -#define TEX_4_OFF BlockIOTag(0x74u) /* GT */ -#define TEX_5_OFF BlockIOTag(0x75u) /* GT */ -#define TEX_6_OFF BlockIOTag(0x76u) /* GT */ -#define SCALE_WIDTH BlockIOTag(0x77u) /* GT */ -#define TEX_7_OFF BlockIOTag(0x77u) /* GT */ -#define SCALE_HEIGHT BlockIOTag(0x78u) /* GT */ -#define TEX_8_OFF BlockIOTag(0x78u) /* GT */ -#define TEX_9_OFF BlockIOTag(0x79u) /* GT */ -#define TEX_10_OFF BlockIOTag(0x7au) /* GT */ -#define S_Y_INC BlockIOTag(0x7bu) /* GT */ -#define SCALE_Y_PITCH BlockIOTag(0x7bu) /* GT */ -#define SCALE_X_INC BlockIOTag(0x7cu) /* GT */ -#define RED_X_INC BlockIOTag(0x7cu) /* GT */ -#define GREEN_X_INC BlockIOTag(0x7du) /* GT */ -#define SCALE_Y_INC BlockIOTag(0x7du) /* GT */ -#define SCALE_VACC BlockIOTag(0x7eu) /* GT */ -#define SCALE_3D_CNTL BlockIOTag(0x7fu) /* GT */ -#define HOST_DATA_0 BlockIOTag(0x80u) -#define HOST_DATA_1 BlockIOTag(0x81u) -#define HOST_DATA_2 BlockIOTag(0x82u) -#define HOST_DATA_3 BlockIOTag(0x83u) -#define HOST_DATA_4 BlockIOTag(0x84u) -#define HOST_DATA_5 BlockIOTag(0x85u) -#define HOST_DATA_6 BlockIOTag(0x86u) -#define HOST_DATA_7 BlockIOTag(0x87u) -#define HOST_DATA_8 BlockIOTag(0x88u) -#define HOST_DATA_9 BlockIOTag(0x89u) -#define HOST_DATA_A BlockIOTag(0x8au) -#define HOST_DATA_B BlockIOTag(0x8bu) -#define HOST_DATA_C BlockIOTag(0x8cu) -#define HOST_DATA_D BlockIOTag(0x8du) -#define HOST_DATA_E BlockIOTag(0x8eu) -#define HOST_DATA_F BlockIOTag(0x8fu) -#define HOST_CNTL BlockIOTag(0x90u) -#define HOST_BYTE_ALIGN 0x00000001ul -#define HOST_BIG_ENDIAN_EN 0x00000002ul /* GX-E/CT */ -/* ? 0xfffffffcul */ -#define BM_HOSTDATA BlockIOTag(0x91u) /* VTB/GTB */ -#define BM_ADDR BlockIOTag(0x92u) /* VTB/GTB */ -#define BM_DATA BlockIOTag(0x92u) /* VTB/GTB */ -#define BM_GUI_TABLE_CMD BlockIOTag(0x93u) /* GTPro */ -# define CIRCULAR_BUF_SIZE_16KB (0 << 0) -# define CIRCULAR_BUF_SIZE_32KB (1 << 0) -# define CIRCULAR_BUF_SIZE_64KB (2 << 0) -# define CIRCULAR_BUF_SIZE_128KB (3 << 0) -# define LAST_DESCRIPTOR (1 << 31) -/* ? BlockIOTag(0x94u) */ -/* ? BlockIOTag(0x95u) */ -/* ? BlockIOTag(0x96u) */ -/* ? BlockIOTag(0x97u) */ -/* ? BlockIOTag(0x98u) */ -/* ? BlockIOTag(0x99u) */ -/* ? BlockIOTag(0x9au) */ -/* ? BlockIOTag(0x9bu) */ -/* ? BlockIOTag(0x9cu) */ -/* ? BlockIOTag(0x9du) */ -/* ? BlockIOTag(0x9eu) */ -/* ? BlockIOTag(0x9fu) */ -#define PAT_REG0 BlockIOTag(0xa0u) -#define PAT_REG1 BlockIOTag(0xa1u) -#define PAT_CNTL BlockIOTag(0xa2u) -#define PAT_MONO_EN 0x00000001ul -#define PAT_CLR_4x2_EN 0x00000002ul -#define PAT_CLR_8x1_EN 0x00000004ul -/* ? 0xfffffff8ul */ -/* ? BlockIOTag(0xa3u) */ -/* ? BlockIOTag(0xa4u) */ -/* ? BlockIOTag(0xa5u) */ -/* ? BlockIOTag(0xa6u) */ -/* ? BlockIOTag(0xa7u) */ -#define SC_LEFT BlockIOTag(0xa8u) -#define SC_RIGHT BlockIOTag(0xa9u) -#define SC_LEFT_RIGHT BlockIOTag(0xaau) -#define SC_TOP BlockIOTag(0xabu) -#define SC_BOTTOM BlockIOTag(0xacu) -#define SC_TOP_BOTTOM BlockIOTag(0xadu) -#define USR1_DST_OFF_PITCH BlockIOTag(0xaeu) /* LTPro */ -#define USR2_DST_OFF_PITCH BlockIOTag(0xafu) /* LTPro */ -#define DP_BKGD_CLR BlockIOTag(0xb0u) -#define DP_FRGD_CLR BlockIOTag(0xb1u) -#define DP_WRITE_MASK BlockIOTag(0xb2u) -#define DP_CHAIN_MASK BlockIOTag(0xb3u) -#define DP_CHAIN_1BPP 0x00000000ul /* Irrelevant */ -#define DP_CHAIN_4BPP 0x00008888ul -#define DP_CHAIN_8BPP 0x00008080ul -#define DP_CHAIN_8BPP_332 0x00009292ul -#define DP_CHAIN_15BPP_1555 0x00004210ul -#define DP_CHAIN_16BPP_565 0x00008410ul -#define DP_CHAIN_24BPP_888 0x00008080ul -#define DP_CHAIN_32BPP_8888 0x00008080ul -/* ? 0xffff0000ul */ -#define DP_PIX_WIDTH BlockIOTag(0xb4u) -#define DP_DST_PIX_WIDTH 0x0000000ful -#define COMPOSITE_PIX_WIDTH 0x000000f0ul /* GTPro */ -#define DP_SRC_PIX_WIDTH 0x00000f00ul -/* ? 0x00001000ul */ -#define DP_HOST_TRIPLE_EN 0x00002000ul /* GT2c/VT4 */ -#define DP_SRC_AUTONA_FIX_DIS 0x00004000ul /* GTB */ -#define DP_FAST_SRCCOPY_DIS 0x00008000ul /* GTB */ -#define DP_HOST_PIX_WIDTH 0x000f0000ul -#define DP_CI4_RGB_INDEX 0x00f00000ul /* GTB */ -#define DP_BYTE_PIX_ORDER 0x01000000ul -#define DP_CONVERSION_TEMP 0x02000000ul /* GTB */ -#define DP_CI4_RGB_LOW_NIBBLE 0x04000000ul /* GTB */ -#define DP_C14_RGB_HIGH_NIBBLE 0x08000000ul /* GTB */ -#define DP_SCALE_PIX_WIDTH 0xf0000000ul /* GTB */ -#define DP_MIX BlockIOTag(0xb5u) -# define BKGD_MIX_NOT_D (0 << 0) -# define BKGD_MIX_ZERO (1 << 0) -# define BKGD_MIX_ONE (2 << 0) -# define BKGD_MIX_D (3 << 0) -# define BKGD_MIX_NOT_S (4 << 0) -# define BKGD_MIX_D_XOR_S (5 << 0) -# define BKGD_MIX_NOT_D_XOR_S (6 << 0) -# define BKGD_MIX_S (7 << 0) -# define BKGD_MIX_NOT_D_OR_NOT_S (8 << 0) -# define BKGD_MIX_D_OR_NOT_S (9 << 0) -# define BKGD_MIX_NOT_D_OR_S (10 << 0) -# define BKGD_MIX_D_OR_S (11 << 0) -# define BKGD_MIX_D_AND_S (12 << 0) -# define BKGD_MIX_NOT_D_AND_S (13 << 0) -# define BKGD_MIX_D_AND_NOT_S (14 << 0) -# define BKGD_MIX_NOT_D_AND_NOT_S (15 << 0) -# define BKGD_MIX_D_PLUS_S_DIV2 (23 << 0) -# define FRGD_MIX_NOT_D (0 << 16) -# define FRGD_MIX_ZERO (1 << 16) -# define FRGD_MIX_ONE (2 << 16) -# define FRGD_MIX_D (3 << 16) -# define FRGD_MIX_NOT_S (4 << 16) -# define FRGD_MIX_D_XOR_S (5 << 16) -# define FRGD_MIX_NOT_D_XOR_S (6 << 16) -# define FRGD_MIX_S (7 << 16) -# define FRGD_MIX_NOT_D_OR_NOT_S (8 << 16) -# define FRGD_MIX_D_OR_NOT_S (9 << 16) -# define FRGD_MIX_NOT_D_OR_S (10 << 16) -# define FRGD_MIX_D_OR_S (11 << 16) -# define FRGD_MIX_D_AND_S (12 << 16) -# define FRGD_MIX_NOT_D_AND_S (13 << 16) -# define FRGD_MIX_D_AND_NOT_S (14 << 16) -# define FRGD_MIX_NOT_D_AND_NOT_S (15 << 16) -# define FRGD_MIX_D_PLUS_S_DIV2 (23 << 16) -#define DP_SRC BlockIOTag(0xb6u) -# define BKGD_SRC_BKGD_CLR (0 << 0) -# define BKGD_SRC_FRGD_CLR (1 << 0) -# define BKGD_SRC_HOST (2 << 0) -# define BKGD_SRC_BLIT (3 << 0) -# define BKGD_SRC_PATTERN (4 << 0) -# define BKGD_SRC_3D (5 << 0) -# define FRGD_SRC_BKGD_CLR (0 << 8) -# define FRGD_SRC_FRGD_CLR (1 << 8) -# define FRGD_SRC_HOST (2 << 8) -# define FRGD_SRC_BLIT (3 << 8) -# define FRGD_SRC_PATTERN (4 << 8) -# define FRGD_SRC_3D (5 << 8) -# define MONO_SRC_ONE (0 << 16) -# define MONO_SRC_PATTERN (1 << 16) -# define MONO_SRC_HOST (2 << 16) -# define MONO_SRC_BLIT (3 << 16) -#define DP_FRGD_CLR_MIX BlockIOTag(0xb7u) /* VTB/GTB */ -#define DP_FRGD_BKGD_CLR BlockIOTag(0xb8u) /* VTB/GTB */ -/* ? BlockIOTag(0xb9u) */ -#define DST_X_Y BlockIOTag(0xbau) /* VTB/GTB */ -#define DST_WIDTH_HEIGHT BlockIOTag(0xbbu) /* VTB/GTB */ -#define USR_DST_PITCH BlockIOTag(0xbcu) /* GTPro */ -/* ? BlockIOTag(0xbdu) */ -#define DP_SET_GUI_ENGINE2 BlockIOTag(0xbeu) /* GTPro */ -#define DP_SET_GUI_ENGINE BlockIOTag(0xbfu) /* VTB/GTB */ -#define CLR_CMP_CLR BlockIOTag(0xc0u) -#define CLR_CMP_MSK BlockIOTag(0xc1u) -#define CLR_CMP_CNTL BlockIOTag(0xc2u) -#define CLR_CMP_FN 0x00000007ul -#define CLR_CMP_FN_FALSE 0x00000000ul -#define CLR_CMP_FN_TRUE 0x00000001ul -/* ? 0x00000002ul */ -/* ? 0x00000003ul */ -#define CLR_CMP_FN_NOT_EQUAL 0x00000004ul -#define CLR_CMP_FN_EQUAL 0x00000005ul -/* ? 0x00000006ul */ -/* ? 0x00000007ul */ -/* ? 0x00fffff8ul */ -#define CLR_CMP_SRC 0x03000000ul -#define CLR_CMP_SRC_DST 0x00000000ul -#define CLR_CMP_SRC_2D 0x01000000ul -#define CLR_CMP_SRC_TEXEL 0x02000000ul -/* ? 0x03000000ul */ -/* ? 0xfc000000ul */ -/* ? BlockIOTag(0xc3u) */ -#define FIFO_STAT BlockIOTag(0xc4u) -#define FIFO_STAT_BITS 0x0000fffful -/* ? 0x7fff0000ul */ -#define FIFO_ERR 0x80000000ul -/* ? BlockIOTag(0xc5u) */ -/* ? BlockIOTag(0xc6u) */ -/* ? BlockIOTag(0xc7u) */ -#define CONTEXT_MASK BlockIOTag(0xc8u) -/* ? BlockIOTag(0xc9u) */ -/* ? BlockIOTag(0xcau) */ -#define CONTEXT_LOAD_CNTL BlockIOTag(0xcbu) -#define CONTEXT_LOAD_PTR 0x00007ffful -/* ? 0x00008000ul */ -#define CONTEXT_LOAD_CMD 0x00030000ul -#define CONTEXT_LOAD_NONE 0x00000000ul -#define CONTEXT_LOAD_ONLY 0x00010000ul -#define CONTEXT_LOAD_FILL 0x00020000ul -#define CONTEXT_LOAD_LINE 0x00030000ul -/* ? 0x7ffc0000ul */ -#define CONTEXT_LOAD_DIS 0x80000000ul -#define GUI_TRAJ_CNTL BlockIOTag(0xccu) -/* ? BlockIOTag(0xcdu) */ -#define GUI_STAT BlockIOTag(0xceu) -#define GUI_ACTIVE 0x00000001ul -/* ? 0x000000feul */ -#define DSTX_LT_SCISSOR_LEFT 0x00000100ul -#define DSTX_GT_SCISSOR_RIGHT 0x00000200ul -#define DSTY_LT_SCISSOR_TOP 0x00000400ul -#define DSTY_GT_SCISSOR_BOTTOM 0x00000800ul -/* ? 0x0000f000ul */ -#define GUI_FIFO 0x03ff0000ul /* VTB/GTB */ -/* ? 0xfc000000ul */ -/* ? BlockIOTag(0xcfu) */ -#define S_X_INC2 BlockIOTag(0xd0u) /* GTB */ -#define TEX_PALETTE_INDEX BlockIOTag(0xd0u) /* GTPro */ -#define S_Y_INC2 BlockIOTag(0xd1u) /* GTB */ -#define STW_EXP BlockIOTag(0xd1u) /* GTPro */ -#define S_XY_INC2 BlockIOTag(0xd2u) /* GTB */ -#define LOG_MAX_INC BlockIOTag(0xd2u) /* GTPro */ -#define S_XINC_START BlockIOTag(0xd3u) /* GTB */ -/* S_Y_INC BlockIOTag(0xd4u) */ /* Duplicate */ -/* SCALE_Y_PITCH BlockIOTag(0xd4u) */ /* Duplicate */ -#define S_START BlockIOTag(0xd5u) /* GTB */ -#define T_X_INC2 BlockIOTag(0xd6u) /* GTB */ -#define W_X_INC BlockIOTag(0xd6u) /* GTPro */ -#define T_Y_INC2 BlockIOTag(0xd7u) /* GTB */ -#define W_Y_INC BlockIOTag(0xd7u) /* GTPro */ -#define T_XY_INC2 BlockIOTag(0xd8u) /* GTB */ -#define W_START BlockIOTag(0xd8u) /* GTPro */ -#define T_XINC_START BlockIOTag(0xd9u) /* GTB */ -#define T_Y_INC BlockIOTag(0xdau) /* GTB */ -#define SECONDARY_SCALE_PITCH BlockIOTag(0xdau) /* GTPro */ -#define T_START BlockIOTag(0xdbu) /* GTB */ -#define TEX_SIZE_PITCH BlockIOTag(0xdcu) /* GTB */ -#define TEX_CNTL BlockIOTag(0xddu) /* GTPro */ -#define SECONDARY_TEX_OFFSET BlockIOTag(0xdeu) /* GTPro */ -#define TEX_PAL_WR BlockIOTag(0xdfu) /* GTB */ -#define TEX_PALETTE BlockIOTag(0xdfu) /* GTPro */ -#define SCALE_PITCH_BOTH BlockIOTag(0xe0u) /* GTPro */ -#define SECONDARY_SCALE_OFF_ACC BlockIOTag(0xe1u) /* GTPro */ -#define SCALE_OFF_ACC BlockIOTag(0xe2u) /* GTPro */ -#define SCALE_DST_Y_X BlockIOTag(0xe3u) /* GTPro */ -/* ? BlockIOTag(0xe4u) */ -/* ? BlockIOTag(0xe5u) */ -#define COMPOSITE_SHADOW_ID BlockIOTag(0xe6u) /* GTPro */ -#define SECONDARY_SCALE_X_INC BlockIOTag(0xe7u) /* GTPro */ -#define SPECULAR_RED_X_INC BlockIOTag(0xe7u) /* GTPro */ -#define SPECULAR_RED_Y_INC BlockIOTag(0xe8u) /* GTPro */ -#define SPECULAR_RED_START BlockIOTag(0xe9u) /* GTPro */ -#define SECONDARY_SCALE_HACC BlockIOTag(0xe9u) /* GTPro */ -#define SPECULAR_GREEN_X_INC BlockIOTag(0xeau) /* GTPro */ -#define SPECULAR_GREEN_Y_INC BlockIOTag(0xebu) /* GTPro */ -#define SPECULAR_GREEN_START BlockIOTag(0xecu) /* GTPro */ -#define SPECULAR_BLUE_X_INC BlockIOTag(0xedu) /* GTPro */ -#define SPECULAR_BLUE_Y_INC BlockIOTag(0xeeu) /* GTPro */ -#define SPECULAR_BLUE_START BlockIOTag(0xefu) /* GTPro */ -/* SCALE_X_INC BlockIOTag(0xf0u) */ /* Duplicate */ -/* RED_X_INC BlockIOTag(0xf0u) */ /* Duplicate */ -#define RED_Y_INC BlockIOTag(0xf1u) /* GTB */ -#define SCALE_HACC BlockIOTag(0xf2u) /* GTB */ -#define RED_START BlockIOTag(0xf2u) /* GTB */ -/* GREEN_X_INC BlockIOTag(0xf3u) */ /* Duplicate */ -/* SCALE_Y_INC BlockIOTag(0xf3u) */ /* Duplicate */ -#define GREEN_Y_INC BlockIOTag(0xf4u) /* GTB */ -#define SECONDARY_SCALE_Y_INC BlockIOTag(0xf4u) /* GTPro */ -#define SECONDARY_SCALE_VACC BlockIOTag(0xf5u) /* GTPro */ -#define GREEN_START BlockIOTag(0xf5u) /* GTB */ -#define BLUE_X_INC BlockIOTag(0xf6u) /* GTB */ -#define SCALE_XUV_INC BlockIOTag(0xf6u) /* GTB */ -#define BLUE_Y_INC BlockIOTag(0xf7u) /* GTB */ -#define BLUE_START BlockIOTag(0xf8u) /* GTB */ -#define SCALE_UV_HACC BlockIOTag(0xf8u) /* GTB */ -#define Z_X_INC BlockIOTag(0xf9u) /* GTB */ -#define Z_Y_INC BlockIOTag(0xfau) /* GTB */ -#define Z_START BlockIOTag(0xfbu) /* GTB */ -#define ALPHA_FOG_X_INC BlockIOTag(0xfcu) /* GTB */ -#define ALPHA_FOG_Y_INC BlockIOTag(0xfdu) /* GTB */ -#define ALPHA_FOG_START BlockIOTag(0xfeu) /* GTB */ -/* ? BlockIOTag(0xffu) */ -#define OVERLAY_Y_X_START BlockIOTag(0x100u) -#define OVERLAY_Y_X_END BlockIOTag(0x101u) -#define OVERLAY_VIDEO_KEY_CLR BlockIOTag(0x102u) -#define OVERLAY_VIDEO_KEY_MSK BlockIOTag(0x103u) -#define OVERLAY_GRAPHICS_KEY_CLR BlockIOTag(0x104u) -#define OVERLAY_GRAPHICS_KEY_MSK BlockIOTag(0x105u) -#define OVERLAY_KEY_CNTL BlockIOTag(0x106u) -# define VIDEO_KEY_FN_MASK 0x00000007L -# define VIDEO_KEY_FN_FALSE 0x00000000L -# define VIDEO_KEY_FN_TRUE 0x00000001L -# define VIDEO_KEY_FN_NE 0x00000004L -# define VIDEO_KEY_FN_EQ 0x00000005L // EQ and NE are exchanged relative to radeon -# define GRAPHIC_KEY_FN_MASK 0x00000070L -# define GRAPHIC_KEY_FN_FALSE 0x00000000L -# define GRAPHIC_KEY_FN_TRUE 0x00000010L -# define GRAPHIC_KEY_FN_NE 0x00000040L -# define GRAPHIC_KEY_FN_EQ 0x00000050L // EQ and NE are exchanged relative to radeon -# define CMP_MIX_MASK 0x00000100L -# define CMP_MIX_OR 0x00000000L -# define CMP_MIX_AND 0x00000100L -/* ? BlockIOTag(0x107u) */ -#define OVERLAY_SCALE_INC BlockIOTag(0x108u) -#define OVERLAY_SCALE_CNTL BlockIOTag(0x109u) -#define SCALER_HEIGHT_WIDTH BlockIOTag(0x10au) -#define OVERLAY_TEST BlockIOTag(0x10bu) -#define SCALER_THRESHOLD BlockIOTag(0x10cu) -#define SCALER_BUF0_OFFSET BlockIOTag(0x10du) /* VTB/GTB */ -#define SCALER_BUF1_OFFSET BlockIOTag(0x10eu) /* VTB/GTB */ -#define SCALER_BUF_PITCH BlockIOTag(0x10fu) /* VTB/GTB */ -#define CAPTURE_Y_X BlockIOTag(0x110u) -#define CAPTURE_START_END BlockIOTag(0x110u) /* VTB/GTB */ -#define CAPTURE_HEIGHT_WIDTH BlockIOTag(0x111u) -#define CAPTURE_X_WIDTH BlockIOTag(0x111u) /* VTB/GTB */ -#define VIDEO_FORMAT BlockIOTag(0x112u) -#define VIDEO_CONFIG BlockIOTag(0x113u) -#define VBI_START_END BlockIOTag(0x113u) /* VTB/GTB */ -#define CAPTURE_CONFIG BlockIOTag(0x114u) -#define TRIG_CNTL BlockIOTag(0x115u) -#define VIDEO_SYNC_TEST BlockIOTag(0x116u) -#define OVERLAY_EXCLUSIVE_HORZ BlockIOTag(0x116u) /* VTB/GTB */ -#define EXT_CRTC_GEN_CNTL_R BlockIOTag(0x117u) /* VT-A4 (R) */ -#define OVERLAY_EXCLUSIVE_VERT BlockIOTag(0x117u) /* VTB/GTB */ -#define VMC_CONFIG BlockIOTag(0x118u) -#define VBI_WIDTH BlockIOTag(0x118u) /* VTB/GTB */ -#define VMC_STATUS BlockIOTag(0x119u) -#define CAPTURE_DEBUG BlockIOTag(0x119u) /* VTB/GTB */ -#define VMC_CMD BlockIOTag(0x11au) -#define VIDEO_SYNC_TEST_B BlockIOTag(0x11au) /* VTB/GTB */ -#define VMC_ARG0 BlockIOTag(0x11bu) -#define VMC_ARG1 BlockIOTag(0x11cu) -#define SNAPSHOT_VH_COUNTS BlockIOTag(0x11cu) /* GTPro */ -#define VMC_SNOOP_ARG0 BlockIOTag(0x11du) -#define SNAPSHOT_F_COUNT BlockIOTag(0x11du) /* GTPro */ -#define VMC_SNOOP_ARG1 BlockIOTag(0x11eu) -#define N_VIF_COUNT BlockIOTag(0x11eu) /* GTPro */ -#define SNAPSHOT_VIF_COUNT BlockIOTag(0x11fu) /* GTPro */ -#define BUF0_OFFSET BlockIOTag(0x120u) -#define CAPTURE_BUF0_OFFSET BlockIOTag(0x120u) /* VTB/GTB */ -#define CAPTURE_BUF1_OFFSET BlockIOTag(0x121u) /* VTB/GTB */ -#define ONESHOT_BUF_OFFSET BlockIOTag(0x122u) /* VTB/GTB */ -#define BUF0_PITCH BlockIOTag(0x123u) -/* ? BlockIOTag(0x124u) */ -/* ? BlockIOTag(0x125u) */ -#define BUF1_OFFSET BlockIOTag(0x126u) -/* ? BlockIOTag(0x127u) */ -/* ? BlockIOTag(0x128u) */ -#define BUF1_PITCH BlockIOTag(0x129u) -/* ? BlockIOTag(0x12au) */ -#define BUF0_CAP_ODD_OFFSET BlockIOTag(0x12bu) -#define BUF1_CAP_ODD_OFFSET BlockIOTag(0x12cu) -#define SNAPSHOT2_VH_COUNTS BlockIOTag(0x12cu) /* LTPro */ -#define SNAPSHOT2_F_COUNT BlockIOTag(0x12du) /* LTPro */ -#define N_VIF2_COUNT BlockIOTag(0x12eu) /* LTPro */ -#define SNAPSHOT2_VIF_COUNT BlockIOTag(0x12fu) /* LTPro */ -#define VMC_STRM_DATA_0 BlockIOTag(0x130u) -/* MPP_CONFIG BlockIOTag(0x130u) */ /* See 0x3bu */ -#define VMC_STRM_DATA_1 BlockIOTag(0x131u) -/* MPP_STROBE_SEQ BlockIOTag(0x131u) */ /* See 0x3cu */ -#define VMC_STRM_DATA_2 BlockIOTag(0x132u) -/* MPP_ADDR BlockIOTag(0x132u) */ /* See 0x3du */ -#define VMC_STRM_DATA_3 BlockIOTag(0x133u) -/* MPP_DATA BlockIOTag(0x133u) */ /* See 0x3eu */ -#define VMC_STRM_DATA_4 BlockIOTag(0x134u) -#define VMC_STRM_DATA_5 BlockIOTag(0x135u) -#define VMC_STRM_DATA_6 BlockIOTag(0x136u) -#define VMC_STRM_DATA_7 BlockIOTag(0x137u) -#define VMC_STRM_DATA_8 BlockIOTag(0x138u) -#define VMC_STRM_DATA_9 BlockIOTag(0x139u) -#define VMC_STRM_DATA_A BlockIOTag(0x13au) -#define VMC_STRM_DATA_B BlockIOTag(0x13bu) -#define VMC_STRM_DATA_C BlockIOTag(0x13cu) -#define VMC_STRM_DATA_D BlockIOTag(0x13du) -#define VMC_STRM_DATA_E BlockIOTag(0x13eu) -#define VMC_STRM_DATA_F BlockIOTag(0x13fu) -/* TVO_CNTL BlockIOTag(0x140u) */ /* See 0x3fu */ -/* ? BlockIOTag(0x141u) */ -/* ? BlockIOTag(0x142u) */ -/* ? BlockIOTag(0x143u) */ -/* ? BlockIOTag(0x144u) */ -/* ? BlockIOTag(0x145u) */ -/* ? BlockIOTag(0x146u) */ -/* ? BlockIOTag(0x147u) */ -/* ? BlockIOTag(0x148u) */ -/* ? BlockIOTag(0x149u) */ -/* ? BlockIOTag(0x14au) */ -/* ? BlockIOTag(0x14bu) */ -/* ? BlockIOTag(0x14cu) */ -/* ? BlockIOTag(0x14du) */ -/* ? BlockIOTag(0x14eu) */ -/* ? BlockIOTag(0x14fu) */ -/* ? BlockIOTag(0x150u) */ -#define CRT_HORZ_VERT_LOAD BlockIOTag(0x151u) /* VTB/GTB */ -#define AGP_BASE BlockIOTag(0x152u) /* GTPro */ -#define AGP_CNTL BlockIOTag(0x153u) /* GTPro */ -#define SCALER_COLOUR_CNTL BlockIOTag(0x154u) /* GTPro */ -#define SCALER_H_COEFF0 BlockIOTag(0x155u) /* GTPro */ -#define SCALER_H_COEFF1 BlockIOTag(0x156u) /* GTPro */ -#define SCALER_H_COEFF2 BlockIOTag(0x157u) /* GTPro */ -#define SCALER_H_COEFF3 BlockIOTag(0x158u) /* GTPro */ -#define SCALER_H_COEFF4 BlockIOTag(0x159u) /* GTPro */ -/* ? BlockIOTag(0x15au) */ -/* ? BlockIOTag(0x15bu) */ -#define GUI_CMDFIFO_DEBUG BlockIOTag(0x15cu) /* GT2c/VT4 */ -#define GUI_CMDFIFO_DATA BlockIOTag(0x15du) /* GT2c/VT4 */ -#define GUI_CNTL BlockIOTag(0x15eu) /* GT2c/VT4 */ -# define CMDFIFO_SIZE_MASK 0x00000003ul -# define CMDFIFO_SIZE_192 0x00000000ul -# define CMDFIFO_SIZE_128 0x00000001ul -# define CMDFIFO_SIZE_64 0x00000002ul -/* ? 0x0000fffcul */ -# define IDCT_PRSR_MODE 0x00010000ul /* XL/XC */ -# define IDCT_BLOCK_GUI_INITIATOR 0x00020000ul /* XL/XC */ -/* ? 0xfffc0000ul */ -/* ? BlockIOTag(0x15fu) */ -/* BUS MASTERING */ -#define BM_FRAME_BUF_OFFSET BlockIOTag(0x160u) /* VTB/GTB */ -#define BM_SYSTEM_MEM_ADDR BlockIOTag(0x161u) /* VTB/GTB */ -#define BM_COMMAND BlockIOTag(0x162u) /* VTB/GTB */ -#define BM_STATUS BlockIOTag(0x163u) /* VTB/GTB */ -/* ? BlockIOTag(0x164u) */ -/* ? BlockIOTag(0x165u) */ -/* ? BlockIOTag(0x166u) */ -/* ? BlockIOTag(0x167u) */ -/* ? BlockIOTag(0x168u) */ -/* ? BlockIOTag(0x169u) */ -/* ? BlockIOTag(0x16au) */ -/* ? BlockIOTag(0x16bu) */ -/* ? BlockIOTag(0x16cu) */ -/* ? BlockIOTag(0x16du) */ -#define BM_GUI_TABLE BlockIOTag(0x16eu) /* VTB/GTB */ -#define BM_SYSTEM_TABLE BlockIOTag(0x16fu) /* VTB/GTB */ -# define DMA_GUI_COMMAND__BYTE_COUNT_MASK 0x001fffff -# define DMA_GUI_COMMAND__HOLD_VIDEO_OFFSET 0x40000000 -# define DMA_GUI_COMMAND__EOL 0x80000000 -# define SYSTEM_TRIGGER_SYSTEM_TO_VIDEO 0x0 -# define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM 0x1 -# define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM_AFTER_BUF0_READY 0x2 -# define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM_AFTER_BUF1_READY 0x3 -# define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM_AFTER_SNAPSHOT_READY 0x4 -/* ? BlockIOTag(0x170u) */ -/* ? BlockIOTag(0x171u) */ -/* ? BlockIOTag(0x172u) */ -/* ? BlockIOTag(0x173u) */ -/* ? BlockIOTag(0x174u) */ -#define SCALER_BUF0_OFFSET_V BlockIOTag(0x175u) /* GTPro */ -#define SCALER_BUF0_OFFSET_U BlockIOTag(0x176u) /* GTPro */ -#define SCALER_BUF1_OFFSET_V BlockIOTag(0x177u) /* GTPro */ -#define SCALER_BUF1_OFFSET_U BlockIOTag(0x178u) /* GTPro */ -/* ? BlockIOTag(0x179u) */ -/* ? BlockIOTag(0x17au) */ -/* ? BlockIOTag(0x17bu) */ -/* ? BlockIOTag(0x17cu) */ -/* ? BlockIOTag(0x17du) */ -/* ? BlockIOTag(0x17eu) */ -/* ? BlockIOTag(0x17fu) */ -/* ? BlockIOTag(0x180u) */ -/* ? BlockIOTag(0x181u) */ -/* ? BlockIOTag(0x182u) */ -/* ? BlockIOTag(0x183u) */ -/* ? BlockIOTag(0x184u) */ -/* ? BlockIOTag(0x185u) */ -/* ? BlockIOTag(0x186u) */ -/* ? BlockIOTag(0x187u) */ -/* ? BlockIOTag(0x188u) */ -/* ? BlockIOTag(0x189u) */ -/* ? BlockIOTag(0x18au) */ -/* ? BlockIOTag(0x18bu) */ -/* ? BlockIOTag(0x18cu) */ -/* ? BlockIOTag(0x18du) */ -/* ? BlockIOTag(0x18eu) */ -/* ? BlockIOTag(0x18fu) */ -#define VERTEX_1_S BlockIOTag(0x190u) /* GTPro */ -#define VERTEX_1_T BlockIOTag(0x191u) /* GTPro */ -#define VERTEX_1_W BlockIOTag(0x192u) /* GTPro */ -#define VERTEX_1_SPEC_ARGB BlockIOTag(0x193u) /* GTPro */ -#define VERTEX_1_Z BlockIOTag(0x194u) /* GTPro */ -#define VERTEX_1_ARGB BlockIOTag(0x195u) /* GTPro */ -#define VERTEX_1_X_Y BlockIOTag(0x196u) /* GTPro */ -#define ONE_OVER_AREA BlockIOTag(0x197u) /* GTPro */ -#define VERTEX_2_S BlockIOTag(0x198u) /* GTPro */ -#define VERTEX_2_T BlockIOTag(0x199u) /* GTPro */ -#define VERTEX_2_W BlockIOTag(0x19au) /* GTPro */ -#define VERTEX_2_SPEC_ARGB BlockIOTag(0x19bu) /* GTPro */ -#define VERTEX_2_Z BlockIOTag(0x19cu) /* GTPro */ -#define VERTEX_2_ARGB BlockIOTag(0x19du) /* GTPro */ -#define VERTEX_2_X_Y BlockIOTag(0x19eu) /* GTPro */ -/* ONE_OVER_AREA BlockIOTag(0x19fu) */ /* Duplicate */ -#define VERTEX_3_S BlockIOTag(0x1a0u) /* GTPro */ -#define VERTEX_3_T BlockIOTag(0x1a1u) /* GTPro */ -#define VERTEX_3_W BlockIOTag(0x1a2u) /* GTPro */ -#define VERTEX_3_SPEC_ARGB BlockIOTag(0x1a3u) /* GTPro */ -#define VERTEX_3_Z BlockIOTag(0x1a4u) /* GTPro */ -#define VERTEX_3_ARGB BlockIOTag(0x1a5u) /* GTPro */ -#define VERTEX_3_X_Y BlockIOTag(0x1a6u) /* GTPro */ -/* ONE_OVER_AREA BlockIOTag(0x1a7u) */ /* Duplicate */ -#define VERTEX_3_SECONDARY_S BlockIOTag(0x1a8u) /* GTPro */ -#define VERTEX_3_SECONDARY_T BlockIOTag(0x1a9u) /* GTPro */ -#define VERTEX_3_SECONDARY_W BlockIOTag(0x1aau) /* GTPro */ -/* VERTEX_1_S BlockIOTag(0x1abu) */ /* Duplicate */ -/* VERTEX_1_T BlockIOTag(0x1acu) */ /* Duplicate */ -/* VERTEX_1_W BlockIOTag(0x1adu) */ /* Duplicate */ -/* VERTEX_2_S BlockIOTag(0x1aeu) */ /* Duplicate */ -/* VERTEX_2_T BlockIOTag(0x1afu) */ /* Duplicate */ -/* VERTEX_2_W BlockIOTag(0x1b0u) */ /* Duplicate */ -/* VERTEX_3_S BlockIOTag(0x1b1u) */ /* Duplicate */ -/* VERTEX_3_T BlockIOTag(0x1b2u) */ /* Duplicate */ -/* VERTEX_3_W BlockIOTag(0x1b3u) */ /* Duplicate */ -/* VERTEX_1_SPEC_ARGB BlockIOTag(0x1b4u) */ /* Duplicate */ -/* VERTEX_2_SPEC_ARGB BlockIOTag(0x1b5u) */ /* Duplicate */ -/* VERTEX_3_SPEC_ARGB BlockIOTag(0x1b6u) */ /* Duplicate */ -/* VERTEX_1_Z BlockIOTag(0x1b7u) */ /* Duplicate */ -/* VERTEX_2_Z BlockIOTag(0x1b8u) */ /* Duplicate */ -/* VERTEX_3_Z BlockIOTag(0x1b9u) */ /* Duplicate */ -/* VERTEX_1_ARGB BlockIOTag(0x1bau) */ /* Duplicate */ -/* VERTEX_2_ARGB BlockIOTag(0x1bbu) */ /* Duplicate */ -/* VERTEX_3_ARGB BlockIOTag(0x1bcu) */ /* Duplicate */ -/* VERTEX_1_X_Y BlockIOTag(0x1bdu) */ /* Duplicate */ -/* VERTEX_2_X_Y BlockIOTag(0x1beu) */ /* Duplicate */ -/* VERTEX_3_X_Y BlockIOTag(0x1bfu) */ /* Duplicate */ -#define ONE_OVER_AREA_UC BlockIOTag(0x1c0u) /* GTPro */ -#define SETUP_CNTL BlockIOTag(0x1c1u) /* GTPro */ -/* ? BlockIOTag(0x1c2u) */ -/* ? BlockIOTag(0x1c3u) */ -/* ? BlockIOTag(0x1c4u) */ -/* ? BlockIOTag(0x1c5u) */ -/* ? BlockIOTag(0x1c6u) */ -/* ? BlockIOTag(0x1c7u) */ -/* ? BlockIOTag(0x1c8u) */ -/* ? BlockIOTag(0x1c9u) */ -#define VERTEX_1_SECONDARY_S BlockIOTag(0x1cau) /* GTPro */ -#define VERTEX_1_SECONDARY_T BlockIOTag(0x1cbu) /* GTPro */ -#define VERTEX_1_SECONDARY_W BlockIOTag(0x1ccu) /* GTPro */ -#define VERTEX_2_SECONDARY_S BlockIOTag(0x1cdu) /* GTPro */ -#define VERTEX_2_SECONDARY_T BlockIOTag(0x1ceu) /* GTPro */ -#define VERTEX_2_SECONDARY_W BlockIOTag(0x1cfu) /* GTPro */ -/* ? BlockIOTag(0x1d0u) */ -/* ? BlockIOTag(0x1d1u) */ -/* ? BlockIOTag(0x1d2u) */ -/* ? BlockIOTag(0x1d3u) */ -/* ? BlockIOTag(0x1d4u) */ -/* ? BlockIOTag(0x1d5u) */ -/* ? BlockIOTag(0x1d6u) */ -/* ? BlockIOTag(0x1d7u) */ -/* ? BlockIOTag(0x1d8u) */ -/* ? BlockIOTag(0x1d9u) */ -/* ? BlockIOTag(0x1dau) */ -/* ? BlockIOTag(0x1dbu) */ -/* ? BlockIOTag(0x1dcu) */ -/* ? BlockIOTag(0x1ddu) */ -/* ? BlockIOTag(0x1deu) */ -/* ? BlockIOTag(0x1dfu) */ -/* ? BlockIOTag(0x1e0u) */ -/* ? BlockIOTag(0x1e1u) */ -/* ? BlockIOTag(0x1e2u) */ -/* ? BlockIOTag(0x1e3u) */ -/* ? BlockIOTag(0x1e4u) */ -/* ? BlockIOTag(0x1e5u) */ -/* ? BlockIOTag(0x1e6u) */ -/* ? BlockIOTag(0x1e7u) */ -/* ? BlockIOTag(0x1e8u) */ -/* ? BlockIOTag(0x1e9u) */ -/* ? BlockIOTag(0x1eau) */ -/* ? BlockIOTag(0x1ebu) */ -/* ? BlockIOTag(0x1ecu) */ -/* ? BlockIOTag(0x1edu) */ -/* ? BlockIOTag(0x1eeu) */ -/* ? BlockIOTag(0x1efu) */ -/* ? BlockIOTag(0x1f0u) */ -/* ? BlockIOTag(0x1f1u) */ -/* ? BlockIOTag(0x1f2u) */ -/* ? BlockIOTag(0x1f3u) */ -/* ? BlockIOTag(0x1f4u) */ -/* ? BlockIOTag(0x1f5u) */ -/* ? BlockIOTag(0x1f6u) */ -/* ? BlockIOTag(0x1f7u) */ -/* ? BlockIOTag(0x1f8u) */ -/* ? BlockIOTag(0x1f9u) */ -/* ? BlockIOTag(0x1fau) */ -/* ? BlockIOTag(0x1fbu) */ -/* ? BlockIOTag(0x1fcu) */ -/* ? BlockIOTag(0x1fdu) */ -/* ? BlockIOTag(0x1feu) */ -/* ? BlockIOTag(0x1ffu) */ - -/* Definitions for MEM_CNTL's CTL_MEM_?????_APER_ENDIAN fields */ -#define CTL_MEM_APER_BYTE_ENDIAN 0x00u -#define CTL_MEM_APER_WORD_ENDIAN 0x01u -#define CTL_MEM_APER_LONG_ENDIAN 0x02u -/* ? 0x03u */ - -/* Definitions for an ICS2595's programme word */ -#define ICS2595_CLOCK 0x000001f0ul -#define ICS2595_FB_DIV 0x0001fe00ul /* Feedback divider */ -#define ICS2595_POST_DIV 0x000c0000ul /* Post-divider */ -#define ICS2595_STOP 0x00300000ul /* Stop bits */ -#define ICS2595_TOGGLE (ICS2595_POST_DIV | ICS2595_STOP) - -/* Definitions for internal PLL registers on a 264xT */ -#define PLL_MPLL_CNTL 0x00u -#define MPLL_PC_GAIN 0x07u -#define MPLL_VC_GAIN 0x18u -#define MPLL_D_CYC 0x60u -#define MPLL_RANGE 0x80u -#define VPLL_CNTL 0x01u -#define VPLL_PC_GAIN 0x07u -#define VPLL_VC_GAIN 0x18u -#define VPLL_D_CYC 0x60u -#define VPLL_RANGE 0x80u -#define PLL_REF_DIV 0x02u -#define PLL_GEN_CNTL 0x03u -#define PLL_OVERRIDE 0x01u -#define PLL_SLEEP 0x01u /* GTPro */ -#define PLL_MCLK_RESET 0x02u -#define PLL_OSC_EN 0x04u -#define PLL_EXT_CLK_EN 0x08u -#define PLL_MCLK_SRC_SEL 0x70u -#define PLL_EXT_CLK_CNTL 0x80u /* CT/ET */ -#define PLL_DLL_PWDN 0x80u /* VTB/GTB/LT */ -#define PLL_MCLK_FB_DIV 0x04u -#define PLL_VCLK_CNTL 0x05u -#define PLL_VCLK_SRC_SEL 0x03u -#define PLL_VCLK_RESET 0x04u -#define PLL_VCLK_INVERT 0x08u -#define PLL_ECP_DIV 0x30u /* VT/GT */ -#define PLL_ERATE_GT_XRATE 0x40u /* VT/GT */ -#define PLL_SCALER_LOCK_EN 0x80u /* VT/GT */ -#define PLL_VCLK_POST_DIV 0x06u -#define PLL_VCLK0_POST_DIV 0x03u -#define PLL_VCLK1_POST_DIV 0x0cu -#define PLL_VCLK2_POST_DIV 0x30u -#define PLL_VCLK3_POST_DIV 0xc0u -#define PLL_VCLK0_FB_DIV 0x07u -#define PLL_VCLK1_FB_DIV 0x08u -#define PLL_VCLK2_FB_DIV 0x09u -#define PLL_VCLK3_FB_DIV 0x0au -#define PLL_XCLK_CNTL 0x0bu /* VT/GT */ -#define PLL_XCLK_MCLK_RATIO 0x03u -#define PLL_XCLK_SRC_SEL 0x07u /* VTB/GTB/LT */ -#define PLL_MFB_TIMES_4_2B 0x08u -#define PLL_VCLK0_XDIV 0x10u -#define PLL_VCLK1_XDIV 0x20u -#define PLL_VCLK2_XDIV 0x40u -#define PLL_VCLK3_XDIV 0x80u -#define PLL_FCP_CNTL 0x0cu /* VT/GT */ -#define PLL_FCP_POST_DIV 0x0fu -#define PLL_FCP_SRC_SEL 0x70u -#define PLL_DCLK_BY2_EN 0x80u -#define PLL_DLL_CNTL 0x0cu /* VTB/GTB/LT */ -#define PLL_DLL_REF_SRC 0x03u -#define PLL_DLL_FB_SRC 0x0cu -#define PLL_DLL_GAIN 0x30u -#define PLL_DLL_RESET 0x40u -#define PLL_DLL_HCLK_OUT_EN 0x80u -#define PLL_VFC_CNTL 0x0du /* VT/GT */ -#define PLL_DCLK_INVB 0x01u -#define PLL_DCLKBY2_EN 0x02u -#define PLL_VFC_2PHASE 0x04u -#define PLL_VFC_DELAY 0x18u -#define PLL_VFC_DCLKBY2_SHIFT 0x20u -/* ? 0x40u */ -#define PLL_TST_SRC_SEL_BIT5 0x80u /* VTB/GTB/LT */ -#define PLL_TEST_CNTL 0x0eu -#define PLL_TST_SRC_SEL 0x1fu -#define PLL_TST_DIVIDERS 0x20u -#define PLL_TST_MASK_READ 0x40u -#define PLL_TST_ANALOG_MON_EN 0x80u -#define PLL_TEST_COUNT 0x0fu -#define PLL_LVDSPLL_CNTL0 0x10u /* LT */ -#define PLL_FPDI_NS_TIMING 0x01u -#define PLL_CURR_LEVEL 0x0eu -#define PLL_LVDS_TEST_MODE 0xf0u -#define PLL_LVDSPLL_CNTL1 0x11u /* LT */ -#define PLL_LPPL_RANGE 0x01u -#define PLL_LPLL_DUTY 0x06u -#define PLL_LPLL_VC_GAIN 0x18u -#define PLL_LPLL_CP_GAIN 0xe0u -#define PLL_AGP1_CNTL 0x12u /* GTPro */ -#define PLL_AGP2_CNTL 0x13u /* GTPro */ -#define PLL_DLL2_CNTL 0x14u /* GTPro */ -#define PLL_SCLK_FB_DIV 0x15u /* GTPro */ -#define PLL_SPLL_CNTL1 0x16u /* GTPro */ -#define PLL_SPLL_CNTL2 0x17u /* GTPro */ -#define PLL_APLL_STRAPS 0x18u /* GTPro */ -#define PLL_EXT_VPLL_CNTL 0x19u /* GTPro */ -#define PLL_EXT_VPLL_REF_SRC 0x03u -#define PLL_EXT_VPLL_EN 0x04u -#define PLL_EXT_VPLL_VGA_EN 0x08u -#define PLL_EXT_VPLL_INSYNC 0x10u -/* ? 0x60u */ -#define PLL_EXT_V2PLL_EN 0x80u -#define PLL_EXT_VPLL_REF_DIV 0x1au /* GTPro */ -#define PLL_EXT_VPLL_FB_DIV 0x1bu /* GTPro */ -#define PLL_EXT_VPLL_MSB 0x1cu /* GTPro */ -#define PLL_HTOTAL_CNTL 0x1du /* GTPro */ -#define PLL_BYTE_CLK_CNTL 0x1eu /* GTPro */ -#define PLL_TV_REF_DIV 0x1fu /* LTPro */ -#define PLL_TV_FB_DIV 0x20u /* LTPro */ -#define PLL_TV_CNTL 0x21u /* LTPro */ -#define PLL_TV_GEN_CNTL 0x22u /* LTPro */ -#define PLL_V2_CNTL 0x23u /* LTPro */ -#define PLL_V2_GEN_CNTL 0x24u /* LTPro */ -#define PLL_V2_REF_DIV 0x25u /* LTPro */ -#define PLL_V2_FB_DIV 0x26u /* LTPro */ -#define PLL_V2_MSB 0x27u /* LTPro */ -#define PLL_HTOTAL2_CNTL 0x28u /* LTPro */ -#define PLL_YCLK_CNTL 0x29u /* XC/XL */ -#define PM_DYN_CLK_CNTL 0x2au /* XC/XL */ -/* ? 0x2bu */ -/* ? 0x2cu */ -/* ? 0x2du */ -/* ? 0x2eu */ -/* ? 0x2fu */ -/* ? 0x30u */ -/* ? 0x31u */ -/* ? 0x32u */ -/* ? 0x33u */ -/* ? 0x34u */ -/* ? 0x35u */ -/* ? 0x36u */ -/* ? 0x37u */ -/* ? 0x38u */ -/* ? 0x39u */ -/* ? 0x3au */ -/* ? 0x3bu */ -/* ? 0x3cu */ -/* ? 0x3du */ -/* ? 0x3eu */ -/* ? 0x3fu */ - -/* Definitions for an LTPro's 32-bit LCD registers */ -#define LCD_CONFIG_PANEL 0x00u /* See LT's CONFIG_PANEL (0x1d) */ -#define LCD_GEN_CNTL 0x01u /* See LT's LCD_GEN_CTRL (0x35) */ -#define LCD_DSTN_CONTROL 0x02u /* See LT's DSTN_CONTROL (0x1f) */ -#define LCD_HFB_PITCH_ADDR 0x03u /* See LT's HFB_PITCH_ADDR (0x2a) */ -#define LCD_HORZ_STRETCHING 0x04u /* See LT's HORZ_STRETCHING (0x32) */ -#define LCD_VERT_STRETCHING 0x05u /* See LT's VERT_STRETCHING (0x33) */ -#define LCD_EXT_VERT_STRETCH 0x06u -#define VERT_STRETCH_RATIO3 0x000003fful -#define FORCE_DAC_DATA 0x000000fful -#define FORCE_DAC_DATA_SEL 0x00000300ul -#define VERT_STRETCH_MODE 0x00000400ul -#define VERT_PANEL_SIZE 0x003ff800ul -#define AUTO_VERT_RATIO 0x00400000ul -#define USE_AUTO_FP_POS 0x00800000ul -#define USE_AUTO_LCD_VSYNC 0x01000000ul -/* ? 0xfe000000ul */ -#define LCD_LT_GIO 0x07u /* See LT's LT_GIO (0x2f) */ -#define LCD_POWER_MANAGEMENT 0x08u /* See LT's POWER_MANAGEMENT (0x36) */ -#define LCD_ZVGPIO 0x09u -#define LCD_ICON_CLR0 0x0au /* XC/XL */ -#define LCD_ICON_CLR1 0x0bu /* XC/XL */ -#define LCD_ICON_OFFSET 0x0cu /* XC/XL */ -#define LCD_ICON_HORZ_VERT_POSN 0x0du /* XC/XL */ -#define LCD_ICON_HORZ_VERT_OFF 0x0eu /* XC/XL */ -#define LCD_ICON2_CLR0 0x0fu /* XC/XL */ -#define LCD_ICON2_CLR1 0x10u /* XC/XL */ -#define LCD_ICON2_OFFSET 0x11u /* XC/XL */ -#define LCD_ICON2_HORZ_VERT_POSN 0x12u /* XC/XL */ -#define LCD_ICON2_HORZ_VERT_OFF 0x13u /* XC/XL */ -#define LCD_MISC_CNTL 0x14u /* XC/XL */ -#define BL_MOD_LEVEL 0x000000fful -#define BIAS_MOD_LEVEL 0x0000ff00ul -#define BLMOD_EN 0x00010000ul -#define BIASMOD_EN 0x00020000ul -/* ? 0x00040000ul */ -#define PWRSEQ_MODE 0x00080000ul -#define APC_EN 0x00100000ul -#define MONITOR_DET_EN 0x00200000ul -#define FORCE_DAC_DATA_SEL_X 0x00c00000ul -#define FORCE_DAC_DATA_X 0xff000000ul -#define LCD_TMDS_CNTL 0x15u /* XC/XL */ -#define LCD_TMDS_SYNC_CHAR_SETA 0x16u /* XC/XL */ -#define LCD_TMDS_SYNC_CHAR_SETB 0x17u /* XC/XL */ -#define LCD_TMDS_SRC 0x18u /* XC/XL */ -#define LCD_PLTSTBLK_CNTL 0x19u /* XC/XL */ -#define LCD_SYNC_GEN_CNTL 0x1au /* XC/XL */ -#define LCD_PATTERN_GEN_SEED 0x1bu /* XC/XL */ -#define LCD_APC_CNTL 0x1cu /* XC/XL */ -#define LCD_POWER_MANAGEMENT_2 0x1du /* XC/XL */ -#define LCD_XCLK_DISP_PM_EN 0x00000001ul -#define LCD_XCLK_DISP2_PM_EN 0x00000002ul /* Mobility */ -#define LCD_XCLK_VID_PM_EN 0x00000004ul -#define LCD_XCLK_SCL_PM_EN 0x00000008ul -#define LCD_XCLK_GUI_PM_EN 0x00000010ul -#define LCD_XCLK_SUB_PM_EN 0x00000020ul -/* ? 0x000000c0ul */ -#define LCD_MCLK_PM_EN 0x00000100ul -#define LCD_SS_EN 0x00000200ul -#define LCD_BLON_DIGON_EN 0x00000400ul -/* ? 0x00000800ul */ -#define LCD_PM_DYN_XCLK_SYNC 0x00003000ul -#define LCD_SEL_W4MS 0x00004000ul -/* ? 0x00008000ul */ -#define LCD_PM_DYN_XCLK_EN 0x00010000ul -#define LCD_PM_XCLK_ALWAYS 0x00020000ul -#define LCD_PM_DYN_XCLK_STATUS 0x00040000ul -#define LCD_PCI_ACC_DIS 0x00080000ul -#define LCD_PM_DYN_XCLK_DISP 0x00100000ul -#define LCD_PM_DYN_XCLK_DISP2 0x00200000ul /* Mobility */ -#define LCD_PM_DYN_XCLK_VID 0x00400000ul -#define LCD_PM_DYN_XCLK_HFB 0x00800000ul -#define LCD_PM_DYN_XCLK_SCL 0x01000000ul -#define LCD_PM_DYN_XCLK_SUB 0x02000000ul -#define LCD_PM_DYN_XCLK_GUI 0x04000000ul -#define LCD_PM_DYN_XCLK_HOST 0x08000000ul -/* ? 0xf0000000ul */ -#define LCD_PRI_ERR_PATTERN 0x1eu /* XC/XL */ -#define LCD_CUR_ERR_PATTERN 0x1fu /* XC/XL */ -#define LCD_PLTSTBLK_RPT 0x20u /* XC/XL */ -#define LCD_SYNC_RPT 0x21u /* XC/XL */ -#define LCD_CRC_PATTERN_RPT 0x22u /* XC/XL */ -#define LCD_PL_TRANSMITTER_CNTL 0x23u /* XC/XL */ -#define LCD_PL_PLL_CNTL 0x24u /* XC/XL */ -#define LCD_ALPHA_BLENDING 0x25u /* XC/XL */ -#define LCD_PORTRAIT_GEN_CNTL 0x26u /* XC/XL */ -#define LCD_APC_CTRL_IO 0x27u /* XC/XL */ -#define LCD_TEST_IO 0x28u /* XC/XL */ -/* ? 0x29u */ -#define LCD_DP1_MEM_ACCESS 0x2au /* XC/XL */ -#define LCD_DP0_MEM_ACCESS 0x2bu /* XC/XL */ -#define LCD_DP0_DEBUG_A 0x2cu /* XC/XL */ -#define LCD_DP0_DEBUG_B 0x2du /* XC/XL */ -#define LCD_DP1_DEBUG_A 0x2eu /* XC/XL */ -#define LCD_DP1_DEBUG_B 0x2fu /* XC/XL */ -#define LCD_DPCTRL_DEBUG_A 0x30u /* XC/XL */ -#define LCD_DPCTRL_DEBUG_B 0x31u /* XC/XL */ -#define LCD_MEMBLK_DEBUG 0x32u /* XC/XL */ -#define LCD_APC_LUT_AB 0x33u /* XC/XL */ -#define LCD_APC_LUT_CD 0x34u /* XC/XL */ -#define LCD_APC_LUT_EF 0x35u /* XC/XL */ -#define LCD_APC_LUT_GH 0x36u /* XC/XL */ -#define LCD_APC_LUT_IJ 0x37u /* XC/XL */ -#define LCD_APC_LUT_KL 0x38u /* XC/XL */ -#define LCD_APC_LUT_MN 0x39u /* XC/XL */ -#define LCD_APC_LUT_OP 0x3au /* XC/XL */ -/* ? 0x3bu */ -/* ? 0x3cu */ -/* ? 0x3du */ -/* ? 0x3eu */ -/* ? 0x3fu */ - -/* Definitions for an LTPro's TV registers */ -/* ? 0x00u */ -/* ? 0x01u */ -/* ? 0x02u */ -/* ? 0x03u */ -/* ? 0x04u */ -/* ? 0x05u */ -/* ? 0x06u */ -/* ? 0x07u */ -/* ? 0x08u */ -/* ? 0x09u */ -/* ? 0x0au */ -/* ? 0x0bu */ -/* ? 0x0cu */ -/* ? 0x0du */ -/* ? 0x0eu */ -/* ? 0x0fu */ -#define TV_MASTER_CNTL 0x10u -/* ? 0x11u */ -#define TV_RGB_CNTL 0x12u -/* ? 0x13u */ -#define TV_SYNC_CNTL 0x14u -/* ? 0x15u */ -/* ? 0x16u */ -/* ? 0x17u */ -/* ? 0x18u */ -/* ? 0x19u */ -/* ? 0x1au */ -/* ? 0x1bu */ -/* ? 0x1cu */ -/* ? 0x1du */ -/* ? 0x1eu */ -/* ? 0x1fu */ -#define TV_HTOTAL 0x20u -#define TV_HDISP 0x21u -#define TV_HSIZE 0x22u -#define TV_HSTART 0x23u -#define TV_HCOUNT 0x24u -#define TV_VTOTAL 0x25u -#define TV_VDISP 0x26u -#define TV_VCOUNT 0x27u -#define TV_FTOTAL 0x28u -#define TV_FCOUNT 0x29u -#define TV_FRESTART 0x2au -#define TV_HRESTART 0x2bu -#define TV_VRESTART 0x2cu -/* ? 0x2du */ -/* ? 0x2eu */ -/* ? 0x2fu */ -/* ? 0x30u */ -/* ? 0x31u */ -/* ? 0x32u */ -/* ? 0x33u */ -/* ? 0x34u */ -/* ? 0x35u */ -/* ? 0x36u */ -/* ? 0x37u */ -/* ? 0x38u */ -/* ? 0x39u */ -/* ? 0x3au */ -/* ? 0x3bu */ -/* ? 0x3cu */ -/* ? 0x3du */ -/* ? 0x3eu */ -/* ? 0x3fu */ -/* ? 0x40u */ -/* ? 0x41u */ -/* ? 0x42u */ -/* ? 0x43u */ -/* ? 0x44u */ -/* ? 0x45u */ -/* ? 0x46u */ -/* ? 0x47u */ -/* ? 0x48u */ -/* ? 0x49u */ -/* ? 0x4au */ -/* ? 0x4bu */ -/* ? 0x4cu */ -/* ? 0x4du */ -/* ? 0x4eu */ -/* ? 0x4fu */ -/* ? 0x50u */ -/* ? 0x51u */ -/* ? 0x52u */ -/* ? 0x53u */ -/* ? 0x54u */ -/* ? 0x55u */ -/* ? 0x56u */ -/* ? 0x57u */ -/* ? 0x58u */ -/* ? 0x59u */ -/* ? 0x5au */ -/* ? 0x5bu */ -/* ? 0x5cu */ -/* ? 0x5du */ -/* ? 0x5eu */ -/* ? 0x5fu */ -#define TV_HOST_READ_DATA 0x60u -#define TV_HOST_WRITE_DATA 0x61u -#define TV_HOST_RD_WT_CNTL 0x62u -/* ? 0x63u */ -/* ? 0x64u */ -/* ? 0x65u */ -/* ? 0x66u */ -/* ? 0x67u */ -/* ? 0x68u */ -/* ? 0x69u */ -/* ? 0x6au */ -/* ? 0x6bu */ -/* ? 0x6cu */ -/* ? 0x6du */ -/* ? 0x6eu */ -/* ? 0x6fu */ -#define TV_VSCALER_CNTL 0x70u -#define TV_TIMING_CNTL 0x71u -#define TV_GAMMA_CNTL 0x72u -#define TV_Y_FALL_CNTL 0x73u -#define TV_Y_RISE_CNTL 0x74u -#define TV_Y_SAW_TOOTH_CNTL 0x75u -/* ? 0x76u */ -/* ? 0x77u */ -/* ? 0x78u */ -/* ? 0x79u */ -/* ? 0x7au */ -/* ? 0x7bu */ -/* ? 0x7cu */ -/* ? 0x7du */ -/* ? 0x7eu */ -/* ? 0x7fu */ -#define TV_MODULATOR_CNTL1 0x80u -#define TV_MODULATOR_CNTL2 0x81u -/* ? 0x82u */ -/* ? 0x83u */ -/* ? 0x84u */ -/* ? 0x85u */ -/* ? 0x86u */ -/* ? 0x87u */ -/* ? 0x88u */ -/* ? 0x89u */ -/* ? 0x8au */ -/* ? 0x8bu */ -/* ? 0x8cu */ -/* ? 0x8du */ -/* ? 0x8eu */ -/* ? 0x8fu */ -#define TV_PRE_DAC_MUX_CNTL 0x90u -/* ? 0x91u */ -/* ? 0x92u */ -/* ? 0x93u */ -/* ? 0x94u */ -/* ? 0x95u */ -/* ? 0x96u */ -/* ? 0x97u */ -/* ? 0x98u */ -/* ? 0x99u */ -/* ? 0x9au */ -/* ? 0x9bu */ -/* ? 0x9cu */ -/* ? 0x9du */ -/* ? 0x9eu */ -/* ? 0x9fu */ -#define TV_DAC_CNTL 0xa0u -/* ? 0xa1u */ -/* ? 0xa2u */ -/* ? 0xa3u */ -/* ? 0xa4u */ -/* ? 0xa5u */ -/* ? 0xa6u */ -/* ? 0xa7u */ -/* ? 0xa8u */ -/* ? 0xa9u */ -/* ? 0xaau */ -/* ? 0xabu */ -/* ? 0xacu */ -/* ? 0xadu */ -/* ? 0xaeu */ -/* ? 0xafu */ -#define TV_CRC_CNTL 0xb0u -#define TV_VIDEO_PORT_SIG 0xb1u -/* ? 0xb2u */ -/* ? 0xb3u */ -/* ? 0xb4u */ -/* ? 0xb5u */ -/* ? 0xb6u */ -/* ? 0xb7u */ -#define TV_VBI_CC_CNTL 0xb8u -#define TV_VBI_EDS_CNTL 0xb9u -#define TV_VBI_20BIT_CNTL 0xbau -/* ? 0xbbu */ -/* ? 0xbcu */ -#define TV_VBI_DTO_CNTL 0xbdu -#define TV_VBI_LEVEL_CNTL 0xbeu -/* ? 0xbfu */ -#define TV_UV_ADR 0xc0u -#define TV_FIFO_TEST_CNTL 0xc1u -/* ? 0xc2u */ -/* ? 0xc3u */ -/* ? 0xc4u */ -/* ? 0xc5u */ -/* ? 0xc6u */ -/* ? 0xc7u */ -/* ? 0xc8u */ -/* ? 0xc9u */ -/* ? 0xcau */ -/* ? 0xcbu */ -/* ? 0xccu */ -/* ? 0xcdu */ -/* ? 0xceu */ -/* ? 0xcfu */ -/* ? 0xd0u */ -/* ? 0xd1u */ -/* ? 0xd2u */ -/* ? 0xd3u */ -/* ? 0xd4u */ -/* ? 0xd5u */ -/* ? 0xd6u */ -/* ? 0xd7u */ -/* ? 0xd8u */ -/* ? 0xd9u */ -/* ? 0xdau */ -/* ? 0xdbu */ -/* ? 0xdcu */ -/* ? 0xddu */ -/* ? 0xdeu */ -/* ? 0xdfu */ -/* ? 0xe0u */ -/* ? 0xe1u */ -/* ? 0xe2u */ -/* ? 0xe3u */ -/* ? 0xe4u */ -/* ? 0xe5u */ -/* ? 0xe6u */ -/* ? 0xe7u */ -/* ? 0xe8u */ -/* ? 0xe9u */ -/* ? 0xeau */ -/* ? 0xebu */ -/* ? 0xecu */ -/* ? 0xedu */ -/* ? 0xeeu */ -/* ? 0xefu */ -/* ? 0xf0u */ -/* ? 0xf1u */ -/* ? 0xf2u */ -/* ? 0xf3u */ -/* ? 0xf4u */ -/* ? 0xf5u */ -/* ? 0xf6u */ -/* ? 0xf7u */ -/* ? 0xf8u */ -/* ? 0xf9u */ -/* ? 0xfau */ -/* ? 0xfbu */ -/* ? 0xfcu */ -/* ? 0xfdu */ -/* ? 0xfeu */ -/* ? 0xffu */ - -/* Miscellaneous */ - -/* Current X, Y & Dest X, Y mask */ -#define COORD_MASK 0x07ffu - -/* Pixel widths */ -#define PIX_WIDTH_1BPP 0x00u -#define PIX_WIDTH_4BPP 0x01u /* CRTC2: 8bpp */ -#define PIX_WIDTH_8BPP 0x02u /* CRTC2: Undefined */ -#define PIX_WIDTH_15BPP 0x03u -#define PIX_WIDTH_16BPP 0x04u -#define PIX_WIDTH_24BPP 0x05u -#define PIX_WIDTH_32BPP 0x06u -#define PIX_WIDTH_YUV422 0x07u /* CRTC2 only */ - -/* Source definitions */ -#define SRC_BKGD 0x00u -#define SRC_FRGD 0x01u -#define SRC_HOST 0x02u -#define SRC_BLIT 0x03u -#define SRC_PATTERN 0x04u -#define SRC_SCALER_3D 0x05u -/* ? 0x06u */ -/* ? 0x07u */ - -/* The Mixes */ -#define MIX_MASK 0x001fu - -#define MIX_NOT_DST 0x0000u -#define MIX_0 0x0001u -#define MIX_1 0x0002u -#define MIX_DST 0x0003u -#define MIX_NOT_SRC 0x0004u -#define MIX_XOR 0x0005u -#define MIX_XNOR 0x0006u -#define MIX_SRC 0x0007u -#define MIX_NAND 0x0008u -#define MIX_NOT_SRC_OR_DST 0x0009u -#define MIX_SRC_OR_NOT_DST 0x000au -#define MIX_OR 0x000bu -#define MIX_AND 0x000cu -#define MIX_SRC_AND_NOT_DST 0x000du -#define MIX_NOT_SRC_AND_DST 0x000eu -#define MIX_NOR 0x000fu - -#define MIX_MIN 0x0010u -#define MIX_DST_MINUS_SRC 0x0011u -#define MIX_SRC_MINUS_DST 0x0012u -#define MIX_PLUS 0x0013u -#define MIX_MAX 0x0014u -#define MIX_HALF__DST_MINUS_SRC 0x0015u -#define MIX_HALF__SRC_MINUS_DST 0x0016u -#define MIX_AVERAGE 0x0017u -#define MIX_DST_MINUS_SRC_SAT 0x0018u -#define MIX_SRC_MINUS_DST_SAT 0x001au -#define MIX_HALF__DST_MINUS_SRC_SAT 0x001cu -#define MIX_HALF__SRC_MINUS_DST_SAT 0x001eu -#define MIX_AVERAGE_SAT 0x001fu -#define MIX_FN_PAINT MIX_SRC - - -#endif
--- a/vidix/drivers/mach64_vid.c Sat Mar 31 23:48:48 2007 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1066 +0,0 @@ -/* - mach64_vid - VIDIX based video driver for Mach64 and 3DRage chips - Copyrights 2002 Nick Kurshev. This file is based on sources from - GATOS (gatos.sf.net) and X11 (www.xfree86.org) - Licence: GPL - WARNING: THIS DRIVER IS IN BETTA STAGE -*/ -#include <errno.h> -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include <math.h> -#include <inttypes.h> -#include <fcntl.h> - -#include "../../config.h" -#include "../../libavutil/common.h" -#include "../../mpbswap.h" -#include "../vidix.h" -#include "../fourcc.h" -#include "../../libdha/libdha.h" -#include "../../libdha/pci_ids.h" -#include "../../libdha/pci_names.h" - -#include "mach64.h" -#include "../../version.h" - -#define UNUSED(x) ((void)(x)) /**< Removes warning about unused arguments */ - -static void *mach64_mmio_base = 0; -static void *mach64_mem_base = 0; -static int32_t mach64_overlay_offset = 0; -static uint32_t mach64_ram_size = 0; -static uint32_t mach64_buffer_base[10][3]; -static int num_mach64_buffers=-1; -static int supports_planar=0; -static int supports_lcd_v_stretch=0; - -pciinfo_t pci_info; -static int probed = 0; -static int __verbose = 0; - -#define VERBOSE_LEVEL 1 - -typedef struct bes_registers_s -{ - /* base address of yuv framebuffer */ - uint32_t yuv_base; - uint32_t fourcc; - /* YUV BES registers */ - uint32_t reg_load_cntl; - uint32_t scale_inc; - uint32_t y_x_start; - uint32_t y_x_end; - uint32_t vid_buf_pitch; - uint32_t height_width; - - uint32_t scale_cntl; - uint32_t exclusive_horz; - uint32_t auto_flip_cntl; - uint32_t filter_cntl; - uint32_t key_cntl; - uint32_t test; - /* Configurable stuff */ - - int brightness; - int saturation; - - int ckey_on; - uint32_t graphics_key_clr; - uint32_t graphics_key_msk; - - int deinterlace_on; - uint32_t deinterlace_pattern; - -} bes_registers_t; - -static bes_registers_t besr; - -typedef struct video_registers_s -{ - const char * sname; - uint32_t name; - uint32_t value; -}video_registers_t; - -static bes_registers_t besr; - -/* Graphic keys */ -static vidix_grkey_t mach64_grkey; - -#define DECLARE_VREG(name) { #name, name, 0 } -static video_registers_t vregs[] = -{ - DECLARE_VREG(OVERLAY_SCALE_INC), - DECLARE_VREG(OVERLAY_Y_X_START), - DECLARE_VREG(OVERLAY_Y_X_END), - DECLARE_VREG(OVERLAY_SCALE_CNTL), - DECLARE_VREG(OVERLAY_EXCLUSIVE_HORZ), - DECLARE_VREG(OVERLAY_EXCLUSIVE_VERT), - DECLARE_VREG(OVERLAY_TEST), - DECLARE_VREG(SCALER_BUF_PITCH), - DECLARE_VREG(SCALER_HEIGHT_WIDTH), - DECLARE_VREG(SCALER_BUF0_OFFSET), - DECLARE_VREG(SCALER_BUF0_OFFSET_U), - DECLARE_VREG(SCALER_BUF0_OFFSET_V), - DECLARE_VREG(SCALER_BUF1_OFFSET), - DECLARE_VREG(SCALER_BUF1_OFFSET_U), - DECLARE_VREG(SCALER_BUF1_OFFSET_V), - DECLARE_VREG(SCALER_H_COEFF0), - DECLARE_VREG(SCALER_H_COEFF1), - DECLARE_VREG(SCALER_H_COEFF2), - DECLARE_VREG(SCALER_H_COEFF3), - DECLARE_VREG(SCALER_H_COEFF4), - DECLARE_VREG(SCALER_COLOUR_CNTL), - DECLARE_VREG(SCALER_THRESHOLD), - DECLARE_VREG(VIDEO_FORMAT), - DECLARE_VREG(VIDEO_CONFIG), - DECLARE_VREG(VIDEO_SYNC_TEST), - DECLARE_VREG(VIDEO_SYNC_TEST_B) -}; - -/* have to restore it on exit */ -static uint32_t SAVED_OVERLAY_GRAPHICS_KEY_CLR; - -/* VIDIX exports */ - -/* MMIO space*/ -#define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ)))) -#define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL - -#define INREG8(addr) GETREG(uint8_t,(uint8_t *)mach64_mmio_base,((addr)^0x100)<<2) -#define OUTREG8(addr,val) SETREG(uint8_t,(uint8_t *)mach64_mmio_base,((addr)^0x100)<<2,val) - -static inline uint32_t INREG (uint32_t addr) { - uint32_t tmp = GETREG(uint32_t,(uint8_t *)mach64_mmio_base,((addr)^0x100)<<2); - return le2me_32(tmp); -} -#define OUTREG(addr,val) SETREG(uint32_t,(uint8_t *)mach64_mmio_base,((addr)^0x100)<<2,le2me_32(val)) - -#define OUTREGP(addr,val,mask) \ - do { \ - unsigned int _tmp = INREG(addr); \ - _tmp &= (mask); \ - _tmp |= (val); \ - OUTREG(addr, _tmp); \ - } while (0) - -static __inline__ int ATIGetMach64LCDReg(int _Index) -{ - OUTREG8(LCD_INDEX, _Index); - return INREG(LCD_DATA); -} - -static __inline__ uint32_t INPLL(uint32_t addr) -{ - uint32_t res; - uint32_t in; - - in= INREG(CLOCK_CNTL); - in &= ~((PLL_WR_EN | PLL_ADDR)); //clean some stuff - OUTREG(CLOCK_CNTL, in | (addr<<10)); - - /* read the register value */ - res = (INREG(CLOCK_CNTL)>>16)&0xFF; - return res; -} - -static __inline__ void OUTPLL(uint32_t addr,uint32_t val) -{ -//FIXME buggy but its not used - /* write addr byte */ - OUTREG8(CLOCK_CNTL + 1, (addr << 2) | PLL_WR_EN); - /* write the register value */ - OUTREG(CLOCK_CNTL + 2, val); - OUTREG8(CLOCK_CNTL + 1, (addr << 2) & ~PLL_WR_EN); -} - -#define OUTPLLP(addr,val,mask) \ - do { \ - unsigned int _tmp = INPLL(addr); \ - _tmp &= (mask); \ - _tmp |= (val); \ - OUTPLL(addr, _tmp); \ - } while (0) - -static void mach64_fifo_wait(unsigned n) -{ - while ((INREG(FIFO_STAT) & 0xffff) > ((uint32_t)(0x8000 >> n))); -} - -static void mach64_wait_for_idle( void ) -{ - mach64_fifo_wait(16); - while ((INREG(GUI_STAT) & 1)!= 0); -} - -static void mach64_wait_vsync( void ) -{ - int i; - - for(i=0; i<2000000; i++) - if( (INREG(CRTC_INT_CNTL)&CRTC_VBLANK)==0 ) break; - for(i=0; i<2000000; i++) - if( (INREG(CRTC_INT_CNTL)&CRTC_VBLANK) ) break; - -} - -static vidix_capability_t mach64_cap = -{ - "BES driver for Mach64/3DRage cards", - "Nick Kurshev and Michael Niedermayer", - TYPE_OUTPUT, - { 0, 0, 0, 0 }, - 2048, - 2048, - 4, - 4, - -1, - FLAG_UPSCALER|FLAG_DOWNSCALER, - VENDOR_ATI, - -1, - { 0, 0, 0, 0 } -}; - -static uint32_t mach64_vid_get_dbpp( void ) -{ - uint32_t dbpp,retval; - dbpp = (INREG(CRTC_GEN_CNTL)>>8)& 0x7; - switch(dbpp) - { - case 1: retval = 4; break; - case 2: retval = 8; break; - case 3: retval = 15; break; - case 4: retval = 16; break; - case 5: retval = 24; break; - default: retval=32; break; - } - return retval; -} - -static int mach64_is_dbl_scan( void ) -{ - return INREG(CRTC_GEN_CNTL) & CRTC_DBL_SCAN_EN; -} - -static int mach64_is_interlace( void ) -{ - return INREG(CRTC_GEN_CNTL) & CRTC_INTERLACE_EN; -} - -static uint32_t mach64_get_xres( void ) -{ - /* FIXME: currently we extract that from CRTC!!!*/ - uint32_t xres,h_total; - h_total = INREG(CRTC_H_TOTAL_DISP); - xres = (h_total >> 16) & 0xffff; - return (xres + 1)*8; -} - -static uint32_t mach64_get_yres( void ) -{ - /* FIXME: currently we extract that from CRTC!!!*/ - uint32_t yres,v_total; - v_total = INREG(CRTC_V_TOTAL_DISP); - yres = (v_total >> 16) & 0xffff; - return yres + 1; -} - -// returns the verical stretch factor in 16.16 -static int mach64_get_vert_stretch(void) -{ - int lcd_index; - int vert_stretching; - int ext_vert_stretch; - int ret; - int yres= mach64_get_yres(); - - if(!supports_lcd_v_stretch){ - if(__verbose>0) printf("[mach64] vertical stretching not supported\n"); - return 1<<16; - } - - lcd_index= INREG(LCD_INDEX); - - vert_stretching= ATIGetMach64LCDReg(LCD_VERT_STRETCHING); - if(!(vert_stretching&VERT_STRETCH_EN)) ret= 1<<16; - else - { - int panel_size; - - ext_vert_stretch= ATIGetMach64LCDReg(LCD_EXT_VERT_STRETCH); - panel_size= (ext_vert_stretch&VERT_PANEL_SIZE)>>11; - panel_size++; - - ret= ((yres<<16) + (panel_size>>1))/panel_size; - } - -// lcd_gen_ctrl = ATIGetMach64LCDReg(LCD_GEN_CNTL); - - OUTREG(LCD_INDEX, lcd_index); - - if(__verbose>0) printf("[mach64] vertical stretching factor= %d\n", ret); - - return ret; -} - -static void mach64_vid_make_default(void) -{ - mach64_fifo_wait(5); - OUTREG(SCALER_COLOUR_CNTL,0x00101000); - - besr.ckey_on=0; - besr.graphics_key_msk=0; - besr.graphics_key_clr=0; - - OUTREG(OVERLAY_GRAPHICS_KEY_MSK, besr.graphics_key_msk); - OUTREG(OVERLAY_GRAPHICS_KEY_CLR, besr.graphics_key_clr); - OUTREG(OVERLAY_KEY_CNTL,VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_EQ|CMP_MIX_AND); - -} - -static void mach64_vid_dump_regs( void ) -{ - size_t i; - printf("[mach64] *** Begin of DRIVER variables dump ***\n"); - printf("[mach64] mach64_mmio_base=%p\n",mach64_mmio_base); - printf("[mach64] mach64_mem_base=%p\n",mach64_mem_base); - printf("[mach64] mach64_overlay_off=%08X\n",mach64_overlay_offset); - printf("[mach64] mach64_ram_size=%08X\n",mach64_ram_size); - printf("[mach64] video mode: %ux%u@%u\n",mach64_get_xres(),mach64_get_yres(),mach64_vid_get_dbpp()); - printf("[mach64] *** Begin of OV0 registers dump ***\n"); - for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) - { - mach64_wait_for_idle(); - printf("[mach64] %s = %08X\n",vregs[i].sname,INREG(vregs[i].name)); - } - printf("[mach64] *** End of OV0 registers dump ***\n"); -} - - -unsigned int vixGetVersion(void) -{ - return(VIDIX_VERSION); -} - -static unsigned short ati_card_ids[] = -{ - DEVICE_ATI_215CT_MACH64_CT, - DEVICE_ATI_210888CX_MACH64_CX, - DEVICE_ATI_210888ET_MACH64_ET, - DEVICE_ATI_MACH64_VT, - DEVICE_ATI_210888GX_MACH64_GX, - DEVICE_ATI_264LT_MACH64_LT, - DEVICE_ATI_264VT_MACH64_VT, - DEVICE_ATI_264VT3_MACH64_VT3, - DEVICE_ATI_264VT4_MACH64_VT4, - /**/ - DEVICE_ATI_3D_RAGE_PRO, - DEVICE_ATI_3D_RAGE_PRO2, - DEVICE_ATI_3D_RAGE_PRO3, - DEVICE_ATI_3D_RAGE_PRO4, - DEVICE_ATI_RAGE_XC, - DEVICE_ATI_RAGE_XL_AGP, - DEVICE_ATI_RAGE_XC_AGP, - DEVICE_ATI_RAGE_XL, - DEVICE_ATI_3D_RAGE_PRO5, - DEVICE_ATI_3D_RAGE_PRO6, - DEVICE_ATI_RAGE_XL2, - DEVICE_ATI_RAGE_XC2, - DEVICE_ATI_3D_RAGE_I_II, - DEVICE_ATI_3D_RAGE_II, - DEVICE_ATI_3D_RAGE_IIC, - DEVICE_ATI_3D_RAGE_IIC2, - DEVICE_ATI_3D_RAGE_IIC3, - DEVICE_ATI_3D_RAGE_IIC4, - DEVICE_ATI_3D_RAGE_LT, - DEVICE_ATI_3D_RAGE_LT2, - DEVICE_ATI_3D_RAGE_LT_G, - DEVICE_ATI_3D_RAGE_LT3, - DEVICE_ATI_RAGE_MOBILITY_P_M, - DEVICE_ATI_RAGE_MOBILITY_L, - DEVICE_ATI_3D_RAGE_LT4, - DEVICE_ATI_3D_RAGE_LT5, - DEVICE_ATI_RAGE_MOBILITY_P_M2, - DEVICE_ATI_RAGE_MOBILITY_L2 -}; - -static int find_chip(unsigned chip_id) -{ - unsigned i; - for(i = 0;i < sizeof(ati_card_ids)/sizeof(unsigned short);i++) - { - if(chip_id == ati_card_ids[i]) return i; - } - return -1; -} - -int vixProbe(int verbose,int force) -{ - pciinfo_t lst[MAX_PCI_DEVICES]; - unsigned i,num_pci; - int err; - __verbose = verbose; - err = pci_scan(lst,&num_pci); - if(err) - { - printf("[mach64] Error occurred during pci scan: %s\n",strerror(err)); - return err; - } - else - { - err = ENXIO; - for(i=0;i<num_pci;i++) - { - if(lst[i].vendor == VENDOR_ATI) - { - int idx; - const char *dname; - idx = find_chip(lst[i].device); - if(idx == -1 && force == PROBE_NORMAL) continue; - dname = pci_device_name(VENDOR_ATI,lst[i].device); - dname = dname ? dname : "Unknown chip"; - printf("[mach64] Found chip: %s\n",dname); - if ((lst[i].command & PCI_COMMAND_IO) == 0) - { - printf("[mach64] Device is disabled, ignoring\n"); - continue; - } - if(force > PROBE_NORMAL) - { - printf("[mach64] Driver was forced. Was found %sknown chip\n",idx == -1 ? "un" : ""); - if(idx == -1) - printf("[mach64] Assuming it as Mach64\n"); - } - mach64_cap.device_id = lst[i].device; - err = 0; - memcpy(&pci_info,&lst[i],sizeof(pciinfo_t)); - probed=1; - break; - } - } - } - if(err && verbose) printf("[mach64] Can't find chip\n"); - return err; -} - -static void reset_regs( void ) -{ - size_t i; - for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) - { - mach64_fifo_wait(2); - OUTREG(vregs[i].name,0); - } -} - - -int vixInit(void) -{ - int err; - if(!probed) - { - printf("[mach64] Driver was not probed but is being initializing\n"); - return EINTR; - } - if(__verbose>0) printf("[mach64] version %s\n", VERSION); - - if((mach64_mmio_base = map_phys_mem(pci_info.base2,0x1000))==(void *)-1) return ENOMEM; - mach64_wait_for_idle(); - mach64_ram_size = INREG(MEM_CNTL) & CTL_MEM_SIZEB; - if (mach64_ram_size < 8) mach64_ram_size = (mach64_ram_size + 1) * 512; - else if (mach64_ram_size < 12) mach64_ram_size = (mach64_ram_size - 3) * 1024; - else mach64_ram_size = (mach64_ram_size - 7) * 2048; - mach64_ram_size *= 0x400; /* KB -> bytes */ - if((mach64_mem_base = map_phys_mem(pci_info.base0,mach64_ram_size))==(void *)-1) return ENOMEM; - memset(&besr,0,sizeof(bes_registers_t)); - printf("[mach64] Video memory = %uMb\n",mach64_ram_size/0x100000); - err = mtrr_set_type(pci_info.base0,mach64_ram_size,MTRR_TYPE_WRCOMB); - if(!err) printf("[mach64] Set write-combining type of video memory\n"); - - /* save this */ - mach64_wait_for_idle(); - SAVED_OVERLAY_GRAPHICS_KEY_CLR = INREG(OVERLAY_GRAPHICS_KEY_CLR); - - /* check if planar formats are supported */ - supports_planar=0; - mach64_wait_for_idle(); - mach64_fifo_wait(2); - if(INREG(SCALER_BUF0_OFFSET_U)) supports_planar=1; - else - { - OUTREG(SCALER_BUF0_OFFSET_U, -1); - - mach64_wait_vsync(); - mach64_wait_for_idle(); - mach64_fifo_wait(2); - - if(INREG(SCALER_BUF0_OFFSET_U)) supports_planar=1; - } - if(supports_planar) printf("[mach64] Planar YUV formats are supported :)\n"); - else printf("[mach64] Planar YUV formats are not supported :(\n"); - - if( mach64_cap.device_id==DEVICE_ATI_RAGE_MOBILITY_P_M - || mach64_cap.device_id==DEVICE_ATI_RAGE_MOBILITY_P_M2 - || mach64_cap.device_id==DEVICE_ATI_RAGE_MOBILITY_L - || mach64_cap.device_id==DEVICE_ATI_RAGE_MOBILITY_L2) - supports_lcd_v_stretch=1; - else - supports_lcd_v_stretch=0; - - reset_regs(); - mach64_vid_make_default(); - - if(__verbose > VERBOSE_LEVEL) mach64_vid_dump_regs(); - return 0; -} - -void vixDestroy(void) -{ - /*restore this*/ - mach64_wait_for_idle(); - OUTREG(OVERLAY_GRAPHICS_KEY_CLR,SAVED_OVERLAY_GRAPHICS_KEY_CLR); - - unmap_phys_mem(mach64_mem_base,mach64_ram_size); - unmap_phys_mem(mach64_mmio_base,0x1000); -} - -int vixGetCapability(vidix_capability_t *to) -{ - memcpy(to, &mach64_cap, sizeof(vidix_capability_t)); - return 0; -} - -static unsigned mach64_query_pitch(unsigned fourcc,const vidix_yuv_t *spitch) -{ - unsigned pitch,spy,spv,spu; - spy = spv = spu = 0; - switch(spitch->y) - { - case 16: - case 32: - case 64: - case 128: - case 256: spy = spitch->y; break; - default: break; - } - switch(spitch->u) - { - case 16: - case 32: - case 64: - case 128: - case 256: spu = spitch->u; break; - default: break; - } - switch(spitch->v) - { - case 16: - case 32: - case 64: - case 128: - case 256: spv = spitch->v; break; - default: break; - } - switch(fourcc) - { - /* 4:2:0 */ - case IMGFMT_IYUV: - case IMGFMT_YV12: - case IMGFMT_I420: - if(spy > 16 && spu == spy/2 && spv == spy/2) pitch = spy; - else pitch = 32; - break; - case IMGFMT_YVU9: - if(spy > 32 && spu == spy/4 && spv == spy/4) pitch = spy; - else pitch = 64; - break; - default: - if(spy >= 16) pitch = spy; - else pitch = 16; - break; - } - return pitch; -} - -static void mach64_compute_framesize(vidix_playback_t *info) -{ - unsigned pitch,awidth; - pitch = mach64_query_pitch(info->fourcc,&info->src.pitch); - switch(info->fourcc) - { - case IMGFMT_I420: - case IMGFMT_YV12: - case IMGFMT_IYUV: - awidth = (info->src.w + (pitch-1)) & ~(pitch-1); - info->frame_size = awidth*(info->src.h+info->src.h/2); - break; - case IMGFMT_YVU9: - awidth = (info->src.w + (pitch-1)) & ~(pitch-1); - info->frame_size = awidth*(info->src.h+info->src.h/8); - break; -// case IMGFMT_RGB32: - case IMGFMT_BGR32: - awidth = (info->src.w*4 + (pitch-1)) & ~(pitch-1); - info->frame_size = (awidth*info->src.h); - break; - /* YUY2 YVYU, RGB15, RGB16 */ - default: - awidth = (info->src.w*2 + (pitch-1)) & ~(pitch-1); - info->frame_size = (awidth*info->src.h); - break; - } - info->frame_size+=256; // so we have some space for alignment & such - info->frame_size&=~16; -} - -static void mach64_vid_stop_video( void ) -{ - mach64_fifo_wait(14); - OUTREG(OVERLAY_SCALE_CNTL, 0x80000000); - OUTREG(OVERLAY_EXCLUSIVE_HORZ, 0); - OUTREG(OVERLAY_EXCLUSIVE_VERT, 0); - OUTREG(SCALER_H_COEFF0, 0x00002000); - OUTREG(SCALER_H_COEFF1, 0x0D06200D); - OUTREG(SCALER_H_COEFF2, 0x0D0A1C0D); - OUTREG(SCALER_H_COEFF3, 0x0C0E1A0C); - OUTREG(SCALER_H_COEFF4, 0x0C14140C); - OUTREG(VIDEO_FORMAT, 0xB000B); - OUTREG(OVERLAY_TEST, 0x0); -} - -static void mach64_vid_display_video( void ) -{ - uint32_t vf; - mach64_fifo_wait(14); - - OUTREG(OVERLAY_Y_X_START, besr.y_x_start); - OUTREG(OVERLAY_Y_X_END, besr.y_x_end); - OUTREG(OVERLAY_SCALE_INC, besr.scale_inc); - OUTREG(SCALER_BUF_PITCH, besr.vid_buf_pitch); - OUTREG(SCALER_HEIGHT_WIDTH, besr.height_width); - OUTREG(SCALER_BUF0_OFFSET, mach64_buffer_base[0][0]); - OUTREG(SCALER_BUF0_OFFSET_U, mach64_buffer_base[0][1]); - OUTREG(SCALER_BUF0_OFFSET_V, mach64_buffer_base[0][2]); - OUTREG(SCALER_BUF1_OFFSET, mach64_buffer_base[0][0]); - OUTREG(SCALER_BUF1_OFFSET_U, mach64_buffer_base[0][1]); - OUTREG(SCALER_BUF1_OFFSET_V, mach64_buffer_base[0][2]); - mach64_wait_vsync(); - - mach64_fifo_wait(4); - OUTREG(OVERLAY_SCALE_CNTL, 0xC4000003); -// OVERLAY_SCALE_CNTL bits & what they seem to affect -// bit 0 no effect -// bit 1 yuv2rgb coeff related -// bit 2 horizontal interpolation if 0 -// bit 3 vertical interpolation if 0 -// bit 4 chroma encoding (0-> 128=neutral / 1-> 0->neutral) -// bit 5-6 gamma correction -// bit 7 nothing visible if set -// bit 8-27 no effect -// bit 28-31 nothing interresting just crashed my system when i played with them :( - - mach64_wait_for_idle(); - vf = INREG(VIDEO_FORMAT); - -// Bits 16-19 seem to select the format -// 0x0 dunno behaves strange -// 0x1 dunno behaves strange -// 0x2 dunno behaves strange -// 0x3 BGR15 -// 0x4 BGR16 -// 0x5 BGR16 (hmm, that need investigation, 2 BGR16 formats, i guess 1 will have only 5bits for green) -// 0x6 BGR32 -// 0x7 BGR32 with somehow mixed even / odd pixels ? -// 0x8 YYYYUVUV -// 0x9 YVU9 -// 0xA YV12 -// 0xB YUY2 -// 0xC UYVY -// 0xD UYVY (no difference is visible if i switch between C/D for every even/odd frame) -// 0xE dunno behaves strange -// 0xF dunno behaves strange -// Bit 28 all values are assumed to be 7 bit with chroma=64 for black (tested with YV12 & YUY2) -// the remaining bits seem to have no effect - - - switch(besr.fourcc) - { - /* BGR formats */ - case IMGFMT_BGR15: OUTREG(VIDEO_FORMAT, 0x00030000); break; - case IMGFMT_BGR16: OUTREG(VIDEO_FORMAT, 0x00040000); break; - case IMGFMT_BGR32: OUTREG(VIDEO_FORMAT, 0x00060000); break; - /* 4:2:0 */ - case IMGFMT_IYUV: - case IMGFMT_I420: - case IMGFMT_YV12: OUTREG(VIDEO_FORMAT, 0x000A0000); break; - - case IMGFMT_YVU9: OUTREG(VIDEO_FORMAT, 0x00090000); break; - /* 4:2:2 */ - case IMGFMT_YVYU: - case IMGFMT_UYVY: OUTREG(VIDEO_FORMAT, 0x000C0000); break; - case IMGFMT_YUY2: - default: OUTREG(VIDEO_FORMAT, 0x000B0000); break; - } - if(__verbose > VERBOSE_LEVEL) mach64_vid_dump_regs(); -} - -static int mach64_vid_init_video( vidix_playback_t *config ) -{ - uint32_t src_w,src_h,dest_w,dest_h,pitch,h_inc,v_inc,left,leftUV,top,ecp,y_pos; - int is_420,best_pitch,mpitch; - int src_offset_y, src_offset_u, src_offset_v; - unsigned int i; - - mach64_vid_stop_video(); -/* warning, if left or top are != 0 this will fail, as the framesize is too small then */ - left = config->src.x; - top = config->src.y; - src_h = config->src.h; - src_w = config->src.w; - is_420 = 0; - if(config->fourcc == IMGFMT_YV12 || - config->fourcc == IMGFMT_I420 || - config->fourcc == IMGFMT_IYUV) is_420 = 1; - best_pitch = mach64_query_pitch(config->fourcc,&config->src.pitch); - mpitch = best_pitch-1; - switch(config->fourcc) - { - case IMGFMT_YVU9: - /* 4:2:0 */ - case IMGFMT_IYUV: - case IMGFMT_YV12: - case IMGFMT_I420: pitch = (src_w + mpitch) & ~mpitch; - config->dest.pitch.y = - config->dest.pitch.u = - config->dest.pitch.v = best_pitch; - besr.vid_buf_pitch= pitch; - break; - /* RGB 4:4:4:4 */ - case IMGFMT_RGB32: - case IMGFMT_BGR32: pitch = (src_w*4 + mpitch) & ~mpitch; - config->dest.pitch.y = - config->dest.pitch.u = - config->dest.pitch.v = best_pitch; - besr.vid_buf_pitch= pitch>>2; - break; - /* 4:2:2 */ - default: /* RGB15, RGB16, YVYU, UYVY, YUY2 */ - pitch = ((src_w*2) + mpitch) & ~mpitch; - config->dest.pitch.y = - config->dest.pitch.u = - config->dest.pitch.v = best_pitch; - besr.vid_buf_pitch= pitch>>1; - break; - } - dest_w = config->dest.w; - dest_h = config->dest.h; - besr.fourcc = config->fourcc; - ecp = (INPLL(PLL_VCLK_CNTL) & PLL_ECP_DIV) >> 4; -#if 0 -{ -int i; -for(i=0; i<32; i++){ - printf("%X ", INPLL(i)); -} -} -#endif - if(__verbose>0) printf("[mach64] ecp: %d\n", ecp); - v_inc = src_h * mach64_get_vert_stretch(); - - if(mach64_is_interlace()) v_inc<<=1; - if(mach64_is_dbl_scan() ) v_inc>>=1; - v_inc>>=4; // convert 16.16 -> 20.12 - v_inc/= dest_h; - - h_inc = (src_w << (12+ecp)) / dest_w; - /* keep everything in 16.16 */ - config->offsets[0] = 0; - for(i=1; i<config->num_frames; i++) - config->offsets[i] = config->offsets[i-1] + config->frame_size; - - /*FIXME the left / top stuff is broken (= zoom a src rectangle from a larger one) - 1. the framesize isn't known as the outer src rectangle dimensions aren't known - 2. the mach64 needs aligned addresses so it can't work anyway - -> so we could shift the outer buffer to compensate that but that would mean - alignment problems for the code which writes into it - */ - - if(is_420) - { - config->offset.y= 0; - config->offset.u= (pitch*src_h + 15)&~15; - config->offset.v= (config->offset.u + (pitch*src_h>>2) + 15)&~15; - - if(besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV) - { - uint32_t tmp; - tmp = config->offset.u; - config->offset.u = config->offset.v; - config->offset.v = tmp; - } - - src_offset_y= config->offset.y + top*pitch + left; - src_offset_u= config->offset.u + (top*pitch>>2) + (left>>1); - src_offset_v= config->offset.v + (top*pitch>>2) + (left>>1); - } - else if(besr.fourcc == IMGFMT_YVU9) - { - config->offset.y= 0; - config->offset.u= (pitch*src_h + 15)&~15; - config->offset.v= (config->offset.u + (pitch*src_h>>4) + 15)&~15; - - src_offset_y= config->offset.y + top*pitch + left; - src_offset_u= config->offset.u + (top*pitch>>4) + (left>>1); - src_offset_v= config->offset.v + (top*pitch>>4) + (left>>1); - } - else if(besr.fourcc == IMGFMT_BGR32) - { - config->offset.y = config->offset.u = config->offset.v = 0; - src_offset_y= src_offset_u= src_offset_v= top*pitch + (left << 2); - } - else - { - config->offset.y = config->offset.u = config->offset.v = 0; - src_offset_y= src_offset_u= src_offset_v= top*pitch + (left << 1); - } - - num_mach64_buffers= config->num_frames; - for(i=0; i<config->num_frames; i++) - { - mach64_buffer_base[i][0]= (mach64_overlay_offset + config->offsets[i] + src_offset_y)&~15; - mach64_buffer_base[i][1]= (mach64_overlay_offset + config->offsets[i] + src_offset_u)&~15; - mach64_buffer_base[i][2]= (mach64_overlay_offset + config->offsets[i] + src_offset_v)&~15; - } - - leftUV = (left >> 17) & 15; - left = (left >> 16) & 15; - besr.scale_inc = ( h_inc << 16 ) | v_inc; - y_pos = config->dest.y; - if(mach64_is_dbl_scan()) y_pos*=2; - else - if(mach64_is_interlace()) y_pos/=2; - besr.y_x_start = y_pos | (config->dest.x << 16); - y_pos =config->dest.y + dest_h; - if(mach64_is_dbl_scan()) y_pos*=2; - else - if(mach64_is_interlace()) y_pos/=2; - besr.y_x_end = y_pos | ((config->dest.x + dest_w) << 16); - besr.height_width = ((src_w - left)<<16) | (src_h - top); - - return 0; -} - -static int is_supported_fourcc(uint32_t fourcc) -{ - switch(fourcc) - { - case IMGFMT_YV12: - case IMGFMT_I420: - case IMGFMT_YVU9: - case IMGFMT_IYUV: - return supports_planar; - case IMGFMT_YUY2: - case IMGFMT_UYVY: - case IMGFMT_BGR15: - case IMGFMT_BGR16: - case IMGFMT_BGR32: - return 1; - default: - return 0; - } -} - -int vixQueryFourcc(vidix_fourcc_t *to) -{ - if(is_supported_fourcc(to->fourcc)) - { - to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | - VID_DEPTH_4BPP | VID_DEPTH_8BPP | - VID_DEPTH_12BPP| VID_DEPTH_15BPP| - VID_DEPTH_16BPP| VID_DEPTH_24BPP| - VID_DEPTH_32BPP; - to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; - return 0; - } - else to->depth = to->flags = 0; - return ENOSYS; -} - -int vixConfigPlayback(vidix_playback_t *info) -{ - if(!is_supported_fourcc(info->fourcc)) return ENOSYS; - - mach64_compute_framesize(info); - - if(info->num_frames>4) info->num_frames=4; - for(;info->num_frames>0; info->num_frames--) - { - mach64_overlay_offset = mach64_ram_size - info->frame_size*info->num_frames; - mach64_overlay_offset &= 0xffff0000; - if(mach64_overlay_offset>0) break; - } - if(info->num_frames <= 0) return EINVAL; - - info->dga_addr = (char *)mach64_mem_base + mach64_overlay_offset; - mach64_vid_init_video(info); - return 0; -} - -int vixPlaybackOn(void) -{ - mach64_vid_display_video(); - return 0; -} - -int vixPlaybackOff(void) -{ - mach64_vid_stop_video(); - return 0; -} - -int vixPlaybackFrameSelect(unsigned int frame) -{ - uint32_t off[6]; - int i; - int last_frame= (frame-1+num_mach64_buffers) % num_mach64_buffers; -//printf("Selecting frame %d\n", frame); - /* - buf3-5 always should point onto second buffer for better - deinterlacing and TV-in - */ - if(num_mach64_buffers==1) return 0; - - for(i=0; i<3; i++) - { - off[i] = mach64_buffer_base[frame][i]; - off[i+3]= mach64_buffer_base[last_frame][i]; - } - -#if 0 // delay routine so the individual frames can be ssen better -{ -volatile int i=0; -for(i=0; i<10000000; i++); -} -#endif - - mach64_wait_for_idle(); - mach64_fifo_wait(7); - - OUTREG(SCALER_BUF0_OFFSET, off[0]); - OUTREG(SCALER_BUF0_OFFSET_U, off[1]); - OUTREG(SCALER_BUF0_OFFSET_V, off[2]); - OUTREG(SCALER_BUF1_OFFSET, off[3]); - OUTREG(SCALER_BUF1_OFFSET_U, off[4]); - OUTREG(SCALER_BUF1_OFFSET_V, off[5]); - if(num_mach64_buffers==2) mach64_wait_vsync(); //only wait for vsync if we do double buffering - - if(__verbose > VERBOSE_LEVEL) mach64_vid_dump_regs(); - return 0; -} - -vidix_video_eq_t equal = -{ - VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION - , - 0, 0, 0, 0, 0, 0, 0, 0 }; - -int vixPlaybackGetEq( vidix_video_eq_t * eq) -{ - memcpy(eq,&equal,sizeof(vidix_video_eq_t)); - return 0; -} - -int vixPlaybackSetEq( const vidix_video_eq_t * eq) -{ - int br,sat; - if(eq->cap & VEQ_CAP_BRIGHTNESS) equal.brightness = eq->brightness; - if(eq->cap & VEQ_CAP_CONTRAST) equal.contrast = eq->contrast; - if(eq->cap & VEQ_CAP_SATURATION) equal.saturation = eq->saturation; - if(eq->cap & VEQ_CAP_HUE) equal.hue = eq->hue; - if(eq->cap & VEQ_CAP_RGB_INTENSITY) - { - equal.red_intensity = eq->red_intensity; - equal.green_intensity = eq->green_intensity; - equal.blue_intensity = eq->blue_intensity; - } - equal.flags = eq->flags; - br = equal.brightness * 64 / 1000; - if(br < -64) br = -64; if(br > 63) br = 63; - sat = (equal.saturation + 1000) * 16 / 1000; - if(sat < 0) sat = 0; if(sat > 31) sat = 31; - OUTREG(SCALER_COLOUR_CNTL, (br & 0x7f) | (sat << 8) | (sat << 16)); - return 0; -} - -int vixGetGrKeys(vidix_grkey_t *grkey) -{ - memcpy(grkey, &mach64_grkey, sizeof(vidix_grkey_t)); - return(0); -} - -int vixSetGrKeys(const vidix_grkey_t *grkey) -{ - memcpy(&mach64_grkey, grkey, sizeof(vidix_grkey_t)); - - if(mach64_grkey.ckey.op == CKEY_TRUE) - { - besr.ckey_on=1; - - switch(mach64_vid_get_dbpp()) - { - case 15: - besr.graphics_key_msk=0x7FFF; - besr.graphics_key_clr= - ((mach64_grkey.ckey.blue &0xF8)>>3) - | ((mach64_grkey.ckey.green&0xF8)<<2) - | ((mach64_grkey.ckey.red &0xF8)<<7); - break; - case 16: - besr.graphics_key_msk=0xFFFF; - besr.graphics_key_clr= - ((mach64_grkey.ckey.blue &0xF8)>>3) - | ((mach64_grkey.ckey.green&0xFC)<<3) - | ((mach64_grkey.ckey.red &0xF8)<<8); - //besr.graphics_key_clr=le2me_32(besr.graphics_key_clr); - break; - case 24: - besr.graphics_key_msk=0xFFFFFF; - besr.graphics_key_clr= - ((mach64_grkey.ckey.blue &0xFF)) - | ((mach64_grkey.ckey.green&0xFF)<<8) - | ((mach64_grkey.ckey.red &0xFF)<<16); - break; - case 32: - besr.graphics_key_msk=0xFFFFFF; - besr.graphics_key_clr= - ((mach64_grkey.ckey.blue &0xFF)) - | ((mach64_grkey.ckey.green&0xFF)<<8) - | ((mach64_grkey.ckey.red &0xFF)<<16); - break; - default: - besr.ckey_on=0; - besr.graphics_key_msk=0; - besr.graphics_key_clr=0; - } - } - else - { - besr.ckey_on=0; - besr.graphics_key_msk=0; - besr.graphics_key_clr=0; - } - - mach64_fifo_wait(4); - OUTREG(OVERLAY_GRAPHICS_KEY_MSK, besr.graphics_key_msk); - OUTREG(OVERLAY_GRAPHICS_KEY_CLR, besr.graphics_key_clr); -// OUTREG(OVERLAY_VIDEO_KEY_MSK, 0); -// OUTREG(OVERLAY_VIDEO_KEY_CLR, 0); - if(besr.ckey_on) - OUTREG(OVERLAY_KEY_CNTL,VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_EQ|CMP_MIX_AND); - else - OUTREG(OVERLAY_KEY_CNTL,VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_TRUE|CMP_MIX_AND); - - return(0); -}
--- a/vidix/drivers/mga_vid.c Sat Mar 31 23:48:48 2007 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1508 +0,0 @@ -/* - Matrox MGA driver - - ported to VIDIX by Alex Beregszaszi - - YUY2 support (see config.format) added by A'rpi/ESP-team - double buffering added by A'rpi/ESP-team - - Brightness/contrast support by Nick Kurshev/Dariush Pietrzak (eyck) and me - - TODO: - * fix memory size detection (current reading pci userconfig isn't - working as requested - returns the max avail. ram on arch?) - * translate all non-english comments to english -*/ - -/* - * Original copyright: - * - * mga_vid.c - * - * Copyright (C) 1999 Aaron Holtzman - * - * Module skeleton based on gutted agpgart module by Jeff Hartmann - * <slicer@ionet.net> - * - * Matrox MGA G200/G400 YUV Video Interface module Version 0.1.0 - * - * BES == Back End Scaler - * - * This software has been released under the terms of the GNU Public - * license. See http://www.gnu.org/copyleft/gpl.html for details. - */ - -//#define CRTC2 - -// Set this value, if autodetection fails! (video ram size in megabytes) -//#define MGA_MEMORY_SIZE 16 - -/* No irq support in userspace implemented yet, do not enable this! */ -/* disable irq */ -#undef MGA_ALLOW_IRQ - -#define MGA_VSYNC_POS 2 - -#undef MGA_PCICONFIG_MEMDETECT - -#define MGA_DEFAULT_FRAMES 4 - -#include <errno.h> -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include <math.h> -#include <inttypes.h> - -#include "../vidix.h" -#include "../fourcc.h" -#include "../../libdha/libdha.h" -#include "../../libdha/pci_ids.h" -#include "../../libdha/pci_names.h" - -#ifdef __MINGW32__ -#define ENOTSUP 134 -#endif - -#if !defined(ENOTSUP) && defined(EOPNOTSUPP) -#define ENOTSUP EOPNOTSUPP -#endif - -/* from radeon_vid */ -#define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ)))) -#define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL - -#define readb(addr) GETREG(uint8_t,(uint32_t)(addr),0) -#define writeb(val,addr) SETREG(uint8_t,(uint32_t)(addr),0,val) -#define readl(addr) GETREG(uint32_t,(uint32_t)(addr),0) -#define writel(val,addr) SETREG(uint32_t,(uint32_t)(addr),0,val) - -static int mga_verbose = 0; - -/* for device detection */ -static int probed = 0; -static pciinfo_t pci_info; - -/* internal booleans */ -static int mga_vid_in_use = 0; -static int is_g400 = 0; -static int vid_src_ready = 0; -static int vid_overlay_on = 0; - -/* mapped physical addresses */ -static uint8_t *mga_mmio_base = 0; -static uint8_t *mga_mem_base = 0; - -static int mga_src_base = 0; /* YUV buffer position in video memory */ - -static uint32_t mga_ram_size = 0; /* how much megabytes videoram we have */ - -/* Graphic keys */ -static vidix_grkey_t mga_grkey; - -static int colkey_saved = 0; -static int colkey_on = 0; -static unsigned char colkey_color[4]; -static unsigned char colkey_mask[4]; - -/* for IRQ */ -static int mga_irq = -1; - -static int mga_next_frame = 0; - -static vidix_capability_t mga_cap = -{ - "Matrox MGA G200/G4x0/G5x0 YUV Video", - "Aaron Holtzman, Arpad Gereoffy, Alex Beregszaszi, Nick Kurshev", - TYPE_OUTPUT, - { 0, 0, 0, 0 }, - 2048, - 2048, - 4, - 4, - -1, - FLAG_UPSCALER | FLAG_DOWNSCALER | FLAG_EQUALIZER, - VENDOR_MATROX, - -1, /* will be set in vixProbe */ - { 0, 0, 0, 0} -}; - -/* MATROX BES registers */ -typedef struct bes_registers_s -{ - //BES Control - uint32_t besctl; - //BES Global control - uint32_t besglobctl; - //Luma control (brightness and contrast) - uint32_t beslumactl; - //Line pitch - uint32_t bespitch; - - //Buffer A-1 Chroma 3 plane org - uint32_t besa1c3org; - //Buffer A-1 Chroma org - uint32_t besa1corg; - //Buffer A-1 Luma org - uint32_t besa1org; - - //Buffer A-2 Chroma 3 plane org - uint32_t besa2c3org; - //Buffer A-2 Chroma org - uint32_t besa2corg; - //Buffer A-2 Luma org - uint32_t besa2org; - - //Buffer B-1 Chroma 3 plane org - uint32_t besb1c3org; - //Buffer B-1 Chroma org - uint32_t besb1corg; - //Buffer B-1 Luma org - uint32_t besb1org; - - //Buffer B-2 Chroma 3 plane org - uint32_t besb2c3org; - //Buffer B-2 Chroma org - uint32_t besb2corg; - //Buffer B-2 Luma org - uint32_t besb2org; - - //BES Horizontal coord - uint32_t beshcoord; - //BES Horizontal inverse scaling [5.14] - uint32_t beshiscal; - //BES Horizontal source start [10.14] (for scaling) - uint32_t beshsrcst; - //BES Horizontal source ending [10.14] (for scaling) - uint32_t beshsrcend; - //BES Horizontal source last - uint32_t beshsrclst; - - - //BES Vertical coord - uint32_t besvcoord; - //BES Vertical inverse scaling [5.14] - uint32_t besviscal; - //BES Field 1 vertical source last position - uint32_t besv1srclst; - //BES Field 1 weight start - uint32_t besv1wght; - //BES Field 2 vertical source last position - uint32_t besv2srclst; - //BES Field 2 weight start - uint32_t besv2wght; - -} bes_registers_t; -static bes_registers_t regs; - -#ifdef CRTC2 -typedef struct crtc2_registers_s -{ - uint32_t c2ctl; - uint32_t c2datactl; - uint32_t c2misc; - uint32_t c2hparam; - uint32_t c2hsync; - uint32_t c2offset; - uint32_t c2pl2startadd0; - uint32_t c2pl2startadd1; - uint32_t c2pl3startadd0; - uint32_t c2pl3startadd1; - uint32_t c2preload; - uint32_t c2spicstartadd0; - uint32_t c2spicstartadd1; - uint32_t c2startadd0; - uint32_t c2startadd1; - uint32_t c2subpiclut; - uint32_t c2vcount; - uint32_t c2vparam; - uint32_t c2vsync; -} crtc2_registers_t; -static crtc2_registers_t cregs; -#endif - -//All register offsets are converted to word aligned offsets (32 bit) -//because we want all our register accesses to be 32 bits -#define VCOUNT 0x1e20 - -#define PALWTADD 0x3c00 // Index register for X_DATAREG port -#define X_DATAREG 0x3c0a - -#define XMULCTRL 0x19 -#define BPP_8 0x00 -#define BPP_15 0x01 -#define BPP_16 0x02 -#define BPP_24 0x03 -#define BPP_32_DIR 0x04 -#define BPP_32_PAL 0x07 - -#define XCOLMSK 0x40 -#define X_COLKEY 0x42 -#define XKEYOPMODE 0x51 -#define XCOLMSK0RED 0x52 -#define XCOLMSK0GREEN 0x53 -#define XCOLMSK0BLUE 0x54 -#define XCOLKEY0RED 0x55 -#define XCOLKEY0GREEN 0x56 -#define XCOLKEY0BLUE 0x57 - -#ifdef CRTC2 -/*CRTC2 registers*/ -#define XMISCCTRL 0x1e -#define C2CTL 0x3c10 -#define C2DATACTL 0x3c4c -#define C2MISC 0x3c44 -#define C2HPARAM 0x3c14 -#define C2HSYNC 0x3c18 -#define C2OFFSET 0x3c40 -#define C2PL2STARTADD0 0x3c30 // like BESA1CORG -#define C2PL2STARTADD1 0x3c34 // like BESA2CORG -#define C2PL3STARTADD0 0x3c38 // like BESA1C3ORG -#define C2PL3STARTADD1 0x3c3c // like BESA2C3ORG -#define C2PRELOAD 0x3c24 -#define C2SPICSTARTADD0 0x3c54 -#define C2SPICSTARTADD1 0x3c58 -#define C2STARTADD0 0x3c28 // like BESA1ORG -#define C2STARTADD1 0x3c2c // like BESA2ORG -#define C2SUBPICLUT 0x3c50 -#define C2VCOUNT 0x3c48 -#define C2VPARAM 0x3c1c -#define C2VSYNC 0x3c20 -#endif /* CRTC2 */ - -// Backend Scaler registers -#define BESCTL 0x3d20 -#define BESGLOBCTL 0x3dc0 -#define BESLUMACTL 0x3d40 -#define BESPITCH 0x3d24 - -#define BESA1C3ORG 0x3d60 -#define BESA1CORG 0x3d10 -#define BESA1ORG 0x3d00 - -#define BESA2C3ORG 0x3d64 -#define BESA2CORG 0x3d14 -#define BESA2ORG 0x3d04 - -#define BESB1C3ORG 0x3d68 -#define BESB1CORG 0x3d18 -#define BESB1ORG 0x3d08 - -#define BESB2C3ORG 0x3d6C -#define BESB2CORG 0x3d1C -#define BESB2ORG 0x3d0C - -#define BESHCOORD 0x3d28 -#define BESHISCAL 0x3d30 -#define BESHSRCEND 0x3d3C -#define BESHSRCLST 0x3d50 -#define BESHSRCST 0x3d38 -#define BESV1WGHT 0x3d48 -#define BESV2WGHT 0x3d4c -#define BESV1SRCLST 0x3d54 -#define BESV2SRCLST 0x3d58 -#define BESVISCAL 0x3d34 -#define BESVCOORD 0x3d2c -#define BESSTATUS 0x3dc4 - -#define CRTCX 0x1fd4 -#define CRTCD 0x1fd5 -#define IEN 0x1e1c -#define ICLEAR 0x1e18 -#define STATUS 0x1e14 - - -#ifdef CRTC2 -static void crtc2_frame_sel(int frame) -{ -switch(frame) { -case 0: - cregs.c2pl2startadd0=regs.besa1corg; - cregs.c2pl3startadd0=regs.besa1c3org; - cregs.c2startadd0=regs.besa1org; - break; -case 1: - cregs.c2pl2startadd0=regs.besa2corg; - cregs.c2pl3startadd0=regs.besa2c3org; - cregs.c2startadd0=regs.besa2org; - break; -case 2: - cregs.c2pl2startadd0=regs.besb1corg; - cregs.c2pl3startadd0=regs.besb1c3org; - cregs.c2startadd0=regs.besb1org; - break; -case 3: - cregs.c2pl2startadd0=regs.besb2corg; - cregs.c2pl3startadd0=regs.besb2c3org; - cregs.c2startadd0=regs.besb2org; - break; -} - writel(cregs.c2startadd0, mga_mmio_base + C2STARTADD0); - writel(cregs.c2pl2startadd0, mga_mmio_base + C2PL2STARTADD0); - writel(cregs.c2pl3startadd0, mga_mmio_base + C2PL3STARTADD0); -} -#endif - -int vixPlaybackFrameSelect(unsigned int frame) -{ - mga_next_frame = frame; - if (mga_verbose>1) printf("[mga] frameselect: %d\n", mga_next_frame); -#if MGA_ALLOW_IRQ - if (mga_irq == -1) -#endif - { - //we don't need the vcount protection as we're only hitting - //one register (and it doesn't seem to be double buffered) - regs.besctl = (regs.besctl & ~0x07000000) + (mga_next_frame << 25); - writel( regs.besctl, mga_mmio_base + BESCTL ); - -// writel( regs.besglobctl + ((readl(mga_mmio_base + VCOUNT)+2)<<16), - writel( regs.besglobctl + (MGA_VSYNC_POS<<16), - mga_mmio_base + BESGLOBCTL); -#ifdef CRTC2 - crtc2_frame_sel(mga_next_frame); -#endif - } - - return(0); -} - - -static void mga_vid_write_regs(int restore) -{ - //Make sure internal registers don't get updated until we're done - writel( (readl(mga_mmio_base + VCOUNT)-1)<<16, - mga_mmio_base + BESGLOBCTL); - - // color or coordinate keying - - if(restore && colkey_saved){ - // restore it - colkey_saved=0; - -// printf("[mga] Restoring colorkey (ON: %d %02X:%02X:%02X)\n", -// colkey_on,colkey_color[0],colkey_color[1],colkey_color[2]); - - // Set color key registers: - writeb( XKEYOPMODE, mga_mmio_base + PALWTADD); - writeb( colkey_on, mga_mmio_base + X_DATAREG); - - writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD); - writeb( colkey_color[0], mga_mmio_base + X_DATAREG); - writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD); - writeb( colkey_color[1], mga_mmio_base + X_DATAREG); - writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD); - writeb( colkey_color[2], mga_mmio_base + X_DATAREG); - writeb( X_COLKEY, mga_mmio_base + PALWTADD); - writeb( colkey_color[3], mga_mmio_base + X_DATAREG); - - writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD); - writeb( colkey_mask[0], mga_mmio_base + X_DATAREG); - writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD); - writeb( colkey_mask[1], mga_mmio_base + X_DATAREG); - writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD); - writeb( colkey_mask[2], mga_mmio_base + X_DATAREG); - writeb( XCOLMSK, mga_mmio_base + PALWTADD); - writeb( colkey_mask[3], mga_mmio_base + X_DATAREG); - - } else if(!colkey_saved){ - // save it - colkey_saved=1; - // Get color key registers: - writeb( XKEYOPMODE, mga_mmio_base + PALWTADD); - colkey_on=(unsigned char)readb(mga_mmio_base + X_DATAREG) & 1; - - writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD); - colkey_color[0]=(unsigned char)readb(mga_mmio_base + X_DATAREG); - writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD); - colkey_color[1]=(unsigned char)readb(mga_mmio_base + X_DATAREG); - writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD); - colkey_color[2]=(unsigned char)readb(mga_mmio_base + X_DATAREG); - writeb( X_COLKEY, mga_mmio_base + PALWTADD); - colkey_color[3]=(unsigned char)readb(mga_mmio_base + X_DATAREG); - - writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD); - colkey_mask[0]=(unsigned char)readb(mga_mmio_base + X_DATAREG); - writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD); - colkey_mask[1]=(unsigned char)readb(mga_mmio_base + X_DATAREG); - writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD); - colkey_mask[2]=(unsigned char)readb(mga_mmio_base + X_DATAREG); - writeb( XCOLMSK, mga_mmio_base + PALWTADD); - colkey_mask[3]=(unsigned char)readb(mga_mmio_base + X_DATAREG); - -// printf("[mga] Saved colorkey (ON: %d %02X:%02X:%02X)\n", -// colkey_on,colkey_color[0],colkey_color[1],colkey_color[2]); - - } - -if(!restore){ - writeb( XKEYOPMODE, mga_mmio_base + PALWTADD); - writeb( mga_grkey.ckey.op == CKEY_TRUE, mga_mmio_base + X_DATAREG); - if ( mga_grkey.ckey.op == CKEY_TRUE ) - { - uint32_t r=0, g=0, b=0; - - writeb( XMULCTRL, mga_mmio_base + PALWTADD); - switch (readb (mga_mmio_base + X_DATAREG)) - { - case BPP_8: - /* Need to look up the color index, just using - color 0 for now. */ - break; - - case BPP_15: - r = mga_grkey.ckey.red >> 3; - g = mga_grkey.ckey.green >> 3; - b = mga_grkey.ckey.blue >> 3; - break; - - case BPP_16: - r = mga_grkey.ckey.red >> 3; - g = mga_grkey.ckey.green >> 2; - b = mga_grkey.ckey.blue >> 3; - break; - - case BPP_24: - case BPP_32_DIR: - case BPP_32_PAL: - r = mga_grkey.ckey.red; - g = mga_grkey.ckey.green; - b = mga_grkey.ckey.blue; - break; - } - - // Enable colorkeying - writeb( XKEYOPMODE, mga_mmio_base + PALWTADD); - writeb( 1, mga_mmio_base + X_DATAREG); - - // Disable color keying on alpha channel - writeb( XCOLMSK, mga_mmio_base + PALWTADD); - writeb( 0x00, mga_mmio_base + X_DATAREG); - writeb( X_COLKEY, mga_mmio_base + PALWTADD); - writeb( 0x00, mga_mmio_base + X_DATAREG); - - - // Set up color key registers - writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD); - writeb( r, mga_mmio_base + X_DATAREG); - writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD); - writeb( g, mga_mmio_base + X_DATAREG); - writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD); - writeb( b, mga_mmio_base + X_DATAREG); - - // Set up color key mask registers - writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD); - writeb( 0xff, mga_mmio_base + X_DATAREG); - writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD); - writeb( 0xff, mga_mmio_base + X_DATAREG); - writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD); - writeb( 0xff, mga_mmio_base + X_DATAREG); - } - else - { - // Disable colorkeying - writeb( XKEYOPMODE, mga_mmio_base + PALWTADD); - writeb( 0, mga_mmio_base + X_DATAREG); - } -} - - // Backend Scaler - writel( regs.besctl, mga_mmio_base + BESCTL); - if(is_g400) - writel( regs.beslumactl, mga_mmio_base + BESLUMACTL); - writel( regs.bespitch, mga_mmio_base + BESPITCH); - - writel( regs.besa1org, mga_mmio_base + BESA1ORG); - writel( regs.besa1corg, mga_mmio_base + BESA1CORG); - writel( regs.besa2org, mga_mmio_base + BESA2ORG); - writel( regs.besa2corg, mga_mmio_base + BESA2CORG); - writel( regs.besb1org, mga_mmio_base + BESB1ORG); - writel( regs.besb1corg, mga_mmio_base + BESB1CORG); - writel( regs.besb2org, mga_mmio_base + BESB2ORG); - writel( regs.besb2corg, mga_mmio_base + BESB2CORG); - if(is_g400) - { - writel( regs.besa1c3org, mga_mmio_base + BESA1C3ORG); - writel( regs.besa2c3org, mga_mmio_base + BESA2C3ORG); - writel( regs.besb1c3org, mga_mmio_base + BESB1C3ORG); - writel( regs.besb2c3org, mga_mmio_base + BESB2C3ORG); - } - - writel( regs.beshcoord, mga_mmio_base + BESHCOORD); - writel( regs.beshiscal, mga_mmio_base + BESHISCAL); - writel( regs.beshsrcst, mga_mmio_base + BESHSRCST); - writel( regs.beshsrcend, mga_mmio_base + BESHSRCEND); - writel( regs.beshsrclst, mga_mmio_base + BESHSRCLST); - - writel( regs.besvcoord, mga_mmio_base + BESVCOORD); - writel( regs.besviscal, mga_mmio_base + BESVISCAL); - - writel( regs.besv1srclst, mga_mmio_base + BESV1SRCLST); - writel( regs.besv1wght, mga_mmio_base + BESV1WGHT); - writel( regs.besv2srclst, mga_mmio_base + BESV2SRCLST); - writel( regs.besv2wght, mga_mmio_base + BESV2WGHT); - - //update the registers somewhere between 1 and 2 frames from now. - writel( regs.besglobctl + ((readl(mga_mmio_base + VCOUNT)+2)<<16), - mga_mmio_base + BESGLOBCTL); - - if (mga_verbose > 1) - { - printf("[mga] wrote BES registers\n"); - printf("[mga] BESCTL = 0x%08x\n", - readl(mga_mmio_base + BESCTL)); - printf("[mga] BESGLOBCTL = 0x%08x\n", - readl(mga_mmio_base + BESGLOBCTL)); - printf("[mga] BESSTATUS= 0x%08x\n", - readl(mga_mmio_base + BESSTATUS)); - } -#ifdef CRTC2 -// printf("c2ctl:0x%08x c2datactl:0x%08x\n",readl(mga_mmio_base + C2CTL),readl(mga_mmio_base + C2DATACTL)); -// printf("c2misc:0x%08x\n",readl(mga_mmio_base + C2MISC)); -// printf("c2ctl:0x%08x c2datactl:0x%08x\n",cregs.c2ctl,cregs.c2datactl); - -// writel(cregs.c2ctl, mga_mmio_base + C2CTL); - - writel(((readl(mga_mmio_base + C2CTL) & ~0x03e00000) + (cregs.c2ctl & 0x03e00000)), mga_mmio_base + C2CTL); - writel(((readl(mga_mmio_base + C2DATACTL) & ~0x000000ff) + (cregs.c2datactl & 0x000000ff)), mga_mmio_base + C2DATACTL); - // ctrc2 - // disable CRTC2 acording to specs -// writel(cregs.c2ctl & 0xfffffff0, mga_mmio_base + C2CTL); - // je to treba ??? -// writeb((readb(mga_mmio_base + XMISCCTRL) & 0x19) | 0xa2, mga_mmio_base + XMISCCTRL); // MAFC - mfcsel & vdoutsel -// writeb((readb(mga_mmio_base + XMISCCTRL) & 0x19) | 0x92, mga_mmio_base + XMISCCTRL); -// writeb((readb(mga_mmio_base + XMISCCTRL) & ~0xe9) + 0xa2, mga_mmio_base + XMISCCTRL); -// writel(cregs.c2datactl, mga_mmio_base + C2DATACTL); -// writel(cregs.c2hparam, mga_mmio_base + C2HPARAM); -// writel(cregs.c2hsync, mga_mmio_base + C2HSYNC); -// writel(cregs.c2vparam, mga_mmio_base + C2VPARAM); -// writel(cregs.c2vsync, mga_mmio_base + C2VSYNC); - writel(cregs.c2misc, mga_mmio_base + C2MISC); - - if (mga_verbose > 1) printf("[mga] c2offset = %d\n",cregs.c2offset); - - writel(cregs.c2offset, mga_mmio_base + C2OFFSET); - writel(cregs.c2startadd0, mga_mmio_base + C2STARTADD0); -// writel(cregs.c2startadd1, mga_mmio_base + C2STARTADD1); - writel(cregs.c2pl2startadd0, mga_mmio_base + C2PL2STARTADD0); -// writel(cregs.c2pl2startadd1, mga_mmio_base + C2PL2STARTADD1); - writel(cregs.c2pl3startadd0, mga_mmio_base + C2PL3STARTADD0); -// writel(cregs.c2pl3startadd1, mga_mmio_base + C2PL3STARTADD1); - writel(cregs.c2spicstartadd0, mga_mmio_base + C2SPICSTARTADD0); -// writel(cregs.c2spicstartadd1, mga_mmio_base + C2SPICSTARTADD1); -// writel(cregs.c2subpiclut, mga_mmio_base + C2SUBPICLUT); -// writel(cregs.c2preload, mga_mmio_base + C2PRELOAD); - // finaly enable everything -// writel(cregs.c2ctl, mga_mmio_base + C2CTL); -// printf("c2ctl:0x%08x c2datactl:0x%08x\n",readl(mga_mmio_base + C2CTL),readl(mga_mmio_base + C2DATACTL)); -// printf("c2misc:0x%08x\n", readl(mga_mmio_base + C2MISC)); -#endif -} - -#ifdef MGA_ALLOW_IRQ -static void enable_irq(){ - long int cc; - - cc = readl(mga_mmio_base + IEN); -// printf("*** !!! IRQREG = %d\n", (int)(cc&0xff)); - - writeb( 0x11, mga_mmio_base + CRTCX); - - writeb(0x20, mga_mmio_base + CRTCD ); /* clear 0, enable off */ - writeb(0x00, mga_mmio_base + CRTCD ); /* enable on */ - writeb(0x10, mga_mmio_base + CRTCD ); /* clear = 1 */ - - writel( regs.besglobctl , mga_mmio_base + BESGLOBCTL); - - return; -} - -static void disable_irq() -{ - writeb( 0x11, mga_mmio_base + CRTCX); - writeb(0x20, mga_mmio_base + CRTCD ); /* clear 0, enable off */ - - return; -} - -void mga_handle_irq(int irq, void *dev_id/*, struct pt_regs *pregs*/) { -// static int frame=0; -// static int counter=0; - long int cc; -// if ( ! mga_enabled_flag ) return; - -// printf("vcount = %d\n",readl(mga_mmio_base + VCOUNT)); - - //printf("mga_interrupt #%d\n", irq); - - if ( irq != -1 ) { - - cc = readl(mga_mmio_base + STATUS); - if ( ! (cc & 0x10) ) return; /* vsyncpen */ -// debug_irqcnt++; - } - -// if ( debug_irqignore ) { -// debug_irqignore = 0; - - -/* - if ( mga_conf_deinterlace ) { - if ( mga_first_field ) { - // printf("mga_interrupt first field\n"); - if ( syncfb_interrupt() ) - mga_first_field = 0; - } else { - // printf("mga_interrupt second field\n"); - mga_select_buffer( mga_current_field | 2 ); - mga_first_field = 1; - } - } else { - syncfb_interrupt(); - } -*/ - -// frame=(frame+1)&1; - regs.besctl = (regs.besctl & ~0x07000000) + (mga_next_frame << 25); - writel( regs.besctl, mga_mmio_base + BESCTL ); - -#ifdef CRTC2 -// sem pridat vyber obrazku !!!! - crtc2_frame_sel(mga_next_frame); -#endif - -#if 0 - ++counter; - if(!(counter&63)){ - printf("mga irq counter = %d\n",counter); - } -#endif - -// } else { -// debug_irqignore = 1; -// } - - if ( irq != -1 ) { - writeb( 0x11, mga_mmio_base + CRTCX); - writeb( 0, mga_mmio_base + CRTCD ); - writeb( 0x10, mga_mmio_base + CRTCD ); - } - -// writel( regs.besglobctl, mga_mmio_base + BESGLOBCTL); - - - return; - -} -#endif /* MGA_ALLOW_IRQ */ - -int vixConfigPlayback(vidix_playback_t *config) -{ - unsigned int i; - int x, y, sw, sh, dw, dh; - int besleft, bestop, ifactor, ofsleft, ofstop, baseadrofs, weight, weights; -#ifdef CRTC2 -#define right_margin 0 -#define left_margin 18 -#define hsync_len 46 -#define lower_margin 10 -#define vsync_len 4 -#define upper_margin 39 - - unsigned int hdispend = (config->src.w + 31) & ~31; - unsigned int hsyncstart = hdispend + (right_margin & ~7); - unsigned int hsyncend = hsyncstart + (hsync_len & ~7); - unsigned int htotal = hsyncend + (left_margin & ~7); - unsigned int vdispend = config->src.h; - unsigned int vsyncstart = vdispend + lower_margin; - unsigned int vsyncend = vsyncstart + vsync_len; - unsigned int vtotal = vsyncend + upper_margin; -#endif - - if ((config->num_frames < 1) || (config->num_frames > 4)) - { - printf("[mga] illegal num_frames: %d, setting to %d\n", - config->num_frames, MGA_DEFAULT_FRAMES); - config->num_frames = MGA_DEFAULT_FRAMES; - } - - x = config->dest.x; - y = config->dest.y; - sw = config->src.w; - sh = config->src.h; - dw = config->dest.w; - dh = config->dest.h; - - config->dest.pitch.y=32; - config->dest.pitch.u=config->dest.pitch.v=32; - - if (mga_verbose) printf("[mga] Setting up a %dx%d-%dx%d video window (src %dx%d) format %X\n", - dw, dh, x, y, sw, sh, config->fourcc); - - if ((sw < 4) || (sh < 4) || (dw < 4) || (dh < 4)) - { - printf("[mga] Invalid src/dest dimensions\n"); - return(EINVAL); - } - - //FIXME check that window is valid and inside desktop - -// printf("[mga] vcount = %d\n", readl(mga_mmio_base + VCOUNT)); - - sw+=sw&1; - switch(config->fourcc) - { - case IMGFMT_I420: - case IMGFMT_IYUV: - case IMGFMT_YV12: - sh+=sh&1; - config->frame_size = ((sw + 31) & ~31) * sh + (((sw + 31) & ~31) * sh) / 2; - break; - case IMGFMT_YUY2: - case IMGFMT_UYVY: - config->frame_size = ((sw + 31) & ~31) * sh * 2; - break; - default: - printf("[mga] Unsupported pixel format: %x\n", config->fourcc); - return(ENOTSUP); - } - - config->offsets[0] = 0; -// config->offsets[1] = config->frame_size; -// config->offsets[2] = 2*config->frame_size; -// config->offsets[3] = 3*config->frame_size; - for (i = 1; i < config->num_frames+1; i++) - config->offsets[i] = i*config->frame_size; - - config->offset.y=0; - if(config->fourcc == IMGFMT_I420 || config->fourcc == IMGFMT_IYUV) - { - config->offset.u=((sw + 31) & ~31) * sh; - config->offset.v=config->offset.u+((sw + 31) & ~31) * sh /4; - } - else { - config->offset.v=((sw + 31) & ~31) * sh; - config->offset.u=config->offset.v+((sw + 31) & ~31) * sh /4; - } - - //FIXME figure out a better way to allocate memory on card - //allocate 2 megs - //mga_src_base = mga_mem_base + (MGA_VIDMEM_SIZE-2) * 0x100000; - //mga_src_base = (MGA_VIDMEM_SIZE-3) * 0x100000; - - mga_src_base = (mga_ram_size*0x100000-config->num_frames*config->frame_size); - if (mga_src_base < 0) - { - printf("[mga] not enough memory for frames!\n"); - return(EFAULT); - } - mga_src_base &= (~0xFFFF); /* 64k boundary */ - if (mga_verbose > 1) printf("[mga] YUV buffer base: %#x\n", mga_src_base); - - config->dga_addr = mga_mem_base + mga_src_base; - - /* for G200 set Interleaved UV planes */ - if (!is_g400) - config->flags = VID_PLAY_INTERLEAVED_UV | INTERLEAVING_UV; - - //Setup the BES registers for a three plane 4:2:0 video source - - regs.besglobctl = 0; - - switch(config->fourcc) - { - case IMGFMT_YV12: - case IMGFMT_I420: - case IMGFMT_IYUV: - regs.besctl = 1 // BES enabled - + (0<<6) // even start polarity - + (1<<10) // x filtering enabled - + (1<<11) // y filtering enabled - + (1<<16) // chroma upsampling - + (1<<17) // 4:2:0 mode - + (1<<18); // dither enabled -#if 0 - if(is_g400) - { - //zoom disabled, zoom filter disabled, 420 3 plane format, proc amp - //disabled, rgb mode disabled - regs.besglobctl = (1<<5); - } - else - { - //zoom disabled, zoom filter disabled, Cb samples in 0246, Cr - //in 1357, BES register update on besvcnt - regs.besglobctl = 0; - } -#endif - break; - - case IMGFMT_YUY2: - regs.besctl = 1 // BES enabled - + (0<<6) // even start polarity - + (1<<10) // x filtering enabled - + (1<<11) // y filtering enabled - + (1<<16) // chroma upsampling - + (0<<17) // 4:2:2 mode - + (1<<18); // dither enabled - - regs.besglobctl = 0; // YUY2 format selected - break; - - case IMGFMT_UYVY: - regs.besctl = 1 // BES enabled - + (0<<6) // even start polarity - + (1<<10) // x filtering enabled - + (1<<11) // y filtering enabled - + (1<<16) // chroma upsampling - + (0<<17) // 4:2:2 mode - + (1<<18); // dither enabled - - regs.besglobctl = 1<<6; // UYVY format selected - break; - - } - - //Disable contrast and brightness control - regs.besglobctl |= (1<<5) + (1<<7); - regs.beslumactl = (0x7f << 16) + (0x80<<0); - regs.beslumactl = 0x80<<0; - - //Setup destination window boundaries - besleft = x > 0 ? x : 0; - bestop = y > 0 ? y : 0; - regs.beshcoord = (besleft<<16) + (x + dw-1); - regs.besvcoord = (bestop<<16) + (y + dh-1); - - //Setup source dimensions - regs.beshsrclst = (sw - 1) << 16; - regs.bespitch = (sw + 31) & ~31 ; - - //Setup horizontal scaling - ifactor = ((sw-1)<<14)/(dw-1); - ofsleft = besleft - x; - - regs.beshiscal = ifactor<<2; - regs.beshsrcst = (ofsleft*ifactor)<<2; - regs.beshsrcend = regs.beshsrcst + (((dw - ofsleft - 1) * ifactor) << 2); - - //Setup vertical scaling - ifactor = ((sh-1)<<14)/(dh-1); - ofstop = bestop - y; - - regs.besviscal = ifactor<<2; - - baseadrofs = ((ofstop*regs.besviscal)>>16)*regs.bespitch; - //frame_size = ((sw + 31) & ~31) * sh + (((sw + 31) & ~31) * sh) / 2; - regs.besa1org = (uint32_t) mga_src_base + baseadrofs; - regs.besa2org = (uint32_t) mga_src_base + baseadrofs + 1*config->frame_size; - regs.besb1org = (uint32_t) mga_src_base + baseadrofs + 2*config->frame_size; - regs.besb2org = (uint32_t) mga_src_base + baseadrofs + 3*config->frame_size; - -if(config->fourcc==IMGFMT_YV12 - ||config->fourcc==IMGFMT_IYUV - ||config->fourcc==IMGFMT_I420 - ){ - // planar YUV frames: - if (is_g400) - baseadrofs = (((ofstop*regs.besviscal)/4)>>16)*regs.bespitch; - else - baseadrofs = (((ofstop*regs.besviscal)/2)>>16)*regs.bespitch; - - if(config->fourcc==IMGFMT_YV12){ - regs.besa1corg = (uint32_t) mga_src_base + baseadrofs + regs.bespitch * sh ; - regs.besa2corg = (uint32_t) mga_src_base + baseadrofs + 1*config->frame_size + regs.bespitch * sh; - regs.besb1corg = (uint32_t) mga_src_base + baseadrofs + 2*config->frame_size + regs.bespitch * sh; - regs.besb2corg = (uint32_t) mga_src_base + baseadrofs + 3*config->frame_size + regs.bespitch * sh; - regs.besa1c3org = regs.besa1corg + ((regs.bespitch * sh) / 4); - regs.besa2c3org = regs.besa2corg + ((regs.bespitch * sh) / 4); - regs.besb1c3org = regs.besb1corg + ((regs.bespitch * sh) / 4); - regs.besb2c3org = regs.besb2corg + ((regs.bespitch * sh) / 4); - } else { - regs.besa1c3org = (uint32_t) mga_src_base + baseadrofs + regs.bespitch * sh ; - regs.besa2c3org = (uint32_t) mga_src_base + baseadrofs + 1*config->frame_size + regs.bespitch * sh; - regs.besb1c3org = (uint32_t) mga_src_base + baseadrofs + 2*config->frame_size + regs.bespitch * sh; - regs.besb2c3org = (uint32_t) mga_src_base + baseadrofs + 3*config->frame_size + regs.bespitch * sh; - regs.besa1corg = regs.besa1c3org + ((regs.bespitch * sh) / 4); - regs.besa2corg = regs.besa2c3org + ((regs.bespitch * sh) / 4); - regs.besb1corg = regs.besb1c3org + ((regs.bespitch * sh) / 4); - regs.besb2corg = regs.besb2c3org + ((regs.bespitch * sh) / 4); - } - -} - - weight = ofstop * (regs.besviscal >> 2); - weights = weight < 0 ? 1 : 0; - regs.besv2wght = regs.besv1wght = (weights << 16) + ((weight & 0x3FFF) << 2); - regs.besv2srclst = regs.besv1srclst = sh - 1 - (((ofstop * regs.besviscal) >> 16) & 0x03FF); - -#ifdef CRTC2 - // pridat hlavni registry - tj. casovani ... - - -switch(config->fourcc){ - case IMGFMT_YV12: - case IMGFMT_I420: - case IMGFMT_IYUV: - cregs.c2ctl = 1 // CRTC2 enabled - + (1<<1) // external clock - + (0<<2) // external clock - + (1<<3) // pixel clock enable - not needed ??? - + (0<<4) // high prioryty req - + (1<<5) // high prioryty req - + (0<<6) // high prioryty req - + (1<<8) // high prioryty req max - + (0<<9) // high prioryty req max - + (0<<10) // high prioryty req max - + (0<<20) // CRTC1 to DAC - + (1<<21) // 420 mode - + (1<<22) // 420 mode - + (1<<23) // 420 mode - + (0<<24) // single chroma line for 420 mode - need to be corrected - + (0<<25) /*/ interlace mode - need to be corrected*/ - + (0<<26) // field legth polariry - + (0<<27) // field identification polariry - + (1<<28) // VIDRST detection mode - + (0<<29) // VIDRST detection mode - + (1<<30) // Horizontal counter preload - + (1<<31) // Vertical counter preload - ; - cregs.c2datactl = 1 // disable dither - propably not needed, we are already in YUV mode - + (1<<1) // Y filter enable - + (1<<2) // CbCr filter enable - + (0<<3) // subpicture enable (disabled) - + (0<<4) // NTSC enable (disabled - PAL) - + (0<<5) // C2 static subpicture enable (disabled) - + (0<<6) // C2 subpicture offset division (disabled) - + (0<<7) // 422 subformat selection ! -/* + (0<<8) // 15 bpp high alpha - + (0<<9) // 15 bpp high alpha - + (0<<10) // 15 bpp high alpha - + (0<<11) // 15 bpp high alpha - + (0<<12) // 15 bpp high alpha - + (0<<13) // 15 bpp high alpha - + (0<<14) // 15 bpp high alpha - + (0<<15) // 15 bpp high alpha - + (0<<16) // 15 bpp low alpha - + (0<<17) // 15 bpp low alpha - + (0<<18) // 15 bpp low alpha - + (0<<19) // 15 bpp low alpha - + (0<<20) // 15 bpp low alpha - + (0<<21) // 15 bpp low alpha - + (0<<22) // 15 bpp low alpha - + (0<<23) // 15 bpp low alpha - + (0<<24) // static subpicture key - + (0<<25) // static subpicture key - + (0<<26) // static subpicture key - + (0<<27) // static subpicture key - + (0<<28) // static subpicture key -*/ ; - break; - - case IMGFMT_YUY2: - cregs.c2ctl = 1 // CRTC2 enabled - + (1<<1) // external clock - + (0<<2) // external clock - + (1<<3) // pixel clock enable - not needed ??? - + (0<<4) // high prioryty req - acc to spec - + (1<<5) // high prioryty req - + (0<<6) // high prioryty req - // 7 reserved - + (1<<8) // high prioryty req max - + (0<<9) // high prioryty req max - + (0<<10) // high prioryty req max - // 11-19 reserved - + (0<<20) // CRTC1 to DAC - + (1<<21) // 422 mode - + (0<<22) // 422 mode - + (1<<23) // 422 mode - + (0<<24) // single chroma line for 420 mode - need to be corrected - + (0<<25) /*/ interlace mode - need to be corrected*/ - + (0<<26) // field legth polariry - + (0<<27) // field identification polariry - + (1<<28) // VIDRST detection mode - + (0<<29) // VIDRST detection mode - + (1<<30) // Horizontal counter preload - + (1<<31) // Vertical counter preload - ; - cregs.c2datactl = 1 // disable dither - propably not needed, we are already in YUV mode - + (1<<1) // Y filter enable - + (1<<2) // CbCr filter enable - + (0<<3) // subpicture enable (disabled) - + (0<<4) // NTSC enable (disabled - PAL) - + (0<<5) // C2 static subpicture enable (disabled) - + (0<<6) // C2 subpicture offset division (disabled) - + (0<<7) // 422 subformat selection ! -/* + (0<<8) // 15 bpp high alpha - + (0<<9) // 15 bpp high alpha - + (0<<10) // 15 bpp high alpha - + (0<<11) // 15 bpp high alpha - + (0<<12) // 15 bpp high alpha - + (0<<13) // 15 bpp high alpha - + (0<<14) // 15 bpp high alpha - + (0<<15) // 15 bpp high alpha - + (0<<16) // 15 bpp low alpha - + (0<<17) // 15 bpp low alpha - + (0<<18) // 15 bpp low alpha - + (0<<19) // 15 bpp low alpha - + (0<<20) // 15 bpp low alpha - + (0<<21) // 15 bpp low alpha - + (0<<22) // 15 bpp low alpha - + (0<<23) // 15 bpp low alpha - + (0<<24) // static subpicture key - + (0<<25) // static subpicture key - + (0<<26) // static subpicture key - + (0<<27) // static subpicture key - + (0<<28) // static subpicture key -*/ ; - break; - - case IMGFMT_UYVY: - cregs.c2ctl = 1 // CRTC2 enabled - + (1<<1) // external clock - + (0<<2) // external clock - + (1<<3) // pixel clock enable - not needed ??? - + (0<<4) // high prioryty req - + (1<<5) // high prioryty req - + (0<<6) // high prioryty req - + (1<<8) // high prioryty req max - + (0<<9) // high prioryty req max - + (0<<10) // high prioryty req max - + (0<<20) // CRTC1 to DAC - + (1<<21) // 422 mode - + (0<<22) // 422 mode - + (1<<23) // 422 mode - + (1<<24) // single chroma line for 420 mode - need to be corrected - + (1<<25) /*/ interlace mode - need to be corrected*/ - + (0<<26) // field legth polariry - + (0<<27) // field identification polariry - + (1<<28) // VIDRST detection mode - + (0<<29) // VIDRST detection mode - + (1<<30) // Horizontal counter preload - + (1<<31) // Vertical counter preload - ; - cregs.c2datactl = 0 // enable dither - propably not needed, we are already in YUV mode - + (1<<1) // Y filter enable - + (1<<2) // CbCr filter enable - + (0<<3) // subpicture enable (disabled) - + (0<<4) // NTSC enable (disabled - PAL) - + (0<<5) // C2 static subpicture enable (disabled) - + (0<<6) // C2 subpicture offset division (disabled) - + (1<<7) // 422 subformat selection ! -/* + (0<<8) // 15 bpp high alpha - + (0<<9) // 15 bpp high alpha - + (0<<10) // 15 bpp high alpha - + (0<<11) // 15 bpp high alpha - + (0<<12) // 15 bpp high alpha - + (0<<13) // 15 bpp high alpha - + (0<<14) // 15 bpp high alpha - + (0<<15) // 15 bpp high alpha - + (0<<16) // 15 bpp low alpha - + (0<<17) // 15 bpp low alpha - + (0<<18) // 15 bpp low alpha - + (0<<19) // 15 bpp low alpha - + (0<<20) // 15 bpp low alpha - + (0<<21) // 15 bpp low alpha - + (0<<22) // 15 bpp low alpha - + (0<<23) // 15 bpp low alpha - + (0<<24) // static subpicture key - + (0<<25) // static subpicture key - + (0<<26) // static subpicture key - + (0<<27) // static subpicture key - + (0<<28) // static subpicture key -*/ ; - break; - } - - cregs.c2hparam=((hdispend - 8) << 16) | (htotal - 8); - cregs.c2hsync=((hsyncend - 8) << 16) | (hsyncstart - 8); - - cregs.c2misc=0 // CRTCV2 656 togg f0 - +(0<<1) // CRTCV2 656 togg f0 - +(0<<2) // CRTCV2 656 togg f0 - +(0<<4) // CRTCV2 656 togg f1 - +(0<<5) // CRTCV2 656 togg f1 - +(0<<6) // CRTCV2 656 togg f1 - +(0<<8) // Hsync active high - +(0<<9) // Vsync active high - // 16-27 c2vlinecomp - nevim co tam dat - ; - cregs.c2offset=(regs.bespitch << 1); - - cregs.c2pl2startadd0=regs.besa1corg; -// cregs.c2pl2startadd1=regs.besa2corg; - cregs.c2pl3startadd0=regs.besa1c3org; -// cregs.c2pl3startadd1=regs.besa2c3org; - - cregs.c2preload=(vsyncstart << 16) | (hsyncstart); // from - - cregs.c2spicstartadd0=0; // not used -// cregs.c2spicstartadd1=0; // not used - - cregs.c2startadd0=regs.besa1org; -// cregs.c2startadd1=regs.besa2org; - - cregs.c2subpiclut=0; //not used - - cregs.c2vparam=((vdispend - 1) << 16) | (vtotal - 1); - cregs.c2vsync=((vsyncend - 1) << 16) | (vsyncstart - 1); -#endif /* CRTC2 */ - - mga_vid_write_regs(0); - return(0); -} - -int vixPlaybackOn(void) -{ - if (mga_verbose) printf("[mga] playback on\n"); - - vid_src_ready = 1; - if(vid_overlay_on) - { - regs.besctl |= 1; - mga_vid_write_regs(0); - } -#ifdef MGA_ALLOW_IRQ - if (mga_irq != -1) - enable_irq(); -#endif - mga_next_frame=0; - - return(0); -} - -int vixPlaybackOff(void) -{ - if (mga_verbose) printf("[mga] playback off\n"); - - vid_src_ready = 0; -#ifdef MGA_ALLOW_IRQ - if (mga_irq != -1) - disable_irq(); -#endif - regs.besctl &= ~1; - regs.besglobctl &= ~(1<<6); /* UYVY format selected */ - mga_vid_write_regs(0); - - return(0); -} - -int vixProbe(int verbose,int force) -{ - pciinfo_t lst[MAX_PCI_DEVICES]; - unsigned int i, num_pci; - int err; - - if (verbose) printf("[mga] probe\n"); - - mga_verbose = verbose; - - is_g400 = -1; - - err = pci_scan(lst, &num_pci); - if (err) - { - printf("[mga] Error occurred during pci scan: %s\n", strerror(err)); - return(err); - } - - if (mga_verbose) - printf("[mga] found %d pci devices\n", num_pci); - - for (i = 0; i < num_pci; i++) - { - if (mga_verbose > 1) - printf("[mga] pci[%d] vendor: %d device: %d\n", - i, lst[i].vendor, lst[i].device); - if (lst[i].vendor == VENDOR_MATROX) - { - if ((lst[i].command & PCI_COMMAND_IO) == 0) - { - printf("[mga] Device is disabled, ignoring\n"); - continue; - } - switch(lst[i].device) - { - case DEVICE_MATROX_MGA_G550_AGP: - printf("[mga] Found MGA G550\n"); - is_g400 = 1; - goto card_found; - case DEVICE_MATROX_MGA_G400_AGP: - printf("[mga] Found MGA G400/G450\n"); - is_g400 = 1; - goto card_found; - case DEVICE_MATROX_MGA_G200_AGP: - printf("[mga] Found MGA G200 AGP\n"); - is_g400 = 0; - goto card_found; - case DEVICE_MATROX_MGA_G200: - printf("[mga] Found MGA G200 PCI\n"); - is_g400 = 0; - goto card_found; - } - } - } - - if (is_g400 == -1) - { - if (verbose) printf("[mga] Can't find chip\n"); - return(ENXIO); - } - -card_found: - probed = 1; - memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); - - mga_cap.device_id = pci_info.device; /* set device id in capabilites */ - - return(0); -} - -int vixInit(void) -{ - unsigned int card_option = 0; - int err; - - if (mga_verbose) printf("[mga] init\n"); - - mga_vid_in_use = 0; - - printf("Matrox MGA G200/G400/G450 YUV Video interface v2.01 (c) Aaron Holtzman & A'rpi\n"); -#ifdef CRCT2 - printf("Driver compiled with TV-out (second-head) support\n"); -#endif - - if (!probed) - { - printf("[mga] driver was not probed but is being initializing\n"); - return(EINTR); - } - -#ifdef MGA_PCICONFIG_MEMDETECT - pci_config_read(pci_info.bus, pci_info.card, pci_info.func, - 0x40, 4, &card_option); - if (mga_verbose > 1) printf("[mga] OPTION word: 0x%08X mem: 0x%02X %s\n", card_option, - (card_option>>10)&0x17, ((card_option>>14)&1)?"SGRAM":"SDRAM"); -#endif - - if (mga_ram_size) - { - printf("[mga] RAMSIZE forced to %d MB\n", mga_ram_size); - } - else - { -#ifdef MGA_MEMORY_SIZE - mga_ram_size = MGA_MEMORY_SIZE; - printf("[mga] hard-coded RAMSIZE is %d MB\n", (unsigned int) mga_ram_size); -#else - if (is_g400) - { - switch((card_option>>10)&0x17) - { - // SDRAM: - case 0x00: - case 0x04: mga_ram_size = 16; break; - case 0x03: mga_ram_size = 32; break; - // SGRAM: - case 0x10: - case 0x14: mga_ram_size = 32; break; - case 0x11: - case 0x12: mga_ram_size = 16; break; - default: - mga_ram_size = 16; - printf("[mga] Couldn't detect RAMSIZE, assuming 16MB!\n"); - } - } - else - { - switch((card_option>>10)&0x17) - { -// case 0x10: -// case 0x13: mga_ram_size = 8; break; - default: mga_ram_size = 8; - } - } - -#if 0 -// printf("List resources -----------\n"); - for(temp=0;temp<DEVICE_COUNT_RESOURCE;temp++){ - struct resource *res=&pci_dev->resource[temp]; - if(res->flags){ - int size=(1+res->end-res->start)>>20; - printf("res %d: start: 0x%X end: 0x%X (%d MB) flags=0x%X\n",temp,res->start,res->end,size,res->flags); - if(res->flags&(IORESOURCE_MEM|IORESOURCE_PREFETCH)){ - if(size>mga_ram_size && size<=64) mga_ram_size=size; - } - } - } -#endif - - printf("[mga] detected RAMSIZE is %d MB\n", (unsigned int) mga_ram_size); -#endif - } - - if (mga_ram_size) - { - if ((mga_ram_size < 4) || (mga_ram_size > 64)) - { - printf("[mga] invalid RAMSIZE: %d MB\n", mga_ram_size); - return(EINVAL); - } - } - - if (mga_verbose > 1) printf("[mga] hardware addresses: mmio: %#x, framebuffer: %#x\n", - pci_info.base1, pci_info.base0); - - mga_mmio_base = map_phys_mem(pci_info.base1,0x4000); - mga_mem_base = map_phys_mem(pci_info.base0,mga_ram_size*1024*1024); - - if (mga_verbose > 1) printf("[mga] MMIO at %p, IRQ: %d, framebuffer: %p\n", - mga_mmio_base, mga_irq, mga_mem_base); - err = mtrr_set_type(pci_info.base0,mga_ram_size*1024*1024,MTRR_TYPE_WRCOMB); - if(!err) printf("[mga] Set write-combining type of video memory\n"); -#ifdef MGA_ALLOW_IRQ - if (mga_irq != -1) - { - int tmp = request_irq(mga_irq, mga_handle_irq, SA_INTERRUPT | SA_SHIRQ, "Syncfb Time Base", &mga_irq); - if (tmp) - { - printf("syncfb (mga): cannot register irq %d (Err: %d)\n", mga_irq, tmp); - mga_irq=-1; - } - else - { - printf("syncfb (mga): registered irq %d\n", mga_irq); - } - } - else - { - printf("syncfb (mga): No valid irq was found\n"); - mga_irq=-1; - } -#else - printf("syncfb (mga): IRQ disabled in mga_vid.c\n"); - mga_irq=-1; -#endif - - return(0); -} - -void vixDestroy(void) -{ - if (mga_verbose) printf("[mga] destroy\n"); - - /* FIXME turn off BES */ - vid_src_ready = 0; - regs.besctl &= ~1; - regs.besglobctl &= ~(1<<6); // UYVY format selected -// mga_config.colkey_on=0; //!!! - mga_vid_write_regs(1); - mga_vid_in_use = 0; - -#ifdef MGA_ALLOW_IRQ - if (mga_irq != -1) - free_irq(mga_irq, &mga_irq); -#endif - - if (mga_mmio_base) - unmap_phys_mem(mga_mmio_base, 0x4000); - if (mga_mem_base) - unmap_phys_mem(mga_mem_base, mga_ram_size); - return; -} - -int vixQueryFourcc(vidix_fourcc_t *to) -{ - if (mga_verbose) printf("[mga] query fourcc (%x)\n", to->fourcc); - - switch(to->fourcc) - { - case IMGFMT_YV12: - case IMGFMT_IYUV: - case IMGFMT_I420: - case IMGFMT_YUY2: - case IMGFMT_UYVY: - break; - default: - to->depth = to->flags = 0; - return(ENOTSUP); - } - - to->depth = VID_DEPTH_12BPP | - VID_DEPTH_15BPP | VID_DEPTH_16BPP | - VID_DEPTH_24BPP | VID_DEPTH_32BPP; - to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; - return(0); -} - -unsigned int vixGetVersion(void) -{ - return(VIDIX_VERSION); -} - -int vixGetCapability(vidix_capability_t *to) -{ - memcpy(to, &mga_cap, sizeof(vidix_capability_t)); - return(0); -} - -int vixGetGrKeys(vidix_grkey_t *grkey) -{ - memcpy(grkey, &mga_grkey, sizeof(vidix_grkey_t)); - return(0); -} - -int vixSetGrKeys(const vidix_grkey_t *grkey) -{ - memcpy(&mga_grkey, grkey, sizeof(vidix_grkey_t)); - mga_vid_write_regs(0); - return(0); -} - -int vixPlaybackSetEq( const vidix_video_eq_t * eq) -{ - /* contrast and brightness control isn't supported on G200 - alex */ - if (!is_g400) - { - if (mga_verbose) printf("[mga] equalizer isn't supported with G200\n"); - return(ENOTSUP); - } - - // only brightness&contrast are supported: - if(!(eq->cap & (VEQ_CAP_BRIGHTNESS|VEQ_CAP_CONTRAST))) - return(ENOTSUP); - - //regs.beslumactl = readl(mga_mmio_base + BESLUMACTL); -// printf("LUMA = %08X \n",regs.beslumactl); - if (eq->cap & VEQ_CAP_BRIGHTNESS) { - regs.beslumactl &= 0xFFFF; - regs.beslumactl |= (eq->brightness*255/2000)<<16; - } - if (eq->cap & VEQ_CAP_CONTRAST) { - regs.beslumactl &= 0xFFFF0000; - regs.beslumactl |= (128+eq->contrast*255/2000)&0xFFFF; - } - writel(regs.beslumactl,mga_mmio_base + BESLUMACTL); - - return(0); -} - -int vixPlaybackGetEq( vidix_video_eq_t * eq) -{ - /* contrast and brightness control isn't supported on G200 - alex */ - if (!is_g400) - { - if (mga_verbose) printf("[mga] equalizer isn't supported with G200\n"); - return(ENOTSUP); - } - -// regs.beslumactl = readl(mga_mmio_base + BESLUMACTL); - - eq->brightness = (signed short int)(regs.beslumactl >> 16) * 1000 / 128; - eq->contrast = (signed short int)(regs.beslumactl & 0xFFFF) * 1000 / 128 - 1000; - eq->cap = VEQ_CAP_BRIGHTNESS | VEQ_CAP_CONTRAST; - - printf("MGA GET_EQ: br=%d c=%d \n",eq->brightness,eq->contrast); - - return(0); -}
--- a/vidix/drivers/nvidia_vid.c Sat Mar 31 23:48:48 2007 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,935 +0,0 @@ -/* - nvidia_vid - VIDIX based video driver for NVIDIA chips - Copyrights 2003 - 2004 Sascha Sommer. This file is based on sources from - RIVATV (rivatv.sf.net) - Licence: GPL - WARNING: THIS DRIVER IS IN BETA STAGE - - multi buffer support and TNT2 fixes by Dmitry Baryshkov -*/ - - -#include <errno.h> -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include <math.h> -#include <inttypes.h> -#include <unistd.h> - - -#include "../vidix.h" -#include "../fourcc.h" -#include "../../libdha/libdha.h" -#include "../../libdha/pci_ids.h" -#include "../../libdha/pci_names.h" -#include "../../config.h" -#include "../../libavutil/common.h" -#include "../../mpbswap.h" - - -pciinfo_t pci_info; - - -#define MAX_FRAMES 3 -#define NV04_BES_SIZE 1024*2000*4 - - -static vidix_capability_t nvidia_cap = { - "NVIDIA RIVA OVERLAY DRIVER", - "Sascha Sommer <saschasommer@freenet.de>", - TYPE_OUTPUT, - { 0, 0, 0, 0 }, - 2046, - 2046, - 4, - 4, - -1, - FLAG_UPSCALER|FLAG_DOWNSCALER, - VENDOR_NVIDIA2, - -1, - { 0, 0, 0, 0 } -}; - - -unsigned int vixGetVersion(void){ - return(VIDIX_VERSION); -} - - -#define NV_ARCH_03 0x03 -#define NV_ARCH_04 0x04 -#define NV_ARCH_10 0x10 -#define NV_ARCH_20 0x20 -#define NV_ARCH_30 0x30 - -// since no useful information whatsoever is passed -// to the equalizer functions we need this -static struct { - uint32_t lum; // luminance (brightness + contrast) - uint32_t chrom; // chrominance (saturation + hue) - uint8_t red_off; // for NV03/NV04 - uint8_t green_off; - uint8_t blue_off; - vidix_video_eq_t vals; -} eq; - -struct nvidia_cards { - unsigned short chip_id; - unsigned short arch; -}; - - -static struct nvidia_cards nvidia_card_ids[] = { - /*NV03*/ - {DEVICE_NVIDIA2_RIVA128, NV_ARCH_03}, - {DEVICE_NVIDIA2_RIVA128ZX,NV_ARCH_03}, - /*NV04*/ - {DEVICE_NVIDIA_NV4_RIVA_TNT,NV_ARCH_04}, - {DEVICE_NVIDIA_NV5_RIVA_TNT2,NV_ARCH_04}, - {DEVICE_NVIDIA_NV5_RIVA_TNT22,NV_ARCH_04}, - {DEVICE_NVIDIA_NV5_RIVA_TNT23,NV_ARCH_04}, - {DEVICE_NVIDIA_NV5_RIVA_TNT24,NV_ARCH_04}, - {DEVICE_NVIDIA_NV6_VANTA,NV_ARCH_04}, - {DEVICE_NVIDIA_RIVA_TNT2_MODEL,NV_ARCH_04}, - {DEVICE_NVIDIA_NV6_VANTA2,NV_ARCH_04}, - {DEVICE_NVIDIA_NV6_VANTA3,NV_ARCH_04}, - {DEVICE_NVIDIA_NV5_RIVA_TNT25,NV_ARCH_04}, - {DEVICE_NVIDIA2_TNT,NV_ARCH_04}, - {DEVICE_NVIDIA2_TNT2,NV_ARCH_04}, - {DEVICE_NVIDIA2_VTNT2,NV_ARCH_04}, - {DEVICE_NVIDIA2_UTNT2 ,NV_ARCH_04}, - {DEVICE_NVIDIA2_ITNT2,NV_ARCH_04}, - /*NV10*/ - {DEVICE_NVIDIA_NV10_GEFORCE_256,NV_ARCH_10}, - {DEVICE_NVIDIA_NV10_GEFORCE_2562,NV_ARCH_10}, - {DEVICE_NVIDIA_NV11_GEFORCE2_MX,NV_ARCH_10}, - {DEVICE_NVIDIA_NV11_GEFORCE2_MX2,NV_ARCH_10}, - {DEVICE_NVIDIA_NV11_GEFORCE2_GO,NV_ARCH_10}, - {DEVICE_NVIDIA_NV11_GEFORCE2_MXR ,NV_ARCH_10}, - {DEVICE_NVIDIA_NV15_GEFORCE2_GTS,NV_ARCH_10}, - {DEVICE_NVIDIA_NV15_GEFORCE2_TI,NV_ARCH_10}, - {DEVICE_NVIDIA_NV15_GEFORCE2_ULTRA,NV_ARCH_10}, - {DEVICE_NVIDIA_NV17_GEFORCE4_MX460,NV_ARCH_10}, - {DEVICE_NVIDIA_NV17_GEFORCE4_MX440,NV_ARCH_10}, - {DEVICE_NVIDIA_NV17_GEFORCE4_MX420,NV_ARCH_10}, - {DEVICE_NVIDIA_NV17_GEFORCE4_440,NV_ARCH_10}, - {DEVICE_NVIDIA_NV17_GEFORCE4_420,NV_ARCH_10}, - {DEVICE_NVIDIA_NV17_GEFORCE4_4202,NV_ARCH_10}, - {DEVICE_NVIDIA_NV17_GEFORCE4_4402,NV_ARCH_10}, - {DEVICE_NVIDIA_NV18_GEFORCE4_MX440,NV_ARCH_10}, - {DEVICE_NVIDIA_NV15_GEFORCE2,NV_ARCH_10}, - /*NV20*/ - {DEVICE_NVIDIA_NV20_GEFORCE3,NV_ARCH_20}, - {DEVICE_NVIDIA_NV20_GEFORCE3_TI200,NV_ARCH_20}, - {DEVICE_NVIDIA_NV20_GEFORCE3_TI500,NV_ARCH_20}, - {DEVICE_NVIDIA_NV25_GEFORCE4_TI4600,NV_ARCH_20}, - {DEVICE_NVIDIA_NV25_GEFORCE4_TI4400,NV_ARCH_20}, - {DEVICE_NVIDIA_NV25_GEFORCE4_TI4200,NV_ARCH_20}, - {DEVICE_NVIDIA_QUADRO4_900XGL,NV_ARCH_20}, - {DEVICE_NVIDIA_QUADRO4_750XGL,NV_ARCH_20}, - {DEVICE_NVIDIA_QUADRO4_700XGL,NV_ARCH_20}, - {DEVICE_NVIDIA_NV28_GEFORCE4_TI,NV_ARCH_20}, - {DEVICE_NVIDIA_NV28_GEFORCE4_TI2,NV_ARCH_20}, - {DEVICE_NVIDIA_NV28_GEFORCE4_TI3,NV_ARCH_20}, - {DEVICE_NVIDIA_NV28_GEFORCE4_TI4,NV_ARCH_20}, - {DEVICE_NVIDIA_NV28GL_QUADRO4_980,NV_ARCH_20}, - {DEVICE_NVIDIA_NV28GL_QUADRO4_780,NV_ARCH_20}, - /*NV30*/ - {DEVICE_NVIDIA_NV30_GEFORCE_FX,NV_ARCH_30}, - {DEVICE_NVIDIA_NV30_GEFORCE_FX2,NV_ARCH_30}, - {DEVICE_NVIDIA_NV30_GEFORCE_FX3,NV_ARCH_30}, - {DEVICE_NVIDIA_NV30GL_QUADRO_FX,NV_ARCH_30}, - {DEVICE_NVIDIA_NV30GL_QUADRO_FX2,NV_ARCH_30}, - {DEVICE_NVIDIA_NV31_GEFORCE_FX,NV_ARCH_30}, - {DEVICE_NVIDIA_NV31_GEFORCE_FX2,NV_ARCH_30}, - {DEVICE_NVIDIA_NV34_GEFORCE_FX,NV_ARCH_30}, - {DEVICE_NVIDIA_NV34_GEFORCE_FX2,NV_ARCH_30}, - {DEVICE_NVIDIA_NV34_GEFORCE_FX3,NV_ARCH_30}, - {DEVICE_NVIDIA_NV34M_GEFORCE_FX,NV_ARCH_30}, - {DEVICE_NVIDIA_NV34GL_QUADRO_FX,NV_ARCH_30}, - {DEVICE_NVIDIA_NV35_GEFORCE_FX,NV_ARCH_30}, - {DEVICE_NVIDIA_NV35_GEFORCE_FX2,NV_ARCH_30}, - {DEVICE_NVIDIA_NV35GL_QUADRO_FX,NV_ARCH_30}, - {DEVICE_NVIDIA_NV36_GEFORCE_FX,NV_ARCH_30}, -}; - - -static int find_chip(unsigned chip_id){ - unsigned i; - for(i = 0;i < sizeof(nvidia_card_ids)/sizeof(struct nvidia_cards);i++) - { - if(chip_id == nvidia_card_ids[i].chip_id)return i; - } - return -1; -} - -int vixProbe(int verbose, int force){ - pciinfo_t lst[MAX_PCI_DEVICES]; - unsigned i,num_pci; - int err; - - if (force) - printf("[nvidia_vid]: warning: forcing not supported yet!\n"); - err = pci_scan(lst,&num_pci); - if(err){ - printf("[nvidia_vid] Error occurred during pci scan: %s\n",strerror(err)); - return err; - } - else { - err = ENXIO; - for(i=0; i < num_pci; i++){ - if(lst[i].vendor == VENDOR_NVIDIA2 || lst[i].vendor == VENDOR_NVIDIA){ - int idx; - const char *dname; - idx = find_chip(lst[i].device); - if(idx == -1) - continue; - dname = pci_device_name(lst[i].vendor, lst[i].device); - dname = dname ? dname : "Unknown chip"; - printf("[nvidia_vid] Found chip: %s\n", dname); - if ((lst[i].command & PCI_COMMAND_IO) == 0){ - printf("[nvidia_vid] Device is disabled, ignoring\n"); - continue; - } - nvidia_cap.device_id = lst[i].device; - err = 0; - memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); - break; - } - } - } - if(err && verbose) printf("[nvidia_vid] Can't find chip\n"); - return err; -} - - - - -/* - * PCI-Memory IO access macros. - */ - -#define MEM_BARRIER() __asm__ __volatile__ ("" : : : "memory") - -#undef VID_WR08 -#define VID_WR08(p,i,val) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]=(val); }) -#undef VID_RD08 -#define VID_RD08(p,i) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]; }) - -#undef VID_WR32 -#define VID_WR32(p,i,val) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]=val; }) -#undef VID_RD32 -#define VID_RD32(p,i) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]; }) - -#define VID_AND32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)&(val)) -#define VID_OR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)|(val)) -#define VID_XOR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)^(val)) - - - - - - -struct rivatv_chip { - volatile uint32_t *PMC; /* general control */ - volatile uint32_t *PME; /* multimedia port */ - volatile uint32_t *PFB; /* framebuffer control */ - volatile uint32_t *PVIDEO; /* overlay control */ - volatile uint8_t *PCIO; /* SVGA (CRTC, ATTR) registers */ - volatile uint8_t *PVIO; /* SVGA (MISC, GRAPH, SEQ) registers */ - volatile uint32_t *PRAMIN; /* instance memory */ - volatile uint32_t *PRAMHT; /* hash table */ - volatile uint32_t *PRAMFC; /* fifo context table */ - volatile uint32_t *PRAMRO; /* fifo runout table */ - volatile uint32_t *PFIFO; /* fifo control region */ - volatile uint32_t *FIFO; /* fifo channels (USER) */ - volatile uint32_t *PGRAPH; /* graphics engine */ - - unsigned long fbsize; /* framebuffer size */ - int arch; /* compatible NV_ARCH_XX define */ - int realarch; /* real architecture */ - void (* lock) (struct rivatv_chip *, int); -}; -typedef struct rivatv_chip rivatv_chip; - - -struct rivatv_info { - unsigned int use_colorkey; - unsigned int colorkey; /* saved xv colorkey*/ - unsigned int vidixcolorkey; /*currently used colorkey*/ - unsigned int depth; - unsigned int format; - unsigned int pitch; - unsigned int width,height; - unsigned int d_width,d_height; /*scaled width && height*/ - unsigned int wx,wy; /*window x && y*/ - unsigned int screen_x; /*screen width*/ - unsigned int screen_y; /*screen height*/ - unsigned long buffer_size; /* size of the image buffer */ - struct rivatv_chip chip; /* NV architecture structure */ - void* video_base; /* virtual address of control region */ - void* control_base; /* virtual address of fb region */ - void* picture_base; /* direct pointer to video picture */ - unsigned long picture_offset; /* offset of video picture in frame buffer */ -// struct rivatv_dma dma; /* DMA structure */ - unsigned int cur_frame; - unsigned int num_frames; /* number of buffers */ - int bps; /* bytes per line */ -}; -typedef struct rivatv_info rivatv_info; - -//framebuffer size funcs -static unsigned long rivatv_fbsize_nv03 (struct rivatv_chip *chip){ - if (VID_RD32 (chip->PFB, 0) & 0x00000020) { - if (((VID_RD32 (chip->PMC, 0) & 0xF0) == 0x20) - && ((VID_RD32 (chip->PMC, 0) & 0x0F) >= 0x02)) { - /* SDRAM 128 ZX. */ - return ((1 << (VID_RD32 (chip->PFB, 0) & 0x03)) * 1024 * 1024); - } - else { - return 1024 * 1024 * 8; - } - } - else { - /* SGRAM 128. */ - switch (VID_RD32(chip->PFB, 0) & 0x00000003) { - case 0: - return 1024 * 1024 * 8; - break; - case 2: - return 1024 * 1024 * 4; - break; - default: - return 1024 * 1024 * 2; - break; - } - } -} -static unsigned long rivatv_fbsize_nv04 (struct rivatv_chip *chip){ - if (VID_RD32 (chip->PFB, 0) & 0x00000100) { - return ((VID_RD32 (chip->PFB, 0) >> 12) & 0x0F) * 1024 * 1024 * 2 - + 1024 * 1024 * 2; - } else { - switch (VID_RD32 (chip->PFB, 0) & 0x00000003) { - case 0: - return 1024 * 1024 * 32; - break; - case 1: - return 1024 * 1024 * 4; - break; - case 2: - return 1024 * 1024 * 8; - break; - case 3: - default: - return 1024 * 1024 * 16; - break; - } - } -} - -static unsigned long rivatv_fbsize_nv10 (struct rivatv_chip *chip){ - return VID_RD32 (chip->PFB, 0x20C) & 0xFFF00000; -} - -//lock funcs -static void rivatv_lock_nv03 (struct rivatv_chip *chip, int LockUnlock){ - VID_WR08 (chip->PVIO, 0x3C4, 0x06); - VID_WR08 (chip->PVIO, 0x3C5, LockUnlock ? 0x99 : 0x57); -} - -static void rivatv_lock_nv04 (struct rivatv_chip *chip, int LockUnlock){ - VID_WR08 (chip->PCIO, 0x3C4, 0x06); - VID_WR08 (chip->PCIO, 0x3C5, LockUnlock ? 0x99 : 0x57); - VID_WR08 (chip->PCIO, 0x3D4, 0x1F); - VID_WR08 (chip->PCIO, 0x3D5, LockUnlock ? 0x99 : 0x57); -} - - - - -/* Enable PFB (Framebuffer), PVIDEO (Overlay unit) and PME (Mediaport) if neccessary. */ -static void rivatv_enable_PMEDIA (struct rivatv_info *info){ - uint32_t reg; - - /* switch off interrupts once for a while */ -// VID_WR32 (info->chip.PME, 0x200140, 0x00); -// VID_WR32 (info->chip.PMC, 0x000140, 0x00); - - reg = VID_RD32 (info->chip.PMC, 0x000200); - - /* NV3 (0x10100010): NV03_PMC_ENABLE_PMEDIA, NV03_PMC_ENABLE_PFB, NV03_PMC_ENABLE_PVIDEO */ - - if ((reg & 0x10100010) != 0x10100010) { - printf("PVIDEO and PFB disabled, enabling...\n"); - VID_OR32 (info->chip.PMC, 0x000200, 0x10100010); - } - - /* save the current colorkey */ - switch (info->chip.arch ) { - case NV_ARCH_10: - case NV_ARCH_20: - case NV_ARCH_30: - /* NV_PVIDEO_COLOR_KEY */ - info->colorkey = VID_RD32 (info->chip.PVIDEO, 0xB00); - break; - case NV_ARCH_03: - case NV_ARCH_04: - /* NV_PVIDEO_KEY */ - info->colorkey = VID_RD32 (info->chip.PVIDEO, 0x240); - break; - } - - - /* re-enable interrupts again */ -// VID_WR32 (info->chip.PMC, 0x000140, 0x01); -// VID_WR32 (info->chip.PME, 0x200140, 0x01); -} - -/* Stop overlay video. */ -static void rivatv_overlay_stop (struct rivatv_info *info) { - switch (info->chip.arch ) { - case NV_ARCH_10: - case NV_ARCH_20: - case NV_ARCH_30: - /* NV_PVIDEO_COLOR_KEY */ - /* Xv-Extension-Hack: Restore previously saved value. */ - VID_WR32 (info->chip.PVIDEO, 0xB00, info->colorkey); - /* NV_PVIDEO_STOP */ - VID_OR32 (info->chip.PVIDEO, 0x704, 0x11); - /* NV_PVIDEO_BUFFER */ - VID_AND32 (info->chip.PVIDEO, 0x700, ~0x11); - /* NV_PVIDEO_INTR_EN_BUFFER */ -// VID_AND32 (info->chip.PVIDEO, 0x140, ~0x11); - break; - case NV_ARCH_03: - case NV_ARCH_04: - /* NV_PVIDEO_KEY */ - VID_WR32 (info->chip.PVIDEO, 0x240, info->colorkey); - /* NV_PVIDEO_OVERLAY_VIDEO_OFF */ - VID_AND32 (info->chip.PVIDEO, 0x244, ~0x01); - /* NV_PVIDEO_INTR_EN_0_NOTIFY */ -// VID_AND32 (info->chip.PVIDEO, 0x140, ~0x01); - /* NV_PVIDEO_OE_STATE */ - VID_WR32 (info->chip.PVIDEO, 0x224, 0); - /* NV_PVIDEO_SU_STATE */ - VID_WR32 (info->chip.PVIDEO, 0x228, 0); - /* NV_PVIDEO_RM_STATE */ - VID_WR32 (info->chip.PVIDEO, 0x22C, 0); - break; - } -} - -/* Get pan offset of the physical screen. */ -static uint32_t rivatv_overlay_pan (struct rivatv_info *info){ - uint32_t pan; - info->chip.lock (&info->chip, 0); - VID_WR08 (info->chip.PCIO, 0x3D4, 0x0D); - pan = VID_RD08 (info->chip.PCIO, 0x3D5); - VID_WR08 (info->chip.PCIO, 0x3D4, 0x0C); - pan |= VID_RD08 (info->chip.PCIO, 0x3D5) << 8; - VID_WR08 (info->chip.PCIO, 0x3D4, 0x19); - pan |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0x1F) << 16; - VID_WR08 (info->chip.PCIO, 0x3D4, 0x2D); - pan |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0x60) << 16; - return pan << 2; -} - -/* Compute and set colorkey depending on the colour depth. */ -static void rivatv_overlay_colorkey (rivatv_info* info, unsigned int chromakey){ - uint32_t r, g, b, key = 0; - - r = (chromakey & 0x00FF0000) >> 16; - g = (chromakey & 0x0000FF00) >> 8; - b = chromakey & 0x000000FF; - switch (info->depth) { - case 15: - key = ((r >> 3) << 10) | ((g >> 3) << 5) | ((b >> 3)); -#ifndef WIN32 - key = key | 0x00008000; -#endif - break; - case 16: // XXX unchecked - key = ((r >> 3) << 11) | ((g >> 2) << 5) | ((b >> 3)); -#ifndef WIN32 - key = key | 0x00008000; -#endif - break; - case 24: // XXX unchecked, maybe swap order of masking - FIXME Can the card be in 24 bit mode anyway? - key = (chromakey & 0x00FFFFFF) | 0x00800000; - break; - case 32: - key = chromakey; -#ifndef WIN32 - key = key | 0x80000000; -#endif - break; - } - //printf("[nvidia_vid] depth=%d %08X \n", info->depth, chromakey); - switch (info->chip.arch) { - case NV_ARCH_10: - case NV_ARCH_20: - case NV_ARCH_30: - VID_WR32 (info->chip.PVIDEO, 0xB00, key); - break; - case NV_ARCH_03: - case NV_ARCH_04: - VID_WR32 (info->chip.PVIDEO, 0x240, key); - break; - } -} - -static void nv_getscreenproperties(struct rivatv_info *info){ - uint32_t bpp=0,x; - info->chip.lock(&info->chip, 0); - /*get screen depth*/ - VID_WR08(info->chip.PCIO, 0x03D4,0x28); - bpp = VID_RD08(info->chip.PCIO,0x03D5)&0x3; - if((bpp == 2) && (VID_RD32(info->chip.PVIDEO,0x600) & 0x00001000) == 0x0)info->depth=15; - else info->depth = 0x04 << bpp; - /*get screen width*/ - VID_WR08(info->chip.PCIO, 0x03D4, 0x1); - info->screen_x = (1 + VID_RD08(info->chip.PCIO, 0x3D5)) * 8; - /*get screen height*/ - /* get first 8 bits in VT_DISPLAY_END*/ - VID_WR08(info->chip.PCIO, 0x03D4, 0x12); - info->screen_y = VID_RD08(info->chip.PCIO,0x03D5); - VID_WR08(info->chip.PCIO,0x03D4,0x07); - /* get 9th bit in CRTC_OVERFLOW*/ - info->screen_y |= (VID_RD08(info->chip.PCIO,0x03D5) &0x02)<<7; - /* and the 10th in CRTC_OVERFLOW*/ - info->screen_y |=(VID_RD08(info->chip.PCIO,0x03D5) &0x40)<<3; - ++info->screen_y; - - /* NV_PCRTC_OFFSET */ - VID_WR08 (info->chip.PCIO, 0x3D4, 0x13); - x = VID_RD08 (info->chip.PCIO, 0x3D5); - /* NV_PCRTC_REPAINT0_OFFSET_10_8 */ - VID_WR08 (info->chip.PCIO, 0x3D4, 0x19); - x |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0xE0) << 3; - /* NV_PCRTC_EXTRA_OFFSET_11 */ - VID_WR08 (info->chip.PCIO, 0x3D4, 0x25); - x |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0x20) << 6; x <<= 3; - info->bps = x * bpp; -} - - - - -/* Start overlay video. */ -static void rivatv_overlay_start (struct rivatv_info *info,int bufno){ - uint32_t base, size, offset, xscale, yscale, pan; - uint32_t value; - int x=info->wx, y=info->wy; - int lwidth=info->d_width, lheight=info->d_height; - - size = info->buffer_size; - base = info->picture_offset; - offset = bufno*size; - /*update depth & dimensions here because it may change with vo vesa or vo fbdev*/ - nv_getscreenproperties(info); - - if(info->depth){ - /* get pan offset of the physical screen */ - pan = rivatv_overlay_pan (info); - /* adjust window position depending on the pan offset */ - if (info->bps != 0) - { - x = info->wx - (pan % info->bps) * 8 / info->depth; - y = info->wy - (pan / info->bps); - } - } else { - // we can't adjust the window position correctly in textmode - // setting y to 8 seems to work ok, though - if(info->chip.arch < NV_ARCH_10 && y < 8) y = 8; - } - - /* adjust negative output window variables */ - if (x < 0) { - lwidth = info->d_width + x; - offset += (-x * info->width / info->d_width) << 1; -// offset += (-window->x * port->vld_width / window->width) << 1; - x = 0; - } - if (y < 0) { - lheight = info->d_height + y; - offset += (-y * info->height / info->d_height * info->width) << 1; -// offset += (-window->y * port->vld_height / window->height * port->org_width) << 1; - y = 0; - } - - switch (info->chip.arch) { - case NV_ARCH_10: - case NV_ARCH_20: - case NV_ARCH_30: - - /* NV_PVIDEO_BASE */ - VID_WR32 (info->chip.PVIDEO, 0x900 + 0, base + offset); - //VID_WR32 (info->chip.PVIDEO, 0x900 + 4, base); - /* NV_PVIDEO_LIMIT */ - VID_WR32 (info->chip.PVIDEO, 0x908 + 0, base + offset + size - 1); - //VID_WR32 (info->chip.PVIDEO, 0x908 + 4, base + size - 1); - - /* extra code for NV20 && NV30 architectures */ - if (info->chip.arch == NV_ARCH_20 || info->chip.arch == NV_ARCH_30) { - VID_WR32 (info->chip.PVIDEO, 0x800 + 0, base + offset); - //VID_WR32 (info->chip.PVIDEO, 0x800 + 4, base); - VID_WR32 (info->chip.PVIDEO, 0x808 + 0, base + offset + size - 1); - //VID_WR32 (info->chip.PVIDEO, 0x808 + 4, base + size - 1); - } - - /* NV_PVIDEO_LUMINANCE */ - VID_WR32 (info->chip.PVIDEO, 0x910 + 0, eq.lum); - //VID_WR32 (info->chip.PVIDEO, 0x910 + 4, 0x00001000); - /* NV_PVIDEO_CHROMINANCE */ - VID_WR32 (info->chip.PVIDEO, 0x918 + 0, eq.chrom); - //VID_WR32 (info->chip.PVIDEO, 0x918 + 4, 0x00001000); - - /* NV_PVIDEO_OFFSET */ - VID_WR32 (info->chip.PVIDEO, 0x920 + 0, 0x0); - //VID_WR32 (info->chip.PVIDEO, 0x920 + 4, offset + pitch); - /* NV_PVIDEO_SIZE_IN */ - VID_WR32 (info->chip.PVIDEO, 0x928 + 0, ((info->height) << 16) | info->width); - //VID_WR32 (info->chip.PVIDEO, 0x928 + 4, ((port->org_height/2) << 16) | port->org_width); - /* NV_PVIDEO_POINT_IN */ - VID_WR32 (info->chip.PVIDEO, 0x930 + 0, 0x00000000); - //VID_WR32 (info->chip.PVIDEO, 0x930 + 4, 0x00000000); - /* NV_PVIDEO_DS_DX_RATIO */ - VID_WR32 (info->chip.PVIDEO, 0x938 + 0, (info->width << 20) / info->d_width); - //VID_WR32 (info->chip.PVIDEO, 0x938 + 4, (port->org_width << 20) / window->width); - /* NV_PVIDEO_DT_DY_RATIO */ - VID_WR32 (info->chip.PVIDEO, 0x940 + 0, ((info->height) << 20) / info->d_height); - //VID_WR32 (info->chip.PVIDEO, 0x940 + 4, ((port->org_height/2) << 20) / window->height); - - /* NV_PVIDEO_POINT_OUT */ - VID_WR32 (info->chip.PVIDEO, 0x948 + 0, ((y + 0) << 16) | x); - //VID_WR32 (info->chip.PVIDEO, 0x948 + 4, ((y + 0) << 16) | x); - /* NV_PVIDEO_SIZE_OUT */ - VID_WR32 (info->chip.PVIDEO, 0x950 + 0, (lheight << 16) | lwidth); - //VID_WR32 (info->chip.PVIDEO, 0x950 + 4, (height << 16) | width); - - /* NV_PVIDEO_FORMAT */ - value = info->pitch; - if(info->use_colorkey)value |= 1 << 20; - if(info->format == IMGFMT_YUY2)value |= 1 << 16; - VID_WR32 (info->chip.PVIDEO, 0x958 + 0, value); - //VID_WR32 (info->chip.PVIDEO, 0x958 + 4, (pitch << 1) | 0x00100000); - - /* NV_PVIDEO_INTR_EN_BUFFER */ -// VID_OR32 (info->chip.PVIDEO, 0x140, 0x01/*0x11*/); - /* NV_PVIDEO_STOP */ - VID_WR32 (info->chip.PVIDEO, 0x704,0x0); - /* NV_PVIDEO_BUFFER */ - VID_WR32 (info->chip.PVIDEO, 0x700, 0x01/*0x11*/); - break; - - case NV_ARCH_03: - case NV_ARCH_04: - - - /* NV_PVIDEO_OE_STATE */ - VID_WR32 (info->chip.PVIDEO, 0x224, 0); - /* NV_PVIDEO_SU_STATE */ - VID_WR32 (info->chip.PVIDEO, 0x228, 0); - /* NV_PVIDEO_RM_STATE */ - VID_WR32 (info->chip.PVIDEO, 0x22C, 0); - - /* NV_PVIDEO_BUFF0_START_ADDRESS */ - VID_WR32 (info->chip.PVIDEO, 0x20C + 0, base + offset + 0); - VID_WR32 (info->chip.PVIDEO, 0x20C + 4, base + offset + 0); - /* NV_PVIDEO_BUFF0_PITCH_LENGTH */ - VID_WR32 (info->chip.PVIDEO, 0x214 + 0, info->pitch); - VID_WR32 (info->chip.PVIDEO, 0x214 + 4, info->pitch); - - /* NV_PVIDEO_WINDOW_START */ - VID_WR32 (info->chip.PVIDEO, 0x230, (y << 16) | x); - /* NV_PVIDEO_WINDOW_SIZE */ - VID_WR32 (info->chip.PVIDEO, 0x234, (lheight << 16) | lwidth); - /* NV_PVIDEO_STEP_SIZE */ - yscale = ((info->height - 1) << 11) / (info->d_height - 1); - xscale = ((info->width - 1) << 11) / (info->d_width - 1); - VID_WR32 (info->chip.PVIDEO, 0x200, (yscale << 16) | xscale); - - /* NV_PVIDEO_RED_CSC_OFFSET */ - VID_WR32 (info->chip.PVIDEO, 0x280, eq.red_off); - /* NV_PVIDEO_GREEN_CSC_OFFSET */ - VID_WR32 (info->chip.PVIDEO, 0x284, eq.green_off); - /* NV_PVIDEO_BLUE_CSC_OFFSET */ - VID_WR32 (info->chip.PVIDEO, 0x288, eq.blue_off); - /* NV_PVIDEO_CSC_ADJUST */ - VID_WR32 (info->chip.PVIDEO, 0x28C, 0x00000); /* No colour correction! */ - - /* NV_PVIDEO_CONTROL_Y (BLUR_ON, LINE_HALF) */ - VID_WR32 (info->chip.PVIDEO, 0x204, 0x001); - /* NV_PVIDEO_CONTROL_X (WEIGHT_HEAVY, SHARPENING_ON, SMOOTHING_ON) */ - VID_WR32 (info->chip.PVIDEO, 0x208, 0x111); /*directx overlay 0x110 */ - - /* NV_PVIDEO_FIFO_BURST_LENGTH */ - VID_WR32 (info->chip.PVIDEO, 0x23C, 0x03); - /* NV_PVIDEO_FIFO_THRES_SIZE */ - VID_WR32 (info->chip.PVIDEO, 0x238, 0x38); /*windows uses 0x40*/ - - /* NV_PVIDEO_BUFF0_OFFSET */ - VID_WR32 (info->chip.PVIDEO, 0x21C + 0, 0); - VID_WR32 (info->chip.PVIDEO, 0x21C + 4, 0); - - /* NV_PVIDEO_INTR_EN_0_NOTIFY_ENABLED */ -// VID_OR32 (info->chip.PVIDEO, 0x140, 0x01); - - /* NV_PVIDEO_OVERLAY (KEY_ON, VIDEO_ON, FORMAT_CCIR) */ - value = 0x1; /*video on*/ - if(info->format==IMGFMT_YUY2)value |= 0x100; - if(info->use_colorkey)value |=0x10; - VID_WR32 (info->chip.PVIDEO, 0x244, value); - - /* NV_PVIDEO_SU_STATE */ - VID_XOR32 (info->chip.PVIDEO, 0x228, 1 << 16); - break; - } - /*set colorkey*/ - rivatv_overlay_colorkey(info,info->vidixcolorkey); - -} - - - - - - - -static rivatv_info* info; - - - - -int vixInit(void){ - int mtrr; - info = calloc(1,sizeof(rivatv_info)); - info->control_base = map_phys_mem(pci_info.base0, 0x00C00000 + 0x00008000); - info->chip.arch = nvidia_card_ids[find_chip(pci_info.device)].arch; - printf("[nvidia_vid] arch %x register base %p\n",info->chip.arch,info->control_base); - info->chip.PFIFO = (uint32_t *) (info->control_base + 0x00002000); - info->chip.FIFO = (uint32_t *) (info->control_base + 0x00800000); - info->chip.PMC = (uint32_t *) (info->control_base + 0x00000000); - info->chip.PFB = (uint32_t *) (info->control_base + 0x00100000); - info->chip.PME = (uint32_t *) (info->control_base + 0x00000000); - info->chip.PCIO = (uint8_t *) (info->control_base + 0x00601000); - info->chip.PVIO = (uint8_t *) (info->control_base + 0x000C0000); - info->chip.PGRAPH = (uint32_t *) (info->control_base + 0x00400000); - /* setup chip specific functions */ - switch (info->chip.arch) { - case NV_ARCH_03: - info->chip.lock = rivatv_lock_nv03; - info->chip.fbsize = rivatv_fbsize_nv03 (&info->chip); - info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00680000); - break; - case NV_ARCH_04: - info->chip.lock = rivatv_lock_nv04; - info->chip.fbsize = rivatv_fbsize_nv04 (&info->chip); - info->chip.PRAMIN = (uint32_t *) (info->control_base + 0x00700000); - info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00680000); - break; - case NV_ARCH_10: - case NV_ARCH_20: - case NV_ARCH_30: - info->chip.lock = rivatv_lock_nv04; - info->chip.fbsize = rivatv_fbsize_nv10 (&info->chip); - info->chip.PRAMIN = (uint32_t *) (info->control_base + 0x00700000); - info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00008000); - break; - } - switch (info->chip.arch) { - case NV_ARCH_03: - { - /* This maps framebuffer @6MB, thus 2MB are left for video. */ - info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize); - /* This may trash your screen for resolutions greater than 1024x768, sorry. */ - info->picture_offset = 1024*768* 4 * ((info->chip.fbsize > 4194304)?2:1); - info->picture_base = info->video_base + info->picture_offset; - info->chip.PRAMIN = (uint32_t *) (info->video_base + 0x00C00000); - break; - } - case NV_ARCH_04: - case NV_ARCH_10: - case NV_ARCH_20: - case NV_ARCH_30: - { - info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize); - info->picture_offset = info->chip.fbsize - NV04_BES_SIZE; - if(info->chip.fbsize > 16*1024*1024) - info->picture_offset -= NV04_BES_SIZE; -// info->picture_base = (unsigned long)map_phys_mem(pci_info.base1+info->picture_offset,NV04_BES_SIZE); - info->picture_base = info->video_base + info->picture_offset; - break; - } - } - - printf("[nvidia_vid] detected memory size %u MB\n",(uint32_t)(info->chip.fbsize /1024/1024)); - - if ((mtrr = mtrr_set_type(pci_info.base1, info->chip.fbsize, MTRR_TYPE_WRCOMB))!= 0) - printf("[nvidia_vid] unable to setup MTRR: %s\n", strerror(mtrr)); - else - printf("[nvidia_vid] MTRR set up\n"); - - nv_getscreenproperties(info); - if(!info->depth)printf("[nvidia_vid] text mode: %ux%u\n",info->screen_x,info->screen_y); - else printf("[nvidia_vid] video mode: %ux%u@%u\n",info->screen_x,info->screen_y, info->depth); - - - rivatv_enable_PMEDIA(info); - info->cur_frame = 0; - info->use_colorkey = 0; - - eq.lum = 0x00001000; - eq.chrom = 0x00001000; - memset(&eq.vals, 0, sizeof(vidix_video_eq_t)); - eq.vals.cap = VEQ_CAP_BRIGHTNESS; - if (info->chip.arch > NV_ARCH_04) - eq.vals.cap |= VEQ_CAP_CONTRAST | VEQ_CAP_SATURATION | VEQ_CAP_HUE; - eq.red_off = 0x69; - eq.green_off = 0x3e; - eq.blue_off = 0x89; - return 0; -} - -void vixDestroy(void){ - unmap_phys_mem(info->control_base ,0x00C00000 + 0x00008000); - unmap_phys_mem(info->video_base, info->chip.fbsize); - free(info); -} - -int vixGetCapability(vidix_capability_t *to){ - memcpy(to, &nvidia_cap, sizeof(vidix_capability_t)); - return 0; -} - -inline static int is_supported_fourcc(uint32_t fourcc) -{ - if (fourcc == IMGFMT_UYVY || fourcc == IMGFMT_YUY2) - return 1; - else - return 0; -} - -int vixQueryFourcc(vidix_fourcc_t *to){ - if(is_supported_fourcc(to->fourcc)){ - to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | - VID_DEPTH_4BPP | VID_DEPTH_8BPP | - VID_DEPTH_12BPP| VID_DEPTH_15BPP| - VID_DEPTH_16BPP| VID_DEPTH_24BPP| - VID_DEPTH_32BPP; - to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; - return 0; - } - else to->depth = to->flags = 0; - return ENOSYS; -} - -int vixConfigPlayback(vidix_playback_t *vinfo){ - uint32_t i; - printf("called %s\n", __FUNCTION__); - if (! is_supported_fourcc(vinfo->fourcc)) - return ENOSYS; - - info->width = vinfo->src.w; - info->height = vinfo->src.h; - - info->d_width = vinfo->dest.w; - info->d_height = vinfo->dest.h; - info->wx = vinfo->dest.x; - info->wy = vinfo->dest.y; - info->format = vinfo->fourcc; - - printf("[nvidia_vid] setting up a %dx%d-%dx%d video window (src %dx%d), format 0x%X\n", - info->d_width, info->d_height, info->wx, info->wy, info->width, info->height, vinfo->fourcc); - - - vinfo->dga_addr=info->picture_base; - - switch (vinfo->fourcc) - { - case IMGFMT_YUY2: - case IMGFMT_UYVY: - - vinfo->dest.pitch.y = 64; - vinfo->dest.pitch.u = 0; - vinfo->dest.pitch.v = 0; - - vinfo->offset.y = 0; - vinfo->offset.v = 0; - vinfo->offset.u = 0; - info->pitch = ((info->width << 1) + (vinfo->dest.pitch.y-1)) & ~(vinfo->dest.pitch.y-1); - vinfo->frame_size = info->pitch * info->height; - break; - } - info->buffer_size = vinfo->frame_size; - info->num_frames = vinfo->num_frames= (info->chip.fbsize - info->picture_offset)/vinfo->frame_size; - if(vinfo->num_frames > MAX_FRAMES)vinfo->num_frames = MAX_FRAMES; -// vinfo->num_frames = 1; -// printf("[nvidia_vid] Number of frames %i\n",vinfo->num_frames); - for(i=0;i <vinfo->num_frames;i++)vinfo->offsets[i] = vinfo->frame_size*i; - return 0; -} - -int vixPlaybackOn(void){ - rivatv_overlay_start(info,info->cur_frame); - return 0; -} - -int vixPlaybackOff(void){ - rivatv_overlay_stop(info); - return 0; -} - -int vixSetGrKeys( const vidix_grkey_t * grkey){ - if (grkey->ckey.op == CKEY_FALSE) - { - info->use_colorkey = 0; - printf("[nvidia_vid] colorkeying disabled\n"); - } - else { - info->use_colorkey = 1; - info->vidixcolorkey = ((grkey->ckey.red<<16)|(grkey->ckey.green<<8)|grkey->ckey.blue); - printf("[nvidia_vid] set colorkey 0x%x\n",info->vidixcolorkey); - } - if(info->d_width && info->d_height)rivatv_overlay_start(info,0); - return 0; -} - -int vixPlaybackFrameSelect(unsigned int frame){ -// printf("selecting buffer %d\n", frame); - rivatv_overlay_start(info, frame); - if (info->num_frames >= 1) - info->cur_frame = frame/*(frame+1)%info->num_frames*/; - return 0; -} - -int vixPlaybackSetEq(const vidix_video_eq_t *eq_parm) { - double angle; - int16_t chrom_cos, chrom_sin; - if (eq_parm->cap & VEQ_CAP_BRIGHTNESS) - eq.vals.brightness = eq_parm->brightness; - if (eq_parm->cap & VEQ_CAP_CONTRAST) - eq.vals.contrast = eq_parm->contrast; - if (eq_parm->cap & VEQ_CAP_SATURATION) - eq.vals.saturation = eq_parm->saturation; - if (eq_parm->cap & VEQ_CAP_HUE) - eq.vals.hue = eq_parm->hue; - eq.lum = (((eq.vals.brightness * 512 + 500) / 1000) << 16) | - ((((eq.vals.contrast + 1000) * 8191 + 1000) / 2000) & 0xffff); - angle = (double)eq.vals.hue / 1000.0 * 3.1415927; - chrom_cos = ((eq.vals.saturation + 1000) * 8191 * cos(angle) + 1000) / 2000; - chrom_sin = ((eq.vals.saturation + 1000) * 8191 * sin(angle) + 1000) / 2000; - eq.chrom = chrom_sin << 16 | chrom_cos; - eq.red_off = 0x69 - eq.vals.brightness * 62 / 1000; - eq.green_off = 0x3e + eq.vals.brightness * 62 / 1000; - eq.blue_off = 0x89 - eq.vals.brightness * 62 / 1000; - return 0; -} - -int vixPlaybackGetEq(vidix_video_eq_t *eq_parm) { - memcpy(eq_parm, &eq.vals, sizeof(vidix_video_eq_t)); - return 0; -} -
--- a/vidix/drivers/pm3_regs.h Sat Mar 31 23:48:48 2007 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1113 +0,0 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/glint/pm3_regs.h,v 1.9 2001/11/20 00:09:15 alanh Exp $ */ - -/* - * glint register file - * - * Copyright by Sven Luther - * Authors: Sven Luther, <luther@dpt-info.u-strasbg.fr> - * Thomas Witzel, <twitzel@nmr.mgh.harvard.edu> - * - * this work is sponsored by Appian Graphics. - * - */ - -#ifndef _PM3_REG_H_ -#define _PM3_REG_H_ - -/********************************************** -* GLINT Permedia3 Control Status registers * -***********************************************/ -/* Control Status Registers */ -#define PM3ResetStatus 0x0000 -#define PM3IntEnable 0x0008 -#define PM3IntFlags 0x0010 -#define PM3InFIFOSpace 0x0018 -#define PM3OutFIFOWords 0x0020 -#define PM3DMAAddress 0x0028 -#define PM3DMACount 0x0030 -#define PM3ErrorFlags 0x0038 -#define PM3VClkCtl 0x0040 -#define PM3TestRegister 0x0048 -#define PM3Aperture0 0x0050 -#define PM3Aperture1 0x0058 -#define PM3DMAControl 0x0060 -#define PM3FIFODis 0x0068 -#define PM3ChipConfig 0x0070 -#define PM3AGPControl 0x0078 - -#define PM3GPOutDMAAddress 0x0080 -#define PM3PCIFeedbackCount 0x0088 -#define PM3PCIAbortStatus 0x0090 -#define PM3PCIAbortAddress 0x0098 - -#define PM3PCIPLLStatus 0x00f0 - -#define PM3HostTextureAddress 0x0100 -#define PM3TextureDownloadControl 0x0108 -#define PM3TextureOperation 0x0110 -#define PM3LogicalTexturePage 0x0118 -#define PM3TexDMAAddress 0x0120 -#define PM3TexFIFOSpace 0x0128 - -/********************************************** -* GLINT Permedia3 Region 0 Bypass Controls * -***********************************************/ -#define PM3ByAperture1Mode 0x0300 - #define PM3ByApertureMode_BYTESWAP_ABCD (0<<0) - #define PM3ByApertureMode_BYTESWAP_BADC (1<<0) - #define PM3ByApertureMode_BYTESWAP_CDAB (2<<0) - #define PM3ByApertureMode_BYTESWAP_DCBA (3<<0) - #define PM3ByApertureMode_PATCH_DISABLE (0<<2) - #define PM3ByApertureMode_PATCH_ENABLE (1<<2) - #define PM3ByApertureMode_FORMAT_RAW (0<<3) - #define PM3ByApertureMode_FORMAT_YUYV (1<<3) - #define PM3ByApertureMode_FORMAT_UYVY (2<<3) - #define PM3ByApertureMode_PIXELSIZE_8BIT (0<<5) - #define PM3ByApertureMode_PIXELSIZE_16BIT (1<<5) - #define PM3ByApertureMode_PIXELSIZE_32BIT (2<<5) - #define PM3ByApertureMode_EFFECTIVE_STRIDE_1024 (0<<7) - #define PM3ByApertureMode_EFFECTIVE_STRIDE_2048 (1<<7) - #define PM3ByApertureMode_EFFECTIVE_STRIDE_4096 (2<<7) - #define PM3ByApertureMode_EFFECTIVE_STRIDE_8192 (3<<7) - #define PM3ByApertureMode_PATCH_OFFSET_X(off) (((off)&7f)<<9) - #define PM3ByApertureMode_PATCH_OFFSET_Y(off) (((off)&7f)<<16) - #define PM3ByApertureMode_FRAMEBUFFER (0<<21) - #define PM3ByApertureMode_LOCALBUFFER (1<<21) - #define PM3ByApertureMode_DOUBLE_WRITE_OFF (0<<22) - #define PM3ByApertureMode_DOUBLE_WRITE_1MB (1<<22) - #define PM3ByApertureMode_DOUBLE_WRITE_2MB (2<<22) - #define PM3ByApertureMode_DOUBLE_WRITE_4MB (3<<22) - #define PM3ByApertureMode_DOUBLE_WRITE_8MB (4<<22) - #define PM3ByApertureMode_DOUBLE_WRITE_16MB (5<<22) - #define PM3ByApertureMode_DOUBLE_WRITE_32MB (6<<22) - -#define PM3ByAperture2Mode 0x0328 - -/********************************************** -* GLINT Permedia3 Memory Control (0x1000) * -***********************************************/ -#define PM3MemCounter 0x1000 -#define PM3MemBypassWriteMask 0x1008 -#define PM3MemScratch 0x1010 -#define PM3LocalMemCaps 0x1018 - #define PM3LocalMemCaps_NoWriteMask (1<<28) -#define PM3LocalMemTimings 0x1020 -#define PM3LocalMemControl 0x1028 -#define PM3LocalMemRefresh 0x1030 -#define PM3LocalMemPowerDown 0x1038 -#define PM3RemoteMemControl 0x1100 - -/********************************************** -* GLINT Permedia3 Video Control (0x3000) * -***********************************************/ - -#define PM3ScreenBase 0x3000 -#define PM3ScreenStride 0x3008 -#define PM3HTotal 0x3010 -#define PM3HgEnd 0x3018 -#define PM3HbEnd 0x3020 -#define PM3HsStart 0x3028 -#define PM3HsEnd 0x3030 -#define PM3VTotal 0x3038 -#define PM3VbEnd 0x3040 -#define PM3VsStart 0x3048 -#define PM3VsEnd 0x3050 -#define PM3VideoControl 0x3058 - #define PM3VideoControl_DISABLE (0<<0) - #define PM3VideoControl_ENABLE (1<<0) - #define PM3VideoControl_BLANK_ACTIVE_HIGH (0<<1) - #define PM3VideoControl_BLANK_ACTIVE_LOW (1<<1) - #define PM3VideoControl_LINE_DOUBLE_OFF (0<<2) - #define PM3VideoControl_LINE_DOUBLE_ON (1<<2) - #define PM3VideoControl_HSYNC_FORCE_HIGH (0<<3) - #define PM3VideoControl_HSYNC_ACTIVE_HIGH (1<<3) - #define PM3VideoControl_HSYNC_FORCE_LOW (2<<3) - #define PM3VideoControl_HSYNC_ACTIVE_LOW (3<<3) - #define PM3VideoControl_VSYNC_FORCE_HIGH (0<<5) - #define PM3VideoControl_VSYNC_ACTIVE_HIGH (1<<5) - #define PM3VideoControl_VSYNC_FORCE_LOW (2<<5) - #define PM3VideoControl_VSYNC_ACTIVE_LOW (3<<5) - #define PM3VideoControl_BYTE_DOUBLE_OFF (0<<7) - #define PM3VideoControl_BYTE_DOUBLE_ON (1<<7) - #define PM3VideoControl_BUFFER_SWAP_SYNCON_FRAMEBLANK (0<<9) - #define PM3VideoControl_BUFFER_SWAP_FREE_RUNNING (1<<9) - #define PM3VideoControl_BUFFER_SWAP_LIMITETO_FRAMERATE (2<<9) - #define PM3VideoControl_STEREO_DISABLE (0<<11) - #define PM3VideoControl_STEREO_ENABLE (1<<11) - #define PM3VideoControl_RIGHT_EYE_ACTIVE_HIGH (0<<12) - #define PM3VideoControl_RIGHT_EYE_ACTIVE_LOW (1<<12) - #define PM3VideoControl_VIDEO_EXT_LOW (0<<14) - #define PM3VideoControl_VIDEO_EXT_HIGH (1<<14) - #define PM3VideoControl_SYNC_MODE_INDEPENDENT (0<<16) - #define PM3VideoControl_SYNC_MODE_SYNCTO_VSA (1<<16) - #define PM3VideoControl_SYNC_MODE_SYNCTO_VSB (2<<16) - #define PM3VideoControl_PATCH_DISABLE (0<<18) - #define PM3VideoControl_PATCH_ENABLE (1<<18) - #define PM3VideoControl_PIXELSIZE_8BIT (0<<19) - #define PM3VideoControl_PIXELSIZE_16BIT (1<<19) - #define PM3VideoControl_PIXELSIZE_32BIT (2<<19) - #define PM3VideoControl_DISPLAY_DISABLE (0<<21) - #define PM3VideoControl_DISPLAY_ENABLE (1<<21) - #define PM3VideoControl_PATCH_OFFSET_X(off) (((off)&0x3f)<<22) - #define PM3VideoControl_PATCH_OFFSET_Y(off) (((off)&0x3f)<<28) -#define PM3InterruptLine 0x3060 -#define PM3DisplayData 0x3068 -#define PM3VerticalLineCount 0x3070 -#define PM3FifoControl 0x3078 -#define PM3ScreenBaseRight 0x3080 -#define PM3MiscControl 0x3088 - -#define PM3VideoOverlayUpdate 0x3100 - #define PM3VideoOverlayUpdate_DISABLE (0<<0) - #define PM3VideoOverlayUpdate_ENABLE (1<<0) -#define PM3VideoOverlayMode 0x3108 - #define PM3VideoOverlayMode_DISABLE (0<<0) - #define PM3VideoOverlayMode_ENABLE (1<<0) - #define PM3VideoOverlayMode_BUFFERSYNC_MANUAL (0<<1) - #define PM3VideoOverlayMode_BUFFERSYNC_VIDEOSTREAMA (1<<1) - #define PM3VideoOverlayMode_BUFFERSYNC_VIDEOSTREAMB (2<<1) - #define PM3VideoOverlayMode_FIELDPOLARITY_NORMAL (0<<4) - #define PM3VideoOverlayMode_FIELDPOLARITY_INVERT (1<<4) - #define PM3VideoOverlayMode_PIXELSIZE_8BIT (0<<5) - #define PM3VideoOverlayMode_PIXELSIZE_16BIT (1<<5) - #define PM3VideoOverlayMode_PIXELSIZE_32BIT (2<<5) - #define PM3VideoOverlayMode_COLORFORMAT_RGB8888 ((0<<7)|(1<<12)|(2<<5)) - #define PM3VideoOverlayMode_COLORFORMAT_RGB4444 ((1<<7)|(1<<12)|(1<<5)) - #define PM3VideoOverlayMode_COLORFORMAT_RGB5551 ((2<<7)|(1<<12)|(1<<5)) - #define PM3VideoOverlayMode_COLORFORMAT_RGB565 ((3<<7)|(1<<12)|(1<<5)) - #define PM3VideoOverlayMode_COLORFORMAT_RGB332 ((4<<7)|(1<<12)|(0<<5)) - #define PM3VideoOverlayMode_COLORFORMAT_BGR8888 ((0<<7)|(2<<5)) - #define PM3VideoOverlayMode_COLORFORMAT_BGR4444 ((1<<7)|(1<<5)) - #define PM3VideoOverlayMode_COLORFORMAT_BGR5551 ((2<<7)|(1<<5)) - #define PM3VideoOverlayMode_COLORFORMAT_BGR565 ((3<<7)|(1<<5)) - #define PM3VideoOverlayMode_COLORFORMAT_BGR332 ((4<<7)|(0<<5)) - #define PM3VideoOverlayMode_COLORFORMAT_CI8 ((5<<7)|(1<<12)|(0<<5)) - #define PM3VideoOverlayMode_COLORFORMAT_VUY444 ((2<<10)|(1<<12)|(2<<5)) - #define PM3VideoOverlayMode_COLORFORMAT_YUV444 ((2<<10)|(2<<5)) - #define PM3VideoOverlayMode_COLORFORMAT_VUY422 ((1<<10)|(1<<12)|(1<<5)) - #define PM3VideoOverlayMode_COLORFORMAT_YUV422 ((1<<10)|(1<<5)) - #define PM3VideoOverlayMode_COLORORDER_BGR (0<<12) - #define PM3VideoOverlayMode_COLORORDER_RGB (1<<12) - #define PM3VideoOverlayMode_LINEARCOLOREXT_OFF (0<<13) - #define PM3VideoOverlayMode_LINEARCOLOREXT_ON (1<<13) - #define PM3VideoOverlayMode_FILTER_MASK (3<<14) - #define PM3VideoOverlayMode_FILTER_OFF (0<<14) - #define PM3VideoOverlayMode_FILTER_FULL (1<<14) - #define PM3VideoOverlayMode_FILTER_PARTIAL (2<<14) - #define PM3VideoOverlayMode_DEINTERLACE_OFF (0<<16) - #define PM3VideoOverlayMode_DEINTERLACE_BOB (1<<16) - #define PM3VideoOverlayMode_PATCHMODE_OFF (0<<18) - #define PM3VideoOverlayMode_PATCHMODE_ON (1<<18) - #define PM3VideoOverlayMode_FLIP_VIDEO (0<<20) - #define PM3VideoOverlayMode_FLIP_VIDEOSTREAMA (1<<20) - #define PM3VideoOverlayMode_FLIP_VIDEOSTREAMB (2<<20) - #define PM3VideoOverlayMode_MIRROR_MASK (3<<23) - #define PM3VideoOverlayMode_MIRRORX_OFF (0<<23) - #define PM3VideoOverlayMode_MIRRORX_ON (1<<23) - #define PM3VideoOverlayMode_MIRRORY_OFF (0<<24) - #define PM3VideoOverlayMode_MIRRORY_ON (1<<24) -#define PM3VideoOverlayFifoControl 0x3110 -#define PM3VideoOverlayIndex 0x3118 -#define PM3VideoOverlayBase 0x3120 -#define PM3VideoOverlayBase0 0x3120 -#define PM3VideoOverlayBase1 0x3128 -#define PM3VideoOverlayBase2 0x3130 -#define PM3VideoOverlayStride 0x3138 - #define PM3VideoOverlayStride_STRIDE(s) (((s)&0xfff)<<0) -#define PM3VideoOverlayWidth 0x3140 - #define PM3VideoOverlayWidth_WIDTH(w) (((w)&0xfff)<<0) -#define PM3VideoOverlayHeight 0x3148 - #define PM3VideoOverlayHeight_HEIGHT(h) (((h)&0xfff)<<0) -#define PM3VideoOverlayOrigin 0x3150 - #define PM3VideoOverlayOrigin_XORIGIN(x) (((x)&0xfff)<<0) - #define PM3VideoOverlayOrigin_YORIGIN(y) (((y)&0xfff)<<16) -#define PM3VideoOverlayShrinkXDelta 0x3158 - #define PM3VideoOverlayShrinkXDelta_NONE (1<<16) - #define PM3VideoOverlayShrinkXDelta_DELTA(s,d) \ - ((((s)<<16)/(d))&0x0ffffff0) -#define PM3VideoOverlayZoomXDelta 0x3160 - #define PM3VideoOverlayZoomXDelta_NONE (1<<16) - #define PM3VideoOverlayZoomXDelta_DELTA(s,d) \ - ((((s)<<16)/(d))&0x0001fff0) -#define PM3VideoOverlayYDelta 0x3168 - #define PM3VideoOverlayYDelta_NONE (1<<16) - #define PM3VideoOverlayYDelta_DELTA(s,d) \ - ((((s)<<16)/(d))&0x0ffffff0) -#define PM3VideoOverlayFieldOffset 0x3170 -#define PM3VideoOverlayStatus 0x3178 - -/********************************************** -* GLINT Permedia3 RAMDAC Registers (0x4000) * -***********************************************/ -/* Direct Registers */ -#define PM3RD_PaletteWriteAddress 0x4000 -#define PM3RD_PaletteData 0x4008 -#define PM3RD_PixelMask 0x4010 -#define PM3RD_PaletteReadAddress 0x4018 - -#define PM3RD_IndexLow 0x4020 -#define PM3RD_IndexHigh 0x4028 -#define PM3RD_IndexedData 0x4030 -#define PM3RD_IndexControl 0x4038 - #define PM3RD_IndexControl_AUTOINCREMENT_ENABLE (1<<0) - #define PM3RD_IndexControl_AUTOINCREMENT_DISABLE (0<<0) - -/* Indirect Registers */ -#define PM3RD_MiscControl 0x000 - #define PM3RD_MiscControl_HIGHCOLOR_RES_DISABLE (0<<0) - #define PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE (1<<0) - #define PM3RD_MiscControl_PIXELDOUBLE_DISABLE (0<<1) - #define PM3RD_MiscControl_PIXELDOUBLE_ENABLE (1<<1) - #define PM3RD_MiscControl_LASTREAD_ADDR_DISABLE (0<<2) - #define PM3RD_MiscControl_LASTREAD_ADDR_ENABLE (1<<2) - #define PM3RD_MiscControl_DIRECTCOLOR_DISABLE (0<<3) - #define PM3RD_MiscControl_DIRECTCOLOR_ENABLE (1<<3) - #define PM3RD_MiscControl_OVERLAY_DISABLE (0<<4) - #define PM3RD_MiscControl_OVERLAY_ENABLE (1<<4) - #define PM3RD_MiscControl_PIXELDOUBLE_BUFFER_DISABLE (0<<5) - #define PM3RD_MiscControl_PIXELDOUBLE_BUFFER_ENABLE (1<<5) - #define PM3RD_MiscControl_VSB_OUTPUT_DISABLE (0<<6) - #define PM3RD_MiscControl_VSB_OUTPUT_ENABLE (1<<6) - #define PM3RD_MiscControl_STEREODOUBLE_BUFFER_DISABLE (0<<7) - #define PM3RD_MiscControl_STEREODOUBLE_BUFFER_ENABLE (1<<7) -#define PM3RD_SyncControl 0x001 - #define PM3RD_SyncControl_HSYNC_ACTIVE_LOW (0<<0) - #define PM3RD_SyncControl_HSYNC_ACTIVE_HIGH (1<<0) - #define PM3RD_SyncControl_HSYNC_FORCE_ACTIVE (3<<0) - #define PM3RD_SyncControl_HSYNC_FORCE_INACTIVE (4<<0) - #define PM3RD_SyncControl_HSYNC_TRI_STATE (2<<0) - #define PM3RD_SyncControl_VSYNC_ACTIVE_LOW (0<<3) - #define PM3RD_SyncControl_VSYNC_ACTIVE_HIGH (1<<3) - #define PM3RD_SyncControl_VSYNC_TRI_STATE (2<<3) - #define PM3RD_SyncControl_VSYNC_FORCE_ACTIVE (3<<3) - #define PM3RD_SyncControl_VSYNC_FORCE_INACTIVE (4<<3) - #define PM3RD_SyncControl_HSYNC_OVERRIDE_SETBY_HSYNC (0<<6) - #define PM3RD_SyncControl_HSYNC_OVERRIDE_FORCE_HIGH (1<<6) - #define PM3RD_SyncControl_VSYNC_OVERRIDE_SETBY_VSYNC (0<<7) - #define PM3RD_SyncControl_VSYNC_OVERRIDE_FORCE_HIGH (1<<7) -#define PM3RD_DACControl 0x002 - #define PM3RD_DACControl_DAC_POWER_ON (0<<0) - #define PM3RD_DACControl_DAC_POWER_OFF (1<<0) - #define PM3RD_DACControl_SYNC_ON_GREEN_DISABLE (0<<3) - #define PM3RD_DACControl_SYNC_ON_GREEN_ENABLE (1<<3) - #define PM3RD_DACControl_BLANK_RED_DAC_DISABLE (0<<4) - #define PM3RD_DACControl_BLANK_RED_DAC_ENABLE (1<<4) - #define PM3RD_DACControl_BLANK_GREEN_DAC_DISABLE (0<<5) - #define PM3RD_DACControl_BLANK_GREEN_DAC_ENABLE (1<<5) - #define PM3RD_DACControl_BLANK_BLUE_DAC_DISABLE (0<<6) - #define PM3RD_DACControl_BLANK_BLUE_DAC_ENABLE (1<<6) - #define PM3RD_DACControl_BLANK_PEDESTAL_DISABLE (0<<7) - #define PM3RD_DACControl_BLANK_PEDESTAL_ENABLE (1<<7) -#define PM3RD_PixelSize 0x003 - #define PM3RD_PixelSize_24_BIT_PIXELS (4<<0) - #define PM3RD_PixelSize_32_BIT_PIXELS (2<<0) - #define PM3RD_PixelSize_16_BIT_PIXELS (1<<0) - #define PM3RD_PixelSize_8_BIT_PIXELS (0<<0) -#define PM3RD_ColorFormat 0x004 - #define PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE (1<<6) - #define PM3RD_ColorFormat_LINEAR_COLOR_EXT_DISABLE (0<<6) - #define PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW (1<<5) - #define PM3RD_ColorFormat_COLOR_ORDER_RED_LOW (0<<5) - #define PM3RD_ColorFormat_COLOR_FORMAT_MASK (0x1f<<0) - #define PM3RD_ColorFormat_8888_COLOR (0<<0) - #define PM3RD_ColorFormat_5551_FRONT_COLOR (1<<0) - #define PM3RD_ColorFormat_4444_COLOR (2<<0) - #define PM3RD_ColorFormat_332_FRONT_COLOR (5<<0) - #define PM3RD_ColorFormat_332_BACK_COLOR (6<<0) - #define PM3RD_ColorFormat_2321_FRONT_COLOR (9<<0) - #define PM3RD_ColorFormat_2321_BACK_COLOR (10<<0) - #define PM3RD_ColorFormat_232_FRONTOFF_COLOR (11<<0) - #define PM3RD_ColorFormat_232_BACKOFF_COLOR (12<<0) - #define PM3RD_ColorFormat_5551_BACK_COLOR (13<<0) - #define PM3RD_ColorFormat_CI8_COLOR (14<<0) - #define PM3RD_ColorFormat_565_FRONT_COLOR (16<<0) - #define PM3RD_ColorFormat_565_BACK_COLOR (17<<0) -#define PM3RD_CursorMode 0x005 - #define PM3RD_CursorMode_CURSOR_DISABLE (0<<0) - #define PM3RD_CursorMode_CURSOR_ENABLE (1<<0) - #define PM3RD_CursorMode_FORMAT_64x64_2BPE_P0123 (0<<2) - #define PM3RD_CursorMode_FORMAT_32x32_2BPE_P0 (1<<2) - #define PM3RD_CursorMode_FORMAT_32x32_2BPE_P1 (2<<2) - #define PM3RD_CursorMode_FORMAT_32x32_2BPE_P2 (3<<2) - #define PM3RD_CursorMode_FORMAT_32x32_2BPE_P3 (4<<2) - #define PM3RD_CursorMode_FORMAT_32x32_4BPE_P01 (5<<2) - #define PM3RD_CursorMode_FORMAT_32x32_4BPE_P23 (6<<2) - #define PM3RD_CursorMode_TYPE_MS (0<<4) - #define PM3RD_CursorMode_TYPE_X (1<<4) - #define PM3RD_CursorMode_REVERSE_PIXEL_ORDER_DISABLE (0<<6) - #define PM3RD_CursorMode_REVERSE_PIXEL_ORDER_ENABLE (1<<6) - #define PM3RD_CursorMode_REVERSE_PIXEL_ORDER_3_COLOR (2<<6) - #define PM3RD_CursorMode_REVERSE_PIXEL_ORDER_15_COLOR (3<<6) -#define PM3RD_CursorControl 0x006 - #define PM3RD_CursorControl_DOUBLE_X_DISABLED (0<<0) - #define PM3RD_CursorControl_DOUBLE_X_ENABLED (1<<0) - #define PM3RD_CursorControl_DOUBLE_Y_DISABLED (0<<1) - #define PM3RD_CursorControl_DOUBLE_Y_ENABLED (1<<1) - #define PM3RD_CursorControl_READBACK_POS_DISABLED (0<<2) - #define PM3RD_CursorControl_READBACK_POS_ENABLED (1<<2) - -#define PM3RD_CursorXLow 0x007 -#define PM3RD_CursorXHigh 0x008 -#define PM3RD_CursorYLow 0x009 -#define PM3RD_CursorYHigh 0x00a -#define PM3RD_CursorHotSpotX 0x00b -#define PM3RD_CursorHotSpotY 0x00c -#define PM3RD_OverlayKey 0x00d -#define PM3RD_Pan 0x00e - #define PM3RD_Pan_DISABLE (0<<0) - #define PM3RD_Pan_ENABLE (1<<0) - #define PM3RD_Pan_GATE_DISABLE (0<<1) - #define PM3RD_Pan_GATE_ENABLE (1<<1) -#define PM3RD_Sense 0x00f - -#define PM3RD_CheckControl 0x018 - #define PM3RD_CheckControl_PIXEL_DISABLED (0<<0) - #define PM3RD_CheckControl_PIXEL_ENABLED (1<<0) - #define PM3RD_CheckControl_LUT_DISABLED (0<<1) - #define PM3RD_CheckControl_LUT_ENABLED (1<<1) -#define PM3RD_CheckPixelRed 0x019 -#define PM3RD_CheckPixelGreen 0x01a -#define PM3RD_CheckPixelBlue 0x01b -#define PM3RD_CheckLUTRed 0x01c -#define PM3RD_CheckLUTGreen 0x01d -#define PM3RD_CheckLUTBlue 0x01e -#define PM3RD_Scratch 0x01f - -#define PM3RD_VideoOverlayControl 0x020 - #define PM3RD_VideoOverlayControl_DISABLE (0<<0) - #define PM3RD_VideoOverlayControl_ENABLE (1<<0) - #define PM3RD_VideoOverlayControl_MODE_MASK (3<<1) - #define PM3RD_VideoOverlayControl_MODE_MAINKEY (0<<1) - #define PM3RD_VideoOverlayControl_MODE_OVERLAYKEY (1<<1) - #define PM3RD_VideoOverlayControl_MODE_ALWAYS (2<<1) - #define PM3RD_VideoOverlayControl_MODE_BLEND (3<<1) - #define PM3RD_VideoOverlayControl_DIRECTCOLOR_DISABLED (0<<3) - #define PM3RD_VideoOverlayControl_DIRECTCOLOR_ENABLED (1<<3) - #define PM3RD_VideoOverlayControl_BLENDSRC_MAIN (0<<4) - #define PM3RD_VideoOverlayControl_BLENDSRC_REGISTER (1<<4) - #define PM3RD_VideoOverlayControl_KEY_COLOR (0<<5) - #define PM3RD_VideoOverlayControl_KEY_ALPHA (1<<5) -#define PM3RD_VideoOverlayXStartLow 0x021 -#define PM3RD_VideoOverlayXStartHigh 0x022 -#define PM3RD_VideoOverlayYStartLow 0x023 -#define PM3RD_VideoOverlayYStartHigh 0x024 -#define PM3RD_VideoOverlayXEndLow 0x025 -#define PM3RD_VideoOverlayXEndHigh 0x026 -#define PM3RD_VideoOverlayYEndLow 0x027 -#define PM3RD_VideoOverlayYEndHigh 0x028 -#define PM3RD_VideoOverlayKeyR 0x029 -#define PM3RD_VideoOverlayKeyG 0x02a -#define PM3RD_VideoOverlayKeyB 0x02b -#define PM3RD_VideoOverlayBlend 0x02c - #define PM3RD_VideoOverlayBlend_FACTOR_0_PERCENT (0<<6) - #define PM3RD_VideoOverlayBlend_FACTOR_25_PERCENT (1<<6) - #define PM3RD_VideoOverlayBlend_FACTOR_75_PERCENT (2<<6) - #define PM3RD_VideoOverlayBlend_FACTOR_100_PERCENT (3<<6) - -#define PM3RD_DClkSetup1 0x1f0 -#define PM3RD_DClkSetup2 0x1f1 -#define PM3RD_KClkSetup1 0x1f2 -#define PM3RD_KClkSetup2 0x1f3 - -#define PM3RD_DClkControl 0x200 - #define PM3RD_DClkControl_SOURCE_PLL (0<<4) - #define PM3RD_DClkControl_SOURCE_VSA (1<<4) - #define PM3RD_DClkControl_SOURCE_VSB (2<<4) - #define PM3RD_DClkControl_SOURCE_EXT (3<<4) - #define PM3RD_DClkControl_STATE_RUN (2<<2) - #define PM3RD_DClkControl_STATE_HIGH (1<<2) - #define PM3RD_DClkControl_STATE_LOW (0<<2) - #define PM3RD_DClkControl_LOCKED (1<<1) - #define PM3RD_DClkControl_NOT_LOCKED (0<<1) - #define PM3RD_DClkControl_ENABLE (1<<0) - #define PM3RD_DClkControl_DISABLE (0<<0) -#define PM3RD_DClk0PreScale 0x201 -#define PM3RD_DClk0FeedbackScale 0x202 -#define PM3RD_DClk0PostScale 0x203 -#define PM3RD_DClk1PreScale 0x204 -#define PM3RD_DClk1FeedbackScale 0x205 -#define PM3RD_DClk1PostScale 0x206 -#define PM3RD_DClk2PreScale 0x207 -#define PM3RD_DClk2FeedbackScale 0x208 -#define PM3RD_DClk2PostScale 0x209 -#define PM3RD_DClk3PreScale 0x20a -#define PM3RD_DClk3FeedbackScale 0x20b -#define PM3RD_DClk3PostScale 0x20c -#define PM3RD_KClkControl 0x20d - #define PM3RD_KClkControl_DISABLE (0<<0) - #define PM3RD_KClkControl_ENABLE (1<<0) - #define PM3RD_KClkControl_NOT_LOCKED (0<<1) - #define PM3RD_KClkControl_LOCKED (1<<1) - #define PM3RD_KClkControl_STATE_LOW (0<<2) - #define PM3RD_KClkControl_STATE_HIGH (1<<2) - #define PM3RD_KClkControl_STATE_RUN (2<<2) - #define PM3RD_KClkControl_STATE_LOW_POWER (3<<2) - #define PM3RD_KClkControl_SOURCE_PCLK (0<<4) - #define PM3RD_KClkControl_SOURCE_HALF_PCLK (1<<4) - #define PM3RD_KClkControl_SOURCE_PLL (2<<4) -#define PM3RD_KClkPreScale 0x20e -#define PM3RD_KClkFeedbackScale 0x20f -#define PM3RD_KClkPostScale 0x210 -#define PM3RD_MClkControl 0x211 - #define PM3RD_MClkControl_DISABLE (0<<0) - #define PM3RD_MClkControl_ENABLE (1<<0) - #define PM3RD_MClkControl_NOT_LOCKED (0<<1) - #define PM3RD_MClkControl_LOCKED (1<<1) - #define PM3RD_MClkControl_STATE_LOW (0<<2) - #define PM3RD_MClkControl_STATE_HIGH (1<<2) - #define PM3RD_MClkControl_STATE_RUN (2<<2) - #define PM3RD_MClkControl_STATE_LOW_POWER (3<<2) - #define PM3RD_MClkControl_SOURCE_PCLK (0<<4) - #define PM3RD_MClkControl_SOURCE_HALF_PCLK (1<<4) - #define PM3RD_MClkControl_SOURCE_HALF_EXT (3<<4) - #define PM3RD_MClkControl_SOURCE_EXT (4<<4) - #define PM3RD_MClkControl_SOURCE_HALF_KCLK (5<<4) - #define PM3RD_MClkControl_SOURCE_KCLK (6<<4) -#define PM3RD_MClkPreScale 0x212 -#define PM3RD_MClkFeedbackScale 0x213 -#define PM3RD_MClkPostScale 0x214 -#define PM3RD_SClkControl 0x215 - #define PM3RD_SClkControl_DISABLE (0<<0) - #define PM3RD_SClkControl_ENABLE (1<<0) - #define PM3RD_SClkControl_NOT_LOCKED (0<<1) - #define PM3RD_SClkControl_LOCKED (1<<1) - #define PM3RD_SClkControl_STATE_LOW (0<<2) - #define PM3RD_SClkControl_STATE_HIGH (1<<2) - #define PM3RD_SClkControl_STATE_RUN (2<<2) - #define PM3RD_SClkControl_STATE_LOW_POWER (3<<2) - #define PM3RD_SClkControl_SOURCE_PCLK (0<<4) - #define PM3RD_SClkControl_SOURCE_HALF_PCLK (1<<4) - #define PM3RD_SClkControl_SOURCE_HALF_EXT (3<<4) - #define PM3RD_SClkControl_SOURCE_EXT (4<<4) - #define PM3RD_SClkControl_SOURCE_HALF_KCLK (5<<4) - #define PM3RD_SClkControl_SOURCE_KCLK (6<<4) -#define PM3RD_SClkPreScale 0x216 -#define PM3RD_SClkFeedbackScale 0x217 -#define PM3RD_SClkPostScale 0x218 - -#define PM3RD_CursorPalette(p) (0x303+(p)) -#define PM3RD_CursorPattern(p) (0x400+(p)) -/****************************************************** -* GLINT Permedia3 Video Streaming Registers (0x5000) * -*******************************************************/ - -#define PM3VSConfiguration 0x5800 - -/********************************************** -* GLINT Permedia3 Core Registers (0x8000+) * -***********************************************/ -#define PM3AALineWidth 0x94c0 -#define PM3AAPointsize 0x94a0 -#define PM3AlphaBlendAlphaMode 0xafa8 -#define PM3AlphaBlendAlphaModeAnd 0xad30 -#define PM3AlphaBlendAlphaModeOr 0xad38 -#define PM3AlphaBlendColorMode 0xafa0 -#define PM3AlphaBlendColorModeAnd 0xacb0 -#define PM3AlphaBlendColorModeOr 0xacb8 -#define PM3AlphaDestColor 0xaf88 -#define PM3AlphaSourceColor 0xaf80 -#define PM3AlphaTestMode 0x8800 -#define PM3AlphaTestModeAnd 0xabf0 -#define PM3AlphaTestModeOr 0xabf8 -#define PM3AntialiasMode 0x8808 -#define PM3AntialiasModeAnd 0xac00 -#define PM3AntialiasModeOr 0xac08 -/* ... */ -#define PM3BackgroundColor 0xb0c8 -/* ... */ -#define PM3ColorDDAMode 0x87e0 -#define PM3ColorDDAModeAnd 0xabe0 -#define PM3ColorDDAModeOr 0xabe8 -#define PM3CommandInterrupt 0xa990 -#define PM3ConstantColorDDA 0xafb0 - #define PM3ConstantColorDDA_R(r) ((r)&0xff) - #define PM3ConstantColorDDA_G(g) (((g)&0xff)<<8) - #define PM3ConstantColorDDA_B(b) (((b)&0xff)<<16) - #define PM3ConstantColorDDA_A(a) (((a)&0xff)<<24) -#define PM3ContextData 0x8dd0 -#define PM3ContextDump 0x8dc0 -#define PM3ContextRestore 0x8dc8 -#define PM3Continue 0x8058 -#define PM3ContinueNewDom 0x8048 -#define PM3ContinueNewLine 0x8040 -#define PM3ContinueNewSub 0x8050 -#define PM3Count 0x8030 -/* ... */ -#define PM3DeltaControl 0x9350 -#define PM3DeltaControlAnd 0xab20 -#define PM3DeltaControlOr 0xab28 -#define PM3DeltaMode 0x9300 -#define PM3DeltaModeAnd 0xaad0 -#define PM3DeltaModeOr 0xaad8 -/* ... */ -#define PM3DitherMode 0x8818 -#define PM3DitherModeAnd 0xacd0 -#define PM3DitherModeOr 0xacd8 -/* ... */ -#define PM3dXDom 0x8008 -#define PM3dXSub 0x8018 -#define PM3dY 0x8028 -/* ... */ -#define PM3FBBlockColor 0x8ac8 -#define PM3FBBlockColor0 0xb060 -#define PM3FBBlockColor1 0xb068 -#define PM3FBBlockColor2 0xb070 -#define PM3FBBlockColor3 0xb078 -#define PM3FBBlockColorBack 0xb0a0 -#define PM3FBBlockColorBack0 0xb080 -#define PM3FBBlockColorBack1 0xb088 -#define PM3FBBlockColorBack2 0xb090 -#define PM3FBBlockColorBack3 0xb098 -#define PM3FBColor 0x8a98 -#define PM3FBDestReadBufferAddr0 0xae80 -#define PM3FBDestReadBufferAddr1 0xae88 -#define PM3FBDestReadBufferAddr2 0xae90 -#define PM3FBDestReadBufferAddr3 0xae98 -#define PM3FBDestReadBufferOffset0 0xaea0 -#define PM3FBDestReadBufferOffset1 0xaea8 -#define PM3FBDestReadBufferOffset2 0xaeb0 -#define PM3FBDestReadBufferOffset3 0xaeb8 - #define PM3FBDestReadBufferOffset_XOffset(x) ((x)&0xffff) - #define PM3FBDestReadBufferOffset_YOffset(y) (((y)&0xffff)<<16) -#define PM3FBDestReadBufferWidth0 0xaec0 -#define PM3FBDestReadBufferWidth1 0xaec8 -#define PM3FBDestReadBufferWidth2 0xaed0 -#define PM3FBDestReadBufferWidth3 0xaed8 - #define PM3FBDestReadBufferWidth_Width(w) ((w)&0x0fff) - -#define PM3FBDestReadEnables 0xaee8 -#define PM3FBDestReadEnablesAnd 0xad20 -#define PM3FBDestReadEnablesOr 0xad28 - #define PM3FBDestReadEnables_E(e) ((e)&0xff) - #define PM3FBDestReadEnables_E0 1<<0 - #define PM3FBDestReadEnables_E1 1<<1 - #define PM3FBDestReadEnables_E2 1<<2 - #define PM3FBDestReadEnables_E3 1<<3 - #define PM3FBDestReadEnables_E4 1<<4 - #define PM3FBDestReadEnables_E5 1<<5 - #define PM3FBDestReadEnables_E6 1<<6 - #define PM3FBDestReadEnables_E7 1<<7 - #define PM3FBDestReadEnables_R(r) (((r)&0xff)<<8) - #define PM3FBDestReadEnables_R0 1<<8 - #define PM3FBDestReadEnables_R1 1<<9 - #define PM3FBDestReadEnables_R2 1<<10 - #define PM3FBDestReadEnables_R3 1<<11 - #define PM3FBDestReadEnables_R4 1<<12 - #define PM3FBDestReadEnables_R5 1<<13 - #define PM3FBDestReadEnables_R6 1<<14 - #define PM3FBDestReadEnables_R7 1<<15 - #define PM3FBDestReadEnables_ReferenceAlpha(a) (((a)&0xff)<<24) - -#define PM3FBDestReadMode 0xaee0 -#define PM3FBDestReadModeAnd 0xac90 -#define PM3FBDestReadModeOr 0xac98 - #define PM3FBDestReadMode_ReadDisable 0<<0 - #define PM3FBDestReadMode_ReadEnable 1<<0 - #define PM3FBDestReadMode_StripePitch(sp) (((sp)&0x7)<<2) - #define PM3FBDestReadMode_StripeHeight(sh) (((sh)&0x7)<<7) - #define PM3FBDestReadMode_Enable0 1<<8 - #define PM3FBDestReadMode_Enable1 1<<9 - #define PM3FBDestReadMode_Enable2 1<<10 - #define PM3FBDestReadMode_Enable3 1<<11 - #define PM3FBDestReadMode_Layout0(l) (((l)&0x3)<<12) - #define PM3FBDestReadMode_Layout1(l) (((l)&0x3)<<14) - #define PM3FBDestReadMode_Layout2(l) (((l)&0x3)<<16) - #define PM3FBDestReadMode_Layout3(l) (((l)&0x3)<<18) - #define PM3FBDestReadMode_Origin0 1<<20 - #define PM3FBDestReadMode_Origin1 1<<21 - #define PM3FBDestReadMode_Origin2 1<<22 - #define PM3FBDestReadMode_Origin3 1<<23 - #define PM3FBDestReadMode_Blocking 1<<24 - #define PM3FBDestReadMode_UseReadEnabled 1<<26 - #define PM3FBDestReadMode_AlphaFiltering 1<<27 - -#define PM3FBHardwareWriteMask 0x8ac0 -#define PM3FBSoftwareWriteMask 0x8820 -#define PM3FBData 0x8aa0 -#define PM3FBSourceData 0x8aa8 -#define PM3FBSourceReadBufferAddr 0xaf08 -#define PM3FBSourceReadBufferOffset 0xaf10 - #define PM3FBSourceReadBufferOffset_XOffset(x) ((x)&0xffff) - #define PM3FBSourceReadBufferOffset_YOffset(y) (((y)&0xffff)<<16) -#define PM3FBSourceReadBufferWidth 0xaf18 - #define PM3FBSourceReadBufferWidth_Width(w) ((w)&0x0fff) -#define PM3FBSourceReadMode 0xaf00 -#define PM3FBSourceReadModeAnd 0xaca0 -#define PM3FBSourceReadModeOr 0xaca8 - #define PM3FBSourceReadMode_ReadDisable (0<<0) - #define PM3FBSourceReadMode_ReadEnable (1<<0) - #define PM3FBSourceReadMode_StripePitch(sp) (((sp)&0x7)<<2) - #define PM3FBSourceReadMode_StripeHeight(sh) (((sh)&0x7)<<7) - #define PM3FBSourceReadMode_Layout(l) (((l)&0x3)<<8) - #define PM3FBSourceReadMode_Origin 1<<10 - #define PM3FBSourceReadMode_Blocking 1<<11 - #define PM3FBSourceReadMode_UserTexelCoord 1<<13 - #define PM3FBSourceReadMode_WrapXEnable 1<<14 - #define PM3FBSourceReadMode_WrapYEnable 1<<15 - #define PM3FBSourceReadMode_WrapX(w) (((w)&0xf)<<16) - #define PM3FBSourceReadMode_WrapY(w) (((w)&0xf)<<20) - #define PM3FBSourceReadMode_ExternalSourceData 1<<24 -#define PM3FBWriteBufferAddr0 0xb000 -#define PM3FBWriteBufferAddr1 0xb008 -#define PM3FBWriteBufferAddr2 0xb010 -#define PM3FBWriteBufferAddr3 0xb018 - -#define PM3FBWriteBufferOffset0 0xb020 -#define PM3FBWriteBufferOffset1 0xb028 -#define PM3FBWriteBufferOffset2 0xb030 -#define PM3FBWriteBufferOffset3 0xb038 - #define PM3FBWriteBufferOffset_XOffset(x) ((x)&0xffff) - #define PM3FBWriteBufferOffset_YOffset(y) (((y)&0xffff)<<16) - -#define PM3FBWriteBufferWidth0 0xb040 -#define PM3FBWriteBufferWidth1 0xb048 -#define PM3FBWriteBufferWidth2 0xb050 -#define PM3FBWriteBufferWidth3 0xb058 - #define PM3FBWriteBufferWidth_Width(w) ((w)&0x0fff) - -#define PM3FBWriteMode 0x8ab8 -#define PM3FBWriteModeAnd 0xacf0 -#define PM3FBWriteModeOr 0xacf8 - #define PM3FBWriteMode_WriteDisable 0<<0 - #define PM3FBWriteMode_WriteEnable 1<<0 - #define PM3FBWriteMode_Replicate 1<<4 - #define PM3FBWriteMode_OpaqueSpan 1<<5 - #define PM3FBWriteMode_StripePitch(p) (((p)&0x7)<<6) - #define PM3FBWriteMode_StripeHeight(h) (((h)&0x7)<<9) - #define PM3FBWriteMode_Enable0 1<<12 - #define PM3FBWriteMode_Enable1 1<<13 - #define PM3FBWriteMode_Enable2 1<<14 - #define PM3FBWriteMode_Enable3 1<<15 - #define PM3FBWriteMode_Layout0(l) (((l)&0x3)<<16) - #define PM3FBWriteMode_Layout1(l) (((l)&0x3)<<18) - #define PM3FBWriteMode_Layout2(l) (((l)&0x3)<<20) - #define PM3FBWriteMode_Layout3(l) (((l)&0x3)<<22) - #define PM3FBWriteMode_Origin0 1<<24 - #define PM3FBWriteMode_Origin1 1<<25 - #define PM3FBWriteMode_Origin2 1<<26 - #define PM3FBWriteMode_Origin3 1<<27 -#define PM3ForegroundColor 0xb0c0 -/* ... */ -#define PM3GIDMode 0xb538 -#define PM3GIDModeAnd 0xb5b0 -#define PM3GIDModeOr 0xb5b8 -/* ... */ -#define PM3LBDestReadBufferAddr 0xb510 -#define PM3LBDestReadBufferOffset 0xb518 -#define PM3LBDestReadEnables 0xb508 -#define PM3LBDestReadEnablesAnd 0xb590 -#define PM3LBDestReadEnablesOr 0xb598 -#define PM3LBDestReadMode 0xb500 -#define PM3LBDestReadModeAnd 0xb580 -#define PM3LBDestReadModeOr 0xb588 - #define PM3LBDestReadMode_Disable 0<<0 - #define PM3LBDestReadMode_Enable 1<<0 - #define PM3LBDestReadMode_StripePitch(p) (((p)&0x7)<<2) - #define PM3LBDestReadMode_StripeHeight(h) (((h)&0x7)<<5) - #define PM3LBDestReadMode_Layout 1<<8 - #define PM3LBDestReadMode_Origin 1<<9 - #define PM3LBDestReadMode_UserReadEnables 1<<10 - #define PM3LBDestReadMode_Packed16 1<<11 - #define PM3LBDestReadMode_Width(w) (((w)&0xfff)<<12) -#define PM3LBReadFormat 0x8888 - #define PM3LBReadFormat_DepthWidth(w) (((w)&0x3)<<0) - #define PM3LBReadFormat_StencilWidth(w) (((w)&0xf)<<2) - #define PM3LBReadFormat_StencilPosition(p) (((p)&0x1f)<<6) - #define PM3LBReadFormat_FCPWidth(w) (((w)&0xf)<<11) - #define PM3LBReadFormat_FCPPosition(p) (((p)&0x1f)<<15) - #define PM3LBReadFormat_GIDWidth(w) (((w)&0x7)<<20) - #define PM3LBReadFormat_GIDPosition(p) (((p)&0x1f)<<23) -#define PM3LBSourceReadBufferAddr 0xb528 -#define PM3LBSourceReadBufferOffset 0xb530 -#define PM3LBSourceReadMode 0xb520 -#define PM3LBSourceReadModeAnd 0xb5a0 -#define PM3LBSourceReadModeOr 0xb5a8 - #define PM3LBSourceReadMode_Enable 1<<0 - #define PM3LBSourceReadMode_StripePitch(p) (((p)&0x7)<<2) - #define PM3LBSourceReadMode_StripeHeight(h) (((h)&0x7)<<5) - #define PM3LBSourceReadMode_Layout 1<<8 - #define PM3LBSourceReadMode_Origin 1<<9 - #define PM3LBSourceReadMode_Packed16 1<<10 - #define PM3LBSourceReadMode_Width(w) (((w)&0xfff)<<11) -#define PM3LBStencil 0x88a8 -#define PM3LBWriteBufferAddr 0xb540 -#define PM3LBWriteBufferOffset 0xb548 -#define PM3LBWriteFormat 0x88c8 - #define PM3LBWriteFormat_DepthWidth(w) (((w)&0x3)<<0) - #define PM3LBWriteFormat_StencilWidth(w) (((w)&0xf)<<2) - #define PM3LBWriteFormat_StencilPosition(p) (((p)&0x1f)<<6) - #define PM3LBWriteFormat_GIDWidth(w) (((w)&0x7)<<20) - #define PM3LBWriteFormat_GIDPosition(p) (((p)&0x1f)<<23) -#define PM3LBWriteMode 0x88c0 -#define PM3LBWriteModeAnd 0xac80 -#define PM3LBWriteModeOr 0xac88 - #define PM3LBWriteMode_WriteDisable 0<<0 - #define PM3LBWriteMode_WriteEnable 1<<0 - #define PM3LBWriteMode_StripePitch(p) (((p)&0x7)<<3) - #define PM3LBWriteMode_StripeHeight(h) (((h)&0x7)<<6) - #define PM3LBWriteMode_Layout 1<<9 - #define PM3LBWriteMode_Origin 1<<10 - #define PM3LBWriteMode_Packed16 1<<11 - #define PM3LBWriteMode_Width(w) (((w)&0xfff)<<12) -/* ... */ -#define PM3LineStippleMode 0x81a8 -#define PM3LineStippleModeAnd 0xabc0 -#define PM3LineStippleModeOr 0xabc8 -#define PM3LoadLineStippleCounters 0x81b0 -/* ... */ -#define PM3LogicalOpMode 0x8828 -#define PM3LogicalOpModeAnd 0xace0 -#define PM3LogicalOpModeOr 0xace8 - #define PM3LogicalOpMode_Disable (0<<0) - #define PM3LogicalOpMode_Enable (1<<0) - #define PM3LogicalOpMode_LogicOp(op) (((op)&0xf)<<1) - #define PM3LogicalOpMode_UseConstantWriteData_Disable (0<<5) - #define PM3LogicalOpMode_UseConstantWriteData_Enable (1<<5) - #define PM3LogicalOpMode_Background_Disable (0<<6) - #define PM3LogicalOpMode_Background_Enable (1<<6) - #define PM3LogicalOpMode_Background_LogicOp(op) (((op)&0xf)<<7) - #define PM3LogicalOpMode_UseConstantSource_Disable (0<<11) - #define PM3LogicalOpMode_UseConstantSource_Enable (1<<11) - -/* ... */ -#define PM3LUT 0x8e80 -/* ... */ -#define PM3LUT 0x8e80 -#define PM3LUTAddress 0x84d0 -#define PM3LUTData 0x84c8 -#define PM3LUTIndex 0x84c0 -#define PM3LUTMode 0xb378 -#define PM3LUTModeAnd 0xad70 -#define PM3LUTModeOr 0xad78 -#define PM3LUTTransfer 0x84d8 -/* ... */ -#define PM3PixelSize 0x80c0 - #define PM3PixelSize_GLOBAL_32BIT (0<<0) - #define PM3PixelSize_GLOBAL_16BIT (1<<0) - #define PM3PixelSize_GLOBAL_8BIT (2<<0) - #define PM3PixelSize_RASTERIZER_32BIT (0<<2) - #define PM3PixelSize_RASTERIZER_16BIT (1<<2) - #define PM3PixelSize_RASTERIZER_8BIT (2<<2) - #define PM3PixelSize_SCISSOR_AND_STIPPLE_32BIT (0<<4) - #define PM3PixelSize_SCISSOR_AND_STIPPLE_16BIT (1<<4) - #define PM3PixelSize_SCISSOR_AND_STIPPLE_8BIT (2<<4) - #define PM3PixelSize_TEXTURE_32BIT (0<<6) - #define PM3PixelSize_TEXTURE_16BIT (1<<6) - #define PM3PixelSize_TEXTURE_8BIT (2<<6) - #define PM3PixelSize_LUT_32BIT (0<<8) - #define PM3PixelSize_LUT_16BIT (1<<8) - #define PM3PixelSize_LUT_8BIT (2<<8) - #define PM3PixelSize_FRAMEBUFFER_32BIT (0<<10) - #define PM3PixelSize_FRAMEBUFFER_16BIT (1<<10) - #define PM3PixelSize_FRAMEBUFFER_8BIT (2<<10) - #define PM3PixelSize_LOGICAL_OP_32BIT (0<<12) - #define PM3PixelSize_LOGICAL_OP_16BIT (1<<12) - #define PM3PixelSize_LOGICAL_OP_8BIT (2<<12) - #define PM3PixelSize_LOCALBUFFER_32BIT (0<<14) - #define PM3PixelSize_LOCALBUFFER_16BIT (1<<14) - #define PM3PixelSize_LOCALBUFFER_8BIT (2<<14) - #define PM3PixelSize_SETUP_32BIT (0<<16) - #define PM3PixelSize_SETUP_16BIT (1<<16) - #define PM3PixelSize_SETUP_8BIT (2<<16) - #define PM3PixelSize_GLOBAL (0<<31) - #define PM3PixelSize_INDIVIDUAL (1<<31) -/* ... */ -#define PM3Render 0x8038 - #define PM3Render_AreaStipple_Disable (0<<0) - #define PM3Render_AreaStipple_Enable (1<<0) - #define PM3Render_LineStipple_Disable (0<<1) - #define PM3Render_LineStipple_Enable (1<<1) - #define PM3Render_ResetLine_Disable (0<<2) - #define PM3Render_ResetLine_Enable (1<<2) - #define PM3Render_FastFill_Disable (0<<3) - #define PM3Render_FastFill_Enable (1<<3) - #define PM3Render_Primitive_Line (0<<6) - #define PM3Render_Primitive_Trapezoid (1<<6) - #define PM3Render_Primitive_Point (2<<6) - #define PM3Render_Antialias_Disable (0<<8) - #define PM3Render_Antialias_Enable (1<<8) - #define PM3Render_Antialias_SubPixelRes_4x4 (0<<9) - #define PM3Render_Antialias_SubPixelRes_8x8 (1<<9) - #define PM3Render_UsePointTable_Disable (0<<10) - #define PM3Render_UsePointTable_Enable (1<<10) - #define PM3Render_SyncOnbitMask_Disable (0<<11) - #define PM3Render_SyncOnBitMask_Enable (1<<11) - #define PM3Render_SyncOnHostData_Disable (0<<12) - #define PM3Render_SyncOnHostData_Enable (1<<12) - #define PM3Render_Texture_Disable (0<<13) - #define PM3Render_Texture_Enable (1<<13) - #define PM3Render_Fog_Disable (0<<14) - #define PM3Render_Fog_Enable (1<<14) - #define PM3Render_Coverage_Disable (0<<15) - #define PM3Render_Coverage_Enable (1<<15) - #define PM3Render_SubPixelCorrection_Disable (0<<16) - #define PM3Render_SubPixelCorrection_Enable (1<<16) - #define PM3Render_SpanOperation_Disable (0<<18) - #define PM3Render_SpanOperation_Enable (1<<18) - #define PM3Render_FBSourceRead_Disable (0<<27) - #define PM3Render_FBSourceRead_Enable (1<<27) -#define PM3RasterizerMode 0x80a0 -#define PM3RasterizerModeAnd 0xaba0 -#define PM3RasterizerModeOr 0xabb8 -#define PM3RectangleHeight 0x94e0 -#define PM3Render 0x8038 -#define PM3RepeatLine 0x9328 -#define PM3ResetPickResult 0x8c20 -#define PM3RLEMask 0x8c48 -#define PM3RouterMode 0x8840 -#define PM3RStart 0x8780 -#define PM3S1Start 0x8400 -#define PM3aveLineStippleCounters 0x81c0 -#define PM3ScissorMaxXY 0x8190 -#define PM3ScissorMinXY 0x8188 -#define PM3ScissorMode 0x8180 -#define PM3ScissorModeAnd 0xabb0 -#define PM3ScissorModeOr 0xabb8 -#define PM3ScreenSize 0x8198 -#define PM3Security 0x8908 -#define PM3SetLogicalTexturePage 0xb360 -#define PM3SizeOfFramebuffer 0xb0a8 -#define PM3SStart 0x8388 -#define PM3StartXDom 0x8000 -#define PM3StartXSub 0x8010 -#define PM3StartY 0x8020 -/* ... */ -#define PM3SpanColorMask 0x8168 -/* ... */ -#define PM3TextureApplicationMode 0x8680 -#define PM3TextureApplicationModeAnd 0xac50 -#define PM3TextureApplicationModeOr 0xac58 -#define PM3TextureBaseAddr 0x8500 -#define PM3TextureCacheControl 0x8490 -#define PM3TextureChromaLower0 0x84f0 -#define PM3TextureChromaLower1 0x8608 -#define PM3TextureChromaUpper0 0x84e8 -#define PM3TextureChromaUpper1 0x8600 -#define PM3TextureCompositeAlphaMode0 0xb310 -#define PM3TextureCompositeAlphaMode0And 0xb390 -#define PM3TextureCompositeAlphaMode0Or 0xb398 -#define PM3TextureCompositeAlphaMode1 0xb320 -#define PM3TextureCompositeAlphaMode1And 0xb3b0 -#define PM3TextureCompositeAlphaMode1Or 0xb3b8 -#define PM3TextureCompositeColorMode0 0xb308 -#define PM3TextureCompositeColorMode0And 0xb380 -#define PM3TextureCompositeColorMode0Or 0xb388 -#define PM3TextureCompositeColorMode1 0xb318 -#define PM3TextureCompositeColorMode1And 0xb3a0 -#define PM3TextureCompositeColorMode1Or 0xb3a8 -#define PM3TextureCompositeFactor0 0xb328 -#define PM3TextureCompositeFactor1 0xb330 -#define PM3TextureCompositeMode 0xb300 -#define PM3TextureCoordMode 0x8380 -#define PM3TextureCoordModeAnd 0xac20 -#define PM3TextureCoordModeOr 0xac28 -#define PM3TextureData 0x88e8 -/* -#define PM3TextureDownloadControl 0x0108 -*/ -#define PM3TextureDownloadOffset 0x88f0 -#define PM3TextureEnvColor 0x8688 -#define PM3TextureFilterMode 0x84e0 -#define PM3TextureFilterModeAnd 0xad50 -#define PM3TextureFilterModeOr 0xad58 -#define PM3TextureIndexMode0 0xb338 -#define PM3TextureIndexMode0And 0xb3c0 -#define PM3TextureIndexMode0Or 0xb3c8 -#define PM3TextureIndexMode1 0xb340 -#define PM3TextureIndexMode1And 0xb3d0 -#define PM3TextureIndexMode1Or 0xb3d8 -#define PM3TextureLODBiasS 0x8450 -#define PM3TextureLODBiasT 0x8458 -/* ... */ -#define PM3TextureMapSize 0xb428 -#define PM3TextureMapWidth0 0x8580 -#define PM3TextureMapWidth1 0x8588 - #define PM3TextureMapWidth_Width(w) ((w&0xfff)<<0) - #define PM3TextureMapWidth_BorderLayout (1<<12) - #define PM3TextureMapWidth_Layout_Linear (0<<13) - #define PM3TextureMapWidth_Layout_Patch64 (1<<13) - #define PM3TextureMapWidth_Layout_Patch32_2 (2<<13) - #define PM3TextureMapWidth_Layout_Patch2 (3<<13) - #define PM3TextureMapWidth_HostTexture (1<<15) -#define PM3TextureReadMode0 0xb400 -#define PM3TextureReadMode0And 0xac30 -#define PM3TextureReadMode0Or 0xac38 -#define PM3TextureReadMode1 0xb408 -#define PM3TextureReadMode1And 0xad40 -#define PM3TextureReadMode1Or 0xad48 -/* ... */ -#define PM3WaitForCompletion 0x80b8 -#define PM3Window 0x8980 - #define PM3Window_ForceLBUpdate 1<<3 - #define PM3Window_LBUpdateSource 1<<4 - #define PM3Window_FrameCount(c) (((c)&0xff)<<9) - #define PM3Window_StencilFCP 1<<17 - #define PM3Window_DepthFCP 1<<18 - #define PM3Window_OverrideWriteFiltering 1<<19 -#define PM3WindowAnd 0xab80 -#define PM3WindowOr 0xab88 -#define PM3WindowOrigin 0x81c8 -#define PM3XBias 0x9480 -#define PM3YBias 0x9488 -#define PM3YLimits 0x80a8 -#define PM3UVMode 0x8f00 -#define PM3ZFogBias 0x86b8 -#define PM3ZStart 0xadd8 -#define PM3ZStartL 0x89b8 -#define PM3ZStartU 0x89b0 - - -/********************************************** -* GLINT Permedia3 2D setup Unit * -***********************************************/ -#define PM3Config2D 0xb618 - #define PM3Config2D_OpaqueSpan 1<<0 - #define PM3Config2D_MultiRXBlit 1<<1 - #define PM3Config2D_UserScissorEnable 1<<2 - #define PM3Config2D_FBDestReadEnable 1<<3 - #define PM3Config2D_AlphaBlendEnable 1<<4 - #define PM3Config2D_DitherEnable 1<<5 - #define PM3Config2D_ForegroundROPEnable 1<<6 - #define PM3Config2D_ForegroundROP(rop) (((rop)&0xf)<<7) - #define PM3Config2D_BackgroundROPEnable 1<<11 - #define PM3Config2D_BackgroundROP(rop) (((rop)&0xf)<<12) - #define PM3Config2D_UseConstantSource 1<<16 - #define PM3Config2D_FBWriteEnable 1<<17 - #define PM3Config2D_Blocking 1<<18 - #define PM3Config2D_ExternalSourceData 1<<19 - #define PM3Config2D_LUTModeEnable 1<<20 -#define PM3DownloadGlyphwidth 0xb658 - #define PM3DownloadGlyphwidth_GlyphWidth(gw) ((gw)&0xffff) -#define PM3DownloadTarget 0xb650 - #define PM3DownloadTarget_TagName(tag) ((tag)&0x1fff) -#define PM3GlyphData 0xb660 -#define PM3GlyphPosition 0xb608 - #define PM3GlyphPosition_XOffset(x) ((x)&0xffff) - #define PM3GlyphPosition_YOffset(y) (((y)&0xffff)<<16) -#define PM3Packed4Pixels 0xb668 -#define PM3Packed8Pixels 0xb630 -#define PM3Packed16Pixels 0xb638 -#define PM3RectanglePosition 0xb600 - #define PM3RectanglePosition_XOffset(x) ((x)&0xffff) - #define PM3RectanglePosition_YOffset(y) (((y)&0xffff)<<16) -#define PM3Render2D 0xb640 - #define PM3Render2D_Width(w) ((w)&0x0fff) - #define PM3Render2D_Operation_Normal 0<<12 - #define PM3Render2D_Operation_SyncOnHostData 1<<12 - #define PM3Render2D_Operation_SyncOnBitMask 2<<12 - #define PM3Render2D_Operation_PatchOrderRendering 3<<12 - #define PM3Render2D_FBSourceReadEnable 1<<14 - #define PM3Render2D_SpanOperation 1<<15 - #define PM3Render2D_Height(h) (((h)&0x0fff)<<16) - #define PM3Render2D_XPositive 1<<28 - #define PM3Render2D_YPositive 1<<29 - #define PM3Render2D_AreaStippleEnable 1<<30 - #define PM3Render2D_TextureEnable 1<<31 -#define PM3Render2DGlyph 0xb648 - #define PM3Render2DGlyph_Width(w) ((w)&0x7f) - #define PM3Render2DGlyph_Height(h) (((h)&0x7f)<<7) - #define PM3Render2DGlyph_XOffset(x) (((x)&0x1ff)<<14) - #define PM3Render2DGlyph_YOffset(y) (((y)&0x1ff)<<23) -#define PM3RenderPatchOffset 0xb610 - #define PM3RenderPatchOffset_XOffset(x) ((x)&0xffff) - #define PM3RenderPatchOffset_YOffset(y) (((y)&0xffff)<<16) -#define PM3RLCount 0xb678 - #define PM3RLCount_Count(c) ((c)&0x0fff) -#define PM3RLData 0xb670 - -/********************************************** -* GLINT Permedia3 Alias Register * -***********************************************/ -#define PM3FillBackgroundColor 0x8330 -#define PM3FillConfig2D0 0x8338 -#define PM3FillConfig2D1 0x8360 - #define PM3FillConfig2D_OpaqueSpan 1<<0 - #define PM3FillConfig2D_MultiRXBlit 1<<1 - #define PM3FillConfig2D_UserScissorEnable 1<<2 - #define PM3FillConfig2D_FBDestReadEnable 1<<3 - #define PM3FillConfig2D_AlphaBlendEnable 1<<4 - #define PM3FillConfig2D_DitherEnable 1<<5 - #define PM3FillConfig2D_ForegroundROPEnable 1<<6 - #define PM3FillConfig2D_ForegroundROP(rop) (((rop)&0xf)<<7) - #define PM3FillConfig2D_BackgroundROPEnable 1<<11 - #define PM3FillConfig2D_BackgroundROP(rop) (((rop)&0xf)<<12) - #define PM3FillConfig2D_UseConstantSource 1<<16 - #define PM3FillConfig2D_FBWriteEnable 1<<17 - #define PM3FillConfig2D_Blocking 1<<18 - #define PM3FillConfig2D_ExternalSourceData 1<<19 - #define PM3FillConfig2D_LUTModeEnable 1<<20 -#define PM3FillFBDestReadBufferAddr 0x8310 -#define PM3FillFBSourceReadBufferAddr 0x8308 -#define PM3FillFBSourceReadBufferOffset 0x8340 - #define PM3FillFBSourceReadBufferOffset_XOffset(x) ((x)&0xffff) - #define PM3FillFBSourceReadBufferOffset_YOffset(y) (((y)&0xffff)<<16) -#define PM3FillFBWriteBufferAddr 0x8300 -#define PM3FillForegroundColor0 0x8328 -#define PM3FillForegroundColor1 0x8358 -#define PM3FillGlyphPosition 0x8368 - #define PM3FillGlyphPosition_XOffset(x) ((x)&0xffff) - #define PM3FillGlyphPosition_YOffset(y) (((y)&0xffff)<<16) -#define PM3FillRectanglePosition 0x8348 - #define PM3FillRectanglePosition_XOffset(x) ((x)&0xffff) - #define PM3FillRectanglePosition_YOffset(y) (((y)&0xffff)<<16) - -#if 1 - -/********************************************** -* GLINT Permedia3 Macros * -***********************************************/ - -extern void *pm3_reg_base; - -#define WRITE_REG(offset,val) \ - *(volatile unsigned long *)(((unsigned char *)(pm3_reg_base)) + (offset)) = (val) - -#define READ_REG(offset) \ - *(volatile unsigned long *)(((unsigned char *)(pm3_reg_base)) + (offset)) - -#define UPDATE_SET_REG(offset,val) \ - { \ - unsigned long temp; \ - temp = READ_REG(offset); \ - WRITE_REG(offset,temp|(val)); \ - } - -#define UPDATE_CLEAR_REG(offset,val) \ - { \ - unsigned long temp; \ - temp = READ_REG(offset); \ - WRITE_REG(offset,temp&(~(val))); \ - } - -#define RAMDAC_DELAY(x) do { \ - int delay = x; \ - unsigned char tmp; \ - while(delay--){tmp = READ_REG(PM3InFIFOSpace);}; \ -} while(0) - -#define SLOW_WRITE_REG(v,r) \ -do{ \ - RAMDAC_DELAY(5); \ - WRITE_REG(v,r); \ - RAMDAC_DELAY(5); \ -}while(0) - -#define RAMDAC_SET_INDEX(index) \ -{ \ - SLOW_WRITE_REG (PM3RD_IndexHigh,((index)>>8)&0xff); \ - SLOW_WRITE_REG (PM3RD_IndexLow,(index)&0xff); \ -} - -#define RAMDAC_SET_REG(index, data) \ -{ \ - RAMDAC_SET_INDEX(index); \ - SLOW_WRITE_REG(PM3RD_IndexedData, data); \ -} - -#define RAMDAC_GET_REG(index, temp) \ -{ \ - RAMDAC_SET_INDEX(index); \ - temp = READ_REG(PM3RD_IndexedData); \ -} -#endif -#endif /* _PM3_REG_H_ */
--- a/vidix/drivers/pm3_vid.c Sat Mar 31 23:48:48 2007 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,375 +0,0 @@ -/** - Driver for 3DLabs GLINT R3 and Permedia3 chips. - - Copyright (C) 2002 Måns Rullgård - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA -**/ - -#include <errno.h> -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include <inttypes.h> -#include <unistd.h> - -#include "../vidix.h" -#include "../fourcc.h" -#include "../../libdha/libdha.h" -#include "../../libdha/pci_ids.h" -#include "../../libdha/pci_names.h" -#include "../../config.h" - -#include "pm3_regs.h" - -#if 0 -#define TRACE_ENTER() fprintf(stderr, "%s: enter\n", __FUNCTION__) -#define TRACE_EXIT() fprintf(stderr, "%s: exit\n", __FUNCTION__) -#else -#define TRACE_ENTER() -#define TRACE_EXIT() -#endif - -pciinfo_t pci_info; - -void *pm3_reg_base; -void *pm3_mem; - -static vidix_capability_t pm3_cap = -{ - "3DLabs GLINT R3/Permedia3 driver", - "Måns Rullgård <mru@users.sf.net>", - TYPE_OUTPUT, - { 0, 0, 0, 0 }, - 2048, - 2048, - 4, - 4, - -1, - FLAG_UPSCALER|FLAG_DOWNSCALER, - VENDOR_3DLABS, - -1, - { 0, 0, 0, 0 } -}; - - -unsigned int vixGetVersion(void) -{ - return(VIDIX_VERSION); -} - -static unsigned short pm3_card_ids[] = -{ - DEVICE_3DLABS_GLINT_R3 -}; - -static int find_chip(unsigned chip_id) -{ - unsigned i; - for(i = 0;i < sizeof(pm3_card_ids)/sizeof(unsigned short);i++) - { - if(chip_id == pm3_card_ids[i]) return i; - } - return -1; -} - -int vixProbe(int verbose, int force) -{ - pciinfo_t lst[MAX_PCI_DEVICES]; - unsigned i,num_pci; - int err; - - err = pci_scan(lst,&num_pci); - if(err) - { - printf("[pm3] Error occurred during pci scan: %s\n",strerror(err)); - return err; - } - else - { - err = ENXIO; - for(i=0; i < num_pci; i++) - { - if(lst[i].vendor == VENDOR_3DLABS) - { - int idx; - const char *dname; - idx = find_chip(lst[i].device); - if(idx == -1) - continue; - dname = pci_device_name(VENDOR_3DLABS, lst[i].device); - dname = dname ? dname : "Unknown chip"; - printf("[pm3] Found chip: %s\n", dname); - if ((lst[i].command & PCI_COMMAND_IO) == 0) - { - printf("[pm3] Device is disabled, ignoring\n"); - continue; - } - pm3_cap.device_id = lst[i].device; - err = 0; - memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); - break; - } - } - } - if(err && verbose) printf("[pm3] Can't find chip\n"); - return err; -} - -#define PRINT_REG(reg) \ -{ \ - long _foo = READ_REG(reg); \ - printf("[pm3] " #reg " (%x) = %#lx (%li)\n", reg, _foo, _foo); \ -} - -int vixInit(void) -{ - pm3_reg_base = map_phys_mem(pci_info.base0, 0x20000); - pm3_mem = map_phys_mem(pci_info.base2, 0x2000000); - return 0; -} - -void vixDestroy(void) -{ - unmap_phys_mem(pm3_reg_base, 0x20000); - unmap_phys_mem(pm3_mem, 0x2000000); -} - -int vixGetCapability(vidix_capability_t *to) -{ - memcpy(to, &pm3_cap, sizeof(vidix_capability_t)); - return 0; -} - -static int is_supported_fourcc(uint32_t fourcc) -{ - switch(fourcc){ - case IMGFMT_YUY2: - case IMGFMT_UYVY: - return 1; - default: - return 0; - } -} - -int vixQueryFourcc(vidix_fourcc_t *to) -{ - if(is_supported_fourcc(to->fourcc)) - { - to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | - VID_DEPTH_4BPP | VID_DEPTH_8BPP | - VID_DEPTH_12BPP| VID_DEPTH_15BPP| - VID_DEPTH_16BPP| VID_DEPTH_24BPP| - VID_DEPTH_32BPP; - to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; - return 0; - } - else to->depth = to->flags = 0; - return ENOSYS; -} - -#define FORMAT_RGB8888 PM3VideoOverlayMode_COLORFORMAT_RGB8888 -#define FORMAT_RGB4444 PM3VideoOverlayMode_COLORFORMAT_RGB4444 -#define FORMAT_RGB5551 PM3VideoOverlayMode_COLORFORMAT_RGB5551 -#define FORMAT_RGB565 PM3VideoOverlayMode_COLORFORMAT_RGB565 -#define FORMAT_RGB332 PM3VideoOverlayMode_COLORFORMAT_RGB332 -#define FORMAT_BGR8888 PM3VideoOverlayMode_COLORFORMAT_BGR8888 -#define FORMAT_BGR4444 PM3VideoOverlayMode_COLORFORMAT_BGR4444 -#define FORMAT_BGR5551 PM3VideoOverlayMode_COLORFORMAT_BGR5551 -#define FORMAT_BGR565 PM3VideoOverlayMode_COLORFORMAT_BGR565 -#define FORMAT_BGR332 PM3VideoOverlayMode_COLORFORMAT_BGR332 -#define FORMAT_CI8 PM3VideoOverlayMode_COLORFORMAT_CI8 -#define FORMAT_VUY444 PM3VideoOverlayMode_COLORFORMAT_VUY444 -#define FORMAT_YUV444 PM3VideoOverlayMode_COLORFORMAT_YUV444 -#define FORMAT_VUY422 PM3VideoOverlayMode_COLORFORMAT_VUY422 -#define FORMAT_YUV422 PM3VideoOverlayMode_COLORFORMAT_YUV422 - -/* Notice, have to check that we don't overflow the deltas here ... */ -static void -compute_scale_factor( - short* src_w, short* dst_w, - unsigned int* shrink_delta, unsigned int* zoom_delta) -{ - /* NOTE: If we don't return reasonable values here then the video - * unit can potential shut off and won't display an image until re-enabled. - * Seems as though the zoom_delta is o.k, and I've not had the problem. - * The 'shrink_delta' is prone to this the most - FIXME ! */ - - if (*src_w >= *dst_w) { - *src_w &= ~0x3; - *dst_w &= ~0x3; - *shrink_delta = (((*src_w << 16) / *dst_w) + 0x0f) & 0x0ffffff0; - *zoom_delta = 1<<16; - if ( ((*shrink_delta * *dst_w) >> 16) & 0x03 ) - *shrink_delta += 0x10; - } else { - *src_w &= ~0x3; - *dst_w &= ~0x3; - *zoom_delta = (((*src_w << 16) / *dst_w) + 0x0f) & 0x0001fff0; - *shrink_delta = 1<<16; - if ( ((*zoom_delta * *dst_w) >> 16) & 0x03 ) - *zoom_delta += 0x10; - } -} - -static int frames[VID_PLAY_MAXFRAMES]; - -static long overlay_mode, overlay_control; - -int vixConfigPlayback(vidix_playback_t *info) -{ - int shrink, zoom; - short src_w, drw_w; - short src_h, drw_h; - long base0; - int pitch; - int format; - unsigned int i; - - TRACE_ENTER(); - - if(!is_supported_fourcc(info->fourcc)) - return -1; - - switch(info->fourcc){ - case IMGFMT_YUY2: - format = FORMAT_YUV422; - break; - case IMGFMT_UYVY: - format = FORMAT_VUY422; - break; - default: - return -1; - } - - src_w = info->src.w; - src_h = info->src.h; - - drw_w = info->dest.w; - drw_h = info->dest.h; - - pitch = src_w; - - /* Assume we have 16 MB to play with */ - info->num_frames = 0x1000000 / (pitch * src_h * 2); - if(info->num_frames > VID_PLAY_MAXFRAMES) - info->num_frames = VID_PLAY_MAXFRAMES; - - /* Start at 16 MB. Let's hope it's not in use. */ - base0 = 0x1000000; - info->dga_addr = pm3_mem + base0; - - info->dest.pitch.y = 2; - info->dest.pitch.u = 0; - info->dest.pitch.v = 0; - info->offset.y = 0; - info->offset.v = 0; - info->offset.u = 0; - info->frame_size = pitch * src_h * 2; - for(i = 0; i < info->num_frames; i++){ - info->offsets[i] = info->frame_size * i; - frames[i] = (base0 + info->offsets[i]) >> 1; - } - - compute_scale_factor(&src_w, &drw_w, &shrink, &zoom); - - WRITE_REG(PM3VideoOverlayBase0, base0 >> 1); - WRITE_REG(PM3VideoOverlayStride, PM3VideoOverlayStride_STRIDE(pitch)); - WRITE_REG(PM3VideoOverlayWidth, PM3VideoOverlayWidth_WIDTH(src_w)); - WRITE_REG(PM3VideoOverlayHeight, PM3VideoOverlayHeight_HEIGHT(src_h)); - WRITE_REG(PM3VideoOverlayOrigin, 0); - - /* Scale the source to the destinationsize */ - if (src_h == drw_h) { - WRITE_REG(PM3VideoOverlayYDelta, PM3VideoOverlayYDelta_NONE); - } else { - WRITE_REG(PM3VideoOverlayYDelta, - PM3VideoOverlayYDelta_DELTA(src_h, drw_h)); - } - if (src_w == drw_w) { - WRITE_REG(PM3VideoOverlayShrinkXDelta, 1<<16); - WRITE_REG(PM3VideoOverlayZoomXDelta, 1<<16); - } else { - WRITE_REG(PM3VideoOverlayShrinkXDelta, shrink); - WRITE_REG(PM3VideoOverlayZoomXDelta, zoom); - } - WRITE_REG(PM3VideoOverlayIndex, 0); - - /* Now set the ramdac video overlay region and mode */ - RAMDAC_SET_REG(PM3RD_VideoOverlayXStartLow, (info->dest.x & 0xff)); - RAMDAC_SET_REG(PM3RD_VideoOverlayXStartHigh, (info->dest.x & 0xf00)>>8); - RAMDAC_SET_REG(PM3RD_VideoOverlayXEndLow, (info->dest.x+drw_w) & 0xff); - RAMDAC_SET_REG(PM3RD_VideoOverlayXEndHigh, - ((info->dest.x+drw_w) & 0xf00)>>8); - RAMDAC_SET_REG(PM3RD_VideoOverlayYStartLow, (info->dest.y & 0xff)); - RAMDAC_SET_REG(PM3RD_VideoOverlayYStartHigh, (info->dest.y & 0xf00)>>8); - RAMDAC_SET_REG(PM3RD_VideoOverlayYEndLow, (info->dest.y+drw_h) & 0xff); - RAMDAC_SET_REG(PM3RD_VideoOverlayYEndHigh, - ((info->dest.y+drw_h) & 0xf00)>>8); - - RAMDAC_SET_REG(PM3RD_VideoOverlayKeyR, 0xff); - RAMDAC_SET_REG(PM3RD_VideoOverlayKeyG, 0x00); - RAMDAC_SET_REG(PM3RD_VideoOverlayKeyB, 0xff); - - overlay_mode = - 1 << 5 | - format | - PM3VideoOverlayMode_FILTER_FULL | - PM3VideoOverlayMode_BUFFERSYNC_MANUAL | - PM3VideoOverlayMode_FLIP_VIDEO; - - overlay_control = - PM3RD_VideoOverlayControl_KEY_COLOR | - PM3RD_VideoOverlayControl_MODE_MAINKEY | - PM3RD_VideoOverlayControl_DIRECTCOLOR_ENABLED; - - TRACE_EXIT(); - return 0; -} - -int vixPlaybackOn(void) -{ - TRACE_ENTER(); - - WRITE_REG(PM3VideoOverlayMode, - overlay_mode | PM3VideoOverlayMode_ENABLE); - RAMDAC_SET_REG(PM3RD_VideoOverlayControl, - overlay_control | PM3RD_VideoOverlayControl_ENABLE); - WRITE_REG(PM3VideoOverlayUpdate, - PM3VideoOverlayUpdate_ENABLE); - - TRACE_EXIT(); - return 0; -} - -int vixPlaybackOff(void) -{ - RAMDAC_SET_REG(PM3RD_VideoOverlayControl, - PM3RD_VideoOverlayControl_DISABLE); - WRITE_REG(PM3VideoOverlayMode, - PM3VideoOverlayMode_DISABLE); - - RAMDAC_SET_REG(PM3RD_VideoOverlayKeyR, 0x01); - RAMDAC_SET_REG(PM3RD_VideoOverlayKeyG, 0x01); - RAMDAC_SET_REG(PM3RD_VideoOverlayKeyB, 0xfe); - - return 0; -} - -int vixPlaybackFrameSelect(unsigned int frame) -{ - WRITE_REG(PM3VideoOverlayBase0, frames[frame]); - return 0; -}
--- a/vidix/drivers/radeon.h Sat Mar 31 23:48:48 2007 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,2156 +0,0 @@ -/* - * radeon.h - * This software has been released under the terms of the GNU Public - * license. See http://www.gnu.org/copyleft/gpl.html for details. - * - * This collection of definition was written by Nick Kurshev - * It's based on radeonfb, X11, GATOS sources - * and partly compatible with Rage128 set (in OV0, CAP0, CAP1 parts) -*/ - -#ifndef _RADEON_H -#define _RADEON_H - -#define RADEON_REGSIZE 0x4000 -#define MM_INDEX 0x0000 -/* MM_INDEX bit constants */ -# define MM_APER 0x80000000 -#define MM_DATA 0x0004 -#define BUS_CNTL 0x0030 -/* BUS_CNTL bit constants */ -# define BUS_DBL_RESYNC 0x00000001 -# define BUS_MSTR_RESET 0x00000002 -# define BUS_FLUSH_BUF 0x00000004 -# define BUS_STOP_REQ_DIS 0x00000008 -# define BUS_ROTATION_DIS 0x00000010 -# define BUS_MASTER_DIS 0x00000040 -# define BUS_ROM_WRT_EN 0x00000080 -# define BUS_DIS_ROM 0x00001000 -# define BUS_PCI_READ_RETRY_EN 0x00002000 -# define BUS_AGP_AD_STEPPING_EN 0x00004000 -# define BUS_PCI_WRT_RETRY_EN 0x00008000 -# define BUS_MSTR_RD_MULT 0x00100000 -# define BUS_MSTR_RD_LINE 0x00200000 -# define BUS_SUSPEND 0x00400000 -# define LAT_16X 0x00800000 -# define BUS_RD_DISCARD_EN 0x01000000 -# define BUS_RD_ABORT_EN 0x02000000 -# define BUS_MSTR_WS 0x04000000 -# define BUS_PARKING_DIS 0x08000000 -# define BUS_MSTR_DISCONNECT_EN 0x10000000 -# define BUS_WRT_BURST 0x20000000 -# define BUS_READ_BURST 0x40000000 -# define BUS_RDY_READ_DLY 0x80000000 -#define HI_STAT 0x004C -#define BUS_CNTL1 0x0034 -# define BUS_WAIT_ON_LOCK_EN (1 << 4) -#define I2C_CNTL_0 0x0090 -# define I2C_DONE (1<<0) -# define I2C_NACK (1<<1) -# define I2C_HALT (1<<2) -# define I2C_SOFT_RST (1<<5) -# define I2C_DRIVE_EN (1<<6) -# define I2C_DRIVE_SEL (1<<7) -# define I2C_START (1<<8) -# define I2C_STOP (1<<9) -# define I2C_RECEIVE (1<<10) -# define I2C_ABORT (1<<11) -# define I2C_GO (1<<12) -# define I2C_SEL (1<<16) -# define I2C_EN (1<<17) -#define I2C_CNTL_1 0x0094 -#define I2C_DATA 0x0098 -#define CONFIG_CNTL 0x00E0 -/* CONFIG_CNTL bit constants */ -# define CFG_VGA_RAM_EN 0x00000100 -#ifdef RAGE128 -#define GEN_RESET_CNTL 0x00f0 -# define SOFT_RESET_GUI 0x00000001 -# define SOFT_RESET_VCLK 0x00000100 -# define SOFT_RESET_PCLK 0x00000200 -# define SOFT_RESET_ECP 0x00000400 -# define SOFT_RESET_DISPENG_XCLK 0x00000800 -# define SOFT_RESET_MEMCTLR_XCLK 0x00001000 -#endif -#define CONFIG_MEMSIZE 0x00F8 -#define CONFIG_APER_0_BASE 0x0100 -#define CONFIG_APER_1_BASE 0x0104 -#define CONFIG_APER_SIZE 0x0108 -#define CONFIG_REG_1_BASE 0x010C -#define CONFIG_REG_APER_SIZE 0x0110 -#define PAD_AGPINPUT_DELAY 0x0164 -#define PAD_CTLR_STRENGTH 0x0168 -#define PAD_CTLR_UPDATE 0x016C -#define AGP_CNTL 0x0174 -# define AGP_APER_SIZE_256MB (0x00 << 0) -# define AGP_APER_SIZE_128MB (0x20 << 0) -# define AGP_APER_SIZE_64MB (0x30 << 0) -# define AGP_APER_SIZE_32MB (0x38 << 0) -# define AGP_APER_SIZE_16MB (0x3c << 0) -# define AGP_APER_SIZE_8MB (0x3e << 0) -# define AGP_APER_SIZE_4MB (0x3f << 0) -# define AGP_APER_SIZE_MASK (0x3f << 0) -#define AMCGPIO_A_REG 0x01a0 -#define AMCGPIO_EN_REG 0x01a8 -#define AMCGPIO_MASK 0x0194 -#define AMCGPIO_Y_REG 0x01a4 -/*#define BM_STATUS 0x0160*/ -#define MPP_TB_CONFIG 0x01c0 /* ? */ -#define MPP_GP_CONFIG 0x01c8 /* ? */ -#define VENDOR_ID 0x0F00 -#define DEVICE_ID 0x0F02 -#define COMMAND 0x0F04 -#define STATUS 0x0F06 -#define REVISION_ID 0x0F08 -#define REGPROG_INF 0x0F09 -#define SUB_CLASS 0x0F0A -#define CACHE_LINE 0x0F0C -#define LATENCY 0x0F0D -#define HEADER 0x0F0E -#define BIST 0x0F0F -#define REG_MEM_BASE 0x0F10 -#define REG_IO_BASE 0x0F14 -#define REG_REG_BASE 0x0F18 -#define ADAPTER_ID 0x0F2C -#define BIOS_ROM 0x0F30 -#define CAPABILITIES_PTR 0x0F34 -#define INTERRUPT_LINE 0x0F3C -#define INTERRUPT_PIN 0x0F3D -#define MIN_GRANT 0x0F3E -#define MAX_LATENCY 0x0F3F -#define ADAPTER_ID_W 0x0F4C -#define PMI_CAP_ID 0x0F50 -#define PMI_NXT_CAP_PTR 0x0F51 -#define PMI_PMC_REG 0x0F52 -#define PM_STATUS 0x0F54 -#define PMI_DATA 0x0F57 -#define AGP_CAP_ID 0x0F58 -#define AGP_STATUS 0x0F5C -# define AGP_1X_MODE 0x01 -# define AGP_2X_MODE 0x02 -# define AGP_4X_MODE 0x04 -# define AGP_MODE_MASK 0x07 -#define AGP_COMMAND 0x0F60 - -/* Video muxer unit */ -#define VIDEOMUX_CNTL 0x0190 -#define VIPPAD_MASK 0x0198 -#define VIPPAD1_A 0x01AC -#define VIPPAD1_EN 0x01B0 -#define VIPPAD1_Y 0x01B4 - -#define AIC_CTRL 0x01D0 -#define AIC_STAT 0x01D4 -#define AIC_PT_BASE 0x01D8 -#define AIC_LO_ADDR 0x01DC -#define AIC_HI_ADDR 0x01E0 -#define AIC_TLB_ADDR 0x01E4 -#define AIC_TLB_DATA 0x01E8 -#define DAC_CNTL 0x0058 -/* DAC_CNTL bit constants */ -# define DAC_8BIT_EN 0x00000100 -# define DAC_4BPP_PIX_ORDER 0x00000200 -# define DAC_CRC_EN 0x00080000 -# define DAC_MASK_ALL (0xff << 24) -# define DAC_VGA_ADR_EN (1 << 13) -# define DAC_RANGE_CNTL (3 << 0) -# define DAC_BLANKING (1 << 2) -#define DAC_CNTL2 0x007c -/* DAC_CNTL2 bit constants */ -# define DAC2_DAC_CLK_SEL (1 << 0) -# define DAC2_DAC2_CLK_SEL (1 << 1) -# define DAC2_PALETTE_ACC_CTL (1 << 5) -#define TV_DAC_CNTL 0x088c -/* TV_DAC_CNTL bit constants */ -# define TV_DAC_STD_MASK 0x0300 -# define TV_DAC_RDACPD (1 << 24) -# define TV_DAC_GDACPD (1 << 25) -# define TV_DAC_BDACPD (1 << 26) -#define CRTC_GEN_CNTL 0x0050 -/* CRTC_GEN_CNTL bit constants */ -# define CRTC_DBL_SCAN_EN 0x00000001 -# define CRTC_INTERLACE_EN (1 << 1) -# define CRTC_CSYNC_EN (1 << 4) -# define CRTC_CUR_EN 0x00010000 -# define CRTC_CUR_MODE_MASK (7 << 17) -# define CRTC_ICON_EN (1 << 20) -# define CRTC_EXT_DISP_EN (1 << 24) -# define CRTC_EN (1 << 25) -# define CRTC_DISP_REQ_EN_B (1 << 26) -#define CRTC2_GEN_CNTL 0x03f8 -/* CRTC2_GEN_CNTL bit constants */ -# define CRTC2_DBL_SCAN_EN (1 << 0) -# define CRTC2_INTERLACE_EN (1 << 1) -# define CRTC2_SYNC_TRISTAT (1 << 4) -# define CRTC2_HSYNC_TRISTAT (1 << 5) -# define CRTC2_VSYNC_TRISTAT (1 << 6) -# define CRTC2_CRT2_ON (1 << 7) -# define CRTC2_ICON_EN (1 << 15) -# define CRTC2_CUR_EN (1 << 16) -# define CRTC2_CUR_MODE_MASK (7 << 20) -# define CRTC2_DISP_DIS (1 << 23) -# define CRTC2_EN (1 << 25) -# define CRTC2_DISP_REQ_EN_B (1 << 26) -# define CRTC2_HSYNC_DIS (1 << 28) -# define CRTC2_VSYNC_DIS (1 << 29) -#define MEM_CNTL 0x0140 -/* MEM_CNTL bit constants */ -# define MEM_CTLR_STATUS_IDLE 0x00000000 -# define MEM_CTLR_STATUS_BUSY 0x00100000 -# define MEM_SEQNCR_STATUS_IDLE 0x00000000 -# define MEM_SEQNCR_STATUS_BUSY 0x00200000 -# define MEM_ARBITER_STATUS_IDLE 0x00000000 -# define MEM_ARBITER_STATUS_BUSY 0x00400000 -# define MEM_REQ_UNLOCK 0x00000000 -# define MEM_REQ_LOCK 0x00800000 -#define EXT_MEM_CNTL 0x0144 -#define MC_AGP_LOCATION 0x014C -#define MEM_IO_CNTL_A0 0x0178 -#define MEM_INIT_LATENCY_TIMER 0x0154 -#define MEM_SDRAM_MODE_REG 0x0158 -#define AGP_BASE 0x0170 -#ifdef RAGE128 -#define PCI_GART_PAGE 0x017c -#define PC_NGUI_MODE 0x0180 -#define PC_NGUI_CTLSTAT 0x0184 -# define PC_FLUSH_GUI (3 << 0) -# define PC_RI_GUI (1 << 2) -# define PC_FLUSH_ALL 0x00ff -# define PC_BUSY (1 << 31) -#define PC_MISC_CNTL 0x0188 -#else -#define MEM_IO_CNTL_A1 0x017C -#define MEM_IO_CNTL_B0 0x0180 -#define MEM_IO_CNTL_B1 0x0184 -#define MC_DEBUG 0x0188 -#endif -#define MC_STATUS 0x0150 -#define MEM_IO_OE_CNTL 0x018C -#define MC_FB_LOCATION 0x0148 -#define HOST_PATH_CNTL 0x0130 -#define MEM_VGA_WP_SEL 0x0038 -#define MEM_VGA_RP_SEL 0x003C -#define HDP_DEBUG 0x0138 -#define SW_SEMAPHORE 0x013C -#define SURFACE_CNTL 0x0B00 -/* SURFACE_CNTL bit constants */ -# define SURF_TRANSLATION_DIS (1 << 8) -# define NONSURF_AP0_SWP_16BPP (1 << 20) -# define NONSURF_AP0_SWP_32BPP (2 << 20) -#define SURFACE0_LOWER_BOUND 0x0B04 -#define SURFACE1_LOWER_BOUND 0x0B14 -#define SURFACE2_LOWER_BOUND 0x0B24 -#define SURFACE3_LOWER_BOUND 0x0B34 -#define SURFACE4_LOWER_BOUND 0x0B44 -#define SURFACE5_LOWER_BOUND 0x0B54 -#define SURFACE6_LOWER_BOUND 0x0B64 -#define SURFACE7_LOWER_BOUND 0x0B74 -#define SURFACE0_UPPER_BOUND 0x0B08 -#define SURFACE1_UPPER_BOUND 0x0B18 -#define SURFACE2_UPPER_BOUND 0x0B28 -#define SURFACE3_UPPER_BOUND 0x0B38 -#define SURFACE4_UPPER_BOUND 0x0B48 -#define SURFACE5_UPPER_BOUND 0x0B58 -#define SURFACE6_UPPER_BOUND 0x0B68 -#define SURFACE7_UPPER_BOUND 0x0B78 -#define SURFACE0_INFO 0x0B0C -#define SURFACE1_INFO 0x0B1C -#define SURFACE2_INFO 0x0B2C -#define SURFACE3_INFO 0x0B3C -#define SURFACE4_INFO 0x0B4C -#define SURFACE5_INFO 0x0B5C -#define SURFACE6_INFO 0x0B6C -#define SURFACE7_INFO 0x0B7C -#define SURFACE_ACCESS_FLAGS 0x0BF8 -#define SURFACE_ACCESS_CLR 0x0BFC -#define GEN_INT_CNTL 0x0040 -#define GEN_INT_STATUS 0x0044 -# define VSYNC_INT_AK (1 << 2) -# define VSYNC_INT (1 << 2) -#define CRTC_EXT_CNTL 0x0054 -/* CRTC_EXT_CNTL bit constants */ -# define CRTC_VGA_XOVERSCAN (1 << 0) -# define VGA_ATI_LINEAR 0x00000008 -# define VGA_128KAP_PAGING 0x00000010 -# define XCRT_CNT_EN (1 << 6) -# define CRTC_HSYNC_DIS (1 << 8) -# define CRTC_VSYNC_DIS (1 << 9) -# define CRTC_DISPLAY_DIS (1 << 10) -# define CRTC_SYNC_TRISTAT (1 << 11) -# define CRTC_CRT_ON (1 << 15) -#define CRTC_EXT_CNTL_DPMS_BYTE 0x0055 -# define CRTC_HSYNC_DIS_BYTE (1 << 0) -# define CRTC_VSYNC_DIS_BYTE (1 << 1) -# define CRTC_DISPLAY_DIS_BYTE (1 << 2) -#define RB3D_CNTL 0x1C3C -#define WAIT_UNTIL 0x1720 -#define ISYNC_CNTL 0x1724 -#define RBBM_GUICNTL 0x172C -#define RBBM_STATUS 0x0E40 -# define RBBM_FIFOCNT_MASK 0x007f -# define RBBM_ACTIVE (1 << 31) -#define RBBM_STATUS_alt_1 0x1740 -#define RBBM_CNTL 0x00EC -#define RBBM_CNTL_alt_1 0x0E44 -#define RBBM_SOFT_RESET 0x00F0 -/* RBBM_SOFT_RESET bit constants */ -# define SOFT_RESET_CP (1 << 0) -# define SOFT_RESET_HI (1 << 1) -# define SOFT_RESET_SE (1 << 2) -# define SOFT_RESET_RE (1 << 3) -# define SOFT_RESET_PP (1 << 4) -# define SOFT_RESET_E2 (1 << 5) -# define SOFT_RESET_RB (1 << 6) -# define SOFT_RESET_HDP (1 << 7) -#define RBBM_SOFT_RESET_alt_1 0x0E48 -#define NQWAIT_UNTIL 0x0E50 -#define RBBM_DEBUG 0x0E6C -#define RBBM_CMDFIFO_ADDR 0x0E70 -#define RBBM_CMDFIFO_DATAL 0x0E74 -#define RBBM_CMDFIFO_DATAH 0x0E78 -#define RBBM_CMDFIFO_STAT 0x0E7C -#define CRTC_STATUS 0x005C -/* CRTC_STATUS bit constants */ -# define CRTC_VBLANK 0x00000001 -# define CRTC_VBLANK_SAVE ( 1 << 1) -#define GPIO_VGA_DDC 0x0060 -#define GPIO_DVI_DDC 0x0064 -#define GPIO_MONID 0x0068 -#define PALETTE_INDEX 0x00B0 -#define PALETTE_DATA 0x00B4 -#define PALETTE_30_DATA 0x00B8 -#define CRTC_H_TOTAL_DISP 0x0200 -# define CRTC_H_TOTAL (0x03ff << 0) -# define CRTC_H_TOTAL_SHIFT 0 -# define CRTC_H_DISP (0x01ff << 16) -# define CRTC_H_DISP_SHIFT 16 -#define CRTC2_H_TOTAL_DISP 0x0300 -# define CRTC2_H_TOTAL (0x03ff << 0) -# define CRTC2_H_TOTAL_SHIFT 0 -# define CRTC2_H_DISP (0x01ff << 16) -# define CRTC2_H_DISP_SHIFT 16 -#define CRTC_H_SYNC_STRT_WID 0x0204 -# define CRTC_H_SYNC_STRT_PIX (0x07 << 0) -# define CRTC_H_SYNC_STRT_CHAR (0x3ff << 3) -# define CRTC_H_SYNC_STRT_CHAR_SHIFT 3 -# define CRTC_H_SYNC_WID (0x3f << 16) -# define CRTC_H_SYNC_WID_SHIFT 16 -# define CRTC_H_SYNC_POL (1 << 23) -#define CRTC2_H_SYNC_STRT_WID 0x0304 -# define CRTC2_H_SYNC_STRT_PIX (0x07 << 0) -# define CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3) -# define CRTC2_H_SYNC_STRT_CHAR_SHIFT 3 -# define CRTC2_H_SYNC_WID (0x3f << 16) -# define CRTC2_H_SYNC_WID_SHIFT 16 -# define CRTC2_H_SYNC_POL (1 << 23) -#define CRTC_V_TOTAL_DISP 0x0208 -# define CRTC_V_TOTAL (0x07ff << 0) -# define CRTC_V_TOTAL_SHIFT 0 -# define CRTC_V_DISP (0x07ff << 16) -# define CRTC_V_DISP_SHIFT 16 -#define CRTC2_V_TOTAL_DISP 0x0308 -# define CRTC2_V_TOTAL (0x07ff << 0) -# define CRTC2_V_TOTAL_SHIFT 0 -# define CRTC2_V_DISP (0x07ff << 16) -# define CRTC2_V_DISP_SHIFT 16 -#define CRTC_V_SYNC_STRT_WID 0x020C -# define CRTC_V_SYNC_STRT (0x7ff << 0) -# define CRTC_V_SYNC_STRT_SHIFT 0 -# define CRTC_V_SYNC_WID (0x1f << 16) -# define CRTC_V_SYNC_WID_SHIFT 16 -# define CRTC_V_SYNC_POL (1 << 23) -#define CRTC2_V_SYNC_STRT_WID 0x030C -# define CRTC2_V_SYNC_STRT (0x7ff << 0) -# define CRTC2_V_SYNC_STRT_SHIFT 0 -# define CRTC2_V_SYNC_WID (0x1f << 16) -# define CRTC2_V_SYNC_WID_SHIFT 16 -# define CRTC2_V_SYNC_POL (1 << 23) -#define CRTC_VLINE_CRNT_VLINE 0x0210 -# define CRTC_CRNT_VLINE_MASK (0x7ff << 16) -#define CRTC2_VLINE_CRNT_VLINE 0x0310 -#define CRTC_CRNT_FRAME 0x0214 -#define CRTC2_CRNT_FRAME 0x0314 -#define CRTC_GUI_TRIG_VLINE 0x0218 -#define CRTC2_GUI_TRIG_VLINE 0x0318 -#define CRTC_DEBUG 0x021C -#define CRTC2_DEBUG 0x031C -#define CRTC_OFFSET_RIGHT 0x0220 -#define CRTC_OFFSET 0x0224 -#define CRTC2_OFFSET 0x0324 -#define CRTC_OFFSET_CNTL 0x0228 -# define CRTC_TILE_EN (1 << 15) -#define CRTC2_OFFSET_CNTL 0x0328 -# define CRTC2_TILE_EN (1 << 15) -#define CRTC_PITCH 0x022C -#define CRTC2_PITCH 0x032C -#define TMDS_CRC 0x02a0 -#define OVR_CLR 0x0230 -#define OVR_WID_LEFT_RIGHT 0x0234 -#define OVR_WID_TOP_BOTTOM 0x0238 -#define DISPLAY_BASE_ADDR 0x023C -#define SNAPSHOT_VH_COUNTS 0x0240 -#define SNAPSHOT_F_COUNT 0x0244 -#define N_VIF_COUNT 0x0248 -#define SNAPSHOT_VIF_COUNT 0x024C -#define FP_CRTC_H_TOTAL_DISP 0x0250 -#define FP_CRTC2_H_TOTAL_DISP 0x0350 -#define FP_CRTC_V_TOTAL_DISP 0x0254 -#define FP_CRTC2_V_TOTAL_DISP 0x0354 -# define FP_CRTC_H_TOTAL_MASK 0x000003ff -# define FP_CRTC_H_DISP_MASK 0x01ff0000 -# define FP_CRTC_V_TOTAL_MASK 0x00000fff -# define FP_CRTC_V_DISP_MASK 0x0fff0000 -# define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 -# define FP_H_SYNC_WID_MASK 0x003f0000 -# define FP_V_SYNC_STRT_MASK 0x00000fff -# define FP_V_SYNC_WID_MASK 0x001f0000 -# define FP_CRTC_H_TOTAL_SHIFT 0x00000000 -# define FP_CRTC_H_DISP_SHIFT 0x00000010 -# define FP_CRTC_V_TOTAL_SHIFT 0x00000000 -# define FP_CRTC_V_DISP_SHIFT 0x00000010 -# define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 -# define FP_H_SYNC_WID_SHIFT 0x00000010 -# define FP_V_SYNC_STRT_SHIFT 0x00000000 -# define FP_V_SYNC_WID_SHIFT 0x00000010 -#define CRT_CRTC_H_SYNC_STRT_WID 0x0258 -#define CRT_CRTC_V_SYNC_STRT_WID 0x025C -#define CUR_OFFSET 0x0260 -#define CUR_HORZ_VERT_POSN 0x0264 -#define CUR_HORZ_VERT_OFF 0x0268 -/* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */ -# define CUR_LOCK 0x80000000 -#define CUR_CLR0 0x026C -#define CUR_CLR1 0x0270 -#define CUR2_OFFSET 0x0360 -#define CUR2_HORZ_VERT_POSN 0x0364 -#define CUR2_HORZ_VERT_OFF 0x0368 -# define CUR2_LOCK (1 << 31) -#define CUR2_CLR0 0x036c -#define CUR2_CLR1 0x0370 -#define FP_HORZ_VERT_ACTIVE 0x0278 -#define CRTC_MORE_CNTL 0x027C -#define DAC_EXT_CNTL 0x0280 -#define FP_GEN_CNTL 0x0284 -/* FP_GEN_CNTL bit constants */ -# define FP_FPON (1 << 0) -# define FP_TMDS_EN (1 << 2) -# define FP_EN_TMDS (1 << 7) -# define FP_DETECT_SENSE (1 << 8) -# define FP_SEL_CRTC2 (1 << 13) -# define FP_CRTC_DONT_SHADOW_HPAR (1 << 15) -# define FP_CRTC_DONT_SHADOW_VPAR (1 << 16) -# define FP_CRTC_DONT_SHADOW_HEND (1 << 17) -# define FP_CRTC_USE_SHADOW_VEND (1 << 18) -# define FP_RMX_HVSYNC_CONTROL_EN (1 << 20) -# define FP_DFP_SYNC_SEL (1 << 21) -# define FP_CRTC_LOCK_8DOT (1 << 22) -# define FP_CRT_SYNC_SEL (1 << 23) -# define FP_USE_SHADOW_EN (1 << 24) -# define FP_CRT_SYNC_ALT (1 << 26) -#define FP2_GEN_CNTL 0x0288 -/* FP2_GEN_CNTL bit constants */ -# define FP2_FPON (1 << 0) -# define FP2_TMDS_EN (1 << 2) -# define FP2_EN_TMDS (1 << 7) -# define FP2_DETECT_SENSE (1 << 8) -# define FP2_SEL_CRTC2 (1 << 13) -# define FP2_FP_POL (1 << 16) -# define FP2_LP_POL (1 << 17) -# define FP2_SCK_POL (1 << 18) -# define FP2_LCD_CNTL_MASK (7 << 19) -# define FP2_PAD_FLOP_EN (1 << 22) -# define FP2_CRC_EN (1 << 23) -# define FP2_CRC_READ_EN (1 << 24) -#define FP_HORZ_STRETCH 0x028C -#define FP_HORZ2_STRETCH 0x038C -# define HORZ_STRETCH_RATIO_MASK 0xffff -# define HORZ_STRETCH_RATIO_MAX 4096 -# define HORZ_PANEL_SIZE (0x1ff << 16) -# define HORZ_PANEL_SHIFT 16 -# define HORZ_STRETCH_PIXREP (0 << 25) -# define HORZ_STRETCH_BLEND (1 << 26) -# define HORZ_STRETCH_ENABLE (1 << 25) -# define HORZ_AUTO_RATIO (1 << 27) -# define HORZ_FP_LOOP_STRETCH (0x7 << 28) -# define HORZ_AUTO_RATIO_INC (1 << 31) -#define FP_VERT_STRETCH 0x0290 -#define FP_VERT2_STRETCH 0x0390 -# define VERT_PANEL_SIZE (0xfff << 12) -# define VERT_PANEL_SHIFT 12 -# define VERT_STRETCH_RATIO_MASK 0xfff -# define VERT_STRETCH_RATIO_SHIFT 0 -# define VERT_STRETCH_RATIO_MAX 4096 -# define VERT_STRETCH_ENABLE (1 << 25) -# define VERT_STRETCH_LINEREP (0 << 26) -# define VERT_STRETCH_BLEND (1 << 26) -# define VERT_AUTO_RATIO_EN (1 << 27) -# define VERT_STRETCH_RESERVED 0xf1000000 -#define FP_H_SYNC_STRT_WID 0x02C4 -#define FP_H2_SYNC_STRT_WID 0x03C4 -#define FP_V_SYNC_STRT_WID 0x02C8 -#define FP_V2_SYNC_STRT_WID 0x03C8 -#define LVDS_GEN_CNTL 0x02d0 -# define LVDS_ON (1 << 0) -# define LVDS_DISPLAY_DIS (1 << 1) -# define LVDS_PANEL_TYPE (1 << 2) -# define LVDS_PANEL_FORMAT (1 << 3) -# define LVDS_EN (1 << 7) -# define LVDS_DIGON (1 << 18) -# define LVDS_BLON (1 << 19) -# define LVDS_SEL_CRTC2 (1 << 23) -#define LVDS_PLL_CNTL 0x02d4 -# define HSYNC_DELAY_SHIFT 28 -# define HSYNC_DELAY_MASK (0xf << 28) -#define AUX_WINDOW_HORZ_CNTL 0x02D8 -#define AUX_WINDOW_VERT_CNTL 0x02DC -#define DDA_CONFIG 0x02e0 -#define DDA_ON_OFF 0x02e4 - -#define GRPH_BUFFER_CNTL 0x02F0 -#define VGA_BUFFER_CNTL 0x02F4 - -/* first overlay unit (there is only one) */ - -#define OV0_Y_X_START 0x0400 -#define OV0_Y_X_END 0x0404 -#define OV0_PIPELINE_CNTL 0x0408 -#define OV0_EXCLUSIVE_HORZ 0x0408 -# define EXCL_HORZ_START_MASK 0x000000ff -# define EXCL_HORZ_END_MASK 0x0000ff00 -# define EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000 -# define EXCL_HORZ_EXCLUSIVE_EN 0x80000000 -#define OV0_EXCLUSIVE_VERT 0x040C -# define EXCL_VERT_START_MASK 0x000003ff -# define EXCL_VERT_END_MASK 0x03ff0000 -#define OV0_REG_LOAD_CNTL 0x0410 -# define REG_LD_CTL_LOCK 0x00000001L -# define REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L -# define REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L -# define REG_LD_CTL_LOCK_READBACK 0x00000008L -#define OV0_SCALE_CNTL 0x0420 -# define SCALER_PIX_EXPAND 0x00000001L -# define SCALER_Y2R_TEMP 0x00000002L -#ifdef RAGE128 -# define SCALER_HORZ_PICK_NEAREST 0x00000003L -# define SCALER_VERT_PICK_NEAREST 0x00000004L -#else -# define SCALER_HORZ_PICK_NEAREST 0x00000004L -# define SCALER_VERT_PICK_NEAREST 0x00000008L -#endif -# define SCALER_SIGNED_UV 0x00000010L -# define SCALER_GAMMA_SEL_MASK 0x00000060L -# define SCALER_GAMMA_SEL_BRIGHT 0x00000000L -# define SCALER_GAMMA_SEL_G22 0x00000020L -# define SCALER_GAMMA_SEL_G18 0x00000040L -# define SCALER_GAMMA_SEL_G14 0x00000060L -# define SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L -# define SCALER_SURFAC_FORMAT 0x00000f00L -# define SCALER_SOURCE_UNK0 0x00000000L /* 2 bpp ??? */ -# define SCALER_SOURCE_UNK1 0x00000100L /* 4 bpp ??? */ -# define SCALER_SOURCE_UNK2 0x00000200L /* 8 bpp ??? */ -# define SCALER_SOURCE_15BPP 0x00000300L -# define SCALER_SOURCE_16BPP 0x00000400L -/*# define SCALER_SOURCE_24BPP 0x00000500L*/ -# define SCALER_SOURCE_32BPP 0x00000600L -# define SCALER_SOURCE_UNK3 0x00000700L /* 8BPP_RGB332 ??? */ -# define SCALER_SOURCE_UNK4 0x00000800L /* 8BPP_Y8 ??? */ -# define SCALER_SOURCE_YUV9 0x00000900L /* 8BPP_RGB8 */ -# define SCALER_SOURCE_YUV12 0x00000A00L -# define SCALER_SOURCE_VYUY422 0x00000B00L -# define SCALER_SOURCE_YVYU422 0x00000C00L -# define SCALER_SOURCE_UNK5 0x00000D00L /* ??? */ -# define SCALER_SOURCE_UNK6 0x00000E00L /* 32BPP_AYUV444 */ -# define SCALER_SOURCE_UNK7 0x00000F00L /* 16BPP_ARGB4444 */ -# define SCALER_ADAPTIVE_DEINT 0x00001000L -# define R200_SCALER_TEMPORAL_DEINT 0x00002000L -# define SCALER_UNKNOWN_FLAG1 0x00004000L /* ??? */ -# define SCALER_SMART_SWITCH 0x00008000L -#ifdef RAGE128 -# define SCALER_BURST_PER_PLANE 0x00ff0000L -#else -# define SCALER_BURST_PER_PLANE 0x007f0000L -#endif -# define SCALER_DOUBLE_BUFFER 0x01000000L -# define SCALER_UNKNOWN_FLAG3 0x02000000L /* ??? */ -# define SCALER_UNKNOWN_FLAG4 0x04000000L /* ??? */ -# define SCALER_DIS_LIMIT 0x08000000L -#ifdef RAGE128 -# define SCALER_PRG_LOAD_START 0x10000000L -#endif -# define SCALER_INT_EMU 0x20000000L -# define SCALER_ENABLE 0x40000000L -# define SCALER_SOFT_RESET 0x80000000L -#define OV0_V_INC 0x0424 -#define OV0_P1_V_ACCUM_INIT 0x0428 -# define OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L -# define OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L -#define OV0_P23_V_ACCUM_INIT 0x042C -# define OV0_P23_MAX_LN_IN_PER_LN_OUT 0x00000003L -# define OV0_P23_V_ACCUM_INIT_MASK 0x01ff8000L -#define OV0_P1_BLANK_LINES_AT_TOP 0x0430 -# define P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL -# define P1_ACTIVE_LINES_M1 0x0fff0000L -#define OV0_P23_BLANK_LINES_AT_TOP 0x0434 -# define P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL -# define P23_ACTIVE_LINES_M1 0x07ff0000L -#ifndef RAGE128 -#define OV0_BASE_ADDR 0x043C -#endif -#define OV0_VID_BUF0_BASE_ADRS 0x0440 -# define VIF_BUF0_PITCH_SEL 0x00000001L -# define VIF_BUF0_TILE_ADRS 0x00000002L -# define VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L -# define VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L -#define OV0_VID_BUF1_BASE_ADRS 0x0444 -# define VIF_BUF1_PITCH_SEL 0x00000001L -# define VIF_BUF1_TILE_ADRS 0x00000002L -# define VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L -# define VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L -#define OV0_VID_BUF2_BASE_ADRS 0x0448 -# define VIF_BUF2_PITCH_SEL 0x00000001L -# define VIF_BUF2_TILE_ADRS 0x00000002L -# define VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L -# define VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L -#define OV0_VID_BUF3_BASE_ADRS 0x044C -# define VIF_BUF3_PITCH_SEL 0x00000001L -# define VIF_BUF3_TILE_ADRS 0x00000002L -# define VIF_BUF3_BASE_ADRS_MASK 0x03fffff0L -# define VIF_BUF3_1ST_LINE_LSBS_MASK 0x48000000L -#define OV0_VID_BUF4_BASE_ADRS 0x0450 -# define VIF_BUF4_PITCH_SEL 0x00000001L -# define VIF_BUF4_TILE_ADRS 0x00000002L -# define VIF_BUF4_BASE_ADRS_MASK 0x03fffff0L -# define VIF_BUF4_1ST_LINE_LSBS_MASK 0x48000000L -#define OV0_VID_BUF5_BASE_ADRS 0x0454 -# define VIF_BUF5_PITCH_SEL 0x00000001L -# define VIF_BUF5_TILE_ADRS 0x00000002L -# define VIF_BUF5_BASE_ADRS_MASK 0x03fffff0L -# define VIF_BUF5_1ST_LINE_LSBS_MASK 0x48000000L -#define OV0_VID_BUF_PITCH0_VALUE 0x0460 -#define OV0_VID_BUF_PITCH1_VALUE 0x0464 -#define OV0_AUTO_FLIP_CNTL 0x0470 -# define OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x00000007 -# define OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x00000008 -# define OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x00000010 -# define OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020 -# define OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x00000040 -# define OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x00000300 -# define OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x00010000 -# define OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x00040000 -# define OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x00080000 -# define OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x00800000 -#define OV0_DEINTERLACE_PATTERN 0x0474 -#define OV0_SUBMIT_HISTORY 0x0478 -#define OV0_H_INC 0x0480 -#define OV0_STEP_BY 0x0484 -#define OV0_P1_H_ACCUM_INIT 0x0488 -#define OV0_P23_H_ACCUM_INIT 0x048C -#define OV0_P1_X_START_END 0x0494 -#define OV0_P2_X_START_END 0x0498 -#define OV0_P3_X_START_END 0x049C -#define OV0_FILTER_CNTL 0x04A0 -# define FILTER_PROGRAMMABLE_COEF 0x00000000 -# define FILTER_HARD_SCALE_HORZ_Y 0x00000001 -# define FILTER_HARD_SCALE_HORZ_UV 0x00000002 -# define FILTER_HARD_SCALE_VERT_Y 0x00000004 -# define FILTER_HARD_SCALE_VERT_UV 0x00000008 -# define FILTER_HARDCODED_COEF 0x0000000F -# define FILTER_COEF_MASK 0x0000000F -/* When bit is set hard coded coefficients are used. */ - -/* - Top quality 4x4-tap filtered vertical and horizontal scaler. - It allows up to 64:1 upscaling and downscaling without - performance or quality degradation. -*/ -#define OV0_FOUR_TAP_COEF_0 0x04B0 -# define OV0_FOUR_TAP_PHASE_0_TAP_0 0x0000000F -# define OV0_FOUR_TAP_PHASE_0_TAP_1 0x00007F00 -# define OV0_FOUR_TAP_PHASE_0_TAP_2 0x007F0000 -# define OV0_FOUR_TAP_PHASE_0_TAP_3 0x0F000000 -#define OV0_FOUR_TAP_COEF_1 0x04B4 -# define OV0_FOUR_TAP_PHASE_1_5_TAP_0 0x0000000F -# define OV0_FOUR_TAP_PHASE_1_5_TAP_1 0x00007F00 -# define OV0_FOUR_TAP_PHASE_1_5_TAP_2 0x007F0000 -# define OV0_FOUR_TAP_PHASE_1_5_TAP_3 0x0F000000 -#define OV0_FOUR_TAP_COEF_2 0x04B8 -# define OV0_FOUR_TAP_PHASE_2_6_TAP_0 0x0000000F -# define OV0_FOUR_TAP_PHASE_2_6_TAP_1 0x00007F00 -# define OV0_FOUR_TAP_PHASE_2_6_TAP_2 0x007F0000 -# define OV0_FOUR_TAP_PHASE_2_6_TAP_3 0x0F000000 -#define OV0_FOUR_TAP_COEF_3 0x04BC -# define OV0_FOUR_TAP_PHASE_3_7_TAP_0 0x0000000F -# define OV0_FOUR_TAP_PHASE_3_7_TAP_1 0x00007F00 -# define OV0_FOUR_TAP_PHASE_3_7_TAP_2 0x007F0000 -# define OV0_FOUR_TAP_PHASE_3_7_TAP_3 0x0F000000 -#define OV0_FOUR_TAP_COEF_4 0x04C0 -# define OV0_FOUR_TAP_PHASE_4_TAP_0 0x0000000F -# define OV0_FOUR_TAP_PHASE_4_TAP_1 0x00007F00 -# define OV0_FOUR_TAP_PHASE_4_TAP_2 0x007F0000 -# define OV0_FOUR_TAP_PHASE_4_TAP_3 0x0F000000 -/* 0th_tap means that the left most of top most pixel in a set of four will - be multiplied by this coefficient. */ - -#define OV0_FLAG_CNTL 0x04DC -#ifdef RAGE128 -#define OV0_COLOUR_CNTL 0x04E0 -# define COLOUR_CNTL_BRIGHTNESS 0x0000007F -# define COLOUR_CNTL_SATURATION 0x001F1F00 -#else -/* NB: radeons have no COLOUR_CNTL register */ -#define OV0_SLICE_CNTL 0x04E0 -# define SLICE_CNTL_DISABLE 0x40000000 -#endif -/* Video and graphics keys allow alpha blending, color correction - and many other video effects */ -#define OV0_VID_KEY_CLR 0x04E4 -#define OV0_VID_KEY_MSK 0x04E8 -#define OV0_GRAPHICS_KEY_CLR 0x04EC -#define OV0_GRAPHICS_KEY_MSK 0x04F0 -#define OV0_KEY_CNTL 0x04F4 -#ifdef RAGE128 -# define VIDEO_KEY_FN_MASK 0x00000007L -# define VIDEO_KEY_FN_FALSE 0x00000000L -# define VIDEO_KEY_FN_TRUE 0x00000001L -# define VIDEO_KEY_FN_EQ 0x00000004L -# define VIDEO_KEY_FN_NE 0x00000005L -# define GRAPHIC_KEY_FN_MASK 0x00000070L -# define GRAPHIC_KEY_FN_FALSE 0x00000000L -# define GRAPHIC_KEY_FN_TRUE 0x00000010L -# define GRAPHIC_KEY_FN_EQ 0x00000040L -# define GRAPHIC_KEY_FN_NE 0x00000050L -#else -# define VIDEO_KEY_FN_MASK 0x00000003L -# define VIDEO_KEY_FN_FALSE 0x00000000L -# define VIDEO_KEY_FN_TRUE 0x00000001L -# define VIDEO_KEY_FN_EQ 0x00000002L -# define VIDEO_KEY_FN_NE 0x00000003L -# define GRAPHIC_KEY_FN_MASK 0x00000030L -# define GRAPHIC_KEY_FN_FALSE 0x00000000L -# define GRAPHIC_KEY_FN_TRUE 0x00000010L -# define GRAPHIC_KEY_FN_EQ 0x00000020L -# define GRAPHIC_KEY_FN_NE 0x00000030L -#endif -# define CMP_MIX_MASK 0x00000100L -# define CMP_MIX_OR 0x00000000L -# define CMP_MIX_AND 0x00000100L -#define OV0_TEST 0x04F8 -#define OV0_LIN_TRANS_A 0x0D20 -#define OV0_LIN_TRANS_B 0x0D24 -#define OV0_LIN_TRANS_C 0x0D28 -#define OV0_LIN_TRANS_D 0x0D2C -#define OV0_LIN_TRANS_E 0x0D30 -#define OV0_LIN_TRANS_F 0x0D34 -#define OV0_GAMMA_0_F 0x0D40 -#define OV0_GAMMA_10_1F 0x0D44 -#define OV0_GAMMA_20_3F 0x0D48 -#define OV0_GAMMA_40_7F 0x0D4C -/* These registers exist on R200 only */ -#define OV0_GAMMA_80_BF 0x0E00 -#define OV0_GAMMA_C0_FF 0x0E04 -#define OV0_GAMMA_100_13F 0x0E08 -#define OV0_GAMMA_140_17F 0x0E0C -#define OV0_GAMMA_180_1BF 0x0E10 -#define OV0_GAMMA_1C0_1FF 0x0E14 -#define OV0_GAMMA_200_23F 0x0E18 -#define OV0_GAMMA_240_27F 0x0E1C -#define OV0_GAMMA_280_2BF 0x0E20 -#define OV0_GAMMA_2C0_2FF 0x0E24 -#define OV0_GAMMA_300_33F 0x0E28 -#define OV0_GAMMA_340_37F 0x0E2C -/* End of R200 specific definitions */ -#define OV0_GAMMA_380_3BF 0x0D50 -#define OV0_GAMMA_3C0_3FF 0x0D54 - -/* - IDCT ENGINE: - It's MPEG-2 hardware decoder which incorporates run-level decode, de-zigzag - and IDCT into an IDCT engine to complement the motion compensation engine. -*/ -#define IDCT_RUNS 0x1F80 -#define IDCT_LEVELS 0x1F84 -#define IDCT_AUTH_CONTROL 0x1F88 -#define IDCT_AUTH 0x1F8C -#define IDCT_CONTROL 0x1FBC - -#define SE_MC_SRC2_CNTL 0x19D4 -#define SE_MC_SRC1_CNTL 0x19D8 -#define SE_MC_DST_CNTL 0x19DC -#define SE_MC_CNTL_START 0x19E0 -#ifndef RAGE128 -#define SE_MC_BUF_BASE 0x19E4 -#define PP_MC_CONTEXT 0x19E8 -#define PP_MISC 0x1C14 -#endif -/* - SUBPICTURE UNIT: - Decompressing, scaling and alpha blending the compressed bitmap on the fly. - Provide optimal DVD subpicture qualtity. -*/ -#define SUBPIC_CNTL 0x0540 -#define SUBPIC_DEFCOLCON 0x0544 -#define SUBPIC_Y_X_START 0x054C -#define SUBPIC_Y_X_END 0x0550 -#define SUBPIC_V_INC 0x0554 -#define SUBPIC_H_INC 0x0558 -#define SUBPIC_BUF0_OFFSET 0x055C -#define SUBPIC_BUF1_OFFSET 0x0560 -#define SUBPIC_LC0_OFFSET 0x0564 -#define SUBPIC_LC1_OFFSET 0x0568 -#define SUBPIC_PITCH 0x056C -#define SUBPIC_BTN_HLI_COLCON 0x0570 -#define SUBPIC_BTN_HLI_Y_X_START 0x0574 -#define SUBPIC_BTN_HLI_Y_X_END 0x0578 -#define SUBPIC_PALETTE_INDEX 0x057C -#define SUBPIC_PALETTE_DATA 0x0580 -#define SUBPIC_H_ACCUM_INIT 0x0584 -#define SUBPIC_V_ACCUM_INIT 0x0588 - -#define CP_RB_BASE 0x0700 -#define CP_RB_CNTL 0x0704 -#define CP_RB_RPTR_ADDR 0x070C -#define CP_RB_RPTR 0x0710 -#define CP_RB_WPTR 0x0714 -#define CP_RB_WPTR_DELAY 0x0718 -#define CP_IB_BASE 0x0738 -#define CP_IB_BUFSZ 0x073C -#define CP_CSQ_CNTL 0x0740 -#define SCRATCH_UMSK 0x0770 -#define SCRATCH_ADDR 0x0774 -#define DMA_GUI_TABLE_ADDR 0x0780 -# define DMA_GUI_COMMAND__BYTE_COUNT_MASK 0x001fffff -# define DMA_GUI_COMMAND__INTDIS 0x40000000 -# define DMA_GUI_COMMAND__EOL 0x80000000 -#define DMA_GUI_SRC_ADDR 0x0784 -#define DMA_GUI_DST_ADDR 0x0788 -#define DMA_GUI_COMMAND 0x078C -#define DMA_GUI_STATUS 0x0790 -#define DMA_GUI_ACT_DSCRPTR 0x0794 -#define DMA_VID_TABLE_ADDR 0x07A0 -#define DMA_VID_SRC_ADDR 0x07A4 -#define DMA_VID_DST_ADDR 0x07A8 -#define DMA_VID_COMMAND 0x07AC -#define DMA_VID_STATUS 0x07B0 -#define DMA_VID_ACT_DSCRPTR 0x07B4 -#define CP_ME_CNTL 0x07D0 -#define CP_ME_RAM_ADDR 0x07D4 -#define CP_ME_RAM_RADDR 0x07D8 -#define CP_ME_RAM_DATAH 0x07DC -#define CP_ME_RAM_DATAL 0x07E0 -#define CP_CSQ_ADDR 0x07F0 -#define CP_CSQ_DATA 0x07F4 -#define CP_CSQ_STAT 0x07F8 - -#define DISP_MISC_CNTL 0x0D00 -# define SOFT_RESET_GRPH_PP (1 << 0) -#define DAC_MACRO_CNTL 0x0D04 -#define DISP_PWR_MAN 0x0D08 -#define DISP_TEST_DEBUG_CNTL 0x0D10 -#define DISP_HW_DEBUG 0x0D14 -#define DAC_CRC_SIG1 0x0D18 -#define DAC_CRC_SIG2 0x0D1C - -/* first capture unit */ - -#define VID_BUFFER_CONTROL 0x0900 -#define CAP_INT_CNTL 0x0908 -#define CAP_INT_STATUS 0x090C -#define FCP_CNTL 0x0910 -# define FCP_CNTL__PCICLK 0 -# define FCP_CNTL__PCLK 1 -# define FCP_CNTL__PCLKb 2 -# define FCP_CNTL__HREF 3 -# define FCP_CNTL__GND 4 -# define FCP_CNTL__HREFb 5 - -#define CAP0_BUF0_OFFSET 0x0920 -#define CAP0_BUF1_OFFSET 0x0924 -#define CAP0_BUF0_EVEN_OFFSET 0x0928 -#define CAP0_BUF1_EVEN_OFFSET 0x092C -#define CAP0_BUF_PITCH 0x0930 -#define CAP0_V_WINDOW 0x0934 -#define CAP0_H_WINDOW 0x0938 -#define CAP0_VBI0_OFFSET 0x093C -#define CAP0_VBI1_OFFSET 0x0940 -#define CAP0_VBI_V_WINDOW 0x0944 -#define CAP0_VBI_H_WINDOW 0x0948 -#define CAP0_PORT_MODE_CNTL 0x094C -#define CAP0_TRIG_CNTL 0x0950 -#define CAP0_DEBUG 0x0954 -#define CAP0_CONFIG 0x0958 -# define CAP0_CONFIG_CONTINUOS 0x00000001 -# define CAP0_CONFIG_START_FIELD_EVEN 0x00000002 -# define CAP0_CONFIG_START_BUF_GET 0x00000004 -# define CAP0_CONFIG_START_BUF_SET 0x00000008 -# define CAP0_CONFIG_BUF_TYPE_ALT 0x00000010 -# define CAP0_CONFIG_BUF_TYPE_FRAME 0x00000020 -# define CAP0_CONFIG_ONESHOT_MODE_FRAME 0x00000040 -# define CAP0_CONFIG_BUF_MODE_DOUBLE 0x00000080 -# define CAP0_CONFIG_BUF_MODE_TRIPLE 0x00000100 -# define CAP0_CONFIG_MIRROR_EN 0x00000200 -# define CAP0_CONFIG_ONESHOT_MIRROR_EN 0x00000400 -# define CAP0_CONFIG_VIDEO_SIGNED_UV 0x00000800 -# define CAP0_CONFIG_ANC_DECODE_EN 0x00001000 -# define CAP0_CONFIG_VBI_EN 0x00002000 -# define CAP0_CONFIG_SOFT_PULL_DOWN_EN 0x00004000 -# define CAP0_CONFIG_VIP_EXTEND_FLAG_EN 0x00008000 -# define CAP0_CONFIG_FAKE_FIELD_EN 0x00010000 -# define CAP0_CONFIG_ODD_ONE_MORE_LINE 0x00020000 -# define CAP0_CONFIG_EVEN_ONE_MORE_LINE 0x00040000 -# define CAP0_CONFIG_HORZ_DIVIDE_2 0x00080000 -# define CAP0_CONFIG_HORZ_DIVIDE_4 0x00100000 -# define CAP0_CONFIG_VERT_DIVIDE_2 0x00200000 -# define CAP0_CONFIG_VERT_DIVIDE_4 0x00400000 -# define CAP0_CONFIG_FORMAT_BROOKTREE 0x00000000 -# define CAP0_CONFIG_FORMAT_CCIR656 0x00800000 -# define CAP0_CONFIG_FORMAT_ZV 0x01000000 -# define CAP0_CONFIG_FORMAT_VIP 0x01800000 -# define CAP0_CONFIG_FORMAT_TRANSPORT 0x02000000 -# define CAP0_CONFIG_HORZ_DECIMATOR 0x04000000 -# define CAP0_CONFIG_VIDEO_IN_YVYU422 0x00000000 -# define CAP0_CONFIG_VIDEO_IN_VYUY422 0x20000000 -# define CAP0_CONFIG_VBI_DIVIDE_2 0x40000000 -# define CAP0_CONFIG_VBI_DIVIDE_4 0x80000000 -#define CAP0_ANC_ODD_OFFSET 0x095C -#define CAP0_ANC_EVEN_OFFSET 0x0960 -#define CAP0_ANC_H_WINDOW 0x0964 -#define CAP0_VIDEO_SYNC_TEST 0x0968 -#define CAP0_ONESHOT_BUF_OFFSET 0x096C -#define CAP0_BUF_STATUS 0x0970 -#ifdef RAGE128 -#define CAP0_DWNSC_XRATIO 0x0978 -#define CAP0_XSHARPNESS 0x097C -#else -/* #define CAP0_DWNSC_XRATIO 0x0978 */ -/* #define CAP0_XSHARPNESS 0x097C */ -#endif -#define CAP0_VBI2_OFFSET 0x0980 -#define CAP0_VBI3_OFFSET 0x0984 -#define CAP0_ANC2_OFFSET 0x0988 -#define CAP0_ANC3_OFFSET 0x098C - -/* second capture unit */ - -#define CAP1_BUF0_OFFSET 0x0990 -#define CAP1_BUF1_OFFSET 0x0994 -#define CAP1_BUF0_EVEN_OFFSET 0x0998 -#define CAP1_BUF1_EVEN_OFFSET 0x099C - -#define CAP1_BUF_PITCH 0x09A0 -#define CAP1_V_WINDOW 0x09A4 -#define CAP1_H_WINDOW 0x09A8 -#define CAP1_VBI_ODD_OFFSET 0x09AC -#define CAP1_VBI_EVEN_OFFSET 0x09B0 -#define CAP1_VBI_V_WINDOW 0x09B4 -#define CAP1_VBI_H_WINDOW 0x09B8 -#define CAP1_PORT_MODE_CNTL 0x09BC -#define CAP1_TRIG_CNTL 0x09C0 -#define CAP1_DEBUG 0x09C4 -#define CAP1_CONFIG 0x09C8 -#define CAP1_ANC_ODD_OFFSET 0x09CC -#define CAP1_ANC_EVEN_OFFSET 0x09D0 -#define CAP1_ANC_H_WINDOW 0x09D4 -#define CAP1_VIDEO_SYNC_TEST 0x09D8 -#define CAP1_ONESHOT_BUF_OFFSET 0x09DC -#define CAP1_BUF_STATUS 0x09E0 -#define CAP1_DWNSC_XRATIO 0x09E8 -#define CAP1_XSHARPNESS 0x09EC - -#define DISP_MERGE_CNTL 0x0D60 -#define DISP_OUTPUT_CNTL 0x0D64 -# define DISP_DAC_SOURCE_MASK 0x03 -# define DISP_DAC_SOURCE_CRTC2 0x01 -#define DISP_LIN_TRANS_GRPH_A 0x0D80 -#define DISP_LIN_TRANS_GRPH_B 0x0D84 -#define DISP_LIN_TRANS_GRPH_C 0x0D88 -#define DISP_LIN_TRANS_GRPH_D 0x0D8C -#define DISP_LIN_TRANS_GRPH_E 0x0D90 -#define DISP_LIN_TRANS_GRPH_F 0x0D94 -#define DISP_LIN_TRANS_VID_A 0x0D98 -#define DISP_LIN_TRANS_VID_B 0x0D9C -#define DISP_LIN_TRANS_VID_C 0x0DA0 -#define DISP_LIN_TRANS_VID_D 0x0DA4 -#define DISP_LIN_TRANS_VID_E 0x0DA8 -#define DISP_LIN_TRANS_VID_F 0x0DAC -#define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0 -#define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4 -#define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8 -#define RMX_HORZ_PHASE 0x0DBC -#define DAC_EMBEDDED_SYNC_CNTL 0x0DC0 -#define DAC_BROAD_PULSE 0x0DC4 -#define DAC_SKEW_CLKS 0x0DC8 -#define DAC_INCR 0x0DCC -#define DAC_NEG_SYNC_LEVEL 0x0DD0 -#define DAC_POS_SYNC_LEVEL 0x0DD4 -#define DAC_BLANK_LEVEL 0x0DD8 -#define CLOCK_CNTL_INDEX 0x0008 -/* CLOCK_CNTL_INDEX bit constants */ -# define PLL_WR_EN 0x00000080 -# define PLL_DIV_SEL (3 << 8) -# define PLL2_DIV_SEL_MASK ~(3 << 8) -#define CLOCK_CNTL_DATA 0x000C -#define CP_RB_CNTL 0x0704 -#define CP_RB_BASE 0x0700 -#define CP_RB_RPTR_ADDR 0x070C -#define CP_RB_RPTR 0x0710 -#define CP_RB_WPTR 0x0714 -#define CP_RB_WPTR_DELAY 0x0718 -#define CP_IB_BASE 0x0738 -#define CP_IB_BUFSZ 0x073C -#define SCRATCH_REG0 0x15E0 -#define GUI_SCRATCH_REG0 0x15E0 -#define SCRATCH_REG1 0x15E4 -#define GUI_SCRATCH_REG1 0x15E4 -#define SCRATCH_REG2 0x15E8 -#define GUI_SCRATCH_REG2 0x15E8 -#define SCRATCH_REG3 0x15EC -#define GUI_SCRATCH_REG3 0x15EC -#define SCRATCH_REG4 0x15F0 -#define GUI_SCRATCH_REG4 0x15F0 -#define SCRATCH_REG5 0x15F4 -#define GUI_SCRATCH_REG5 0x15F4 -#define SCRATCH_UMSK 0x0770 -#define SCRATCH_ADDR 0x0774 -#define DP_BRUSH_FRGD_CLR 0x147C -#define DP_BRUSH_BKGD_CLR 0x1478 -#define DST_LINE_START 0x1600 -#define DST_LINE_END 0x1604 -#define SRC_OFFSET 0x15AC -#define SRC_PITCH 0x15B0 -#define SRC_TILE 0x1704 -#define SRC_PITCH_OFFSET 0x1428 -#define SRC_X 0x1414 -#define SRC_Y 0x1418 -#define DST_WIDTH_X 0x1588 -#define DST_HEIGHT_WIDTH_8 0x158C -#define SRC_X_Y 0x1590 -#define SRC_Y_X 0x1434 -#define DST_Y_X 0x1438 -#define DST_WIDTH_HEIGHT 0x1598 -#define DST_HEIGHT_WIDTH 0x143c -#ifdef RAGE128 -#define GUI_STAT 0x1740 -# define GUI_FIFOCNT_MASK 0x0fff -# define GUI_ACTIVE (1 << 31) -#endif -#define SRC_CLUT_ADDRESS 0x1780 -#define SRC_CLUT_DATA 0x1784 -#define SRC_CLUT_DATA_RD 0x1788 -#define HOST_DATA0 0x17C0 -#define HOST_DATA1 0x17C4 -#define HOST_DATA2 0x17C8 -#define HOST_DATA3 0x17CC -#define HOST_DATA4 0x17D0 -#define HOST_DATA5 0x17D4 -#define HOST_DATA6 0x17D8 -#define HOST_DATA7 0x17DC -#define HOST_DATA_LAST 0x17E0 -#define DP_SRC_ENDIAN 0x15D4 -#define DP_SRC_FRGD_CLR 0x15D8 -#define DP_SRC_BKGD_CLR 0x15DC -#define DP_WRITE_MASK 0x16cc -#define SC_LEFT 0x1640 -#define SC_RIGHT 0x1644 -#define SC_TOP 0x1648 -#define SC_BOTTOM 0x164C -#define SRC_SC_RIGHT 0x1654 -#define SRC_SC_BOTTOM 0x165C -#define DP_CNTL 0x16C0 -/* DP_CNTL bit constants */ -# define DST_X_RIGHT_TO_LEFT 0x00000000 -# define DST_X_LEFT_TO_RIGHT 0x00000001 -# define DST_Y_BOTTOM_TO_TOP 0x00000000 -# define DST_Y_TOP_TO_BOTTOM 0x00000002 -# define DST_X_MAJOR 0x00000000 -# define DST_Y_MAJOR 0x00000004 -# define DST_X_TILE 0x00000008 -# define DST_Y_TILE 0x00000010 -# define DST_LAST_PEL 0x00000020 -# define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000 -# define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040 -# define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000 -# define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080 -# define DST_BRES_SIGN 0x00000100 -# define DST_HOST_BIG_ENDIAN_EN 0x00000200 -# define DST_POLYLINE_NONLAST 0x00008000 -# define DST_RASTER_STALL 0x00010000 -# define DST_POLY_EDGE 0x00040000 -#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0 -/* DP_CNTL_XDIR_YDIR_YMAJOR bit constants (short version of DP_CNTL) */ -# define DST_X_MAJOR_S 0x00000000 -# define DST_Y_MAJOR_S 0x00000001 -# define DST_Y_BOTTOM_TO_TOP_S 0x00000000 -# define DST_Y_TOP_TO_BOTTOM_S 0x00008000 -# define DST_X_RIGHT_TO_LEFT_S 0x00000000 -# define DST_X_LEFT_TO_RIGHT_S 0x80000000 -#define DP_DATATYPE 0x16C4 -/* DP_DATATYPE bit constants */ -# define DST_8BPP 0x00000002 -# define DST_15BPP 0x00000003 -# define DST_16BPP 0x00000004 -# define DST_24BPP 0x00000005 -# define DST_32BPP 0x00000006 -# define DST_8BPP_RGB332 0x00000007 -# define DST_8BPP_Y8 0x00000008 -# define DST_8BPP_RGB8 0x00000009 -# define DST_16BPP_VYUY422 0x0000000b -# define DST_16BPP_YVYU422 0x0000000c -# define DST_32BPP_AYUV444 0x0000000e -# define DST_16BPP_ARGB4444 0x0000000f -# define BRUSH_SOLIDCOLOR 0x00000d00 -# define SRC_MONO 0x00000000 -# define SRC_MONO_LBKGD 0x00010000 -# define SRC_DSTCOLOR 0x00030000 -# define BYTE_ORDER_MSB_TO_LSB 0x00000000 -# define BYTE_ORDER_LSB_TO_MSB 0x40000000 -# define DP_CONVERSION_TEMP 0x80000000 -# define HOST_BIG_ENDIAN_EN (1 << 29) -#define DP_MIX 0x16C8 -/* DP_MIX bit constants */ -# define DP_SRC_RECT 0x00000200 -# define DP_SRC_HOST 0x00000300 -# define DP_SRC_HOST_BYTEALIGN 0x00000400 -#define DP_WRITE_MSK 0x16CC -#define DP_XOP 0x17F8 -#define CLR_CMP_CLR_SRC 0x15C4 -#define CLR_CMP_CLR_DST 0x15C8 -#define CLR_CMP_CNTL 0x15C0 -/* CLR_CMP_CNTL bit constants */ -# define COMPARE_SRC_FALSE 0x00000000 -# define COMPARE_SRC_TRUE 0x00000001 -# define COMPARE_SRC_NOT_EQUAL 0x00000004 -# define COMPARE_SRC_EQUAL 0x00000005 -# define COMPARE_SRC_EQUAL_FLIP 0x00000007 -# define COMPARE_DST_FALSE 0x00000000 -# define COMPARE_DST_TRUE 0x00000100 -# define COMPARE_DST_NOT_EQUAL 0x00000400 -# define COMPARE_DST_EQUAL 0x00000500 -# define COMPARE_DESTINATION 0x00000000 -# define COMPARE_SOURCE 0x01000000 -# define COMPARE_SRC_AND_DST 0x02000000 -#define CLR_CMP_MSK 0x15CC -#define DSTCACHE_MODE 0x1710 -#define DSTCACHE_CTLSTAT 0x1714 -/* DSTCACHE_CTLSTAT bit constants */ -# define RB2D_DC_FLUSH (3 << 0) -# define RB2D_DC_FLUSH_ALL 0xf -# define RB2D_DC_BUSY (1 << 31) -#define DEFAULT_OFFSET 0x16e0 -#define DEFAULT_PITCH_OFFSET 0x16E0 -#define DEFAULT_SC_BOTTOM_RIGHT 0x16E8 -/* DEFAULT_SC_BOTTOM_RIGHT bit constants */ -# define DEFAULT_SC_RIGHT_MAX (0x1fff << 0) -# define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) -#define DP_GUI_MASTER_CNTL 0x146C -/* DP_GUI_MASTER_CNTL bit constants */ -# define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000 -# define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001 -# define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000 -# define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002 -# define GMC_SRC_CLIP_DEFAULT 0x00000000 -# define GMC_SRC_CLIP_LEAVE 0x00000004 -# define GMC_DST_CLIP_DEFAULT 0x00000000 -# define GMC_DST_CLIP_LEAVE 0x00000008 -# define GMC_BRUSH_8x8MONO 0x00000000 -# define GMC_BRUSH_8x8MONO_LBKGD 0x00000010 -# define GMC_BRUSH_8x1MONO 0x00000020 -# define GMC_BRUSH_8x1MONO_LBKGD 0x00000030 -# define GMC_BRUSH_1x8MONO 0x00000040 -# define GMC_BRUSH_1x8MONO_LBKGD 0x00000050 -# define GMC_BRUSH_32x1MONO 0x00000060 -# define GMC_BRUSH_32x1MONO_LBKGD 0x00000070 -# define GMC_BRUSH_32x32MONO 0x00000080 -# define GMC_BRUSH_32x32MONO_LBKGD 0x00000090 -# define GMC_BRUSH_8x8COLOR 0x000000a0 -# define GMC_BRUSH_8x1COLOR 0x000000b0 -# define GMC_BRUSH_1x8COLOR 0x000000c0 -# define GMC_BRUSH_SOLID_COLOR 0x000000d0 -# define GMC_DST_8BPP 0x00000200 -# define GMC_DST_15BPP 0x00000300 -# define GMC_DST_16BPP 0x00000400 -# define GMC_DST_24BPP 0x00000500 -# define GMC_DST_32BPP 0x00000600 -# define GMC_DST_8BPP_RGB332 0x00000700 -# define GMC_DST_8BPP_Y8 0x00000800 -# define GMC_DST_8BPP_RGB8 0x00000900 -# define GMC_DST_16BPP_VYUY422 0x00000b00 -# define GMC_DST_16BPP_YVYU422 0x00000c00 -# define GMC_DST_32BPP_AYUV444 0x00000e00 -# define GMC_DST_16BPP_ARGB4444 0x00000f00 -# define GMC_SRC_MONO 0x00000000 -# define GMC_SRC_MONO_LBKGD 0x00001000 -# define GMC_SRC_DSTCOLOR 0x00003000 -# define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 -# define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000 -# define GMC_DP_CONVERSION_TEMP_9300 0x00008000 -# define GMC_DP_CONVERSION_TEMP_6500 0x00000000 -# define GMC_DP_SRC_RECT 0x02000000 -# define GMC_DP_SRC_HOST 0x03000000 -# define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000 -# define GMC_3D_FCN_EN_CLR 0x00000000 -# define GMC_3D_FCN_EN_SET 0x08000000 -# define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000 -# define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000 -# define GMC_AUX_CLIP_LEAVE 0x00000000 -# define GMC_AUX_CLIP_CLEAR 0x20000000 -# define GMC_WRITE_MASK_LEAVE 0x00000000 -# define GMC_WRITE_MASK_SET 0x40000000 -# define GMC_CLR_CMP_CNTL_DIS (1 << 28) -# define GMC_SRC_DATATYPE_COLOR (3 << 12) -# define ROP3_S 0x00cc0000 -# define ROP3_SRCCOPY 0x00cc0000 -# define ROP3_P 0x00f00000 -# define ROP3_PATCOPY 0x00f00000 -# define DP_SRC_SOURCE_MASK (7 << 24) -# define GMC_BRUSH_NONE (15 << 4) -# define DP_SRC_SOURCE_MEMORY (2 << 24) -# define GMC_BRUSH_SOLIDCOLOR 0x000000d0 -#define SC_TOP_LEFT 0x16EC -#define SC_BOTTOM_RIGHT 0x16F0 -#define SRC_SC_BOTTOM_RIGHT 0x16F4 -#define RB2D_DSTCACHE_CTLSTAT 0x342C -#define RB2D_DSTCACHE_MODE 0x3428 - -#define BASE_CODE 0x0f0b -#define RADEON_BIOS_0_SCRATCH 0x0010 -#define RADEON_BIOS_1_SCRATCH 0x0014 -#define RADEON_BIOS_2_SCRATCH 0x0018 -#define RADEON_BIOS_3_SCRATCH 0x001c -#define RADEON_BIOS_4_SCRATCH 0x0020 -#define RADEON_BIOS_5_SCRATCH 0x0024 -#define RADEON_BIOS_6_SCRATCH 0x0028 -#define RADEON_BIOS_7_SCRATCH 0x002c - - -#define CLK_PIN_CNTL 0x0001 -#define PPLL_CNTL 0x0002 -# define PPLL_RESET (1 << 0) -# define PPLL_SLEEP (1 << 1) -# define PPLL_ATOMIC_UPDATE_EN (1 << 16) -# define PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17) -# define PPLL_ATOMIC_UPDATE_VSYNC (1 << 18) -#define PPLL_REF_DIV 0x0003 -# define PPLL_REF_DIV_MASK 0x03ff -# define PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ -# define PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ -#define PPLL_DIV_0 0x0004 -#define PPLL_DIV_1 0x0005 -#define PPLL_DIV_2 0x0006 -#define PPLL_DIV_3 0x0007 -#define VCLK_ECP_CNTL 0x0008 -# define VCLK_SRC_SEL_MASK 0x03 -# define VCLK_SRC_SEL_CPUCLK 0x00 -# define VCLK_SRC_SEL_PSCANCLK 0x01 -# define VCLK_SRC_SEL_BYTECLK 0x02 -# define VCLK_SRC_SEL_PPLLCLK 0x03 -#define HTOTAL_CNTL 0x0009 -#define HTOTAL2_CNTL 0x002e /* PLL */ -#define M_SPLL_REF_FB_DIV 0x000a -#define AGP_PLL_CNTL 0x000b -#define SPLL_CNTL 0x000c -#define SCLK_CNTL 0x000d -# define DYN_STOP_LAT_MASK 0x00007ff8 -# define CP_MAX_DYN_STOP_LAT 0x0008 -# define SCLK_FORCEON_MASK 0xffff8000 -#define SCLK_MORE_CNTL 0x0035 /* PLL */ -# define SCLK_MORE_FORCEON 0x0700 -#define MPLL_CNTL 0x000e -#ifdef RAGE128 -#define MCLK_CNTL 0x000f /* PLL */ -# define FORCE_GCP (1 << 16) -# define FORCE_PIPE3D_CP (1 << 17) -# define FORCE_RCP (1 << 18) -#else -#define MCLK_CNTL 0x0012 -/* MCLK_CNTL bit constants */ -# define FORCEON_MCLKA (1 << 16) -# define FORCEON_MCLKB (1 << 17) -# define FORCEON_YCLKA (1 << 18) -# define FORCEON_YCLKB (1 << 19) -# define FORCEON_MC (1 << 20) -# define FORCEON_AIC (1 << 21) -#endif -#define PLL_TEST_CNTL 0x0013 -#define P2PLL_CNTL 0x002a /* P2PLL */ -# define P2PLL_RESET (1 << 0) -# define P2PLL_SLEEP (1 << 1) -# define P2PLL_ATOMIC_UPDATE_EN (1 << 16) -# define P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17) -# define P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18) -#define P2PLL_DIV_0 0x002c -# define P2PLL_FB0_DIV_MASK 0x07ff -# define P2PLL_POST0_DIV_MASK 0x00070000 -#define P2PLL_REF_DIV 0x002B /* PLL */ -# define P2PLL_REF_DIV_MASK 0x03ff -# define P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ -# define P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ -#define PIXCLKS_CNTL 0x002d -# define PIX2CLK_SRC_SEL_MASK 0x03 -# define PIX2CLK_SRC_SEL_CPUCLK 0x00 -# define PIX2CLK_SRC_SEL_PSCANCLK 0x01 -# define PIX2CLK_SRC_SEL_BYTECLK 0x02 -# define PIX2CLK_SRC_SEL_P2PLLCLK 0x03 - -/* masks */ - -#define CONFIG_MEMSIZE_MASK 0x1f000000 -#define MEM_CFG_TYPE 0x40000000 -#define DST_OFFSET_MASK 0x003fffff -#define DST_PITCH_MASK 0x3fc00000 -#define DEFAULT_TILE_MASK 0xc0000000 -#define PPLL_DIV_SEL_MASK 0x00000300 -#define PPLL_FB3_DIV_MASK 0x000007ff -#define PPLL_POST3_DIV_MASK 0x00070000 - -/* BUS MASTERING */ -#define BM_FRAME_BUF_OFFSET 0xA00 -#define BM_SYSTEM_MEM_ADDR 0xA04 -#define BM_COMMAND 0xA08 -# define BM_INTERRUPT_DIS 0x08000000 -# define BM_TRANSFER_DEST_REG 0x10000000 -# define BM_FORCE_TO_PCI 0x20000000 -# define BM_FRAME_OFFSET_HOLD 0x40000000 -# define BM_END_OF_LIST 0x80000000 -#define BM_STATUS 0xA0c -#define BM_QUEUE_STATUS 0xA10 -#define BM_QUEUE_FREE_STATUS 0xA14 -#define BM_CHUNK_0_VAL 0xA18 -# define BM_PTR_FORCE_TO_PCI 0x00200000 -# define BM_PM4_RD_FORCE_TO_PCI 0x00400000 -# define BM_GLOBAL_FORCE_TO_PCI 0x00800000 -# define BM_VIP3_NOCHUNK 0x10000000 -# define BM_VIP2_NOCHUNK 0x20000000 -# define BM_VIP1_NOCHUNK 0x40000000 -# define BM_VIP0_NOCHUNK 0x80000000 -#define BM_CHUNK_1_VAL 0xA1C -#define BM_VIP0_BUF 0xA20 -# define SYSTEM_TRIGGER_SYSTEM_TO_VIDEO 0x0 -# define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM 0x1 -#define BM_VIP0_ACTIVE 0xA24 -#define BM_VIP1_BUF 0xA30 -#define BM_VIP1_ACTIVE 0xA34 -#define BM_VIP2_BUF 0xA40 -#define BM_VIP2_ACTIVE 0xA44 -#define BM_VIP3_BUF 0xA50 -#define BM_VIP3_ACTIVE 0xA54 -#define BM_VIDCAP_BUF0 0xA60 -#define BM_VIDCAP_BUF1 0xA64 -#define BM_VIDCAP_BUF2 0xA68 -#define BM_VIDCAP_ACTIVE 0xA6c -#define BM_GUI 0xA80 - -/* RAGE THEATER REGISTERS */ - -#define DMA_VIPH0_COMMAND 0x0A00 -#define DMA_VIPH1_COMMAND 0x0A04 -#define DMA_VIPH2_COMMAND 0x0A08 -#define DMA_VIPH3_COMMAND 0x0A0C -#define DMA_VIPH_STATUS 0x0A10 -#define DMA_VIPH_CHUNK_0 0x0A18 -#define DMA_VIPH_CHUNK_1_VAL 0x0A1C -#define DMA_VIP0_TABLE_ADDR 0x0A20 -#define DMA_VIPH0_ACTIVE 0x0A24 -#define DMA_VIP1_TABLE_ADDR 0x0A30 -#define DMA_VIPH1_ACTIVE 0x0A34 -#define DMA_VIP2_TABLE_ADDR 0x0A40 -#define DMA_VIPH2_ACTIVE 0x0A44 -#define DMA_VIP3_TABLE_ADDR 0x0A50 -#define DMA_VIPH3_ACTIVE 0x0A54 -#define DMA_VIPH_ABORT 0x0A88 - -#define VIPH_CH0_DATA 0x0c00 -#define VIPH_CH1_DATA 0x0c04 -#define VIPH_CH2_DATA 0x0c08 -#define VIPH_CH3_DATA 0x0c0c -#define VIPH_CH0_ADDR 0x0c10 -#define VIPH_CH1_ADDR 0x0c14 -#define VIPH_CH2_ADDR 0x0c18 -#define VIPH_CH3_ADDR 0x0c1c -#define VIPH_CH0_SBCNT 0x0c20 -#define VIPH_CH1_SBCNT 0x0c24 -#define VIPH_CH2_SBCNT 0x0c28 -#define VIPH_CH3_SBCNT 0x0c2c -#define VIPH_CH0_ABCNT 0x0c30 -#define VIPH_CH1_ABCNT 0x0c34 -#define VIPH_CH2_ABCNT 0x0c38 -#define VIPH_CH3_ABCNT 0x0c3c -#define VIPH_CONTROL 0x0c40 -#define VIPH_DV_LAT 0x0c44 -#define VIPH_BM_CHUNK 0x0c48 -#define VIPH_DV_INT 0x0c4c -#define VIPH_TIMEOUT_STAT 0x0c50 - -#define VIPH_REG_DATA 0x0084 -#define VIPH_REG_ADDR 0x0080 - -/* Address Space Rage Theatre Registers (VIP Access) */ -#define VIP_VIP_VENDOR_DEVICE_ID 0x0000 -#define VIP_VIP_SUB_VENDOR_DEVICE_ID 0x0004 -#define VIP_VIP_COMMAND_STATUS 0x0008 -#define VIP_VIP_REVISION_ID 0x000c -#define VIP_HW_DEBUG 0x0010 -#define VIP_SW_SCRATCH 0x0014 -#define VIP_I2C_CNTL_0 0x0020 -#define VIP_I2C_CNTL_1 0x0024 -#define VIP_I2C_DATA 0x0028 -#define VIP_INT_CNTL 0x002c -#define VIP_GPIO_INOUT 0x0030 -#define VIP_GPIO_CNTL 0x0034 -#define VIP_CLKOUT_GPIO_CNTL 0x0038 -#define VIP_RIPINTF_PORT_CNTL 0x003c -#define VIP_ADC_CNTL 0x0400 -#define VIP_ADC_DEBUG 0x0404 -#define VIP_STANDARD_SELECT 0x0408 -#define VIP_THERMO2BIN_STATUS 0x040c -#define VIP_COMB_CNTL0 0x0440 -#define VIP_COMB_CNTL1 0x0444 -#define VIP_COMB_CNTL2 0x0448 -#define VIP_COMB_LINE_LENGTH 0x044c -#define VIP_NOISE_CNTL0 0x0450 -#define VIP_HS_PLINE 0x0480 -#define VIP_HS_DTOINC 0x0484 -#define VIP_HS_PLLGAIN 0x0488 -#define VIP_HS_MINMAXWIDTH 0x048c -#define VIP_HS_GENLOCKDELAY 0x0490 -#define VIP_HS_WINDOW_LIMIT 0x0494 -#define VIP_HS_WINDOW_OC_SPEED 0x0498 -#define VIP_HS_PULSE_WIDTH 0x049c -#define VIP_HS_PLL_ERROR 0x04a0 -#define VIP_HS_PLL_FS_PATH 0x04a4 -#define VIP_SG_BLACK_GATE 0x04c0 -#define VIP_SG_SYNCTIP_GATE 0x04c4 -#define VIP_SG_UVGATE_GATE 0x04c8 -#define VIP_LP_AGC_CLAMP_CNTL0 0x0500 -#define VIP_LP_AGC_CLAMP_CNTL1 0x0504 -#define VIP_LP_BRIGHTNESS 0x0508 -#define VIP_LP_CONTRAST 0x050c -#define VIP_LP_SLICE_LIMIT 0x0510 -#define VIP_LP_WPA_CNTL0 0x0514 -#define VIP_LP_WPA_CNTL1 0x0518 -#define VIP_LP_BLACK_LEVEL 0x051c -#define VIP_LP_SLICE_LEVEL 0x0520 -#define VIP_LP_SYNCTIP_LEVEL 0x0524 -#define VIP_LP_VERT_LOCKOUT 0x0528 -#define VIP_VS_DETECTOR_CNTL 0x0540 -#define VIP_VS_BLANKING_CNTL 0x0544 -#define VIP_VS_FIELD_ID_CNTL 0x0548 -#define VIP_VS_COUNTER_CNTL 0x054c -#define VIP_VS_FRAME_TOTAL 0x0550 -#define VIP_VS_LINE_COUNT 0x0554 -#define VIP_CP_PLL_CNTL0 0x0580 -#define VIP_CP_PLL_CNTL1 0x0584 -#define VIP_CP_HUE_CNTL 0x0588 -#define VIP_CP_BURST_GAIN 0x058c -#define VIP_CP_AGC_CNTL 0x0590 -#define VIP_CP_ACTIVE_GAIN 0x0594 -#define VIP_CP_PLL_STATUS0 0x0598 -#define VIP_CP_PLL_STATUS1 0x059c -#define VIP_CP_PLL_STATUS2 0x05a0 -#define VIP_CP_PLL_STATUS3 0x05a4 -#define VIP_CP_PLL_STATUS4 0x05a8 -#define VIP_CP_PLL_STATUS5 0x05ac -#define VIP_CP_PLL_STATUS6 0x05b0 -#define VIP_CP_PLL_STATUS7 0x05b4 -#define VIP_CP_DEBUG_FORCE 0x05b8 -#define VIP_CP_VERT_LOCKOUT 0x05bc -#define VIP_H_ACTIVE_WINDOW 0x05c0 -#define VIP_V_ACTIVE_WINDOW 0x05c4 -#define VIP_H_VBI_WINDOW 0x05c8 -#define VIP_V_VBI_WINDOW 0x05cc -#define VIP_VBI_CONTROL 0x05d0 -#define VIP_DECODER_DEBUG_CNTL 0x05d4 -#define VIP_SINGLE_STEP_DATA 0x05d8 -#define VIP_MASTER_CNTL 0x0040 -#define VIP_RGB_CNTL 0x0048 -#define VIP_CLKOUT_CNTL 0x004c -#define VIP_SYNC_CNTL 0x0050 -#define VIP_I2C_CNTL 0x0054 -#define VIP_HTOTAL 0x0080 -#define VIP_HDISP 0x0084 -#define VIP_HSIZE 0x0088 -#define VIP_HSTART 0x008c -#define VIP_HCOUNT 0x0090 -#define VIP_VTOTAL 0x0094 -#define VIP_VDISP 0x0098 -#define VIP_VCOUNT 0x009c -#define VIP_VFTOTAL 0x00a0 -#define VIP_DFCOUNT 0x00a4 -#define VIP_DFRESTART 0x00a8 -#define VIP_DHRESTART 0x00ac -#define VIP_DVRESTART 0x00b0 -#define VIP_SYNC_SIZE 0x00b4 -#define VIP_TV_PLL_FINE_CNTL 0x00b8 -#define VIP_CRT_PLL_FINE_CNTL 0x00bc -#define VIP_TV_PLL_CNTL 0x00c0 -#define VIP_CRT_PLL_CNTL 0x00c4 -#define VIP_PLL_CNTL0 0x00c8 -#define VIP_PLL_TEST_CNTL 0x00cc -#define VIP_CLOCK_SEL_CNTL 0x00d0 -#define VIP_VIN_PLL_CNTL 0x00d4 -#define VIP_VIN_PLL_FINE_CNTL 0x00d8 -#define VIP_AUD_PLL_CNTL 0x00e0 -#define VIP_AUD_PLL_FINE_CNTL 0x00e4 -#define VIP_AUD_CLK_DIVIDERS 0x00e8 -#define VIP_AUD_DTO_INCREMENTS 0x00ec -#define VIP_L54_PLL_CNTL 0x00f0 -#define VIP_L54_PLL_FINE_CNTL 0x00f4 -#define VIP_L54_DTO_INCREMENTS 0x00f8 -#define VIP_PLL_CNTL1 0x00fc -#define VIP_FRAME_LOCK_CNTL 0x0100 -#define VIP_SYNC_LOCK_CNTL 0x0104 -#define VIP_TVO_SYNC_PAT_ACCUM 0x0108 -#define VIP_TVO_SYNC_THRESHOLD 0x010c -#define VIP_TVO_SYNC_PAT_EXPECT 0x0110 -#define VIP_DELAY_ONE_MAP_A 0x0114 -#define VIP_DELAY_ONE_MAP_B 0x0118 -#define VIP_DELAY_ZERO_MAP_A 0x011c -#define VIP_DELAY_ZERO_MAP_B 0x0120 -#define VIP_TVO_DATA_DELAY_A 0x0140 -#define VIP_TVO_DATA_DELAY_B 0x0144 -#define VIP_HOST_READ_DATA 0x0180 -#define VIP_HOST_WRITE_DATA 0x0184 -#define VIP_HOST_RD_WT_CNTL 0x0188 -#define VIP_VSCALER_CNTL1 0x01c0 -#define VIP_TIMING_CNTL 0x01c4 -#define VIP_VSCALER_CNTL2 0x01c8 -#define VIP_Y_FALL_CNTL 0x01cc -#define VIP_Y_RISE_CNTL 0x01d0 -#define VIP_Y_SAW_TOOTH_CNTL 0x01d4 -#define VIP_UPSAMP_AND_GAIN_CNTL 0x01e0 -#define VIP_GAIN_LIMIT_SETTINGS 0x01e4 -#define VIP_LINEAR_GAIN_SETTINGS 0x01e8 -#define VIP_MODULATOR_CNTL1 0x0200 -#define VIP_MODULATOR_CNTL2 0x0204 -#define VIP_MV_MODE_CNTL 0x0208 -#define VIP_MV_STRIPE_CNTL 0x020c -#define VIP_MV_LEVEL_CNTL1 0x0210 -#define VIP_MV_LEVEL_CNTL2 0x0214 -#define VIP_PRE_DAC_MUX_CNTL 0x0240 -#define VIP_TV_DAC_CNTL 0x0280 -#define VIP_CRC_CNTL 0x02c0 -#define VIP_VIDEO_PORT_SIG 0x02c4 -#define VIP_VBI_CC_CNTL 0x02c8 -#define VIP_VBI_EDS_CNTL 0x02cc -#define VIP_VBI_20BIT_CNTL 0x02d0 -#define VIP_VBI_DTO_CNTL 0x02d4 -#define VIP_VBI_LEVEL_CNTL 0x02d8 -#define VIP_UV_ADR 0x0300 -#define VIP_MV_STATUS 0x0330 -#define VIP_UPSAMP_COEFF0_0 0x0340 -#define VIP_UPSAMP_COEFF0_1 0x0344 -#define VIP_UPSAMP_COEFF0_2 0x0348 -#define VIP_UPSAMP_COEFF1_0 0x034c -#define VIP_UPSAMP_COEFF1_1 0x0350 -#define VIP_UPSAMP_COEFF1_2 0x0354 -#define VIP_UPSAMP_COEFF2_0 0x0358 -#define VIP_UPSAMP_COEFF2_1 0x035c -#define VIP_UPSAMP_COEFF2_2 0x0360 -#define VIP_UPSAMP_COEFF3_0 0x0364 -#define VIP_UPSAMP_COEFF3_1 0x0368 -#define VIP_UPSAMP_COEFF3_2 0x036c -#define VIP_UPSAMP_COEFF4_0 0x0370 -#define VIP_UPSAMP_COEFF4_1 0x0374 -#define VIP_UPSAMP_COEFF4_2 0x0378 -#define VIP_TV_DTO_INCREMENTS 0x0390 -#define VIP_CRT_DTO_INCREMENTS 0x0394 -#define VIP_VSYNC_DIFF_CNTL 0x03a0 -#define VIP_VSYNC_DIFF_LIMITS 0x03a4 -#define VIP_VSYNC_DIFF_RD_DATA 0x03a8 -#define VIP_SCALER_IN_WINDOW 0x0618 -#define VIP_SCALER_OUT_WINDOW 0x061c -#define VIP_H_SCALER_CONTROL 0x0600 -#define VIP_V_SCALER_CONTROL 0x0604 -#define VIP_V_DEINTERLACE_CONTROL 0x0608 -#define VIP_VBI_SCALER_CONTROL 0x060c -#define VIP_DVS_PORT_CTRL 0x0610 -#define VIP_DVS_PORT_READBACK 0x0614 -#define VIP_FIFOA_CONFIG 0x0800 -#define VIP_FIFOB_CONFIG 0x0804 -#define VIP_FIFOC_CONFIG 0x0808 -#define VIP_SPDIF_PORT_CNTL 0x080c -#define VIP_SPDIF_CHANNEL_STAT 0x0810 -#define VIP_SPDIF_AC3_PREAMBLE 0x0814 -#define VIP_I2S_TRANSMIT_CNTL 0x0818 -#define VIP_I2S_RECEIVE_CNTL 0x081c -#define VIP_SPDIF_TX_CNT_REG 0x0820 -#define VIP_IIS_TX_CNT_REG 0x0824 - -/* Status defines */ -#define VIP_BUSY 0 -#define VIP_IDLE 1 -#define VIP_RESET 2 - -#define VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010 -#define VIPH_TIMEOUT_STAT__VIPH_REG_AK 0x00000010 -#define VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000 -#define TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN 0x00000001 - -#define RT_ATI_ID 0x4D541002 - -/* Register/Field values: */ -#define RT_COMP0 0x0 -#define RT_COMP1 0x1 -#define RT_COMP2 0x2 -#define RT_YF_COMP3 0x3 -#define RT_YR_COMP3 0x4 -#define RT_YCF_COMP4 0x5 -#define RT_YCR_COMP4 0x6 - -/* Video standard defines */ -#define RT_NTSC 0x0 -#define RT_PAL 0x1 -#define RT_SECAM 0x2 -#define extNONE 0x0000 -#define extNTSC 0x0100 -#define extRsvd 0x0200 -#define extPAL 0x0300 -#define extPAL_M 0x0400 -#define extPAL_N 0x0500 -#define extSECAM 0x0600 -#define extPAL_NCOMB 0x0700 -#define extNTSC_J 0x0800 -#define extNTSC_443 0x0900 -#define extPAL_BGHI 0x0A00 -#define extPAL_60 0x0B00 - /* these are used in MSP3430 */ -#define extPAL_DK1 0x0C00 -#define extPAL_AUTO 0x0D00 - -#define RT_FREF_2700 6 -#define RT_FREF_2950 5 - -#define RT_COMPOSITE 0x0 -#define RT_SVIDEO 0x1 - -#define RT_NORM_SHARPNESS 0x03 -#define RT_HIGH_SHARPNESS 0x0F - -#define RT_HUE_PAL_DEF 0x00 - -#define RT_DECINTERLACED 0x1 -#define RT_DECNONINTERLACED 0x0 - -#define NTSC_LINES 525 -#define PAL_SECAM_LINES 625 - -#define RT_ASYNC_ENABLE 0x0 -#define RT_ASYNC_DISABLE 0x1 -#define RT_ASYNC_RESET 0x1 - -#define RT_VINRST_ACTIVE 0x0 -#define RT_VINRST_RESET 0x1 -#define RT_L54RST_RESET 0x1 - -#define RT_REF_CLK 0x0 -#define RT_PLL_VIN_CLK 0x1 - -#define RT_VIN_ASYNC_RST 0x20 -#define RT_DVS_ASYNC_RST 0x80 - -#define RT_ADC_ENABLE 0x0 -#define RT_ADC_DISABLE 0x1 - -#define RT_DVSDIR_IN 0x0 -#define RT_DVSDIR_OUT 0x1 - -#define RT_DVSCLK_HIGH 0x0 -#define RT_DVSCLK_LOW 0x1 - -#define RT_DVSCLK_SEL_8FS 0x0 -#define RT_DVSCLK_SEL_27MHZ 0x1 - -#define RT_DVS_CONTSTREAM 0x1 -#define RT_DVS_NONCONTSTREAM 0x0 - -#define RT_DVSDAT_HIGH 0x0 -#define RT_DVSDAT_LOW 0x1 - -#define RT_ADC_CNTL_DEFAULT 0x03252338 - -/* COMB_CNTL0 FILTER SETTINGS FOR DIFFERENT STANDARDS: */ -#define RT_NTSCM_COMB_CNTL0_COMPOSITE 0x09438090 -#define RT_NTSCM_COMB_CNTL0_SVIDEO 0x48540000 - -#define RT_PAL_COMB_CNTL0_COMPOSITE 0x09438090 -#define RT_PAL_COMB_CNTL0_SVIDEO 0x40348090 - -#define RT_SECAM_COMB_CNTL0_COMPOSITE 0xD0108090 /* instead of orig 0xD0088090 - eric*/ -#define RT_SECAM_COMB_CNTL0_SVIDEO 0x50148090 - -#define RT_PALN_COMB_CNTL0_COMPOSITE 0x09438090 -#define RT_PALN_COMB_CNTL0_SVIDEO 0x40348090 - -#define RT_PALM_COMB_CNTL0_COMPOSITE 0x09438090 -#define RT_PALM_COMB_CNTL0_SVIDEO 0x40348090 -/* End of filter settings. */ - -/* COMB_CNTL1 FILTER SETTINGS FOR DIFFERENT STANDARDS: */ -#define RT_NTSCM_COMB_CNTL1_COMPOSITE 0x00000010 -#define RT_NTSCM_COMB_CNTL1_SVIDEO 0x00000081 - -#define RT_PAL_COMB_CNTL1_COMPOSITE 0x00000010 -#define RT_PAL_COMB_CNTL1_SVIDEO 0x000000A1 - -#define RT_SECAM_COMB_CNTL1_COMPOSITE 0x00000091 -#define RT_SECAM_COMB_CNTL1_SVIDEO 0x00000081 - -#define RT_PALN_COMB_CNTL1_COMPOSITE 0x00000010 -#define RT_PALN_COMB_CNTL1_SVIDEO 0x000000A1 - -#define RT_PALM_COMB_CNTL1_COMPOSITE 0x00000010 -#define RT_PALM_COMB_CNTL1_SVIDEO 0x000000A1 -/* End of filter settings. */ - -/* COMB_CNTL2 FILTER SETTINGS FOR DIFFERENT STANDARDS: */ -#define RT_NTSCM_COMB_CNTL2_COMPOSITE 0x16161010 -#define RT_NTSCM_COMB_CNTL2_SVIDEO 0xFFFFFFFF - -#define RT_PAL_COMB_CNTL2_COMPOSITE 0x06080102 /* instead of 0x16161010 - Ivo */ -#define RT_PAL_COMB_CNTL2_SVIDEO 0x06080102 - -#define RT_SECAM_COMB_CNTL2_COMPOSITE 0xffffffff /* instead of 0x06080102 - eric */ -#define RT_SECAM_COMB_CNTL2_SVIDEO 0x06080102 - -#define RT_PALN_COMB_CNTL2_COMPOSITE 0x06080102 -#define RT_PALN_COMB_CNTL2_SVIDEO 0x06080102 - -#define RT_PALM_COMB_CNTL2_COMPOSITE 0x06080102 -#define RT_PALM_COMB_CNTL2_SVIDEO 0x06080102 -/* End of filter settings. */ - -/* COMB_LINE_LENGTH FILTER SETTINGS FOR DIFFERENT STANDARDS: */ -#define RT_NTSCM_COMB_LENGTH_COMPOSITE 0x0718038A -#define RT_NTSCM_COMB_LENGTH_SVIDEO 0x0718038A - -#define RT_PAL_COMB_LENGTH_COMPOSITE 0x08DA046B -#define RT_PAL_COMB_LENGTH_SVIDEO 0x08DA046B - -#define RT_SECAM_COMB_LENGTH_COMPOSITE 0x08DA046A -#define RT_SECAM_COMB_LENGTH_SVIDEO 0x08DA046A - -#define RT_PALN_COMB_LENGTH_COMPOSITE 0x07260391 -#define RT_PALN_COMB_LENGTH_SVIDEO 0x07260391 - -#define RT_PALM_COMB_LENGTH_COMPOSITE 0x07160389 -#define RT_PALM_COMB_LENGTH_SVIDEO 0x07160389 -/* End of filter settings. */ - -/* LP_AGC_CLAMP_CNTL0 */ -#define RT_NTSCM_SYNCTIP_REF0 0x00000037 -#define RT_NTSCM_SYNCTIP_REF1 0x00000029 -#define RT_NTSCM_CLAMP_REF 0x0000003B -#define RT_NTSCM_PEAKWHITE 0x000000FF -#define RT_NTSCM_VBI_PEAKWHITE 0x000000C2 - -#define RT_NTSCM_WPA_THRESHOLD 0x00000406 -#define RT_NTSCM_WPA_TRIGGER_LO 0x000000B3 - -#define RT_NTSCM_WPA_TRIGGER_HIGH 0x0000021B - -#define RT_NTSCM_LP_LOCKOUT_START 0x00000206 -#define RT_NTSCM_LP_LOCKOUT_END 0x00000021 -#define RT_NTSCM_CH_DTO_INC 0x00400000 -#define RT_NTSCM_CH_PLL_SGAIN 0x00000001 -#define RT_NTSCM_CH_PLL_FGAIN 0x00000002 - -#define RT_NTSCM_CR_BURST_GAIN 0x0000007A -#define RT_NTSCM_CB_BURST_GAIN 0x000000AC - -#define RT_NTSCM_CH_HEIGHT 0x000000CD -#define RT_NTSCM_CH_KILL_LEVEL 0x000000C0 -#define RT_NTSCM_CH_AGC_ERROR_LIM 0x00000002 -#define RT_NTSCM_CH_AGC_FILTER_EN 0x00000000 -#define RT_NTSCM_CH_AGC_LOOP_SPEED 0x00000000 - -#define RT_NTSCM_CRDR_ACTIVE_GAIN 0x0000007A -#define RT_NTSCM_CBDB_ACTIVE_GAIN 0x000000AC - -#define RT_NTSCM_VERT_LOCKOUT_START 0x00000207 -#define RT_NTSCM_VERT_LOCKOUT_END 0x0000000E - -#define RT_NTSCJ_SYNCTIP_REF0 0x00000004 -#define RT_NTSCJ_SYNCTIP_REF1 0x00000012 -#define RT_NTSCJ_CLAMP_REF 0x0000003B -#define RT_NTSCJ_PEAKWHITE 0x000000CB -#define RT_NTSCJ_VBI_PEAKWHITE 0x000000C2 -#define RT_NTSCJ_WPA_THRESHOLD 0x000004B0 -#define RT_NTSCJ_WPA_TRIGGER_LO 0x000000B4 -#define RT_NTSCJ_WPA_TRIGGER_HIGH 0x0000021C -#define RT_NTSCJ_LP_LOCKOUT_START 0x00000206 -#define RT_NTSCJ_LP_LOCKOUT_END 0x00000021 - -#define RT_NTSCJ_CR_BURST_GAIN 0x00000071 -#define RT_NTSCJ_CB_BURST_GAIN 0x0000009F -#define RT_NTSCJ_CH_HEIGHT 0x000000CD -#define RT_NTSCJ_CH_KILL_LEVEL 0x000000C0 -#define RT_NTSCJ_CH_AGC_ERROR_LIM 0x00000002 -#define RT_NTSCJ_CH_AGC_FILTER_EN 0x00000000 -#define RT_NTSCJ_CH_AGC_LOOP_SPEED 0x00000000 - -#define RT_NTSCJ_CRDR_ACTIVE_GAIN 0x00000071 -#define RT_NTSCJ_CBDB_ACTIVE_GAIN 0x0000009F -#define RT_NTSCJ_VERT_LOCKOUT_START 0x00000207 -#define RT_NTSCJ_VERT_LOCKOUT_END 0x0000000E - -#define RT_PAL_SYNCTIP_REF0 0x37 /* instead of 0x00000004 - Ivo */ -#define RT_PAL_SYNCTIP_REF1 0x26 /* instead of 0x0000000F - Ivo */ -#define RT_PAL_CLAMP_REF 0x0000003B -#define RT_PAL_PEAKWHITE 0xFF /* instead of 0x000000C1 - Ivo */ -#define RT_PAL_VBI_PEAKWHITE 0xC6 /* instead of 0x000000C7 - Ivo */ -#define RT_PAL_WPA_THRESHOLD 0x59C /* instead of 0x000006A4 - Ivo */ - -#define RT_PAL_WPA_TRIGGER_LO 0x00000096 -#define RT_PAL_WPA_TRIGGER_HIGH 0x000001C2 -#define RT_PAL_LP_LOCKOUT_START 0x00000263 -#define RT_PAL_LP_LOCKOUT_END 0x0000002C - -#define RT_PAL_CH_DTO_INC 0x00400000 -#define RT_PAL_CH_PLL_SGAIN 1 /* instead of 0x00000002 - Ivo */ -#define RT_PAL_CH_PLL_FGAIN 2 /* instead of 0x00000001 - Ivo */ -#define RT_PAL_CR_BURST_GAIN 0x0000007A -#define RT_PAL_CB_BURST_GAIN 0x000000AB -#define RT_PAL_CH_HEIGHT 0x0000009C -#define RT_PAL_CH_KILL_LEVEL 4 /* instead of 0x00000090 - Ivo */ -#define RT_PAL_CH_AGC_ERROR_LIM 1 /* instead of 0x00000002 - Ivo */ -#define RT_PAL_CH_AGC_FILTER_EN 1 /* instead of 0x00000000 - Ivo */ -#define RT_PAL_CH_AGC_LOOP_SPEED 0x00000000 - -#define RT_PAL_CRDR_ACTIVE_GAIN 0x9E /* instead of 0x0000007A - Ivo */ -#define RT_PAL_CBDB_ACTIVE_GAIN 0xDF /* instead of 0x000000AB - Ivo */ -#define RT_PAL_VERT_LOCKOUT_START 0x00000269 -#define RT_PAL_VERT_LOCKOUT_END 0x00000012 - -#define RT_SECAM_SYNCTIP_REF0 0x37 /* instead of 0x00000004 - Ivo */ -#define RT_SECAM_SYNCTIP_REF1 0x26 /* instead of 0x0000000F - Ivo */ -#define RT_SECAM_CLAMP_REF 0x0000003B -#define RT_SECAM_PEAKWHITE 0xFF /* instead of 0x000000C1 - Ivo */ -#define RT_SECAM_VBI_PEAKWHITE 0xC6 /* instead of 0x000000C7 - Ivo */ -#define RT_SECAM_WPA_THRESHOLD 0x57A /* instead of 0x6A4, instead of 0x0000059C is Ivo's value , -eric*/ - -#define RT_SECAM_WPA_TRIGGER_LO 0x96 /* instead of 0x0000026B - eric */ -#define RT_SECAM_WPA_TRIGGER_HIGH 0x000001C2 -#define RT_SECAM_LP_LOCKOUT_START 0x263 /* instead of 0x0000026B - eric */ -#define RT_SECAM_LP_LOCKOUT_END 0x2b /* instead of 0x0000002C -eric */ - -#define RT_SECAM_CH_DTO_INC 0x003E7A28 -#define RT_SECAM_CH_PLL_SGAIN 0x4 /* instead of 0x00000006 -Volodya */ -#define RT_SECAM_CH_PLL_FGAIN 0x7 /* instead of 0x00000006 -Volodya */ - -#define RT_SECAM_CR_BURST_GAIN 0x1FF /* instead of 0x00000200 -Volodya */ -#define RT_SECAM_CB_BURST_GAIN 0x1FF /* instead of 0x00000200 -Volodya */ -#define RT_SECAM_CH_HEIGHT 0x00000066 -#define RT_SECAM_CH_KILL_LEVEL 0x00000060 -#define RT_SECAM_CH_AGC_ERROR_LIM 0x00000003 -#define RT_SECAM_CH_AGC_FILTER_EN 0x00000000 -#define RT_SECAM_CH_AGC_LOOP_SPEED 0x00000000 - -#define RT_SECAM_CRDR_ACTIVE_GAIN 0x11B /* instead of 0x00000200 - eric */ -#define RT_SECAM_CBDB_ACTIVE_GAIN 0x15A /* instead of 0x00000200 - eric */ -#define RT_SECAM_VERT_LOCKOUT_START 0x00000269 -#define RT_SECAM_VERT_LOCKOUT_END 0x00000012 - -#define RT_PAL_VS_FIELD_BLANK_END 0x2A /* instead of 0x0000002C - Ivo*/ -#define RT_NTSCM_VS_FIELD_BLANK_END 0x0000000A - -#define RT_NTSCM_FIELD_IDLOCATION 0x00000105 -#define RT_PAL_FIELD_IDLOCATION 0x00000137 - -#define RT_NTSCM_H_ACTIVE_START 0x00000070 -#define RT_NTSCM_H_ACTIVE_END 0x00000363 - -#define RT_PAL_H_ACTIVE_START 0x0000009A -#define RT_PAL_H_ACTIVE_END 0x00000439 - -#define RT_NTSCM_V_ACTIVE_START ((22-4)*2+1) -#define RT_NTSCM_V_ACTIVE_END ((22+240-4)*2+1) - -#define RT_PAL_V_ACTIVE_START 0x2E /* instead of 0x00000023 (Same as SECAM) - Ivo */ -#define RT_PAL_V_ACTIVE_END 0x269 /* instead of 0x00000262 - Ivo */ - -/* VBI */ -#define RT_NTSCM_H_VBI_WIND_START 0x00000049 -#define RT_NTSCM_H_VBI_WIND_END 0x00000366 - -#define RT_PAL_H_VBI_WIND_START 0x00000084 -#define RT_PAL_H_VBI_WIND_END 0x0000041F - -#define RT_NTSCM_V_VBI_WIND_START fld_V_VBI_WIND_START_def -#define RT_NTSCM_V_VBI_WIND_END fld_V_VBI_WIND_END_def - -#define RT_PAL_V_VBI_WIND_START 0x8 /* instead of 0x0000000B - Ivo */ -#define RT_PAL_V_VBI_WIND_END 0x2D /* instead of 0x00000022 - Ivo */ - -#define RT_VBI_CAPTURE_EN 0x00000001 /* Enable */ -#define RT_VBI_CAPTURE_DIS 0x00000000 /* Disable */ -#define RT_RAW_CAPTURE 0x00000002 /* Use raw Video Capture. */ - -#define RT_NTSCM_VSYNC_INT_TRIGGER 0x2AA -#define RT_PALSEM_VSYNC_INT_TRIGGER 0x353 - -#define RT_NTSCM_VSYNC_INT_HOLD 0x17 -#define RT_PALSEM_VSYNC_INT_HOLD 0x1C - -#define RT_NTSCM_VS_FIELD_BLANK_START 0x206 -#define RT_PALSEM_VS_FIELD_BLANK_START 0x26D /* instead of 0x26C - Ivo */ - -#define RT_FIELD_FLIP_EN 0x4 -#define RT_V_FIELD_FLIP_INVERTED 0x2000 - -#define RT_NTSCM_H_IN_START 0x70 -#define RT_PAL_H_IN_START 154 /* instead of 144 - Ivo */ -#define RT_SECAM_H_IN_START 0x91 /* instead of 0x9A, Ivo value is 154, instead of 144 - Volodya, - eric */ -#define RT_NTSC_H_ACTIVE_SIZE 744 -#define RT_PAL_H_ACTIVE_SIZE 928 /* instead of 927 - Ivo */ -#define RT_SECAM_H_ACTIVE_SIZE 932 /* instead of 928, instead of 927 - Ivo, - eric */ -#define RT_NTSCM_V_IN_START (0x23) -#define RT_PAL_V_IN_START 44 /* instead of (45-6) - Ivo */ -#define RT_SECAM_V_IN_START 0x2C /* instead of (45-6) - Volodya */ -#define RT_NTSCM_V_ACTIVE_SIZE 480 -#define RT_PAL_V_ACTIVE_SIZE 572 /* instead of 575 - Ivo */ -#define RT_SECAM_V_ACTIVE_SIZE 570 /* instead of 572, instead of 575 - Ivo, - eric */ - -#define RT_NTSCM_WIN_CLOSE_LIMIT 0x4D -#define RT_NTSCJ_WIN_CLOSE_LIMIT 0x4D -#define RT_NTSC443_WIN_CLOSE_LIMIT 0x5F -#define RT_PALM_WIN_CLOSE_LIMIT 0x4D -#define RT_PALN_WIN_CLOSE_LIMIT 0x5F -#define RT_SECAM_WIN_CLOSE_LIMIT 0xC7 /* instead of 0x5F - eric */ - -#define RT_NTSCM_VS_FIELD_BLANK_START 0x206 - -#define RT_NTSCM_HS_PLL_SGAIN 0x5 -#define RT_NTSCM_HS_PLL_FGAIN 0x7 - -#define RT_NTSCM_H_OUT_WIND_WIDTH 0x2F4 -#define RT_NTSCM_V_OUT_WIND_HEIGHT 0xF0 - -#define TV 0x1 -#define LINEIN 0x2 -#define MUTE 0x3 - -#define DEC_COMPOSITE 0 -#define DEC_SVIDEO 1 -#define DEC_TUNER 2 - -#define DEC_NTSC 0 -#define DEC_PAL 1 -#define DEC_SECAM 2 -#define DEC_NTSC_J 8 - -#define DEC_SMOOTH 0 -#define DEC_SHARP 1 - -/* RT Register Field Defaults: */ -#define fld_tmpReg1_def 0x00000000 -#define fld_tmpReg2_def 0x00000001 -#define fld_tmpReg3_def 0x00000002 - -#define fld_LP_CONTRAST_def 0x0000006e -#define fld_LP_BRIGHTNESS_def 0x00003ff0 -#define fld_CP_HUE_CNTL_def 0x00000000 -#define fld_LUMA_FILTER_def 0x00000001 -#define fld_H_SCALE_RATIO_def 0x00010000 -#define fld_H_SHARPNESS_def 0x00000000 - -#define fld_V_SCALE_RATIO_def 0x00000800 -#define fld_V_DEINTERLACE_ON_def 0x00000001 -#define fld_V_BYPSS_def 0x00000000 -#define fld_V_DITHER_ON_def 0x00000001 -#define fld_EVENF_OFFSET_def 0x00000000 -#define fld_ODDF_OFFSET_def 0x00000000 - -#define fld_INTERLACE_DETECTED_def 0x00000000 - -#define fld_VS_LINE_COUNT_def 0x00000000 -#define fld_VS_DETECTED_LINES_def 0x00000000 -#define fld_VS_ITU656_VB_def 0x00000000 - -#define fld_VBI_CC_DATA_def 0x00000000 -#define fld_VBI_CC_WT_def 0x00000000 -#define fld_VBI_CC_WT_ACK_def 0x00000000 -#define fld_VBI_CC_HOLD_def 0x00000000 -#define fld_VBI_DECODE_EN_def 0x00000000 - -#define fld_VBI_CC_DTO_P_def 0x00001802 -#define fld_VBI_20BIT_DTO_P_def 0x0000155c - -#define fld_VBI_CC_LEVEL_def 0x0000003f -#define fld_VBI_20BIT_LEVEL_def 0x00000059 -#define fld_VBI_CLK_RUNIN_GAIN_def 0x0000010f - -#define fld_H_VBI_WIND_START_def 0x00000041 -#define fld_H_VBI_WIND_END_def 0x00000366 - -#define fld_V_VBI_WIND_START_def 0x0D -#define fld_V_VBI_WIND_END_def 0x24 - -#define fld_VBI_20BIT_DATA0_def 0x00000000 -#define fld_VBI_20BIT_DATA1_def 0x00000000 -#define fld_VBI_20BIT_WT_def 0x00000000 -#define fld_VBI_20BIT_WT_ACK_def 0x00000000 -#define fld_VBI_20BIT_HOLD_def 0x00000000 - -#define fld_VBI_CAPTURE_ENABLE_def 0x00000000 - -#define fld_VBI_EDS_DATA_def 0x00000000 -#define fld_VBI_EDS_WT_def 0x00000000 -#define fld_VBI_EDS_WT_ACK_def 0x00000000 -#define fld_VBI_EDS_HOLD_def 0x00000000 - -#define fld_VBI_SCALING_RATIO_def 0x00010000 -#define fld_VBI_ALIGNER_ENABLE_def 0x00000000 - -#define fld_H_ACTIVE_START_def 0x00000070 -#define fld_H_ACTIVE_END_def 0x000002f0 - -#define fld_V_ACTIVE_START_def ((22-4)*2+1) -#define fld_V_ACTIVE_END_def ((22+240-4)*2+2) - -#define fld_CH_HEIGHT_def 0x000000CD -#define fld_CH_KILL_LEVEL_def 0x000000C0 -#define fld_CH_AGC_ERROR_LIM_def 0x00000002 -#define fld_CH_AGC_FILTER_EN_def 0x00000000 -#define fld_CH_AGC_LOOP_SPEED_def 0x00000000 - -#define fld_HUE_ADJ_def 0x00000000 - -#define fld_STANDARD_SEL_def 0x00000000 -#define fld_STANDARD_YC_def 0x00000000 - -#define fld_ADC_PDWN_def 0x00000001 -#define fld_INPUT_SELECT_def 0x00000000 - -#define fld_ADC_PREFLO_def 0x00000003 -#define fld_H_SYNC_PULSE_WIDTH_def 0x00000000 -#define fld_HS_GENLOCKED_def 0x00000000 -#define fld_HS_SYNC_IN_WIN_def 0x00000000 - -#define fld_VIN_ASYNC_RST_def 0x00000001 -#define fld_DVS_ASYNC_RST_def 0x00000001 - -/* Vendor IDs: */ -#define fld_VIP_VENDOR_ID_def 0x00001002 -#define fld_VIP_DEVICE_ID_def 0x00004d54 -#define fld_VIP_REVISION_ID_def 0x00000001 - -/* AGC Delay Register */ -#define fld_BLACK_INT_START_def 0x00000031 -#define fld_BLACK_INT_LENGTH_def 0x0000000f - -#define fld_UV_INT_START_def 0x0000003b -#define fld_U_INT_LENGTH_def 0x0000000f -#define fld_V_INT_LENGTH_def 0x0000000f -#define fld_CRDR_ACTIVE_GAIN_def 0x0000007a -#define fld_CBDB_ACTIVE_GAIN_def 0x000000ac - -#define fld_DVS_DIRECTION_def 0x00000000 -#define fld_DVS_VBI_CARD8_SWAP_def 0x00000000 -#define fld_DVS_CLK_SELECT_def 0x00000000 -#define fld_CONTINUOUS_STREAM_def 0x00000000 -#define fld_DVSOUT_CLK_DRV_def 0x00000001 -#define fld_DVSOUT_DATA_DRV_def 0x00000001 - -#define fld_COMB_CNTL0_def 0x09438090 -#define fld_COMB_CNTL1_def 0x00000010 - -#define fld_COMB_CNTL2_def 0x16161010 -#define fld_COMB_LENGTH_def 0x0718038A - -#define fld_SYNCTIP_REF0_def 0x00000037 -#define fld_SYNCTIP_REF1_def 0x00000029 -#define fld_CLAMP_REF_def 0x0000003B -#define fld_AGC_PEAKWHITE_def 0x000000FF -#define fld_VBI_PEAKWHITE_def 0x000000D2 - -#define fld_WPA_THRESHOLD_def 0x000003B0 - -#define fld_WPA_TRIGGER_LO_def 0x000000B4 -#define fld_WPA_TRIGGER_HIGH_def 0x0000021C - -#define fld_LOCKOUT_START_def 0x00000206 -#define fld_LOCKOUT_END_def 0x00000021 - -#define fld_CH_DTO_INC_def 0x00400000 -#define fld_PLL_SGAIN_def 0x00000001 -#define fld_PLL_FGAIN_def 0x00000002 - -#define fld_CR_BURST_GAIN_def 0x0000007a -#define fld_CB_BURST_GAIN_def 0x000000ac - -#define fld_VERT_LOCKOUT_START_def 0x00000207 -#define fld_VERT_LOCKOUT_END_def 0x0000000E - -#define fld_H_IN_WIND_START_def 0x00000070 -#define fld_V_IN_WIND_START_def 0x00000027 - -#define fld_H_OUT_WIND_WIDTH_def 0x000002f4 - -#define fld_V_OUT_WIND_WIDTH_def 0x000000f0 - -#define fld_HS_LINE_TOTAL_def 0x0000038E - -#define fld_MIN_PULSE_WIDTH_def 0x0000002F -#define fld_MAX_PULSE_WIDTH_def 0x00000046 - -#define fld_WIN_CLOSE_LIMIT_def 0x0000004D -#define fld_WIN_OPEN_LIMIT_def 0x000001B7 - -#define fld_VSYNC_INT_TRIGGER_def 0x000002AA - -#define fld_VSYNC_INT_HOLD_def 0x0000001D - -#define fld_VIN_M0_def 0x00000039 -#define fld_VIN_N0_def 0x0000014c -#define fld_MNFLIP_EN_def 0x00000000 -#define fld_VIN_P_def 0x00000006 -#define fld_REG_CLK_SEL_def 0x00000000 - -#define fld_VIN_M1_def 0x00000000 -#define fld_VIN_N1_def 0x00000000 -#define fld_VIN_DRIVER_SEL_def 0x00000000 -#define fld_VIN_MNFLIP_REQ_def 0x00000000 -#define fld_VIN_MNFLIP_DONE_def 0x00000000 -#define fld_TV_LOCK_TO_VIN_def 0x00000000 -#define fld_TV_P_FOR_WINCLK_def 0x00000004 - -#define fld_VINRST_def 0x00000001 -#define fld_VIN_CLK_SEL_def 0x00000000 - -#define fld_VS_FIELD_BLANK_START_def 0x00000206 - -#define fld_VS_FIELD_BLANK_END_def 0x0000000A - -/*#define fld_VS_FIELD_IDLOCATION_def 0x00000105 */ -#define fld_VS_FIELD_IDLOCATION_def 0x00000001 -#define fld_VS_FRAME_TOTAL_def 0x00000217 - -#define fld_SYNC_TIP_START_def 0x00000372 -#define fld_SYNC_TIP_LENGTH_def 0x0000000F - -#define fld_GAIN_FORCE_DATA_def 0x00000000 -#define fld_GAIN_FORCE_EN_def 0x00000000 -#define fld_I_CLAMP_SEL_def 0x00000003 -#define fld_I_AGC_SEL_def 0x00000001 -#define fld_EXT_CLAMP_CAP_def 0x00000001 -#define fld_EXT_AGC_CAP_def 0x00000001 -#define fld_DECI_DITHER_EN_def 0x00000001 -#define fld_ADC_PREFHI_def 0x00000000 -#define fld_ADC_CH_GAIN_SEL_def 0x00000001 - -#define fld_HS_PLL_SGAIN_def 0x00000003 - -#define fld_NREn_def 0x00000000 -#define fld_NRGainCntl_def 0x00000000 -#define fld_NRBWTresh_def 0x00000000 -#define fld_NRGCTresh_def 0x00000000 -#define fld_NRCoefDespeclMode_def 0x00000000 - -#define fld_GPIO_5_OE_def 0x00000000 -#define fld_GPIO_6_OE_def 0x00000000 - -#define fld_GPIO_5_OUT_def 0x00000000 -#define fld_GPIO_6_OUT_def 0x00000000 - -/* End of field default values. */ - -#endif /* RADEON_H */
--- a/vidix/drivers/radeon_vid.c Sat Mar 31 23:48:48 2007 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,2101 +0,0 @@ -/* - radeon_vid - VIDIX based video driver for Radeon and Rage128 chips - Copyrights 2002 Nick Kurshev. This file is based on sources from - GATOS (gatos.sf.net) and X11 (www.xfree86.org) - Licence: GPL - - 31.12.2002 added support for fglrx drivers by Marcel Naziri (zwobbl@zwobbl.de) - 6.04.2004 fixes to allow compiling vidix without X11 (broken in original patch) - PPC support by Alex Beregszaszi -*/ - -#include <errno.h> -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include <math.h> -#include <inttypes.h> - -#include "../../config.h" -#include "../../libavutil/common.h" -#include "../../mpbswap.h" -#include "../../libdha/pci_ids.h" -#include "../../libdha/pci_names.h" -#include "../vidix.h" -#include "../fourcc.h" -#include "../../libdha/libdha.h" -#include "radeon.h" - -#ifdef HAVE_X11 -#include <X11/Xlib.h> -#endif - -#ifdef RAGE128 -#define RADEON_MSG "[rage128]" -#define X_ADJUST 0 -#else -#define RADEON_MSG "[radeon]" -#define X_ADJUST (is_shift_required ? 8 : 0) -#ifndef RADEON -#define RADEON -#endif -#endif - -static int __verbose = 0; -#ifdef RADEON -static int is_shift_required = 0; -#endif - -typedef struct bes_registers_s -{ - /* base address of yuv framebuffer */ - uint32_t yuv_base; - uint32_t fourcc; - uint32_t dest_bpp; - /* YUV BES registers */ - uint32_t reg_load_cntl; - uint32_t h_inc; - uint32_t step_by; - uint32_t y_x_start; - uint32_t y_x_end; - uint32_t v_inc; - uint32_t p1_blank_lines_at_top; - uint32_t p23_blank_lines_at_top; - uint32_t vid_buf_pitch0_value; - uint32_t vid_buf_pitch1_value; - uint32_t p1_x_start_end; - uint32_t p2_x_start_end; - uint32_t p3_x_start_end; - uint32_t base_addr; - uint32_t vid_buf_base_adrs_y[VID_PLAY_MAXFRAMES]; - uint32_t vid_buf_base_adrs_u[VID_PLAY_MAXFRAMES]; - uint32_t vid_buf_base_adrs_v[VID_PLAY_MAXFRAMES]; - uint32_t vid_nbufs; - - uint32_t p1_v_accum_init; - uint32_t p1_h_accum_init; - uint32_t p23_v_accum_init; - uint32_t p23_h_accum_init; - uint32_t scale_cntl; - uint32_t exclusive_horz; - uint32_t auto_flip_cntl; - uint32_t filter_cntl; - uint32_t key_cntl; - uint32_t test; - /* Configurable stuff */ - int double_buff; - - int brightness; - int saturation; - - int ckey_on; - uint32_t graphics_key_clr; - uint32_t graphics_key_msk; - uint32_t ckey_cntl; - - int deinterlace_on; - uint32_t deinterlace_pattern; - -} bes_registers_t; - -typedef struct video_registers_s -{ - const char * sname; - uint32_t name; - uint32_t value; -}video_registers_t; - -static bes_registers_t besr; -#ifndef RAGE128 -static int RadeonFamily=100; -#endif -#define DECLARE_VREG(name) { #name, name, 0 } -static video_registers_t vregs[] = -{ - DECLARE_VREG(VIDEOMUX_CNTL), - DECLARE_VREG(VIPPAD_MASK), - DECLARE_VREG(VIPPAD1_A), - DECLARE_VREG(VIPPAD1_EN), - DECLARE_VREG(VIPPAD1_Y), - DECLARE_VREG(OV0_Y_X_START), - DECLARE_VREG(OV0_Y_X_END), - DECLARE_VREG(OV0_PIPELINE_CNTL), - DECLARE_VREG(OV0_EXCLUSIVE_HORZ), - DECLARE_VREG(OV0_EXCLUSIVE_VERT), - DECLARE_VREG(OV0_REG_LOAD_CNTL), - DECLARE_VREG(OV0_SCALE_CNTL), - DECLARE_VREG(OV0_V_INC), - DECLARE_VREG(OV0_P1_V_ACCUM_INIT), - DECLARE_VREG(OV0_P23_V_ACCUM_INIT), - DECLARE_VREG(OV0_P1_BLANK_LINES_AT_TOP), - DECLARE_VREG(OV0_P23_BLANK_LINES_AT_TOP), -#ifdef RADEON - DECLARE_VREG(OV0_BASE_ADDR), -#endif - DECLARE_VREG(OV0_VID_BUF0_BASE_ADRS), - DECLARE_VREG(OV0_VID_BUF1_BASE_ADRS), - DECLARE_VREG(OV0_VID_BUF2_BASE_ADRS), - DECLARE_VREG(OV0_VID_BUF3_BASE_ADRS), - DECLARE_VREG(OV0_VID_BUF4_BASE_ADRS), - DECLARE_VREG(OV0_VID_BUF5_BASE_ADRS), - DECLARE_VREG(OV0_VID_BUF_PITCH0_VALUE), - DECLARE_VREG(OV0_VID_BUF_PITCH1_VALUE), - DECLARE_VREG(OV0_AUTO_FLIP_CNTL), - DECLARE_VREG(OV0_DEINTERLACE_PATTERN), - DECLARE_VREG(OV0_SUBMIT_HISTORY), - DECLARE_VREG(OV0_H_INC), - DECLARE_VREG(OV0_STEP_BY), - DECLARE_VREG(OV0_P1_H_ACCUM_INIT), - DECLARE_VREG(OV0_P23_H_ACCUM_INIT), - DECLARE_VREG(OV0_P1_X_START_END), - DECLARE_VREG(OV0_P2_X_START_END), - DECLARE_VREG(OV0_P3_X_START_END), - DECLARE_VREG(OV0_FILTER_CNTL), - DECLARE_VREG(OV0_FOUR_TAP_COEF_0), - DECLARE_VREG(OV0_FOUR_TAP_COEF_1), - DECLARE_VREG(OV0_FOUR_TAP_COEF_2), - DECLARE_VREG(OV0_FOUR_TAP_COEF_3), - DECLARE_VREG(OV0_FOUR_TAP_COEF_4), - DECLARE_VREG(OV0_FLAG_CNTL), -#ifdef RAGE128 - DECLARE_VREG(OV0_COLOUR_CNTL), -#else - DECLARE_VREG(OV0_SLICE_CNTL), -#endif - DECLARE_VREG(OV0_VID_KEY_CLR), - DECLARE_VREG(OV0_VID_KEY_MSK), - DECLARE_VREG(OV0_GRAPHICS_KEY_CLR), - DECLARE_VREG(OV0_GRAPHICS_KEY_MSK), - DECLARE_VREG(OV0_KEY_CNTL), - DECLARE_VREG(OV0_TEST), - DECLARE_VREG(OV0_LIN_TRANS_A), - DECLARE_VREG(OV0_LIN_TRANS_B), - DECLARE_VREG(OV0_LIN_TRANS_C), - DECLARE_VREG(OV0_LIN_TRANS_D), - DECLARE_VREG(OV0_LIN_TRANS_E), - DECLARE_VREG(OV0_LIN_TRANS_F), - DECLARE_VREG(OV0_GAMMA_0_F), - DECLARE_VREG(OV0_GAMMA_10_1F), - DECLARE_VREG(OV0_GAMMA_20_3F), - DECLARE_VREG(OV0_GAMMA_40_7F), - DECLARE_VREG(OV0_GAMMA_380_3BF), - DECLARE_VREG(OV0_GAMMA_3C0_3FF), - DECLARE_VREG(SUBPIC_CNTL), - DECLARE_VREG(SUBPIC_DEFCOLCON), - DECLARE_VREG(SUBPIC_Y_X_START), - DECLARE_VREG(SUBPIC_Y_X_END), - DECLARE_VREG(SUBPIC_V_INC), - DECLARE_VREG(SUBPIC_H_INC), - DECLARE_VREG(SUBPIC_BUF0_OFFSET), - DECLARE_VREG(SUBPIC_BUF1_OFFSET), - DECLARE_VREG(SUBPIC_LC0_OFFSET), - DECLARE_VREG(SUBPIC_LC1_OFFSET), - DECLARE_VREG(SUBPIC_PITCH), - DECLARE_VREG(SUBPIC_BTN_HLI_COLCON), - DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_START), - DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_END), - DECLARE_VREG(SUBPIC_PALETTE_INDEX), - DECLARE_VREG(SUBPIC_PALETTE_DATA), - DECLARE_VREG(SUBPIC_H_ACCUM_INIT), - DECLARE_VREG(SUBPIC_V_ACCUM_INIT), - DECLARE_VREG(IDCT_RUNS), - DECLARE_VREG(IDCT_LEVELS), - DECLARE_VREG(IDCT_AUTH_CONTROL), - DECLARE_VREG(IDCT_AUTH), - DECLARE_VREG(IDCT_CONTROL), - DECLARE_VREG(CONFIG_CNTL) -}; - -#ifdef HAVE_X11 -static uint32_t firegl_shift = 0; -#endif -static void * radeon_mmio_base = 0; -static void * radeon_mem_base = 0; -static int32_t radeon_overlay_off = 0; -static uint32_t radeon_ram_size = 0; -/* Restore on exit */ -static uint32_t SAVED_OV0_GRAPHICS_KEY_CLR = 0; -static uint32_t SAVED_OV0_GRAPHICS_KEY_MSK = 0; -static uint32_t SAVED_OV0_VID_KEY_CLR = 0; -static uint32_t SAVED_OV0_VID_KEY_MSK = 0; -static uint32_t SAVED_OV0_KEY_CNTL = 0; -#ifdef WORDS_BIGENDIAN -static uint32_t SAVED_CONFIG_CNTL = 0; -#if defined(RAGE128) -#define APER_0_BIG_ENDIAN_16BPP_SWAP (1<<0) -#define APER_0_BIG_ENDIAN_32BPP_SWAP (2<<0) -#else -#define RADEON_SURFACE_CNTL 0x0b00 -#define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20) -#define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21) -#endif -#endif - -#define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ)))) -#define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL - -#define INREG8(addr) GETREG(uint8_t,(uint8_t*)(radeon_mmio_base),addr) -#define OUTREG8(addr,val) SETREG(uint8_t,(uint8_t*)(radeon_mmio_base),addr,val) - -static inline uint32_t INREG (uint32_t addr) { - uint32_t tmp = GETREG(uint32_t,(uint8_t*)(radeon_mmio_base),addr); - return le2me_32(tmp); -} -//#define OUTREG(addr,val) SETREG(uint32_t,(uint8_t*)(radeon_mmio_base),addr,val) -#define OUTREG(addr,val) SETREG(uint32_t,(uint8_t*)(radeon_mmio_base),addr,le2me_32(val)) -#define OUTREGP(addr,val,mask) \ - do { \ - unsigned int _tmp = INREG(addr); \ - _tmp &= (mask); \ - _tmp |= (val); \ - OUTREG(addr, _tmp); \ - } while (0) - -static __inline__ uint32_t INPLL(uint32_t addr) -{ - OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000001f); - return (INREG(CLOCK_CNTL_DATA)); -} - -#define OUTPLL(addr,val) OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000001f) | 0x00000080); \ - OUTREG(CLOCK_CNTL_DATA, val) -#define OUTPLLP(addr,val,mask) \ - do { \ - unsigned int _tmp = INPLL(addr); \ - _tmp &= (mask); \ - _tmp |= (val); \ - OUTPLL(addr, _tmp); \ - } while (0) - -static uint32_t radeon_vid_get_dbpp( void ) -{ - uint32_t dbpp,retval; - dbpp = (INREG(CRTC_GEN_CNTL)>>8)& 0xF; - switch(dbpp) - { - case DST_8BPP: retval = 8; break; - case DST_15BPP: retval = 15; break; - case DST_16BPP: retval = 16; break; - case DST_24BPP: retval = 24; break; - default: retval=32; break; - } - return retval; -} - -static int radeon_is_dbl_scan( void ) -{ - return (INREG(CRTC_GEN_CNTL))&CRTC_DBL_SCAN_EN; -} - -static int radeon_is_interlace( void ) -{ - return (INREG(CRTC_GEN_CNTL))&CRTC_INTERLACE_EN; -} - -static uint32_t radeon_get_xres( void ) -{ - /* FIXME: currently we extract that from CRTC!!!*/ - uint32_t xres,h_total; - h_total = INREG(CRTC_H_TOTAL_DISP); - xres = (h_total >> 16) & 0xffff; - return (xres + 1)*8; -} - -static uint32_t radeon_get_yres( void ) -{ - /* FIXME: currently we extract that from CRTC!!!*/ - uint32_t yres,v_total; - v_total = INREG(CRTC_V_TOTAL_DISP); - yres = (v_total >> 16) & 0xffff; - return yres + 1; -} - -/* get flat panel x resolution*/ -static uint32_t radeon_get_fp_xres( void ){ - uint32_t xres=(INREG(FP_HORZ_STRETCH)&0x00fff000)>>16; - xres=(xres+1)*8; - return xres; -} - -/* get flat panel y resolution*/ -static uint32_t radeon_get_fp_yres( void ){ - uint32_t yres=(INREG(FP_VERT_STRETCH)&0x00fff000)>>12; - return yres+1; -} - -static void radeon_wait_vsync(void) -{ - int i; - - OUTREG(GEN_INT_STATUS, VSYNC_INT_AK); - for (i = 0; i < 2000000; i++) - { - if (INREG(GEN_INT_STATUS) & VSYNC_INT) break; - } -} - -#ifdef RAGE128 -static void _radeon_engine_idle(void); -static void _radeon_fifo_wait(unsigned); -#define radeon_engine_idle() _radeon_engine_idle() -#define radeon_fifo_wait(entries) _radeon_fifo_wait(entries) -/* Flush all dirty data in the Pixel Cache to memory. */ -static __inline__ void radeon_engine_flush ( void ) -{ - unsigned i; - - OUTREGP(PC_NGUI_CTLSTAT, PC_FLUSH_ALL, ~PC_FLUSH_ALL); - for (i = 0; i < 2000000; i++) { - if (!(INREG(PC_NGUI_CTLSTAT) & PC_BUSY)) break; - } -} - -/* Reset graphics card to known state. */ -static void radeon_engine_reset( void ) -{ - uint32_t clock_cntl_index; - uint32_t mclk_cntl; - uint32_t gen_reset_cntl; - - radeon_engine_flush(); - - clock_cntl_index = INREG(CLOCK_CNTL_INDEX); - mclk_cntl = INPLL(MCLK_CNTL); - - OUTPLL(MCLK_CNTL, mclk_cntl | FORCE_GCP | FORCE_PIPE3D_CP); - - gen_reset_cntl = INREG(GEN_RESET_CNTL); - - OUTREG(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI); - INREG(GEN_RESET_CNTL); - OUTREG(GEN_RESET_CNTL, - gen_reset_cntl & (uint32_t)(~SOFT_RESET_GUI)); - INREG(GEN_RESET_CNTL); - - OUTPLL(MCLK_CNTL, mclk_cntl); - OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index); - OUTREG(GEN_RESET_CNTL, gen_reset_cntl); -} -#else - -static __inline__ void radeon_engine_flush ( void ) -{ - int i; - - /* initiate flush */ - OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, - ~RB2D_DC_FLUSH_ALL); - - for (i=0; i < 2000000; i++) { - if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) - break; - } -} - -static void _radeon_engine_idle(void); -static void _radeon_fifo_wait(unsigned); -#define radeon_engine_idle() _radeon_engine_idle() -#define radeon_fifo_wait(entries) _radeon_fifo_wait(entries) - -static void radeon_engine_reset( void ) -{ - uint32_t clock_cntl_index, mclk_cntl, rbbm_soft_reset; - - radeon_engine_flush (); - - clock_cntl_index = INREG(CLOCK_CNTL_INDEX); - mclk_cntl = INPLL(MCLK_CNTL); - - OUTPLL(MCLK_CNTL, (mclk_cntl | - FORCEON_MCLKA | - FORCEON_MCLKB | - FORCEON_YCLKA | - FORCEON_YCLKB | - FORCEON_MC | - FORCEON_AIC)); - rbbm_soft_reset = INREG(RBBM_SOFT_RESET); - - OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset | - SOFT_RESET_CP | - SOFT_RESET_HI | - SOFT_RESET_SE | - SOFT_RESET_RE | - SOFT_RESET_PP | - SOFT_RESET_E2 | - SOFT_RESET_RB | - SOFT_RESET_HDP); - INREG(RBBM_SOFT_RESET); - OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (uint32_t) - ~(SOFT_RESET_CP | - SOFT_RESET_HI | - SOFT_RESET_SE | - SOFT_RESET_RE | - SOFT_RESET_PP | - SOFT_RESET_E2 | - SOFT_RESET_RB | - SOFT_RESET_HDP)); - INREG(RBBM_SOFT_RESET); - - OUTPLL(MCLK_CNTL, mclk_cntl); - OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index); - OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset); - - return; -} -#endif -static void radeon_engine_restore( void ) -{ -#ifndef RAGE128 - int pitch64; - uint32_t xres,yres,bpp; - radeon_fifo_wait(1); - xres = radeon_get_xres(); - yres = radeon_get_yres(); - bpp = radeon_vid_get_dbpp(); - /* turn of all automatic flushing - we'll do it all */ - OUTREG(RB2D_DSTCACHE_MODE, 0); - - pitch64 = ((xres * (bpp / 8) + 0x3f)) >> 6; - - radeon_fifo_wait(1); - OUTREG(DEFAULT_OFFSET, (INREG(DEFAULT_OFFSET) & 0xC0000000) | - (pitch64 << 22)); - - radeon_fifo_wait(1); -#if defined(WORDS_BIGENDIAN) -#ifdef RADEON - OUTREGP(DP_DATATYPE, HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN); -#endif -#else - OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN); -#endif - - radeon_fifo_wait(1); - OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX - | DEFAULT_SC_BOTTOM_MAX)); - radeon_fifo_wait(1); - OUTREG(DP_GUI_MASTER_CNTL, (INREG(DP_GUI_MASTER_CNTL) - | GMC_BRUSH_SOLID_COLOR - | GMC_SRC_DATATYPE_COLOR)); - - radeon_fifo_wait(7); - OUTREG(DST_LINE_START, 0); - OUTREG(DST_LINE_END, 0); - OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff); - OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000); - OUTREG(DP_SRC_FRGD_CLR, 0xffffffff); - OUTREG(DP_SRC_BKGD_CLR, 0x00000000); - OUTREG(DP_WRITE_MASK, 0xffffffff); - - radeon_engine_idle(); -#endif -} -#ifdef RAGE128 -static void _radeon_fifo_wait (unsigned entries) -{ - unsigned i; - - for(;;) - { - for (i=0; i<2000000; i++) - if ((INREG(GUI_STAT) & GUI_FIFOCNT_MASK) >= entries) - return; - radeon_engine_reset(); - radeon_engine_restore(); - } -} - -static void _radeon_engine_idle ( void ) -{ - unsigned i; - - /* ensure FIFO is empty before waiting for idle */ - radeon_fifo_wait (64); - for(;;) - { - for (i=0; i<2000000; i++) { - if ((INREG(GUI_STAT) & GUI_ACTIVE) == 0) { - radeon_engine_flush (); - return; - } - } - radeon_engine_reset(); - radeon_engine_restore(); - } -} -#else -static void _radeon_fifo_wait (unsigned entries) -{ - unsigned i; - - for(;;) - { - for (i=0; i<2000000; i++) - if ((INREG(RBBM_STATUS) & RBBM_FIFOCNT_MASK) >= entries) - return; - radeon_engine_reset(); - radeon_engine_restore(); - } -} -static void _radeon_engine_idle ( void ) -{ - int i; - - /* ensure FIFO is empty before waiting for idle */ - radeon_fifo_wait (64); - for(;;) - { - for (i=0; i<2000000; i++) { - if (((INREG(RBBM_STATUS) & RBBM_ACTIVE)) == 0) { - radeon_engine_flush (); - return; - } - } - radeon_engine_reset(); - radeon_engine_restore(); - } -} -#endif - -#ifndef RAGE128 -/* Reference color space transform data */ -typedef struct tagREF_TRANSFORM -{ - float RefLuma; - float RefRCb; - float RefRCr; - float RefGCb; - float RefGCr; - float RefBCb; - float RefBCr; -} REF_TRANSFORM; - -/* Parameters for ITU-R BT.601 and ITU-R BT.709 colour spaces */ -REF_TRANSFORM trans[2] = -{ - {1.1678, 0.0, 1.6007, -0.3929, -0.8154, 2.0232, 0.0}, /* BT.601 */ - {1.1678, 0.0, 1.7980, -0.2139, -0.5345, 2.1186, 0.0} /* BT.709 */ -}; -/**************************************************************************** - * SetTransform * - * Function: Calculates and sets color space transform from supplied * - * reference transform, gamma, brightness, contrast, hue and * - * saturation. * - * Inputs: bright - brightness * - * cont - contrast * - * sat - saturation * - * hue - hue * - * red_intensity - intense of red component * - * green_intensity - intense of green component * - * blue_intensity - intense of blue component * - * ref - index to the table of refernce transforms * - * Outputs: NONE * - ****************************************************************************/ - -static void radeon_set_transform(float bright, float cont, float sat, - float hue, float red_intensity, - float green_intensity,float blue_intensity, - unsigned ref) -{ - float OvHueSin, OvHueCos; - float CAdjLuma, CAdjOff; - float RedAdj,GreenAdj,BlueAdj; - float CAdjRCb, CAdjRCr; - float CAdjGCb, CAdjGCr; - float CAdjBCb, CAdjBCr; - float OvLuma, OvROff, OvGOff, OvBOff; - float OvRCb, OvRCr; - float OvGCb, OvGCr; - float OvBCb, OvBCr; - float Loff = 64.0; - float Coff = 512.0f; - - uint32_t dwOvLuma, dwOvROff, dwOvGOff, dwOvBOff; - uint32_t dwOvRCb, dwOvRCr; - uint32_t dwOvGCb, dwOvGCr; - uint32_t dwOvBCb, dwOvBCr; - - if (ref >= 2) return; - - OvHueSin = sin((double)hue); - OvHueCos = cos((double)hue); - - CAdjLuma = cont * trans[ref].RefLuma; - CAdjOff = cont * trans[ref].RefLuma * bright * 1023.0; - RedAdj = cont * trans[ref].RefLuma * red_intensity * 1023.0; - GreenAdj = cont * trans[ref].RefLuma * green_intensity * 1023.0; - BlueAdj = cont * trans[ref].RefLuma * blue_intensity * 1023.0; - - CAdjRCb = sat * -OvHueSin * trans[ref].RefRCr; - CAdjRCr = sat * OvHueCos * trans[ref].RefRCr; - CAdjGCb = sat * (OvHueCos * trans[ref].RefGCb - OvHueSin * trans[ref].RefGCr); - CAdjGCr = sat * (OvHueSin * trans[ref].RefGCb + OvHueCos * trans[ref].RefGCr); - CAdjBCb = sat * OvHueCos * trans[ref].RefBCb; - CAdjBCr = sat * OvHueSin * trans[ref].RefBCb; - -#if 0 /* default constants */ - CAdjLuma = 1.16455078125; - - CAdjRCb = 0.0; - CAdjRCr = 1.59619140625; - CAdjGCb = -0.39111328125; - CAdjGCr = -0.8125; - CAdjBCb = 2.01708984375; - CAdjBCr = 0; -#endif - OvLuma = CAdjLuma; - OvRCb = CAdjRCb; - OvRCr = CAdjRCr; - OvGCb = CAdjGCb; - OvGCr = CAdjGCr; - OvBCb = CAdjBCb; - OvBCr = CAdjBCr; - OvROff = RedAdj + CAdjOff - - OvLuma * Loff - (OvRCb + OvRCr) * Coff; - OvGOff = GreenAdj + CAdjOff - - OvLuma * Loff - (OvGCb + OvGCr) * Coff; - OvBOff = BlueAdj + CAdjOff - - OvLuma * Loff - (OvBCb + OvBCr) * Coff; -#if 0 /* default constants */ - OvROff = -888.5; - OvGOff = 545; - OvBOff = -1104; -#endif - - dwOvROff = ((int)(OvROff * 2.0)) & 0x1fff; - dwOvGOff = (int)(OvGOff * 2.0) & 0x1fff; - dwOvBOff = (int)(OvBOff * 2.0) & 0x1fff; - /* Whatever docs say about R200 having 3.8 format instead of 3.11 - as in Radeon is a lie */ -#if 0 - if(RadeonFamily == 100) - { -#endif - dwOvLuma =(((int)(OvLuma * 2048.0))&0x7fff)<<17; - dwOvRCb = (((int)(OvRCb * 2048.0))&0x7fff)<<1; - dwOvRCr = (((int)(OvRCr * 2048.0))&0x7fff)<<17; - dwOvGCb = (((int)(OvGCb * 2048.0))&0x7fff)<<1; - dwOvGCr = (((int)(OvGCr * 2048.0))&0x7fff)<<17; - dwOvBCb = (((int)(OvBCb * 2048.0))&0x7fff)<<1; - dwOvBCr = (((int)(OvBCr * 2048.0))&0x7fff)<<17; -#if 0 - } - else - { - dwOvLuma = (((int)(OvLuma * 256.0))&0x7ff)<<20; - dwOvRCb = (((int)(OvRCb * 256.0))&0x7ff)<<4; - dwOvRCr = (((int)(OvRCr * 256.0))&0x7ff)<<20; - dwOvGCb = (((int)(OvGCb * 256.0))&0x7ff)<<4; - dwOvGCr = (((int)(OvGCr * 256.0))&0x7ff)<<20; - dwOvBCb = (((int)(OvBCb * 256.0))&0x7ff)<<4; - dwOvBCr = (((int)(OvBCr * 256.0))&0x7ff)<<20; - } -#endif - OUTREG(OV0_LIN_TRANS_A, dwOvRCb | dwOvLuma); - OUTREG(OV0_LIN_TRANS_B, dwOvROff | dwOvRCr); - OUTREG(OV0_LIN_TRANS_C, dwOvGCb | dwOvLuma); - OUTREG(OV0_LIN_TRANS_D, dwOvGOff | dwOvGCr); - OUTREG(OV0_LIN_TRANS_E, dwOvBCb | dwOvLuma); - OUTREG(OV0_LIN_TRANS_F, dwOvBOff | dwOvBCr); -} - -/* Gamma curve definition */ -typedef struct -{ - unsigned int gammaReg; - unsigned int gammaSlope; - unsigned int gammaOffset; -}GAMMA_SETTINGS; - -/* Recommended gamma curve parameters */ -GAMMA_SETTINGS r200_def_gamma[18] = -{ - {OV0_GAMMA_0_F, 0x100, 0x0000}, - {OV0_GAMMA_10_1F, 0x100, 0x0020}, - {OV0_GAMMA_20_3F, 0x100, 0x0040}, - {OV0_GAMMA_40_7F, 0x100, 0x0080}, - {OV0_GAMMA_80_BF, 0x100, 0x0100}, - {OV0_GAMMA_C0_FF, 0x100, 0x0100}, - {OV0_GAMMA_100_13F, 0x100, 0x0200}, - {OV0_GAMMA_140_17F, 0x100, 0x0200}, - {OV0_GAMMA_180_1BF, 0x100, 0x0300}, - {OV0_GAMMA_1C0_1FF, 0x100, 0x0300}, - {OV0_GAMMA_200_23F, 0x100, 0x0400}, - {OV0_GAMMA_240_27F, 0x100, 0x0400}, - {OV0_GAMMA_280_2BF, 0x100, 0x0500}, - {OV0_GAMMA_2C0_2FF, 0x100, 0x0500}, - {OV0_GAMMA_300_33F, 0x100, 0x0600}, - {OV0_GAMMA_340_37F, 0x100, 0x0600}, - {OV0_GAMMA_380_3BF, 0x100, 0x0700}, - {OV0_GAMMA_3C0_3FF, 0x100, 0x0700} -}; - -GAMMA_SETTINGS r100_def_gamma[6] = -{ - {OV0_GAMMA_0_F, 0x100, 0x0000}, - {OV0_GAMMA_10_1F, 0x100, 0x0020}, - {OV0_GAMMA_20_3F, 0x100, 0x0040}, - {OV0_GAMMA_40_7F, 0x100, 0x0080}, - {OV0_GAMMA_380_3BF, 0x100, 0x0100}, - {OV0_GAMMA_3C0_3FF, 0x100, 0x0100} -}; - -static void make_default_gamma_correction( void ) -{ - size_t i; - if(RadeonFamily == 100) { - OUTREG(OV0_LIN_TRANS_A, 0x12A00000); - OUTREG(OV0_LIN_TRANS_B, 0x199018FE); - OUTREG(OV0_LIN_TRANS_C, 0x12A0F9B0); - OUTREG(OV0_LIN_TRANS_D, 0xF2F0043B); - OUTREG(OV0_LIN_TRANS_E, 0x12A02050); - OUTREG(OV0_LIN_TRANS_F, 0x0000174E); - for(i=0; i<6; i++){ - OUTREG(r100_def_gamma[i].gammaReg, - (r100_def_gamma[i].gammaSlope<<16) | - r100_def_gamma[i].gammaOffset); - } - } - else{ - OUTREG(OV0_LIN_TRANS_A, 0x12a00000); - OUTREG(OV0_LIN_TRANS_B, 0x1990190e); - OUTREG(OV0_LIN_TRANS_C, 0x12a0f9c0); - OUTREG(OV0_LIN_TRANS_D, 0xf3000442); - OUTREG(OV0_LIN_TRANS_E, 0x12a02040); - OUTREG(OV0_LIN_TRANS_F, 0x175f); - - /* Default Gamma, - Of 18 segments for gamma cure, all segments in R200 are programmable, - while only lower 4 and upper 2 segments are programmable in Radeon*/ - for(i=0; i<18; i++){ - OUTREG(r200_def_gamma[i].gammaReg, - (r200_def_gamma[i].gammaSlope<<16) | - r200_def_gamma[i].gammaOffset); - } - } -} -#endif - -static void radeon_vid_make_default(void) -{ -#ifdef RAGE128 - OUTREG(OV0_COLOUR_CNTL,0x00101000UL); /* Default brightness and saturation for Rage128 */ -#else - make_default_gamma_correction(); -#endif - besr.deinterlace_pattern = 0x900AAAAA; - OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); - besr.deinterlace_on=1; - besr.double_buff=1; - besr.ckey_on=0; - besr.graphics_key_msk=0; - besr.graphics_key_clr=0; - besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_TRUE|CMP_MIX_AND; -} - - -unsigned vixGetVersion( void ) { return VIDIX_VERSION; } - -static unsigned short ati_card_ids[] = -{ -#ifdef RAGE128 - /* - This driver should be compatible with Rage128 (pro) chips. - (include adaptive deinterlacing!!!). - Moreover: the same logic can be used with Mach64 chips. - (I mean: mach64xx, 3d rage, 3d rage IIc, 3D rage pro, 3d rage mobility). - but they are incompatible by i/o ports. So if enthusiasts will want - then they can redefine OUTREG and INREG macros and redefine OV0_* - constants. Also it seems that mach64 chips supports only: YUY2, YV12, UYVY - fourccs (422 and 420 formats only). - */ -/* Rage128 Pro GL */ - DEVICE_ATI_RAGE_128_PA_PRO, - DEVICE_ATI_RAGE_128_PB_PRO, - DEVICE_ATI_RAGE_128_PC_PRO, - DEVICE_ATI_RAGE_128_PD_PRO, - DEVICE_ATI_RAGE_128_PE_PRO, - DEVICE_ATI_RAGE_128_PF_PRO, -/* Rage128 Pro VR */ - DEVICE_ATI_RAGE_128_PG_PRO, - DEVICE_ATI_RAGE_128_PH_PRO, - DEVICE_ATI_RAGE_128_PI_PRO, - DEVICE_ATI_RAGE_128_PJ_PRO, - DEVICE_ATI_RAGE_128_PK_PRO, - DEVICE_ATI_RAGE_128_PL_PRO, - DEVICE_ATI_RAGE_128_PM_PRO, - DEVICE_ATI_RAGE_128_PN_PRO, - DEVICE_ATI_RAGE_128_PO_PRO, - DEVICE_ATI_RAGE_128_PP_PRO, - DEVICE_ATI_RAGE_128_PQ_PRO, - DEVICE_ATI_RAGE_128_PR_PRO, - DEVICE_ATI_RAGE_128_PS_PRO, - DEVICE_ATI_RAGE_128_PT_PRO, - DEVICE_ATI_RAGE_128_PU_PRO, - DEVICE_ATI_RAGE_128_PV_PRO, - DEVICE_ATI_RAGE_128_PW_PRO, - DEVICE_ATI_RAGE_128_PX_PRO, -/* Rage128 GL */ - DEVICE_ATI_RAGE_128_RE_SG, - DEVICE_ATI_RAGE_128_RF_SG, - DEVICE_ATI_RAGE_128_RG, - DEVICE_ATI_RAGE_128_RK_VR, - DEVICE_ATI_RAGE_128_RL_VR, - DEVICE_ATI_RAGE_128_SE_4X, - DEVICE_ATI_RAGE_128_SF_4X, - DEVICE_ATI_RAGE_128_SG_4X, - DEVICE_ATI_RAGE_128_SH, - DEVICE_ATI_RAGE_128_SK_4X, - DEVICE_ATI_RAGE_128_SL_4X, - DEVICE_ATI_RAGE_128_SM_4X, - DEVICE_ATI_RAGE_128_4X, - DEVICE_ATI_RAGE_128_PRO, - DEVICE_ATI_RAGE_128_PRO2, - DEVICE_ATI_RAGE_128_PRO3, -/* these seem to be based on rage 128 instead of mach64 */ - DEVICE_ATI_RAGE_MOBILITY_M3, - DEVICE_ATI_RAGE_MOBILITY_M32 -#else -/* Radeons (indeed: Rage 256 Pro ;) */ - DEVICE_ATI_RADEON_R100_QD, - DEVICE_ATI_RADEON_R100_QE, - DEVICE_ATI_RADEON_R100_QF, - DEVICE_ATI_RADEON_R100_QG, - DEVICE_ATI_RADEON_VE_QY, - DEVICE_ATI_RADEON_VE_QZ, - DEVICE_ATI_RADEON_MOBILITY_M7, - DEVICE_ATI_RADEON_MOBILITY_M72, - DEVICE_ATI_RADEON_MOBILITY_M6, - DEVICE_ATI_RADEON_MOBILITY_M62, - DEVICE_ATI_RADEON_MOBILITY_U1, - DEVICE_ATI_RADEON_R200_BB, - DEVICE_ATI_RADEON_R200_QH, - DEVICE_ATI_RADEON_R200_QI, - DEVICE_ATI_RADEON_R200_QJ, - DEVICE_ATI_RADEON_R200_QK, - DEVICE_ATI_RADEON_R200_QL, - DEVICE_ATI_RADEON_R200_QM, - DEVICE_ATI_RADEON_R200_QH2, - DEVICE_ATI_RADEON_R200_QI2, - DEVICE_ATI_RADEON_R200_QJ2, - DEVICE_ATI_RADEON_R200_QK2, - DEVICE_ATI_RADEON_RV200_QW, - DEVICE_ATI_RADEON_RV200_QX, - DEVICE_ATI_RADEON_R250_ID, - DEVICE_ATI_RADEON_R250_IE, - DEVICE_ATI_RADEON_R250_IF, - DEVICE_ATI_RADEON_R250_IG, - DEVICE_ATI_RADEON_R250_LD, - DEVICE_ATI_RADEON_R250_LE, - DEVICE_ATI_RADEON_R250_LF, - DEVICE_ATI_RADEON_R250_LG, - DEVICE_ATI_RV370_5B60_RADEON, - DEVICE_ATI_RV250_5C61_RADEON, - DEVICE_ATI_RV250_5C63_RADEON, - DEVICE_ATI_RV280_RADEON_9200, - DEVICE_ATI_RV280_RADEON_92002, - DEVICE_ATI_RV280_RADEON_92003, - DEVICE_ATI_RV280_RADEON_92004, - DEVICE_ATI_RV280_RADEON_92005, - DEVICE_ATI_RV280_RADEON_92006, - DEVICE_ATI_RADEON_R300_ND, - DEVICE_ATI_RADEON_R300_NE, - DEVICE_ATI_RADEON_R300_NF, - DEVICE_ATI_RADEON_R300_NG, - DEVICE_ATI_RADEON_R300_AE, - DEVICE_ATI_RADEON_R300_AF, - DEVICE_ATI_RADEON_RV350_AP, - DEVICE_ATI_RADEON_RV350_AQ, - DEVICE_ATI_RADEON_RV350_AR, - DEVICE_ATI_RADEON_RV350_BK, - DEVICE_ATI_RADEON_R350_AH, - DEVICE_ATI_RADEON_R350_AI, - DEVICE_ATI_RADEON_R350_NH, - DEVICE_ATI_RADEON_R360_NJ, - DEVICE_ATI_RV350_MOBILITY_RADEON, - DEVICE_ATI_RV350_MOBILITY_RADEON2 -#endif -}; - -static int find_chip(unsigned chip_id) -{ - unsigned i; - for(i = 0;i < sizeof(ati_card_ids)/sizeof(unsigned short);i++) - { - if(chip_id == ati_card_ids[i]) return i; - } - return -1; -} - -static pciinfo_t pci_info; -static int probed=0; - -vidix_capability_t def_cap = -{ -#ifdef RAGE128 - "BES driver for Rage128 cards", -#else - "BES driver for Radeon cards", -#endif - "Nick Kurshev", - TYPE_OUTPUT | TYPE_FX, - { 0, 0, 0, 0 }, - 2048, - 2048, - 4, - 4, - -1, - FLAG_UPSCALER | FLAG_DOWNSCALER | FLAG_EQUALIZER, - VENDOR_ATI, - 0, - { 0, 0, 0, 0} -}; - -#ifdef HAVE_X11 -static void probe_fireGL_driver(void) { - Display *dp = XOpenDisplay ((void*)0); - int n = 0; - char **extlist; - if (dp==NULL) { - return; - } - extlist = XListExtensions (dp, &n); - XCloseDisplay (dp); - if (extlist) { - int i; - int ext_fgl = 0, ext_fglrx = 0; - for (i = 0; i < n; i++) { - if (!strcmp(extlist[i], "ATIFGLEXTENSION")) ext_fgl = 1; - if (!strcmp(extlist[i], "ATIFGLRXDRI")) ext_fglrx = 1; - } - if (ext_fgl) { - printf(RADEON_MSG" ATI FireGl driver detected"); - firegl_shift = 0x500000; - if (!ext_fglrx) { - printf(", but DRI seems not to be activated\n"); - printf(RADEON_MSG" Output may not work correctly, check your DRI configuration!"); - } - printf("\n"); - } - } -} -#endif - -int vixProbe( int verbose,int force ) -{ - pciinfo_t lst[MAX_PCI_DEVICES]; - unsigned i,num_pci; - int err; - __verbose = verbose; - err = pci_scan(lst,&num_pci); - if(err) - { - printf(RADEON_MSG" Error occurred during pci scan: %s\n",strerror(err)); - return err; - } - else - { - err = ENXIO; - for(i=0;i<num_pci;i++) - { - if(lst[i].vendor == VENDOR_ATI) - { - int idx; - const char *dname; - idx = find_chip(lst[i].device); - if(idx == -1 && force == PROBE_NORMAL) continue; - dname = pci_device_name(VENDOR_ATI,lst[i].device); - dname = dname ? dname : "Unknown chip"; - printf(RADEON_MSG" Found chip: %s\n",dname); -#if 0 - if ((lst[i].command & PCI_COMMAND_IO) == 0) - { - printf("[radeon] Device is disabled, ignoring\n"); - continue; - } -#endif -#ifndef RAGE128 - if(idx != -1) -#ifdef HAVE_X11 - probe_fireGL_driver(); -#endif - { - switch(ati_card_ids[idx]) { - /* Original radeon */ - case DEVICE_ATI_RADEON_R100_QD: - case DEVICE_ATI_RADEON_R100_QE: - case DEVICE_ATI_RADEON_R100_QF: - case DEVICE_ATI_RADEON_R100_QG: - RadeonFamily = 100; - break; - - /* Radeon VE / Radeon Mobility */ - case DEVICE_ATI_RADEON_VE_QY: - case DEVICE_ATI_RADEON_VE_QZ: - case DEVICE_ATI_RADEON_MOBILITY_M6: - case DEVICE_ATI_RADEON_MOBILITY_M62: - case DEVICE_ATI_RADEON_MOBILITY_U1: - RadeonFamily = 120; - break; - - /* Radeon 7500 / Radeon Mobility 7500 */ - case DEVICE_ATI_RADEON_RV200_QW: - case DEVICE_ATI_RADEON_RV200_QX: - case DEVICE_ATI_RADEON_MOBILITY_M7: - case DEVICE_ATI_RADEON_MOBILITY_M72: - RadeonFamily = 150; - break; - - /* Radeon 8500 */ - case DEVICE_ATI_RADEON_R200_BB: - case DEVICE_ATI_RADEON_R200_QH: - case DEVICE_ATI_RADEON_R200_QI: - case DEVICE_ATI_RADEON_R200_QJ: - case DEVICE_ATI_RADEON_R200_QK: - case DEVICE_ATI_RADEON_R200_QL: - case DEVICE_ATI_RADEON_R200_QM: - case DEVICE_ATI_RADEON_R200_QH2: - case DEVICE_ATI_RADEON_R200_QI2: - case DEVICE_ATI_RADEON_R200_QJ2: - case DEVICE_ATI_RADEON_R200_QK2: - RadeonFamily = 200; - break; - - /* Radeon 9000 */ - case DEVICE_ATI_RADEON_R250_ID: - case DEVICE_ATI_RADEON_R250_IE: - case DEVICE_ATI_RADEON_R250_IF: - case DEVICE_ATI_RADEON_R250_IG: - case DEVICE_ATI_RADEON_R250_LD: - case DEVICE_ATI_RADEON_R250_LE: - case DEVICE_ATI_RADEON_R250_LF: - case DEVICE_ATI_RADEON_R250_LG: - case DEVICE_ATI_RV250_5C61_RADEON: - case DEVICE_ATI_RV250_5C63_RADEON: - RadeonFamily = 250; - break; - - /* Radeon 9200 */ - case DEVICE_ATI_RV280_RADEON_9200: - case DEVICE_ATI_RV280_RADEON_92002: - case DEVICE_ATI_RV280_RADEON_92003: - case DEVICE_ATI_RV280_RADEON_92004: - case DEVICE_ATI_RV280_RADEON_92005: - case DEVICE_ATI_RV280_RADEON_92006: - RadeonFamily = 280; - break; - - /* Radeon 9700 */ - case DEVICE_ATI_RADEON_R300_ND: - case DEVICE_ATI_RADEON_R300_NE: - case DEVICE_ATI_RADEON_R300_NF: - case DEVICE_ATI_RADEON_R300_NG: - case DEVICE_ATI_RADEON_R300_AE: - case DEVICE_ATI_RADEON_R300_AF: - RadeonFamily = 300; - break; - - /* Radeon 9600/9800 */ - case DEVICE_ATI_RV370_5B60_RADEON: - case DEVICE_ATI_RADEON_RV350_AP: - case DEVICE_ATI_RADEON_RV350_AQ: - case DEVICE_ATI_RADEON_RV350_AR: - case DEVICE_ATI_RADEON_RV350_BK: - case DEVICE_ATI_RADEON_R350_NH: - case DEVICE_ATI_RADEON_R350_AH: - case DEVICE_ATI_RADEON_R350_AI: - case DEVICE_ATI_RADEON_R360_NJ: - case DEVICE_ATI_RV350_MOBILITY_RADEON: - case DEVICE_ATI_RV350_MOBILITY_RADEON2: - RadeonFamily = 350; - break; - - default: - break; - } - } -#endif - if(force > PROBE_NORMAL) - { - printf(RADEON_MSG" Driver was forced. Was found %sknown chip\n",idx == -1 ? "un" : ""); - if(idx == -1) -#ifdef RAGE128 - printf(RADEON_MSG" Assuming it as Rage128\n"); -#else - printf(RADEON_MSG" Assuming it as Radeon1\n"); -#endif - } - def_cap.device_id = lst[i].device; - err = 0; - memcpy(&pci_info,&lst[i],sizeof(pciinfo_t)); - probed=1; - break; - } - } - } - if(err && verbose) printf(RADEON_MSG" Can't find chip\n"); - return err; -} - -static void radeon_vid_dump_regs( void ); /* forward declaration */ - -int vixInit( void ) -{ - int err; - if(!probed) - { - printf(RADEON_MSG" Driver was not probed but is being initializing\n"); - return EINTR; - } - if((radeon_mmio_base = map_phys_mem(pci_info.base2,0xFFFF))==(void *)-1) return ENOMEM; - radeon_ram_size = INREG(CONFIG_MEMSIZE); - /* mem size is bits [28:0], mask off the rest. Range: from 1Mb up to 512 Mb */ - radeon_ram_size &= CONFIG_MEMSIZE_MASK; -#ifdef RADEON - /* according to XFree86 4.2.0, some production M6's return 0 for 8MB */ - if (radeon_ram_size == 0 && - (def_cap.device_id == DEVICE_ATI_RADEON_MOBILITY_M6 || - def_cap.device_id == DEVICE_ATI_RADEON_MOBILITY_M62)) - { - printf(RADEON_MSG" Workarounding buggy Radeon Mobility M6 (0 vs. 8MB ram)\n"); - radeon_ram_size = 8192*1024; - } -#else - /* Rage Mobility (rage128) also has memsize bug */ - if (radeon_ram_size == 0 && - (def_cap.device_id == DEVICE_ATI_RAGE_MOBILITY_M3 || - def_cap.device_id == DEVICE_ATI_RAGE_128_RL_VR || - def_cap.device_id == DEVICE_ATI_RAGE_MOBILITY_M32)) - { - printf(RADEON_MSG" Workarounding buggy Rage Mobility M3 (0 vs. 8MB ram)\n"); - radeon_ram_size = 8192*1024; - } -#endif - printf(RADEON_MSG" Video memory = %uMb\n",radeon_ram_size/0x100000); -#ifdef WIN32 - //mapping large areas of video ram will fail on windows - if(radeon_ram_size > 16*1024*1024)radeon_ram_size=16*1024*1024; -#endif - if((radeon_mem_base = map_phys_mem(pci_info.base0,radeon_ram_size))==(void *)-1) return ENOMEM; - memset(&besr,0,sizeof(bes_registers_t)); - radeon_vid_make_default(); - err = mtrr_set_type(pci_info.base0,radeon_ram_size,MTRR_TYPE_WRCOMB); - if(!err) printf(RADEON_MSG" Set write-combining type of video memory\n"); - - radeon_fifo_wait(3); - SAVED_OV0_GRAPHICS_KEY_CLR = INREG(OV0_GRAPHICS_KEY_CLR); - SAVED_OV0_GRAPHICS_KEY_MSK = INREG(OV0_GRAPHICS_KEY_MSK); - SAVED_OV0_VID_KEY_CLR = INREG(OV0_VID_KEY_CLR); - SAVED_OV0_VID_KEY_MSK = INREG(OV0_VID_KEY_MSK); - SAVED_OV0_KEY_CNTL = INREG(OV0_KEY_CNTL); - printf(RADEON_MSG" Saved overlay colorkey settings\n"); - -#ifdef RADEON - switch(RadeonFamily) - { - case 100: - case 120: - case 150: - case 250: - case 280: - is_shift_required=1; - break; - default: - break; - } -#endif - -/* XXX: hack, but it works for me (tm) */ -#ifdef WORDS_BIGENDIAN -#if defined(RAGE128) - /* code from gatos */ - { - SAVED_CONFIG_CNTL = INREG(CONFIG_CNTL); - OUTREG(CONFIG_CNTL, SAVED_CONFIG_CNTL & - ~(APER_0_BIG_ENDIAN_16BPP_SWAP|APER_0_BIG_ENDIAN_32BPP_SWAP)); - -// printf("saved: %x, current: %x\n", SAVED_CONFIG_CNTL, -// INREG(CONFIG_CNTL)); - } -#else - /*code from radeon_video.c*/ - { - SAVED_CONFIG_CNTL = INREG(RADEON_SURFACE_CNTL); -/* OUTREG(RADEON_SURFACE_CNTL, (SAVED_CONFIG_CNTL | - RADEON_NONSURF_AP0_SWP_32BPP) & ~RADEON_NONSURF_AP0_SWP_16BPP); -*/ - OUTREG(RADEON_SURFACE_CNTL, SAVED_CONFIG_CNTL & ~(RADEON_NONSURF_AP0_SWP_32BPP - | RADEON_NONSURF_AP0_SWP_16BPP)); - -/* - OUTREG(RADEON_SURFACE_CNTL, (SAVED_CONFIG_CNTL | RADEON_NONSURF_AP0_SWP_32BPP) - & ~RADEON_NONSURF_AP0_SWP_16BPP); -*/ - } -#endif -#endif - - if(__verbose > 1) radeon_vid_dump_regs(); - return 0; -} - -void vixDestroy( void ) -{ - /* remove colorkeying */ - radeon_fifo_wait(3); - OUTREG(OV0_GRAPHICS_KEY_CLR, SAVED_OV0_GRAPHICS_KEY_CLR); - OUTREG(OV0_GRAPHICS_KEY_MSK, SAVED_OV0_GRAPHICS_KEY_MSK); - OUTREG(OV0_VID_KEY_CLR, SAVED_OV0_VID_KEY_CLR); - OUTREG(OV0_VID_KEY_MSK, SAVED_OV0_VID_KEY_MSK); - OUTREG(OV0_KEY_CNTL, SAVED_OV0_KEY_CNTL); - printf(RADEON_MSG" Restored overlay colorkey settings\n"); - -#ifdef WORDS_BIGENDIAN -#if defined(RAGE128) - OUTREG(CONFIG_CNTL, SAVED_CONFIG_CNTL); -// printf("saved: %x, restored: %x\n", SAVED_CONFIG_CNTL, -// INREG(CONFIG_CNTL)); -#else - OUTREG(RADEON_SURFACE_CNTL, SAVED_CONFIG_CNTL); -#endif -#endif - - unmap_phys_mem(radeon_mem_base,radeon_ram_size); - unmap_phys_mem(radeon_mmio_base,0xFFFF); -} - -int vixGetCapability(vidix_capability_t *to) -{ - memcpy(to,&def_cap,sizeof(vidix_capability_t)); - return 0; -} - -/* - Full list of fourcc which are supported by Win2K redeon driver: - YUY2, UYVY, DDES, OGLT, OGL2, OGLS, OGLB, OGNT, OGNZ, OGNS, - IF09, YVU9, IMC4, M2IA, IYUV, VBID, DXT1, DXT2, DXT3, DXT4, DXT5 -*/ -uint32_t supported_fourcc[] = -{ - IMGFMT_Y800, IMGFMT_Y8, IMGFMT_YVU9, IMGFMT_IF09, - IMGFMT_YV12, IMGFMT_I420, IMGFMT_IYUV, - IMGFMT_UYVY, IMGFMT_YUY2, IMGFMT_YVYU, - IMGFMT_RGB15, IMGFMT_BGR15, - IMGFMT_RGB16, IMGFMT_BGR16, - IMGFMT_RGB32, IMGFMT_BGR32 -}; - -inline static int is_supported_fourcc(uint32_t fourcc) -{ - unsigned int i; - for(i=0;i<sizeof(supported_fourcc)/sizeof(uint32_t);i++) - { - if(fourcc==supported_fourcc[i]) return 1; - } - return 0; -} - -int vixQueryFourcc(vidix_fourcc_t *to) -{ - if(is_supported_fourcc(to->fourcc)) - { - to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | - VID_DEPTH_4BPP | VID_DEPTH_8BPP | - VID_DEPTH_12BPP| VID_DEPTH_15BPP| - VID_DEPTH_16BPP| VID_DEPTH_24BPP| - VID_DEPTH_32BPP; - to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; - return 0; - } - else to->depth = to->flags = 0; - return ENOSYS; -} - -static void radeon_vid_dump_regs( void ) -{ - size_t i; - printf(RADEON_MSG"*** Begin of DRIVER variables dump ***\n"); - printf(RADEON_MSG"radeon_mmio_base=%p\n",radeon_mmio_base); - printf(RADEON_MSG"radeon_mem_base=%p\n",radeon_mem_base); - printf(RADEON_MSG"radeon_overlay_off=%08X\n",radeon_overlay_off); - printf(RADEON_MSG"radeon_ram_size=%08X\n",radeon_ram_size); - printf(RADEON_MSG"video mode: %ux%u@%u\n",radeon_get_xres(),radeon_get_yres(),radeon_vid_get_dbpp()); - printf(RADEON_MSG"flatpanel size: %ux%u\n",radeon_get_fp_xres(),radeon_get_fp_yres()); - printf(RADEON_MSG"*** Begin of OV0 registers dump ***\n"); - for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) - printf(RADEON_MSG"%s = %08X\n",vregs[i].sname,INREG(vregs[i].name)); - printf(RADEON_MSG"*** End of OV0 registers dump ***\n"); -} - -static void radeon_vid_stop_video( void ) -{ - radeon_engine_idle(); - OUTREG(OV0_SCALE_CNTL, SCALER_SOFT_RESET); - OUTREG(OV0_EXCLUSIVE_HORZ, 0); - OUTREG(OV0_AUTO_FLIP_CNTL, 0); /* maybe */ - OUTREG(OV0_FILTER_CNTL, FILTER_HARDCODED_COEF); -#ifdef RADEON - OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_EQ); -#else - OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_NE); -#endif - OUTREG(OV0_TEST, 0); -} - -static void radeon_vid_display_video( void ) -{ - int bes_flags; - /** workaround for Xorg-6.8 not saving the surface registers on bigendian architectures */ -#ifdef WORDS_BIGENDIAN -#if defined(RAGE128) - /* code from gatos */ - { - SAVED_CONFIG_CNTL = INREG(CONFIG_CNTL); - OUTREG(CONFIG_CNTL, SAVED_CONFIG_CNTL & - ~(APER_0_BIG_ENDIAN_16BPP_SWAP|APER_0_BIG_ENDIAN_32BPP_SWAP)); - -// printf("saved: %x, current: %x\n", SAVED_CONFIG_CNTL, -// INREG(CONFIG_CNTL)); - } -#else - /*code from radeon_video.c*/ - { - SAVED_CONFIG_CNTL = INREG(RADEON_SURFACE_CNTL); -/* OUTREG(RADEON_SURFACE_CNTL, (SAVED_CONFIG_CNTL | - RADEON_NONSURF_AP0_SWP_32BPP) & ~RADEON_NONSURF_AP0_SWP_16BPP); -*/ - OUTREG(RADEON_SURFACE_CNTL, SAVED_CONFIG_CNTL & ~(RADEON_NONSURF_AP0_SWP_32BPP - | RADEON_NONSURF_AP0_SWP_16BPP)); - -/* - OUTREG(RADEON_SURFACE_CNTL, (SAVED_CONFIG_CNTL | RADEON_NONSURF_AP0_SWP_32BPP) - & ~RADEON_NONSURF_AP0_SWP_16BPP); -*/ - } -#endif -#endif - - - - radeon_fifo_wait(2); - OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); - radeon_engine_idle(); - while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); - radeon_fifo_wait(15); - - /* Shutdown capturing */ - OUTREG(FCP_CNTL, FCP_CNTL__GND); - OUTREG(CAP0_TRIG_CNTL, 0); - - OUTREG(VID_BUFFER_CONTROL, (1<<16) | 0x01); - OUTREG(DISP_TEST_DEBUG_CNTL, 0); - - OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD); - - if(besr.deinterlace_on) OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); -#ifdef RAGE128 - OUTREG(OV0_COLOUR_CNTL, (((besr.brightness*64)/1000) & 0x7f) | - (((besr.saturation*31+31000)/2000) << 8) | - (((besr.saturation*31+31000)/2000) << 16)); -#endif - radeon_fifo_wait(2); - OUTREG(OV0_GRAPHICS_KEY_MSK, besr.graphics_key_msk); - OUTREG(OV0_GRAPHICS_KEY_CLR, besr.graphics_key_clr); - OUTREG(OV0_KEY_CNTL,besr.ckey_cntl); - - OUTREG(OV0_H_INC, besr.h_inc); - OUTREG(OV0_STEP_BY, besr.step_by); - OUTREG(OV0_Y_X_START, besr.y_x_start); - OUTREG(OV0_Y_X_END, besr.y_x_end); - OUTREG(OV0_V_INC, besr.v_inc); - OUTREG(OV0_P1_BLANK_LINES_AT_TOP, besr.p1_blank_lines_at_top); - OUTREG(OV0_P23_BLANK_LINES_AT_TOP, besr.p23_blank_lines_at_top); - OUTREG(OV0_VID_BUF_PITCH0_VALUE, besr.vid_buf_pitch0_value); - OUTREG(OV0_VID_BUF_PITCH1_VALUE, besr.vid_buf_pitch1_value); - OUTREG(OV0_P1_X_START_END, besr.p1_x_start_end); - OUTREG(OV0_P2_X_START_END, besr.p2_x_start_end); - OUTREG(OV0_P3_X_START_END, besr.p3_x_start_end); -#ifdef RADEON - OUTREG(OV0_BASE_ADDR, besr.base_addr); -#endif - OUTREG(OV0_VID_BUF0_BASE_ADRS, besr.vid_buf_base_adrs_y[0]); - OUTREG(OV0_VID_BUF1_BASE_ADRS, besr.vid_buf_base_adrs_v[0]); - OUTREG(OV0_VID_BUF2_BASE_ADRS, besr.vid_buf_base_adrs_u[0]); - radeon_fifo_wait(9); - OUTREG(OV0_VID_BUF3_BASE_ADRS, besr.vid_buf_base_adrs_y[0]); - OUTREG(OV0_VID_BUF4_BASE_ADRS, besr.vid_buf_base_adrs_v[0]); - OUTREG(OV0_VID_BUF5_BASE_ADRS, besr.vid_buf_base_adrs_u[0]); - OUTREG(OV0_P1_V_ACCUM_INIT, besr.p1_v_accum_init); - OUTREG(OV0_P1_H_ACCUM_INIT, besr.p1_h_accum_init); - OUTREG(OV0_P23_H_ACCUM_INIT, besr.p23_h_accum_init); - OUTREG(OV0_P23_V_ACCUM_INIT, besr.p23_v_accum_init); - -#ifdef RADEON - bes_flags = SCALER_ENABLE | - SCALER_SMART_SWITCH; -// SCALER_HORZ_PICK_NEAREST | -// SCALER_VERT_PICK_NEAREST | -#endif - bes_flags = SCALER_ENABLE | - SCALER_SMART_SWITCH | - SCALER_Y2R_TEMP | - SCALER_PIX_EXPAND; - if(besr.double_buff) bes_flags |= SCALER_DOUBLE_BUFFER; - if(besr.deinterlace_on) bes_flags |= SCALER_ADAPTIVE_DEINT; -#ifdef RAGE128 - bes_flags |= SCALER_BURST_PER_PLANE; -#endif - switch(besr.fourcc) - { - case IMGFMT_RGB15: - case IMGFMT_BGR15: bes_flags |= SCALER_SOURCE_15BPP; break; - case IMGFMT_RGB16: - case IMGFMT_BGR16: bes_flags |= SCALER_SOURCE_16BPP; break; -/* - case IMGFMT_RGB24: - case IMGFMT_BGR24: bes_flags |= SCALER_SOURCE_24BPP; break; -*/ - case IMGFMT_RGB32: - case IMGFMT_BGR32: bes_flags |= SCALER_SOURCE_32BPP; break; - /* 4:1:0 */ - case IMGFMT_IF09: - case IMGFMT_YVU9: bes_flags |= SCALER_SOURCE_YUV9; break; - /* 4:0:0 */ - case IMGFMT_Y800: - case IMGFMT_Y8: - /* 4:2:0 */ - case IMGFMT_IYUV: - case IMGFMT_I420: - case IMGFMT_YV12: bes_flags |= SCALER_SOURCE_YUV12; break; - /* 4:2:2 */ - case IMGFMT_YVYU: - case IMGFMT_UYVY: bes_flags |= SCALER_SOURCE_YVYU422; break; - case IMGFMT_YUY2: - default: bes_flags |= SCALER_SOURCE_VYUY422; break; - } - OUTREG(OV0_SCALE_CNTL, bes_flags); - OUTREG(OV0_REG_LOAD_CNTL, 0); - if(__verbose > 1) printf(RADEON_MSG"we wanted: scaler=%08X\n",bes_flags); - if(__verbose > 1) radeon_vid_dump_regs(); -} - -static unsigned radeon_query_pitch(unsigned fourcc,const vidix_yuv_t *spitch) -{ - unsigned pitch,spy,spv,spu; - spy = spv = spu = 0; - switch(spitch->y) - { - case 16: - case 32: - case 64: - case 128: - case 256: spy = spitch->y; break; - default: break; - } - switch(spitch->u) - { - case 16: - case 32: - case 64: - case 128: - case 256: spu = spitch->u; break; - default: break; - } - switch(spitch->v) - { - case 16: - case 32: - case 64: - case 128: - case 256: spv = spitch->v; break; - default: break; - } - switch(fourcc) - { - /* 4:2:0 */ - case IMGFMT_IYUV: - case IMGFMT_YV12: - case IMGFMT_I420: - if(spy > 16 && spu == spy/2 && spv == spy/2) pitch = spy; - else pitch = 32; - break; - /* 4:1:0 */ - case IMGFMT_IF09: - case IMGFMT_YVU9: - if(spy > 32 && spu == spy/4 && spv == spy/4) pitch = spy; - else pitch = 64; - break; - default: - if(spy >= 16) pitch = spy; - else pitch = 16; - break; - } - return pitch; -} - -static int radeon_vid_init_video( vidix_playback_t *config ) -{ - uint32_t i,tmp,src_w,src_h,dest_w,dest_h,pitch,h_inc,step_by,left,leftUV,top; - int is_400,is_410,is_420,is_rgb32,is_rgb,best_pitch,mpitch; - radeon_vid_stop_video(); - left = config->src.x << 16; - top = config->src.y << 16; - src_h = config->src.h; - src_w = config->src.w; - is_400 = is_410 = is_420 = is_rgb32 = is_rgb = 0; - if(config->fourcc == IMGFMT_YV12 || - config->fourcc == IMGFMT_I420 || - config->fourcc == IMGFMT_IYUV) is_420 = 1; - if(config->fourcc == IMGFMT_YVU9 || - config->fourcc == IMGFMT_IF09) is_410 = 1; - if(config->fourcc == IMGFMT_Y800 || - config->fourcc == IMGFMT_Y8) is_400 = 1; - if(config->fourcc == IMGFMT_RGB32 || - config->fourcc == IMGFMT_BGR32) is_rgb32 = 1; - if(config->fourcc == IMGFMT_RGB32 || - config->fourcc == IMGFMT_BGR32 || - config->fourcc == IMGFMT_RGB24 || - config->fourcc == IMGFMT_BGR24 || - config->fourcc == IMGFMT_RGB16 || - config->fourcc == IMGFMT_BGR16 || - config->fourcc == IMGFMT_RGB15 || - config->fourcc == IMGFMT_BGR15) is_rgb = 1; - best_pitch = radeon_query_pitch(config->fourcc,&config->src.pitch); - mpitch = best_pitch-1; - switch(config->fourcc) - { - /* 4:0:0 */ - case IMGFMT_Y800: - case IMGFMT_Y8: - /* 4:1:0 */ - case IMGFMT_YVU9: - case IMGFMT_IF09: - /* 4:2:0 */ - case IMGFMT_IYUV: - case IMGFMT_YV12: - case IMGFMT_I420: pitch = (src_w + mpitch) & ~mpitch; - config->dest.pitch.y = - config->dest.pitch.u = - config->dest.pitch.v = best_pitch; - break; - /* RGB 4:4:4:4 */ - case IMGFMT_RGB32: - case IMGFMT_BGR32: pitch = (src_w*4 + mpitch) & ~mpitch; - config->dest.pitch.y = - config->dest.pitch.u = - config->dest.pitch.v = best_pitch; - break; - /* 4:2:2 */ - default: /* RGB15, RGB16, YVYU, UYVY, YUY2 */ - pitch = ((src_w*2) + mpitch) & ~mpitch; - config->dest.pitch.y = - config->dest.pitch.u = - config->dest.pitch.v = best_pitch; - break; - } - dest_w = config->dest.w; - dest_h = config->dest.h; - if(radeon_is_dbl_scan()) dest_h *= 2; - besr.dest_bpp = radeon_vid_get_dbpp(); - besr.fourcc = config->fourcc; - - /* flat panel */ - if(INREG(FP_VERT_STRETCH)&VERT_STRETCH_ENABLE){ - besr.v_inc = (src_h * radeon_get_yres() / radeon_get_fp_yres() << 20) / dest_h; - } - else besr.v_inc = (src_h << 20) / dest_h; - if(radeon_is_interlace()) besr.v_inc *= 2; - h_inc = (src_w << 12) / dest_w; - - { - unsigned int ecp_div; - ecp_div = (INPLL(VCLK_ECP_CNTL) >> 8) & 3; - h_inc <<= ecp_div; - } - - - step_by = 1; - while(h_inc >= (2 << 12)) { - step_by++; - h_inc >>= 1; - } - - /* keep everything in 16.16 */ - besr.base_addr = INREG(DISPLAY_BASE_ADDR); - config->offsets[0] = 0; - for(i=1;i<besr.vid_nbufs;i++) - config->offsets[i] = config->offsets[i-1]+config->frame_size; - if(is_420 || is_410 || is_400) - { - uint32_t d1line,d2line,d3line; - d1line = top*pitch; - if(is_420) - { - d2line = src_h*pitch+(d1line>>2); - d3line = d2line+((src_h*pitch)>>2); - } - else - if(is_410) - { - d2line = src_h*pitch+(d1line>>4); - d3line = d2line+((src_h*pitch)>>4); - } - else - { - d2line = 0; - d3line = 0; - } - d1line += (left >> 16) & ~15; - if(is_420) - { - d2line += (left >> 17) & ~15; - d3line += (left >> 17) & ~15; - } - else - if(is_410) - { - d2line += (left >> 18) & ~15; - d3line += (left >> 18) & ~15; - } - config->offset.y = d1line & VIF_BUF0_BASE_ADRS_MASK; - if(is_400) - { - config->offset.v = 0; - config->offset.u = 0; - } - else - { - config->offset.v = d2line & VIF_BUF1_BASE_ADRS_MASK; - config->offset.u = d3line & VIF_BUF2_BASE_ADRS_MASK; - } - for(i=0;i<besr.vid_nbufs;i++) - { - besr.vid_buf_base_adrs_y[i]=((radeon_overlay_off+config->offsets[i]+config->offset.y)&VIF_BUF0_BASE_ADRS_MASK); - if(is_400) - { - besr.vid_buf_base_adrs_v[i]=0; - besr.vid_buf_base_adrs_u[i]=0; - } - else - { - if (besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV) - { - besr.vid_buf_base_adrs_u[i]=((radeon_overlay_off+config->offsets[i]+config->offset.v)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL; - besr.vid_buf_base_adrs_v[i]=((radeon_overlay_off+config->offsets[i]+config->offset.u)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL; - } - else - { - besr.vid_buf_base_adrs_v[i]=((radeon_overlay_off+config->offsets[i]+config->offset.v)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL; - besr.vid_buf_base_adrs_u[i]=((radeon_overlay_off+config->offsets[i]+config->offset.u)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL; - } - } - } - config->offset.y = ((besr.vid_buf_base_adrs_y[0])&VIF_BUF0_BASE_ADRS_MASK) - radeon_overlay_off; - if(is_400) - { - config->offset.v = 0; - config->offset.u = 0; - } - else - { - config->offset.v = ((besr.vid_buf_base_adrs_v[0])&VIF_BUF1_BASE_ADRS_MASK) - radeon_overlay_off; - config->offset.u = ((besr.vid_buf_base_adrs_u[0])&VIF_BUF2_BASE_ADRS_MASK) - radeon_overlay_off; - } - } - else - { - config->offset.y = config->offset.u = config->offset.v = ((left & ~7) << 1)&VIF_BUF0_BASE_ADRS_MASK; - for(i=0;i<besr.vid_nbufs;i++) - { - besr.vid_buf_base_adrs_y[i] = - besr.vid_buf_base_adrs_u[i] = - besr.vid_buf_base_adrs_v[i] = radeon_overlay_off + config->offsets[i] + config->offset.y; - } - } - - tmp = (left & 0x0003ffff) + 0x00028000 + (h_inc << 3); - besr.p1_h_accum_init = ((tmp << 4) & 0x000f8000) | - ((tmp << 12) & 0xf0000000); - - tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc << 2); - besr.p23_h_accum_init = ((tmp << 4) & 0x000f8000) | - ((tmp << 12) & 0x70000000); - tmp = (top & 0x0000ffff) + 0x00018000; - besr.p1_v_accum_init = ((tmp << 4) & OV0_P1_V_ACCUM_INIT_MASK) - |(OV0_P1_MAX_LN_IN_PER_LN_OUT & 1); - - tmp = ((top >> 1) & 0x0000ffff) + 0x00018000; - besr.p23_v_accum_init = (is_420||is_410) ? - ((tmp << 4) & OV0_P23_V_ACCUM_INIT_MASK) - |(OV0_P23_MAX_LN_IN_PER_LN_OUT & 1) : 0; - - leftUV = (left >> (is_410?18:17)) & 15; - left = (left >> 16) & 15; - if(is_rgb && !is_rgb32) h_inc<<=1; - if(is_rgb32) - besr.h_inc = (h_inc >> 1) | ((h_inc >> 1) << 16); - else - if(is_410) - besr.h_inc = h_inc | ((h_inc >> 2) << 16); - else - besr.h_inc = h_inc | ((h_inc >> 1) << 16); - besr.step_by = step_by | (step_by << 8); - besr.y_x_start = (config->dest.x+X_ADJUST) | (config->dest.y << 16); - besr.y_x_end = (config->dest.x + dest_w+X_ADJUST) | ((config->dest.y + dest_h) << 16); - besr.p1_blank_lines_at_top = P1_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); - if(is_420 || is_410) - { - src_h = (src_h + 1) >> (is_410?2:1); - besr.p23_blank_lines_at_top = P23_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); - } - else besr.p23_blank_lines_at_top = 0; - besr.vid_buf_pitch0_value = pitch; - besr.vid_buf_pitch1_value = is_410 ? pitch>>2 : is_420 ? pitch>>1 : pitch; - besr.p1_x_start_end = (src_w+left-1)|(left<<16); - if (is_410||is_420) src_w>>=is_410?2:1; - if(is_400) - { - besr.p2_x_start_end = 0; - besr.p3_x_start_end = 0; - } - else - { - besr.p2_x_start_end = (src_w+left-1)|(leftUV<<16); - besr.p3_x_start_end = besr.p2_x_start_end; - } - - return 0; -} - -static void radeon_compute_framesize(vidix_playback_t *info) -{ - unsigned pitch,awidth,dbpp; - pitch = radeon_query_pitch(info->fourcc,&info->src.pitch); - dbpp = radeon_vid_get_dbpp(); - switch(info->fourcc) - { - case IMGFMT_I420: - case IMGFMT_YV12: - case IMGFMT_IYUV: - awidth = (info->src.w + (pitch-1)) & ~(pitch-1); - info->frame_size = awidth*(info->src.h+info->src.h/2); - break; - case IMGFMT_Y800: - case IMGFMT_Y8: - awidth = (info->src.w + (pitch-1)) & ~(pitch-1); - info->frame_size = awidth*info->src.h; - break; - case IMGFMT_IF09: - case IMGFMT_YVU9: - awidth = (info->src.w + (pitch-1)) & ~(pitch-1); - info->frame_size = awidth*(info->src.h+info->src.h/8); - break; - case IMGFMT_RGB32: - case IMGFMT_BGR32: - awidth = (info->src.w*4 + (pitch-1)) & ~(pitch-1); - info->frame_size = awidth*info->src.h; - break; - /* YUY2 YVYU, RGB15, RGB16 */ - default: - awidth = (info->src.w*2 + (pitch-1)) & ~(pitch-1); - info->frame_size = awidth*info->src.h; - break; - } -} - -int vixConfigPlayback(vidix_playback_t *info) -{ - unsigned rgb_size,nfr; - if(!is_supported_fourcc(info->fourcc)) return ENOSYS; - if(info->num_frames>VID_PLAY_MAXFRAMES) info->num_frames=VID_PLAY_MAXFRAMES; - if(info->num_frames==1) besr.double_buff=0; - else besr.double_buff=1; - radeon_compute_framesize(info); - - rgb_size = radeon_get_xres()*radeon_get_yres()*((radeon_vid_get_dbpp()+7)/8); - nfr = info->num_frames; - for(;nfr>0; nfr--) - { - radeon_overlay_off = radeon_ram_size - info->frame_size*nfr; -#ifdef HAVE_X11 - radeon_overlay_off -= firegl_shift; -#endif - radeon_overlay_off &= 0xffff0000; - if(radeon_overlay_off >= (int)rgb_size ) break; - } - if(nfr <= 3) - { - nfr = info->num_frames; - for(;nfr>0; nfr--) - { - radeon_overlay_off = radeon_ram_size - info->frame_size*nfr; -#ifdef HAVE_X11 - radeon_overlay_off -= firegl_shift; -#endif - radeon_overlay_off &= 0xffff0000; - if(radeon_overlay_off > 0) break; - } - } - if(nfr <= 0) return EINVAL; - info->num_frames = nfr; - besr.vid_nbufs = info->num_frames; - info->dga_addr = (char *)radeon_mem_base + radeon_overlay_off; - radeon_vid_init_video(info); - return 0; -} - -int vixPlaybackOn( void ) -{ - radeon_vid_display_video(); - return 0; -} - -int vixPlaybackOff( void ) -{ - radeon_vid_stop_video(); - return 0; -} - -int vixPlaybackFrameSelect(unsigned frame) -{ - uint32_t off[6]; - int prev_frame= (frame-1+besr.vid_nbufs) % besr.vid_nbufs; - /* - buf3-5 always should point onto second buffer for better - deinterlacing and TV-in - */ - if(!besr.double_buff) return 0; - if(frame > besr.vid_nbufs) frame = besr.vid_nbufs-1; - if(prev_frame > (int)besr.vid_nbufs) prev_frame = besr.vid_nbufs-1; - off[0] = besr.vid_buf_base_adrs_y[frame]; - off[1] = besr.vid_buf_base_adrs_v[frame]; - off[2] = besr.vid_buf_base_adrs_u[frame]; - off[3] = besr.vid_buf_base_adrs_y[prev_frame]; - off[4] = besr.vid_buf_base_adrs_v[prev_frame]; - off[5] = besr.vid_buf_base_adrs_u[prev_frame]; - radeon_fifo_wait(8); - OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); - radeon_engine_idle(); - while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); - OUTREG(OV0_VID_BUF0_BASE_ADRS, off[0]); - OUTREG(OV0_VID_BUF1_BASE_ADRS, off[1]); - OUTREG(OV0_VID_BUF2_BASE_ADRS, off[2]); - OUTREG(OV0_VID_BUF3_BASE_ADRS, off[3]); - OUTREG(OV0_VID_BUF4_BASE_ADRS, off[4]); - OUTREG(OV0_VID_BUF5_BASE_ADRS, off[5]); - OUTREG(OV0_REG_LOAD_CNTL, 0); - if(besr.vid_nbufs == 2) radeon_wait_vsync(); - if(__verbose > 1) radeon_vid_dump_regs(); - return 0; -} - -vidix_video_eq_t equal = -{ - VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION -#ifndef RAGE128 - | VEQ_CAP_CONTRAST | VEQ_CAP_HUE | VEQ_CAP_RGB_INTENSITY -#endif - , - 0, 0, 0, 0, 0, 0, 0, 0 }; - -int vixPlaybackGetEq( vidix_video_eq_t * eq) -{ - memcpy(eq,&equal,sizeof(vidix_video_eq_t)); - return 0; -} - -#ifndef RAGE128 -#define RTFSaturation(a) (1.0 + ((a)*1.0)/1000.0) -#define RTFBrightness(a) (((a)*1.0)/2000.0) -#define RTFIntensity(a) (((a)*1.0)/2000.0) -#define RTFContrast(a) (1.0 + ((a)*1.0)/1000.0) -#define RTFHue(a) (((a)*3.1416)/1000.0) -#define RTFCheckParam(a) {if((a)<-1000) (a)=-1000; if((a)>1000) (a)=1000;} -#endif - -int vixPlaybackSetEq( const vidix_video_eq_t * eq) -{ -#ifdef RAGE128 - int br,sat; -#else - int itu_space; -#endif - if(eq->cap & VEQ_CAP_BRIGHTNESS) equal.brightness = eq->brightness; - if(eq->cap & VEQ_CAP_CONTRAST) equal.contrast = eq->contrast; - if(eq->cap & VEQ_CAP_SATURATION) equal.saturation = eq->saturation; - if(eq->cap & VEQ_CAP_HUE) equal.hue = eq->hue; - if(eq->cap & VEQ_CAP_RGB_INTENSITY) - { - equal.red_intensity = eq->red_intensity; - equal.green_intensity = eq->green_intensity; - equal.blue_intensity = eq->blue_intensity; - } - equal.flags = eq->flags; -#ifdef RAGE128 - br = equal.brightness * 64 / 1000; - if(br < -64) br = -64; if(br > 63) br = 63; - sat = (equal.saturation + 1000) * 16 / 1000; - if(sat < 0) sat = 0; if(sat > 31) sat = 31; - OUTREG(OV0_COLOUR_CNTL, (br & 0x7f) | (sat << 8) | (sat << 16)); -#else - itu_space = equal.flags == VEQ_FLG_ITU_R_BT_709 ? 1 : 0; - RTFCheckParam(equal.brightness); - RTFCheckParam(equal.saturation); - RTFCheckParam(equal.contrast); - RTFCheckParam(equal.hue); - RTFCheckParam(equal.red_intensity); - RTFCheckParam(equal.green_intensity); - RTFCheckParam(equal.blue_intensity); - radeon_set_transform(RTFBrightness(equal.brightness), - RTFContrast(equal.contrast), - RTFSaturation(equal.saturation), - RTFHue(equal.hue), - RTFIntensity(equal.red_intensity), - RTFIntensity(equal.green_intensity), - RTFIntensity(equal.blue_intensity), - itu_space); -#endif - return 0; -} - -int vixPlaybackSetDeint( const vidix_deinterlace_t * info) -{ - unsigned sflg; - switch(info->flags) - { - default: - case CFG_NON_INTERLACED: - besr.deinterlace_on = 0; - break; - case CFG_EVEN_ODD_INTERLACING: - case CFG_INTERLACED: - besr.deinterlace_on = 1; - besr.deinterlace_pattern = 0x900AAAAA; - break; - case CFG_ODD_EVEN_INTERLACING: - besr.deinterlace_on = 1; - besr.deinterlace_pattern = 0x00055555; - break; - case CFG_UNIQUE_INTERLACING: - besr.deinterlace_on = 1; - besr.deinterlace_pattern = info->deinterlace_pattern; - break; - } - OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); - radeon_engine_idle(); - while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); - radeon_fifo_wait(15); - sflg = INREG(OV0_SCALE_CNTL); - if(besr.deinterlace_on) - { - OUTREG(OV0_SCALE_CNTL,sflg | SCALER_ADAPTIVE_DEINT); - OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); - } - else OUTREG(OV0_SCALE_CNTL,sflg & (~SCALER_ADAPTIVE_DEINT)); - OUTREG(OV0_REG_LOAD_CNTL, 0); - return 0; -} - -int vixPlaybackGetDeint( vidix_deinterlace_t * info) -{ - if(!besr.deinterlace_on) info->flags = CFG_NON_INTERLACED; - else - { - info->flags = CFG_UNIQUE_INTERLACING; - info->deinterlace_pattern = besr.deinterlace_pattern; - } - return 0; -} - - -/* Graphic keys */ -static vidix_grkey_t radeon_grkey; - -static void set_gr_key( void ) -{ - if(radeon_grkey.ckey.op == CKEY_TRUE) - { - int dbpp=radeon_vid_get_dbpp(); - besr.ckey_on=1; - - switch(dbpp) - { - case 15: -#ifdef RADEON - if(RadeonFamily > 100) - besr.graphics_key_clr= - ((radeon_grkey.ckey.blue &0xF8)) - | ((radeon_grkey.ckey.green&0xF8)<<8) - | ((radeon_grkey.ckey.red &0xF8)<<16); - else -#endif - besr.graphics_key_clr= - ((radeon_grkey.ckey.blue &0xF8)>>3) - | ((radeon_grkey.ckey.green&0xF8)<<2) - | ((radeon_grkey.ckey.red &0xF8)<<7); - break; - case 16: -#ifdef RADEON - /* This test may be too general/specific */ - if(RadeonFamily > 100) - besr.graphics_key_clr= - ((radeon_grkey.ckey.blue &0xF8)) - | ((radeon_grkey.ckey.green&0xFC)<<8) - | ((radeon_grkey.ckey.red &0xF8)<<16); - else -#endif - besr.graphics_key_clr= - ((radeon_grkey.ckey.blue &0xF8)>>3) - | ((radeon_grkey.ckey.green&0xFC)<<3) - | ((radeon_grkey.ckey.red &0xF8)<<8); - break; - case 24: - besr.graphics_key_clr= - ((radeon_grkey.ckey.blue &0xFF)) - | ((radeon_grkey.ckey.green&0xFF)<<8) - | ((radeon_grkey.ckey.red &0xFF)<<16); - break; - case 32: - besr.graphics_key_clr= - ((radeon_grkey.ckey.blue &0xFF)) - | ((radeon_grkey.ckey.green&0xFF)<<8) - | ((radeon_grkey.ckey.red &0xFF)<<16); - break; - default: - besr.ckey_on=0; - besr.graphics_key_msk=0; - besr.graphics_key_clr=0; - } -#ifdef RAGE128 - besr.graphics_key_msk=(1<<dbpp)-1; - besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_NE|CMP_MIX_AND; -#else - besr.graphics_key_msk=besr.graphics_key_clr; - besr.ckey_cntl = VIDEO_KEY_FN_TRUE|CMP_MIX_AND|GRAPHIC_KEY_FN_EQ; -#endif - } - else - { - besr.ckey_on=0; - besr.graphics_key_msk=0; - besr.graphics_key_clr=0; - besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_TRUE|CMP_MIX_AND; - } - radeon_fifo_wait(3); - OUTREG(OV0_GRAPHICS_KEY_MSK, besr.graphics_key_msk); - OUTREG(OV0_GRAPHICS_KEY_CLR, besr.graphics_key_clr); - OUTREG(OV0_KEY_CNTL,besr.ckey_cntl); -} - -int vixGetGrKeys(vidix_grkey_t *grkey) -{ - memcpy(grkey, &radeon_grkey, sizeof(vidix_grkey_t)); - return(0); -} - -int vixSetGrKeys(const vidix_grkey_t *grkey) -{ - memcpy(&radeon_grkey, grkey, sizeof(vidix_grkey_t)); - set_gr_key(); - return(0); -}
--- a/vidix/drivers/savage_regs.h Sat Mar 31 23:48:48 2007 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,303 +0,0 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/savage/savage_regs.h,v 1.10 2001/11/04 22:17:48 alanh Exp $ */ - -#ifndef _SAVAGE_REGS_H -#define _SAVAGE_REGS_H - -/* These are here until xf86PciInfo.h is updated. */ - -#ifndef PCI_CHIP_S3TWISTER_P -#define PCI_CHIP_S3TWISTER_P 0x8d01 -#endif -#ifndef PCI_CHIP_S3TWISTER_K -#define PCI_CHIP_S3TWISTER_K 0x8d02 -#endif -#ifndef PCI_CHIP_SUPSAV_MX128 -#define PCI_CHIP_SUPSAV_MX128 0x8c22 -#define PCI_CHIP_SUPSAV_MX64 0x8c24 -#define PCI_CHIP_SUPSAV_MX64C 0x8c26 -#define PCI_CHIP_SUPSAV_IX128SDR 0x8c2a -#define PCI_CHIP_SUPSAV_IX128DDR 0x8c2b -#define PCI_CHIP_SUPSAV_IX64SDR 0x8c2c -#define PCI_CHIP_SUPSAV_IX64DDR 0x8c2d -#define PCI_CHIP_SUPSAV_IXCSDR 0x8c2e -#define PCI_CHIP_SUPSAV_IXCDDR 0x8c2f -#endif -#ifndef PCI_CHIP_PROSAVAGE_DDR -#define PCI_CHIP_PROSAVAGE_DDR 0x8d03 -#define PCI_CHIP_PROSAVAGE_DDRK 0x8d04 -#endif - -#define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX)) - -#define S3_SAVAGE4_SERIES(chip) ((chip==S3_SAVAGE4) || (chip==S3_PROSAVAGE)) - -#define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE)) - -#define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000)) - - -/* Chip tags. These are used to group the adapters into - * related families. - */ - - -enum S3CHIPTAGS { - S3_UNKNOWN = 0, - S3_SAVAGE3D, - S3_SAVAGE_MX, - S3_SAVAGE4, - S3_PROSAVAGE, - S3_SUPERSAVAGE, - S3_SAVAGE2000, - S3_LAST -}; - -typedef struct { - unsigned int mode, refresh; - unsigned char SR08, SR0E, SR0F; - unsigned char SR10, SR11, SR12, SR13, SR15, SR18, SR1B, SR29, SR30; - unsigned char SR54[8]; - unsigned char Clock; - unsigned char CR31, CR32, CR33, CR34, CR36, CR3A, CR3B, CR3C; - unsigned char CR40, CR41, CR42, CR43, CR45; - unsigned char CR50, CR51, CR53, CR55, CR58, CR5B, CR5D, CR5E; - unsigned char CR60, CR63, CR65, CR66, CR67, CR68, CR69, CR6D, CR6F; - unsigned char CR86, CR88; - unsigned char CR90, CR91, CRB0; - unsigned int STREAMS[22]; /* yuck, streams regs */ - unsigned int MMPR0, MMPR1, MMPR2, MMPR3; -} SavageRegRec, *SavageRegPtr; - - - -#define BIOS_BSIZE 1024 -#define BIOS_BASE 0xc0000 - -#define SAVAGE_NEWMMIO_REGBASE_S3 0x1000000 /* 16MB */ -#define SAVAGE_NEWMMIO_REGBASE_S4 0x0000000 -#define SAVAGE_NEWMMIO_REGSIZE 0x0080000 /* 512kb */ -#define SAVAGE_NEWMMIO_VGABASE 0x8000 - -#define BASE_FREQ 14.31818 - -#define FIFO_CONTROL_REG 0x8200 -#define MIU_CONTROL_REG 0x8204 -#define STREAMS_TIMEOUT_REG 0x8208 -#define MISC_TIMEOUT_REG 0x820c - -/* Stream Processor 1 */ - -/* Primary Stream 1 Frame Buffer Address 0 */ -#define PRI_STREAM_FBUF_ADDR0 0x81c0 -/* Primary Stream 1 Frame Buffer Address 0 */ -#define PRI_STREAM_FBUF_ADDR1 0x81c4 -/* Primary Stream 1 Stride */ -#define PRI_STREAM_STRIDE 0x81c8 -/* Primary Stream 1 Frame Buffer Size */ -#define PRI_STREAM_BUFFERSIZE 0x8214 - -/* Secondary stream 1 Color/Chroma Key Control */ -#define SEC_STREAM_CKEY_LOW 0x8184 -/* Secondary stream 1 Chroma Key Upper Bound */ -#define SEC_STREAM_CKEY_UPPER 0x8194 -/* Blend Control of Secondary Stream 1 & 2 */ -#define BLEND_CONTROL 0x8190 -/* Secondary Stream 1 Color conversion/Adjustment 1 */ -#define SEC_STREAM_COLOR_CONVERT1 0x8198 -/* Secondary Stream 1 Color conversion/Adjustment 2 */ -#define SEC_STREAM_COLOR_CONVERT2 0x819c -/* Secondary Stream 1 Color conversion/Adjustment 3 */ -#define SEC_STREAM_COLOR_CONVERT3 0x81e4 -/* Secondary Stream 1 Horizontal Scaling */ -#define SEC_STREAM_HSCALING 0x81a0 -/* Secondary Stream 1 Frame Buffer Size */ -#define SEC_STREAM_BUFFERSIZE 0x81a8 -/* Secondary Stream 1 Horizontal Scaling Normalization (2K only) */ -#define SEC_STREAM_HSCALE_NORMALIZE 0x81ac -/* Secondary Stream 1 Horizontal Scaling */ -#define SEC_STREAM_VSCALING 0x81e8 -/* Secondary Stream 1 Frame Buffer Address 0 */ -#define SEC_STREAM_FBUF_ADDR0 0x81d0 -/* Secondary Stream 1 Frame Buffer Address 1 */ -#define SEC_STREAM_FBUF_ADDR1 0x81d4 -/* Secondary Stream 1 Frame Buffer Address 2 */ -#define SEC_STREAM_FBUF_ADDR2 0x81ec -/* Secondary Stream 1 Stride */ -#define SEC_STREAM_STRIDE 0x81d8 -/* Secondary Stream 1 Window Start Coordinates */ -#define SEC_STREAM_WINDOW_START 0x81f8 -/* Secondary Stream 1 Window Size */ -#define SEC_STREAM_WINDOW_SZ 0x81fc -/* Secondary Streams Tile Offset */ -#define SEC_STREAM_TILE_OFF 0x821c -/* Secondary Stream 1 Opaque Overlay Control */ -#define SEC_STREAM_OPAQUE_OVERLAY 0x81dc - - -/* Stream Processor 2 */ - -/* Primary Stream 2 Frame Buffer Address 0 */ -#define PRI_STREAM2_FBUF_ADDR0 0x81b0 -/* Primary Stream 2 Frame Buffer Address 1 */ -#define PRI_STREAM2_FBUF_ADDR1 0x81b4 -/* Primary Stream 2 Stride */ -#define PRI_STREAM2_STRIDE 0x81b8 -/* Primary Stream 2 Frame Buffer Size */ -#define PRI_STREAM2_BUFFERSIZE 0x8218 - -/* Secondary Stream 2 Color/Chroma Key Control */ -#define SEC_STREAM2_CKEY_LOW 0x8188 -/* Secondary Stream 2 Chroma Key Upper Bound */ -#define SEC_STREAM2_CKEY_UPPER 0x818c -/* Secondary Stream 2 Horizontal Scaling */ -#define SEC_STREAM2_HSCALING 0x81a4 -/* Secondary Stream 2 Horizontal Scaling */ -#define SEC_STREAM2_VSCALING 0x8204 -/* Secondary Stream 2 Frame Buffer Size */ -#define SEC_STREAM2_BUFFERSIZE 0x81ac -/* Secondary Stream 2 Frame Buffer Address 0 */ -#define SEC_STREAM2_FBUF_ADDR0 0x81bc -/* Secondary Stream 2 Frame Buffer Address 1 */ -#define SEC_STREAM2_FBUF_ADDR1 0x81e0 -/* Secondary Stream 2 Frame Buffer Address 2 */ -#define SEC_STREAM2_FBUF_ADDR2 0x8208 -/* Multiple Buffer/LPB and Secondary Stream 2 Stride */ -#define SEC_STREAM2_STRIDE_LPB 0x81cc -/* Secondary Stream 2 Color conversion/Adjustment 1 */ -#define SEC_STREAM2_COLOR_CONVERT1 0x81f0 -/* Secondary Stream 2 Color conversion/Adjustment 2 */ -#define SEC_STREAM2_COLOR_CONVERT2 0x81f4 -/* Secondary Stream 2 Color conversion/Adjustment 3 */ -#define SEC_STREAM2_COLOR_CONVERT3 0x8200 -/* Secondary Stream 2 Window Start Coordinates */ -#define SEC_STREAM2_WINDOW_START 0x820c -/* Secondary Stream 2 Window Size */ -#define SEC_STREAM2_WINDOW_SZ 0x8210 -/* Secondary Stream 2 Opaque Overlay Control */ -#define SEC_STREAM2_OPAQUE_OVERLAY 0x8180 - - -/* savage 2000 */ -#define SEC_STREAM_COLOR_CONVERT0_2000 0x8198 -#define SEC_STREAM_COLOR_CONVERT1_2000 0x819c -#define SEC_STREAM_COLOR_CONVERT2_2000 0x81e0 -#define SEC_STREAM_COLOR_CONVERT3_2000 0x81e4 - -#define SUBSYS_STAT_REG 0x8504 - -#define SRC_BASE 0xa4d4 -#define DEST_BASE 0xa4d8 -#define CLIP_L_R 0xa4dc -#define CLIP_T_B 0xa4e0 -#define DEST_SRC_STR 0xa4e4 -#define MONO_PAT_0 0xa4e8 -#define MONO_PAT_1 0xa4ec - -/* Constants for CR69. */ - -#define CRT_ACTIVE 0x01 -#define LCD_ACTIVE 0x02 -#define TV_ACTIVE 0x04 -#define CRT_ATTACHED 0x10 -#define LCD_ATTACHED 0x20 -#define TV_ATTACHED 0x40 - - -/* - * reads from SUBSYS_STAT - */ -#define STATUS_WORD0 (INREG(0x48C00)) -#define ALT_STATUS_WORD0 (INREG(0x48C60)) -#define MAXLOOP 0xffffff -#define IN_SUBSYS_STAT() (INREG(SUBSYS_STAT_REG)) - -#define MAXFIFO 0x7f00 - -/* - * NOTE: don't remove 'VGAIN8(vgaCRIndex);'. - * If not present it will cause lockups on Savage4. - * Ask S3, why. - */ -/*#define VerticalRetraceWait() \ -{ \ - VGAIN8(0x3d0+4); \ - VGAOUT8(0x3d0+4, 0x17); \ - if (VGAIN8(0x3d0+5) & 0x80) { \ - while ((VGAIN8(0x3d0 + 0x0a) & 0x08) == 0x08) ; \ - while ((VGAIN8(0x3d0 + 0x0a) & 0x08) == 0x00) ; \ - } \ -} -*/ - -#define VerticalRetraceWait() \ -do { \ - VGAIN8(0x3d4); \ - VGAOUT8(0x3d4, 0x17); \ - if (VGAIN8(0x3d5) & 0x80) { \ - int i = 0x10000; \ - while ((VGAIN8(0x3da) & 0x08) == 0x08 && i--) ; \ - i = 0x10000; \ - while ((VGAIN8(0x3da) & 0x08) == 0x00 && i--) ; \ - } \ -} while (0) - - -#define I2C_REG 0xa0 -#define InI2CREG(a) \ -{ \ - VGAOUT8(0x3d0 + 4, I2C_REG); \ - a = VGAIN8(0x3d0 + 5); \ -} - -#define OutI2CREG(a) \ -{ \ - VGAOUT8(0x3d0 + 4, I2C_REG); \ - VGAOUT8(0x3d0 + 5, a); \ -} - -#define HZEXP_COMP_1 0x54 -#define HZEXP_BORDER 0x58 -#define HZEXP_FACTOR_IGA1 0x59 - -#define VTEXP_COMP_1 0x56 -#define VTEXP_BORDER 0x5a -#define VTEXP_FACTOR_IGA1 0x5b - -#define EC1_CENTER_ON 0x10 -#define EC1_EXPAND_ON 0x0c - -#define MODE_24 24 - -#if (MODE_24 == 32) -# define BYTES_PP24 4 -#else -# define BYTES_PP24 3 -#endif - -#define OVERLAY_DEPTH 16 - -#define STREAMS_MODE32 0x7 -#define STREAMS_MODE24 0x6 -#define STREAMS_MODE16 0x5 /* @@@ */ - - -#define DEPTH_BPP(depth) (depth == 24 ? (BYTES_PP24 << 3) : (depth + 7) & ~0x7) -#define DEPTH_2ND(depth) (depth > 8 ? depth\ - : OVERLAY_DEPTH) -#define SSTREAMS_MODE(bpp) (bpp > 16 ? (bpp > 24 ? STREAMS_MODE32 :\ - STREAMS_MODE24) : STREAMS_MODE16) - -#define HSCALING_Shift 0 -#define HSCALING_Mask (((1L << 16)-1) << HSCALING_Shift) -#define HSCALING(w0,w1) ((((unsigned int)(((double)w0/(double)w1) * (1 << 15))) \ - << HSCALING_Shift) \ - & HSCALING_Mask) - -#define VSCALING_Shift 0 -#define VSCALING_Mask (((1L << 20)-1) << VSCALING_Shift) -#define VSCALING(h0,h1) ((((unsigned int) (((double)h0/(double)h1) * (1 << 15))) \ - << VSCALING_Shift) \ - & VSCALING_Mask) - - -#endif /* _SAVAGE_REGS_H */
--- a/vidix/drivers/savage_vid.c Sat Mar 31 23:48:48 2007 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1475 +0,0 @@ -/* - Driver for S3 Savage Series - - Copyright (C) 2004 by Reza Jelveh - - Based on the X11 driver and nvidia vid - - Thanks to Alex Deucher for Support - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - - Changes: - 2004-11-09 - Initial version - - To Do: - -*/ - - -#include <errno.h> -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include <inttypes.h> -#include <unistd.h> -#include <math.h> - -#include "../vidix.h" -#include "../fourcc.h" -#include "../../libdha/libdha.h" -#include "../../libdha/pci_ids.h" -#include "../../libdha/pci_names.h" -#include "../../config.h" - -#include "savage_regs.h" - - -#define VF_STREAMS_ON 0x0001 -#define BASE_PAD 0xf -#define FRAMEBUFFER_SIZE 1024*2000*4 -/************************************** - S3 streams processor -**************************************/ - -#define EXT_MISC_CTRL2 0x67 - -/* New streams */ - -/* CR67[2] = 1 : enable stream 1 */ -#define ENABLE_STREAM1 0x04 -/* CR67[1] = 1 : enable stream 2 */ -#define ENABLE_STREAM2 0x02 -/* mask to clear CR67[2,1] */ -#define NO_STREAMS 0xF9 -/* CR67[3] = 1 : Mem-mapped regs */ -#define USE_MM_FOR_PRI_STREAM 0x08 - -#define HDM_SHIFT 16 -#define HDSCALE_4 (2 << HDM_SHIFT) -#define HDSCALE_8 (3 << HDM_SHIFT) -#define HDSCALE_16 (4 << HDM_SHIFT) -#define HDSCALE_32 (5 << HDM_SHIFT) -#define HDSCALE_64 (6 << HDM_SHIFT) - -/* Old Streams */ - -#define ENABLE_STREAMS_OLD 0x0c -#define NO_STREAMS_OLD 0xf3 -/* CR69[0] = 1 : Mem-mapped regs */ -#define USE_MM_FOR_PRI_STREAM_OLD 0x01 - -void SavageStreamsOn(void); - -/* - * There are two different streams engines used in the Savage line. - * The old engine is in the 3D, 4, Pro, and Twister. - * The new engine is in the 2000, MX, IX, and Super. - */ - - -/* streams registers for old engine */ -#define PSTREAM_CONTROL_REG 0x8180 -#define COL_CHROMA_KEY_CONTROL_REG 0x8184 -#define SSTREAM_CONTROL_REG 0x8190 -#define CHROMA_KEY_UPPER_BOUND_REG 0x8194 -#define SSTREAM_STRETCH_REG 0x8198 -#define COLOR_ADJUSTMENT_REG 0x819C -#define BLEND_CONTROL_REG 0x81A0 -#define PSTREAM_FBADDR0_REG 0x81C0 -#define PSTREAM_FBADDR1_REG 0x81C4 -#define PSTREAM_STRIDE_REG 0x81C8 -#define DOUBLE_BUFFER_REG 0x81CC -#define SSTREAM_FBADDR0_REG 0x81D0 -#define SSTREAM_FBADDR1_REG 0x81D4 -#define SSTREAM_STRIDE_REG 0x81D8 -#define SSTREAM_VSCALE_REG 0x81E0 -#define SSTREAM_VINITIAL_REG 0x81E4 -#define SSTREAM_LINES_REG 0x81E8 -#define STREAMS_FIFO_REG 0x81EC -#define PSTREAM_WINDOW_START_REG 0x81F0 -#define PSTREAM_WINDOW_SIZE_REG 0x81F4 -#define SSTREAM_WINDOW_START_REG 0x81F8 -#define SSTREAM_WINDOW_SIZE_REG 0x81FC -#define FIFO_CONTROL 0x8200 -#define PSTREAM_FBSIZE_REG 0x8300 -#define SSTREAM_FBSIZE_REG 0x8304 -#define SSTREAM_FBADDR2_REG 0x8308 - -#define OS_XY(x,y) (((x+1)<<16)|(y+1)) -#define OS_WH(x,y) (((x-1)<<16)|(y)) - -#define PCI_COMMAND_MEM 0x2 -#define MAX_FRAMES 3 -/** - * @brief Information on PCI device. - */ -pciinfo_t pci_info; - -/** - * @brief Unichrome driver colorkey settings. - */ -static vidix_grkey_t savage_grkey; - -static int frames[VID_PLAY_MAXFRAMES]; -uint8_t *vio; -uint8_t mclk_save[3]; - -#define outb(reg,val) OUTPORT8(reg,val) -#define inb(reg) INPORT8(reg) -#define outw(reg,val) OUTPORT16(reg,val) -#define inw(reg) INPORT16(reg) -#define outl(reg,val) OUTPORT32(reg,val) -#define inl(reg) INPORT32(reg) - - -/* - * PCI-Memory IO access macros. - */ -#define VID_WR08(p,i,val) (((uint8_t *)(p))[(i)]=(val)) -#define VID_RD08(p,i) (((uint8_t *)(p))[(i)]) - -#define VID_WR32(p,i,val) (((uint32_t *)(p))[(i)/4]=(val)) -#define VID_RD32(p,i) (((uint32_t *)(p))[(i)/4]) - -#ifndef USE_RMW_CYCLES -/* - * Can be used to inhibit READ-MODIFY-WRITE cycles. On by default. - */ - -#define MEM_BARRIER() __asm__ __volatile__ ("" : : : "memory") - -#undef VID_WR08 -#define VID_WR08(p,i,val) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]=(val); }) -#undef VID_RD08 -#define VID_RD08(p,i) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]; }) - -#undef VID_WR16 -#define VID_WR16(p,i,val) ({ MEM_BARRIER(); ((uint16_t *)(p))[(i)/2]=(val); }) -#undef VID_RD16 -#define VID_RD16(p,i) ({ MEM_BARRIER(); ((uint16_t *)(p))[(i)/2]; }) - -#undef VID_WR32 -#define VID_WR32(p,i,val) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]=(val); }) -#undef VID_RD32 -#define VID_RD32(p,i) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]; }) -#endif /* USE_RMW_CYCLES */ - -#define VID_AND32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)&(val)) -#define VID_OR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)|(val)) -#define VID_XOR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)^(val)) - - -/* from x driver */ - -#define VGAIN8(addr) VID_RD08(info->control_base+0x8000, addr) -#define VGAIN16(addr) VID_RD16(info->control_base+0x8000, addr) -#define VGAIN(addr) VID_RD32(info->control_base+0x8000, addr) - -#define VGAOUT8(addr,val) VID_WR08(info->control_base+0x8000, addr, val) -#define VGAOUT16(addr,val) VID_WR16(info->control_base+0x8000, addr, val) -#define VGAOUT(addr,val) VID_WR32(info->control_base+0x8000, addr, val) - -#define INREG(addr) VID_RD32(info->control_base, addr) -#define OUTREG(addr,val) VID_WR32(info->control_base, addr, val) -#define INREG8(addr) VID_RD08(info->control_base, addr) -#define OUTREG8(addr,val) VID_WR08(info->control_base, addr, val) -#define INREG16(addr) VID_RD16(info->control_base, addr) -#define OUTREG16(addr,val) VID_WR16(info->control_base, addr, val) - -#define ALIGN_TO(v, n) (((v) + (n-1)) & ~(n-1)) - - -void debugout(unsigned int addr, unsigned int val); - - -struct savage_chip { - volatile uint32_t *PMC; /* general control */ - volatile uint32_t *PME; /* multimedia port */ - volatile uint32_t *PFB; /* framebuffer control */ - volatile uint32_t *PVIDEO; /* overlay control */ - volatile uint8_t *PCIO; /* SVGA (CRTC, ATTR) registers */ - volatile uint8_t *PVIO; /* SVGA (MISC, GRAPH, SEQ) registers */ - volatile uint32_t *PRAMIN; /* instance memory */ - volatile uint32_t *PRAMHT; /* hash table */ - volatile uint32_t *PRAMFC; /* fifo context table */ - volatile uint32_t *PRAMRO; /* fifo runout table */ - volatile uint32_t *PFIFO; /* fifo control region */ - volatile uint32_t *FIFO; /* fifo channels (USER) */ - volatile uint32_t *PGRAPH; /* graphics engine */ - - int arch; /* compatible NV_ARCH_XX define */ - unsigned long fbsize; /* framebuffer size */ - void (* lock) (struct savage_chip *, int); -}; -typedef struct savage_chip savage_chip; - - -struct savage_info { - unsigned int use_colorkey; - unsigned int colorkey; /* saved xv colorkey*/ - unsigned int vidixcolorkey; /*currently used colorkey*/ - unsigned int depth; - unsigned int bpp; - unsigned int videoFlags; - unsigned int format; - unsigned int pitch; - unsigned int blendBase; - unsigned int lastKnownPitch; - unsigned int displayWidth, displayHeight; - unsigned int brightness,hue,saturation,contrast; - unsigned int src_w,src_h; - unsigned int drw_w,drw_h; /*scaled width && height*/ - unsigned int wx,wy; /*window x && y*/ - unsigned int screen_x; /*screen width*/ - unsigned int screen_y; /*screen height*/ - unsigned long buffer_size; /* size of the image buffer */ - struct savage_chip chip; /* NV architecture structure */ - void* video_base; /* virtual address of control region */ - void* control_base; /* virtual address of fb region */ - unsigned long picture_base; /* direct pointer to video picture */ - unsigned long picture_offset; /* offset of video picture in frame buffer */ -// struct savage_dma dma; /* DMA structure */ - unsigned int cur_frame; - unsigned int num_frames; /* number of buffers */ - int bps; /* bytes per line */ - void (*SavageWaitIdle) (); - void (*SavageWaitFifo) (int space); -}; -typedef struct savage_info savage_info; - - -static savage_info* info; - - -/** - * @brief Unichrome driver vidix capabilities. - */ -static vidix_capability_t savage_cap = { - "Savage/ProSavage/Twister vidix", - "Reza Jelveh <reza.jelveh@tuhh.de>", - TYPE_OUTPUT, - {0, 0, 0, 0}, - 4096, - 4096, - 4, - 4, - -1, - FLAG_UPSCALER | FLAG_DOWNSCALER, - VENDOR_S3_INC, - -1, - {0, 0, 0, 0} -}; - -struct savage_cards { - unsigned short chip_id; - unsigned short arch; -}; - - -static -unsigned int GetBlendForFourCC( int id ) -{ - switch( id ) { - case IMGFMT_YUY2: - case IMGFMT_YV12: - case IMGFMT_I420: - return 1; - case IMGFMT_Y211: - return 4; - case IMGFMT_RGB15: - return 3; - case IMGFMT_RGB16: - return 5; - default: - return 0; - } -} - -/** - * @brief list of card IDs compliant with the Unichrome driver . - */ -static struct savage_cards savage_card_ids[] = { - /*[ProSavage PN133] AGP4X VGA Controller (Twister)*/ - { PCI_CHIP_S3TWISTER_P, S3_PROSAVAGE }, - /*[ProSavage KN133] AGP4X VGA Controller (TwisterK)*/ - { PCI_CHIP_S3TWISTER_K, S3_PROSAVAGE }, - /*ProSavage DDR*/ - { PCI_CHIP_PROSAVAGE_DDR , S3_PROSAVAGE }, - /*[ProSavageDDR P4M266 K] */ - { PCI_CHIP_PROSAVAGE_DDRK , S3_PROSAVAGE }, -}; - -static void SavageSetColorOld(void) -{ - - - if( - (info->format == IMGFMT_RGB15) || - (info->format == IMGFMT_RGB16) - ) - { - OUTREG( COLOR_ADJUSTMENT_REG, 0 ); - } - else - { - /* Change 0..255 into 0..15 */ - long sat = info->saturation * 16 / 256; - double hue = info->hue * 0.017453292; - unsigned long hs1 = ((long)(sat * cos(hue))) & 0x1f; - unsigned long hs2 = ((long)(sat * sin(hue))) & 0x1f; - - OUTREG( COLOR_ADJUSTMENT_REG, - 0x80008000 | - (info->brightness + 128) | - ((info->contrast & 0xf8) << (12-7)) | - (hs1 << 16) | - (hs2 << 24) - ); - debugout( COLOR_ADJUSTMENT_REG, - 0x80008000 | - (info->brightness + 128) | - ((info->contrast & 0xf8) << (12-7)) | - (hs1 << 16) | - (hs2 << 24) - ); - - } -} - -static void SavageSetColorKeyOld(void) -{ - int red, green, blue; - - /* Here, we reset the colorkey and all the controls. */ - - red = (info->vidixcolorkey & 0x00FF0000) >> 16; - green = (info->vidixcolorkey & 0x0000FF00) >> 8; - blue = info->vidixcolorkey & 0x000000FF; - - if( !info->vidixcolorkey ) { - printf("SavageSetColorKey disabling colorkey\n"); - OUTREG( COL_CHROMA_KEY_CONTROL_REG, 0 ); - OUTREG( CHROMA_KEY_UPPER_BOUND_REG, 0 ); - OUTREG( BLEND_CONTROL_REG, 0 ); - } - else { - switch (info->depth) { - // FIXME: isnt fixed yet - case 8: - OUTREG( COL_CHROMA_KEY_CONTROL_REG, - 0x37000000 | (info->vidixcolorkey & 0xFF) ); - OUTREG( CHROMA_KEY_UPPER_BOUND_REG, - 0x00000000 | (info->vidixcolorkey & 0xFF) ); - break; - case 15: - /* 15 bpp 555 */ - red&=0x1f; - green&=0x1f; - blue&=0x1f; - OUTREG( COL_CHROMA_KEY_CONTROL_REG, - 0x05000000 | (red<<19) | (green<<11) | (blue<<3) ); - OUTREG( CHROMA_KEY_UPPER_BOUND_REG, - 0x00000000 | (red<<19) | (green<<11) | (blue<<3) ); - break; - case 16: - /* 16 bpp 565 */ - red&=0x1f; - green&=0x3f; - blue&=0x1f; - OUTREG( COL_CHROMA_KEY_CONTROL_REG, - 0x16000000 | (red<<19) | (green<<10) | (blue<<3) ); - OUTREG( CHROMA_KEY_UPPER_BOUND_REG, - 0x00020002 | (red<<19) | (green<<10) | (blue<<3) ); - break; - case 24: - /* 24 bpp 888 */ - OUTREG( COL_CHROMA_KEY_CONTROL_REG, - 0x17000000 | (red<<16) | (green<<8) | (blue) ); - OUTREG( CHROMA_KEY_UPPER_BOUND_REG, - 0x00000000 | (red<<16) | (green<<8) | (blue) ); - break; - } - - /* We use destination colorkey */ - OUTREG( BLEND_CONTROL_REG, 0x05000000 ); - } -} - - -static void -SavageDisplayVideoOld(void) -{ - int vgaCRIndex, vgaCRReg, vgaIOBase; - unsigned int ssControl; - int cr92; - - - vgaIOBase = 0x3d0; - vgaCRIndex = vgaIOBase + 4; - vgaCRReg = vgaIOBase + 5; - -// if( psav->videoFourCC != id ) -// SavageStreamsOff(pScrn); - - if( !info->videoFlags & VF_STREAMS_ON ) - { - SavageStreamsOn(); - // SavageResetVideo(); - SavageSetColorOld(); - SavageSetColorKeyOld(); - } - - - - - /* Set surface format. */ - - OUTREG(SSTREAM_CONTROL_REG,GetBlendForFourCC(info->format) << 24 | info->src_w); - - debugout(SSTREAM_CONTROL_REG,GetBlendForFourCC(info->format) << 24 | info->src_w); - - /* Calculate horizontal scale factor. */ - - //FIXME: enable scaling - OUTREG(SSTREAM_STRETCH_REG, (info->src_w << 15) / info->drw_w ); -// debugout(SSTREAM_STRETCH_REG, 1 << 15); - - OUTREG(SSTREAM_LINES_REG, info->src_h ); - debugout(SSTREAM_LINES_REG, info->src_h ); - - - OUTREG(SSTREAM_VINITIAL_REG, 0 ); - debugout(SSTREAM_VINITIAL_REG, 0 ); - /* Calculate vertical scale factor. */ - -// OUTREG(SSTREAM_VSCALE_REG, 1 << 15); - OUTREG(SSTREAM_VSCALE_REG, VSCALING(info->src_h,info->drw_h) ); - debugout(SSTREAM_VSCALE_REG, VSCALING(info->src_h,info->drw_h) ); -// OUTREG(SSTREAM_VSCALE_REG, (info->src_h << 15) / info->drw_h ); - - /* Set surface location and stride. */ - - OUTREG(SSTREAM_FBADDR0_REG, info->picture_offset ); - debugout(SSTREAM_FBADDR0_REG, info->picture_offset ); - - OUTREG(SSTREAM_FBADDR1_REG, 0 ); - debugout(SSTREAM_FBADDR1_REG, 0 ); - - OUTREG(SSTREAM_STRIDE_REG, info->pitch ); - debugout(SSTREAM_STRIDE_REG, info->pitch ); - - OUTREG(SSTREAM_WINDOW_START_REG, OS_XY(info->wx, info->wy) ); - debugout(SSTREAM_WINDOW_START_REG, OS_XY(info->wx, info->wy) ); - OUTREG(SSTREAM_WINDOW_SIZE_REG, OS_WH(info->drw_w, info->drw_h) ); - debugout(SSTREAM_WINDOW_SIZE_REG, OS_WH(info->drw_w, info->drw_h) ); - - - - ssControl = 0; - - if( info->src_w > (info->drw_w << 1) ) - { - /* BUGBUG shouldn't this be >=? */ - if( info->src_w <= (info->drw_w << 2) ) - ssControl |= HDSCALE_4; - else if( info->src_w > (info->drw_w << 3) ) - ssControl |= HDSCALE_8; - else if( info->src_w > (info->drw_w << 4) ) - ssControl |= HDSCALE_16; - else if( info->src_w > (info->drw_w << 5) ) - ssControl |= HDSCALE_32; - else if( info->src_w > (info->drw_w << 6) ) - ssControl |= HDSCALE_64; - } - - ssControl |= info->src_w; - ssControl |= (1 << 24); - - //FIXME: enable scaling - OUTREG(SSTREAM_CONTROL_REG, ssControl); - debugout(SSTREAM_CONTROL_REG, ssControl); - - // FIXME: this should actually be enabled - - info->pitch = (info->pitch + 7) / 8; - VGAOUT8(vgaCRIndex, 0x92); - cr92 = VGAIN8(vgaCRReg); - VGAOUT8(vgaCRReg, (cr92 & 0x40) | (info->pitch >> 8) | 0x80); - VGAOUT8(vgaCRIndex, 0x93); - VGAOUT8(vgaCRReg, info->pitch); - OUTREG(STREAMS_FIFO_REG, 2 | 25 << 5 | 32 << 11); - - - - -} - -static void SavageInitStreamsOld(void) -{ - /*unsigned long jDelta;*/ - unsigned long format = 0; - - /* - * For the OLD streams engine, several of these registers - * cannot be touched unless streams are on. Seems backwards to me; - * I'd want to set 'em up, then cut 'em loose. - */ - - - /*jDelta = pScrn->displayWidth * (pScrn->bitsPerPixel + 7) / 8;*/ - switch( info->depth ) { - case 8: format = 0 << 24; break; - case 15: format = 3 << 24; break; - case 16: format = 5 << 24; break; - case 24: format = 7 << 24; break; - } -#warning enable this again - OUTREG(PSTREAM_FBSIZE_REG, - info->screen_y * info->screen_x * (info->bpp >> 3)); - - OUTREG( PSTREAM_WINDOW_START_REG, OS_XY(0,0) ); - OUTREG( PSTREAM_WINDOW_SIZE_REG, OS_WH(info->screen_x, info->screen_y) ); - OUTREG( PSTREAM_FBADDR1_REG, 0 ); - /*OUTREG( PSTREAM_STRIDE_REG, jDelta );*/ - OUTREG( PSTREAM_CONTROL_REG, format ); - OUTREG( PSTREAM_FBADDR0_REG, 0 ); - - /*OUTREG( PSTREAM_FBSIZE_REG, jDelta * pScrn->virtualY >> 3 );*/ - - OUTREG( COL_CHROMA_KEY_CONTROL_REG, 0 ); - OUTREG( SSTREAM_CONTROL_REG, 0 ); - OUTREG( CHROMA_KEY_UPPER_BOUND_REG, 0 ); - OUTREG( SSTREAM_STRETCH_REG, 0 ); - OUTREG( COLOR_ADJUSTMENT_REG, 0 ); - OUTREG( BLEND_CONTROL_REG, 1 << 24 ); - OUTREG( DOUBLE_BUFFER_REG, 0 ); - OUTREG( SSTREAM_FBADDR0_REG, 0 ); - OUTREG( SSTREAM_FBADDR1_REG, 0 ); - OUTREG( SSTREAM_FBADDR2_REG, 0 ); - OUTREG( SSTREAM_FBSIZE_REG, 0 ); - OUTREG( SSTREAM_STRIDE_REG, 0 ); - OUTREG( SSTREAM_VSCALE_REG, 0 ); - OUTREG( SSTREAM_LINES_REG, 0 ); - OUTREG( SSTREAM_VINITIAL_REG, 0 ); -#warning is this needed? - OUTREG( SSTREAM_WINDOW_START_REG, OS_XY(0xfffe, 0xfffe) ); - OUTREG( SSTREAM_WINDOW_SIZE_REG, OS_WH(10,2) ); - -} - -void -SavageStreamsOn(void) -{ - unsigned char jStreamsControl; - unsigned short vgaCRIndex = 0x3d0 + 4; - unsigned short vgaCRReg = 0x3d0 + 5; - -// xf86ErrorFVerb(STREAMS_TRACE, "SavageStreamsOn\n" ); - - /* Sequence stolen from streams.c in M7 NT driver */ - - - enable_app_io (); - - /* Unlock extended registers. */ - - /* FIXME: it looks like mmaped io is broken with vgaout16 */ - VGAOUT16(vgaCRIndex, 0x4838 ); - VGAOUT16(vgaCRIndex, 0xa039); - VGAOUT16(0x3c4, 0x0608); - - - - VGAOUT8( vgaCRIndex, EXT_MISC_CTRL2 ); - - if( S3_SAVAGE_MOBILE_SERIES(info->chip.arch) ) - { -// SavageInitStreamsNew( pScrn ); - - jStreamsControl = VGAIN8( vgaCRReg ) | ENABLE_STREAM1; - - /* Wait for VBLANK. */ - VerticalRetraceWait(); - /* Fire up streams! */ - VGAOUT16( vgaCRIndex, (jStreamsControl << 8) | EXT_MISC_CTRL2 ); - /* These values specify brightness, contrast, saturation and hue. */ - OUTREG( SEC_STREAM_COLOR_CONVERT1, 0x0000C892 ); - OUTREG( SEC_STREAM_COLOR_CONVERT2, 0x00039F9A ); - OUTREG( SEC_STREAM_COLOR_CONVERT3, 0x01F1547E ); - } - else if (info->chip.arch == S3_SAVAGE2000) - { -// SavageInitStreams2000( pScrn ); - - jStreamsControl = VGAIN8( vgaCRReg ) | ENABLE_STREAM1; - - /* Wait for VBLANK. */ - VerticalRetraceWait(); - /* Fire up streams! */ - VGAOUT16( vgaCRIndex, (jStreamsControl << 8) | EXT_MISC_CTRL2 ); - /* These values specify brightness, contrast, saturation and hue. */ - OUTREG( SEC_STREAM_COLOR_CONVERT0_2000, 0x0000C892 ); - OUTREG( SEC_STREAM_COLOR_CONVERT1_2000, 0x00033400 ); - OUTREG( SEC_STREAM_COLOR_CONVERT2_2000, 0x000001CF ); - OUTREG( SEC_STREAM_COLOR_CONVERT3_2000, 0x01F1547E ); - } - else - { - jStreamsControl = VGAIN8( vgaCRReg ) | ENABLE_STREAMS_OLD; - - /* Wait for VBLANK. */ - - VerticalRetraceWait(); - - /* Fire up streams! */ - - VGAOUT16( vgaCRIndex, (jStreamsControl << 8) | EXT_MISC_CTRL2 ); - - SavageInitStreamsOld( ); - } - - /* Wait for VBLANK. */ - - VerticalRetraceWait(); - - /* Turn on secondary stream TV flicker filter, once we support TV. */ - - /* SR70 |= 0x10 */ - - info->videoFlags |= VF_STREAMS_ON; - -} - - - - -static void savage_getscreenproperties(struct savage_info *info){ - unsigned char bpp=0; - uint32_t width=0; - - uint32_t vgaIOBase, vgaCRIndex, vgaCRReg; - - vgaIOBase = 0x3d0; - vgaCRIndex = vgaIOBase + 4; - vgaCRReg = vgaIOBase + 5; - - - /* a little reversed from x driver source code */ - VGAOUT8(vgaCRIndex, 0x67); - bpp = VGAIN8(vgaCRReg); - - - switch (bpp&0xf0) { - case 0x00: - case 0x10: - info->depth=8; - info->bpp=8; - break; - case 0x20: - case 0x30: - info->depth=15; - info->bpp=16; - break; - case 0x40: - case 0x50: - info->depth=16; - info->bpp=16; - break; - case 0x70: - case 0xd0: - info->depth=24; - info->bpp=32; - break; - - - } - - - VGAOUT8(vgaCRIndex, 0x1); - info->screen_x = (1 + VGAIN8(vgaCRReg)) <<3; - /*get screen height*/ - /* get first 8 bits in VT_DISPLAY_END*/ - VGAOUT8(0x03D4, 0x12); - info->screen_y = VGAIN8(0x03D5); - VGAOUT8(0x03D4,0x07); - /* get 9th bit in CRTC_OVERFLOW*/ - info->screen_y |= (VGAIN8(0x03D5) &0x02)<<7; - /* and the 10th in CRTC_OVERFLOW*/ - info->screen_y |=(VGAIN8(0x03D5) &0x40)<<3; - ++info->screen_y; - - printf("screen_x = %d, screen_y = %d, bpp = %d\n",info->screen_x,info->screen_y,info->bpp); -} - - -static void SavageStreamsOff(void) -{ - unsigned char jStreamsControl; - unsigned short vgaCRIndex = 0x3d0 + 4; - unsigned short vgaCRReg = 0x3d0 + 5; - - - /* Unlock extended registers. */ - - VGAOUT16(vgaCRIndex, 0x4838); - VGAOUT16(vgaCRIndex, 0xa039); - VGAOUT16(0x3c4, 0x0608); - - VGAOUT8( vgaCRIndex, EXT_MISC_CTRL2 ); - if( S3_SAVAGE_MOBILE_SERIES(info->chip.arch) || - (info->chip.arch == S3_SUPERSAVAGE) || - (info->chip.arch == S3_SAVAGE2000) ) - jStreamsControl = VGAIN8( vgaCRReg ) & NO_STREAMS; - else - jStreamsControl = VGAIN8( vgaCRReg ) & NO_STREAMS_OLD; - - /* Wait for VBLANK. */ - - VerticalRetraceWait(); - - /* Kill streams. */ - - VGAOUT16(vgaCRIndex, (jStreamsControl << 8) | EXT_MISC_CTRL2 ); - - VGAOUT16(vgaCRIndex, 0x0093 ); - VGAOUT8( vgaCRIndex, 0x92 ); - VGAOUT8( vgaCRReg, VGAIN8(vgaCRReg) & 0x40 ); - - info->videoFlags &= ~VF_STREAMS_ON; -} - - -/** - * @brief Check age of driver. - * - * @return vidix version number. - */ -unsigned int -vixGetVersion (void) -{ - return (VIDIX_VERSION); -} - -/** - * @brief Find chip index in Unichrome compliant devices list. - * - * @param chip_id PCI device ID. - * - * @returns index position in savage_card_ids if successful. - * -1 if chip_id is not a compliant chipset ID. - */ - -static int find_chip(unsigned chip_id){ - unsigned i; - for(i = 0;i < sizeof(savage_card_ids)/sizeof(struct savage_cards);i++) - { - if(chip_id == savage_card_ids[i].chip_id)return i; - } - return -1; -} - -/** - * @brief Probe hardware to find some useable chipset. - * - * @param verbose specifies verbose level. - * @param force specifies force mode : driver should ignore - * device_id (danger but useful for new devices) - * - * @returns 0 if it can handle something in PC. - * a negative error code otherwise. - */ - -int vixProbe(int verbose, int force){ - pciinfo_t lst[MAX_PCI_DEVICES]; - unsigned i,num_pci; - int err; - - if (force) - printf("[savage_vid]: warning: forcing not supported yet!\n"); - err = pci_scan(lst,&num_pci); - if(err){ - printf("[savage_vid] Error occurred during pci scan: %s\n",strerror(err)); - return err; - } - else { - err = ENXIO; - for(i=0; i < num_pci; i++){ - if(lst[i].vendor == VENDOR_S3_INC) { - int idx; - const char *dname; - idx = find_chip(lst[i].device); - if(idx == -1) - continue; - dname = pci_device_name(lst[i].vendor, lst[i].device); - dname = dname ? dname : "Unknown chip"; - printf("[savage_vid] Found chip: %s\n", dname); - // FIXME: whats wrong here? - if ((lst[i].command & PCI_COMMAND_IO ) == 0){ - printf("[savage_vid] Device is disabled, ignoring\n"); - continue; - } - savage_cap.device_id = lst[i].device; - err = 0; - memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); - break; - } - } - } - if(err && verbose) printf("[savage_vid] Can't find chip\n"); - return err; -} - -/** - * @brief Initializes driver. - * - * @returns 0 if ok. - * a negative error code otherwise. - */ -int -vixInit (void) -{ - int mtrr; - unsigned char config1, m, n, n1, n2, sr8, cr3f, cr66 = 0, tmp; - - static unsigned char RamSavage3D[] = { 8, 4, 4, 2 }; - static unsigned char RamSavage4[] = { 2, 4, 8, 12, 16, 32, 64, 32 }; - static unsigned char RamSavageMX[] = { 2, 8, 4, 16, 8, 16, 4, 16 }; - static unsigned char RamSavageNB[] = { 0, 2, 4, 8, 16, 32, 16, 2 }; - - int videoRam, videoRambytes; - - uint32_t vgaIOBase, vgaCRIndex, vgaCRReg ; - - unsigned char val; - - vgaIOBase = 0x3d0; - vgaCRIndex = vgaIOBase + 4; - vgaCRReg = vgaIOBase + 5; - - fprintf(stderr, "vixInit enter \n"); -// //getc(stdin); - - info = calloc(1,sizeof(savage_info)); - - - /* need this if we want direct outb and inb access? */ - enable_app_io (); - - /* 12mb + 32kb ? */ - /* allocate some space for control registers */ - info->chip.arch = savage_card_ids[find_chip(pci_info.device)].arch; - - if (info->chip.arch == S3_SAVAGE3D) { - info->control_base = map_phys_mem(pci_info.base0+SAVAGE_NEWMMIO_REGBASE_S3, SAVAGE_NEWMMIO_REGSIZE); - } - else { - info->control_base = map_phys_mem(pci_info.base0+SAVAGE_NEWMMIO_REGBASE_S4, SAVAGE_NEWMMIO_REGSIZE); - } - -// info->chip.PCIO = (uint8_t *) (info->control_base + SAVAGE_NEWMMIO_VGABASE); - - // FIXME: enable mmio? - val = VGAIN8 (0x3c3); - VGAOUT8 (0x3c3, val | 0x01); - val = VGAIN8 (0x3cc); - VGAOUT8 (0x3c2, val | 0x01); - - if (info->chip.arch >= S3_SAVAGE4) - { - VGAOUT8 (0x3d4, 0x40); - val = VGAIN8 (0x3d5); - VGAOUT8 (0x3d5, val | 1); - } - - - - /* unprotect CRTC[0-7] */ - VGAOUT8(vgaCRIndex, 0x11); - tmp = VGAIN8(vgaCRReg); -// printf("$########## tmp = %d\n",tmp); - VGAOUT8(vgaCRReg, tmp & 0x7f); - - - /* unlock extended regs */ - VGAOUT16(vgaCRIndex, 0x4838); - VGAOUT16(vgaCRIndex, 0xa039); - VGAOUT16(0x3c4, 0x0608); - - VGAOUT8(vgaCRIndex, 0x40); - tmp = VGAIN8(vgaCRReg); - VGAOUT8(vgaCRReg, tmp & ~0x01); - - /* unlock sys regs */ - VGAOUT8(vgaCRIndex, 0x38); - VGAOUT8(vgaCRReg, 0x48); - - /* Unlock system registers. */ - VGAOUT16(vgaCRIndex, 0x4838); - - /* Next go on to detect amount of installed ram */ - - VGAOUT8(vgaCRIndex, 0x36); /* for register CR36 (CONFG_REG1), */ - config1 = VGAIN8(vgaCRReg); /* get amount of vram installed */ - - - switch( info->chip.arch ) { - case S3_SAVAGE3D: - videoRam = RamSavage3D[ (config1 & 0xC0) >> 6 ] * 1024; - break; - - case S3_SAVAGE4: - /* - * The Savage4 has one ugly special case to consider. On - * systems with 4 banks of 2Mx32 SDRAM, the BIOS says 4MB - * when it really means 8MB. Why do it the same when you - * can do it different... - */ - VGAOUT8(0x3d4, 0x68); /* memory control 1 */ - if( (VGAIN8(0x3d5) & 0xC0) == (0x01 << 6) ) - RamSavage4[1] = 8; - - /*FALLTHROUGH*/ - - case S3_SAVAGE2000: - videoRam = RamSavage4[ (config1 & 0xE0) >> 5 ] * 1024; - break; - - case S3_SAVAGE_MX: - videoRam = RamSavageMX[ (config1 & 0x0E) >> 1 ] * 1024; - break; - - case S3_PROSAVAGE: - videoRam = RamSavageNB[ (config1 & 0xE0) >> 5 ] * 1024; - break; - - default: - /* How did we get here? */ - videoRam = 0; - break; - } - - - printf("###### videoRam = %d\n",videoRam); - info->chip.fbsize = videoRam * 1024; - - - /* reset graphics engine to avoid memory corruption */ -/* VGAOUT8 (0x3d4, 0x66); - cr66 = VGAIN8 (0x3d5); - VGAOUT8 (0x3d5, cr66 | 0x02); - udelay (10000); - - VGAOUT8 (0x3d4, 0x66); - VGAOUT8 (0x3d5, cr66 & ~0x02); /* clear reset flag */ - /* udelay (10000); */ - - /* This maps framebuffer @6MB, thus 2MB are left for video. */ - if (info->chip.arch == S3_SAVAGE3D) { - info->video_base = map_phys_mem(pci_info.base0, info->chip.fbsize); - info->picture_offset = 1024*768* 4 * ((info->chip.fbsize > 4194304)?2:1); - } - else { - info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize); - info->picture_offset = info->chip.fbsize - FRAMEBUFFER_SIZE; -// info->picture_offset = 1024*1024* 4 * 2; - } - if ( info->video_base < 0 ){ - printf("errno = %s\n", strerror(errno)); - return -1; - } - - - info->picture_base = (uint32_t) info->video_base + info->picture_offset; - - if ( info->chip.arch == S3_SAVAGE3D ){ - mtrr = mtrr_set_type(pci_info.base0, info->chip.fbsize, MTRR_TYPE_WRCOMB); - } - else{ - mtrr = mtrr_set_type(pci_info.base1, info->chip.fbsize, MTRR_TYPE_WRCOMB); - } - - if (mtrr!= 0) - printf("[savage_vid] unable to setup MTRR: %s\n", strerror(mtrr)); - else - printf("[savage_vid] MTRR set up\n"); - - /* This may trash your screen for resolutions greater than 1024x768, sorry. */ - - - savage_getscreenproperties(info); -// return -1; - info->videoFlags = 0; - - SavageStreamsOn(); - //getc(stdin); - //FIXME ADD - return 0; -} - -/** - * @brief Destroys driver. - */ -void -vixDestroy (void) -{ - unmap_phys_mem(info->video_base, info->chip.fbsize); - unmap_phys_mem(info->control_base, SAVAGE_NEWMMIO_REGSIZE); - //FIXME ADD -} - -/** - * @brief Get chipset's hardware capabilities. - * - * @param to Pointer to the vidix_capability_t structure to be filled. - * - * @returns 0. - */ -int -vixGetCapability (vidix_capability_t * to) -{ - memcpy (to, &savage_cap, sizeof (vidix_capability_t)); - return 0; -} - -/** - * @brief Report if the video FourCC is supported by hardware. - * - * @param fourcc input image format. - * - * @returns 1 if the fourcc is supported. - * 0 otherwise. - */ -static int -is_supported_fourcc (uint32_t fourcc) -{ - switch (fourcc) - { -//FIXME: YV12 isnt working properly yet -// case IMGFMT_YV12: -// case IMGFMT_I420: - case IMGFMT_UYVY: - case IMGFMT_YVYU: - case IMGFMT_YUY2: - case IMGFMT_RGB15: - case IMGFMT_RGB16: -// case IMGFMT_BGR32: - return 1; - default: - return 0; - } -} - -/** - * @brief Try to configure video memory for given fourcc. - * - * @param to Pointer to the vidix_fourcc_t structure to be filled. - * - * @returns 0 if ok. - * errno otherwise. - */ -int -vixQueryFourcc (vidix_fourcc_t * to) -{ - if (is_supported_fourcc (to->fourcc)) - { - to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | - VID_DEPTH_4BPP | VID_DEPTH_8BPP | - VID_DEPTH_12BPP | VID_DEPTH_15BPP | - VID_DEPTH_16BPP | VID_DEPTH_24BPP | VID_DEPTH_32BPP; - to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; - return 0; - } - else - to->depth = to->flags = 0; - - return ENOSYS; -} - -/** - * @brief Get the GrKeys - * - * @param grkey Pointer to the vidix_grkey_t structure to be filled by driver. - * - * @return 0. - */ -/*int -vixGetGrKeys (vidix_grkey_t * grkey) -{ - -// if(info->d_width && info->d_height)savage_overlay_start(info,0); - - return (0); -} - * */ - -/** - * @brief Set the GrKeys - * - * @param grkey Colorkey to be set. - * - * @return 0. - */ -int -vixSetGrKeys (const vidix_grkey_t * grkey) -{ - if (grkey->ckey.op == CKEY_FALSE) - { - info->use_colorkey = 0; - info->vidixcolorkey=0; - printf("[savage_vid] colorkeying disabled\n"); - } - else { - info->use_colorkey = 1; - info->vidixcolorkey = ((grkey->ckey.red<<16)|(grkey->ckey.green<<8)|grkey->ckey.blue); - - printf("[savage_vid] set colorkey 0x%x\n",info->vidixcolorkey); - } - //FIXME: freezes if streams arent enabled - SavageSetColorKeyOld(); - return (0); -} - -/** - * @brief Unichrome driver equalizer capabilities. - */ -vidix_video_eq_t equal = { - VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION | VEQ_CAP_HUE, - 300, 100, 0, 0, 0, 0, 0, 0 -}; - - -/** - * @brief Get the equalizer capabilities. - * - * @param eq Pointer to the vidix_video_eq_t structure to be filled by driver. - * - * @return 0. - */ -int -vixPlaybackGetEq (vidix_video_eq_t * eq) -{ - memcpy (eq, &equal, sizeof (vidix_video_eq_t)); - return 0; -} - -/** - * @brief Set the equalizer capabilities for color correction - * - * @param eq equalizer capabilities to be set. - * - * @return 0. - */ -int -vixPlaybackSetEq (const vidix_video_eq_t * eq) -{ - return 0; -} - -/** - * @brief Y, U, V offsets. - */ -static int YOffs, UOffs, VOffs; - -/** - * @brief Configure driver for playback. Driver should prepare BES. - * - * @param info configuration description for playback. - * - * @returns 0 in case of success. - * -1 otherwise. - */ -int -vixConfigPlayback (vidix_playback_t * vinfo) -{ - int uv_size, swap_uv; - unsigned int i; - int extfifo_on; - int srcPitch,srcPitch2; - - /* Overlay register settings */ - uint32_t win_start, win_end; - uint32_t zoom, mini; - uint32_t dcount, falign, qwfetch; - uint32_t y_start, u_start, v_start; - uint32_t v_ctrl, fifo_ctrl; - - if (!is_supported_fourcc (vinfo->fourcc)) - return -1; - - - - info->src_w = vinfo->src.w; - info->src_h = vinfo->src.h; - - info->drw_w = vinfo->dest.w; - info->drw_h = vinfo->dest.h; - - info->wx = vinfo->dest.x; - info->wy = vinfo->dest.y; - info->format = vinfo->fourcc; - - info->lastKnownPitch = 0; - info->brightness = 0; - info->contrast = 128; - info->saturation = 128; - info->hue = 0; - - - vinfo->dga_addr=(void*)(info->picture_base); - - - vinfo->offset.y = 0; - vinfo->offset.v = 0; - vinfo->offset.u = 0; - - vinfo->dest.pitch.y = 32; - vinfo->dest.pitch.u = 32; - vinfo->dest.pitch.v = 32; - // vinfo->dest.pitch.u = 0; - // vinfo->dest.pitch.v = 0; - - - info->pitch = ((info->src_w << 1) + 15) & ~15; - - swap_uv = 0; - switch (vinfo->fourcc) - { - case IMGFMT_YUY2: - case IMGFMT_UYVY: - - info->pitch = ((info->src_w << 1) + (vinfo->dest.pitch.y-1)) & ~(vinfo->dest.pitch.y-1); - - info->pitch = info->src_w << 1; - info->pitch = ALIGN_TO (info->src_w << 1, 32); - uv_size = 0; - break; - case IMGFMT_YV12: - swap_uv = 1; - - - - /* - srcPitch = (info->src_w + 3) & ~3; - vinfo->offset.u = srcPitch * info->src_h; - srcPitch2 = ((info->src_w >> 1) + 3) & ~3; - vinfo->offset.v = (srcPitch2 * (info->src_h >> 1)) + vinfo->offset.v; - - vinfo->dest.pitch.y=srcPitch ; - vinfo->dest.pitch.v=srcPitch2 ; - vinfo->dest.pitch.u=srcPitch2 ; - */ - - - info->pitch = ALIGN_TO (info->src_w, 32); - uv_size = (info->pitch >> 1) * (info->src_h >> 1); - - vinfo->offset.y = 0; - vinfo->offset.v = vinfo->offset.y + info->pitch * info->src_h; - vinfo->offset.u = vinfo->offset.v + uv_size; - vinfo->frame_size = vinfo->offset.u + uv_size; -/* YOffs = info->offset.y; - UOffs = (swap_uv ? vinfo->offset.v : vinfo->offset.u); - VOffs = (swap_uv ? vinfo->offset.u : vinfo->offset.v); - */ -// vinfo->offset.y = info->src_w; -// vinfo->offset.v = vinfo->offset.y + info->src_w /2 * info->src_h; -// vinfo->offset.u = vinfo->offset.v + (info->src_w >> 1) * (info->src_h >> 1) ; - - break; - } - info->pitch |= ((info->pitch >> 1) << 16); - - vinfo->frame_size = info->pitch * info->src_h; - - printf("$#### destination pitch = %u\n", info->pitch&0xffff); - - - - - info->buffer_size = vinfo->frame_size; - info->num_frames = vinfo->num_frames= (info->chip.fbsize - info->picture_offset)/vinfo->frame_size; - if(vinfo->num_frames > MAX_FRAMES)vinfo->num_frames = MAX_FRAMES; -// vinfo->num_frames = 1; -// printf("[nvidia_vid] Number of frames %i\n",vinfo->num_frames); - for(i=0;i <vinfo->num_frames;i++)vinfo->offsets[i] = vinfo->frame_size*i; - - return 0; -} - -/** - * @brief Set playback on : driver should activate BES on this call. - * - * @return 0. - */ -int -vixPlaybackOn (void) -{ - // FIXME: enable - SavageDisplayVideoOld(); -//FIXME ADD - return 0; -} - -/** - * @brief Set playback off : driver should deactivate BES on this call. - * - * @return 0. - */ -int -vixPlaybackOff (void) -{ - // otherwise we wont disable streams properly in new xorg - // FIXME: shouldnt this be enabled? -// SavageStreamsOn(); - SavageStreamsOff(); -// info->vidixcolorkey=0x0; - -// OUTREG( SSTREAM_WINDOW_START_REG, OS_XY(0xfffe, 0xfffe) ); -// SavageSetColorKeyOld(); -//FIXME ADD - return 0; -} - -/** - * @brief Driver should prepare and activate corresponded frame. - * - * @param frame the frame index. - * - * @return 0. - * - * @note This function is used only for double and triple buffering - * and never used for single buffering playback. - */ -#if 0 -int -vixPlaybackFrameSelect (unsigned int frame) -{ -////FIXME ADD -// savage_overlay_start(info, frame); - //if (info->num_frames >= 1) -// info->cur_frame = frame//(frame+1)%info->num_frames; -// -// savage4_waitidle(info); - - printf("vixPlaybackFrameSelect Leave\n" ); - // FIXME: does this work to avoid tearing? -// VerticalRetraceWait(); - - return 0; -} - -#endif - - - -void debugout(unsigned int addr, unsigned int val){ - return ; - switch ( addr ){ - case PSTREAM_CONTROL_REG: - fprintf(stderr,"PSTREAM_CONTROL_REG"); - break; - case COL_CHROMA_KEY_CONTROL_REG: - fprintf(stderr,"COL_CHROMA_KEY_CONTROL_REG"); - break; - case SSTREAM_CONTROL_REG: - fprintf(stderr,"SSTREAM_CONTROL_REG"); - break; - case CHROMA_KEY_UPPER_BOUND_REG: - fprintf(stderr,"CHROMA_KEY_UPPER_BOUND_REG"); - break; - case SSTREAM_STRETCH_REG: - fprintf(stderr,"SSTREAM_STRETCH_REG"); - break; - case COLOR_ADJUSTMENT_REG: - fprintf(stderr,"COLOR_ADJUSTMENT_REG"); - break; - case BLEND_CONTROL_REG: - fprintf(stderr,"BLEND_CONTROL_REG"); - break; - case PSTREAM_FBADDR0_REG: - fprintf(stderr,"PSTREAM_FBADDR0_REG"); - break; - case PSTREAM_FBADDR1_REG: - fprintf(stderr,"PSTREAM_FBADDR1_REG"); - break; - case PSTREAM_STRIDE_REG: - fprintf(stderr,"PSTREAM_STRIDE_REG"); - break; - case DOUBLE_BUFFER_REG: - fprintf(stderr,"DOUBLE_BUFFER_REG"); - break; - case SSTREAM_FBADDR0_REG: - fprintf(stderr,"SSTREAM_FBADDR0_REG"); - break; - case SSTREAM_FBADDR1_REG: - fprintf(stderr,"SSTREAM_FBADDR1_REG"); - break; - case SSTREAM_STRIDE_REG: - fprintf(stderr,"SSTREAM_STRIDE_REG"); - break; - case SSTREAM_VSCALE_REG: - fprintf(stderr,"SSTREAM_VSCALE_REG"); - break; - case SSTREAM_VINITIAL_REG: - fprintf(stderr,"SSTREAM_VINITIAL_REG"); - break; - case SSTREAM_LINES_REG: - fprintf(stderr,"SSTREAM_LINES_REG"); - break; - case STREAMS_FIFO_REG: - fprintf(stderr,"STREAMS_FIFO_REG"); - break; - case PSTREAM_WINDOW_START_REG: - fprintf(stderr,"PSTREAM_WINDOW_START_REG"); - break; - case PSTREAM_WINDOW_SIZE_REG: - fprintf(stderr,"PSTREAM_WINDOW_SIZE_REG"); - break; - case SSTREAM_WINDOW_START_REG: - fprintf(stderr,"SSTREAM_WINDOW_START_REG"); - break; - case SSTREAM_WINDOW_SIZE_REG: - fprintf(stderr,"SSTREAM_WINDOW_SIZE_REG"); - break; - case FIFO_CONTROL: - fprintf(stderr,"FIFO_CONTROL"); - break; - case PSTREAM_FBSIZE_REG: - fprintf(stderr,"PSTREAM_FBSIZE_REG"); - break; - case SSTREAM_FBSIZE_REG: - fprintf(stderr,"SSTREAM_FBSIZE_REG"); - break; - case SSTREAM_FBADDR2_REG: - fprintf(stderr,"SSTREAM_FBADDR2_REG"); - break; - - } - fprintf(stderr,":\t\t 0x%08X = %u\n",val,val); -} - -
--- a/vidix/drivers/sis_bridge.c Sat Mar 31 23:48:48 2007 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,827 +0,0 @@ -/** - Video bridge detection for SiS 300 and 310/325 series chips. - - Copyright 2003 Jake Page, Sugar Media. - - Based on SiS Xv driver: - Copyright 2002-2003 by Thomas Winischhofer, Vienna, Austria. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -**/ - -#include <stdio.h> -#include <stdlib.h> -#include <unistd.h> - -#include "../../libdha/libdha.h" -#include "sis_regs.h" -#include "sis_defs.h" - - -static void sis_ddc2_delay(unsigned short delaytime) -{ - unsigned short i; - int temp; - - for (i = 0; i < delaytime; i++) { - inSISIDXREG(SISSR, 0x05, temp); - } -} - - -static int sis_do_sense(int tempbl, int tempbh, int tempcl, int tempch) -{ - int temp; - - outSISIDXREG(SISPART4, 0x11, tempbl); - temp = tempbh | tempcl; - setSISIDXREG(SISPART4, 0x10, 0xe0, temp); - //usleep(200000); - sis_ddc2_delay(0x1000); - tempch &= 0x7f; - inSISIDXREG(SISPART4, 0x03, temp); - temp ^= 0x0e; - temp &= tempch; - return (temp == tempch); -} - - -/* sense connected devices on 30x bridge */ -static void sis_sense_30x(void) -{ - unsigned char backupP4_0d, backupP2_00, biosflag; - unsigned char testsvhs_tempbl, testsvhs_tempbh; - unsigned char testsvhs_tempcl, testsvhs_tempch; - unsigned char testcvbs_tempbl, testcvbs_tempbh; - unsigned char testcvbs_tempcl, testcvbs_tempch; - unsigned char testvga2_tempbl, testvga2_tempbh; - unsigned char testvga2_tempcl, testvga2_tempch; - int myflag, result = 0, i, j, haveresult; - unsigned short temp; - - inSISIDXREG(SISPART4, 0x0d, backupP4_0d); - outSISIDXREG(SISPART4, 0x0d, (backupP4_0d | 0x04)); - - inSISIDXREG(SISPART2, 0x00, backupP2_00); - outSISIDXREG(SISPART2, 0x00, (backupP2_00 | 0x1c)); - - sis_do_sense(0, 0, 0, 0); - - if ((sis_vga_engine == SIS_315_VGA) || - (sis_device_id == DEVICE_SIS_300)) { -#if 0 - if (0 /*pSiS->sishw_ext.UseROM */ ) { - if (sis_vga_engine == SIS_300_VGA) - temp = 0xfe; - else { - temp = 0xf3; - if (sis_device_id == DEVICE_SIS_330) - temp = 0x11b; - } - if (pSiS->BIOS[temp] & 0x08) { - if (sis_verbose > 1) { - printf - ("[SiS] SiS30x: Video bridge has DVI-I TMDS/VGA combo connector\n"); - } - orSISIDXREG(SISCR, 0x32, 0x80); - } else { - andSISIDXREG(SISCR, 0x32, 0x7f); - } - } -#endif - } - - if (sis_vga_engine == SIS_300_VGA) { - if (0 /*pSiS->sishw_ext.UseROM */ ) { -#if 0 - testvga2_tempbh = pSiS->BIOS[0xf9]; - testvga2_tempbl = pSiS->BIOS[0xf8]; - testsvhs_tempbh = pSiS->BIOS[0xfb]; - testsvhs_tempbl = pSiS->BIOS[0xfa]; - testcvbs_tempbh = pSiS->BIOS[0xfd]; - testcvbs_tempbl = pSiS->BIOS[0xfc]; - biosflag = pSiS->BIOS[0xfe]; -#endif - } else { - testvga2_tempbh = 0x00; - testvga2_tempbl = 0xd1; - testsvhs_tempbh = 0x00; - testsvhs_tempbl = 0xb9; - testcvbs_tempbh = 0x00; - testcvbs_tempbl = 0xb3; - biosflag = 0; - } - if (sis_vbflags & (VB_301B | VB_302B | VB_301LV | VB_302LV)) { - testvga2_tempbh = 0x01; - testvga2_tempbl = 0x90; - testsvhs_tempbh = 0x01; - testsvhs_tempbl = 0x6b; - testcvbs_tempbh = 0x01; - testcvbs_tempbl = 0x74; - } - inSISIDXREG(SISPART4, 0x01, myflag); - if (myflag & 0x04) { - testvga2_tempbh = 0x00; - testvga2_tempbl = 0xfd; - testsvhs_tempbh = 0x00; - testsvhs_tempbl = 0xdd; - testcvbs_tempbh = 0x00; - testcvbs_tempbl = 0xee; - } - testvga2_tempch = 0x0e; - testvga2_tempcl = 0x08; - testsvhs_tempch = 0x06; - testsvhs_tempcl = 0x04; - testcvbs_tempch = 0x08; - testcvbs_tempcl = 0x04; - - if (sis_device_id == DEVICE_SIS_300) { - inSISIDXREG(SISSR, 0x3b, myflag); - if (!(myflag & 0x01)) { - testvga2_tempbh = 0x00; - testvga2_tempbl = 0x00; - testvga2_tempch = 0x00; - testvga2_tempcl = 0x00; - } - } - } else { - if (0 /*pSiS->sishw_ext.UseROM */ ) { -#if 0 - if (sis_device_id == DEVICE_SIS_330) { - testvga2_tempbh = pSiS->BIOS[0xe6]; - testvga2_tempbl = pSiS->BIOS[0xe5]; - testsvhs_tempbh = pSiS->BIOS[0xe8]; - testsvhs_tempbl = pSiS->BIOS[0xe7]; - testcvbs_tempbh = pSiS->BIOS[0xea]; - testcvbs_tempbl = pSiS->BIOS[0xe9]; - biosflag = pSiS->BIOS[0x11b]; - } else { - testvga2_tempbh = pSiS->BIOS[0xbe]; - testvga2_tempbl = pSiS->BIOS[0xbd]; - testsvhs_tempbh = pSiS->BIOS[0xc0]; - testsvhs_tempbl = pSiS->BIOS[0xbf]; - testcvbs_tempbh = pSiS->BIOS[0xc2]; - testcvbs_tempbl = pSiS->BIOS[0xc1]; - biosflag = pSiS->BIOS[0xf3]; - } -#endif - } else { - testvga2_tempbh = 0x00; - testvga2_tempbl = 0xd1; - testsvhs_tempbh = 0x00; - testsvhs_tempbl = 0xb9; - testcvbs_tempbh = 0x00; - testcvbs_tempbl = 0xb3; - biosflag = 0; - } - - if (sis_vbflags & (VB_301B | VB_302B | VB_301LV | VB_302LV)) { - if (0 /*pSiS->sishw_ext.UseROM */ ) { -#if 0 - if (sis_device_id == DEVICE_SIS_330) { - testvga2_tempbh = pSiS->BIOS[0xec]; - testvga2_tempbl = pSiS->BIOS[0xeb]; - testsvhs_tempbh = pSiS->BIOS[0xee]; - testsvhs_tempbl = pSiS->BIOS[0xed]; - testcvbs_tempbh = pSiS->BIOS[0xf0]; - testcvbs_tempbl = pSiS->BIOS[0xef]; - } else { - testvga2_tempbh = pSiS->BIOS[0xc4]; - testvga2_tempbl = pSiS->BIOS[0xc3]; - testsvhs_tempbh = pSiS->BIOS[0xc6]; - testsvhs_tempbl = pSiS->BIOS[0xc5]; - testcvbs_tempbh = pSiS->BIOS[0xc8]; - testcvbs_tempbl = pSiS->BIOS[0xc7]; - } -#endif - } else { - if (sis_vbflags & (VB_301B | VB_302B)) { - testvga2_tempbh = 0x01; - testvga2_tempbl = 0x90; - testsvhs_tempbh = 0x01; - testsvhs_tempbl = 0x6b; - testcvbs_tempbh = 0x01; - testcvbs_tempbl = 0x74; - } else { - testvga2_tempbh = 0x00; - testvga2_tempbl = 0x00; - testsvhs_tempbh = 0x02; - testsvhs_tempbl = 0x00; - testcvbs_tempbh = 0x01; - testcvbs_tempbl = 0x00; - } - } - } - if (sis_vbflags & (VB_301 | VB_301B | VB_302B)) { - inSISIDXREG(SISPART4, 0x01, myflag); - if (myflag & 0x04) { - testvga2_tempbh = 0x00; - testvga2_tempbl = 0xfd; - testsvhs_tempbh = 0x00; - testsvhs_tempbl = 0xdd; - testcvbs_tempbh = 0x00; - testcvbs_tempbl = 0xee; - } - } - if (sis_vbflags & (VB_301LV | VB_302LV)) { - /* TW: No VGA2 or SCART on LV bridges */ - testvga2_tempbh = 0x00; - testvga2_tempbl = 0x00; - testvga2_tempch = 0x00; - testvga2_tempcl = 0x00; - testsvhs_tempch = 0x04; - testsvhs_tempcl = 0x08; - testcvbs_tempch = 0x08; - testcvbs_tempcl = 0x08; - } else { - testvga2_tempch = 0x0e; - testvga2_tempcl = 0x08; - testsvhs_tempch = 0x06; - testsvhs_tempcl = 0x04; - testcvbs_tempch = 0x08; - testcvbs_tempcl = 0x04; - } - } - - /* XXX: ?? andSISIDXREG(SISCR, 0x32, ~0x14); */ - /* pSiS->postVBCR32 &= ~0x14; */ - - /* scan for VGA2/SCART */ - if (testvga2_tempch || testvga2_tempcl || - testvga2_tempbh || testvga2_tempbl) { - - haveresult = 0; - for (j = 0; j < 10; j++) { - result = 0; - for (i = 0; i < 3; i++) { - if (sis_do_sense(testvga2_tempbl, testvga2_tempbh, - testvga2_tempcl, testvga2_tempch)) - result++; - } - if ((result == 0) || (result >= 2)) - break; - } - if (result) { - if (biosflag & 0x01) { - if (sis_verbose > 1) { - printf - ("[SiS] SiS30x: Detected TV connected to SCART output\n"); - } - sis_vbflags |= TV_SCART; - orSISIDXREG(SISCR, 0x32, 0x04); - /*pSiS->postVBCR32 |= 0x04; */ - } else { - if (sis_verbose > 1) { - printf - ("[SiS] SiS30x: Detected secondary VGA connection\n"); - } - sis_vbflags |= VGA2_CONNECTED; - orSISIDXREG(SISCR, 0x32, 0x10); - /*pSiS->postVBCR32 |= 0x10; */ - } - } - } - - /* scanning for TV */ - - /* XXX: ?? andSISIDXREG(SISCR, 0x32, ~0x03); */ - /* pSiS->postVBCR32 &= ~0x03; */ - - result = sis_do_sense(testsvhs_tempbl, testsvhs_tempbh, - testsvhs_tempcl, testsvhs_tempch); - - - haveresult = 0; - for (j = 0; j < 10; j++) { - result = 0; - for (i = 0; i < 3; i++) { - if (sis_do_sense(testsvhs_tempbl, testsvhs_tempbh, - testsvhs_tempcl, testsvhs_tempch)) - result++; - } - if ((result == 0) || (result >= 2)) - break; - } - if (result) { - if (sis_verbose > 1) { - printf - ("[SiS] SiS30x: Detected TV connected to SVIDEO output\n"); - } - /* TW: So we can be sure that there IS a SVIDEO output */ - sis_vbflags |= TV_SVIDEO; - orSISIDXREG(SISCR, 0x32, 0x02); - //pSiS->postVBCR32 |= 0x02; - } - - if ((biosflag & 0x02) || (!(result))) { - haveresult = 0; - for (j = 0; j < 10; j++) { - result = 0; - for (i = 0; i < 3; i++) { - if (sis_do_sense(testcvbs_tempbl, testcvbs_tempbh, - testcvbs_tempcl, testcvbs_tempch)) - result++; - } - if ((result == 0) || (result >= 2)) - break; - } - if (result) { - if (sis_verbose > 1) { - printf - ("[SiS] SiS30x: Detected TV connected to COMPOSITE output\n"); - } - sis_vbflags |= TV_AVIDEO; - orSISIDXREG(SISCR, 0x32, 0x01); - //pSiS->postVBCR32 |= 0x01; - } - } - - sis_do_sense(0, 0, 0, 0); - - outSISIDXREG(SISPART2, 0x00, backupP2_00); - outSISIDXREG(SISPART4, 0x0d, backupP4_0d); -} - - -static void sis_detect_crt1(void) -{ - unsigned char CR32; - unsigned char CRT1Detected = 0; - unsigned char OtherDevices = 0; - - if (!(sis_vbflags & VB_VIDEOBRIDGE)) { - sis_crt1_off = 0; - return; - } - - inSISIDXREG(SISCR, 0x32, CR32); - - if (CR32 & 0x20) - CRT1Detected = 1; - if (CR32 & 0x5F) - OtherDevices = 1; - - if (sis_crt1_off == -1) { - if (!CRT1Detected) { - /* BIOS detected no CRT1. */ - /* If other devices exist, switch it off */ - if (OtherDevices) - sis_crt1_off = 1; - else - sis_crt1_off = 0; - } else { - /* BIOS detected CRT1, leave/switch it on */ - sis_crt1_off = 0; - } - } - if (sis_verbose > 0) { - printf("[SiS] %sCRT1 connection detected\n", - sis_crt1_off ? "No " : ""); - } -} - - -static void sis_detect_lcd(void) -{ - unsigned char CR32, CR36, CR37; - - if (!(sis_vbflags & VB_VIDEOBRIDGE)) { - return; - } - - inSISIDXREG(SISCR, 0x32, CR32); - - if (CR32 & 0x08) - sis_vbflags |= CRT2_LCD; - - /* DDC detection of LCD - not supported yet */ - - /* Get other misc info about LCD - not supported */ -} - - -static void sis_detect_tv(void) -{ - unsigned char SR16, SR38, CR32, CR38 = 0, CR79; - int temp = 0; - - if (!(sis_vbflags & VB_VIDEOBRIDGE)) - return; - - inSISIDXREG(SISCR, 0x32, CR32); - inSISIDXREG(SISSR, 0x16, SR16); - inSISIDXREG(SISSR, 0x38, SR38); - switch (sis_vga_engine) { - case SIS_300_VGA: - if (sis_device_id == DEVICE_SIS_630_VGA) - temp = 0x35; - break; - case SIS_315_VGA: - temp = 0x38; - break; - } - if (temp) { - inSISIDXREG(SISCR, temp, CR38); - } - - if (CR32 & 0x47) - sis_vbflags |= CRT2_TV; - - if (CR32 & 0x04) - sis_vbflags |= TV_SCART; - else if (CR32 & 0x02) - sis_vbflags |= TV_SVIDEO; - else if (CR32 & 0x01) - sis_vbflags |= TV_AVIDEO; - else if (CR32 & 0x40) - sis_vbflags |= (TV_SVIDEO | TV_HIVISION); - else if ((CR38 & 0x04) && (sis_vbflags & (VB_301LV | VB_302LV))) - sis_vbflags |= TV_HIVISION_LV; - else if ((CR38 & 0x04) && (sis_vbflags & VB_CHRONTEL)) - sis_vbflags |= (TV_CHSCART | TV_PAL); - else if ((CR38 & 0x08) && (sis_vbflags & VB_CHRONTEL)) - sis_vbflags |= (TV_CHHDTV | TV_NTSC); - - if (sis_vbflags & (TV_SCART | TV_SVIDEO | TV_AVIDEO | TV_HIVISION)) { - if (sis_vga_engine == SIS_300_VGA) { - /* TW: Should be SR38 here as well, but this - * does not work. Looks like a BIOS bug (2.04.5c). - */ - if (SR16 & 0x20) - sis_vbflags |= TV_PAL; - else - sis_vbflags |= TV_NTSC; - } else if ((sis_device_id == DEVICE_SIS_550_VGA)) { - inSISIDXREG(SISCR, 0x79, CR79); - if (CR79 & 0x08) { - inSISIDXREG(SISCR, 0x79, CR79); - CR79 >>= 5; - } - if (CR79 & 0x01) { - sis_vbflags |= TV_PAL; - if (CR38 & 0x40) - sis_vbflags |= TV_PALM; - else if (CR38 & 0x80) - sis_vbflags |= TV_PALN; - } else - sis_vbflags |= TV_NTSC; - } else if ((sis_device_id == DEVICE_SIS_650_VGA)) { - inSISIDXREG(SISCR, 0x79, CR79); - if (CR79 & 0x20) { - sis_vbflags |= TV_PAL; - if (CR38 & 0x40) - sis_vbflags |= TV_PALM; - else if (CR38 & 0x80) - sis_vbflags |= TV_PALN; - } else - sis_vbflags |= TV_NTSC; - } else { /* 315, 330 */ - if (SR38 & 0x01) { - sis_vbflags |= TV_PAL; - if (CR38 & 0x40) - sis_vbflags |= TV_PALM; - else if (CR38 & 0x80) - sis_vbflags |= TV_PALN; - } else - sis_vbflags |= TV_NTSC; - } - } - - if (sis_vbflags & - (TV_SCART | TV_SVIDEO | TV_AVIDEO | TV_HIVISION | TV_CHSCART | - TV_CHHDTV)) { - if (sis_verbose > 0) { - printf("[SiS] %sTV standard %s\n", - (sis_vbflags & (TV_CHSCART | TV_CHHDTV)) ? "Using " : - "Detected default ", - (sis_vbflags & TV_NTSC) ? ((sis_vbflags & TV_CHHDTV) ? - "480i HDTV" : "NTSC") - : ((sis_vbflags & TV_PALM) ? "PALM" - : ((sis_vbflags & TV_PALN) ? "PALN" : "PAL"))); - } - } - -} - - -static void sis_detect_crt2(void) -{ - unsigned char CR32; - - if (!(sis_vbflags & VB_VIDEOBRIDGE)) - return; - - /* CRT2-VGA not supported on LVDS and 30xLV */ - if (sis_vbflags & (VB_LVDS | VB_301LV | VB_302LV)) - return; - - inSISIDXREG(SISCR, 0x32, CR32); - - if (CR32 & 0x10) - sis_vbflags |= CRT2_VGA; - -#if 0 - if (!(pSiS->nocrt2ddcdetection)) { - if (sis_vbflags & (VB_301B | VB_302B)) { - if (!(sis_vbflags & (CRT2_VGA | CRT2_LCD))) { - printf - ("[SiS] BIOS detected no secondary VGA, sensing via DDC\n"); - if (SiS_SenseVGA2DDC(pSiS->SiS_Pr, pSiS)) { - printf - ("[SiS] DDC error during secondary VGA detection\n"); - } else { - inSISIDXREG(SISCR, 0x32, CR32); - if (CR32 & 0x10) { - sis_vbflags |= CRT2_VGA; - /*pSiS->postVBCR32 |= 0x10; */ - printf - ("[SiS] Detected secondary VGA connection\n"); - } else { - printf - ("[SiS] No secondary VGA connection detected\n"); - } - } - } - } - } -#endif - -} - - -/* Preinit: detect video bridge and sense connected devs */ -static void sis_detect_video_bridge(void) -{ - int temp, temp1, temp2; - - - sis_vbflags = 0; - - if (sis_vga_engine != SIS_300_VGA && sis_vga_engine != SIS_315_VGA) - return; - - inSISIDXREG(SISPART4, 0x00, temp); - temp &= 0x0F; - if (temp == 1) { - inSISIDXREG(SISPART4, 0x01, temp1); - temp1 &= 0xff; - if (temp1 >= 0xE0) { - sis_vbflags |= VB_302LV; - //pSiS->sishw_ext.ujVBChipID = VB_CHIP_302LV; - if (sis_verbose > 1) { - printf - ("[SiS] Detected SiS302LV video bridge (ID 1; Revision 0x%x)\n", - temp1); - } - - } else if (temp1 >= 0xD0) { - sis_vbflags |= VB_301LV; - //pSiS->sishw_ext.ujVBChipID = VB_CHIP_301LV; - if (sis_verbose > 1) { - printf - ("[SiS] Detected SiS301LV video bridge (ID 1; Revision 0x%x)\n", - temp1); - } - } else if (temp1 >= 0xB0) { - sis_vbflags |= VB_301B; - //pSiS->sishw_ext.ujVBChipID = VB_CHIP_301B; - inSISIDXREG(SISPART4, 0x23, temp2); - if (!(temp2 & 0x02)) - sis_vbflags |= VB_30xBDH; - if (sis_verbose > 1) { - printf - ("[SiS] Detected SiS301B%s video bridge (Revision 0x%x)\n", - (temp2 & 0x02) ? "" : " (DH)", temp1); - } - } else { - sis_vbflags |= VB_301; - //pSiS->sishw_ext.ujVBChipID = VB_CHIP_301; - if (sis_verbose > 1) { - printf - ("[SiS] Detected SiS301 video bridge (Revision 0x%x)\n", - temp1); - } - } - - sis_sense_30x(); - - } else if (temp == 2) { - - inSISIDXREG(SISPART4, 0x01, temp1); - temp1 &= 0xff; - if (temp1 >= 0xE0) { - sis_vbflags |= VB_302LV; - //pSiS->sishw_ext.ujVBChipID = VB_CHIP_302LV; - if (sis_verbose > 1) { - printf - ("[SiS] Detected SiS302LV video bridge (ID 2; Revision 0x%x)\n", - temp1); - } - } else if (temp1 >= 0xD0) { - sis_vbflags |= VB_301LV; - //pSiS->sishw_ext.ujVBChipID = VB_CHIP_301LV; - if (sis_verbose > 1) { - printf - ("[SiS] Detected SiS301LV video bridge (ID 2; Revision 0x%x)\n", - temp1); - } - } else { - sis_vbflags |= VB_302B; - //pSiS->sishw_ext.ujVBChipID = VB_CHIP_302B; - inSISIDXREG(SISPART4, 0x23, temp2); - if (!(temp & 0x02)) - sis_vbflags |= VB_30xBDH; - if (sis_verbose > 1) { - printf - ("[SiS] Detected SiS302B%s video bridge (Revision 0x%x)\n", - (temp2 & 0x02) ? "" : " (DH)", temp1); - } - } - - sis_sense_30x(); - - } else if (temp == 3) { - if (sis_verbose > 1) { - printf("[SiS] Detected SiS303 video bridge - not supported\n"); - } - } else { - /* big scary mess of code to handle unknown or Chrontel LVDS */ - /* skipping it for now */ - if (sis_verbose > 1) { - printf - ("[SiS] Detected Chrontel video bridge - not supported\n"); - } - } - - /* this is probably not relevant to video overlay driver... */ - /* detects if brdige uses LCDA for low res text modes */ - if (sis_vga_engine == SIS_315_VGA) { - if (sis_vbflags & (VB_302B | VB_301LV | VB_302LV)) { -#if 0 - if (pSiS->sisfblcda != 0xff) { - if ((pSiS->sisfblcda & 0x03) == 0x03) { - //pSiS->SiS_Pr->SiS_UseLCDA = TRUE; - sis_vbflags |= VB_USELCDA; - } - } else -#endif - { - inSISIDXREG(SISCR, 0x34, temp); - if (temp <= 0x13) { - inSISIDXREG(SISCR, 0x38, temp); - if ((temp & 0x03) == 0x03) { - //pSiS->SiS_Pr->SiS_UseLCDA = TRUE; - sis_vbflags |= VB_USELCDA; - } else { - inSISIDXREG(SISCR, 0x30, temp); - if (temp & 0x20) { - inSISIDXREG(SISPART1, 0x13, temp); - if (temp & 0x40) { - //pSiS->SiS_Pr->SiS_UseLCDA = TRUE; - sis_vbflags |= VB_USELCDA; - } - } - } - } - } - if (sis_vbflags & VB_USELCDA) { - /* printf("Bridge uses LCDA for low resolution and text modes\n"); */ - } - } - } - - -} - - -/* detect video bridge type and sense connected devices */ -void sis_init_video_bridge(void) -{ - - sis_detect_video_bridge(); - - sis_detect_crt1(); - //sis_detect_lcd(); - sis_detect_tv(); - sis_detect_crt2(); - - sis_detected_crt2_devices = - sis_vbflags & (CRT2_LCD | CRT2_TV | CRT2_VGA); - - // force crt2 type - if (sis_force_crt2_type == CRT2_DEFAULT) { - if (sis_vbflags & CRT2_VGA) - sis_force_crt2_type = CRT2_VGA; - else if (sis_vbflags & CRT2_LCD) - sis_force_crt2_type = CRT2_LCD; - else if (sis_vbflags & CRT2_TV) - sis_force_crt2_type = CRT2_TV; - } - - switch (sis_force_crt2_type) { - case CRT2_TV: - sis_vbflags = sis_vbflags & ~(CRT2_LCD | CRT2_VGA); - if (sis_vbflags & VB_VIDEOBRIDGE) - sis_vbflags = sis_vbflags | CRT2_TV; - else - sis_vbflags = sis_vbflags & ~(CRT2_TV); - break; - case CRT2_LCD: - sis_vbflags = sis_vbflags & ~(CRT2_TV | CRT2_VGA); - if ((sis_vbflags & VB_VIDEOBRIDGE) /* XXX: && (pSiS->VBLCDFlags) */ - ) - sis_vbflags = sis_vbflags | CRT2_LCD; - else { - sis_vbflags = sis_vbflags & ~(CRT2_LCD); - if (sis_verbose > 0) { - printf - ("[SiS] Can't force CRT2 to LCD, no panel detected\n"); - } - } - break; - case CRT2_VGA: - if (sis_vbflags & VB_LVDS) { - if (sis_verbose > 0) { - printf("[SiS] LVDS does not support secondary VGA\n"); - } - break; - } - if (sis_vbflags & (VB_301LV | VB_302LV)) { - if (sis_verbose > 0) { - printf - ("[SiS] SiS30xLV bridge does not support secondary VGA\n"); - } - break; - } - sis_vbflags = sis_vbflags & ~(CRT2_TV | CRT2_LCD); - if (sis_vbflags & VB_VIDEOBRIDGE) - sis_vbflags = sis_vbflags | CRT2_VGA; - else - sis_vbflags = sis_vbflags & ~(CRT2_VGA); - break; - default: - sis_vbflags &= ~(CRT2_TV | CRT2_LCD | CRT2_VGA); - } - - /* CRT2 gamma correction?? */ - - /* other force modes: */ - /* have a 'force tv type' (svideo, composite, scart) option? */ - /* have a 'force crt1 type' (to turn it off, etc??) */ - - /* TW: Check if CRT1 used (or needed; this eg. if no CRT2 detected) */ - if (sis_vbflags & VB_VIDEOBRIDGE) { - - /* TW: No CRT2 output? Then we NEED CRT1! - * We also need CRT1 if depth = 8 and bridge=LVDS|630+301B - */ - if ((!(sis_vbflags & (CRT2_VGA | CRT2_LCD | CRT2_TV))) || ( /*(pScrn->bitsPerPixel == 8) && */ - ((sis_vbflags & (VB_LVDS | VB_CHRONTEL)) || ((sis_vga_engine == SIS_300_VGA) && (sis_vbflags & VB_301B))))) { - sis_crt1_off = 0; - } - /* TW: No CRT2 output? Then we can't use hw overlay on CRT2 */ - if (!(sis_vbflags & (CRT2_VGA | CRT2_LCD | CRT2_TV))) - sis_overlay_on_crt1 = 1; - - } else { /* TW: no video bridge? */ - - /* Then we NEED CRT1... */ - sis_crt1_off = 0; - /* ... and can't use CRT2 for overlay output */ - sis_overlay_on_crt1 = 1; - } - - /* tvstandard options ? */ - - // determine using CRT1 or CRT2? - /* -> NO dualhead right now... */ - if (sis_vbflags & DISPTYPE_DISP2) { - if (sis_crt1_off) { - sis_vbflags |= VB_DISPMODE_SINGLE; - /* TW: No CRT1? Then we use the video overlay on CRT2 */ - sis_overlay_on_crt1 = 0; - } else /* TW: CRT1 and CRT2 - mirror or dual head ----- */ - sis_vbflags |= (VB_DISPMODE_MIRROR | DISPTYPE_CRT1); - } else { /* TW: CRT1 only ------------------------------- */ - sis_vbflags |= (VB_DISPMODE_SINGLE | DISPTYPE_CRT1); - } - - if (sis_verbose > 0) { - printf("[SiS] Using hardware overlay on CRT%d\n", - sis_overlay_on_crt1 ? 1 : 2); - } - -}
--- a/vidix/drivers/sis_defs.h Sat Mar 31 23:48:48 2007 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,106 +0,0 @@ -/** - SiS graphics misc definitions. - - Taken from SiS Xv driver: - Copyright 2002-2003 by Thomas Winischhofer, Vienna, Austria. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -**/ - -#ifndef VIDIX_SIS_DEFS_H -#define VIDIX_SIS_DEFS_H - -/** PCI IDs **/ -#define VENDOR_SIS 0x1039 - -#define DEVICE_SIS_300 0x0300 -#define DEVICE_SIS_315H 0x0310 -#define DEVICE_SIS_315 0x0315 -#define DEVICE_SIS_315PRO 0x0325 -#define DEVICE_SIS_330 0x0330 -#define DEVICE_SIS_540 0x0540 -#define DEVICE_SIS_540_VGA 0x5300 -#define DEVICE_SIS_550 0x0550 -#define DEVICE_SIS_550_VGA 0x5315 -#define DEVICE_SIS_630 0x0630 -#define DEVICE_SIS_630_VGA 0x6300 -#define DEVICE_SIS_650 0x0650 -#define DEVICE_SIS_650_VGA 0x6325 -#define DEVICE_SIS_730 0x0730 - - -/* TW: VBFlags */ -#define CRT2_DEFAULT 0x00000001 -#define CRT2_LCD 0x00000002 /* TW: Never change the order of the CRT2_XXX entries */ -#define CRT2_TV 0x00000004 /* (see SISCycleCRT2Type()) */ -#define CRT2_VGA 0x00000008 -#define CRT2_ENABLE (CRT2_LCD | CRT2_TV | CRT2_VGA) -#define DISPTYPE_DISP2 CRT2_ENABLE -#define TV_NTSC 0x00000010 -#define TV_PAL 0x00000020 -#define TV_HIVISION 0x00000040 -#define TV_HIVISION_LV 0x00000080 -#define TV_TYPE (TV_NTSC | TV_PAL | TV_HIVISION | TV_HIVISION_LV) -#define TV_AVIDEO 0x00000100 -#define TV_SVIDEO 0x00000200 -#define TV_SCART 0x00000400 -#define TV_INTERFACE (TV_AVIDEO | TV_SVIDEO | TV_SCART | TV_CHSCART | TV_CHHDTV) -#define VB_USELCDA 0x00000800 -#define TV_PALM 0x00001000 -#define TV_PALN 0x00002000 -#define TV_CHSCART 0x00008000 -#define TV_CHHDTV 0x00010000 -#define VGA2_CONNECTED 0x00040000 -#define DISPTYPE_CRT1 0x00080000 /* TW: CRT1 connected and used */ -#define DISPTYPE_DISP1 DISPTYPE_CRT1 -#define VB_301 0x00100000 /* Video bridge type */ -#define VB_301B 0x00200000 -#define VB_302B 0x00400000 -#define VB_30xBDH 0x00800000 /* 30xB DH version (w/o LCD support) */ -#define VB_LVDS 0x01000000 -#define VB_CHRONTEL 0x02000000 -#define VB_301LV 0x04000000 -#define VB_302LV 0x08000000 -#define VB_30xLV VB_301LV -#define VB_30xLVX VB_302LV -#define VB_TRUMPION 0x10000000 -#define VB_VIDEOBRIDGE (VB_301|VB_301B|VB_302B|VB_301LV|VB_302LV| \ - VB_LVDS|VB_CHRONTEL|VB_TRUMPION) /* TW */ -#define VB_SISBRIDGE (VB_301|VB_301B|VB_302B|VB_301LV|VB_302LV) -#define SINGLE_MODE 0x20000000 /* TW: CRT1 or CRT2; determined by DISPTYPE_CRTx */ -#define VB_DISPMODE_SINGLE SINGLE_MODE /* TW: alias */ -#define MIRROR_MODE 0x40000000 /* TW: CRT1 + CRT2 identical (mirror mode) */ -#define VB_DISPMODE_MIRROR MIRROR_MODE /* TW: alias */ -#define DUALVIEW_MODE 0x80000000 /* TW: CRT1 + CRT2 independent (dual head mode) */ -#define VB_DISPMODE_DUAL DUALVIEW_MODE /* TW: alias */ -#define DISPLAY_MODE (SINGLE_MODE | MIRROR_MODE | DUALVIEW_MODE) /* TW */ - -/* SiS vga engine type */ -#define UNKNOWN_VGA 0 -#define SIS_300_VGA 1 -#define SIS_315_VGA 2 - -extern unsigned int sis_verbose; -extern unsigned short sis_iobase; -extern unsigned int sis_vga_engine; -extern unsigned int sis_vbflags; -extern unsigned int sis_overlay_on_crt1; -extern unsigned int sis_crt1_off; -extern unsigned int sis_detected_crt2_devices; -extern unsigned int sis_force_crt2_type; -extern unsigned int sis_device_id; - -#endif /* VIDIX_SIS_DEFS_H */
--- a/vidix/drivers/sis_regs.h Sat Mar 31 23:48:48 2007 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,412 +0,0 @@ -/** - SiS register definitions and access macros. - From SiS X11 driver. - - Copyright 2001-2003 by Thomas Winischhofer, Vienna, Austria. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - -**/ - -#ifndef VIDIX_SIS_REGS_H -#define VIDIX_SIS_REGS_H - -#define inSISREG(base) INPORT8(base) -#define outSISREG(base,val) OUTPORT8(base, val) -#define orSISREG(base,val) do { \ - unsigned char __Temp = INPORT8(base); \ - outSISREG(base, __Temp | (val)); \ - } while (0) -#define andSISREG(base,val) do { \ - unsigned char __Temp = INPORT8(base); \ - outSISREG(base, __Temp & (val)); \ - } while (0) - -#define inSISIDXREG(base,idx,var) do { \ - OUTPORT8(base, idx); var=INPORT8((base)+1); \ - } while (0) -#define outSISIDXREG(base,idx,val) do { \ - OUTPORT8(base, idx); OUTPORT8((base)+1, val); \ - } while (0) -#define orSISIDXREG(base,idx,val) do { \ - unsigned char __Temp; \ - OUTPORT8(base, idx); \ - __Temp = INPORT8((base)+1)|(val); \ - outSISIDXREG(base,idx,__Temp); \ - } while (0) -#define andSISIDXREG(base,idx,and) do { \ - unsigned char __Temp; \ - OUTPORT8(base, idx); \ - __Temp = INPORT8((base)+1)&(and); \ - outSISIDXREG(base,idx,__Temp); \ - } while (0) -#define setSISIDXREG(base,idx,and,or) do { \ - unsigned char __Temp; \ - OUTPORT8(base, idx); \ - __Temp = (INPORT8((base)+1)&(and))|(or); \ - outSISIDXREG(base,idx,__Temp); \ - } while (0) - -#define BITMASK(h,l) (((unsigned)(1U << ((h)-(l)+1))-1)<<(l)) -#define GENMASK(mask) BITMASK(1?mask,0?mask) - -#define GETBITS(var,mask) (((var) & GENMASK(mask)) >> (0?mask)) -#define SETBITS(val,mask) ((val) << (0?mask)) -#define SETBIT(n) (1<<(n)) - -#define GETBITSTR(val,from,to) ((GETBITS(val,from)) << (0?to)) -#define SETVARBITS(var,val,from,to) (((var)&(~(GENMASK(to)))) | \ - GETBITSTR(val,from,to)) -#define GETVAR8(var) ((var)&0xFF) -#define SETVAR8(var,val) (var) = GETVAR8(val) - -/* #define VGA_RELIO_BASE 0x380 */ - -#define AROFFSET 0x40 /* VGA_ATTR_INDEX - VGA_RELIO_BASE */ -#define ARROFFSET 0x41 /* VGA_ATTR_DATA_R - VGA_RELIO_BASE */ -#define GROFFSET 0x4e /* VGA_GRAPH_INDEX - VGA_RELIO_BASE */ -#define SROFFSET 0x44 /* VGA_SEQ_INDEX - VGA_RELIO_BASE */ -#define CROFFSET 0x54 /* VGA_CRTC_INDEX_OFFSET + VGA_IOBASE_COLOR - VGA_RELIO_BASE */ -#define MISCROFFSET 0x4c /* VGA_MISC_OUT_R - VGA_RELIO_BASE */ -#define MISCWOFFSET 0x42 /* VGA_MISC_OUT_W - VGA_RELIO_BASE */ -#define INPUTSTATOFFSET 0x5A -#define PART1OFFSET 0x04 -#define PART2OFFSET 0x10 -#define PART3OFFSET 0x12 -#define PART4OFFSET 0x14 -#define PART5OFFSET 0x16 -#define VIDEOOFFSET 0x02 -#define COLREGOFFSET 0x48 - -#define SIS_IOBASE sis_iobase /* var defined in sis_vid.c */ -#define SISAR SIS_IOBASE + AROFFSET -#define SISARR SIS_IOBASE + ARROFFSET -#define SISGR SIS_IOBASE + GROFFSET -#define SISSR SIS_IOBASE + SROFFSET -#define SISCR SIS_IOBASE + CROFFSET -#define SISMISCR SIS_IOBASE + MISCROFFSET -#define SISMISCW SIS_IOBASE + MISCWOFFSET -#define SISINPSTAT SIS_IOBASE + INPUTSTATOFFSET -#define SISPART1 SIS_IOBASE + PART1OFFSET -#define SISPART2 SIS_IOBASE + PART2OFFSET -#define SISPART3 SIS_IOBASE + PART3OFFSET -#define SISPART4 SIS_IOBASE + PART4OFFSET -#define SISPART5 SIS_IOBASE + PART5OFFSET -#define SISVID SIS_IOBASE + VIDEOOFFSET -#define SISCOLIDX SIS_IOBASE + COLREGOFFSET -#define SISCOLDATA SIS_IOBASE + COLREGOFFSET + 1 -#define SISCOL2IDX SISPART5 -#define SISCOL2DATA SISPART5 + 1 - - -#define vc_index_offset 0x00 /* Video capture - unused */ -#define vc_data_offset 0x01 -#define vi_index_offset VIDEOOFFSET -#define vi_data_offset (VIDEOOFFSET + 1) -#define crt2_index_offset PART1OFFSET -#define crt2_port_offset (PART1OFFSET + 1) -#define sr_index_offset SROFFSET -#define sr_data_offset (SROFFSET + 1) -#define cr_index_offset CROFFSET -#define cr_data_offset (CROFFSET + 1) -#define input_stat INPUTSTATOFFSET - -/* For old chipsets (5597/5598, 6326, 530/620) ------------ */ -/* SR (3C4) */ -#define BankReg 0x06 -#define ClockReg 0x07 -#define CPUThreshold 0x08 -#define CRTThreshold 0x09 -#define CRTCOff 0x0A -#define DualBanks 0x0B -#define MMIOEnable 0x0B -#define RAMSize 0x0C -#define Mode64 0x0C -#define ExtConfStatus1 0x0E -#define ClockBase 0x13 -#define LinearAdd0 0x20 -#define LinearAdd1 0x21 -#define GraphEng 0x27 -#define MemClock0 0x28 -#define MemClock1 0x29 -#define XR2A 0x2A -#define XR2B 0x2B -#define TurboQueueBase 0x2C -#define FBSize 0x2F -#define ExtMiscCont5 0x34 -#define ExtMiscCont9 0x3C - -/* 3x4 */ -#define Offset 0x13 - -/* SiS Registers for 300, 540, 630, 730, 315, 550, 650, 740 */ - -/* VGA standard register */ -#define Index_SR_Graphic_Mode 0x06 -#define Index_SR_RAMDAC_Ctrl 0x07 -#define Index_SR_Threshold_Ctrl1 0x08 -#define Index_SR_Threshold_Ctrl2 0x09 -#define Index_SR_Misc_Ctrl 0x0F -#define Index_SR_DDC 0x11 -#define Index_SR_Feature_Connector_Ctrl 0x12 -#define Index_SR_DRAM_Sizing 0x14 -#define Index_SR_DRAM_State_Machine_Ctrl 0x15 -#define Index_SR_AGP_PCI_State_Machine 0x21 -#define Index_SR_Internal_MCLK0 0x28 -#define Index_SR_Internal_MCLK1 0x29 -#define Index_SR_Internal_DCLK1 0x2B -#define Index_SR_Internal_DCLK2 0x2C -#define Index_SR_Internal_DCLK3 0x2D -#define Index_SR_Ext_Clock_Sel 0x32 -#define Index_SR_Int_Status 0x34 -#define Index_SR_Int_Enable 0x35 -#define Index_SR_Int_Reset 0x36 -#define Index_SR_Power_On_Trap 0x38 -#define Index_SR_Power_On_Trap2 0x39 -#define Index_SR_Power_On_Trap3 0x3A - -/* video registers (300/630/730/315/550/650/740 only) */ -#define Index_VI_Passwd 0x00 - -/* Video overlay horizontal start/end, unit=screen pixels */ -#define Index_VI_Win_Hor_Disp_Start_Low 0x01 -#define Index_VI_Win_Hor_Disp_End_Low 0x02 -#define Index_VI_Win_Hor_Over 0x03 /* Overflow */ - -/* Video overlay vertical start/end, unit=screen pixels */ -#define Index_VI_Win_Ver_Disp_Start_Low 0x04 -#define Index_VI_Win_Ver_Disp_End_Low 0x05 -#define Index_VI_Win_Ver_Over 0x06 /* Overflow */ - -/* Y Plane (4:2:0) or YUV (4:2:2) buffer start address, unit=word */ -#define Index_VI_Disp_Y_Buf_Start_Low 0x07 -#define Index_VI_Disp_Y_Buf_Start_Middle 0x08 -#define Index_VI_Disp_Y_Buf_Start_High 0x09 - -/* U Plane (4:2:0) buffer start address, unit=word */ -#define Index_VI_U_Buf_Start_Low 0x0A -#define Index_VI_U_Buf_Start_Middle 0x0B -#define Index_VI_U_Buf_Start_High 0x0C - -/* V Plane (4:2:0) buffer start address, unit=word */ -#define Index_VI_V_Buf_Start_Low 0x0D -#define Index_VI_V_Buf_Start_Middle 0x0E -#define Index_VI_V_Buf_Start_High 0x0F - -/* Pitch for Y, UV Planes, unit=word */ -#define Index_VI_Disp_Y_Buf_Pitch_Low 0x10 -#define Index_VI_Disp_UV_Buf_Pitch_Low 0x11 -#define Index_VI_Disp_Y_UV_Buf_Pitch_Middle 0x12 - -/* What is this ? */ -#define Index_VI_Disp_Y_Buf_Preset_Low 0x13 -#define Index_VI_Disp_Y_Buf_Preset_Middle 0x14 - -#define Index_VI_UV_Buf_Preset_Low 0x15 -#define Index_VI_UV_Buf_Preset_Middle 0x16 -#define Index_VI_Disp_Y_UV_Buf_Preset_High 0x17 - -/* Scaling control registers */ -#define Index_VI_Hor_Post_Up_Scale_Low 0x18 -#define Index_VI_Hor_Post_Up_Scale_High 0x19 -#define Index_VI_Ver_Up_Scale_Low 0x1A -#define Index_VI_Ver_Up_Scale_High 0x1B -#define Index_VI_Scale_Control 0x1C - -/* Playback line buffer control */ -#define Index_VI_Play_Threshold_Low 0x1D -#define Index_VI_Play_Threshold_High 0x1E -#define Index_VI_Line_Buffer_Size 0x1F - -/* Destination color key */ -#define Index_VI_Overlay_ColorKey_Red_Min 0x20 -#define Index_VI_Overlay_ColorKey_Green_Min 0x21 -#define Index_VI_Overlay_ColorKey_Blue_Min 0x22 -#define Index_VI_Overlay_ColorKey_Red_Max 0x23 -#define Index_VI_Overlay_ColorKey_Green_Max 0x24 -#define Index_VI_Overlay_ColorKey_Blue_Max 0x25 - -/* Source color key, YUV color space */ -#define Index_VI_Overlay_ChromaKey_Red_Y_Min 0x26 -#define Index_VI_Overlay_ChromaKey_Green_U_Min 0x27 -#define Index_VI_Overlay_ChromaKey_Blue_V_Min 0x28 -#define Index_VI_Overlay_ChromaKey_Red_Y_Max 0x29 -#define Index_VI_Overlay_ChromaKey_Green_U_Max 0x2A -#define Index_VI_Overlay_ChromaKey_Blue_V_Max 0x2B - -/* Contrast enhancement and brightness control */ -#define Index_VI_Contrast_Factor 0x2C /* obviously unused/undefined */ -#define Index_VI_Brightness 0x2D -#define Index_VI_Contrast_Enh_Ctrl 0x2E - -#define Index_VI_Key_Overlay_OP 0x2F - -#define Index_VI_Control_Misc0 0x30 -#define Index_VI_Control_Misc1 0x31 -#define Index_VI_Control_Misc2 0x32 - -/* TW: Subpicture registers */ -#define Index_VI_SubPict_Buf_Start_Low 0x33 -#define Index_VI_SubPict_Buf_Start_Middle 0x34 -#define Index_VI_SubPict_Buf_Start_High 0x35 - -/* TW: What is this ? */ -#define Index_VI_SubPict_Buf_Preset_Low 0x36 -#define Index_VI_SubPict_Buf_Preset_Middle 0x37 - -/* TW: Subpicture pitch, unit=16 bytes */ -#define Index_VI_SubPict_Buf_Pitch 0x38 - -/* TW: Subpicture scaling control */ -#define Index_VI_SubPict_Hor_Scale_Low 0x39 -#define Index_VI_SubPict_Hor_Scale_High 0x3A -#define Index_VI_SubPict_Vert_Scale_Low 0x3B -#define Index_VI_SubPict_Vert_Scale_High 0x3C - -#define Index_VI_SubPict_Scale_Control 0x3D -/* (0x40 = enable/disable subpicture) */ - -/* TW: Subpicture line buffer control */ -#define Index_VI_SubPict_Threshold 0x3E - -/* TW: What is this? */ -#define Index_VI_FIFO_Max 0x3F - -/* TW: Subpicture palette; 16 colors, total 32 bytes address space */ -#define Index_VI_SubPict_Pal_Base_Low 0x40 -#define Index_VI_SubPict_Pal_Base_High 0x41 - -/* I wish I knew how to use these ... */ -#define Index_MPEG_Read_Ctrl0 0x60 /* MPEG auto flip */ -#define Index_MPEG_Read_Ctrl1 0x61 /* MPEG auto flip */ -#define Index_MPEG_Read_Ctrl2 0x62 /* MPEG auto flip */ -#define Index_MPEG_Read_Ctrl3 0x63 /* MPEG auto flip */ - -/* TW: MPEG AutoFlip scale */ -#define Index_MPEG_Ver_Up_Scale_Low 0x64 -#define Index_MPEG_Ver_Up_Scale_High 0x65 - -#define Index_MPEG_Y_Buf_Preset_Low 0x66 -#define Index_MPEG_Y_Buf_Preset_Middle 0x67 -#define Index_MPEG_UV_Buf_Preset_Low 0x68 -#define Index_MPEG_UV_Buf_Preset_Middle 0x69 -#define Index_MPEG_Y_UV_Buf_Preset_High 0x6A - -/* TW: The following registers only exist on the 310/325 series */ - -/* TW: Bit 16:24 of Y_U_V buf start address (?) */ -#define Index_VI_Y_Buf_Start_Over 0x6B -#define Index_VI_U_Buf_Start_Over 0x6C -#define Index_VI_V_Buf_Start_Over 0x6D - -#define Index_VI_Disp_Y_Buf_Pitch_High 0x6E -#define Index_VI_Disp_UV_Buf_Pitch_High 0x6F - -/* Hue and saturation */ -#define Index_VI_Hue 0x70 -#define Index_VI_Saturation 0x71 - -#define Index_VI_SubPict_Start_Over 0x72 -#define Index_VI_SubPict_Buf_Pitch_High 0x73 - -#define Index_VI_Control_Misc3 0x74 - - -/* TW: Bits (and helpers) for Index_VI_Control_Misc0 */ -#define VI_Misc0_Enable_Overlay 0x02 -#define VI_Misc0_420_Plane_Enable 0x04 /* Select Plane or Packed mode */ -#define VI_Misc0_422_Enable 0x20 /* Select 422 or 411 mode */ -#define VI_Misc0_Fmt_YVU420P 0x0C /* YUV420 Planar (I420, YV12) */ -#define VI_Misc0_Fmt_YUYV 0x28 /* YUYV Packed (YUY2) */ -#define VI_Misc0_Fmt_UYVY 0x08 /* (UYVY) */ - -/* TW: Bits for Index_VI_Control_Misc1 */ -/* #define VI_Misc1_? 0x01 */ -#define VI_Misc1_BOB_Enable 0x02 -#define VI_Misc1_Line_Merge 0x04 -#define VI_Misc1_Field_Mode 0x08 -/* #define VI_Misc1_? 0x10 */ -#define VI_Misc1_Non_Interleave 0x20 /* 300 series only? */ -#define VI_Misc1_Buf_Addr_Lock 0x20 /* 310 series only? */ -/* #define VI_Misc1_? 0x40 */ -/* #define VI_Misc1_? 0x80 */ - -/* TW: Bits for Index_VI_Control_Misc2 */ -#define VI_Misc2_Select_Video2 0x01 -#define VI_Misc2_Video2_On_Top 0x02 -/* #define VI_Misc2_? 0x04 */ -#define VI_Misc2_Vertical_Interpol 0x08 -#define VI_Misc2_Dual_Line_Merge 0x10 -#define VI_Misc2_All_Line_Merge 0x20 /* 310 series only? */ -#define VI_Misc2_Auto_Flip_Enable 0x40 /* 300 series only? */ -#define VI_Misc2_Video_Reg_Write_Enable 0x80 /* 310 series only? */ - -/* TW: Bits for Index_VI_Control_Misc3 */ -#define VI_Misc3_Submit_Video_1 0x01 /* AKA "address ready" */ -#define VI_Misc3_Submit_Video_2 0x02 /* AKA "address ready" */ -#define VI_Misc3_Submit_SubPict 0x04 /* AKA "address ready" */ - -/* TW: Values for Index_VI_Key_Overlay_OP (0x2F) */ -#define VI_ROP_Never 0x00 -#define VI_ROP_DestKey 0x03 -#define VI_ROP_Always 0x0F - -/* - * CRT_2 function control register --------------------------------- - */ -#define Index_CRT2_FC_CONTROL 0x00 -#define Index_CRT2_FC_SCREEN_HIGH 0x04 -#define Index_CRT2_FC_SCREEN_MID 0x05 -#define Index_CRT2_FC_SCREEN_LOW 0x06 -#define Index_CRT2_FC_ENABLE_WRITE 0x24 -#define Index_CRT2_FC_VR 0x25 -#define Index_CRT2_FC_VCount 0x27 -#define Index_CRT2_FC_VCount1 0x28 - -#define Index_310_CRT2_FC_VR 0x30 /* d[1] = vertical retrace */ -#define Index_310_CRT2_FC_RT 0x33 /* d[7] = retrace in progress */ - -/* video attributes - these should probably be configurable on the fly - * so users with different desktop sizes can keep - * captured data off the desktop - */ -#define _VINWID 704 -#define _VINHGT _VINHGT_NTSC -#define _VINHGT_NTSC 240 -#define _VINHGT_PAL 290 -#define _VIN_WINDOW (704 * 291 * 2) -#define _VBI_WINDOW (704 * 64 * 2) - -#define _VIN_FIELD_EVEN 1 -#define _VIN_FIELD_ODD 2 -#define _VIN_FIELD_BOTH 4 - - -/* i2c registers (TW; not on 300/310/325 series) */ -#define X_INDEXREG 0x14 -#define X_PORTREG 0x15 -#define X_DATA 0x0f -#define I2C_SCL 0x00 -#define I2C_SDA 0x01 -#define I2C_DELAY 10 - -/* mmio registers for video */ -#define REG_PRIM_CRT_COUNTER 0x8514 - -/* TW: MPEG MMIO registers (630 and later) ----------------------------*/ - -/* Not public (yet?) */ - -#endif /* VIDIX_SIS_REGS_H */
--- a/vidix/drivers/sis_vid.c Sat Mar 31 23:48:48 2007 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1560 +0,0 @@ -/** - VIDIX driver for SiS 300 and 310/325 series chips. - - Copyright 2003 Jake Page, Sugar Media. - - Based on SiS Xv driver: - Copyright 2002-2003 by Thomas Winischhofer, Vienna, Austria. - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - - 2003/10/08 integrated into mplayer/vidix architecture -- Alex Beregszaszi -**/ - -#include <errno.h> -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include <inttypes.h> -#include <unistd.h> - -#include "../vidix.h" -#include "../fourcc.h" -#include "../../libdha/libdha.h" -#include "../../libdha/pci_ids.h" -#include "../../libdha/pci_names.h" -#include "../../config.h" - -#include "sis_regs.h" -#include "sis_defs.h" - - -/** Random defines **/ - -#define WATCHDOG_DELAY 500000 /* Watchdog counter for retrace waiting */ -#define IMAGE_MIN_WIDTH 32 /* Min and max source image sizes */ -#define IMAGE_MIN_HEIGHT 24 -#define IMAGE_MAX_WIDTH 720 -#define IMAGE_MAX_HEIGHT 576 -#define IMAGE_MAX_WIDTH_M650 1920 -#define IMAGE_MAX_HEIGHT_M650 1080 - -#define OVERLAY_MIN_WIDTH 32 /* Minimum overlay sizes */ -#define OVERLAY_MIN_HEIGHT 24 - -#define DISPMODE_SINGLE1 0x1 /* TW: CRT1 only */ -#define DISPMODE_SINGLE2 0x2 /* TW: CRT2 only */ -#define DISPMODE_MIRROR 0x4 /* TW: CRT1 + CRT2 MIRROR */ - -#define VMODE_INTERLACED 0x1 -#define VMODE_DOUBLESCAN 0x2 - -typedef struct { - short x1, y1, x2, y2; -} BoxRec; - -typedef struct { - int pixelFormat; - - uint16_t pitch; - uint16_t origPitch; - - uint8_t keyOP; - uint16_t HUSF; - uint16_t VUSF; - uint8_t IntBit; - uint8_t wHPre; - - uint16_t srcW; - uint16_t srcH; - - BoxRec dstBox; - - uint32_t PSY; - uint32_t PSV; - uint32_t PSU; - uint8_t bobEnable; - - uint8_t contrastCtrl; - uint8_t contrastFactor; - - uint8_t lineBufSize; - - uint8_t(*VBlankActiveFunc) (); - - uint16_t SCREENheight; - -} SISOverlayRec, *SISOverlayPtr; - - -/** static variable definitions **/ -static int sis_probed = 0; -static pciinfo_t pci_info; -unsigned int sis_verbose = 0; - -static void *sis_mem_base; -/* static void *sis_reg_base; */ -unsigned short sis_iobase; - -unsigned int sis_vga_engine = UNKNOWN_VGA; -static unsigned int sis_displaymode = DISPMODE_SINGLE1; -static unsigned int sis_has_two_overlays = 0; -static unsigned int sis_bridge_is_slave = 0; -static unsigned int sis_shift_value = 1; -static unsigned int sis_vmode = 0; -unsigned int sis_vbflags = DISPTYPE_DISP1; -unsigned int sis_overlay_on_crt1 = 1; -unsigned int sis_crt1_off = -1; -unsigned int sis_detected_crt2_devices; -unsigned int sis_force_crt2_type = CRT2_DEFAULT; -unsigned int sis_device_id = -1; - -static int sis_format; -static int sis_Yoff = 0; -static int sis_Voff = 0; -static int sis_Uoff = 0; -static int sis_screen_width = 640; -static int sis_screen_height = 480; - -static int sis_frames[VID_PLAY_MAXFRAMES]; - -static vidix_grkey_t sis_grkey; - -static vidix_capability_t sis_cap = { - "SiS 300/310/325 Video Driver", - "Jake Page", - TYPE_OUTPUT, - {0, 0, 0, 0}, - 2048, - 2048, - 4, - 4, - -1, - FLAG_UPSCALER | FLAG_DOWNSCALER | FLAG_EQUALIZER, - VENDOR_SIS, - -1, - {0, 0, 0, 0} -}; - -vidix_video_eq_t sis_equal = { - VEQ_CAP_BRIGHTNESS | VEQ_CAP_CONTRAST, - 200, 0, 0, 0, 0, 0, 0, 0 -}; - -static unsigned short sis_card_ids[] = { - DEVICE_SIS_300, - DEVICE_SIS_315H, - DEVICE_SIS_315, - DEVICE_SIS_315PRO, - DEVICE_SIS_330, - DEVICE_SIS_540_VGA, - DEVICE_SIS_550_VGA, - DEVICE_SIS_630_VGA, - DEVICE_SIS_650_VGA -}; - -/** function declarations **/ - -extern void sis_init_video_bridge(void); - - -static void set_overlay(SISOverlayPtr pOverlay, int index); -static void close_overlay(void); -static void calc_scale_factor(SISOverlayPtr pOverlay, - int index, int iscrt2); -static void set_line_buf_size(SISOverlayPtr pOverlay); -static void merge_line_buf(int enable); -static void set_format(SISOverlayPtr pOverlay); -static void set_colorkey(void); - -static void set_brightness(uint8_t brightness); -static void set_contrast(uint8_t contrast); -static void set_saturation(char saturation); -static void set_hue(uint8_t hue); -#if 0 -static void set_alpha(uint8_t alpha); -#endif - -/* IO Port access functions */ -static uint8_t getvideoreg(uint8_t reg) -{ - uint8_t ret; - inSISIDXREG(SISVID, reg, ret); - return (ret); -} - -static void setvideoreg(uint8_t reg, uint8_t data) -{ - outSISIDXREG(SISVID, reg, data); -} - -static void setvideoregmask(uint8_t reg, uint8_t data, uint8_t mask) -{ - uint8_t old; - - inSISIDXREG(SISVID, reg, old); - data = (data & mask) | (old & (~mask)); - outSISIDXREG(SISVID, reg, data); -} - -static void setsrregmask(uint8_t reg, uint8_t data, uint8_t mask) -{ - uint8_t old; - - inSISIDXREG(SISSR, reg, old); - data = (data & mask) | (old & (~mask)); - outSISIDXREG(SISSR, reg, data); -} - -/* vblank checking*/ -static uint8_t vblank_active_CRT1(void) -{ - /* this may be too simplistic? */ - return (inSISREG(SISINPSTAT) & 0x08); -} - -static uint8_t vblank_active_CRT2(void) -{ - uint8_t ret; - if (sis_vga_engine == SIS_315_VGA) { - inSISIDXREG(SISPART1, Index_310_CRT2_FC_VR, ret); - } else { - inSISIDXREG(SISPART1, Index_CRT2_FC_VR, ret); - } - return ((ret & 0x02) ^ 0x02); -} - - -unsigned int vixGetVersion(void) -{ - return (VIDIX_VERSION); -} - -static int find_chip(unsigned chip_id) -{ - unsigned i; - for (i = 0; i < sizeof(sis_card_ids) / sizeof(unsigned short); i++) { - if (chip_id == sis_card_ids[i]) - return i; - } - return -1; -} - -int vixProbe(int verbose, int force) -{ - pciinfo_t lst[MAX_PCI_DEVICES]; - unsigned i, num_pci; - int err; - - sis_verbose = verbose; - force = force; - err = pci_scan(lst, &num_pci); - if (err) { - printf("[SiS] Error occurred during pci scan: %s\n", strerror(err)); - return err; - } else { - err = ENXIO; - for (i = 0; i < num_pci; i++) { - if (lst[i].vendor == VENDOR_SIS) { - int idx; - const char *dname; - idx = find_chip(lst[i].device); - if (idx == -1) - continue; - dname = pci_device_name(VENDOR_SIS, lst[i].device); - dname = dname ? dname : "Unknown chip"; - if (sis_verbose > 0) - printf("[SiS] Found chip: %s (0x%X)\n", - dname, lst[i].device); - sis_device_id = sis_cap.device_id = lst[i].device; - err = 0; - memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); - - sis_has_two_overlays = 0; - switch (sis_cap.device_id) { - case DEVICE_SIS_300: - case DEVICE_SIS_630_VGA: - sis_has_two_overlays = 1; - case DEVICE_SIS_540_VGA: - sis_vga_engine = SIS_300_VGA; - break; - case DEVICE_SIS_330: - case DEVICE_SIS_550_VGA: - sis_has_two_overlays = 1; - case DEVICE_SIS_315H: - case DEVICE_SIS_315: - case DEVICE_SIS_315PRO: - case DEVICE_SIS_650_VGA: - /* M650 & 651 have 2 overlays */ - /* JCP: I think this works, but not really tested yet */ - { - unsigned char CR5F; - unsigned char tempreg1, tempreg2; - - inSISIDXREG(SISCR, 0x5F, CR5F); - CR5F &= 0xf0; - andSISIDXREG(SISCR, 0x5c, 0x07); - inSISIDXREG(SISCR, 0x5c, tempreg1); - tempreg1 &= 0xf8; - setSISIDXREG(SISCR, 0x5c, 0x07, 0xf8); - inSISIDXREG(SISCR, 0x5c, tempreg2); - tempreg2 &= 0xf8; - if ((!tempreg1) || (tempreg2)) { - if (CR5F & 0x80) { - sis_has_two_overlays = 1; - } - } else { - sis_has_two_overlays = 1; /* ? */ - } - if (sis_has_two_overlays) { - if (sis_verbose > 0) - printf - ("[SiS] detected M650/651 with 2 overlays\n"); - } - } - sis_vga_engine = SIS_315_VGA; - break; - default: - /* should never get here */ - sis_vga_engine = UNKNOWN_VGA; - break; - } - } - } - } - if (err && sis_verbose) { - printf("[SiS] Can't find chip\n"); - } else { - sis_probed = 1; - } - - return err; -} - -int vixInit(void) -{ - uint8_t sr_data, cr_data, cr_data2; - char *env_overlay_crt; - - if (!sis_probed) { - printf("[SiS] driver was not probed but is being initialized\n"); - return (EINTR); - } - - /* JCP: this is WRONG. Need to coordinate w/ sisfb to use correct mem */ - /* map 16MB scary hack for now. */ - sis_mem_base = map_phys_mem(pci_info.base0, 0x1000000); - /* sis_reg_base = map_phys_mem(pci_info.base1, 0x20000); */ - sis_iobase = pci_info.base2 & 0xFFFC; - - /* would like to use fb ioctl - or some other method - here to get - current resolution. */ - inSISIDXREG(SISCR, 0x12, cr_data); - inSISIDXREG(SISCR, 0x07, cr_data2); - sis_screen_height = - ((cr_data & 0xff) | ((uint16_t) (cr_data2 & 0x02) << 7) | - ((uint16_t) (cr_data2 & 0x40) << 3) | ((uint16_t) (cr_data & 0x02) - << 9)) + 1; - - inSISIDXREG(SISSR, 0x0b, sr_data); - inSISIDXREG(SISCR, 0x01, cr_data); - sis_screen_width = (((cr_data & 0xff) | - ((uint16_t) (sr_data & 0x0C) << 6)) + 1) * 8; - - inSISIDXREG(SISSR, Index_SR_Graphic_Mode, sr_data); - if (sr_data & 0x20) /* interlaced mode */ - sis_vmode |= VMODE_INTERLACED; - -#if 0 /* getting back false data here... */ - /* CR9 bit 7 set = double scan active */ - inSISIDXREG(SISCR, 0x09, cr_data); - if (cr_data & 0x40) { - sis_vmode |= VMODE_DOUBLESCAN; - } -#endif - - /* JCP: eventually I'd like to replace this with a call to sisfb - SISFB_GET_INFO ioctl to get video bridge info. Not for now, - since it requires a very new and not widely distributed version. */ - sis_init_video_bridge(); - - env_overlay_crt = getenv("VIDIX_CRT"); - if (env_overlay_crt) { - int crt = atoi(env_overlay_crt); - if (crt == 1 || crt == 2) { - sis_overlay_on_crt1 = (crt == 1); - if (sis_verbose > 0) { - printf - ("[SiS] override: using overlay on CRT%d from VIDIX_CRT\n", - crt); - } - } - } - - return 0; -} - -void vixDestroy(void) -{ - /* unmap_phys_mem(sis_reg_base, 0x20000); */ - /* JCP: see above, hence also a hack. */ - unmap_phys_mem(sis_mem_base, 0x1000000); -} - -int vixGetCapability(vidix_capability_t * to) -{ - memcpy(to, &sis_cap, sizeof(vidix_capability_t)); - return 0; -} - -static int is_supported_fourcc(uint32_t fourcc) -{ - switch (fourcc) { - case IMGFMT_YV12: - case IMGFMT_I420: - case IMGFMT_UYVY: - case IMGFMT_YUY2: - case IMGFMT_RGB15: - case IMGFMT_RGB16: - return 1; - default: - return 0; - } -} - -int vixQueryFourcc(vidix_fourcc_t * to) -{ - if (is_supported_fourcc(to->fourcc)) { - to->depth = VID_DEPTH_8BPP | VID_DEPTH_16BPP | VID_DEPTH_32BPP; - to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; - return 0; - } else - to->depth = to->flags = 0; - return ENOSYS; -} - -static int bridge_in_slave_mode(void) -{ - unsigned char usScratchP1_00; - - if (!(sis_vbflags & VB_VIDEOBRIDGE)) - return 0; - - inSISIDXREG(SISPART1, 0x00, usScratchP1_00); - if (((sis_vga_engine == SIS_300_VGA) - && (usScratchP1_00 & 0xa0) == 0x20) - || ((sis_vga_engine == SIS_315_VGA) - && (usScratchP1_00 & 0x50) == 0x10)) { - return 1; - } else { - return 0; - } -} - -/* This does not handle X dual head mode, since 1) vidix doesn't support it - and 2) it doesn't make sense for other gfx drivers */ -static void set_dispmode(void) -{ - sis_bridge_is_slave = 0; - - if (bridge_in_slave_mode()) - sis_bridge_is_slave = 1; - - if ((sis_vbflags & VB_DISPMODE_MIRROR) || - (sis_bridge_is_slave && (sis_vbflags & DISPTYPE_DISP2))) { - if (sis_has_two_overlays) - sis_displaymode = DISPMODE_MIRROR; /* TW: CRT1+CRT2 (2 overlays) */ - else if (!sis_overlay_on_crt1) - sis_displaymode = DISPMODE_SINGLE2; - else - sis_displaymode = DISPMODE_SINGLE1; - } else { - if (sis_vbflags & DISPTYPE_DISP1) { - sis_displaymode = DISPMODE_SINGLE1; /* TW: CRT1 only */ - } else { - sis_displaymode = DISPMODE_SINGLE2; /* TW: CRT2 only */ - } - } -} - -static void set_disptype_regs(void) -{ - switch (sis_displaymode) { - case DISPMODE_SINGLE1: /* TW: CRT1 only */ - if (sis_verbose > 2) { - printf("[SiS] Setting up overlay on CRT1\n"); - } - if (sis_has_two_overlays) { - setsrregmask(0x06, 0x00, 0xc0); - setsrregmask(0x32, 0x00, 0xc0); - } else { - setsrregmask(0x06, 0x00, 0xc0); - setsrregmask(0x32, 0x00, 0xc0); - } - break; - case DISPMODE_SINGLE2: /* TW: CRT2 only */ - if (sis_verbose > 2) { - printf("[SiS] Setting up overlay on CRT2\n"); - } - if (sis_has_two_overlays) { - setsrregmask(0x06, 0x80, 0xc0); - setsrregmask(0x32, 0x80, 0xc0); - } else { - setsrregmask(0x06, 0x40, 0xc0); - setsrregmask(0x32, 0x40, 0xc0); - } - break; - case DISPMODE_MIRROR: /* TW: CRT1 + CRT2 */ - default: - if (sis_verbose > 2) { - printf("[SiS] Setting up overlay on CRT1 AND CRT2!\n"); - } - setsrregmask(0x06, 0x80, 0xc0); - setsrregmask(0x32, 0x80, 0xc0); - break; - } -} - -static void init_overlay(void) -{ - /* Initialize first overlay (CRT1) */ - - /* Write-enable video registers */ - setvideoregmask(Index_VI_Control_Misc2, 0x80, 0x81); - - /* Disable overlay */ - setvideoregmask(Index_VI_Control_Misc0, 0x00, 0x02); - - /* Disable bobEnable */ - setvideoregmask(Index_VI_Control_Misc1, 0x02, 0x02); - - /* Reset scale control and contrast */ - setvideoregmask(Index_VI_Scale_Control, 0x60, 0x60); - setvideoregmask(Index_VI_Contrast_Enh_Ctrl, 0x04, 0x1F); - - setvideoreg(Index_VI_Disp_Y_Buf_Preset_Low, 0x00); - setvideoreg(Index_VI_Disp_Y_Buf_Preset_Middle, 0x00); - setvideoreg(Index_VI_UV_Buf_Preset_Low, 0x00); - setvideoreg(Index_VI_UV_Buf_Preset_Middle, 0x00); - setvideoreg(Index_VI_Disp_Y_UV_Buf_Preset_High, 0x00); - setvideoreg(Index_VI_Play_Threshold_Low, 0x00); - setvideoreg(Index_VI_Play_Threshold_High, 0x00); - - /* may not want to init these here, could already be set to other - values by app? */ - setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x01); - setvideoregmask(Index_VI_Contrast_Enh_Ctrl, 0x04, 0x07); - setvideoreg(Index_VI_Brightness, 0x20); - if (sis_vga_engine == SIS_315_VGA) { - setvideoreg(Index_VI_Hue, 0x00); - setvideoreg(Index_VI_Saturation, 0x00); - } - - /* Initialize second overlay (CRT2) */ - if (sis_has_two_overlays) { - /* Write-enable video registers */ - setvideoregmask(Index_VI_Control_Misc2, 0x81, 0x81); - - /* Disable overlay */ - setvideoregmask(Index_VI_Control_Misc0, 0x00, 0x02); - - /* Disable bobEnable */ - setvideoregmask(Index_VI_Control_Misc1, 0x02, 0x02); - - /* Reset scale control and contrast */ - setvideoregmask(Index_VI_Scale_Control, 0x60, 0x60); - setvideoregmask(Index_VI_Contrast_Enh_Ctrl, 0x04, 0x1F); - - setvideoreg(Index_VI_Disp_Y_Buf_Preset_Low, 0x00); - setvideoreg(Index_VI_Disp_Y_Buf_Preset_Middle, 0x00); - setvideoreg(Index_VI_UV_Buf_Preset_Low, 0x00); - setvideoreg(Index_VI_UV_Buf_Preset_Middle, 0x00); - setvideoreg(Index_VI_Disp_Y_UV_Buf_Preset_High, 0x00); - setvideoreg(Index_VI_Play_Threshold_Low, 0x00); - setvideoreg(Index_VI_Play_Threshold_High, 0x00); - - setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x01); - setvideoregmask(Index_VI_Contrast_Enh_Ctrl, 0x04, 0x07); - setvideoreg(Index_VI_Brightness, 0x20); - if (sis_vga_engine == SIS_315_VGA) { - setvideoreg(Index_VI_Hue, 0x00); - setvideoreg(Index_VI_Saturation, 0x00); - } - } -} - -int vixConfigPlayback(vidix_playback_t * info) -{ - SISOverlayRec overlay; - int srcOffsetX = 0, srcOffsetY = 0; - int sx, sy; - int index = 0, iscrt2 = 0; - int total_size; - - short src_w, drw_w; - short src_h, drw_h; - short src_x, drw_x; - short src_y, drw_y; - long dga_offset; - int pitch; - unsigned int i; - - if (!is_supported_fourcc(info->fourcc)) - return -1; - - /* set chipset/engine.dependent config info */ - /* which CRT to use, etc.? */ - switch (sis_vga_engine) { - case SIS_315_VGA: - sis_shift_value = 1; - sis_equal.cap |= VEQ_CAP_SATURATION | VEQ_CAP_HUE; - break; - case SIS_300_VGA: - default: - sis_shift_value = 2; - break; - } - - sis_displaymode = DISPMODE_SINGLE1; /* xV driver code in set_dispmode() */ - set_dispmode(); - - set_disptype_regs(); - - init_overlay(); - - /* get basic dimension info */ - src_x = info->src.x; - src_y = info->src.y; - src_w = info->src.w; - src_h = info->src.h; - - drw_x = info->dest.x; - drw_y = info->dest.y; - drw_w = info->dest.w; - drw_h = info->dest.h; - - switch (info->fourcc) { - case IMGFMT_YV12: - case IMGFMT_I420: - pitch = (src_w + 7) & ~7; - total_size = (pitch * src_h * 3) >> 1; - break; - case IMGFMT_YUY2: - case IMGFMT_UYVY: - case IMGFMT_RGB15: - case IMGFMT_RGB16: - pitch = ((src_w << 1) + 3) & ~3; - total_size = pitch * src_h; - break; - default: - return -1; - } - - /* "allocate" memory for overlay! */ - /* start at 8MB = sisfb's "dri reserved space" - - really shouldn't hardcode though */ - /* XXX: JCP - this can use the sisfb FBIO_ALLOC ioctl to safely - allocate "video heap" memory... */ - dga_offset = 0x800000; - - /* use 7MB for now. need to calc/get real info from sisfb? */ - /* this can result in a LOT of frames - probably not necessary */ - info->num_frames = 0x700000 / (total_size * 2); - if (info->num_frames > VID_PLAY_MAXFRAMES) - info->num_frames = VID_PLAY_MAXFRAMES; - - info->dga_addr = sis_mem_base + dga_offset; - info->dest.pitch.y = 16; - info->dest.pitch.u = 16; - info->dest.pitch.v = 16; - info->offset.y = 0; - info->offset.u = 0; - info->offset.v = 0; - info->frame_size = (total_size * 2); /* why times 2 ? */ - for (i = 0; i < info->num_frames; i++) { - info->offsets[i] = info->frame_size * i; - /* save ptrs to mem buffers */ - sis_frames[i] = (dga_offset + info->offsets[i]); - } - - memset(&overlay, 0, sizeof(overlay)); - overlay.pixelFormat = sis_format = info->fourcc; - overlay.pitch = overlay.origPitch = pitch; - - - overlay.keyOP = (sis_grkey.ckey.op == CKEY_TRUE ? - VI_ROP_DestKey : VI_ROP_Always); - - overlay.bobEnable = 0x00; - - overlay.SCREENheight = sis_screen_height; - - /* probably will not support X virtual screen > phys very well? */ - overlay.dstBox.x1 = drw_x; /* - pScrn->frameX0; */ - overlay.dstBox.x2 = drw_x + drw_w; /* - pScrn->frameX0; ??? */ - overlay.dstBox.y1 = drw_y; /* - pScrn->frameY0; */ - overlay.dstBox.y2 = drw_y + drw_h; /* - pScrn->frameY0; ??? */ - - if ((overlay.dstBox.x1 > overlay.dstBox.x2) || - (overlay.dstBox.y1 > overlay.dstBox.y2)) - return -1; - - if ((overlay.dstBox.x2 < 0) || (overlay.dstBox.y2 < 0)) - return -1; - - if (overlay.dstBox.x1 < 0) { - srcOffsetX = src_w * (-overlay.dstBox.x1) / drw_w; - overlay.dstBox.x1 = 0; - } - if (overlay.dstBox.y1 < 0) { - srcOffsetY = src_h * (-overlay.dstBox.y1) / drw_h; - overlay.dstBox.y1 = 0; - } - - switch (info->fourcc) { - case IMGFMT_YV12: - info->dest.pitch.y = 16; - sx = (src_x + srcOffsetX) & ~7; - sy = (src_y + srcOffsetY) & ~1; - info->offset.y = sis_Yoff = sx + sy * pitch; - /* JCP: NOTE reversed u & v here! Not sure why this is needed. - maybe mplayer & sis define U & V differently?? */ - info->offset.u = sis_Voff = - src_h * pitch + ((sx + sy * pitch / 2) >> 1); - info->offset.v = sis_Uoff = - src_h * pitch * 5 / 4 + ((sx + sy * pitch / 2) >> 1); - - overlay.PSY = (sis_frames[0] + sis_Yoff) >> sis_shift_value; - overlay.PSV = (sis_frames[0] + sis_Voff) >> sis_shift_value; - overlay.PSU = (sis_frames[0] + sis_Uoff) >> sis_shift_value; - break; - case IMGFMT_I420: - sx = (src_x + srcOffsetX) & ~7; - sy = (src_y + srcOffsetY) & ~1; - info->offset.y = sis_Yoff = sx + sy * pitch; - /* JCP: see above... */ - info->offset.u = sis_Voff = - src_h * pitch * 5 / 4 + ((sx + sy * pitch / 2) >> 1); - info->offset.v = sis_Uoff = - src_h * pitch + ((sx + sy * pitch / 2) >> 1); - - overlay.PSY = (sis_frames[0] + sis_Yoff) >> sis_shift_value; - overlay.PSV = (sis_frames[0] + sis_Voff) >> sis_shift_value; - overlay.PSU = (sis_frames[0] + sis_Uoff) >> sis_shift_value; - break; - case IMGFMT_YUY2: - case IMGFMT_UYVY: - case IMGFMT_RGB16: - case IMGFMT_RGB15: - default: - sx = (src_x + srcOffsetX) & ~1; - sy = (src_y + srcOffsetY); - info->offset.y = sis_Yoff = sx * 2 + sy * pitch; - - overlay.PSY = (sis_frames[0] + sis_Yoff) >> sis_shift_value; - break; - } - - /* FIXME: is it possible that srcW < 0? */ - overlay.srcW = src_w - (sx - src_x); - overlay.srcH = src_h - (sy - src_y); - - /* JCP: what to do about this? */ -#if 0 - if ((pPriv->oldx1 != overlay.dstBox.x1) || - (pPriv->oldx2 != overlay.dstBox.x2) || - (pPriv->oldy1 != overlay.dstBox.y1) || - (pPriv->oldy2 != overlay.dstBox.y2)) { - pPriv->mustwait = 1; - pPriv->oldx1 = overlay.dstBox.x1; - pPriv->oldx2 = overlay.dstBox.x2; - pPriv->oldy1 = overlay.dstBox.y1; - pPriv->oldy2 = overlay.dstBox.y2; - } -#endif - - /* set merge line buffer */ - merge_line_buf(overlay.srcW > 384); - - /* calculate line buffer length */ - set_line_buf_size(&overlay); - - if (sis_displaymode == DISPMODE_SINGLE2) { - if (sis_has_two_overlays) { - /* TW: On chips with two overlays we use - * overlay 2 for CRT2 */ - index = 1; - iscrt2 = 1; - } else { - /* TW: On chips with only one overlay we - * use that only overlay for CRT2 */ - index = 0; - iscrt2 = 1; - } - overlay.VBlankActiveFunc = vblank_active_CRT2; - /* overlay.GetScanLineFunc = get_scanline_CRT2; */ - } else { - index = 0; - iscrt2 = 0; - overlay.VBlankActiveFunc = vblank_active_CRT1; - /* overlay.GetScanLineFunc = get_scanline_CRT1; */ - } - - /* calc scale factor (to use below) */ - calc_scale_factor(&overlay, index, iscrt2); - - /* Select video1 (used for CRT1) or video2 (used for CRT2) */ - setvideoregmask(Index_VI_Control_Misc2, index, 0x01); - - set_format(&overlay); - - set_colorkey(); - - vixPlaybackSetEq(&sis_equal); - - /* set up video overlay registers */ - set_overlay(&overlay, index); - - /* prevent badness if bits are not at default setting */ - setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x01); - setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x04); - - /* JCP: Xv driver implementation loops back over above code to - setup mirror CRT2 */ - - return 0; -} - -int vixPlaybackOn(void) -{ - setvideoregmask(Index_VI_Control_Misc0, 0x02, 0x02); - return 0; -} - -int vixPlaybackOff(void) -{ - unsigned char sridx, cridx; - sridx = inSISREG(SISSR); - cridx = inSISREG(SISCR); - close_overlay(); - outSISREG(SISSR, sridx); - outSISREG(SISCR, cridx); - - return 0; -} - -int vixPlaybackFrameSelect(unsigned int frame) -{ - uint8_t data; - int index = 0; - uint32_t PSY; - - if (sis_displaymode == DISPMODE_SINGLE2 && sis_has_two_overlays) { - index = 1; - } - - PSY = (sis_frames[frame] + sis_Yoff) >> sis_shift_value; - - /* Unlock address registers */ - data = getvideoreg(Index_VI_Control_Misc1); - setvideoreg(Index_VI_Control_Misc1, data | 0x20); - /* TEST: Is this required? */ - setvideoreg(Index_VI_Control_Misc1, data | 0x20); - /* TEST end */ - /* TEST: Is this required? */ - if (sis_vga_engine == SIS_315_VGA) - setvideoreg(Index_VI_Control_Misc3, 0x00); - /* TEST end */ - - /* set Y start address */ - setvideoreg(Index_VI_Disp_Y_Buf_Start_Low, (uint8_t) (PSY)); - setvideoreg(Index_VI_Disp_Y_Buf_Start_Middle, (uint8_t) ((PSY) >> 8)); - setvideoreg(Index_VI_Disp_Y_Buf_Start_High, (uint8_t) ((PSY) >> 16)); - /* set 310/325 series overflow bits for Y plane */ - if (sis_vga_engine == SIS_315_VGA) { - setvideoreg(Index_VI_Y_Buf_Start_Over, - ((uint8_t) ((PSY) >> 24) & 0x01)); - } - - /* Set U/V data if using plane formats */ - if ((sis_format == IMGFMT_YV12) || (sis_format == IMGFMT_I420)) { - - uint32_t PSU, PSV; - - PSU = (sis_frames[frame] + sis_Uoff) >> sis_shift_value; - PSV = (sis_frames[frame] + sis_Voff) >> sis_shift_value; - - /* set U/V start address */ - setvideoreg(Index_VI_U_Buf_Start_Low, (uint8_t) PSU); - setvideoreg(Index_VI_U_Buf_Start_Middle, (uint8_t) (PSU >> 8)); - setvideoreg(Index_VI_U_Buf_Start_High, (uint8_t) (PSU >> 16)); - - setvideoreg(Index_VI_V_Buf_Start_Low, (uint8_t) PSV); - setvideoreg(Index_VI_V_Buf_Start_Middle, (uint8_t) (PSV >> 8)); - setvideoreg(Index_VI_V_Buf_Start_High, (uint8_t) (PSV >> 16)); - - /* 310/325 series overflow bits */ - if (sis_vga_engine == SIS_315_VGA) { - setvideoreg(Index_VI_U_Buf_Start_Over, - ((uint8_t) (PSU >> 24) & 0x01)); - setvideoreg(Index_VI_V_Buf_Start_Over, - ((uint8_t) (PSV >> 24) & 0x01)); - } - } - - if (sis_vga_engine == SIS_315_VGA) { - /* Trigger register copy for 310 series */ - setvideoreg(Index_VI_Control_Misc3, 1 << index); - } - - /* Lock the address registers */ - setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x20); - - return 0; -} - -int vixGetGrKeys(vidix_grkey_t * grkey) -{ - memcpy(grkey, &sis_grkey, sizeof(vidix_grkey_t)); - return 0; -} - -int vixSetGrKeys(const vidix_grkey_t * grkey) -{ - memcpy(&sis_grkey, grkey, sizeof(vidix_grkey_t)); - set_colorkey(); - return 0; -} - -int vixPlaybackGetEq(vidix_video_eq_t * eq) -{ - memcpy(eq, &sis_equal, sizeof(vidix_video_eq_t)); - return 0; -} - -int vixPlaybackSetEq(const vidix_video_eq_t * eq) -{ - int br, sat, cr, hue; - if (eq->cap & VEQ_CAP_BRIGHTNESS) - sis_equal.brightness = eq->brightness; - if (eq->cap & VEQ_CAP_CONTRAST) - sis_equal.contrast = eq->contrast; - if (eq->cap & VEQ_CAP_SATURATION) - sis_equal.saturation = eq->saturation; - if (eq->cap & VEQ_CAP_HUE) - sis_equal.hue = eq->hue; - if (eq->cap & VEQ_CAP_RGB_INTENSITY) { - sis_equal.red_intensity = eq->red_intensity; - sis_equal.green_intensity = eq->green_intensity; - sis_equal.blue_intensity = eq->blue_intensity; - } - sis_equal.flags = eq->flags; - - cr = (sis_equal.contrast + 1000) * 7 / 2000; - if (cr < 0) - cr = 0; - if (cr > 7) - cr = 7; - - br = sis_equal.brightness * 127 / 1000; - if (br < -128) - br = -128; - if (br > 127) - br = 127; - - sat = (sis_equal.saturation * 7) / 1000; - if (sat < -7) - sat = -7; - if (sat > 7) - sat = 7; - - hue = sis_equal.hue * 7 / 1000; - if (hue < -8) - hue = -8; - if (hue > 7) - hue = 7; - - set_brightness(br); - set_contrast(cr); - if (sis_vga_engine == SIS_315_VGA) { - set_saturation(sat); - set_hue(hue); - } - - return 0; -} - -static void set_overlay(SISOverlayPtr pOverlay, int index) -{ - uint16_t pitch = 0; - uint8_t h_over = 0, v_over = 0; - uint16_t top, bottom, left, right; - uint16_t screenX = sis_screen_width; - uint16_t screenY = sis_screen_height; - uint8_t data; - uint32_t watchdog; - - top = pOverlay->dstBox.y1; - bottom = pOverlay->dstBox.y2; - if (bottom > screenY) { - bottom = screenY; - } - - left = pOverlay->dstBox.x1; - right = pOverlay->dstBox.x2; - if (right > screenX) { - right = screenX; - } - - /* JCP: these aren't really tested... */ - /* TW: DoubleScan modes require Y coordinates * 2 */ - if (sis_vmode & VMODE_DOUBLESCAN) { - top <<= 1; - bottom <<= 1; - } - /* TW: Interlace modes require Y coordinates / 2 */ - if (sis_vmode & VMODE_INTERLACED) { - top >>= 1; - bottom >>= 1; - } - - h_over = (((left >> 8) & 0x0f) | ((right >> 4) & 0xf0)); - v_over = (((top >> 8) & 0x0f) | ((bottom >> 4) & 0xf0)); - - pitch = pOverlay->pitch >> sis_shift_value; - - /* set line buffer size */ - setvideoreg(Index_VI_Line_Buffer_Size, pOverlay->lineBufSize); - - /* set color key mode */ - setvideoregmask(Index_VI_Key_Overlay_OP, pOverlay->keyOP, 0x0F); - - /* TW: We don't have to wait for vertical retrace in all cases */ - /* JCP: be safe for now. */ - if (1 /*pPriv->mustwait */ ) { - watchdog = WATCHDOG_DELAY; - while (pOverlay->VBlankActiveFunc() && --watchdog); - watchdog = WATCHDOG_DELAY; - while ((!pOverlay->VBlankActiveFunc()) && --watchdog); - if (!watchdog && sis_verbose > 0) { - printf("[SiS]: timed out waiting for vertical retrace\n"); - } - } - - /* Unlock address registers */ - data = getvideoreg(Index_VI_Control_Misc1); - setvideoreg(Index_VI_Control_Misc1, data | 0x20); - /* TEST: Is this required? */ - setvideoreg(Index_VI_Control_Misc1, data | 0x20); - /* TEST end */ - - /* TEST: Is this required? */ - if (sis_vga_engine == SIS_315_VGA) - setvideoreg(Index_VI_Control_Misc3, 0x00); - /* TEST end */ - - /* Set Y buf pitch */ - setvideoreg(Index_VI_Disp_Y_Buf_Pitch_Low, (uint8_t) (pitch)); - setvideoregmask(Index_VI_Disp_Y_UV_Buf_Pitch_Middle, - (uint8_t) (pitch >> 8), 0x0f); - - /* Set Y start address */ - setvideoreg(Index_VI_Disp_Y_Buf_Start_Low, (uint8_t) (pOverlay->PSY)); - setvideoreg(Index_VI_Disp_Y_Buf_Start_Middle, - (uint8_t) ((pOverlay->PSY) >> 8)); - setvideoreg(Index_VI_Disp_Y_Buf_Start_High, - (uint8_t) ((pOverlay->PSY) >> 16)); - - /* set 310/325 series overflow bits for Y plane */ - if (sis_vga_engine == SIS_315_VGA) { - setvideoreg(Index_VI_Disp_Y_Buf_Pitch_High, - (uint8_t) (pitch >> 12)); - setvideoreg(Index_VI_Y_Buf_Start_Over, - ((uint8_t) ((pOverlay->PSY) >> 24) & 0x01)); - } - - /* Set U/V data if using plane formats */ - if ((pOverlay->pixelFormat == IMGFMT_YV12) || - (pOverlay->pixelFormat == IMGFMT_I420)) { - - uint32_t PSU, PSV; - - PSU = pOverlay->PSU; - PSV = pOverlay->PSV; - - /* Set U/V pitch */ - setvideoreg(Index_VI_Disp_UV_Buf_Pitch_Low, - (uint8_t) (pitch >> 1)); - setvideoregmask(Index_VI_Disp_Y_UV_Buf_Pitch_Middle, - (uint8_t) (pitch >> 5), 0xf0); - - /* set U/V start address */ - setvideoreg(Index_VI_U_Buf_Start_Low, (uint8_t) PSU); - setvideoreg(Index_VI_U_Buf_Start_Middle, (uint8_t) (PSU >> 8)); - setvideoreg(Index_VI_U_Buf_Start_High, (uint8_t) (PSU >> 16)); - - setvideoreg(Index_VI_V_Buf_Start_Low, (uint8_t) PSV); - setvideoreg(Index_VI_V_Buf_Start_Middle, (uint8_t) (PSV >> 8)); - setvideoreg(Index_VI_V_Buf_Start_High, (uint8_t) (PSV >> 16)); - - /* 310/325 series overflow bits */ - if (sis_vga_engine == SIS_315_VGA) { - setvideoreg(Index_VI_Disp_UV_Buf_Pitch_High, - (uint8_t) (pitch >> 13)); - setvideoreg(Index_VI_U_Buf_Start_Over, - ((uint8_t) (PSU >> 24) & 0x01)); - setvideoreg(Index_VI_V_Buf_Start_Over, - ((uint8_t) (PSV >> 24) & 0x01)); - } - } - - if (sis_vga_engine == SIS_315_VGA) { - /* Trigger register copy for 310 series */ - setvideoreg(Index_VI_Control_Misc3, 1 << index); - } - - /* set scale factor */ - setvideoreg(Index_VI_Hor_Post_Up_Scale_Low, - (uint8_t) (pOverlay->HUSF)); - setvideoreg(Index_VI_Hor_Post_Up_Scale_High, - (uint8_t) ((pOverlay->HUSF) >> 8)); - setvideoreg(Index_VI_Ver_Up_Scale_Low, (uint8_t) (pOverlay->VUSF)); - setvideoreg(Index_VI_Ver_Up_Scale_High, - (uint8_t) ((pOverlay->VUSF) >> 8)); - - setvideoregmask(Index_VI_Scale_Control, (pOverlay->IntBit << 3) - | (pOverlay->wHPre), 0x7f); - - /* set destination window position */ - setvideoreg(Index_VI_Win_Hor_Disp_Start_Low, (uint8_t) left); - setvideoreg(Index_VI_Win_Hor_Disp_End_Low, (uint8_t) right); - setvideoreg(Index_VI_Win_Hor_Over, (uint8_t) h_over); - - setvideoreg(Index_VI_Win_Ver_Disp_Start_Low, (uint8_t) top); - setvideoreg(Index_VI_Win_Ver_Disp_End_Low, (uint8_t) bottom); - setvideoreg(Index_VI_Win_Ver_Over, (uint8_t) v_over); - - setvideoregmask(Index_VI_Control_Misc1, pOverlay->bobEnable, 0x1a); - - /* Lock the address registers */ - setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x20); -} - - -/* TW: Overlay MUST NOT be switched off while beam is over it */ -static void close_overlay(void) -{ - uint32_t watchdog; - - if ((sis_displaymode == DISPMODE_SINGLE2) || - (sis_displaymode == DISPMODE_MIRROR)) { - if (sis_has_two_overlays) { - setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x01); - watchdog = WATCHDOG_DELAY; - while (vblank_active_CRT2() && --watchdog); - watchdog = WATCHDOG_DELAY; - while ((!vblank_active_CRT2()) && --watchdog); - setvideoregmask(Index_VI_Control_Misc0, 0x00, 0x02); - watchdog = WATCHDOG_DELAY; - while (vblank_active_CRT2() && --watchdog); - watchdog = WATCHDOG_DELAY; - while ((!vblank_active_CRT2()) && --watchdog); - } else if (sis_displaymode == DISPMODE_SINGLE2) { - setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x01); - watchdog = WATCHDOG_DELAY; - while (vblank_active_CRT1() && --watchdog); - watchdog = WATCHDOG_DELAY; - while ((!vblank_active_CRT1()) && --watchdog); - setvideoregmask(Index_VI_Control_Misc0, 0x00, 0x02); - watchdog = WATCHDOG_DELAY; - while (vblank_active_CRT1() && --watchdog); - watchdog = WATCHDOG_DELAY; - while ((!vblank_active_CRT1()) && --watchdog); - } - } - if ((sis_displaymode == DISPMODE_SINGLE1) || - (sis_displaymode == DISPMODE_MIRROR)) { - setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x01); - watchdog = WATCHDOG_DELAY; - while (vblank_active_CRT1() && --watchdog); - watchdog = WATCHDOG_DELAY; - while ((!vblank_active_CRT1()) && --watchdog); - setvideoregmask(Index_VI_Control_Misc0, 0x00, 0x02); - watchdog = WATCHDOG_DELAY; - while (vblank_active_CRT1() && --watchdog); - watchdog = WATCHDOG_DELAY; - while ((!vblank_active_CRT1()) && --watchdog); - } -} - - -static void -calc_scale_factor(SISOverlayPtr pOverlay, int index, int iscrt2) -{ - uint32_t i = 0, mult = 0; - int flag = 0; - - int dstW = pOverlay->dstBox.x2 - pOverlay->dstBox.x1; - int dstH = pOverlay->dstBox.y2 - pOverlay->dstBox.y1; - int srcW = pOverlay->srcW; - int srcH = pOverlay->srcH; - /* uint16_t LCDheight = pSiS->LCDheight; */ - int srcPitch = pOverlay->origPitch; - int origdstH = dstH; - - /* get rid of warnings for now */ - index = index; - iscrt2 = iscrt2; - -#if 0 /* JCP: don't bother with this for now. */ - /* TW: Stretch image due to idiotic LCD "auto"-scaling on LVDS (and 630+301B) */ - if (pSiS->VBFlags & CRT2_LCD) { - if (sis_bridge_is_slave) { - if (pSiS->VBFlags & VB_LVDS) { - dstH = (dstH * LCDheight) / pOverlay->SCREENheight; - } else if ((sis_vga_engine == SIS_300_VGA) && - (pSiS-> - VBFlags & (VB_301B | VB_302B | VB_301LV | - VB_302LV))) { - dstH = (dstH * LCDheight) / pOverlay->SCREENheight; - } - } else if (iscrt2) { - if (pSiS->VBFlags & VB_LVDS) { - dstH = (dstH * LCDheight) / pOverlay->SCREENheight; - if (sis_displaymode == DISPMODE_MIRROR) - flag = 1; - } else if ((sis_vga_engine == SIS_300_VGA) && - (pSiS-> - VBFlags & (VB_301B | VB_302B | VB_301LV | - VB_302LV))) { - dstH = (dstH * LCDheight) / pOverlay->SCREENheight; - if (sis_displaymode == DISPMODE_MIRROR) - flag = 1; - } - } - } -#endif - - /* TW: For double scan modes, we need to double the height - * (Perhaps we also need to scale LVDS, but I'm not sure.) - * On 310/325 series, we need to double the width as well. - * Interlace mode vice versa. - */ - if (sis_vmode & VMODE_DOUBLESCAN) { - dstH = origdstH << 1; - flag = 0; - if (sis_vga_engine == SIS_315_VGA) { - dstW <<= 1; - } - } - if (sis_vmode & VMODE_INTERLACED) { - dstH = origdstH >> 1; - flag = 0; - } - - if (dstW < OVERLAY_MIN_WIDTH) - dstW = OVERLAY_MIN_WIDTH; - if (dstW == srcW) { - pOverlay->HUSF = 0x00; - pOverlay->IntBit = 0x05; - pOverlay->wHPre = 0; - } else if (dstW > srcW) { - dstW += 2; - pOverlay->HUSF = (srcW << 16) / dstW; - pOverlay->IntBit = 0x04; - pOverlay->wHPre = 0; - } else { - int tmpW = dstW; - - /* TW: It seems, the hardware can't scale below factor .125 (=1/8) if the - pitch isn't a multiple of 256. - TODO: Test this on the 310/325 series! - */ - if ((srcPitch % 256) || (srcPitch < 256)) { - if (((dstW * 1000) / srcW) < 125) - dstW = tmpW = ((srcW * 125) / 1000) + 1; - } - - i = 0; - pOverlay->IntBit = 0x01; - while (srcW >= tmpW) { - tmpW <<= 1; - i++; - } - pOverlay->wHPre = (uint8_t) (i - 1); - dstW <<= (i - 1); - if ((srcW % dstW)) - pOverlay->HUSF = ((srcW - dstW) << 16) / dstW; - else - pOverlay->HUSF = 0x00; - } - - if (dstH < OVERLAY_MIN_HEIGHT) - dstH = OVERLAY_MIN_HEIGHT; - if (dstH == srcH) { - pOverlay->VUSF = 0x00; - pOverlay->IntBit |= 0x0A; - } else if (dstH > srcH) { - dstH += 0x02; - pOverlay->VUSF = (srcH << 16) / dstH; - pOverlay->IntBit |= 0x08; - } else { - uint32_t realI; - - i = realI = srcH / dstH; - pOverlay->IntBit |= 0x02; - - if (i < 2) { - pOverlay->VUSF = ((srcH - dstH) << 16) / dstH; - /* TW: Needed for LCD-scaling modes */ - if ((flag) && (mult = (srcH / origdstH)) >= 2) - pOverlay->pitch /= mult; - } else { -#if 0 - if (((pOverlay->bobEnable & 0x08) == 0x00) && - (((srcPitch * i) >> 2) > 0xFFF)) { - pOverlay->bobEnable |= 0x08; - srcPitch >>= 1; - } -#endif - if (((srcPitch * i) >> 2) > 0xFFF) { - i = (0xFFF * 2 / srcPitch); - pOverlay->VUSF = 0xFFFF; - } else { - dstH = i * dstH; - if (srcH % dstH) - pOverlay->VUSF = ((srcH - dstH) << 16) / dstH; - else - pOverlay->VUSF = 0x00; - } - /* set video frame buffer offset */ - pOverlay->pitch = (uint16_t) (srcPitch * i); - } - } -} - -static void set_line_buf_size(SISOverlayPtr pOverlay) -{ - uint8_t preHIDF; - uint32_t i; - uint32_t line = pOverlay->srcW; - - if ((pOverlay->pixelFormat == IMGFMT_YV12) || - (pOverlay->pixelFormat == IMGFMT_I420)) { - preHIDF = pOverlay->wHPre & 0x07; - switch (preHIDF) { - case 3: - if ((line & 0xffffff00) == line) - i = (line >> 8); - else - i = (line >> 8) + 1; - pOverlay->lineBufSize = (uint8_t) (i * 32 - 1); - break; - case 4: - if ((line & 0xfffffe00) == line) - i = (line >> 9); - else - i = (line >> 9) + 1; - pOverlay->lineBufSize = (uint8_t) (i * 64 - 1); - break; - case 5: - if ((line & 0xfffffc00) == line) - i = (line >> 10); - else - i = (line >> 10) + 1; - pOverlay->lineBufSize = (uint8_t) (i * 128 - 1); - break; - case 6: - if ((line & 0xfffff800) == line) - i = (line >> 11); - else - i = (line >> 11) + 1; - pOverlay->lineBufSize = (uint8_t) (i * 256 - 1); - break; - default: - if ((line & 0xffffff80) == line) - i = (line >> 7); - else - i = (line >> 7) + 1; - pOverlay->lineBufSize = (uint8_t) (i * 16 - 1); - break; - } - } else { /* YUV2, UYVY */ - if ((line & 0xffffff8) == line) - i = (line >> 3); - else - i = (line >> 3) + 1; - pOverlay->lineBufSize = (uint8_t) (i - 1); - } -} - -static void merge_line_buf(int enable) -{ - if (enable) { - switch (sis_displaymode) { - case DISPMODE_SINGLE1: - if (sis_has_two_overlays) { - /* dual line merge */ - setvideoregmask(Index_VI_Control_Misc2, 0x10, 0x11); - setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04); - } else { - setvideoregmask(Index_VI_Control_Misc2, 0x10, 0x11); - setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04); - } - break; - case DISPMODE_SINGLE2: - if (sis_has_two_overlays) { - /* line merge */ - setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x11); - setvideoregmask(Index_VI_Control_Misc1, 0x04, 0x04); - } else { - setvideoregmask(Index_VI_Control_Misc2, 0x10, 0x11); - setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04); - } - break; - case DISPMODE_MIRROR: - default: - /* line merge */ - setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x11); - setvideoregmask(Index_VI_Control_Misc1, 0x04, 0x04); - if (sis_has_two_overlays) { - /* line merge */ - setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x11); - setvideoregmask(Index_VI_Control_Misc1, 0x04, 0x04); - } - break; - } - } else { - switch (sis_displaymode) { - case DISPMODE_SINGLE1: - setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x11); - setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04); - break; - case DISPMODE_SINGLE2: - if (sis_has_two_overlays) { - setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x11); - setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04); - } else { - setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x11); - setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04); - } - break; - case DISPMODE_MIRROR: - default: - setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x11); - setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04); - if (sis_has_two_overlays) { - setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x11); - setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04); - } - break; - } - } -} - - -static void set_format(SISOverlayPtr pOverlay) -{ - uint8_t fmt; - - switch (pOverlay->pixelFormat) { - case IMGFMT_YV12: - case IMGFMT_I420: - fmt = 0x0c; - break; - case IMGFMT_YUY2: - fmt = 0x28; - break; - case IMGFMT_UYVY: - fmt = 0x08; - break; - case IMGFMT_RGB15: /* D[5:4] : 00 RGB555, 01 RGB 565 */ - fmt = 0x00; - break; - case IMGFMT_RGB16: - fmt = 0x10; - break; - default: - fmt = 0x00; - break; - } - setvideoregmask(Index_VI_Control_Misc0, fmt, 0x7c); -} - -static void set_colorkey(void) -{ - uint8_t r, g, b; - - b = (uint8_t) sis_grkey.ckey.blue; - g = (uint8_t) sis_grkey.ckey.green; - r = (uint8_t) sis_grkey.ckey.red; - - /* set color key mode */ - setvideoregmask(Index_VI_Key_Overlay_OP, - sis_grkey.ckey.op == CKEY_TRUE ? - VI_ROP_DestKey : VI_ROP_Always, 0x0F); - - /* set colorkey values */ - setvideoreg(Index_VI_Overlay_ColorKey_Blue_Min, (uint8_t) b); - setvideoreg(Index_VI_Overlay_ColorKey_Green_Min, (uint8_t) g); - setvideoreg(Index_VI_Overlay_ColorKey_Red_Min, (uint8_t) r); - - setvideoreg(Index_VI_Overlay_ColorKey_Blue_Max, (uint8_t) b); - setvideoreg(Index_VI_Overlay_ColorKey_Green_Max, (uint8_t) g); - setvideoreg(Index_VI_Overlay_ColorKey_Red_Max, (uint8_t) r); -} - -static void set_brightness(uint8_t brightness) -{ - setvideoreg(Index_VI_Brightness, brightness); -} - -static void set_contrast(uint8_t contrast) -{ - setvideoregmask(Index_VI_Contrast_Enh_Ctrl, contrast, 0x07); -} - -/* Next 3 functions are 310/325 series only */ - -static void set_saturation(char saturation) -{ - uint8_t temp = 0; - - if (saturation < 0) { - temp |= 0x88; - saturation = -saturation; - } - temp |= (saturation & 0x07); - temp |= ((saturation & 0x07) << 4); - - setvideoreg(Index_VI_Saturation, temp); -} - -static void set_hue(uint8_t hue) -{ - setvideoreg(Index_VI_Hue, (hue & 0x08) ? (hue ^ 0x07) : hue); -} - -#if 0 -/* JCP: not used (I don't think it's correct anyway) */ -static void set_alpha(uint8_t alpha) -{ - uint8_t data; - - data = getvideoreg(Index_VI_Key_Overlay_OP); - data &= 0x0F; - setvideoreg(Index_VI_Key_Overlay_OP, data | (alpha << 4)); -} -#endif
--- a/vidix/drivers/unichrome_regs.h Sat Mar 31 23:48:48 2007 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,635 +0,0 @@ -/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/via/via.h,v 1.5 2004/01/05 00:34:17 dawes Exp $ */ -/* - * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved. - * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sub license, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice (including the - * next paragraph) shall be included in all copies or substantial portions - * of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL - * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER - * DEALINGS IN THE SOFTWARE. - */ - -#ifndef _VIA_H_ -#define _VIA_H_ 1 - -/* Video status flag */ - -#define VIDEO_SHOW 0x80000000 /*Video on*/ -#define VIDEO_HIDE 0x00000000 /*Video off*/ -#define VIDEO_MPEG_INUSE 0x08000000 /*Video is used with MPEG */ -#define VIDEO_HQV_INUSE 0x04000000 /*Video is used with HQV*/ -#define VIDEO_CAPTURE0_INUSE 0x02000000 /*Video is used with CAPTURE 0*/ -#define VIDEO_CAPTURE1_INUSE 0x00000000 /*Video is used with CAPTURE 1*/ -#define VIDEO_1_INUSE 0x01000000 /*Video 1 is used with software flip*/ -#define VIDEO_3_INUSE 0x00000000 /*Video 3 is used with software flip*/ -#define MPEG_USE_V1 0x00010000 /*[16] : 1:MPEG use V1, 0:MPEG use V3*/ -#define MPEG_USE_V3 0x00000000 /*[16] : 1:MPEG use V1, 0:MPEG use V3*/ -#define MPEG_USE_HQV 0x00020000 /*[17] : 1:MPEG use HQV,0:MPEG not use HQV*/ -#define MPEG_USE_HW_FLIP 0x00040000 /*[18] : 1:MPEG use H/W flip,0:MPEG use S/W flip*/ -#define MPEG_USE_SW_FLIP 0x00000000 /*[18] : 1:MPEG use H/W flip,0:MPEG use S/W flip*/ -#define CAP0_USE_V1 0x00001000 /*[12] : 1:Capture 0 use V1, 0:Capture 0 use V3*/ -#define CAP0_USE_V3 0x00000000 /*[12] : 1:Capture 0 use V1, 0:Capture 0 use V3*/ -#define CAP0_USE_HQV 0x00002000 /*[13] : 1:Capture 0 use HQV,0:Capture 0 not use HQV*/ -#define CAP0_USE_HW_FLIP 0x00004000 /*[14] : 1:Capture 0 use H/W flip,0:Capture 0 use S/W flip*/ -#define CAP0_USE_CCIR656 0x00008000 /*[15] : 1:Capture 0 use CCIR656,0:Capture 0 CCIR601*/ -#define CAP1_USE_V1 0x00000100 /*[ 8] : 1:Capture 1 use V1, 0:Capture 1 use V3*/ -#define CAP1_USE_V3 0x00000000 /*[ 8] : 1:Capture 1 use V1, 0:Capture 1 use V3*/ -#define CAP1_USE_HQV 0x00000200 /*[ 9] : 1:Capture 1 use HQV,0:Capture 1 not use HQV*/ -#define CAP1_USE_HW_FLIP 0x00000400 /*[10] : 1:Capture 1 use H/W flip,0:Capture 1 use S/W flip */ -#define SW_USE_V1 0x00000010 /*[ 4] : 1:Capture 1 use V1, 0:Capture 1 use V3 */ -#define SW_USE_V3 0x00000000 /*[ 4] : 1:Capture 1 use V1, 0:Capture 1 use V3 */ -#define SW_USE_HQV 0x00000020 /*[ 5] : 1:Capture 1 use HQV,0:Capture 1 not use HQV */ - -/* -#define VIDEO1_INUSE 0x00000010 //[ 4] : 1:Video 1 is used with S/W flip -#define VIDEO1_USE_HQV 0x00000020 //[ 5] : 1:Video 1 use HQV with S/W flip -#define VIDEO3_INUSE 0x00000001 //[ 0] : 1:Video 3 is used with S/W flip -#define VIDEO3_USE_HQV 0x00000002 //[ 1] : 1:Video 3 use HQV with S/W flip -*/ - -/* H/W registers for Video Engine */ - -/* - * bus master - */ -#define PCI_MASTER_ENABLE 0x01 -#define PCI_MASTER_SCATTER 0x00 -#define PCI_MASTER_SINGLE 0x02 -#define PCI_MASTER_GUI 0x00 -#define PCI_MASTER_VIDEO 0x04 -#define PCI_MASTER_INPUT 0x00 -#define PCI_MASTER_OUTPUT 0x08 - -/* - * video registers - */ -#define V_FLAGS 0x00 -#define V_CAP_STATUS 0x04 -#define V_FLIP_STATUS 0x04 -#define V_ALPHA_WIN_START 0x08 -#define V_ALPHA_WIN_END 0x0C -#define V_ALPHA_CONTROL 0x10 -#define V_CRT_STARTADDR 0x14 -#define V_CRT_STARTADDR_2 0x18 -#define V_ALPHA_STRIDE 0x1C -#define V_COLOR_KEY 0x20 -#define V_ALPHA_STARTADDR 0x24 -#define V_CHROMAKEY_LOW 0x28 -#define V_CHROMAKEY_HIGH 0x2C -#define V1_CONTROL 0x30 -#define V12_QWORD_PER_LINE 0x34 -#define V1_STARTADDR_1 0x38 -#define V1_STARTADDR_Y1 V1_STARTADDR_1 -#define V1_STRIDE 0x3C -#define V1_WIN_START_Y 0x40 -#define V1_WIN_START_X 0x42 -#define V1_WIN_END_Y 0x44 -#define V1_WIN_END_X 0x46 -#define V1_STARTADDR_2 0x48 -#define V1_STARTADDR_Y2 V1_STARTADDR_2 -#define V1_ZOOM_CONTROL 0x4C -#define V1_MINI_CONTROL 0x50 -#define V1_STARTADDR_0 0x54 -#define V1_STARTADDR_Y0 V1_STARTADDR_0 -#define V_FIFO_CONTROL 0x58 -#define V1_STARTADDR_3 0x5C -#define V1_STARTADDR_Y3 V1_STARTADDR_3 -#define HI_CONTROL 0x60 -#define SND_COLOR_KEY 0x64 -#define ALPHA_V3_PREFIFO_CONTROL 0x68 -#define V1_SOURCE_HEIGHT 0x6C -#define HI_TRANSPARENT_COLOR 0x70 -#define V_DISPLAY_TEMP 0x74 /* No use */ -#define ALPHA_V3_FIFO_CONTROL 0x78 -#define V3_SOURCE_WIDTH 0x7C -#define V3_COLOR_KEY 0x80 -#define V1_ColorSpaceReg_1 0x84 -#define V1_ColorSpaceReg_2 0x88 -#define V1_STARTADDR_CB0 0x8C -#define V1_OPAQUE_CONTROL 0x90 /* To be deleted */ -#define V3_OPAQUE_CONTROL 0x94 /* To be deleted */ -#define V_COMPOSE_MODE 0x98 -#define V3_STARTADDR_2 0x9C -#define V3_CONTROL 0xA0 -#define V3_STARTADDR_0 0xA4 -#define V3_STARTADDR_1 0xA8 -#define V3_STRIDE 0xAC -#define V3_WIN_START_Y 0xB0 -#define V3_WIN_START_X 0xB2 -#define V3_WIN_END_Y 0xB4 -#define V3_WIN_END_X 0xB6 -#define V3_ALPHA_QWORD_PER_LINE 0xB8 -#define V3_ZOOM_CONTROL 0xBC -#define V3_MINI_CONTROL 0xC0 -#define V3_ColorSpaceReg_1 0xC4 -#define V3_ColorSpaceReg_2 0xC8 -#define V3_DISPLAY_TEMP 0xCC /* No use */ -#define V1_STARTADDR_CB1 0xE4 -#define V1_STARTADDR_CB2 0xE8 -#define V1_STARTADDR_CB3 0xEC -#define V1_STARTADDR_CR0 0xF0 -#define V1_STARTADDR_CR1 0xF4 -#define V1_STARTADDR_CR2 0xF8 -#define V1_STARTADDR_CR3 0xFC - -/* Video Capture Engine Registers - * Capture Port 1 - */ -#define CAP0_MASKS 0x100 -#define CAP1_MASKS 0x104 -#define CAP0_CONTROL 0x110 -#define CAP0_H_RANGE 0x114 -#define CAP0_V_RANGE 0x118 -#define CAP0_SCAL_CONTROL 0x11C -#define CAP0_VBI_H_RANGE 0x120 -#define CAP0_VBI_V_RANGE 0x124 -#define CAP0_VBI_STARTADDR 0x128 -#define CAP0_VBI_STRIDE 0x12C -#define CAP0_ANCIL_COUNT 0x130 -#define CAP0_MAXCOUNT 0x134 -#define CAP0_VBIMAX_COUNT 0x138 -#define CAP0_DATA_COUNT 0x13C -#define CAP0_FB_STARTADDR0 0x140 -#define CAP0_FB_STARTADDR1 0x144 -#define CAP0_FB_STARTADDR2 0x148 -#define CAP0_STRIDE 0x150 -/* Capture Port 2 */ -#define CAP1_CONTROL 0x154 -#define CAP1_SCAL_CONTROL 0x160 -#define CAP1_VBI_H_RANGE 0x164 /*To be deleted*/ -#define CAP1_VBI_V_RANGE 0x168 /*To be deleted*/ -#define CAP1_VBI_STARTADDR 0x16C /*To be deleted*/ -#define CAP1_VBI_STRIDE 0x170 /*To be deleted*/ -#define CAP1_ANCIL_COUNT 0x174 /*To be deleted*/ -#define CAP1_MAXCOUNT 0x178 -#define CAP1_VBIMAX_COUNT 0x17C /*To be deleted*/ -#define CAP1_DATA_COUNT 0x180 -#define CAP1_FB_STARTADDR0 0x184 -#define CAP1_FB_STARTADDR1 0x188 -#define CAP1_STRIDE 0x18C - -/* SUBPICTURE Registers */ -#define SUBP_CONTROL_STRIDE 0x1C0 -#define SUBP_STARTADDR 0x1C4 -#define RAM_TABLE_CONTROL 0x1C8 -#define RAM_TABLE_READ 0x1CC - -/* HQV Registers */ -#define HQV_CONTROL 0x1D0 -#define HQV_SRC_STARTADDR_Y 0x1D4 -#define HQV_SRC_STARTADDR_U 0x1D8 -#define HQV_SRC_STARTADDR_V 0x1DC -#define HQV_SRC_FETCH_LINE 0x1E0 -#define HQV_FILTER_CONTROL 0x1E4 -#define HQV_MINIFY_CONTROL 0x1E8 -#define HQV_DST_STARTADDR0 0x1EC -#define HQV_DST_STARTADDR1 0x1F0 -#define HQV_DST_STARTADDR2 0x1FC -#define HQV_DST_STRIDE 0x1F4 -#define HQV_SRC_STRIDE 0x1F8 - - -/* - * Video command definition - */ -/* #define V_ALPHA_CONTROL 0x210 */ -#define ALPHA_WIN_EXPIRENUMBER_4 0x00040000 -#define ALPHA_WIN_CONSTANT_FACTOR_4 0x00004000 -#define ALPHA_WIN_CONSTANT_FACTOR_12 0x0000c000 -#define ALPHA_WIN_BLENDING_CONSTANT 0x00000000 -#define ALPHA_WIN_BLENDING_ALPHA 0x00000001 -#define ALPHA_WIN_BLENDING_GRAPHIC 0x00000002 -#define ALPHA_WIN_PREFIFO_THRESHOLD_12 0x000c0000 -#define ALPHA_WIN_FIFO_THRESHOLD_8 0x000c0000 -#define ALPHA_WIN_FIFO_DEPTH_16 0x00100000 - -/* V_CHROMAKEY_LOW 0x228 */ -#define V_CHROMAKEY_V3 0x80000000 - -/* V1_CONTROL 0x230 */ -#define V1_ENABLE 0x00000001 -#define V1_FULL_SCREEN 0x00000002 -#define V1_YUV422 0x00000000 -#define V1_RGB32 0x00000004 -#define V1_RGB15 0x00000008 -#define V1_RGB16 0x0000000C -#define V1_YCbCr420 0x00000010 -#define V1_COLORSPACE_SIGN 0x00000080 -#define V1_SRC_IS_FIELD_PIC 0x00000200 -#define V1_SRC_IS_FRAME_PIC 0x00000000 -#define V1_BOB_ENABLE 0x00400000 -#define V1_FIELD_BASE 0x00000000 -#define V1_FRAME_BASE 0x01000000 -#define V1_SWAP_SW 0x00000000 -#define V1_SWAP_HW_HQV 0x02000000 -#define V1_SWAP_HW_CAPTURE 0x04000000 -#define V1_SWAP_HW_MC 0x06000000 -/* #define V1_DOUBLE_BUFFERS 0x00000000 */ -/* #define V1_QUADRUPLE_BUFFERS 0x18000000 */ -#define V1_EXPIRE_NUM 0x00050000 -#define V1_EXPIRE_NUM_A 0x000a0000 -#define V1_EXPIRE_NUM_F 0x000f0000 /* jason */ -#define V1_FIFO_EXTENDED 0x00200000 -#define V1_ON_CRT 0x00000000 -#define V1_ON_SND_DISPLAY 0x80000000 -#define V1_FIFO_32V1_32V2 0x00000000 -#define V1_FIFO_48V1_32V2 0x00200000 - -/* V12_QWORD_PER_LINE 0x234 */ -#define V1_FETCH_COUNT 0x3ff00000 -#define V1_FETCHCOUNT_ALIGNMENT 0x0000000f -#define V1_FETCHCOUNT_UNIT 0x00000004 /* Doubld QWORD */ - -/* V1_STRIDE */ -#define V1_STRIDE_YMASK 0x00001fff -#define V1_STRIDE_UVMASK 0x1ff00000 - -/* V1_ZOOM_CONTROL 0x24C */ -#define V1_X_ZOOM_ENABLE 0x80000000 -#define V1_Y_ZOOM_ENABLE 0x00008000 - -/* V1_MINI_CONTROL 0x250 */ -#define V1_X_INTERPOLY 0x00000002 /* X interpolation */ -#define V1_Y_INTERPOLY 0x00000001 /* Y interpolation */ -#define V1_YCBCR_INTERPOLY 0x00000004 /* Y, Cb, Cr all interpolation */ -#define V1_X_DIV_2 0x01000000 -#define V1_X_DIV_4 0x03000000 -#define V1_X_DIV_8 0x05000000 -#define V1_X_DIV_16 0x07000000 -#define V1_Y_DIV_2 0x00010000 -#define V1_Y_DIV_4 0x00030000 -#define V1_Y_DIV_8 0x00050000 -#define V1_Y_DIV_16 0x00070000 - -/* V1_STARTADDR0 0x254 */ -#define SW_FLIP_ODD 0x08000000 - -/* V_FIFO_CONTROL 0x258 - * IA2 has 32 level FIFO for packet mode video format - * 32 level FIFO for planar mode video YV12. with extension reg 230 bit 21 enable - * 16 level FIFO for planar mode video YV12. with extension reg 230 bit 21 disable - * BCos of 128 bits. 1 level in IA2 = 2 level in VT3122 - */ -#define V1_FIFO_DEPTH12 0x0000000B -#define V1_FIFO_DEPTH16 0x0000000F -#define V1_FIFO_DEPTH32 0x0000001F -#define V1_FIFO_DEPTH48 0x0000002F -#define V1_FIFO_DEPTH64 0x0000003F -#define V1_FIFO_THRESHOLD6 0x00000600 -#define V1_FIFO_THRESHOLD8 0x00000800 -#define V1_FIFO_THRESHOLD12 0x00000C00 -#define V1_FIFO_THRESHOLD16 0x00001000 -#define V1_FIFO_THRESHOLD24 0x00001800 -#define V1_FIFO_THRESHOLD32 0x00002000 -#define V1_FIFO_THRESHOLD40 0x00002800 -#define V1_FIFO_THRESHOLD48 0x00003000 -#define V1_FIFO_THRESHOLD56 0x00003800 -#define V1_FIFO_THRESHOLD61 0x00003D00 -#define V1_FIFO_PRETHRESHOLD10 0x0A000000 -#define V1_FIFO_PRETHRESHOLD12 0x0C000000 -#define V1_FIFO_PRETHRESHOLD29 0x1d000000 -#define V1_FIFO_PRETHRESHOLD40 0x28000000 -#define V1_FIFO_PRETHRESHOLD44 0x2c000000 -#define V1_FIFO_PRETHRESHOLD56 0x38000000 -#define V1_FIFO_PRETHRESHOLD61 0x3D000000 - -/* ALPHA_V3_FIFO_CONTROL 0x278 - * IA2 has 32 level FIFO for packet mode video format - * 32 level FIFO for planar mode video YV12. with extension reg 230 bit 21 enable - * 16 level FIFO for planar mode video YV12. with extension reg 230 bit 21 disable - * 8 level FIFO for ALPHA - * BCos of 128 bits. 1 level in IA2 = 2 level in VT3122 - */ -#define V3_FIFO_DEPTH16 0x0000000F -#define V3_FIFO_DEPTH24 0x00000017 -#define V3_FIFO_DEPTH32 0x0000001F -#define V3_FIFO_DEPTH48 0x0000002F -#define V3_FIFO_DEPTH64 0x0000003F -#define V3_FIFO_THRESHOLD8 0x00000800 -#define V3_FIFO_THRESHOLD12 0x00000C00 -#define V3_FIFO_THRESHOLD16 0x00001000 -#define V3_FIFO_THRESHOLD24 0x00001800 -#define V3_FIFO_THRESHOLD32 0x00002000 -#define V3_FIFO_THRESHOLD40 0x00002800 -#define V3_FIFO_THRESHOLD48 0x00003000 -#define V3_FIFO_THRESHOLD56 0x00003800 -#define V3_FIFO_THRESHOLD61 0x00003D00 -#define V3_FIFO_PRETHRESHOLD10 0x0000000A -#define V3_FIFO_PRETHRESHOLD12 0x0000000C -#define V3_FIFO_PRETHRESHOLD29 0x0000001d -#define V3_FIFO_PRETHRESHOLD40 0x00000028 -#define V3_FIFO_PRETHRESHOLD44 0x0000002c -#define V3_FIFO_PRETHRESHOLD56 0x00000038 -#define V3_FIFO_PRETHRESHOLD61 0x0000003D -#define V3_FIFO_MASK 0x0000007F -#define ALPHA_FIFO_DEPTH8 0x00070000 -#define ALPHA_FIFO_THRESHOLD4 0x04000000 -#define ALPHA_FIFO_MASK 0xffff0000 -#define ALPHA_FIFO_PRETHRESHOLD4 0x00040000 - -/* IA2 */ -#define ColorSpaceValue_1 0x140020f2 -#define ColorSpaceValue_2 0x0a0a2c00 - -#define ColorSpaceValue_1_3123C0 0x13000DED -#define ColorSpaceValue_2_3123C0 0x13171000 - -/* For TV setting */ -#define ColorSpaceValue_1TV 0x140020f2 -#define ColorSpaceValue_2TV 0x0a0a2c00 - -/* V_COMPOSE_MODE 0x298 */ -#define SELECT_VIDEO_IF_COLOR_KEY 0x00000001 /* select video if (color key),otherwise select graphics */ -#define SELECT_VIDEO3_IF_COLOR_KEY 0x00000020 /* For 3123C0, select video3 if (color key),otherwise select graphics */ -#define SELECT_VIDEO_IF_CHROMA_KEY 0x00000002 /* 0x0000000a //select video if (chroma key ),otherwise select graphics */ -#define ALWAYS_SELECT_VIDEO 0x00000000 /* always select video,Chroma key and Color key disable */ -#define COMPOSE_V1_V3 0x00000000 /* V1 on top of V3 */ -#define COMPOSE_V3_V1 0x00100000 /* V3 on top of V1 */ -#define COMPOSE_V1_TOP 0x00000000 -#define COMPOSE_V3_TOP 0x00100000 -#define V1_COMMAND_FIRE 0x80000000 /* V1 commands fire */ -#define V3_COMMAND_FIRE 0x40000000 /* V3 commands fire */ -#define V_COMMAND_LOAD 0x20000000 /* Video register always loaded */ -#define V_COMMAND_LOAD_VBI 0x10000000 /* Video register always loaded at vbi without waiting source flip */ -#define V3_COMMAND_LOAD 0x08000000 /* CLE_C0 Video3 register always loaded */ -#define V3_COMMAND_LOAD_VBI 0x00000100 /* CLE_C0 Video3 register always loaded at vbi without waiting source flip */ -#define SECOND_DISPLAY_COLOR_KEY_ENABLE 0x00010000 - -/* V3_ZOOM_CONTROL 0x2bc */ -#define V3_X_ZOOM_ENABLE 0x80000000 -#define V3_Y_ZOOM_ENABLE 0x00008000 - -/* V3_MINI_CONTROL 0x2c0 */ -#define V3_X_INTERPOLY 0x00000002 /* X interpolation */ -#define V3_Y_INTERPOLY 0x00000001 /* Y interpolation */ -#define V3_YCBCR_INTERPOLY 0x00000004 /* Y, Cb, Cr all interpolation */ -#define V3_X_DIV_2 0x01000000 -#define V3_X_DIV_4 0x03000000 -#define V3_X_DIV_8 0x05000000 -#define V3_X_DIV_16 0x07000000 -#define V3_Y_DIV_2 0x00010000 -#define V3_Y_DIV_4 0x00030000 -#define V3_Y_DIV_8 0x00050000 -#define V3_Y_DIV_16 0x00070000 - -/* SUBP_CONTROL_STRIDE 0x3c0 */ -#define SUBP_HQV_ENABLE 0x00010000 -#define SUBP_IA44 0x00020000 -#define SUBP_AI44 0x00000000 -#define SUBP_STRIDE_MASK 0x00001fff -#define SUBP_CONTROL_MASK 0x00070000 - -/* RAM_TABLE_CONTROL 0x3c8 */ -#define RAM_TABLE_RGB_ENABLE 0x00000007 - -/* CAPTURE0_CONTROL 0x310 */ -#define C0_ENABLE 0x00000001 -#define BUFFER_2_MODE 0x00000000 -#define BUFFER_3_MODE 0x00000004 -#define BUFFER_4_MODE 0x00000006 -#define SWAP_YUYV 0x00000000 -#define SWAP_UYVY 0x00000100 -#define SWAP_YVYU 0x00000200 -#define SWAP_VYUY 0x00000300 -#define IN_601_8 0x00000000 -#define IN_656_8 0x00000010 -#define IN_601_16 0x00000020 -#define IN_656_16 0x00000030 -#define DEINTER_ODD 0x00000000 -#define DEINTER_EVEN 0x00001000 -#define DEINTER_ODD_EVEN 0x00002000 -#define DEINTER_FRAME 0x00003000 -#define VIP_1 0x00000000 -#define VIP_2 0x00000400 -#define H_FILTER_2 0x00010000 -#define H_FILTER_4 0x00020000 -#define H_FILTER_8_1331 0x00030000 -#define H_FILTER_8_12221 0x00040000 -#define VIP_ENABLE 0x00000008 -#define EN_FIELD_SIG 0x00000800 -#define VREF_INVERT 0x00100000 -#define FIELD_INPUT_INVERSE 0x00400000 -#define FIELD_INVERSE 0x40000000 - -#define C1_H_MINI_EN 0x00000800 -#define C0_H_MINI_EN 0x00000800 -#define C1_V_MINI_EN 0x04000000 -#define C0_V_MINI_EN 0x04000000 -#define C1_H_MINI_2 0x00000400 - -/* CAPTURE1_CONTROL 0x354 */ -#define C1_ENABLE 0x00000001 - -/* V3_CONTROL 0x2A0 */ -#define V3_ENABLE 0x00000001 -#define V3_FULL_SCREEN 0x00000002 -#define V3_YUV422 0x00000000 -#define V3_RGB32 0x00000004 -#define V3_RGB15 0x00000008 -#define V3_RGB16 0x0000000C -#define V3_COLORSPACE_SIGN 0x00000080 -#define V3_EXPIRE_NUM 0x00040000 -#define V3_EXPIRE_NUM_F 0x000f0000 -#define V3_BOB_ENABLE 0x00400000 -#define V3_FIELD_BASE 0x00000000 -#define V3_FRAME_BASE 0x01000000 -#define V3_SWAP_SW 0x00000000 -#define V3_SWAP_HW_HQV 0x02000000 -#define V3_FLIP_HW_CAPTURE0 0x04000000 -#define V3_FLIP_HW_CAPTURE1 0x06000000 - -/* V3_ALPHA_FETCH_COUNT 0x2B8 */ -#define V3_FETCH_COUNT 0x3ff00000 -#define ALPHA_FETCH_COUNT 0x000003ff - -/* HQV_CONTROL 0x3D0 */ -#define HQV_RGB32 0x00000000 -#define HQV_RGB16 0x20000000 -#define HQV_RGB15 0x30000000 -#define HQV_YUV422 0x80000000 -#define HQV_YUV420 0xC0000000 -#define HQV_ENABLE 0x08000000 -#define HQV_SRC_SW 0x00000000 -#define HQV_SRC_MC 0x01000000 -#define HQV_SRC_CAPTURE0 0x02000000 -#define HQV_SRC_CAPTURE1 0x03000000 -#define HQV_FLIP_EVEN 0x00000000 -#define HQV_FLIP_ODD 0x00000020 -#define HQV_SW_FLIP 0x00000010 /* Write 1 to flip HQV buffer */ -#define HQV_DEINTERLACE 0x00010000 /* First line of odd field will be repeated 3 times */ -#define HQV_FIELD_2_FRAME 0x00020000 /* Src is field. Display each line 2 times */ -#define HQV_FRAME_2_FIELD 0x00040000 /* Src is field. Display field */ -#define HQV_FRAME_UV 0x00000000 /* Src is Non-interleaved */ -#define HQV_FIELD_UV 0x00100000 /* Src is interleaved */ -#define HQV_IDLE 0x00000008 -#define HQV_FLIP_STATUS 0x00000001 -#define HQV_DOUBLE_BUFF 0x00000000 -#define HQV_TRIPLE_BUFF 0x04000000 -#define HQV_SUBPIC_FLIP 0x00008000 -#define HQV_FIFO_STATUS 0x00001000 - -/* HQV_FILTER_CONTROL 0x3E4 */ -#define HQV_H_LOWPASS_2TAP 0x00000001 -#define HQV_H_LOWPASS_4TAP 0x00000002 -#define HQV_H_LOWPASS_8TAP1 0x00000003 /* To be deleted */ -#define HQV_H_LOWPASS_8TAP2 0x00000004 /* To be deleted */ -#define HQV_H_HIGH_PASS 0x00000008 -#define HQV_H_LOW_PASS 0x00000000 -#define HQV_V_LOWPASS_2TAP 0x00010000 -#define HQV_V_LOWPASS_4TAP 0x00020000 -#define HQV_V_LOWPASS_8TAP1 0x00030000 -#define HQV_V_LOWPASS_8TAP2 0x00040000 -#define HQV_V_HIGH_PASS 0x00080000 -#define HQV_V_LOW_PASS 0x00000000 -#define HQV_H_HIPASS_F1_DEFAULT 0x00000040 -#define HQV_H_HIPASS_F2_DEFAULT 0x00000000 -#define HQV_V_HIPASS_F1_DEFAULT 0x00400000 -#define HQV_V_HIPASS_F2_DEFAULT 0x00000000 -#define HQV_H_HIPASS_F1_2TAP 0x00000050 -#define HQV_H_HIPASS_F2_2TAP 0x00000100 -#define HQV_V_HIPASS_F1_2TAP 0x00500000 -#define HQV_V_HIPASS_F2_2TAP 0x01000000 -#define HQV_H_HIPASS_F1_4TAP 0x00000060 -#define HQV_H_HIPASS_F2_4TAP 0x00000200 -#define HQV_V_HIPASS_F1_4TAP 0x00600000 -#define HQV_V_HIPASS_F2_4TAP 0x02000000 -#define HQV_H_HIPASS_F1_8TAP 0x00000080 -#define HQV_H_HIPASS_F2_8TAP 0x00000400 -#define HQV_V_HIPASS_F1_8TAP 0x00800000 -#define HQV_V_HIPASS_F2_8TAP 0x04000000 -/* IA2 NEW */ -#define HQV_V_FILTER2 0x00080000 -#define HQV_H_FILTER2 0x00000008 -#define HQV_H_TAP2_11 0x00000041 -#define HQV_H_TAP4_121 0x00000042 -#define HQV_H_TAP4_1111 0x00000401 -#define HQV_H_TAP8_1331 0x00000221 -#define HQV_H_TAP8_12221 0x00000402 -#define HQV_H_TAP16_1991 0x00000159 -#define HQV_H_TAP16_141041 0x0000026A -#define HQV_H_TAP32 0x0000015A -#define HQV_V_TAP2_11 0x00410000 -#define HQV_V_TAP4_121 0x00420000 -#define HQV_V_TAP4_1111 0x04010000 -#define HQV_V_TAP8_1331 0x02210000 -#define HQV_V_TAP8_12221 0x04020000 -#define HQV_V_TAP16_1991 0x01590000 -#define HQV_V_TAP16_141041 0x026A0000 -#define HQV_V_TAP32 0x015A0000 -#define HQV_V_FILTER_DEFAULT 0x00420000 -#define HQV_H_FILTER_DEFAULT 0x00000040 - - - - -/* HQV_MINI_CONTROL 0x3E8 */ -#define HQV_H_MINIFY_ENABLE 0x00000800 -#define HQV_V_MINIFY_ENABLE 0x08000000 -#define HQV_VDEBLOCK_FILTER 0x80000000 -#define HQV_HDEBLOCK_FILTER 0x00008000 - - -#define CHROMA_KEY_LOW 0x00FFFFFF -#define CHROMA_KEY_HIGH 0x00FFFFFF - -/* V_CAP_STATUS */ -#define V_ST_UPDATE_NOT_YET 0x00000003 -#define V1_ST_UPDATE_NOT_YET 0x00000001 -#define V3_ST_UPDATE_NOT_YET 0x00000008 - -#define VBI_STATUS 0x00000002 - -/* - * Macros for Video MMIO - */ -#ifndef V4L2 -#define VIDInB(port) *((volatile CARD8 *)(pVia->VidMapBase + (port))) -#define VIDInW(port) *((volatile CARD16 *)(pVia->VidMapBase + (port))) -#define VIDInD(port) *((volatile CARD32 *)(pVia->VidMapBase + (port))) -#define VIDOutB(port, data) *((volatile CARD8 *)(pVia->VidMapBase + (port))) = (data) -#define VIDOutW(port, data) *((volatile CARD16 *)(pVia->VidMapBase + (port))) = (data) -#define VIDOutD(port, data) *((volatile CARD32 *)(pVia->VidMapBase + (port))) = (data) -#define MPGOutD(port, data) *((volatile CARD32 *)(lpMPEGMMIO +(port))) = (data) -#define MPGInD(port) *((volatile CARD32 *)(lpMPEGMMIO +(port))) -#endif - -/* - * Macros for GE MMIO - */ -#define GEInW(port) *((volatile CARD16 *)(lpGEMMIO + (port))) -#define GEInD(port) *((volatile CARD32 *)(lpGEMMIO + (port))) -#define GEOutW(port, data) *((volatile CARD16 *)(lpGEMMIO + (port))) = (data) -#define GEOutD(port, data) *((volatile CARD32 *)(lpGEMMIO + (port))) = (data) - -/* - * MPEG 1/2 Slice Engine (at 0xC00 relative to base) - */ - -#define MPG_CONTROL 0x00 -#define MPG_CONTROL_STRUCT 0x03 -#define MPG_CONTROL_STRUCT_TOP 0x01 -#define MPG_CONTROL_STRUCT_BOTTOM 0x02 -#define MPG_CONTROL_STRUCT_FRAME 0x03 - /* Use TOP if interlaced */ -#define MPG_CONTROL_TYPE 0x3C -#define MPG_CONTROL_TYPE_I (0x01 << 2) -#define MPG_CONTROL_TYPE_B (0x02 << 2) -#define MPG_CONTROL_TYPE_P (0x03 << 3) -#define MPG_CONTROL_ALTSCAN 0x40 -#define MPG_BLOCK 0x08 /* Unsure */ -#define MPG_COMMAND 0x0C -#define MPG_DATA1 0x10 -#define MPG_DATA2 0x14 -#define MPG_DATA3 0x18 -#define MPG_DATA4 0x1C - -#define MPG_YPHYSICAL(x) (0x20 + 12*(x)) -#define MPG_CbPHYSICAL(x) (0x24 + 12*(x)) -#define MPG_CrPHYSICAL(x) (0x28 + 12*(x)) - -#define MPG_PITCH 0x50 -#define MPG_STATUS 0x54 - -#define MPG_MATRIX_IDX 0x5C -#define MPG_MATRIX_IDX_INTRA 0x00 -#define MPG_MATRIX_IDX_NON 0x01 -#define MPG_MATRIX_DATA 0x60 - -#define MPG_SLICE_CTRL_1 0x90 -#define MPG_SLICE_MBAMAX 0x2FFF -#define MPG_SLICE_PREDICTIVE_DCT 0x4000 -#define MPG_SLICE_TOP_FIRST 0x8000 -#define MPG_SLICE_MACROBLOCK_WIDTH(x) ((x)<<18) /* in 64's */ -#define MPG_SLICE_CTRL_2 0x94 -#define MPG_SLICE_CONCEAL_MVEC 0x0000001 -#define MPG_SLICE_QSCALE_TYPE 0x0000002 -#define MPG_SLICE_DCPRECISION 0x000000C -#define MPG_SLICE_MACROBQUOT 0x0FFFFF0 -#define MPG_SLICE_INTRAVLC 0x1000000 -#define MPG_SLICE_CTRL_3 0x98 -#define MPG_SLICE_FHMVR 0x0000003 -#define MPG_SLICE_FVMVR 0x000000C -#define MPG_SLICE_BHMVR 0x0000030 -#define MPG_SLICE_BVMVR 0x00000C0 -#define MPG_SLICE_SECOND_FIELD 0x0100000 -#define MPG_SLICE_RESET 0x0400000 -#define MPG_SLICE_LENGTH 0x9C -#define MPG_SLICE_DATA 0xA0 - - - -#endif /* _VIA_H_ */
--- a/vidix/drivers/unichrome_vid.c Sat Mar 31 23:48:48 2007 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,976 +0,0 @@ -/* - Driver for VIA CLE266 Unichrome - Version 0.1.0 - - Copyright (C) 2004 by Timothy Lee - - Based on Cyberblade/i driver by Alastair M. Robison. - - Thanks to Gilles Frattini for bugfixes - - This program is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 2 of the License, or - (at your option) any later version. - - This program is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program; if not, write to the Free Software - Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - - Changes: - 2004-03-10 - Initial version - 2004-10-09 - Added Doxygen documentation (Benjamin Zores <ben@geexbox.org>) - 2004-11-08 - Added h/w revision detection (Timothy Lee <timothy.lee@siriushk.com>) - - To Do: -*/ - -#include <errno.h> -#include <stdio.h> -#include <stdlib.h> -#include <string.h> -#include <inttypes.h> -#include <unistd.h> - -#include "../vidix.h" -#include "../fourcc.h" -#include "../../libdha/libdha.h" -#include "../../libdha/pci_ids.h" -#include "../../libdha/pci_names.h" -#include "../../config.h" - -#include "unichrome_regs.h" - -/** - * @brief Information on PCI device. - */ -pciinfo_t pci_info; - -/** - * @brief Unichrome driver colorkey settings. - */ -static vidix_grkey_t uc_grkey; - -static int frames[VID_PLAY_MAXFRAMES]; -uint8_t *vio; -uint8_t *uc_mem; -uint8_t mclk_save[3]; -uint8_t hwrev; - -#define VIA_OUT(hwregs, reg, val) *(volatile uint32_t *)((hwregs) + (reg)) = (val) -#define VIA_IN(hwregs, reg) *(volatile uint32_t *)((hwregs) + (reg)) -#define VGA_OUT8(hwregs, reg, val) *(volatile uint8_t *)((hwregs) + (reg) + 0x8000) = (val) -#define VGA_IN8(hwregs, reg) *(volatile uint8_t *)((hwregs) + (reg) + 0x8000) -#define VIDEO_OUT(hwregs, reg, val) VIA_OUT((hwregs)+0x200, reg, val) -#define VIDEO_IN(hwregs, reg) VIA_IN((hwregs)+0x200, reg) - -#define outb(val,reg) OUTPORT8(reg,val) -#define inb(reg) INPORT8(reg) - -#define ALIGN_TO(v, n) (((v) + (n-1)) & ~(n-1)) -#define UC_MAP_V1_FIFO_CONTROL(depth, pre_thr, thr) \ - (((depth)-1) | ((thr) << 8) | ((pre_thr) << 24)) - -#define VIDEOMEMORY_SIZE (8 * 1024 * 1024) -#define FRAMEBUFFER_SIZE 0x200000 -#define FRAMEBUFFER_START (VIDEOMEMORY_SIZE - FRAMEBUFFER_SIZE) - -#ifdef DEBUG_LOGFILE -FILE *logfile = 0; -#define LOGWRITE(x) {if(logfile) fprintf(logfile,x);} -#else -#define LOGWRITE(x) -#endif - -/** - * @brief Unichrome driver vidix capabilities. - */ -static vidix_capability_t uc_cap = { - "VIA CLE266 Unichrome driver", - "Timothy Lee <timothy@siriushk.com>", - TYPE_OUTPUT, - {0, 0, 0, 0}, - 4096, - 4096, - 4, - 4, - -1, - FLAG_UPSCALER | FLAG_DOWNSCALER, - VENDOR_VIA2, - -1, - {0, 0, 0, 0} -}; - -/** - * @brief list of card IDs compliant with the Unichrome driver . - */ -static unsigned short uc_card_ids[] = { - DEVICE_VIA2_VT8623_CLE266_AGP -}; - -/** - * @brief Check age of driver. - * - * @return vidix version number. - */ -unsigned int -vixGetVersion (void) -{ - return (VIDIX_VERSION); -} - -/** - * @brief Find chip index in Unichrome compliant devices list. - * - * @param chip_id PCI device ID. - * - * @returns index position in uc_card_ids if successful. - * -1 if chip_id is not a compliant chipset ID. - */ -static int -find_chip (unsigned chip_id) -{ - unsigned i; - for (i = 0; i < sizeof (uc_card_ids) / sizeof (unsigned short); i++) - { - if (chip_id == uc_card_ids[i]) - return i; - } - return -1; -} - -/** - * @brief Map hardware settings for vertical scaling. - * - * @param sh source height. - * @param dh destination height. - * @param zoom will hold vertical setting of zoom register. - * @param mini will hold vertical setting of mini register. - * - * @returns 1 if successful. - * 0 if the zooming factor is too large or small. - * - * @note Derived from VIA's V4L driver. - * See ddover.c, DDOVER_HQVCalcZoomHeight() - */ -static int -uc_ovl_map_vzoom (int sh, int dh, uint32_t * zoom, uint32_t * mini) -{ - uint32_t sh1, tmp, d; - int zoom_ok = 1; - - if (sh == dh) /* No zoom */ - { - /* Do nothing */ - } - else if (sh < dh) /* Zoom in */ - { - tmp = (sh * 0x0400) / dh; - zoom_ok = !(tmp > 0x3ff); - - *zoom |= (tmp & 0x3ff) | V1_Y_ZOOM_ENABLE; - *mini |= V1_Y_INTERPOLY | V1_YCBCR_INTERPOLY; - } - else /* sw > dh - Zoom out */ - { - /* Find a suitable divider (1 << d) = {2, 4, 8 or 16} */ - sh1 = sh; - for (d = 1; d < 5; d++) - { - sh1 >>= 1; - if (sh1 <= dh) - break; - } - if (d == 5) /* too small */ - { - d = 4; - zoom_ok = 0; - } - - *mini |= ((d << 1) - 1) << 16; /* <= {1,3,5,7} << 16 */ - - /* Add scaling */ - if (sh1 < dh) - { - tmp = (sh1 * 0x400) / dh; - *zoom |= ((tmp & 0x3ff) | V1_Y_ZOOM_ENABLE); - *mini |= V1_Y_INTERPOLY | V1_YCBCR_INTERPOLY; - } - } - - return zoom_ok; -} - -/** - * @brief Map hardware settings for horizontal scaling. - * - * @param sw source width. - * @param dw destination width. - * @param zoom will hold horizontal setting of zoom register. - * @param mini will hold horizontal setting of mini register. - * @param falign will hold fetch aligment. - * @param dcount will hold display count. - * - * @returns 1 if successful. - * 0 if the zooming factor is too large or small. - * - * @note Derived from VIA's V4L driver. - * See ddover.c, DDOVER_HQVCalcZoomWidth() and DDOver_GetDisplayCount() - */ -static int -uc_ovl_map_hzoom (int sw, int dw, uint32_t * zoom, uint32_t * mini, - int *falign, int *dcount) -{ - uint32_t tmp, sw1, d; - int md; /* Minify-divider */ - int zoom_ok = 1; - - md = 1; - *falign = 0; - - if (sw == dw) /* no zoom */ - { - /* Do nothing */ - } - else if (sw < dw) /* zoom in */ - { - tmp = (sw * 0x0800) / dw; - zoom_ok = !(tmp > 0x7ff); - - *zoom |= ((tmp & 0x7ff) << 16) | V1_X_ZOOM_ENABLE; - *mini |= V1_X_INTERPOLY; - } - else /* sw > dw - Zoom out */ - { - /* Find a suitable divider (1 << d) = {2, 4, 8 or 16} */ - sw1 = sw; - for (d = 1; d < 5; d++) - { - sw1 >>= 1; - if (sw1 <= dw) - break; - } - if (d == 5) /* too small */ - { - d = 4; - zoom_ok = 0; - } - - md = 1 << d; /* <= {2,4,8,16} */ - *falign = ((md << 1) - 1) & 0xf; /* <= {3,7,15,15} */ - *mini |= V1_X_INTERPOLY; - *mini |= ((d << 1) - 1) << 24; /* <= {1,3,5,7} << 24 */ - - /* Add scaling */ - if (sw1 < dw) - { - /* CLE bug */ - /* tmp = sw1*0x0800 / dw; */ - tmp = (sw1 - 2) * 0x0800 / dw; - *zoom |= ((tmp & 0x7ff) << 16) | V1_X_ZOOM_ENABLE; - } - } - - *dcount = sw - md; - return zoom_ok; -} - -/** - * @brief qword fetch register setting. - * - * @param format overlay pixel format. - * @param sw source width. - * - * @return qword fetch register setting - * - * @note Derived from VIA's V4L driver. See ddover.c, DDOver_GetFetch() - * @note Only call after uc_ovl_map_hzoom() - */ -static uint32_t -uc_ovl_map_qwfetch (uint32_t format, int sw) -{ - uint32_t fetch = 0; - - switch (format) - { - case IMGFMT_YV12: - case IMGFMT_I420: - fetch = ALIGN_TO (sw, 32) >> 4; - break; - case IMGFMT_UYVY: - case IMGFMT_YVYU: - case IMGFMT_YUY2: - fetch = (ALIGN_TO (sw << 1, 16) >> 4) + 1; - break; - case IMGFMT_BGR15: - case IMGFMT_BGR16: - fetch = (ALIGN_TO (sw << 1, 16) >> 4) + 1; - break; - case IMGFMT_BGR32: - fetch = (ALIGN_TO (sw << 2, 16) >> 4) + 1; - break; - default: - printf ("[unichrome] Unexpected pixelformat!"); - break; - } - - if (fetch < 4) - fetch = 4; - - return fetch; -} - -/** - * @brief Map pixel format. - * - * @param format pixel format. - * - * @return the mapped pixel format. - * - * @note Derived from VIA's V4L driver. See ddover.c, DDOver_GetV1Format() - */ -static uint32_t -uc_ovl_map_format (uint32_t format) -{ - switch (format) - { - case IMGFMT_UYVY: - case IMGFMT_YVYU: - case IMGFMT_YUY2: - return V1_COLORSPACE_SIGN | V1_YUV422; - case IMGFMT_IYUV: - return V1_COLORSPACE_SIGN | V1_YCbCr420 | V1_SWAP_SW; - case IMGFMT_YV12: - case IMGFMT_I420: - return V1_COLORSPACE_SIGN | V1_YCbCr420; - case IMGFMT_BGR15: - return V1_RGB15; - case IMGFMT_BGR16: - return V1_RGB16; - case IMGFMT_BGR32: - return V1_RGB32; - default: - printf ("[unichrome] Unexpected pixelformat!"); - return V1_YUV422; - } -} - -/** - * @brief Calculate V1 control and fifo-control register values. - * - * @param format pixel format. - * @param sw source width. - * @param hwrev CLE266 hardware revision. - * @param extfifo_on set this 1 if the extended FIFO is enabled. - * @param control will hold value for V1_CONTROL. - * @param fifo will hold value for V1_FIFO_CONTROL. - */ -static void -uc_ovl_map_v1_control (uint32_t format, int sw, - int hwrev, int extfifo_on, - uint32_t * control, uint32_t * fifo) -{ - *control = V1_BOB_ENABLE | uc_ovl_map_format (format); - - if (hwrev == 0x10) - { - *control |= V1_EXPIRE_NUM_F; - } - else - { - if (extfifo_on) - { - *control |= V1_EXPIRE_NUM_A | V1_FIFO_EXTENDED; - } - else - { - *control |= V1_EXPIRE_NUM; - } - } - - if ((format == IMGFMT_YV12) || (format == IMGFMT_I420)) - { - /* Minified video will be skewed without this workaround. */ - if (sw <= 80) /* Fetch count <= 5 */ - { - *fifo = UC_MAP_V1_FIFO_CONTROL (16, 0, 0); - } - else - { - if (hwrev == 0x10) - *fifo = UC_MAP_V1_FIFO_CONTROL (64, 56, 56); - else - *fifo = UC_MAP_V1_FIFO_CONTROL (16, 12, 8); - } - } - else - { - if (hwrev == 0x10) - { - *fifo = UC_MAP_V1_FIFO_CONTROL (64, 56, 56); /* Default rev 0x10 */ - } - else - { - if (extfifo_on) - *fifo = UC_MAP_V1_FIFO_CONTROL (48, 40, 40); - else - *fifo = UC_MAP_V1_FIFO_CONTROL (32, 29, 16); /* Default */ - } - } -} - -/** - * @brief Setup extended FIFO. - * - * @param extfifo_on pointer determining if extended fifo is enable or not. - * @param dst_w destination width. - */ -static void -uc_ovl_setup_fifo (int *extfifo_on, int dst_w) -{ - if (dst_w <= 1024) /* Disable extended FIFO */ - { - outb (0x16, 0x3c4); - outb (mclk_save[0], 0x3c5); - outb (0x17, 0x3c4); - outb (mclk_save[1], 0x3c5); - outb (0x18, 0x3c4); - outb (mclk_save[2], 0x3c5); - *extfifo_on = 0; - } - else /* Enable extended FIFO */ - { - outb (0x17, 0x3c4); - outb (0x2f, 0x3c5); - outb (0x16, 0x3c4); - outb ((mclk_save[0] & 0xf0) | 0x14, 0x3c5); - outb (0x18, 0x3c4); - outb (0x56, 0x3c5); - *extfifo_on = 1; - } -} - -static void -uc_ovl_vcmd_wait (volatile uint8_t * vio) -{ - while ((VIDEO_IN (vio, V_COMPOSE_MODE) - & (V1_COMMAND_FIRE | V3_COMMAND_FIRE))); -} - -/** - * @brief Probe hardware to find some useable chipset. - * - * @param verbose specifies verbose level. - * @param force specifies force mode : driver should ignore - * device_id (danger but useful for new devices) - * - * @returns 0 if it can handle something in PC. - * a negative error code otherwise. - */ -int -vixProbe (int verbose, int force) -{ - pciinfo_t lst[MAX_PCI_DEVICES]; - unsigned i, num_pci; - int err; - err = pci_scan (lst, &num_pci); - if (err) - { - printf ("[unichrome] Error occurred during pci scan: %s\n", - strerror (err)); - return err; - } - else - { - err = ENXIO; - for (i = 0; i < num_pci; i++) - { - if (lst[i].vendor == VENDOR_VIA2) - { - int idx; - const char *dname; - idx = find_chip (lst[i].device); - if (idx == -1) - continue; - dname = pci_device_name (VENDOR_VIA2, lst[i].device); - dname = dname ? dname : "Unknown chip"; - printf ("[unichrome] Found chip: %s\n", dname); - if ((lst[i].command & PCI_COMMAND_IO) == 0) - { - printf ("[unichrome] Device is disabled, ignoring\n"); - continue; - } - uc_cap.device_id = lst[i].device; - err = 0; - memcpy (&pci_info, &lst[i], sizeof (pciinfo_t)); - break; - } - } - } - - if (err && verbose) - printf ("[unichrome] Can't find chip\n"); - return err; -} - -/** - * @brief Initializes driver. - * - * @returns 0 if ok. - * a negative error code otherwise. - */ -int -vixInit (void) -{ - long tmp; - uc_mem = map_phys_mem (pci_info.base0, VIDEOMEMORY_SIZE); - enable_app_io (); - - outb (0x2f, 0x3c4); - tmp = inb (0x3c5) << 0x18; - vio = map_phys_mem (tmp, 0x1000); - - outb (0x16, 0x3c4); - mclk_save[0] = inb (0x3c5); - outb (0x17, 0x3c4); - mclk_save[1] = inb (0x3c5); - outb (0x18, 0x3c4); - mclk_save[2] = inb (0x3c5); - - uc_grkey.ckey.blue = 0x00; - uc_grkey.ckey.green = 0x00; - uc_grkey.ckey.red = 0x00; - - /* Detect whether we have a CLE266Ax or CLE266Cx */ - outb (0x4f, 0x3d4); - tmp = inb (0x3d5); - outb (0x4f, 0x3d4); - outb (0x55, 0x3d5); - outb (0x4f, 0x3d4); - if (0x55 == inb (0x3d5)) - { - /* Only CLE266Cx supports CR4F */ - hwrev = 0x11; - } - else - { - /* Otherwise assume to be a CLE266Ax */ - hwrev = 0x00; - } - outb (0x4f, 0x3d4); - outb (tmp, 0x3d5); - -#ifdef DEBUG_LOGFILE - logfile = fopen ("/tmp/uc_vidix.log", "w"); -#endif - return 0; -} - -/** - * @brief Destroys driver. - */ -void -vixDestroy (void) -{ -#ifdef DEBUG_LOGFILE - if (logfile) - fclose (logfile); -#endif - outb (0x16, 0x3c4); - outb (mclk_save[0], 0x3c5); - outb (0x17, 0x3c4); - outb (mclk_save[1], 0x3c5); - outb (0x18, 0x3c4); - outb (mclk_save[2], 0x3c5); - - disable_app_io (); - unmap_phys_mem (uc_mem, VIDEOMEMORY_SIZE); - unmap_phys_mem (vio, 0x1000); -} - -/** - * @brief Get chipset's hardware capabilities. - * - * @param to Pointer to the vidix_capability_t structure to be filled. - * - * @returns 0. - */ -int -vixGetCapability (vidix_capability_t * to) -{ - memcpy (to, &uc_cap, sizeof (vidix_capability_t)); - return 0; -} - -/** - * @brief Report if the video FourCC is supported by hardware. - * - * @param fourcc input image format. - * - * @returns 1 if the fourcc is supported. - * 0 otherwise. - */ -static int -is_supported_fourcc (uint32_t fourcc) -{ - switch (fourcc) - { - case IMGFMT_YV12: - case IMGFMT_I420: - case IMGFMT_UYVY: - case IMGFMT_YVYU: - case IMGFMT_YUY2: - case IMGFMT_BGR15: - case IMGFMT_BGR16: - case IMGFMT_BGR32: - return 1; - default: - return 0; - } -} - -/** - * @brief Try to configure video memory for given fourcc. - * - * @param to Pointer to the vidix_fourcc_t structure to be filled. - * - * @returns 0 if ok. - * errno otherwise. - */ -int -vixQueryFourcc (vidix_fourcc_t * to) -{ - if (is_supported_fourcc (to->fourcc)) - { - to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | - VID_DEPTH_4BPP | VID_DEPTH_8BPP | - VID_DEPTH_12BPP | VID_DEPTH_15BPP | - VID_DEPTH_16BPP | VID_DEPTH_24BPP | VID_DEPTH_32BPP; - to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; - return 0; - } - else - to->depth = to->flags = 0; - return ENOSYS; -} - -/** - * @brief Get the GrKeys - * - * @param grkey Pointer to the vidix_grkey_t structure to be filled by driver. - * - * @return 0. - */ -int -vixGetGrKeys (vidix_grkey_t * grkey) -{ - memcpy (grkey, &uc_grkey, sizeof (vidix_grkey_t)); - return (0); -} - -/** - * @brief Set the GrKeys - * - * @param grkey Colorkey to be set. - * - * @return 0. - */ -int -vixSetGrKeys (const vidix_grkey_t * grkey) -{ - unsigned long dwCompose = VIDEO_IN (vio, V_COMPOSE_MODE) & ~0x0f; - memcpy (&uc_grkey, grkey, sizeof (vidix_grkey_t)); - if (uc_grkey.ckey.op != CKEY_FALSE) - { - /* Set colorkey (how do I detect BPP in hardware ??) */ - unsigned long ckey; - if (1) /* Assume 16-bit graphics */ - { - ckey = (grkey->ckey.blue & 0x1f) - | ((grkey->ckey.green & 0x3f) << 5) - | ((grkey->ckey.red & 0x1f) << 11); - } - else - { - ckey = (grkey->ckey.blue) - | (grkey->ckey.green << 8) | (grkey->ckey.red << 16); - } - VIDEO_OUT (vio, V_COLOR_KEY, ckey); - dwCompose |= SELECT_VIDEO_IF_COLOR_KEY; - } - - /* Execute the changes */ - VIDEO_OUT (vio, V_COMPOSE_MODE, dwCompose | V1_COMMAND_FIRE); - return (0); -} - -/** - * @brief Unichrome driver equalizer capabilities. - */ -vidix_video_eq_t equal = { - VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION | VEQ_CAP_HUE, - 300, 100, 0, 0, 0, 0, 0, 0 -}; - - -/** - * @brief Get the equalizer capabilities. - * - * @param eq Pointer to the vidix_video_eq_t structure to be filled by driver. - * - * @return 0. - */ -int -vixPlaybackGetEq (vidix_video_eq_t * eq) -{ - memcpy (eq, &equal, sizeof (vidix_video_eq_t)); - return 0; -} - -/** - * @brief Set the equalizer capabilities for color correction - * - * @param eq equalizer capabilities to be set. - * - * @return 0. - */ -int -vixPlaybackSetEq (const vidix_video_eq_t * eq) -{ - return 0; -} - -/** - * @brief Y, U, V offsets. - */ -static int YOffs, UOffs, VOffs; - -/** - * @brief Configure driver for playback. Driver should prepare BES. - * - * @param info configuration description for playback. - * - * @returns 0 in case of success. - * -1 otherwise. - */ -int -vixConfigPlayback (vidix_playback_t * info) -{ - int src_w, drw_w; - int src_h, drw_h; - long base0, pitch; - int uv_size, swap_uv; - unsigned int i; - int extfifo_on; - - /* Overlay register settings */ - uint32_t win_start, win_end; - uint32_t zoom, mini; - uint32_t dcount, falign, qwfetch; - uint32_t y_start, u_start, v_start; - uint32_t v_ctrl, fifo_ctrl; - - if (!is_supported_fourcc (info->fourcc)) - return -1; - - src_w = info->src.w; - src_h = info->src.h; - - drw_w = info->dest.w; - drw_h = info->dest.h; - - /* Setup FIFO */ - uc_ovl_setup_fifo (&extfifo_on, src_w); - - /* Get image format, FIFO size, etc. */ - uc_ovl_map_v1_control (info->fourcc, src_w, hwrev, extfifo_on, - &v_ctrl, &fifo_ctrl); - - /* Setup layer window */ - win_start = (info->dest.x << 16) | info->dest.y; - win_end = ((info->dest.x + drw_w - 1) << 16) | (info->dest.y + drw_h - 1); - - /* Get scaling and data-fetch parameters */ - zoom = 0; - mini = 0; - uc_ovl_map_vzoom (src_h, drw_h, &zoom, &mini); - uc_ovl_map_hzoom (src_w, drw_w, &zoom, &mini, &falign, &dcount); - qwfetch = uc_ovl_map_qwfetch (info->fourcc, src_w); - - /* Calculate buffer sizes */ - swap_uv = 0; - switch (info->fourcc) - { - case IMGFMT_YV12: - swap_uv = 1; - case IMGFMT_I420: - case IMGFMT_UYVY: - case IMGFMT_YVYU: - pitch = ALIGN_TO (src_w, 32); - uv_size = (pitch >> 1) * (src_h >> 1); - break; - - case IMGFMT_YUY2: - case IMGFMT_BGR15: - case IMGFMT_BGR16: - pitch = ALIGN_TO (src_w << 1, 32); - uv_size = 0; - break; - - case IMGFMT_BGR32: - pitch = ALIGN_TO (src_w << 2, 32); - uv_size = 0; - break; - } - if ((src_w > 4096) || (src_h > 4096) || - (src_w < 32) || (src_h < 1) || (pitch > 0x1fff)) - { - printf ("[unichrome] Layer size out of bounds\n"); - } - - /* Calculate offsets */ - info->offset.y = 0; - info->offset.v = info->offset.y + pitch * src_h; - info->offset.u = info->offset.v + uv_size; - info->frame_size = info->offset.u + uv_size; - YOffs = info->offset.y; - UOffs = (swap_uv ? info->offset.v : info->offset.u); - VOffs = (swap_uv ? info->offset.u : info->offset.v); - - /* Assume we have 2 MB to play with */ - info->num_frames = FRAMEBUFFER_SIZE / info->frame_size; - if (info->num_frames > VID_PLAY_MAXFRAMES) - info->num_frames = VID_PLAY_MAXFRAMES; - - /* Start at 6 MB. Let's hope it's not in use. */ - base0 = FRAMEBUFFER_START; - info->dga_addr = uc_mem + base0; - - info->dest.pitch.y = 32; - info->dest.pitch.u = 32; - info->dest.pitch.v = 32; - - for (i = 0; i < info->num_frames; i++) - { - info->offsets[i] = info->frame_size * i; - frames[i] = base0 + info->offsets[i]; - } - - /* Write to the hardware */ - uc_ovl_vcmd_wait (vio); - - /* Configure diy_pitchlay parameters now */ - if (v_ctrl & V1_COLORSPACE_SIGN) - { - if (hwrev >= 0x10) - { - VIDEO_OUT (vio, V1_ColorSpaceReg_2, ColorSpaceValue_2_3123C0); - VIDEO_OUT (vio, V1_ColorSpaceReg_1, ColorSpaceValue_1_3123C0); - } - else - { - VIDEO_OUT (vio, V1_ColorSpaceReg_2, ColorSpaceValue_2); - VIDEO_OUT (vio, V1_ColorSpaceReg_1, ColorSpaceValue_1); - } - } - - VIDEO_OUT (vio, V1_CONTROL, v_ctrl); - VIDEO_OUT (vio, V_FIFO_CONTROL, fifo_ctrl); - - VIDEO_OUT (vio, V1_WIN_START_Y, win_start); - VIDEO_OUT (vio, V1_WIN_END_Y, win_end); - - VIDEO_OUT (vio, V1_SOURCE_HEIGHT, (src_h << 16) | dcount); - - VIDEO_OUT (vio, V12_QWORD_PER_LINE, qwfetch << 20); - VIDEO_OUT (vio, V1_STRIDE, pitch | ((pitch >> 1) << 16)); - - VIDEO_OUT (vio, V1_MINI_CONTROL, mini); - VIDEO_OUT (vio, V1_ZOOM_CONTROL, zoom); - - /* Configure buffer address and execute the changes now! */ - vixPlaybackFrameSelect (0); - - return 0; -} - -/** - * @brief Set playback on : driver should activate BES on this call. - * - * @return 0. - */ -int -vixPlaybackOn (void) -{ - LOGWRITE ("Enable overlay\n"); - - /* Turn on overlay */ - VIDEO_OUT (vio, V1_CONTROL, VIDEO_IN (vio, V1_CONTROL) | V1_ENABLE); - - /* Execute the changes */ - VIDEO_OUT (vio, V_COMPOSE_MODE, - VIDEO_IN (vio, V_COMPOSE_MODE) | V1_COMMAND_FIRE); - - return 0; -} - -/** - * @brief Set playback off : driver should deactivate BES on this call. - * - * @return 0. - */ -int -vixPlaybackOff (void) -{ - LOGWRITE ("Disable overlay\n"); - - uc_ovl_vcmd_wait (vio); - - /* Restore FIFO */ - VIDEO_OUT (vio, V_FIFO_CONTROL, UC_MAP_V1_FIFO_CONTROL (16, 12, 8)); - - /* Turn off overlay */ - VIDEO_OUT (vio, V1_CONTROL, VIDEO_IN (vio, V1_CONTROL) & ~V1_ENABLE); - - /* Execute the changes */ - VIDEO_OUT (vio, V_COMPOSE_MODE, - VIDEO_IN (vio, V_COMPOSE_MODE) | V1_COMMAND_FIRE); - - return 0; -} - -/** - * @brief Driver should prepare and activate corresponded frame. - * - * @param frame the frame index. - * - * @return 0. - * - * @note This function is used only for double and triple buffering - * and never used for single buffering playback. - */ -int -vixPlaybackFrameSelect (unsigned int frame) -{ - LOGWRITE ("Frame select\n"); - - uc_ovl_vcmd_wait (vio); - - /* Configure buffer address */ - VIDEO_OUT (vio, V1_STARTADDR_Y0, frames[frame] + YOffs); - VIDEO_OUT (vio, V1_STARTADDR_CB0, frames[frame] + UOffs); - VIDEO_OUT (vio, V1_STARTADDR_CR0, frames[frame] + VOffs); - - /* Execute the changes */ - VIDEO_OUT (vio, V_COMPOSE_MODE, - VIDEO_IN (vio, V_COMPOSE_MODE) | V1_COMMAND_FIRE); - - return 0; -}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/vidix/mach64.h Sun Apr 01 00:02:43 2007 +0000 @@ -0,0 +1,2481 @@ +/* + * mach64.h + * This software has been released under the terms of the GNU Public + * license. See http://www.gnu.org/copyleft/gpl.html for details. + * + * It's based on radeonfb, X11, GATOS sources +*/ + +#ifndef __MACH64_INCLUDED +#define __MACH64_INCLUDED 1 + +/* Note: this model of accessing to IO space is based on MMIO technology. +This means that this sources don't support ISA and VLB cards */ +#define BlockIOTag(val) (val) +#define IOPortTag(sparce,val) (val) + +/* MDA/[M]CGA/EGA/VGA I/O ports */ +#define GENVS 0x0102u /* Write (and Read on uC only) */ + +#define R_GENLPS 0x03b9u /* Read */ + +#define GENHP 0x03bfu + +#define ATTRX 0x03c0u +#define ATTRD 0x03c1u +#define GENS0 0x03c2u /* Read */ +#define GENMO 0x03c2u /* Write */ +#define GENENB 0x03c3u /* Read */ +#define SEQX 0x03c4u +#define SEQD 0x03c5u +#define VGA_DAC_MASK 0x03c6u +#define VGA_DAC_READ 0x03c7u +#define VGA_DAC_WRITE 0x03c8u +#define VGA_DAC_DATA 0x03c9u +#define R_GENFC 0x03cau /* Read */ +/* ? 0x03cbu */ +#define R_GENMO 0x03ccu /* Read */ +/* ? 0x03cdu */ +#define GRAX 0x03ceu +#define GRAD 0x03cfu + +#define GENB 0x03d9u + +#define GENLPS 0x03dcu /* Write */ +#define KCX 0x03ddu +#define KCD 0x03deu + +#define GENENA 0x46e8u /* Write */ + +/* I/O port base numbers */ +#define MonochromeIOBase 0x03b0u +#define ColourIOBase 0x03d0u + +/* Other MDA/[M]CGA/EGA/VGA I/O ports */ +/* ?(_IOBase) ((_IOBase) + 0x00u) */ /* CRTX synonym */ +/* ?(_IOBase) ((_IOBase) + 0x01u) */ /* CRTD synonym */ +/* ?(_IOBase) ((_IOBase) + 0x02u) */ /* CRTX synonym */ +/* ?(_IOBase) ((_IOBase) + 0x03u) */ /* CRTD synonym */ +#define CRTX(_IOBase) ((_IOBase) + 0x04u) +#define CRTD(_IOBase) ((_IOBase) + 0x05u) +/* ?(_IOBase) ((_IOBase) + 0x06u) */ +/* ?(_IOBase) ((_IOBase) + 0x07u) */ +#define GENMC(_IOBase) ((_IOBase) + 0x08u) +/* ?(_IOBase) ((_IOBase) + 0x09u) */ /* R_GENLPS/GENB */ +#define GENS1(_IOBase) ((_IOBase) + 0x0au) /* Read */ +#define GENFC(_IOBase) ((_IOBase) + 0x0au) /* Write */ +#define GENLPC(_IOBase) ((_IOBase) + 0x0bu) +/* ?(_IOBase) ((_IOBase) + 0x0cu) */ /* /GENLPS */ +/* ?(_IOBase) ((_IOBase) + 0x0du) */ /* /KCX */ +/* ?(_IOBase) ((_IOBase) + 0x0eu) */ /* /KCD */ +/* ?(_IOBase) ((_IOBase) + 0x0fu) */ /* GENHP/ */ + +/* 8514/A VESA approved register definitions */ +#define DISP_STAT 0x02e8u /* Read */ +#define SENSE 0x0001u /* Presumably belong here */ +#define VBLANK 0x0002u +#define HORTOG 0x0004u +#define H_TOTAL 0x02e8u /* Write */ +#define IBM_DAC_MASK 0x02eau +#define IBM_DAC_READ 0x02ebu +#define IBM_DAC_WRITE 0x02ecu +#define IBM_DAC_DATA 0x02edu +#define H_DISP 0x06e8u /* Write */ +#define H_SYNC_STRT 0x0ae8u /* Write */ +#define H_SYNC_WID 0x0ee8u /* Write */ +#define HSYNCPOL_POS 0x0000u +#define HSYNCPOL_NEG 0x0020u +#define H_POLARITY_POS HSYNCPOL_POS /* Sigh */ +#define H_POLARITY_NEG HSYNCPOL_NEG /* Sigh */ +#define V_TOTAL 0x12e8u /* Write */ +#define V_DISP 0x16e8u /* Write */ +#define V_SYNC_STRT 0x1ae8u /* Write */ +#define V_SYNC_WID 0x1ee8u /* Write */ +#define VSYNCPOL_POS 0x0000u +#define VSYNCPOL_NEG 0x0020u +#define V_POLARITY_POS VSYNCPOL_POS /* Sigh */ +#define V_POLARITY_NEG VSYNCPOL_NEG /* Sigh */ +#define DISP_CNTL 0x22e8u /* Write */ +#define ODDBNKENAB 0x0001u +#define MEMCFG_2 0x0000u +#define MEMCFG_4 0x0002u +#define MEMCFG_6 0x0004u +#define MEMCFG_8 0x0006u +#define DBLSCAN 0x0008u +#define INTERLACE 0x0010u +#define DISPEN_NC 0x0000u +#define DISPEN_ENAB 0x0020u +#define DISPEN_DISAB 0x0040u +#define R_H_TOTAL 0x26e8u /* Read */ +/* ? 0x2ae8u */ +/* ? 0x2ee8u */ +/* ? 0x32e8u */ +/* ? 0x36e8u */ +/* ? 0x3ae8u */ +/* ? 0x3ee8u */ +#define SUBSYS_STAT 0x42e8u /* Read */ +#define VBLNKFLG 0x0001u +#define PICKFLAG 0x0002u +#define INVALIDIO 0x0004u +#define GPIDLE 0x0008u +#define MONITORID_MASK 0x0070u +/* MONITORID_? 0x0000u */ +#define MONITORID_8507 0x0010u +#define MONITORID_8514 0x0020u +/* MONITORID_? 0x0030u */ +/* MONITORID_? 0x0040u */ +#define MONITORID_8503 0x0050u +#define MONITORID_8512 0x0060u +#define MONITORID_8513 0x0060u +#define MONITORID_NONE 0x0070u +#define _8PLANE 0x0080u +#define SUBSYS_CNTL 0x42e8u /* Write */ +#define RVBLNKFLG 0x0001u +#define RPICKFLAG 0x0002u +#define RINVALIDIO 0x0004u +#define RGPIDLE 0x0008u +#define IVBLNKFLG 0x0100u +#define IPICKFLAG 0x0200u +#define IINVALIDIO 0x0400u +#define IGPIDLE 0x0800u +#define CHPTEST_NC 0x0000u +#define CHPTEST_NORMAL 0x1000u +#define CHPTEST_ENAB 0x2000u +#define GPCTRL_NC 0x0000u +#define GPCTRL_ENAB 0x4000u +#define GPCTRL_RESET 0x8000u +#define ROM_PAGE_SEL 0x46e8u /* Write */ +#define ADVFUNC_CNTL 0x4ae8u /* Write */ +#define DISABPASSTHRU 0x0001u +#define CLOKSEL 0x0004u +/* ? 0x4ee8u */ +#define EXT_CONFIG_0 0x52e8u /* C & T 82C480 */ +#define EXT_CONFIG_1 0x56e8u /* C & T 82C480 */ +#define EXT_CONFIG_2 0x5ae8u /* C & T 82C480 */ +#define EXT_CONFIG_3 0x5ee8u /* C & T 82C480 */ +/* ? 0x62e8u */ +/* ? 0x66e8u */ +/* ? 0x6ae8u */ +/* ? 0x6ee8u */ +/* ? 0x72e8u */ +/* ? 0x76e8u */ +/* ? 0x7ae8u */ +/* ? 0x7ee8u */ +#define CUR_Y 0x82e8u +#define CUR_X 0x86e8u +#define DESTY_AXSTP 0x8ae8u /* Write */ +#define DESTX_DIASTP 0x8ee8u /* Write */ +#define ERR_TERM 0x92e8u +#define MAJ_AXIS_PCNT 0x96e8u /* Write */ +#define GP_STAT 0x9ae8u /* Read */ +#define GE_STAT 0x9ae8u /* Alias */ +#define DATARDY 0x0100u +#define DATA_READY DATARDY /* Alias */ +#define GPBUSY 0x0200u +#define CMD 0x9ae8u /* Write */ +#define WRTDATA 0x0001u +#define PLANAR 0x0002u +#define LASTPIX 0x0004u +#define LINETYPE 0x0008u +#define DRAW 0x0010u +#define INC_X 0x0020u +#define YMAJAXIS 0x0040u +#define INC_Y 0x0080u +#define PCDATA 0x0100u +#define _16BIT 0x0200u +#define CMD_NOP 0x0000u +#define CMD_OP_MSK 0xf000u +#define BYTSEQ 0x1000u +#define CMD_LINE 0x2000u +#define CMD_RECT 0x4000u +#define CMD_RECTV1 0x6000u +#define CMD_RECTV2 0x8000u +#define CMD_LINEAF 0xa000u +#define CMD_BITBLT 0xc000u +#define SHORT_STROKE 0x9ee8u /* Write */ +#define SSVDRAW 0x0010u +#define VECDIR_000 0x0000u +#define VECDIR_045 0x0020u +#define VECDIR_090 0x0040u +#define VECDIR_135 0x0060u +#define VECDIR_180 0x0080u +#define VECDIR_225 0x00a0u +#define VECDIR_270 0x00c0u +#define VECDIR_315 0x00e0u +#define BKGD_COLOR 0xa2e8u /* Write */ +#define FRGD_COLOR 0xa6e8u /* Write */ +#define WRT_MASK 0xaae8u /* Write */ +#define RD_MASK 0xaee8u /* Write */ +#define COLOR_CMP 0xb2e8u /* Write */ +#define BKGD_MIX 0xb6e8u /* Write */ +/* 0x001fu See MIX_* definitions below */ +#define BSS_BKGDCOL 0x0000u +#define BSS_FRGDCOL 0x0020u +#define BSS_PCDATA 0x0040u +#define BSS_BITBLT 0x0060u +#define FRGD_MIX 0xbae8u /* Write */ +/* 0x001fu See MIX_* definitions below */ +#define FSS_BKGDCOL 0x0000u +#define FSS_FRGDCOL 0x0020u +#define FSS_PCDATA 0x0040u +#define FSS_BITBLT 0x0060u +#define MULTIFUNC_CNTL 0xbee8u /* Write */ +#define MIN_AXIS_PCNT 0x0000u +#define SCISSORS_T 0x1000u +#define SCISSORS_L 0x2000u +#define SCISSORS_B 0x3000u +#define SCISSORS_R 0x4000u +#define M32_MEM_CNTL 0x5000u +#define HORCFG_4 0x0000u +#define HORCFG_5 0x0001u +#define HORCFG_8 0x0002u +#define HORCFG_10 0x0003u +#define VRTCFG_2 0x0000u +#define VRTCFG_4 0x0004u +#define VRTCFG_6 0x0008u +#define VRTCFG_8 0x000cu +#define BUFSWP 0x0010u +#define PATTERN_L 0x8000u +#define PATTERN_H 0x9000u +#define PIX_CNTL 0xa000u +#define PLANEMODE 0x0004u +#define COLCMPOP_F 0x0000u +#define COLCMPOP_T 0x0008u +#define COLCMPOP_GE 0x0010u +#define COLCMPOP_LT 0x0018u +#define COLCMPOP_NE 0x0020u +#define COLCMPOP_EQ 0x0028u +#define COLCMPOP_LE 0x0030u +#define COLCMPOP_GT 0x0038u +#define MIXSEL_FRGDMIX 0x0000u +#define MIXSEL_PATT 0x0040u +#define MIXSEL_EXPPC 0x0080u +#define MIXSEL_EXPBLT 0x00c0u +/* ? 0xc2e8u */ +/* ? 0xc6e8u */ +/* ? 0xcae8u */ +/* ? 0xcee8u */ +/* ? 0xd2e8u */ +/* ? 0xd6e8u */ +/* ? 0xdae8u */ +/* ? 0xdee8u */ +#define PIX_TRANS 0xe2e8u +/* ? 0xe6e8u */ +/* ? 0xeae8u */ +/* ? 0xeee8u */ +/* ? 0xf2e8u */ +/* ? 0xf6e8u */ +/* ? 0xfae8u */ +/* ? 0xfee8u */ + +/* ATI Mach8 & Mach32 register definitions */ +#define OVERSCAN_COLOR_8 0x02eeu /* Write */ /* Mach32 */ +#define OVERSCAN_BLUE_24 0x02efu /* Write */ /* Mach32 */ +#define OVERSCAN_GREEN_24 0x06eeu /* Write */ /* Mach32 */ +#define OVERSCAN_RED_24 0x06efu /* Write */ /* Mach32 */ +#define CURSOR_OFFSET_LO 0x0aeeu /* Write */ /* Mach32 */ +#define CURSOR_OFFSET_HI 0x0eeeu /* Write */ /* Mach32 */ +#define CONFIG_STATUS_1 0x12eeu /* Read */ +#define CLK_MODE 0x0001u /* Mach8 */ +#define BUS_16 0x0002u /* Mach8 */ +#define MC_BUS 0x0004u /* Mach8 */ +#define EEPROM_ENA 0x0008u /* Mach8 */ +#define DRAM_ENA 0x0010u /* Mach8 */ +#define MEM_INSTALLED 0x0060u /* Mach8 */ +#define ROM_ENA 0x0080u /* Mach8 */ +#define ROM_PAGE_ENA 0x0100u /* Mach8 */ +#define ROM_LOCATION 0xfe00u /* Mach8 */ +#define _8514_ONLY 0x0001u /* Mach32 */ +#define BUS_TYPE 0x000eu /* Mach32 */ +#define ISA_16_BIT 0x0000u /* Mach32 */ +#define EISA 0x0002u /* Mach32 */ +#define MICRO_C_16_BIT 0x0004u /* Mach32 */ +#define MICRO_C_8_BIT 0x0006u /* Mach32 */ +#define LOCAL_386SX 0x0008u /* Mach32 */ +#define LOCAL_386DX 0x000au /* Mach32 */ +#define LOCAL_486 0x000cu /* Mach32 */ +#define PCI 0x000eu /* Mach32 */ +#define MEM_TYPE 0x0070u /* Mach32 */ +#define CHIP_DIS 0x0080u /* Mach32 */ +#define TST_VCTR_ENA 0x0100u /* Mach32 */ +#define DACTYPE 0x0e00u /* Mach32 */ +#define MC_ADR_DECODE 0x1000u /* Mach32 */ +#define CARD_ID 0xe000u /* Mach32 */ +#define HORZ_CURSOR_POSN 0x12eeu /* Write */ /* Mach32 */ +#define CONFIG_STATUS_2 0x16eeu /* Read */ +#define SHARE_CLOCK 0x0001u /* Mach8 */ +#define HIRES_BOOT 0x0002u /* Mach8 */ +#define EPROM_16_ENA 0x0004u /* Mach8 */ +#define WRITE_PER_BIT 0x0008u /* Mach8 */ +#define FLASH_ENA 0x0010u /* Mach8 */ +#define SLOW_SEQ_EN 0x0001u /* Mach32 */ +#define MEM_ADDR_DIS 0x0002u /* Mach32 */ +#define ISA_16_ENA 0x0004u /* Mach32 */ +#define KOR_TXT_MODE_ENA 0x0008u /* Mach32 */ +#define LOCAL_BUS_SUPPORT 0x0030u /* Mach32 */ +#define LOCAL_BUS_CONFIG_2 0x0040u /* Mach32 */ +#define LOCAL_BUS_RD_DLY_ENA 0x0080u /* Mach32 */ +#define LOCAL_DAC_EN 0x0100u /* Mach32 */ +#define LOCAL_RDY_EN 0x0200u /* Mach32 */ +#define EEPROM_ADR_SEL 0x0400u /* Mach32 */ +#define GE_STRAP_SEL 0x0800u /* Mach32 */ +#define VESA_RDY 0x1000u /* Mach32 */ +#define Z4GB 0x2000u /* Mach32 */ +#define LOC2_MDRAM 0x4000u /* Mach32 */ +#define VERT_CURSOR_POSN 0x16eeu /* Write */ /* Mach32 */ +#define FIFO_TEST_DATA 0x1aeeu /* Read */ /* Mach32 */ +#define CURSOR_COLOR_0 0x1aeeu /* Write */ /* Mach32 */ +#define CURSOR_COLOR_1 0x1aefu /* Write */ /* Mach32 */ +#define HORZ_CURSOR_OFFSET 0x1eeeu /* Write */ /* Mach32 */ +#define VERT_CURSOR_OFFSET 0x1eefu /* Write */ /* Mach32 */ +#define PCI_CNTL 0x22eeu /* Mach32-PCI */ +#define CRT_PITCH 0x26eeu /* Write */ +#define CRT_OFFSET_LO 0x2aeeu /* Write */ +#define CRT_OFFSET_HI 0x2eeeu /* Write */ +#define LOCAL_CNTL 0x32eeu /* Mach32 */ +#define FIFO_OPT 0x36eeu /* Write */ /* Mach8 */ +#define MISC_OPTIONS 0x36eeu /* Mach32 */ +#define W_STATE_ENA 0x0000u /* Mach32 */ +#define HOST_8_ENA 0x0001u /* Mach32 */ +#define MEM_SIZE_ALIAS 0x000cu /* Mach32 */ +#define MEM_SIZE_512K 0x0000u /* Mach32 */ +#define MEM_SIZE_1M 0x0004u /* Mach32 */ +#define MEM_SIZE_2M 0x0008u /* Mach32 */ +#define MEM_SIZE_4M 0x000cu /* Mach32 */ +#define DISABLE_VGA 0x0010u /* Mach32 */ +#define _16_BIT_IO 0x0020u /* Mach32 */ +#define DISABLE_DAC 0x0040u /* Mach32 */ +#define DLY_LATCH_ENA 0x0080u /* Mach32 */ +#define TEST_MODE 0x0100u /* Mach32 */ +#define BLK_WR_ENA 0x0400u /* Mach32 */ +#define _64_DRAW_ENA 0x0800u /* Mach32 */ +#define FIFO_TEST_TAG 0x3aeeu /* Read */ /* Mach32 */ +#define EXT_CURSOR_COLOR_0 0x3aeeu /* Write */ /* Mach32 */ +#define EXT_CURSOR_COLOR_1 0x3eeeu /* Write */ /* Mach32 */ +#define MEM_BNDRY 0x42eeu /* Mach32 */ +#define MEM_PAGE_BNDRY 0x000fu /* Mach32 */ +#define MEM_BNDRY_ENA 0x0010u /* Mach32 */ +#define SHADOW_CTL 0x46eeu /* Write */ +#define CLOCK_SEL 0x4aeeu +/* DISABPASSTHRU 0x0001u See ADVFUNC_CNTL */ +#define VFIFO_DEPTH_1 0x0100u /* Mach32 */ +#define VFIFO_DEPTH_2 0x0200u /* Mach32 */ +#define VFIFO_DEPTH_3 0x0300u /* Mach32 */ +#define VFIFO_DEPTH_4 0x0400u /* Mach32 */ +#define VFIFO_DEPTH_5 0x0500u /* Mach32 */ +#define VFIFO_DEPTH_6 0x0600u /* Mach32 */ +#define VFIFO_DEPTH_7 0x0700u /* Mach32 */ +#define VFIFO_DEPTH_8 0x0800u /* Mach32 */ +#define VFIFO_DEPTH_9 0x0900u /* Mach32 */ +#define VFIFO_DEPTH_A 0x0a00u /* Mach32 */ +#define VFIFO_DEPTH_B 0x0b00u /* Mach32 */ +#define VFIFO_DEPTH_C 0x0c00u /* Mach32 */ +#define VFIFO_DEPTH_D 0x0d00u /* Mach32 */ +#define VFIFO_DEPTH_E 0x0e00u /* Mach32 */ +#define VFIFO_DEPTH_F 0x0f00u /* Mach32 */ +#define COMPOSITE_SYNC 0x1000u +/* ? 0x4eeeu */ +#define ROM_ADDR_1 0x52eeu +#define BIOS_BASE_SEGMENT 0x007fu /* Mach32 */ +/* ? 0xff80u */ /* Mach32 */ +#define ROM_ADDR_2 0x56eeu /* Sick ... */ +#define SHADOW_SET 0x5aeeu /* Write */ +#define MEM_CFG 0x5eeeu /* Mach32 */ +#define MEM_APERT_SEL 0x0003u /* Mach32 */ +#define MEM_APERT_PAGE 0x000cu /* Mach32 */ +#define MEM_APERT_LOC 0xfff0u /* Mach32 */ +#define EXT_GE_STATUS 0x62eeu /* Read */ /* Mach32 */ +#define HORZ_OVERSCAN 0x62eeu /* Write */ /* Mach32 */ +#define VERT_OVERSCAN 0x66eeu /* Write */ /* Mach32 */ +#define MAX_WAITSTATES 0x6aeeu +#define GE_OFFSET_LO 0x6eeeu /* Write */ +#define BOUNDS_LEFT 0x72eeu /* Read */ +#define GE_OFFSET_HI 0x72eeu /* Write */ +#define BOUNDS_TOP 0x76eeu /* Read */ +#define GE_PITCH 0x76eeu /* Write */ +#define BOUNDS_RIGHT 0x7aeeu /* Read */ +#define EXT_GE_CONFIG 0x7aeeu /* Write */ /* Mach32 */ +#define MONITOR_ALIAS 0x0007u /* Mach32 */ +/* MONITOR_? 0x0000u */ /* Mach32 */ +#define MONITOR_8507 0x0001u /* Mach32 */ +#define MONITOR_8514 0x0002u /* Mach32 */ +/* MONITOR_? 0x0003u */ /* Mach32 */ +/* MONITOR_? 0x0004u */ /* Mach32 */ +#define MONITOR_8503 0x0005u /* Mach32 */ +#define MONITOR_8512 0x0006u /* Mach32 */ +#define MONITOR_8513 0x0006u /* Mach32 */ +#define MONITOR_NONE 0x0007u /* Mach32 */ +#define ALIAS_ENA 0x0008u /* Mach32 */ +#define PIXEL_WIDTH_4 0x0000u /* Mach32 */ +#define PIXEL_WIDTH_8 0x0010u /* Mach32 */ +#define PIXEL_WIDTH_16 0x0020u /* Mach32 */ +#define PIXEL_WIDTH_24 0x0030u /* Mach32 */ +#define RGB16_555 0x0000u /* Mach32 */ +#define RGB16_565 0x0040u /* Mach32 */ +#define RGB16_655 0x0080u /* Mach32 */ +#define RGB16_664 0x00c0u /* Mach32 */ +#define MULTIPLEX_PIXELS 0x0100u /* Mach32 */ +#define RGB24 0x0000u /* Mach32 */ +#define RGBx24 0x0200u /* Mach32 */ +#define BGR24 0x0400u /* Mach32 */ +#define xBGR24 0x0600u /* Mach32 */ +#define DAC_8_BIT_EN 0x4000u /* Mach32 */ +#define ORDER_16BPP_565 RGB16_565 /* Mach32 */ +#define BOUNDS_BOTTOM 0x7eeeu /* Read */ +#define MISC_CNTL 0x7eeeu /* Write */ /* Mach32 */ +#define PATT_DATA_INDEX 0x82eeu +/* ? 0x86eeu */ +/* ? 0x8aeeu */ +#define R_EXT_GE_CONFIG 0x8eeeu /* Read */ /* Mach32 */ +#define PATT_DATA 0x8eeeu /* Write */ +#define R_MISC_CNTL 0x92eeu /* Read */ /* Mach32 */ +#define BRES_COUNT 0x96eeu +#define EXT_FIFO_STATUS 0x9aeeu /* Read */ +#define LINEDRAW_INDEX 0x9aeeu /* Write */ +/* ? 0x9eeeu */ +#define LINEDRAW_OPT 0xa2eeu +#define BOUNDS_RESET 0x0100u +#define CLIP_MODE_0 0x0000u /* Clip exception disabled */ +#define CLIP_MODE_1 0x0200u /* Line segments */ +#define CLIP_MODE_2 0x0400u /* Polygon boundary lines */ +#define CLIP_MODE_3 0x0600u /* Patterned lines */ +#define DEST_X_START 0xa6eeu /* Write */ +#define DEST_X_END 0xaaeeu /* Write */ +#define DEST_Y_END 0xaeeeu /* Write */ +#define R_H_TOTAL_DISP 0xb2eeu /* Read */ /* Mach32 */ +#define SRC_X_STRT 0xb2eeu /* Write */ +#define R_H_SYNC_STRT 0xb6eeu /* Read */ /* Mach32 */ +#define ALU_BG_FN 0xb6eeu /* Write */ +#define R_H_SYNC_WID 0xbaeeu /* Read */ /* Mach32 */ +#define ALU_FG_FN 0xbaeeu /* Write */ +#define SRC_X_END 0xbeeeu /* Write */ +#define R_V_TOTAL 0xc2eeu /* Read */ +#define SRC_Y_DIR 0xc2eeu /* Write */ +#define R_V_DISP 0xc6eeu /* Read */ /* Mach32 */ +#define EXT_SHORT_STROKE 0xc6eeu /* Write */ +#define R_V_SYNC_STRT 0xcaeeu /* Read */ /* Mach32 */ +#define SCAN_X 0xcaeeu /* Write */ +#define VERT_LINE_CNTR 0xceeeu /* Read */ /* Mach32 */ +#define DP_CONFIG 0xceeeu /* Write */ +#define READ_WRITE 0x0001u +#define DATA_WIDTH 0x0200u +#define DATA_ORDER 0x1000u +#define FG_COLOR_SRC_FG 0x2000u +#define FG_COLOR_SRC_BLIT 0x6000u +#define R_V_SYNC_WID 0xd2eeu /* Read */ +#define PATT_LENGTH 0xd2eeu /* Write */ +#define PATT_INDEX 0xd6eeu /* Write */ +#define READ_SRC_X 0xdaeeu /* Read */ /* Mach32 */ +#define EXT_SCISSOR_L 0xdaeeu /* Write */ +#define READ_SRC_Y 0xdeeeu /* Read */ /* Mach32 */ +#define EXT_SCISSOR_T 0xdeeeu /* Write */ +#define EXT_SCISSOR_R 0xe2eeu /* Write */ +#define EXT_SCISSOR_B 0xe6eeu /* Write */ +/* ? 0xeaeeu */ +#define DEST_COMP_FN 0xeeeeu /* Write */ +#define DEST_COLOR_CMP_MASK 0xf2eeu /* Write */ /* Mach32 */ +/* ? 0xf6eeu */ +#define CHIP_ID 0xfaeeu /* Read */ /* Mach32 */ +#define CHIP_CODE_0 0x001fu /* Mach32 */ +#define CHIP_CODE_1 0x03e0u /* Mach32 */ +#define CHIP_CLASS 0x0c00u /* Mach32 */ +#define CHIP_REV 0xf000u /* Mach32 */ +#define LINEDRAW 0xfeeeu /* Write */ + +/* ATI Mach64 register definitions */ +#define CRTC_H_TOTAL_DISP IOPortTag(0x00u, 0x00u) +#define CRTC_H_TOTAL 0x000001fful +/* ? 0x0000fe00ul */ +#define CRTC_H_DISP 0x01ff0000ul +/* ? 0xfe000000ul */ +#define CRTC_H_SYNC_STRT_WID IOPortTag(0x01u, 0x01u) +#define CRTC_H_SYNC_STRT 0x000000fful +#define CRTC_H_SYNC_DLY 0x00000700ul +/* ? 0x00000800ul */ +#define CRTC_H_SYNC_STRT_HI 0x00001000ul +/* ? 0x0000e000ul */ +#define CRTC_H_SYNC_WID 0x001f0000ul +#define CRTC_H_SYNC_POL 0x00200000ul +/* ? 0xffc00000ul */ +#define CRTC_V_TOTAL_DISP IOPortTag(0x02u, 0x02u) +#define CRTC_V_TOTAL 0x000007fful +/* ? 0x0000f800ul */ +#define CRTC_V_DISP 0x07ff0000ul +/* ? 0xf8000000ul */ +#define CRTC_V_SYNC_STRT_WID IOPortTag(0x03u, 0x03u) +#define CRTC_V_SYNC_STRT 0x000007fful +/* ? 0x0000f800ul */ +#define CRTC_V_SYNC_WID 0x001f0000ul +#define CRTC_V_SYNC_POL 0x00200000ul +/* ? 0xffc00000ul */ +#define CRTC_VLINE_CRNT_VLINE IOPortTag(0x04u, 0x04u) +#define CRTC_VLINE 0x000007fful +/* ? 0x0000f800ul */ +#define CRTC_CRNT_VLINE 0x07ff0000ul +/* ? 0xf8000000ul */ +#define CRTC_OFF_PITCH IOPortTag(0x05u, 0x05u) +#define CRTC_OFFSET 0x000ffffful +#define CRTC_OFFSET_VGA 0x0003fffful +#define CRTC_OFFSET_LOCK 0x00100000ul /* XC/XL */ +/* ? 0x00200000ul */ +#define CRTC_PITCH 0xffc00000ul +#define CRTC_INT_CNTL IOPortTag(0x06u, 0x06u) +#define CRTC_VBLANK 0x00000001ul +#define CRTC_VBLANK_INT_EN 0x00000002ul +#define CRTC_VBLANK_INT 0x00000004ul +#define CRTC_VLINE_INT_EN 0x00000008ul +#define CRTC_VLINE_INT 0x00000010ul +#define CRTC_VLINE_SYNC 0x00000020ul +#define CRTC_FRAME 0x00000040ul +#define CRTC_SNAPSHOT_INT_EN 0x00000080ul /* GTPro */ +#define CRTC_SNAPSHOT_INT 0x00000100ul /* GTPro */ +#define CRTC_I2C_INT_EN 0x00000200ul /* GTPro */ +#define CRTC_I2C_INT 0x00000400ul /* GTPro */ +#define CRTC2_VBLANK 0x00000800ul /* LTPro */ +#define CRTC2_VBLANK_INT_EN 0x00001000ul /* LTPro */ +#define CRTC2_VBLANK_INT 0x00002000ul /* LTPro */ +#define CRTC2_VLINE_INT_EN 0x00004000ul /* LTPro */ +#define CRTC2_VLINE_INT 0x00008000ul /* LTPro */ +#define CRTC_CAPBUF0_INT_EN 0x00010000ul /* VT/GT */ +#define CRTC_CAPBUF0_INT 0x00020000ul /* VT/GT */ +#define CRTC_CAPBUF1_INT_EN 0x00040000ul /* VT/GT */ +#define CRTC_CAPBUF1_INT 0x00080000ul /* VT/GT */ +#define CRTC_OVERLAY_EOF_INT_EN 0x00100000ul /* VT/GT */ +#define CRTC_OVERLAY_EOF_INT 0x00200000ul /* VT/GT */ +#define CRTC_ONESHOT_CAP_INT_EN 0x00400000ul /* VT/GT */ +#define CRTC_ONESHOT_CAP_INT 0x00800000ul /* VT/GT */ +#define CRTC_BUSMASTER_EOL_INT_EN 0x01000000ul /* VTB/GTB/LT */ +#define CRTC_BUSMASTER_EOL_INT 0x02000000ul /* VTB/GTB/LT */ +#define CRTC_GP_INT_EN 0x04000000ul /* VTB/GTB/LT */ +#define CRTC_GP_INT 0x08000000ul /* VTB/GTB/LT */ +#define CRTC2_VLINE_SYNC 0x10000000ul /* LTPro */ +#define CRTC_SNAPSHOT2_INT_EN 0x20000000ul /* LTPro */ +#define CRTC_SNAPSHOT2_INT 0x40000000ul /* LTPro */ +#define CRTC_VBLANK_BIT2_INT 0x80000000ul /* GTPro */ +#define CRTC_INT_ENS /* *** UPDATE ME *** */ \ + ( \ + CRTC_VBLANK_INT_EN | \ + CRTC_VLINE_INT_EN | \ + CRTC_SNAPSHOT_INT_EN | \ + CRTC_I2C_INT_EN | \ + CRTC2_VBLANK_INT_EN | \ + CRTC2_VLINE_INT_EN | \ + CRTC_CAPBUF0_INT_EN | \ + CRTC_CAPBUF1_INT_EN | \ + CRTC_OVERLAY_EOF_INT_EN | \ + CRTC_ONESHOT_CAP_INT_EN | \ + CRTC_BUSMASTER_EOL_INT_EN | \ + CRTC_GP_INT_EN | \ + CRTC_SNAPSHOT2_INT_EN | \ + 0 \ + ) +#define CRTC_INT_ACKS /* *** UPDATE ME *** */ \ + ( \ + CRTC_VBLANK_INT | \ + CRTC_VLINE_INT | \ + CRTC_SNAPSHOT_INT | \ + CRTC_I2C_INT | \ + CRTC2_VBLANK_INT | \ + CRTC2_VLINE_INT | \ + CRTC_CAPBUF0_INT | \ + CRTC_CAPBUF1_INT | \ + CRTC_OVERLAY_EOF_INT | \ + CRTC_ONESHOT_CAP_INT | \ + CRTC_BUSMASTER_EOL_INT | \ + CRTC_GP_INT | \ + CRTC_SNAPSHOT2_INT | \ + CRTC_VBLANK_BIT2_INT | \ + 0 \ + ) +#define CRTC_GEN_CNTL IOPortTag(0x07u, 0x07u) +#define CRTC_DBL_SCAN_EN 0x00000001ul +#define CRTC_INTERLACE_EN 0x00000002ul +#define CRTC_HSYNC_DIS 0x00000004ul +#define CRTC_VSYNC_DIS 0x00000008ul +#define CRTC_CSYNC_EN 0x00000010ul +#define CRTC_PIX_BY_2_EN 0x00000020ul +#define CRTC2_DBL_SCAN_EN 0x00000020ul /* LTPro */ +#define CRTC_DISPLAY_DIS 0x00000040ul +#define CRTC_VGA_XOVERSCAN 0x00000080ul +#define CRTC_PIX_WIDTH 0x00000700ul +#define CRTC_BYTE_PIX_ORDER 0x00000800ul +#define CRTC_VSYNC_INT_EN 0x00001000ul /* XC/XL */ +#define CRTC_VSYNC_INT 0x00002000ul /* XC/XL */ +#define CRTC_FIFO_OVERFILL 0x0000c000ul /* VT/GT */ +#define CRTC2_VSYNC_INT_EN 0x00004000ul /* XC/XL */ +#define CRTC2_VSYNC_INT 0x00008000ul /* XC/XL */ +#define CRTC_FIFO_LWM 0x000f0000ul +#define CRTC_HVSYNC_IO_DRIVE 0x00010000ul /* XC/XL */ +#define CRTC2_PIX_WIDTH 0x000e0000ul /* LTPro */ +#define CRTC_VGA_128KAP_PAGING 0x00100000ul /* VT/GT */ +#define CRTC_DISPREQ_ONLY 0x00200000ul /* VT/GT */ +#define CRTC_VFC_SYNC_TRISTATE 0x00200000ul /* VTB/GTB/LT */ +#define CRTC2_EN 0x00200000ul /* LTPro */ +#define CRTC_LOCK_REGS 0x00400000ul /* VT/GT */ +#define CRTC_SYNC_TRISTATE 0x00800000ul /* VT/GT */ +#define CRTC_EXT_DISP_EN 0x01000000ul +#define CRTC_EN 0x02000000ul +#define CRTC_DISP_REQ_EN 0x04000000ul +#define CRTC_VGA_LINEAR 0x08000000ul +#define CRTC_VSYNC_FALL_EDGE 0x10000000ul +#define CRTC_VGA_TEXT_132 0x20000000ul +#define CRTC_CNT_EN 0x40000000ul +#define CRTC_CUR_B_TEST 0x80000000ul +#define CRTC_INT_ENS_X /* *** UPDATE ME *** */ \ + ( \ + CRTC_VSYNC_INT_EN | \ + CRTC2_VSYNC_INT_EN | \ + 0 \ + ) +#define CRTC_INT_ACKS_X /* *** UPDATE ME *** */ \ + ( \ + CRTC_VSYNC_INT | \ + CRTC2_VSYNC_INT | \ + 0 \ + ) +#define DSP_CONFIG BlockIOTag(0x08u) /* VTB/GTB/LT */ +#define DSP_XCLKS_PER_QW 0x00003ffful +/* ? 0x00004000ul */ +#define DSP_FLUSH_WB 0x00008000ul +#define DSP_LOOP_LATENCY 0x000f0000ul +#define DSP_PRECISION 0x00700000ul +/* ? 0xff800000ul */ +#define DSP_ON_OFF BlockIOTag(0x09u) /* VTB/GTB/LT */ +#define DSP_OFF 0x000007fful +/* ? 0x0000f800ul */ +#define DSP_ON 0x07ff0000ul +/* ? 0xf8000000ul */ +#define TIMER_CONFIG BlockIOTag(0x0au) /* VTB/GTB/LT */ +#define MEM_BUF_CNTL BlockIOTag(0x0bu) /* VTB/GTB/LT */ +#define SHARED_CNTL BlockIOTag(0x0cu) /* VTB/GTB/LT */ +#define SHARED_MEM_CONFIG BlockIOTag(0x0du) /* VTB/GTB/LT */ +#define MEM_ADDR_CONFIG BlockIOTag(0x0du) /* GTPro */ +#define SHARED_CNTL_CTD BlockIOTag(0x0eu) /* CTD */ +/* ? 0x00fffffful */ +#define CTD_FIFO5 0x01000000ul +/* ? 0xfe000000ul */ +#define CRT_TRAP BlockIOTag(0x0eu) /* VTB/GTB/LT */ +#define DSTN_CONTROL BlockIOTag(0x0fu) /* LT */ +#define I2C_CNTL_0 BlockIOTag(0x0fu) /* GTPro */ +#define OVR_CLR IOPortTag(0x08u, 0x10u) +#define OVR_CLR_8 0x000000fful +#define OVR_CLR_B 0x0000ff00ul +#define OVR_CLR_G 0x00ff0000ul +#define OVR_CLR_R 0xff000000ul +#define OVR_WID_LEFT_RIGHT IOPortTag(0x09u, 0x11u) +#define OVR_WID_LEFT 0x0000003ful /* 0x0f on <LT */ +/* ? 0x0000ffc0ul */ +#define OVR_WID_RIGHT 0x003f0000ul /* 0x0f0000 on <LT */ +/* ? 0xffc00000ul */ +#define OVR_WID_TOP_BOTTOM IOPortTag(0x0au, 0x12u) +#define OVR_WID_TOP 0x000001fful /* 0x00ff on <LT */ +/* ? 0x0000fe00ul */ +#define OVR_WID_BOTTOM 0x01ff0000ul /* 0x00ff0000 on <LT */ +/* ? 0xfe000000ul */ +#define VGA_DSP_CONFIG BlockIOTag(0x13u) /* VTB/GTB/LT */ +#define VGA_DSP_XCLKS_PER_QW DSP_XCLKS_PER_QW +/* ? 0x000fc000ul */ +#define VGA_DSP_PREC_PCLKBY2 0x00700000ul +/* ? 0x00800000ul */ +#define VGA_DSP_PREC_PCLK 0x07000000ul +/* ? 0xf8000000ul */ +#define VGA_DSP_ON_OFF BlockIOTag(0x14u) /* VTB/GTB/LT */ +#define VGA_DSP_OFF DSP_OFF +/* ? 0x0000f800ul */ +#define VGA_DSP_ON DSP_ON +/* ? 0xf8000000ul */ +#define DSP2_CONFIG BlockIOTag(0x15u) /* LTPro */ +#define DSP2_ON_OFF BlockIOTag(0x16u) /* LTPro */ +#define EXT_CRTC_GEN_CNTL BlockIOTag(0x17u) /* VT-A4 (W) */ +#define CRTC2_OFF_PITCH BlockIOTag(0x17u) /* LTPro */ +#define CUR_CLR0 IOPortTag(0x0bu, 0x18u) +#define CUR_CLR1 IOPortTag(0x0cu, 0x19u) +/* These are for both CUR_CLR0 and CUR_CLR1 */ +#define CUR_CLR_I 0x000000fful +#define CUR_CLR_B 0x0000ff00ul +#define CUR_CLR_G 0x00ff0000ul +#define CUR_CLR_R 0xff000000ul +#define CUR_CLR (CUR_CLR_R | CUR_CLR_G | CUR_CLR_B) +#define CUR_OFFSET IOPortTag(0x0du, 0x1au) +#define CUR_HORZ_VERT_POSN IOPortTag(0x0eu, 0x1bu) +#define CUR_HORZ_POSN 0x000007fful +/* ? 0x0000f800ul */ +#define CUR_VERT_POSN 0x07ff0000ul +/* ? 0xf8000000ul */ +#define CUR_HORZ_VERT_OFF IOPortTag(0x0fu, 0x1cu) +#define CUR_HORZ_OFF 0x0000007ful +/* ? 0x0000ff80ul */ +#define CUR_VERT_OFF 0x007f0000ul +/* ? 0xff800000ul */ +#define CONFIG_PANEL BlockIOTag(0x1du) /* LT */ +#define PANEL_FORMAT 0x00000007ul +/* ? 0x00000008ul */ +#define PANEL_TYPE 0x000000f0ul +#define NO_OF_GREY 0x00000700ul +#define MOD_GEN 0x00001800ul +#define EXT_LVDS_CLK 0x00001800ul /* LTPro */ +#define BLINK_RATE 0x00006000ul +#define BLINK_RATE_PRO 0x00002000ul /* LTPro */ +#define DONT_SHADOW_HEND 0x00004000ul /* LTPro */ +#define DONT_USE_F32KHZ 0x00008000ul +#define LCD_IO_DRIVE 0x00008000ul /* XC/XL */ +#define FP_POL 0x00010000ul +#define LP_POL 0x00020000ul +#define DTMG_POL 0x00040000ul +#define SCK_POL 0x00080000ul +#define DITHER_SEL 0x00300000ul +#define INVERSE_VIDEO_EN 0x00400000ul +#define BL_CLK_SEL 0x01800000ul +#define BL_LEVEL 0x0e000000ul +#define BL_CLK_SEL_PRO 0x00800000ul /* LTPro */ +#define BL_LEVEL_PRO 0x03000000ul /* LTPro */ +#define BIAS_LEVEL_PRO 0x0c000000ul /* LTPro */ +#define HSYNC_DELAY 0xf0000000ul +#define TV_OUT_INDEX BlockIOTag(0x1du) /* LTPro */ +#define TV_REG_INDEX 0x000000fful +#define TV_ON 0x00000100ul +/* ? 0xfffffe00ul */ +#define GP_IO IOPortTag(0x1eu, 0x1eu) /* VT/GT */ +#define GP_IO_CNTL BlockIOTag(0x1fu) /* VT/GT */ +#define HW_DEBUG BlockIOTag(0x1fu) /* VTB/GTB/LT */ +#define FAST_SRCCOPY_DIS 0x00000001ul +#define BYPASS_SUBPIC_DBF 0x00000001ul /* XL/XC */ +#define SRC_AUTONA_FIX_DIS 0x00000002ul +#define SYNC_PD_EN 0x00000002ul /* Mobility */ +#define DISP_QW_FIX_DIS 0x00000004ul +#define GUIDST_WB_EXP_DIS 0x00000008ul +#define CYC_ALL_FIX_DIS 0x00000008ul /* GTPro */ +#define AGPPLL_FIX_EN 0x00000008ul /* Mobility */ +#define SRC_AUTONA_ALWAYS_EN 0x00000010ul +#define GUI_BEATS_HOST_P 0x00000010ul /* GTPro */ +#define DRV_CNTL_DQMB_WEB 0x00000020ul +#define FAST_FILL_SCISSOR_DIS 0x00000020ul /* GT2c/VT4 */ +#define INTER_BLIT_FIX_DIS 0x00000020ul /* GTPro */ +#define DRV_CNTL_MA 0x00000040ul +#define AUTO_BLKWRT_COLOR_DIS 0x00000040ul /* GT2c/VT4 */ +#define INTER_PRIM_DIS 0x00000040ul /* GTPro */ +#define DRV_CNTL_MD 0x00000080ul +#define CHG_DEV_ID 0x00000100ul +#define SRC_TRACK_DST_FIX_DIS 0x00000200ul +#define HCLK_FB_SKEW 0x00000380ul /* GT2c/VT4 */ +#define SRC_TRACK_DST_FIX_DIS_P 0x00000080ul /* GTPro */ +#define AUTO_BLKWRT_COLOR_DIS_P 0x00000100ul /* GTPro */ +#define INTER_LINE_OVERLAP_DIS 0x00000200ul /* GTPro */ +#define MEM_OE_PULLBACK 0x00000400ul +#define DBL_BUFFER_EN 0x00000400ul /* GTPro */ +#define MEM_WE_FIX_DIS 0x00000800ul +#define MEM_OE_PULLBACK_B 0x00000800ul /* GT2c/VT4 */ +#define CMDFIFO_SIZE_DIS_P 0x00000800ul /* GTPro */ +#define RD_EN_FIX_DIS 0x00001000ul +#define MEM_WE_FIX_DIS_B 0x00001000ul +#define AUTO_FF_DIS 0x00001000ul /* GTPro */ +#define CMDFIFO_SIZE_DIS 0x00002000ul /* GT2c/VT4 */ +#define AUTO_BLKWRT_DIS 0x00002000ul /* GTPro */ +#define GUI_BEATS_HOST 0x00004000ul /* GT2c/VT4 */ +#define ORED_INVLD_RB_CACHE 0x00004000ul /* GTPro */ +#define BLOCK_DBL_BUF 0x00008000ul /* GTPro */ +#define R2W_TURNAROUND_DELAY 0x00020000ul /* GT2c/VT4 */ +#define ENA_32BIT_DATA_BUS 0x00040000ul /* GT2c/VT4 */ +#define HCLK_FB_SKEW_P 0x00070000ul /* GTPro */ +#define ENA_FLASH_ROM 0x00080000ul /* GT2c/VT4 */ +#define DISABLE_SWITCH_FIX 0x00080000ul /* GTPro */ +#define MCLK_START_EN 0x00080000ul /* LTPro */ +#define SEL_VBLANK_BDL_BUF 0x00100000ul /* GTPro */ +#define CMDFIFO_64EN 0x00200000ul /* GTPro */ +#define BM_FIX_DIS 0x00400000ul /* GTPro */ +#define Z_SWITCH_EN 0x00800000ul /* LTPro */ +#define FLUSH_HOST_WB 0x01000000ul /* GTPro */ +#define HW_DEBUG_WRITE_MSK_FIX_DIS 0x02000000ul /* LTPro */ +#define Z_NO_WRITE_EN 0x04000000ul /* LTPro */ +#define DISABLE_PCLK_RESET_P 0x08000000ul /* LTPro */ +#define PM_D3_SUPPORT_ENABLE_P 0x10000000ul /* LTPro */ +#define STARTCYCLE_FIX_ENABLE 0x20000000ul /* LTPro */ +#define DONT_RST_CHAREN 0x20000000ul /* XL/XC */ +#define C3_FIX_ENABLE 0x40000000ul /* LTPro */ +#define BM_HOSTRA_EN 0x40000000ul /* XL/XC */ +#define PKGBGAb 0x80000000ul /* XL/XC */ +#define AUTOEXP_HORZ_FIX 0x80000000ul /* Mobility */ +#define SCRATCH_REG0 IOPortTag(0x10u, 0x20u) +#define SCRATCH_REG1 IOPortTag(0x11u, 0x21u) +/* BIOS_BASE_SEGMENT 0x0000007ful */ /* As above */ +/* ? 0x00000f80ul */ +#define BIOS_INIT_DAC_SUBTYPE 0x0000f000ul +/* ? 0xffff0000ul */ +#define SCRATCH_REG2 BlockIOTag(0x22u) /* LT */ +#define SCRATCH_REG3 BlockIOTag(0x23u) /* GTPro */ +#define CLOCK_CNTL IOPortTag(0x12u, 0x24u) +#define CLOCK_BIT 0x00000004ul /* For ICS2595 */ +#define CLOCK_PULSE 0x00000008ul /* For ICS2595 */ +#define CLOCK_SELECT 0x0000000ful +#define CLOCK_DIVIDER 0x00000030ul +#define CLOCK_STROBE 0x00000040ul +#define CLOCK_DATA 0x00000080ul +/* ? 0x00000100ul */ +#define PLL_WR_EN 0x00000200ul /* For internal PLL */ +#define PLL_ADDR 0x0000fc00ul /* For internal PLL */ +#define PLL_DATA 0x00ff0000ul /* For internal PLL */ +/* ? 0xff000000ul */ +#define CONFIG_STAT64_1 BlockIOTag(0x25u) /* GTPro */ +#define CFG_SUBSYS_DEV_ID 0x000000fful +#define CFG_SUBSYS_VEN_ID 0x00ffff00ul +/* ? 0x1f000000ul */ +#define CFG_DIMM_TYPE 0xe0000000ul +#define CFG_PCI_SUBSYS_DEV_ID 0x0000fffful /* XC/XL */ +#define CFG_PCI_SUBSYS_VEN_ID 0xffff0000ul /* XC/XL */ +#define CONFIG_STAT64_2 BlockIOTag(0x26u) /* GTPro */ +#define CFG_DIMM_TYPE_3 0x00000001ul +/* ? 0x0000001eul */ +#define CFG_ROMWRTEN 0x00000020ul +#define CFG_AGPVCOGAIN 0x000000c0ul +#define CFG_PCI_TYPE 0x00000100ul +#define CFG_AGPSKEW 0x00000e00ul +#define CFG_X1CLKSKEW 0x00007000ul +#define CFG_PANEL_ID_P 0x000f8000ul /* LTPro */ +/* ? 0x00100000ul */ +#define CFG_PREFETCH_EN 0x00200000ul +#define CFG_ID_DISABLE 0x00400000ul +#define CFG_PRE_TESTEN 0x00800000ul +/* ? 0x01000000ul */ +#define CFG_PCI5VEN 0x02000000ul /* LTPro */ +#define CFG_VGA_DISABLE 0x04000000ul +#define CFG_ENINTB 0x08000000ul +/* ? 0x10000000ul */ +#define CFG_ROM_REMAP_2 0x20000000ul +#define CFG_IDSEL 0x40000000ul +/* ? 0x80000000ul */ +#define TV_OUT_DATA BlockIOTag(0x27u) /* LTPro */ +#define BUS_CNTL IOPortTag(0x13u, 0x28u) +# define BUS_WS 0x0000000ful +# define BUS_DBL_RESYNC 0x00000001ul /* VTB/GTB/LT */ +# define BUS_MSTR_RESET 0x00000002ul /* VTB/GTB/LT */ +# define BUS_FLUSH_BUF 0x00000004ul /* VTB/GTB/LT */ +# define BUS_STOP_REQ_DIS 0x00000008ul /* VTB/GTB/LT */ +# define BUS_ROM_WS 0x000000f0ul +# define BUS_APER_REG_DIS 0x00000010ul /* VTB/GTB/LT */ +# define BUS_EXTRA_PIPE_DIS 0x00000020ul /* VTB/GTB/LT */ +# define BUS_MASTER_DIS 0x00000040ul /* VTB/GTB/LT */ +# define BUS_ROM_WRT_EN 0x00000080ul /* GTPro */ +# define BUS_ROM_PAGE 0x00000f00ul +# define BUS_MINOR_REV_ID 0x00000700ul /* LTPro */ +# define BUS_EXT_REG_EN 0x08000000ul +/* First silicom - Prototype (A11) 0x00000000ul */ +/* Metal mask spin (A12 & A13) 0x00000100ul */ +/* All layer spin (A21) 0x00000200ul */ +/* Fast metal spin (A22) - Prod. 0x00000300ul */ +/* All layer spin (A31) 0x00000700ul */ +/* ? 0x00000800ul */ /* LTPro */ +#define BUS_CHIP_HIDDEN_REV 0x00000300ul /* XC/XL */ +/* ? 0x00001c00ul */ /* XC/XL */ +#define BUS_ROM_DIS 0x00001000ul +#define BUS_IO_16_EN 0x00002000ul /* GX */ +#define BUS_PCI_READ_RETRY_EN 0x00002000ul /* VTB/GTB/LT */ +#define BUS_DAC_SNOOP_EN 0x00004000ul +#define BUS_PCI_RETRY_EN 0x00008000ul /* VT/GT */ +#define BUS_PCI_WRT_RETRY_EN 0x00008000ul /* VTB/GTB/LT */ +#define BUS_FIFO_WS 0x000f0000ul +#define BUS_RETRY_WS 0x000f0000ul /* VTB/GTB/LT */ +#define BUS_FIFO_ERR_INT_EN 0x00100000ul +#define BUS_MSTR_RD_MULT 0x00100000ul /* VTB/GTB/LT */ +#define BUS_FIFO_ERR_INT 0x00200000ul +#define BUS_MSTR_RD_LINE 0x00200000ul /* VTB/GTB/LT */ +#define BUS_HOST_ERR_INT_EN 0x00400000ul +#define BUS_SUSPEND 0x00400000ul /* GTPro */ +#define BUS_HOST_ERR_INT 0x00800000ul +#define BUS_LAT16X 0x00800000ul /* GTPro */ +#define BUS_PCI_DAC_WS 0x07000000ul +#define BUS_RD_DISCARD_EN 0x01000000ul /* VTB/GTB/LT */ +#define BUS_RD_ABORT_EN 0x02000000ul /* VTB/GTB/LT */ +#define BUS_MSTR_WS 0x04000000ul /* VTB/GTB/LT */ +#define BUS_PCI_DAC_DLY 0x08000000ul +#define BUS_EXT_REG_EN 0x08000000ul /* VT/GT */ +#define BUS_PCI_MEMW_WS 0x10000000ul +#define BUS_MSTR_DISCONNECT_EN 0x10000000ul /* VTB/GTB/LT */ +#define BUS_PCI_BURST_DEC 0x20000000ul /* GX/CX */ +#define BUS_BURST 0x20000000ul /* 264xT */ +#define BUS_WRT_BURST 0x20000000ul /* VTB/GTB/LT */ +#define BUS_RDY_READ_DLY 0xc0000000ul +#define BUS_READ_BURST 0x40000000ul /* VTB/GTB/LT */ +#define BUS_RDY_READ_DLY_B 0x80000000ul /* VTB/GTB/LT */ +#define LCD_INDEX BlockIOTag(0x29u) /* LTPro */ +#define LCD_REG_INDEX 0x0000003ful +/* ? 0x000000c0ul */ +#define LCD_DISPLAY_DIS 0x00000100ul +#define LCD_SRC_SEL 0x00000200ul +#define LCD_SRC_SEL_CRTC1 0x00000000ul +#define LCD_SRC_SEL_CRTC2 0x00000200ul +#define LCD_CRTC2_DISPLAY_DIS 0x00000400ul +#define LCD_GUI_ACTIVE 0x00000800ul /* XC/XL */ +/* ? 0x00fff000ul */ +#define LCD_MONDET_SENSE 0x01000000ul /* XC/XL */ +#define LCD_MONDET_INT_POL 0x02000000ul /* XC/XL */ +#define LCD_MONDET_INT_EN 0x04000000ul /* XC/XL */ +#define LCD_MONDET_INT 0x08000000ul /* XC/XL */ +#define LCD_MONDET_EN 0x10000000ul /* XC/XL */ +#define LCD_EN_PL 0x20000000ul /* XC/XL */ +/* ? 0xc0000000ul */ +#define HFB_PITCH_ADDR BlockIOTag(0x2au) /* LT */ +#define LCD_DATA BlockIOTag(0x2au) /* LTPro */ +#define EXT_MEM_CNTL BlockIOTag(0x2bu) /* VTB/GTB/LT */ +#define MEM_CNTL IOPortTag(0x14u, 0x2cu) +#define CTL_MEM_SIZE 0x00000007ul +/* ? 0x00000008ul */ +#define CTL_MEM_REFRESH 0x00000078ul /* VT/GT */ +#define CTL_MEM_SIZEB 0x0000000ful /* VTB/GTB/LT */ +#define CTL_MEM_RD_LATCH_EN 0x00000010ul +#define CTL_MEM_RD_LATCH_DLY 0x00000020ul +#define CTL_MEM_LATENCY 0x00000030ul /* VTB/GTB/LT */ +#define CTL_MEM_SD_LATCH_EN 0x00000040ul +#define CTL_MEM_SD_LATCH_DLY 0x00000080ul +#define CTL_MEM_LATCH 0x000000c0ul /* VTB/GTB/LT */ +#define CTL_MEM_WDOE_CNTL 0x000000c0ul /* XC/XL */ +#define CTL_MEM_FULL_PLS 0x00000100ul +#define CTL_MEM_CYC_LNTH_AUX 0x00000180ul /* VT/GT */ +#define CTL_MEM_TRP 0x00000300ul /* VTB/GTB/LT */ +#define CTL_MEM_CYC_LNTH 0x00000600ul +#define CTL_MEM_REFRESH_RATE 0x00001800ul /* 264xT */ +#define CTL_MEM_TRCD 0x00000c00ul /* VTB/GTB/LT */ +#define CTL_MEM_WR_RDY_SEL 0x00000800ul /* GX/CX */ +#define CTL_MEM_EXT_RMW_CYC_EN 0x00001000ul /* GX/CX */ +#define CTL_MEM_TCRD 0x00001000ul /* VTB/GTB/LT */ +#define CTL_MEM_DLL_RESET 0x00002000ul /* VT/GT */ +#define CTL_MEM_TR2W 0x00002000ul /* GTPro */ +#define CTL_MEM_ACTV_PRE 0x0000c000ul /* VT/GT */ +#define CTL_MEM_CAS_PHASE 0x00004000ul /* GTPro */ +#define CTL_MEM_OE_PULLBACK 0x00008000ul /* GTPro */ +#define CTL_MEM_TWR 0x0000c000ul /* XC/XL */ +#define CTL_MEM_BNDRY 0x00030000ul +#define CTL_MEM_BNDRY_0K 0x00000000ul +#define CTL_MEM_BNDRY_256K 0x00010000ul +#define CTL_MEM_BNDRY_512K 0x00020000ul +#define CTL_MEM_BNDRY_1024K 0x00030000ul +#define CTL_MEM_DLL_GAIN_CNTL 0x00030000ul /* VT/GT */ +#define CTL_MEM_BNDRY_EN 0x00040000ul +#define CTL_MEM_SDRAM_RESET 0x00040000ul /* VT/GT */ +#define CTL_MEM_TRAS 0x00070000ul /* VTB/GTB/LT */ +#define CTL_MEM_TILE_SELECT 0x00180000ul /* VT/GT */ +#define CTL_MEM_REFRESH_DIS 0x00080000ul /* VTB/GTB/LT */ +#define CTL_MEM_LOW_LATENCY_MODE 0x00200000ul /* VT/GT */ +#define CTL_MEM_CDE_PULLBACK 0x00400000ul /* VT/GT */ +#define CTL_MEM_REFRESH_RATE_B 0x00f00000ul /* VTB/GTB/LT */ +#define CTL_MEM_PIX_WIDTH 0x07000000ul +#define CTL_MEM_LOWER_APER_ENDIAN 0x03000000ul /* VTB/GTB/LT */ +#define CTL_MEM_OE_SELECT 0x18000000ul /* VT/GT */ +#define CTL_MEM_UPPER_APER_ENDIAN 0x0c000000ul /* VTB/GTB/LT */ +/* ? 0xe0000000ul */ +#define CTL_MEM_PAGE_SIZE 0x30000000ul /* VTB/GTB/LT */ +#define MEM_VGA_WP_SEL IOPortTag(0x15u, 0x2du) +#define MEM_VGA_WPS0 0x0000fffful +#define MEM_VGA_WPS1 0xffff0000ul +#define MEM_VGA_RP_SEL IOPortTag(0x16u, 0x2eu) +#define MEM_VGA_RPS0 0x0000fffful +#define MEM_VGA_RPS1 0xffff0000ul +#define LT_GIO BlockIOTag(0x2fu) /* LT */ +#define I2C_CNTL_1 BlockIOTag(0x2fu) /* GTPro */ +#define DAC_REGS IOPortTag(0x17u, 0x30u) /* 4 separate bytes */ +#define M64_DAC_WRITE (DAC_REGS + 0) +#define M64_DAC_DATA (DAC_REGS + 1) +#define M64_DAC_MASK (DAC_REGS + 2) +#define M64_DAC_READ (DAC_REGS + 3) +#define DAC_CNTL IOPortTag(0x18u, 0x31u) +#define DAC_EXT_SEL 0x00000003ul +#define DAC_EXT_SEL_RS2 0x000000001ul +#define DAC_EXT_SEL_RS3 0x000000002ul +#define DAC_RANGE_CTL 0x00000003ul /* VTB/GTB/LT */ +#define DAC_BLANKING 0x00000004ul /* 264xT */ +#define DAC_CMP_DIS 0x00000008ul /* 264xT */ +#define DAC1_CLK_SEL 0x00000010ul /* LTPro */ +#define DAC_PALETTE_ACCESS_CNTL 0x00000020ul /* LTPro */ +#define DAC_PALETTE2_SNOOP_EN 0x00000040ul /* LTPro */ +#define DAC_CMP_OUTPUT 0x00000080ul /* 264xT */ +#define DAC_8BIT_EN 0x00000100ul +#define DAC_PIX_DLY 0x00000600ul +#define DAC_DIRECT 0x00000400ul /* VTB/GTB/LT */ +#define DAC_BLANK_ADJ 0x00001800ul +#define DAC_PAL_CLK_SEL 0x00000800ul /* VTB/GTB/LT */ +#define DAC_CRT_SENSE 0x00000800ul /* XC/XL */ +#define DAC_CRT_DETECTION_ON 0x00001000ul /* XC/XL */ +#define DAC_VGA_ADR_EN 0x00002000ul +#define DAC_FEA_CON_EN 0x00004000ul /* 264xT */ +#define DAC_PDMN 0x00008000ul /* 264xT */ +#define DAC_TYPE 0x00070000ul +/* ? 0x00f80000ul */ +#define DAC_MON_ID_STATE0 0x01000000ul /* GX-E+/CX */ +#define DAC_GIO_STATE_1 0x01000000ul /* 264xT */ +#define DAC_MON_ID_STATE1 0x02000000ul /* GX-E+/CX */ +#define DAC_GIO_STATE_0 0x02000000ul /* 264xT */ +#define DAC_MON_ID_STATE2 0x04000000ul /* GX-E+/CX */ +#define DAC_GIO_STATE_4 0x04000000ul /* 264xT */ +#define DAC_MON_ID_DIR0 0x08000000ul /* GX-E+/CX */ +#define DAC_GIO_DIR_1 0x08000000ul /* 264xT */ +#define DAC_MON_ID_DIR1 0x10000000ul /* GX-E+/CX */ +#define DAC_GIO_DIR_0 0x10000000ul /* 264xT */ +#define DAC_MON_ID_DIR2 0x20000000ul /* GX-E+/CX */ +#define DAC_GIO_DIR_4 0x20000000ul /* 264xT */ +#define DAC_MAN_CMP_STATE 0x40000000ul /* GX-E+ */ +#define DAC_RW_WS 0x80000000ul /* VT/GT */ +#define HORZ_STRETCHING BlockIOTag(0x32u) /* LT */ +#define HORZ_STRETCH_BLEND 0x00000ffful +#define HORZ_STRETCH_RATIO 0x0000fffful +#define HORZ_STRETCH_LOOP 0x00070000ul +#define HORZ_STRETCH_LOOP09 0x00000000ul +#define HORZ_STRETCH_LOOP11 0x00010000ul +#define HORZ_STRETCH_LOOP12 0x00020000ul +#define HORZ_STRETCH_LOOP14 0x00030000ul +#define HORZ_STRETCH_LOOP15 0x00040000ul +/* ? 0x00050000ul */ +/* ? 0x00060000ul */ +/* ? 0x00070000ul */ +/* ? 0x00080000ul */ +#define HORZ_PANEL_SIZE 0x0ff00000ul /* XC/XL */ +/* ? 0x10000000ul */ +#define AUTO_HORZ_RATIO 0x20000000ul /* XC/XL */ +#define HORZ_STRETCH_MODE 0x40000000ul +#define HORZ_STRETCH_EN 0x80000000ul +#define EXT_DAC_REGS BlockIOTag(0x32u) /* GTPro */ +#define VERT_STRETCHING BlockIOTag(0x33u) /* LT */ +#define VERT_STRETCH_RATIO0 0x000003fful +#define VERT_STRETCH_RATIO1 0x000ffc00ul +#define VERT_STRETCH_RATIO2 0x3ff00000ul +#define VERT_STRETCH_USE0 0x40000000ul +#define VERT_STRETCH_EN 0x80000000ul +#define GEN_TEST_CNTL IOPortTag(0x19u, 0x34u) +#define GEN_EE_DATA_OUT 0x00000001ul /* GX/CX */ +#define GEN_GIO2_DATA_OUT 0x00000001ul /* 264xT */ +#define GEN_EE_CLOCK 0x00000002ul /* GX/CX */ +/* ? 0x00000002ul */ /* 264xT */ +#define GEN_EE_CHIP_SEL 0x00000004ul /* GX/CX */ +#define GEN_GIO3_DATA_OUT 0x00000004ul /* 264xT */ +#define GEN_EE_DATA_IN 0x00000008ul /* GX/CX */ +#define GEN_GIO2_DATA_IN 0x00000008ul /* 264xT */ +#define GEN_EE_EN 0x00000010ul /* GX/CX */ +#define GEN_GIO2_ENABLE 0x00000010ul /* 264xT */ +#define GEN_ICON2_ENABLE 0x00000010ul /* XC/XL */ +#define GEN_OVR_OUTPUT_EN 0x00000020ul /* GX/CX */ +#define GEN_GIO2_WRITE 0x00000020ul /* 264xT */ +#define GEN_CUR2_ENABLE 0x00000020ul /* XC/XL */ +#define GEN_OVR_POLARITY 0x00000040ul /* GX/CX */ +#define GEN_ICON_ENABLE 0x00000040ul /* XC/XL */ +#define GEN_CUR_EN 0x00000080ul +#define GEN_GUI_EN 0x00000100ul /* GX/CX */ +#define GEN_GUI_RESETB 0x00000100ul /* 264xT */ +#define GEN_BLOCK_WR_EN 0x00000200ul /* GX */ +/* ? 0x00000200ul */ /* CX/264xT */ +#define GEN_SOFT_RESET 0x00000200ul /* VTB/GTB/LT */ +#define GEN_MEM_TRISTATE 0x00000400ul /* GTPro */ +/* ? 0x00000800ul */ +#define GEN_TEST_VECT_MODE 0x00003000ul /* VT/GT */ +/* ? 0x0000c000ul */ +#define GEN_TEST_FIFO_EN 0x00010000ul /* GX/CX */ +#define GEN_TEST_GUI_REGS_EN 0x00020000ul /* GX/CX */ +#define GEN_TEST_VECT_EN 0x00040000ul /* GX/CX */ +#define GEN_TEST_CRC_STR 0x00080000ul /* GX-C/-D */ +/* ? 0x00080000ul */ /* GX-E+/CX */ +#define GEN_TEST_MODE_T 0x000f0000ul /* 264xT */ +#define GEN_TEST_MODE 0x00700000ul /* GX/CX */ +#define GEN_TEST_CNT_EN 0x00100000ul /* 264xT */ +#define GEN_TEST_CRC_EN 0x00200000ul /* 264xT */ +/* ? 0x00400000ul */ /* 264xT */ +/* ? 0x00800000ul */ +#define GEN_TEST_MEM_WR 0x01000000ul /* GX-C/-D */ +#define GEN_TEST_MEM_STROBE 0x02000000ul /* GX-C/-D */ +#define GEN_TEST_DST_SS_EN 0x04000000ul /* GX/CX */ +#define GEN_TEST_DST_SS_STROBE 0x08000000ul /* GX/CX */ +#define GEN_TEST_SRC_SS_EN 0x10000000ul /* GX/CX */ +#define GEN_TEST_SRC_SS_STROBE 0x20000000ul /* GX/CX */ +#define GEN_TEST_CNT_VALUE 0x3f000000ul /* 264xT */ +#define GEN_TEST_CC_EN 0x40000000ul /* GX/CX */ +#define GEN_TEST_CC_STROBE 0x80000000ul /* GX/CX */ +/* ? 0xc0000000ul */ /* 264xT */ +#define GEN_DEBUG_MODE 0xff000000ul /* VTB/GTB/LT */ +#define LCD_GEN_CTRL BlockIOTag(0x35u) /* LT */ +#define CRT_ON 0x00000001ul +#define LCD_ON 0x00000002ul +#define HORZ_DIVBY2_EN 0x00000004ul +#define DONT_DS_ICON 0x00000008ul +#define LOCK_8DOT 0x00000010ul +#define ICON_ENABLE 0x00000020ul +#define DONT_SHADOW_VPAR 0x00000040ul +#define V2CLK_PM_EN 0x00000080ul +#define RST_FM 0x00000100ul +#define DISABLE_PCLK_RESET 0x00000200ul /* XC/XL */ +#define DIS_HOR_CRT_DIVBY2 0x00000400ul +#define SCLK_SEL 0x00000800ul +#define SCLK_DELAY 0x0000f000ul +#define TVCLK_PM_EN 0x00010000ul +#define VCLK_DAC_PM_EN 0x00020000ul +#define VCLK_LCD_OFF 0x00040000ul +#define SELECT_WAIT_4MS 0x00080000ul +#define XTALIN_PM_EN 0x00080000ul /* XC/XL */ +#define V2CLK_DAC_PM_EN 0x00100000ul +#define LVDS_EN 0x00200000ul +#define LVDS_PLL_EN 0x00400000ul +#define LVDS_PLL_RESET 0x00800000ul +#define LVDS_RESERVED_BITS 0x07000000ul +#define CRTC_RW_SELECT 0x08000000ul /* LTPro */ +#define USE_SHADOWED_VEND 0x10000000ul +#define USE_SHADOWED_ROWCUR 0x20000000ul +#define SHADOW_EN 0x40000000ul +#define SHADOW_RW_EN 0x80000000ul +#define CUSTOM_MACRO_CNTL BlockIOTag(0x35u) /* GTPro */ +#define POWER_MANAGEMENT BlockIOTag(0x36u) /* LT */ +#define PWR_MGT_ON 0x00000001ul +#define PWR_MGT_MODE 0x00000006ul +#define AUTO_PWRUP_EN 0x00000008ul +#define ACTIVITY_PIN_ON 0x00000010ul +#define STANDBY_POL 0x00000020ul +#define SUSPEND_POL 0x00000040ul +#define SELF_REFRESH 0x00000080ul +#define ACTIVITY_PIN_EN 0x00000100ul +#define KEYBD_SNOOP 0x00000200ul +#define USE_F32KHZ 0x00000400ul /* LTPro */ +#define DONT_USE_XTALIN 0x00000400ul /* XC/XL */ +#define TRISTATE_MEM_EN 0x00000800ul /* LTPro */ +#define LCDENG_TEST_MODE 0x0000f000ul +#define STANDBY_COUNT 0x000f0000ul +#define SUSPEND_COUNT 0x00f00000ul +#define BAISON 0x01000000ul +#define BLON 0x02000000ul +#define DIGON 0x04000000ul +#define PM_D3_SUPPORT_ENABLE 0x08000000ul /* XC/XL */ +#define STANDBY_NOW 0x10000000ul +#define SUSPEND_NOW 0x20000000ul +#define PWR_MGT_STATUS 0xc0000000ul +#define CONFIG_CNTL IOPortTag(0x1au, 0x37u) +#define CFG_MEM_AP_SIZE 0x00000003ul +#define CFG_MEM_VGA_AP_EN 0x00000004ul +/* ? 0x00000008ul */ +#define CFG_MEM_AP_LOC 0x00003ff0ul +/* ? 0x0000c000ul */ +#define CFG_CARD_ID 0x00070000ul +#define CFG_VGA_DIS 0x00080000ul +/* ? 0x00f00000ul */ +#define CFG_CDE_WINDOW 0x3f000000ul /* VT/GT */ +/* ? 0xc0000000ul */ +#define CONFIG_CHIP_ID IOPortTag(0x1bu, 0x38u) /* Read */ +#define CFG_CHIP_TYPE0 0x000000fful +#define CFG_CHIP_TYPE1 0x0000ff00ul +#define CFG_CHIP_TYPE 0x0000fffful +#define CFG_CHIP_CLASS 0x00ff0000ul +#define CFG_CHIP_REV 0xff000000ul +#define CFG_CHIP_VERSION 0x07000000ul /* 264xT */ +#define CFG_CHIP_FOUNDRY 0x38000000ul /* 264xT */ +#define CFG_CHIP_REVISION 0xc0000000ul /* 264xT */ +#define CONFIG_STATUS64_0 IOPortTag(0x1cu, 0x39u) /* Read (R/W (264xT)) */ +#define CFG_BUS_TYPE 0x00000007ul /* GX/CX */ +#define CFG_MEM_TYPE_T 0x00000007ul /* 264xT */ +#define CFG_MEM_TYPE 0x00000038ul /* GX/CX */ +#define CFG_DUAL_CAS_EN_T 0x00000008ul /* 264xT */ +#define CFG_ROM_128K_EN 0x00000008ul /* VTB/GTB/LT */ +#define CFG_ROM_REMAP 0x00000008ul /* GTPro */ +#define CFG_VGA_EN_T 0x00000010ul /* VT/GT */ +#define CFG_CLOCK_EN 0x00000020ul /* 264xT */ +#define CFG_DUAL_CAS_EN 0x00000040ul /* GX/CX */ +#define CFG_VMC_SENSE 0x00000040ul /* VT/GT */ +#define CFG_SHARED_MEM_EN 0x00000040ul /* VTB/GTB/LT */ +#define CFG_LOCAL_BUS_OPTION 0x00000180ul /* GX/CX */ +#define CFG_VFC_SENSE 0x00000080ul /* VT/GT */ +#define CFG_INIT_DAC_TYPE 0x00000e00ul /* GX/CX */ +#define CFG_INIT_CARD_ID 0x00007000ul /* GX-C/-D */ +#define CFG_BLK_WR_SIZE 0x00001000ul /* GX-E+ */ +#define CFG_INT_QSF_EN 0x00002000ul /* GX-E+ */ +/* ? 0x00004000ul */ /* GX-E+ */ +/* ? 0x00007000ul */ /* CX */ +#define CFG_TRI_BUF_DIS 0x00008000ul /* GX/CX */ +#define CFG_BOARD_ID 0x0000ff00ul /* VT/GT */ +#define CFG_EXT_RAM_ADDR 0x003f0000ul /* GX/CX */ +#define CFG_PANEL_ID 0x001f0000ul /* LT */ +#define CFG_MACROVISION_EN 0x00200000ul /* GTPro */ +#define CFG_ROM_DIS 0x00400000ul /* GX/CX */ +#define CFG_PCI33EN 0x00400000ul /* GTPro */ +#define CFG_VGA_EN 0x00800000ul /* GX/CX */ +#define CFG_FULLAGP 0x00800000ul /* GTPro */ +#define CFG_ARITHMOS_ENABLE 0x00800000ul /* XC/XL */ +#define CFG_LOCAL_BUS_CFG 0x01000000ul /* GX/CX */ +#define CFG_CHIP_EN 0x02000000ul /* GX/CX */ +#define CFG_LOCAL_READ_DLY_DIS 0x04000000ul /* GX/CX */ +#define CFG_ROM_OPTION 0x08000000ul /* GX/CX */ +#define CFG_BUS_OPTION 0x10000000ul /* GX/CX */ +#define CFG_LOCAL_DAC_WR_EN 0x20000000ul /* GX/CX */ +#define CFG_VLB_RDY_DIS 0x40000000ul /* GX/CX */ +#define CFG_AP_4GBYTE_DIS 0x80000000ul /* GX/CX */ +#define CONFIG_STATUS64_1 IOPortTag(0x1du, 0x3au) /* Read */ +#define CFG_PCI_DAC_CFG 0x00000001ul /* GX/CX */ +/* ? 0x0000001eul */ /* GX/CX */ +#define CFG_1C8_IO_SEL 0x00000020ul /* GX/CX */ +/* ? 0xffffffc0ul */ /* GX/CX */ +#define CRC_SIG 0xfffffffful /* 264xT */ +#define MPP_CONFIG BlockIOTag(0x3bu) /* VTB/GTB/LT */ +#define MPP_STROBE_CONFIG BlockIOTag(0x3cu) /* VTB/GTB/LT */ +#define MPP_ADDR BlockIOTag(0x3du) /* VTB/GTB/LT */ +#define MPP_DATA BlockIOTag(0x3eu) /* VTB/GTB/LT */ +#define TVO_CNTL BlockIOTag(0x3fu) /* VTB/GTB/LT */ +/* GP_IO IOPortTag(0x1eu, 0x1eu) */ /* See above */ +/* CRTC_H_TOTAL_DISP IOPortTag(0x1fu, 0x00u) */ /* Duplicate */ +#define DST_OFF_PITCH BlockIOTag(0x40u) +#define DST_OFFSET 0x000ffffful +/* ? 0x00300000ul */ +#define DST_PITCH 0xffc00000ul +#define DST_X BlockIOTag(0x41u) +#define DST_Y BlockIOTag(0x42u) +#define DST_Y_X BlockIOTag(0x43u) +#define DST_WIDTH BlockIOTag(0x44u) +#define DST_HEIGHT BlockIOTag(0x45u) +#define DST_HEIGHT_WIDTH BlockIOTag(0x46u) +#define DST_X_WIDTH BlockIOTag(0x47u) +#define DST_BRES_LNTH BlockIOTag(0x48u) +#define DST_BRES_ERR BlockIOTag(0x49u) +#define DST_BRES_INC BlockIOTag(0x4au) +#define DST_BRES_DEC BlockIOTag(0x4bu) +#define DST_CNTL BlockIOTag(0x4cu) +#define DST_X_DIR 0x00000001ul +#define DST_Y_DIR 0x00000002ul +#define DST_Y_MAJOR 0x00000004ul +#define DST_X_TILE 0x00000008ul +#define DST_Y_TILE 0x00000010ul +#define DST_LAST_PEL 0x00000020ul +#define DST_POLYGON_EN 0x00000040ul +#define DST_24_ROT_EN 0x00000080ul +#define DST_24_ROT 0x00000700ul +#define DST_BRES_SIGN 0x00000800ul /* GX/CX */ +#define DST_BRES_ZERO 0x00000800ul /* CT */ +#define DST_POLYGON_RTEDGE_DIS 0x00001000ul /* CT */ +#define TRAIL_X_DIR 0x00002000ul /* GT */ +#define TRAP_FILL_DIR 0x00004000ul /* GT */ +#define TRAIL_BRES_SIGN 0x00008000ul /* GT */ +/* ? 0x00010000ul */ +#define BRES_SIGN_AUTO 0x00020000ul /* GT */ +/* ? 0x00040000ul */ +#define ALPHA_OVERLAP_ENB 0x00080000ul /* GTPro */ +#define SUB_PIX_ON 0x00100000ul /* GTPro */ +/* ? 0xffe00000ul */ +/* DST_Y_X BlockIOTag(0x4du) */ /* Duplicate */ +#define TRAIL_BRES_ERR BlockIOTag(0x4eu) /* GT */ +#define TRAIL_BRES_INC BlockIOTag(0x4fu) /* GT */ +#define TRAIL_BRES_DEC BlockIOTag(0x50u) /* GT */ +#define LEAD_BRES_LNTH BlockIOTag(0x51u) /* GT */ +#define Z_OFF_PITCH BlockIOTag(0x52u) /* GT */ +#define Z_CNTL BlockIOTag(0x53u) /* GT */ +#define ALPHA_TST_CNTL BlockIOTag(0x54u) /* GTPro */ +/* ? BlockIOTag(0x55u) */ +#define SECONDARY_STW_EXP BlockIOTag(0x56u) /* GTPro */ +#define SECONDARY_S_X_INC BlockIOTag(0x57u) /* GTPro */ +#define SECONDARY_S_Y_INC BlockIOTag(0x58u) /* GTPro */ +#define SECONDARY_S_START BlockIOTag(0x59u) /* GTPro */ +#define SECONDARY_W_X_INC BlockIOTag(0x5au) /* GTPro */ +#define SECONDARY_W_Y_INC BlockIOTag(0x5bu) /* GTPro */ +#define SECONDARY_W_START BlockIOTag(0x5cu) /* GTPro */ +#define SECONDARY_T_X_INC BlockIOTag(0x5du) /* GTPro */ +#define SECONDARY_T_Y_INC BlockIOTag(0x5eu) /* GTPro */ +#define SECONDARY_T_START BlockIOTag(0x5fu) /* GTPro */ +#define SRC_OFF_PITCH BlockIOTag(0x60u) +#define SRC_OFFSET 0x000ffffful +/* ? 0x00300000ul */ +#define SRC_PITCH 0xffc00000ul +#define SRC_X BlockIOTag(0x61u) +#define SRC_Y BlockIOTag(0x62u) +#define SRC_Y_X BlockIOTag(0x63u) +#define SRC_WIDTH1 BlockIOTag(0x64u) +#define SRC_HEIGHT1 BlockIOTag(0x65u) +#define SRC_HEIGHT1_WIDTH1 BlockIOTag(0x66u) +#define SRC_X_START BlockIOTag(0x67u) +#define SRC_Y_START BlockIOTag(0x68u) +#define SRC_Y_X_START BlockIOTag(0x69u) +#define SRC_WIDTH2 BlockIOTag(0x6au) +#define SRC_HEIGHT2 BlockIOTag(0x6bu) +#define SRC_HEIGHT2_WIDTH2 BlockIOTag(0x6cu) +#define SRC_CNTL BlockIOTag(0x6du) +# define SRC_PATT_EN 0x00000001ul +# define SRC_PATT_ROT_EN 0x00000002ul +# define SRC_LINEAR_EN 0x00000004ul +# define SRC_BYTE_ALIGN 0x00000008ul +# define SRC_LINE_X_DIR 0x00000010ul +# define SRC_8X8X8_BRUSH 0x00000020ul /* VTB/GTB */ +# define FAST_FILL_EN 0x00000040ul /* VTB/GTB */ +# define SRC_TRACK_DST 0x00000080ul /* VTB/GTB */ +# define BUS_MASTER_EN 0x00000100ul /* VTB/GTB */ +# define BUS_MASTER_SYNC 0x00000200ul /* VTB/GTB */ +# define BUS_MASTER_OP 0x00000c00ul /* VTB/GTB */ +# define BM_OP_FRAME_TO_SYSTEM (0 << 10) +# define BM_OP_SYSTEM_TO_FRAME (1 << 10) +# define BM_OP_REG_TO_SYSTEM (2 << 10) +# define BM_OP_SYSTEM_TO_REG (3 << 10) +# define SRC_8X8X8_BRUSH_LOADED 0x00001000ul /* VTB/GTB */ +# define COLOR_REG_WRITE_EN 0x00002000ul /* VTB/GTB */ +# define BLOCK_WRITE_EN 0x00004000ul /* VTB/GTB */ +/* ? 0xffff8000ul */ +/* ? BlockIOTag(0x6eu) */ +/* ? BlockIOTag(0x6fu) */ +#define SCALE_Y_OFF BlockIOTag(0x70u) /* GT */ +#define SCALE_OFF BlockIOTag(0x70u) /* GTPro */ +#define SECONDARY_SCALE_OFF BlockIOTag(0x70u) /* GTPro */ +#define TEX_0_OFF BlockIOTag(0x70u) /* GT */ +#define TEX_1_OFF BlockIOTag(0x71u) /* GT */ +#define TEX_2_OFF BlockIOTag(0x72u) /* GT */ +#define TEX_3_OFF BlockIOTag(0x73u) /* GT */ +#define TEX_4_OFF BlockIOTag(0x74u) /* GT */ +#define TEX_5_OFF BlockIOTag(0x75u) /* GT */ +#define TEX_6_OFF BlockIOTag(0x76u) /* GT */ +#define SCALE_WIDTH BlockIOTag(0x77u) /* GT */ +#define TEX_7_OFF BlockIOTag(0x77u) /* GT */ +#define SCALE_HEIGHT BlockIOTag(0x78u) /* GT */ +#define TEX_8_OFF BlockIOTag(0x78u) /* GT */ +#define TEX_9_OFF BlockIOTag(0x79u) /* GT */ +#define TEX_10_OFF BlockIOTag(0x7au) /* GT */ +#define S_Y_INC BlockIOTag(0x7bu) /* GT */ +#define SCALE_Y_PITCH BlockIOTag(0x7bu) /* GT */ +#define SCALE_X_INC BlockIOTag(0x7cu) /* GT */ +#define RED_X_INC BlockIOTag(0x7cu) /* GT */ +#define GREEN_X_INC BlockIOTag(0x7du) /* GT */ +#define SCALE_Y_INC BlockIOTag(0x7du) /* GT */ +#define SCALE_VACC BlockIOTag(0x7eu) /* GT */ +#define SCALE_3D_CNTL BlockIOTag(0x7fu) /* GT */ +#define HOST_DATA_0 BlockIOTag(0x80u) +#define HOST_DATA_1 BlockIOTag(0x81u) +#define HOST_DATA_2 BlockIOTag(0x82u) +#define HOST_DATA_3 BlockIOTag(0x83u) +#define HOST_DATA_4 BlockIOTag(0x84u) +#define HOST_DATA_5 BlockIOTag(0x85u) +#define HOST_DATA_6 BlockIOTag(0x86u) +#define HOST_DATA_7 BlockIOTag(0x87u) +#define HOST_DATA_8 BlockIOTag(0x88u) +#define HOST_DATA_9 BlockIOTag(0x89u) +#define HOST_DATA_A BlockIOTag(0x8au) +#define HOST_DATA_B BlockIOTag(0x8bu) +#define HOST_DATA_C BlockIOTag(0x8cu) +#define HOST_DATA_D BlockIOTag(0x8du) +#define HOST_DATA_E BlockIOTag(0x8eu) +#define HOST_DATA_F BlockIOTag(0x8fu) +#define HOST_CNTL BlockIOTag(0x90u) +#define HOST_BYTE_ALIGN 0x00000001ul +#define HOST_BIG_ENDIAN_EN 0x00000002ul /* GX-E/CT */ +/* ? 0xfffffffcul */ +#define BM_HOSTDATA BlockIOTag(0x91u) /* VTB/GTB */ +#define BM_ADDR BlockIOTag(0x92u) /* VTB/GTB */ +#define BM_DATA BlockIOTag(0x92u) /* VTB/GTB */ +#define BM_GUI_TABLE_CMD BlockIOTag(0x93u) /* GTPro */ +# define CIRCULAR_BUF_SIZE_16KB (0 << 0) +# define CIRCULAR_BUF_SIZE_32KB (1 << 0) +# define CIRCULAR_BUF_SIZE_64KB (2 << 0) +# define CIRCULAR_BUF_SIZE_128KB (3 << 0) +# define LAST_DESCRIPTOR (1 << 31) +/* ? BlockIOTag(0x94u) */ +/* ? BlockIOTag(0x95u) */ +/* ? BlockIOTag(0x96u) */ +/* ? BlockIOTag(0x97u) */ +/* ? BlockIOTag(0x98u) */ +/* ? BlockIOTag(0x99u) */ +/* ? BlockIOTag(0x9au) */ +/* ? BlockIOTag(0x9bu) */ +/* ? BlockIOTag(0x9cu) */ +/* ? BlockIOTag(0x9du) */ +/* ? BlockIOTag(0x9eu) */ +/* ? BlockIOTag(0x9fu) */ +#define PAT_REG0 BlockIOTag(0xa0u) +#define PAT_REG1 BlockIOTag(0xa1u) +#define PAT_CNTL BlockIOTag(0xa2u) +#define PAT_MONO_EN 0x00000001ul +#define PAT_CLR_4x2_EN 0x00000002ul +#define PAT_CLR_8x1_EN 0x00000004ul +/* ? 0xfffffff8ul */ +/* ? BlockIOTag(0xa3u) */ +/* ? BlockIOTag(0xa4u) */ +/* ? BlockIOTag(0xa5u) */ +/* ? BlockIOTag(0xa6u) */ +/* ? BlockIOTag(0xa7u) */ +#define SC_LEFT BlockIOTag(0xa8u) +#define SC_RIGHT BlockIOTag(0xa9u) +#define SC_LEFT_RIGHT BlockIOTag(0xaau) +#define SC_TOP BlockIOTag(0xabu) +#define SC_BOTTOM BlockIOTag(0xacu) +#define SC_TOP_BOTTOM BlockIOTag(0xadu) +#define USR1_DST_OFF_PITCH BlockIOTag(0xaeu) /* LTPro */ +#define USR2_DST_OFF_PITCH BlockIOTag(0xafu) /* LTPro */ +#define DP_BKGD_CLR BlockIOTag(0xb0u) +#define DP_FRGD_CLR BlockIOTag(0xb1u) +#define DP_WRITE_MASK BlockIOTag(0xb2u) +#define DP_CHAIN_MASK BlockIOTag(0xb3u) +#define DP_CHAIN_1BPP 0x00000000ul /* Irrelevant */ +#define DP_CHAIN_4BPP 0x00008888ul +#define DP_CHAIN_8BPP 0x00008080ul +#define DP_CHAIN_8BPP_332 0x00009292ul +#define DP_CHAIN_15BPP_1555 0x00004210ul +#define DP_CHAIN_16BPP_565 0x00008410ul +#define DP_CHAIN_24BPP_888 0x00008080ul +#define DP_CHAIN_32BPP_8888 0x00008080ul +/* ? 0xffff0000ul */ +#define DP_PIX_WIDTH BlockIOTag(0xb4u) +#define DP_DST_PIX_WIDTH 0x0000000ful +#define COMPOSITE_PIX_WIDTH 0x000000f0ul /* GTPro */ +#define DP_SRC_PIX_WIDTH 0x00000f00ul +/* ? 0x00001000ul */ +#define DP_HOST_TRIPLE_EN 0x00002000ul /* GT2c/VT4 */ +#define DP_SRC_AUTONA_FIX_DIS 0x00004000ul /* GTB */ +#define DP_FAST_SRCCOPY_DIS 0x00008000ul /* GTB */ +#define DP_HOST_PIX_WIDTH 0x000f0000ul +#define DP_CI4_RGB_INDEX 0x00f00000ul /* GTB */ +#define DP_BYTE_PIX_ORDER 0x01000000ul +#define DP_CONVERSION_TEMP 0x02000000ul /* GTB */ +#define DP_CI4_RGB_LOW_NIBBLE 0x04000000ul /* GTB */ +#define DP_C14_RGB_HIGH_NIBBLE 0x08000000ul /* GTB */ +#define DP_SCALE_PIX_WIDTH 0xf0000000ul /* GTB */ +#define DP_MIX BlockIOTag(0xb5u) +# define BKGD_MIX_NOT_D (0 << 0) +# define BKGD_MIX_ZERO (1 << 0) +# define BKGD_MIX_ONE (2 << 0) +# define BKGD_MIX_D (3 << 0) +# define BKGD_MIX_NOT_S (4 << 0) +# define BKGD_MIX_D_XOR_S (5 << 0) +# define BKGD_MIX_NOT_D_XOR_S (6 << 0) +# define BKGD_MIX_S (7 << 0) +# define BKGD_MIX_NOT_D_OR_NOT_S (8 << 0) +# define BKGD_MIX_D_OR_NOT_S (9 << 0) +# define BKGD_MIX_NOT_D_OR_S (10 << 0) +# define BKGD_MIX_D_OR_S (11 << 0) +# define BKGD_MIX_D_AND_S (12 << 0) +# define BKGD_MIX_NOT_D_AND_S (13 << 0) +# define BKGD_MIX_D_AND_NOT_S (14 << 0) +# define BKGD_MIX_NOT_D_AND_NOT_S (15 << 0) +# define BKGD_MIX_D_PLUS_S_DIV2 (23 << 0) +# define FRGD_MIX_NOT_D (0 << 16) +# define FRGD_MIX_ZERO (1 << 16) +# define FRGD_MIX_ONE (2 << 16) +# define FRGD_MIX_D (3 << 16) +# define FRGD_MIX_NOT_S (4 << 16) +# define FRGD_MIX_D_XOR_S (5 << 16) +# define FRGD_MIX_NOT_D_XOR_S (6 << 16) +# define FRGD_MIX_S (7 << 16) +# define FRGD_MIX_NOT_D_OR_NOT_S (8 << 16) +# define FRGD_MIX_D_OR_NOT_S (9 << 16) +# define FRGD_MIX_NOT_D_OR_S (10 << 16) +# define FRGD_MIX_D_OR_S (11 << 16) +# define FRGD_MIX_D_AND_S (12 << 16) +# define FRGD_MIX_NOT_D_AND_S (13 << 16) +# define FRGD_MIX_D_AND_NOT_S (14 << 16) +# define FRGD_MIX_NOT_D_AND_NOT_S (15 << 16) +# define FRGD_MIX_D_PLUS_S_DIV2 (23 << 16) +#define DP_SRC BlockIOTag(0xb6u) +# define BKGD_SRC_BKGD_CLR (0 << 0) +# define BKGD_SRC_FRGD_CLR (1 << 0) +# define BKGD_SRC_HOST (2 << 0) +# define BKGD_SRC_BLIT (3 << 0) +# define BKGD_SRC_PATTERN (4 << 0) +# define BKGD_SRC_3D (5 << 0) +# define FRGD_SRC_BKGD_CLR (0 << 8) +# define FRGD_SRC_FRGD_CLR (1 << 8) +# define FRGD_SRC_HOST (2 << 8) +# define FRGD_SRC_BLIT (3 << 8) +# define FRGD_SRC_PATTERN (4 << 8) +# define FRGD_SRC_3D (5 << 8) +# define MONO_SRC_ONE (0 << 16) +# define MONO_SRC_PATTERN (1 << 16) +# define MONO_SRC_HOST (2 << 16) +# define MONO_SRC_BLIT (3 << 16) +#define DP_FRGD_CLR_MIX BlockIOTag(0xb7u) /* VTB/GTB */ +#define DP_FRGD_BKGD_CLR BlockIOTag(0xb8u) /* VTB/GTB */ +/* ? BlockIOTag(0xb9u) */ +#define DST_X_Y BlockIOTag(0xbau) /* VTB/GTB */ +#define DST_WIDTH_HEIGHT BlockIOTag(0xbbu) /* VTB/GTB */ +#define USR_DST_PITCH BlockIOTag(0xbcu) /* GTPro */ +/* ? BlockIOTag(0xbdu) */ +#define DP_SET_GUI_ENGINE2 BlockIOTag(0xbeu) /* GTPro */ +#define DP_SET_GUI_ENGINE BlockIOTag(0xbfu) /* VTB/GTB */ +#define CLR_CMP_CLR BlockIOTag(0xc0u) +#define CLR_CMP_MSK BlockIOTag(0xc1u) +#define CLR_CMP_CNTL BlockIOTag(0xc2u) +#define CLR_CMP_FN 0x00000007ul +#define CLR_CMP_FN_FALSE 0x00000000ul +#define CLR_CMP_FN_TRUE 0x00000001ul +/* ? 0x00000002ul */ +/* ? 0x00000003ul */ +#define CLR_CMP_FN_NOT_EQUAL 0x00000004ul +#define CLR_CMP_FN_EQUAL 0x00000005ul +/* ? 0x00000006ul */ +/* ? 0x00000007ul */ +/* ? 0x00fffff8ul */ +#define CLR_CMP_SRC 0x03000000ul +#define CLR_CMP_SRC_DST 0x00000000ul +#define CLR_CMP_SRC_2D 0x01000000ul +#define CLR_CMP_SRC_TEXEL 0x02000000ul +/* ? 0x03000000ul */ +/* ? 0xfc000000ul */ +/* ? BlockIOTag(0xc3u) */ +#define FIFO_STAT BlockIOTag(0xc4u) +#define FIFO_STAT_BITS 0x0000fffful +/* ? 0x7fff0000ul */ +#define FIFO_ERR 0x80000000ul +/* ? BlockIOTag(0xc5u) */ +/* ? BlockIOTag(0xc6u) */ +/* ? BlockIOTag(0xc7u) */ +#define CONTEXT_MASK BlockIOTag(0xc8u) +/* ? BlockIOTag(0xc9u) */ +/* ? BlockIOTag(0xcau) */ +#define CONTEXT_LOAD_CNTL BlockIOTag(0xcbu) +#define CONTEXT_LOAD_PTR 0x00007ffful +/* ? 0x00008000ul */ +#define CONTEXT_LOAD_CMD 0x00030000ul +#define CONTEXT_LOAD_NONE 0x00000000ul +#define CONTEXT_LOAD_ONLY 0x00010000ul +#define CONTEXT_LOAD_FILL 0x00020000ul +#define CONTEXT_LOAD_LINE 0x00030000ul +/* ? 0x7ffc0000ul */ +#define CONTEXT_LOAD_DIS 0x80000000ul +#define GUI_TRAJ_CNTL BlockIOTag(0xccu) +/* ? BlockIOTag(0xcdu) */ +#define GUI_STAT BlockIOTag(0xceu) +#define GUI_ACTIVE 0x00000001ul +/* ? 0x000000feul */ +#define DSTX_LT_SCISSOR_LEFT 0x00000100ul +#define DSTX_GT_SCISSOR_RIGHT 0x00000200ul +#define DSTY_LT_SCISSOR_TOP 0x00000400ul +#define DSTY_GT_SCISSOR_BOTTOM 0x00000800ul +/* ? 0x0000f000ul */ +#define GUI_FIFO 0x03ff0000ul /* VTB/GTB */ +/* ? 0xfc000000ul */ +/* ? BlockIOTag(0xcfu) */ +#define S_X_INC2 BlockIOTag(0xd0u) /* GTB */ +#define TEX_PALETTE_INDEX BlockIOTag(0xd0u) /* GTPro */ +#define S_Y_INC2 BlockIOTag(0xd1u) /* GTB */ +#define STW_EXP BlockIOTag(0xd1u) /* GTPro */ +#define S_XY_INC2 BlockIOTag(0xd2u) /* GTB */ +#define LOG_MAX_INC BlockIOTag(0xd2u) /* GTPro */ +#define S_XINC_START BlockIOTag(0xd3u) /* GTB */ +/* S_Y_INC BlockIOTag(0xd4u) */ /* Duplicate */ +/* SCALE_Y_PITCH BlockIOTag(0xd4u) */ /* Duplicate */ +#define S_START BlockIOTag(0xd5u) /* GTB */ +#define T_X_INC2 BlockIOTag(0xd6u) /* GTB */ +#define W_X_INC BlockIOTag(0xd6u) /* GTPro */ +#define T_Y_INC2 BlockIOTag(0xd7u) /* GTB */ +#define W_Y_INC BlockIOTag(0xd7u) /* GTPro */ +#define T_XY_INC2 BlockIOTag(0xd8u) /* GTB */ +#define W_START BlockIOTag(0xd8u) /* GTPro */ +#define T_XINC_START BlockIOTag(0xd9u) /* GTB */ +#define T_Y_INC BlockIOTag(0xdau) /* GTB */ +#define SECONDARY_SCALE_PITCH BlockIOTag(0xdau) /* GTPro */ +#define T_START BlockIOTag(0xdbu) /* GTB */ +#define TEX_SIZE_PITCH BlockIOTag(0xdcu) /* GTB */ +#define TEX_CNTL BlockIOTag(0xddu) /* GTPro */ +#define SECONDARY_TEX_OFFSET BlockIOTag(0xdeu) /* GTPro */ +#define TEX_PAL_WR BlockIOTag(0xdfu) /* GTB */ +#define TEX_PALETTE BlockIOTag(0xdfu) /* GTPro */ +#define SCALE_PITCH_BOTH BlockIOTag(0xe0u) /* GTPro */ +#define SECONDARY_SCALE_OFF_ACC BlockIOTag(0xe1u) /* GTPro */ +#define SCALE_OFF_ACC BlockIOTag(0xe2u) /* GTPro */ +#define SCALE_DST_Y_X BlockIOTag(0xe3u) /* GTPro */ +/* ? BlockIOTag(0xe4u) */ +/* ? BlockIOTag(0xe5u) */ +#define COMPOSITE_SHADOW_ID BlockIOTag(0xe6u) /* GTPro */ +#define SECONDARY_SCALE_X_INC BlockIOTag(0xe7u) /* GTPro */ +#define SPECULAR_RED_X_INC BlockIOTag(0xe7u) /* GTPro */ +#define SPECULAR_RED_Y_INC BlockIOTag(0xe8u) /* GTPro */ +#define SPECULAR_RED_START BlockIOTag(0xe9u) /* GTPro */ +#define SECONDARY_SCALE_HACC BlockIOTag(0xe9u) /* GTPro */ +#define SPECULAR_GREEN_X_INC BlockIOTag(0xeau) /* GTPro */ +#define SPECULAR_GREEN_Y_INC BlockIOTag(0xebu) /* GTPro */ +#define SPECULAR_GREEN_START BlockIOTag(0xecu) /* GTPro */ +#define SPECULAR_BLUE_X_INC BlockIOTag(0xedu) /* GTPro */ +#define SPECULAR_BLUE_Y_INC BlockIOTag(0xeeu) /* GTPro */ +#define SPECULAR_BLUE_START BlockIOTag(0xefu) /* GTPro */ +/* SCALE_X_INC BlockIOTag(0xf0u) */ /* Duplicate */ +/* RED_X_INC BlockIOTag(0xf0u) */ /* Duplicate */ +#define RED_Y_INC BlockIOTag(0xf1u) /* GTB */ +#define SCALE_HACC BlockIOTag(0xf2u) /* GTB */ +#define RED_START BlockIOTag(0xf2u) /* GTB */ +/* GREEN_X_INC BlockIOTag(0xf3u) */ /* Duplicate */ +/* SCALE_Y_INC BlockIOTag(0xf3u) */ /* Duplicate */ +#define GREEN_Y_INC BlockIOTag(0xf4u) /* GTB */ +#define SECONDARY_SCALE_Y_INC BlockIOTag(0xf4u) /* GTPro */ +#define SECONDARY_SCALE_VACC BlockIOTag(0xf5u) /* GTPro */ +#define GREEN_START BlockIOTag(0xf5u) /* GTB */ +#define BLUE_X_INC BlockIOTag(0xf6u) /* GTB */ +#define SCALE_XUV_INC BlockIOTag(0xf6u) /* GTB */ +#define BLUE_Y_INC BlockIOTag(0xf7u) /* GTB */ +#define BLUE_START BlockIOTag(0xf8u) /* GTB */ +#define SCALE_UV_HACC BlockIOTag(0xf8u) /* GTB */ +#define Z_X_INC BlockIOTag(0xf9u) /* GTB */ +#define Z_Y_INC BlockIOTag(0xfau) /* GTB */ +#define Z_START BlockIOTag(0xfbu) /* GTB */ +#define ALPHA_FOG_X_INC BlockIOTag(0xfcu) /* GTB */ +#define ALPHA_FOG_Y_INC BlockIOTag(0xfdu) /* GTB */ +#define ALPHA_FOG_START BlockIOTag(0xfeu) /* GTB */ +/* ? BlockIOTag(0xffu) */ +#define OVERLAY_Y_X_START BlockIOTag(0x100u) +#define OVERLAY_Y_X_END BlockIOTag(0x101u) +#define OVERLAY_VIDEO_KEY_CLR BlockIOTag(0x102u) +#define OVERLAY_VIDEO_KEY_MSK BlockIOTag(0x103u) +#define OVERLAY_GRAPHICS_KEY_CLR BlockIOTag(0x104u) +#define OVERLAY_GRAPHICS_KEY_MSK BlockIOTag(0x105u) +#define OVERLAY_KEY_CNTL BlockIOTag(0x106u) +# define VIDEO_KEY_FN_MASK 0x00000007L +# define VIDEO_KEY_FN_FALSE 0x00000000L +# define VIDEO_KEY_FN_TRUE 0x00000001L +# define VIDEO_KEY_FN_NE 0x00000004L +# define VIDEO_KEY_FN_EQ 0x00000005L // EQ and NE are exchanged relative to radeon +# define GRAPHIC_KEY_FN_MASK 0x00000070L +# define GRAPHIC_KEY_FN_FALSE 0x00000000L +# define GRAPHIC_KEY_FN_TRUE 0x00000010L +# define GRAPHIC_KEY_FN_NE 0x00000040L +# define GRAPHIC_KEY_FN_EQ 0x00000050L // EQ and NE are exchanged relative to radeon +# define CMP_MIX_MASK 0x00000100L +# define CMP_MIX_OR 0x00000000L +# define CMP_MIX_AND 0x00000100L +/* ? BlockIOTag(0x107u) */ +#define OVERLAY_SCALE_INC BlockIOTag(0x108u) +#define OVERLAY_SCALE_CNTL BlockIOTag(0x109u) +#define SCALER_HEIGHT_WIDTH BlockIOTag(0x10au) +#define OVERLAY_TEST BlockIOTag(0x10bu) +#define SCALER_THRESHOLD BlockIOTag(0x10cu) +#define SCALER_BUF0_OFFSET BlockIOTag(0x10du) /* VTB/GTB */ +#define SCALER_BUF1_OFFSET BlockIOTag(0x10eu) /* VTB/GTB */ +#define SCALER_BUF_PITCH BlockIOTag(0x10fu) /* VTB/GTB */ +#define CAPTURE_Y_X BlockIOTag(0x110u) +#define CAPTURE_START_END BlockIOTag(0x110u) /* VTB/GTB */ +#define CAPTURE_HEIGHT_WIDTH BlockIOTag(0x111u) +#define CAPTURE_X_WIDTH BlockIOTag(0x111u) /* VTB/GTB */ +#define VIDEO_FORMAT BlockIOTag(0x112u) +#define VIDEO_CONFIG BlockIOTag(0x113u) +#define VBI_START_END BlockIOTag(0x113u) /* VTB/GTB */ +#define CAPTURE_CONFIG BlockIOTag(0x114u) +#define TRIG_CNTL BlockIOTag(0x115u) +#define VIDEO_SYNC_TEST BlockIOTag(0x116u) +#define OVERLAY_EXCLUSIVE_HORZ BlockIOTag(0x116u) /* VTB/GTB */ +#define EXT_CRTC_GEN_CNTL_R BlockIOTag(0x117u) /* VT-A4 (R) */ +#define OVERLAY_EXCLUSIVE_VERT BlockIOTag(0x117u) /* VTB/GTB */ +#define VMC_CONFIG BlockIOTag(0x118u) +#define VBI_WIDTH BlockIOTag(0x118u) /* VTB/GTB */ +#define VMC_STATUS BlockIOTag(0x119u) +#define CAPTURE_DEBUG BlockIOTag(0x119u) /* VTB/GTB */ +#define VMC_CMD BlockIOTag(0x11au) +#define VIDEO_SYNC_TEST_B BlockIOTag(0x11au) /* VTB/GTB */ +#define VMC_ARG0 BlockIOTag(0x11bu) +#define VMC_ARG1 BlockIOTag(0x11cu) +#define SNAPSHOT_VH_COUNTS BlockIOTag(0x11cu) /* GTPro */ +#define VMC_SNOOP_ARG0 BlockIOTag(0x11du) +#define SNAPSHOT_F_COUNT BlockIOTag(0x11du) /* GTPro */ +#define VMC_SNOOP_ARG1 BlockIOTag(0x11eu) +#define N_VIF_COUNT BlockIOTag(0x11eu) /* GTPro */ +#define SNAPSHOT_VIF_COUNT BlockIOTag(0x11fu) /* GTPro */ +#define BUF0_OFFSET BlockIOTag(0x120u) +#define CAPTURE_BUF0_OFFSET BlockIOTag(0x120u) /* VTB/GTB */ +#define CAPTURE_BUF1_OFFSET BlockIOTag(0x121u) /* VTB/GTB */ +#define ONESHOT_BUF_OFFSET BlockIOTag(0x122u) /* VTB/GTB */ +#define BUF0_PITCH BlockIOTag(0x123u) +/* ? BlockIOTag(0x124u) */ +/* ? BlockIOTag(0x125u) */ +#define BUF1_OFFSET BlockIOTag(0x126u) +/* ? BlockIOTag(0x127u) */ +/* ? BlockIOTag(0x128u) */ +#define BUF1_PITCH BlockIOTag(0x129u) +/* ? BlockIOTag(0x12au) */ +#define BUF0_CAP_ODD_OFFSET BlockIOTag(0x12bu) +#define BUF1_CAP_ODD_OFFSET BlockIOTag(0x12cu) +#define SNAPSHOT2_VH_COUNTS BlockIOTag(0x12cu) /* LTPro */ +#define SNAPSHOT2_F_COUNT BlockIOTag(0x12du) /* LTPro */ +#define N_VIF2_COUNT BlockIOTag(0x12eu) /* LTPro */ +#define SNAPSHOT2_VIF_COUNT BlockIOTag(0x12fu) /* LTPro */ +#define VMC_STRM_DATA_0 BlockIOTag(0x130u) +/* MPP_CONFIG BlockIOTag(0x130u) */ /* See 0x3bu */ +#define VMC_STRM_DATA_1 BlockIOTag(0x131u) +/* MPP_STROBE_SEQ BlockIOTag(0x131u) */ /* See 0x3cu */ +#define VMC_STRM_DATA_2 BlockIOTag(0x132u) +/* MPP_ADDR BlockIOTag(0x132u) */ /* See 0x3du */ +#define VMC_STRM_DATA_3 BlockIOTag(0x133u) +/* MPP_DATA BlockIOTag(0x133u) */ /* See 0x3eu */ +#define VMC_STRM_DATA_4 BlockIOTag(0x134u) +#define VMC_STRM_DATA_5 BlockIOTag(0x135u) +#define VMC_STRM_DATA_6 BlockIOTag(0x136u) +#define VMC_STRM_DATA_7 BlockIOTag(0x137u) +#define VMC_STRM_DATA_8 BlockIOTag(0x138u) +#define VMC_STRM_DATA_9 BlockIOTag(0x139u) +#define VMC_STRM_DATA_A BlockIOTag(0x13au) +#define VMC_STRM_DATA_B BlockIOTag(0x13bu) +#define VMC_STRM_DATA_C BlockIOTag(0x13cu) +#define VMC_STRM_DATA_D BlockIOTag(0x13du) +#define VMC_STRM_DATA_E BlockIOTag(0x13eu) +#define VMC_STRM_DATA_F BlockIOTag(0x13fu) +/* TVO_CNTL BlockIOTag(0x140u) */ /* See 0x3fu */ +/* ? BlockIOTag(0x141u) */ +/* ? BlockIOTag(0x142u) */ +/* ? BlockIOTag(0x143u) */ +/* ? BlockIOTag(0x144u) */ +/* ? BlockIOTag(0x145u) */ +/* ? BlockIOTag(0x146u) */ +/* ? BlockIOTag(0x147u) */ +/* ? BlockIOTag(0x148u) */ +/* ? BlockIOTag(0x149u) */ +/* ? BlockIOTag(0x14au) */ +/* ? BlockIOTag(0x14bu) */ +/* ? BlockIOTag(0x14cu) */ +/* ? BlockIOTag(0x14du) */ +/* ? BlockIOTag(0x14eu) */ +/* ? BlockIOTag(0x14fu) */ +/* ? BlockIOTag(0x150u) */ +#define CRT_HORZ_VERT_LOAD BlockIOTag(0x151u) /* VTB/GTB */ +#define AGP_BASE BlockIOTag(0x152u) /* GTPro */ +#define AGP_CNTL BlockIOTag(0x153u) /* GTPro */ +#define SCALER_COLOUR_CNTL BlockIOTag(0x154u) /* GTPro */ +#define SCALER_H_COEFF0 BlockIOTag(0x155u) /* GTPro */ +#define SCALER_H_COEFF1 BlockIOTag(0x156u) /* GTPro */ +#define SCALER_H_COEFF2 BlockIOTag(0x157u) /* GTPro */ +#define SCALER_H_COEFF3 BlockIOTag(0x158u) /* GTPro */ +#define SCALER_H_COEFF4 BlockIOTag(0x159u) /* GTPro */ +/* ? BlockIOTag(0x15au) */ +/* ? BlockIOTag(0x15bu) */ +#define GUI_CMDFIFO_DEBUG BlockIOTag(0x15cu) /* GT2c/VT4 */ +#define GUI_CMDFIFO_DATA BlockIOTag(0x15du) /* GT2c/VT4 */ +#define GUI_CNTL BlockIOTag(0x15eu) /* GT2c/VT4 */ +# define CMDFIFO_SIZE_MASK 0x00000003ul +# define CMDFIFO_SIZE_192 0x00000000ul +# define CMDFIFO_SIZE_128 0x00000001ul +# define CMDFIFO_SIZE_64 0x00000002ul +/* ? 0x0000fffcul */ +# define IDCT_PRSR_MODE 0x00010000ul /* XL/XC */ +# define IDCT_BLOCK_GUI_INITIATOR 0x00020000ul /* XL/XC */ +/* ? 0xfffc0000ul */ +/* ? BlockIOTag(0x15fu) */ +/* BUS MASTERING */ +#define BM_FRAME_BUF_OFFSET BlockIOTag(0x160u) /* VTB/GTB */ +#define BM_SYSTEM_MEM_ADDR BlockIOTag(0x161u) /* VTB/GTB */ +#define BM_COMMAND BlockIOTag(0x162u) /* VTB/GTB */ +#define BM_STATUS BlockIOTag(0x163u) /* VTB/GTB */ +/* ? BlockIOTag(0x164u) */ +/* ? BlockIOTag(0x165u) */ +/* ? BlockIOTag(0x166u) */ +/* ? BlockIOTag(0x167u) */ +/* ? BlockIOTag(0x168u) */ +/* ? BlockIOTag(0x169u) */ +/* ? BlockIOTag(0x16au) */ +/* ? BlockIOTag(0x16bu) */ +/* ? BlockIOTag(0x16cu) */ +/* ? BlockIOTag(0x16du) */ +#define BM_GUI_TABLE BlockIOTag(0x16eu) /* VTB/GTB */ +#define BM_SYSTEM_TABLE BlockIOTag(0x16fu) /* VTB/GTB */ +# define DMA_GUI_COMMAND__BYTE_COUNT_MASK 0x001fffff +# define DMA_GUI_COMMAND__HOLD_VIDEO_OFFSET 0x40000000 +# define DMA_GUI_COMMAND__EOL 0x80000000 +# define SYSTEM_TRIGGER_SYSTEM_TO_VIDEO 0x0 +# define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM 0x1 +# define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM_AFTER_BUF0_READY 0x2 +# define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM_AFTER_BUF1_READY 0x3 +# define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM_AFTER_SNAPSHOT_READY 0x4 +/* ? BlockIOTag(0x170u) */ +/* ? BlockIOTag(0x171u) */ +/* ? BlockIOTag(0x172u) */ +/* ? BlockIOTag(0x173u) */ +/* ? BlockIOTag(0x174u) */ +#define SCALER_BUF0_OFFSET_V BlockIOTag(0x175u) /* GTPro */ +#define SCALER_BUF0_OFFSET_U BlockIOTag(0x176u) /* GTPro */ +#define SCALER_BUF1_OFFSET_V BlockIOTag(0x177u) /* GTPro */ +#define SCALER_BUF1_OFFSET_U BlockIOTag(0x178u) /* GTPro */ +/* ? BlockIOTag(0x179u) */ +/* ? BlockIOTag(0x17au) */ +/* ? BlockIOTag(0x17bu) */ +/* ? BlockIOTag(0x17cu) */ +/* ? BlockIOTag(0x17du) */ +/* ? BlockIOTag(0x17eu) */ +/* ? BlockIOTag(0x17fu) */ +/* ? BlockIOTag(0x180u) */ +/* ? BlockIOTag(0x181u) */ +/* ? BlockIOTag(0x182u) */ +/* ? BlockIOTag(0x183u) */ +/* ? BlockIOTag(0x184u) */ +/* ? BlockIOTag(0x185u) */ +/* ? BlockIOTag(0x186u) */ +/* ? BlockIOTag(0x187u) */ +/* ? BlockIOTag(0x188u) */ +/* ? BlockIOTag(0x189u) */ +/* ? BlockIOTag(0x18au) */ +/* ? BlockIOTag(0x18bu) */ +/* ? BlockIOTag(0x18cu) */ +/* ? BlockIOTag(0x18du) */ +/* ? BlockIOTag(0x18eu) */ +/* ? BlockIOTag(0x18fu) */ +#define VERTEX_1_S BlockIOTag(0x190u) /* GTPro */ +#define VERTEX_1_T BlockIOTag(0x191u) /* GTPro */ +#define VERTEX_1_W BlockIOTag(0x192u) /* GTPro */ +#define VERTEX_1_SPEC_ARGB BlockIOTag(0x193u) /* GTPro */ +#define VERTEX_1_Z BlockIOTag(0x194u) /* GTPro */ +#define VERTEX_1_ARGB BlockIOTag(0x195u) /* GTPro */ +#define VERTEX_1_X_Y BlockIOTag(0x196u) /* GTPro */ +#define ONE_OVER_AREA BlockIOTag(0x197u) /* GTPro */ +#define VERTEX_2_S BlockIOTag(0x198u) /* GTPro */ +#define VERTEX_2_T BlockIOTag(0x199u) /* GTPro */ +#define VERTEX_2_W BlockIOTag(0x19au) /* GTPro */ +#define VERTEX_2_SPEC_ARGB BlockIOTag(0x19bu) /* GTPro */ +#define VERTEX_2_Z BlockIOTag(0x19cu) /* GTPro */ +#define VERTEX_2_ARGB BlockIOTag(0x19du) /* GTPro */ +#define VERTEX_2_X_Y BlockIOTag(0x19eu) /* GTPro */ +/* ONE_OVER_AREA BlockIOTag(0x19fu) */ /* Duplicate */ +#define VERTEX_3_S BlockIOTag(0x1a0u) /* GTPro */ +#define VERTEX_3_T BlockIOTag(0x1a1u) /* GTPro */ +#define VERTEX_3_W BlockIOTag(0x1a2u) /* GTPro */ +#define VERTEX_3_SPEC_ARGB BlockIOTag(0x1a3u) /* GTPro */ +#define VERTEX_3_Z BlockIOTag(0x1a4u) /* GTPro */ +#define VERTEX_3_ARGB BlockIOTag(0x1a5u) /* GTPro */ +#define VERTEX_3_X_Y BlockIOTag(0x1a6u) /* GTPro */ +/* ONE_OVER_AREA BlockIOTag(0x1a7u) */ /* Duplicate */ +#define VERTEX_3_SECONDARY_S BlockIOTag(0x1a8u) /* GTPro */ +#define VERTEX_3_SECONDARY_T BlockIOTag(0x1a9u) /* GTPro */ +#define VERTEX_3_SECONDARY_W BlockIOTag(0x1aau) /* GTPro */ +/* VERTEX_1_S BlockIOTag(0x1abu) */ /* Duplicate */ +/* VERTEX_1_T BlockIOTag(0x1acu) */ /* Duplicate */ +/* VERTEX_1_W BlockIOTag(0x1adu) */ /* Duplicate */ +/* VERTEX_2_S BlockIOTag(0x1aeu) */ /* Duplicate */ +/* VERTEX_2_T BlockIOTag(0x1afu) */ /* Duplicate */ +/* VERTEX_2_W BlockIOTag(0x1b0u) */ /* Duplicate */ +/* VERTEX_3_S BlockIOTag(0x1b1u) */ /* Duplicate */ +/* VERTEX_3_T BlockIOTag(0x1b2u) */ /* Duplicate */ +/* VERTEX_3_W BlockIOTag(0x1b3u) */ /* Duplicate */ +/* VERTEX_1_SPEC_ARGB BlockIOTag(0x1b4u) */ /* Duplicate */ +/* VERTEX_2_SPEC_ARGB BlockIOTag(0x1b5u) */ /* Duplicate */ +/* VERTEX_3_SPEC_ARGB BlockIOTag(0x1b6u) */ /* Duplicate */ +/* VERTEX_1_Z BlockIOTag(0x1b7u) */ /* Duplicate */ +/* VERTEX_2_Z BlockIOTag(0x1b8u) */ /* Duplicate */ +/* VERTEX_3_Z BlockIOTag(0x1b9u) */ /* Duplicate */ +/* VERTEX_1_ARGB BlockIOTag(0x1bau) */ /* Duplicate */ +/* VERTEX_2_ARGB BlockIOTag(0x1bbu) */ /* Duplicate */ +/* VERTEX_3_ARGB BlockIOTag(0x1bcu) */ /* Duplicate */ +/* VERTEX_1_X_Y BlockIOTag(0x1bdu) */ /* Duplicate */ +/* VERTEX_2_X_Y BlockIOTag(0x1beu) */ /* Duplicate */ +/* VERTEX_3_X_Y BlockIOTag(0x1bfu) */ /* Duplicate */ +#define ONE_OVER_AREA_UC BlockIOTag(0x1c0u) /* GTPro */ +#define SETUP_CNTL BlockIOTag(0x1c1u) /* GTPro */ +/* ? BlockIOTag(0x1c2u) */ +/* ? BlockIOTag(0x1c3u) */ +/* ? BlockIOTag(0x1c4u) */ +/* ? BlockIOTag(0x1c5u) */ +/* ? BlockIOTag(0x1c6u) */ +/* ? BlockIOTag(0x1c7u) */ +/* ? BlockIOTag(0x1c8u) */ +/* ? BlockIOTag(0x1c9u) */ +#define VERTEX_1_SECONDARY_S BlockIOTag(0x1cau) /* GTPro */ +#define VERTEX_1_SECONDARY_T BlockIOTag(0x1cbu) /* GTPro */ +#define VERTEX_1_SECONDARY_W BlockIOTag(0x1ccu) /* GTPro */ +#define VERTEX_2_SECONDARY_S BlockIOTag(0x1cdu) /* GTPro */ +#define VERTEX_2_SECONDARY_T BlockIOTag(0x1ceu) /* GTPro */ +#define VERTEX_2_SECONDARY_W BlockIOTag(0x1cfu) /* GTPro */ +/* ? BlockIOTag(0x1d0u) */ +/* ? BlockIOTag(0x1d1u) */ +/* ? BlockIOTag(0x1d2u) */ +/* ? BlockIOTag(0x1d3u) */ +/* ? BlockIOTag(0x1d4u) */ +/* ? BlockIOTag(0x1d5u) */ +/* ? BlockIOTag(0x1d6u) */ +/* ? BlockIOTag(0x1d7u) */ +/* ? BlockIOTag(0x1d8u) */ +/* ? BlockIOTag(0x1d9u) */ +/* ? BlockIOTag(0x1dau) */ +/* ? BlockIOTag(0x1dbu) */ +/* ? BlockIOTag(0x1dcu) */ +/* ? BlockIOTag(0x1ddu) */ +/* ? BlockIOTag(0x1deu) */ +/* ? BlockIOTag(0x1dfu) */ +/* ? BlockIOTag(0x1e0u) */ +/* ? BlockIOTag(0x1e1u) */ +/* ? BlockIOTag(0x1e2u) */ +/* ? BlockIOTag(0x1e3u) */ +/* ? BlockIOTag(0x1e4u) */ +/* ? BlockIOTag(0x1e5u) */ +/* ? BlockIOTag(0x1e6u) */ +/* ? BlockIOTag(0x1e7u) */ +/* ? BlockIOTag(0x1e8u) */ +/* ? BlockIOTag(0x1e9u) */ +/* ? BlockIOTag(0x1eau) */ +/* ? BlockIOTag(0x1ebu) */ +/* ? BlockIOTag(0x1ecu) */ +/* ? BlockIOTag(0x1edu) */ +/* ? BlockIOTag(0x1eeu) */ +/* ? BlockIOTag(0x1efu) */ +/* ? BlockIOTag(0x1f0u) */ +/* ? BlockIOTag(0x1f1u) */ +/* ? BlockIOTag(0x1f2u) */ +/* ? BlockIOTag(0x1f3u) */ +/* ? BlockIOTag(0x1f4u) */ +/* ? BlockIOTag(0x1f5u) */ +/* ? BlockIOTag(0x1f6u) */ +/* ? BlockIOTag(0x1f7u) */ +/* ? BlockIOTag(0x1f8u) */ +/* ? BlockIOTag(0x1f9u) */ +/* ? BlockIOTag(0x1fau) */ +/* ? BlockIOTag(0x1fbu) */ +/* ? BlockIOTag(0x1fcu) */ +/* ? BlockIOTag(0x1fdu) */ +/* ? BlockIOTag(0x1feu) */ +/* ? BlockIOTag(0x1ffu) */ + +/* Definitions for MEM_CNTL's CTL_MEM_?????_APER_ENDIAN fields */ +#define CTL_MEM_APER_BYTE_ENDIAN 0x00u +#define CTL_MEM_APER_WORD_ENDIAN 0x01u +#define CTL_MEM_APER_LONG_ENDIAN 0x02u +/* ? 0x03u */ + +/* Definitions for an ICS2595's programme word */ +#define ICS2595_CLOCK 0x000001f0ul +#define ICS2595_FB_DIV 0x0001fe00ul /* Feedback divider */ +#define ICS2595_POST_DIV 0x000c0000ul /* Post-divider */ +#define ICS2595_STOP 0x00300000ul /* Stop bits */ +#define ICS2595_TOGGLE (ICS2595_POST_DIV | ICS2595_STOP) + +/* Definitions for internal PLL registers on a 264xT */ +#define PLL_MPLL_CNTL 0x00u +#define MPLL_PC_GAIN 0x07u +#define MPLL_VC_GAIN 0x18u +#define MPLL_D_CYC 0x60u +#define MPLL_RANGE 0x80u +#define VPLL_CNTL 0x01u +#define VPLL_PC_GAIN 0x07u +#define VPLL_VC_GAIN 0x18u +#define VPLL_D_CYC 0x60u +#define VPLL_RANGE 0x80u +#define PLL_REF_DIV 0x02u +#define PLL_GEN_CNTL 0x03u +#define PLL_OVERRIDE 0x01u +#define PLL_SLEEP 0x01u /* GTPro */ +#define PLL_MCLK_RESET 0x02u +#define PLL_OSC_EN 0x04u +#define PLL_EXT_CLK_EN 0x08u +#define PLL_MCLK_SRC_SEL 0x70u +#define PLL_EXT_CLK_CNTL 0x80u /* CT/ET */ +#define PLL_DLL_PWDN 0x80u /* VTB/GTB/LT */ +#define PLL_MCLK_FB_DIV 0x04u +#define PLL_VCLK_CNTL 0x05u +#define PLL_VCLK_SRC_SEL 0x03u +#define PLL_VCLK_RESET 0x04u +#define PLL_VCLK_INVERT 0x08u +#define PLL_ECP_DIV 0x30u /* VT/GT */ +#define PLL_ERATE_GT_XRATE 0x40u /* VT/GT */ +#define PLL_SCALER_LOCK_EN 0x80u /* VT/GT */ +#define PLL_VCLK_POST_DIV 0x06u +#define PLL_VCLK0_POST_DIV 0x03u +#define PLL_VCLK1_POST_DIV 0x0cu +#define PLL_VCLK2_POST_DIV 0x30u +#define PLL_VCLK3_POST_DIV 0xc0u +#define PLL_VCLK0_FB_DIV 0x07u +#define PLL_VCLK1_FB_DIV 0x08u +#define PLL_VCLK2_FB_DIV 0x09u +#define PLL_VCLK3_FB_DIV 0x0au +#define PLL_XCLK_CNTL 0x0bu /* VT/GT */ +#define PLL_XCLK_MCLK_RATIO 0x03u +#define PLL_XCLK_SRC_SEL 0x07u /* VTB/GTB/LT */ +#define PLL_MFB_TIMES_4_2B 0x08u +#define PLL_VCLK0_XDIV 0x10u +#define PLL_VCLK1_XDIV 0x20u +#define PLL_VCLK2_XDIV 0x40u +#define PLL_VCLK3_XDIV 0x80u +#define PLL_FCP_CNTL 0x0cu /* VT/GT */ +#define PLL_FCP_POST_DIV 0x0fu +#define PLL_FCP_SRC_SEL 0x70u +#define PLL_DCLK_BY2_EN 0x80u +#define PLL_DLL_CNTL 0x0cu /* VTB/GTB/LT */ +#define PLL_DLL_REF_SRC 0x03u +#define PLL_DLL_FB_SRC 0x0cu +#define PLL_DLL_GAIN 0x30u +#define PLL_DLL_RESET 0x40u +#define PLL_DLL_HCLK_OUT_EN 0x80u +#define PLL_VFC_CNTL 0x0du /* VT/GT */ +#define PLL_DCLK_INVB 0x01u +#define PLL_DCLKBY2_EN 0x02u +#define PLL_VFC_2PHASE 0x04u +#define PLL_VFC_DELAY 0x18u +#define PLL_VFC_DCLKBY2_SHIFT 0x20u +/* ? 0x40u */ +#define PLL_TST_SRC_SEL_BIT5 0x80u /* VTB/GTB/LT */ +#define PLL_TEST_CNTL 0x0eu +#define PLL_TST_SRC_SEL 0x1fu +#define PLL_TST_DIVIDERS 0x20u +#define PLL_TST_MASK_READ 0x40u +#define PLL_TST_ANALOG_MON_EN 0x80u +#define PLL_TEST_COUNT 0x0fu +#define PLL_LVDSPLL_CNTL0 0x10u /* LT */ +#define PLL_FPDI_NS_TIMING 0x01u +#define PLL_CURR_LEVEL 0x0eu +#define PLL_LVDS_TEST_MODE 0xf0u +#define PLL_LVDSPLL_CNTL1 0x11u /* LT */ +#define PLL_LPPL_RANGE 0x01u +#define PLL_LPLL_DUTY 0x06u +#define PLL_LPLL_VC_GAIN 0x18u +#define PLL_LPLL_CP_GAIN 0xe0u +#define PLL_AGP1_CNTL 0x12u /* GTPro */ +#define PLL_AGP2_CNTL 0x13u /* GTPro */ +#define PLL_DLL2_CNTL 0x14u /* GTPro */ +#define PLL_SCLK_FB_DIV 0x15u /* GTPro */ +#define PLL_SPLL_CNTL1 0x16u /* GTPro */ +#define PLL_SPLL_CNTL2 0x17u /* GTPro */ +#define PLL_APLL_STRAPS 0x18u /* GTPro */ +#define PLL_EXT_VPLL_CNTL 0x19u /* GTPro */ +#define PLL_EXT_VPLL_REF_SRC 0x03u +#define PLL_EXT_VPLL_EN 0x04u +#define PLL_EXT_VPLL_VGA_EN 0x08u +#define PLL_EXT_VPLL_INSYNC 0x10u +/* ? 0x60u */ +#define PLL_EXT_V2PLL_EN 0x80u +#define PLL_EXT_VPLL_REF_DIV 0x1au /* GTPro */ +#define PLL_EXT_VPLL_FB_DIV 0x1bu /* GTPro */ +#define PLL_EXT_VPLL_MSB 0x1cu /* GTPro */ +#define PLL_HTOTAL_CNTL 0x1du /* GTPro */ +#define PLL_BYTE_CLK_CNTL 0x1eu /* GTPro */ +#define PLL_TV_REF_DIV 0x1fu /* LTPro */ +#define PLL_TV_FB_DIV 0x20u /* LTPro */ +#define PLL_TV_CNTL 0x21u /* LTPro */ +#define PLL_TV_GEN_CNTL 0x22u /* LTPro */ +#define PLL_V2_CNTL 0x23u /* LTPro */ +#define PLL_V2_GEN_CNTL 0x24u /* LTPro */ +#define PLL_V2_REF_DIV 0x25u /* LTPro */ +#define PLL_V2_FB_DIV 0x26u /* LTPro */ +#define PLL_V2_MSB 0x27u /* LTPro */ +#define PLL_HTOTAL2_CNTL 0x28u /* LTPro */ +#define PLL_YCLK_CNTL 0x29u /* XC/XL */ +#define PM_DYN_CLK_CNTL 0x2au /* XC/XL */ +/* ? 0x2bu */ +/* ? 0x2cu */ +/* ? 0x2du */ +/* ? 0x2eu */ +/* ? 0x2fu */ +/* ? 0x30u */ +/* ? 0x31u */ +/* ? 0x32u */ +/* ? 0x33u */ +/* ? 0x34u */ +/* ? 0x35u */ +/* ? 0x36u */ +/* ? 0x37u */ +/* ? 0x38u */ +/* ? 0x39u */ +/* ? 0x3au */ +/* ? 0x3bu */ +/* ? 0x3cu */ +/* ? 0x3du */ +/* ? 0x3eu */ +/* ? 0x3fu */ + +/* Definitions for an LTPro's 32-bit LCD registers */ +#define LCD_CONFIG_PANEL 0x00u /* See LT's CONFIG_PANEL (0x1d) */ +#define LCD_GEN_CNTL 0x01u /* See LT's LCD_GEN_CTRL (0x35) */ +#define LCD_DSTN_CONTROL 0x02u /* See LT's DSTN_CONTROL (0x1f) */ +#define LCD_HFB_PITCH_ADDR 0x03u /* See LT's HFB_PITCH_ADDR (0x2a) */ +#define LCD_HORZ_STRETCHING 0x04u /* See LT's HORZ_STRETCHING (0x32) */ +#define LCD_VERT_STRETCHING 0x05u /* See LT's VERT_STRETCHING (0x33) */ +#define LCD_EXT_VERT_STRETCH 0x06u +#define VERT_STRETCH_RATIO3 0x000003fful +#define FORCE_DAC_DATA 0x000000fful +#define FORCE_DAC_DATA_SEL 0x00000300ul +#define VERT_STRETCH_MODE 0x00000400ul +#define VERT_PANEL_SIZE 0x003ff800ul +#define AUTO_VERT_RATIO 0x00400000ul +#define USE_AUTO_FP_POS 0x00800000ul +#define USE_AUTO_LCD_VSYNC 0x01000000ul +/* ? 0xfe000000ul */ +#define LCD_LT_GIO 0x07u /* See LT's LT_GIO (0x2f) */ +#define LCD_POWER_MANAGEMENT 0x08u /* See LT's POWER_MANAGEMENT (0x36) */ +#define LCD_ZVGPIO 0x09u +#define LCD_ICON_CLR0 0x0au /* XC/XL */ +#define LCD_ICON_CLR1 0x0bu /* XC/XL */ +#define LCD_ICON_OFFSET 0x0cu /* XC/XL */ +#define LCD_ICON_HORZ_VERT_POSN 0x0du /* XC/XL */ +#define LCD_ICON_HORZ_VERT_OFF 0x0eu /* XC/XL */ +#define LCD_ICON2_CLR0 0x0fu /* XC/XL */ +#define LCD_ICON2_CLR1 0x10u /* XC/XL */ +#define LCD_ICON2_OFFSET 0x11u /* XC/XL */ +#define LCD_ICON2_HORZ_VERT_POSN 0x12u /* XC/XL */ +#define LCD_ICON2_HORZ_VERT_OFF 0x13u /* XC/XL */ +#define LCD_MISC_CNTL 0x14u /* XC/XL */ +#define BL_MOD_LEVEL 0x000000fful +#define BIAS_MOD_LEVEL 0x0000ff00ul +#define BLMOD_EN 0x00010000ul +#define BIASMOD_EN 0x00020000ul +/* ? 0x00040000ul */ +#define PWRSEQ_MODE 0x00080000ul +#define APC_EN 0x00100000ul +#define MONITOR_DET_EN 0x00200000ul +#define FORCE_DAC_DATA_SEL_X 0x00c00000ul +#define FORCE_DAC_DATA_X 0xff000000ul +#define LCD_TMDS_CNTL 0x15u /* XC/XL */ +#define LCD_TMDS_SYNC_CHAR_SETA 0x16u /* XC/XL */ +#define LCD_TMDS_SYNC_CHAR_SETB 0x17u /* XC/XL */ +#define LCD_TMDS_SRC 0x18u /* XC/XL */ +#define LCD_PLTSTBLK_CNTL 0x19u /* XC/XL */ +#define LCD_SYNC_GEN_CNTL 0x1au /* XC/XL */ +#define LCD_PATTERN_GEN_SEED 0x1bu /* XC/XL */ +#define LCD_APC_CNTL 0x1cu /* XC/XL */ +#define LCD_POWER_MANAGEMENT_2 0x1du /* XC/XL */ +#define LCD_XCLK_DISP_PM_EN 0x00000001ul +#define LCD_XCLK_DISP2_PM_EN 0x00000002ul /* Mobility */ +#define LCD_XCLK_VID_PM_EN 0x00000004ul +#define LCD_XCLK_SCL_PM_EN 0x00000008ul +#define LCD_XCLK_GUI_PM_EN 0x00000010ul +#define LCD_XCLK_SUB_PM_EN 0x00000020ul +/* ? 0x000000c0ul */ +#define LCD_MCLK_PM_EN 0x00000100ul +#define LCD_SS_EN 0x00000200ul +#define LCD_BLON_DIGON_EN 0x00000400ul +/* ? 0x00000800ul */ +#define LCD_PM_DYN_XCLK_SYNC 0x00003000ul +#define LCD_SEL_W4MS 0x00004000ul +/* ? 0x00008000ul */ +#define LCD_PM_DYN_XCLK_EN 0x00010000ul +#define LCD_PM_XCLK_ALWAYS 0x00020000ul +#define LCD_PM_DYN_XCLK_STATUS 0x00040000ul +#define LCD_PCI_ACC_DIS 0x00080000ul +#define LCD_PM_DYN_XCLK_DISP 0x00100000ul +#define LCD_PM_DYN_XCLK_DISP2 0x00200000ul /* Mobility */ +#define LCD_PM_DYN_XCLK_VID 0x00400000ul +#define LCD_PM_DYN_XCLK_HFB 0x00800000ul +#define LCD_PM_DYN_XCLK_SCL 0x01000000ul +#define LCD_PM_DYN_XCLK_SUB 0x02000000ul +#define LCD_PM_DYN_XCLK_GUI 0x04000000ul +#define LCD_PM_DYN_XCLK_HOST 0x08000000ul +/* ? 0xf0000000ul */ +#define LCD_PRI_ERR_PATTERN 0x1eu /* XC/XL */ +#define LCD_CUR_ERR_PATTERN 0x1fu /* XC/XL */ +#define LCD_PLTSTBLK_RPT 0x20u /* XC/XL */ +#define LCD_SYNC_RPT 0x21u /* XC/XL */ +#define LCD_CRC_PATTERN_RPT 0x22u /* XC/XL */ +#define LCD_PL_TRANSMITTER_CNTL 0x23u /* XC/XL */ +#define LCD_PL_PLL_CNTL 0x24u /* XC/XL */ +#define LCD_ALPHA_BLENDING 0x25u /* XC/XL */ +#define LCD_PORTRAIT_GEN_CNTL 0x26u /* XC/XL */ +#define LCD_APC_CTRL_IO 0x27u /* XC/XL */ +#define LCD_TEST_IO 0x28u /* XC/XL */ +/* ? 0x29u */ +#define LCD_DP1_MEM_ACCESS 0x2au /* XC/XL */ +#define LCD_DP0_MEM_ACCESS 0x2bu /* XC/XL */ +#define LCD_DP0_DEBUG_A 0x2cu /* XC/XL */ +#define LCD_DP0_DEBUG_B 0x2du /* XC/XL */ +#define LCD_DP1_DEBUG_A 0x2eu /* XC/XL */ +#define LCD_DP1_DEBUG_B 0x2fu /* XC/XL */ +#define LCD_DPCTRL_DEBUG_A 0x30u /* XC/XL */ +#define LCD_DPCTRL_DEBUG_B 0x31u /* XC/XL */ +#define LCD_MEMBLK_DEBUG 0x32u /* XC/XL */ +#define LCD_APC_LUT_AB 0x33u /* XC/XL */ +#define LCD_APC_LUT_CD 0x34u /* XC/XL */ +#define LCD_APC_LUT_EF 0x35u /* XC/XL */ +#define LCD_APC_LUT_GH 0x36u /* XC/XL */ +#define LCD_APC_LUT_IJ 0x37u /* XC/XL */ +#define LCD_APC_LUT_KL 0x38u /* XC/XL */ +#define LCD_APC_LUT_MN 0x39u /* XC/XL */ +#define LCD_APC_LUT_OP 0x3au /* XC/XL */ +/* ? 0x3bu */ +/* ? 0x3cu */ +/* ? 0x3du */ +/* ? 0x3eu */ +/* ? 0x3fu */ + +/* Definitions for an LTPro's TV registers */ +/* ? 0x00u */ +/* ? 0x01u */ +/* ? 0x02u */ +/* ? 0x03u */ +/* ? 0x04u */ +/* ? 0x05u */ +/* ? 0x06u */ +/* ? 0x07u */ +/* ? 0x08u */ +/* ? 0x09u */ +/* ? 0x0au */ +/* ? 0x0bu */ +/* ? 0x0cu */ +/* ? 0x0du */ +/* ? 0x0eu */ +/* ? 0x0fu */ +#define TV_MASTER_CNTL 0x10u +/* ? 0x11u */ +#define TV_RGB_CNTL 0x12u +/* ? 0x13u */ +#define TV_SYNC_CNTL 0x14u +/* ? 0x15u */ +/* ? 0x16u */ +/* ? 0x17u */ +/* ? 0x18u */ +/* ? 0x19u */ +/* ? 0x1au */ +/* ? 0x1bu */ +/* ? 0x1cu */ +/* ? 0x1du */ +/* ? 0x1eu */ +/* ? 0x1fu */ +#define TV_HTOTAL 0x20u +#define TV_HDISP 0x21u +#define TV_HSIZE 0x22u +#define TV_HSTART 0x23u +#define TV_HCOUNT 0x24u +#define TV_VTOTAL 0x25u +#define TV_VDISP 0x26u +#define TV_VCOUNT 0x27u +#define TV_FTOTAL 0x28u +#define TV_FCOUNT 0x29u +#define TV_FRESTART 0x2au +#define TV_HRESTART 0x2bu +#define TV_VRESTART 0x2cu +/* ? 0x2du */ +/* ? 0x2eu */ +/* ? 0x2fu */ +/* ? 0x30u */ +/* ? 0x31u */ +/* ? 0x32u */ +/* ? 0x33u */ +/* ? 0x34u */ +/* ? 0x35u */ +/* ? 0x36u */ +/* ? 0x37u */ +/* ? 0x38u */ +/* ? 0x39u */ +/* ? 0x3au */ +/* ? 0x3bu */ +/* ? 0x3cu */ +/* ? 0x3du */ +/* ? 0x3eu */ +/* ? 0x3fu */ +/* ? 0x40u */ +/* ? 0x41u */ +/* ? 0x42u */ +/* ? 0x43u */ +/* ? 0x44u */ +/* ? 0x45u */ +/* ? 0x46u */ +/* ? 0x47u */ +/* ? 0x48u */ +/* ? 0x49u */ +/* ? 0x4au */ +/* ? 0x4bu */ +/* ? 0x4cu */ +/* ? 0x4du */ +/* ? 0x4eu */ +/* ? 0x4fu */ +/* ? 0x50u */ +/* ? 0x51u */ +/* ? 0x52u */ +/* ? 0x53u */ +/* ? 0x54u */ +/* ? 0x55u */ +/* ? 0x56u */ +/* ? 0x57u */ +/* ? 0x58u */ +/* ? 0x59u */ +/* ? 0x5au */ +/* ? 0x5bu */ +/* ? 0x5cu */ +/* ? 0x5du */ +/* ? 0x5eu */ +/* ? 0x5fu */ +#define TV_HOST_READ_DATA 0x60u +#define TV_HOST_WRITE_DATA 0x61u +#define TV_HOST_RD_WT_CNTL 0x62u +/* ? 0x63u */ +/* ? 0x64u */ +/* ? 0x65u */ +/* ? 0x66u */ +/* ? 0x67u */ +/* ? 0x68u */ +/* ? 0x69u */ +/* ? 0x6au */ +/* ? 0x6bu */ +/* ? 0x6cu */ +/* ? 0x6du */ +/* ? 0x6eu */ +/* ? 0x6fu */ +#define TV_VSCALER_CNTL 0x70u +#define TV_TIMING_CNTL 0x71u +#define TV_GAMMA_CNTL 0x72u +#define TV_Y_FALL_CNTL 0x73u +#define TV_Y_RISE_CNTL 0x74u +#define TV_Y_SAW_TOOTH_CNTL 0x75u +/* ? 0x76u */ +/* ? 0x77u */ +/* ? 0x78u */ +/* ? 0x79u */ +/* ? 0x7au */ +/* ? 0x7bu */ +/* ? 0x7cu */ +/* ? 0x7du */ +/* ? 0x7eu */ +/* ? 0x7fu */ +#define TV_MODULATOR_CNTL1 0x80u +#define TV_MODULATOR_CNTL2 0x81u +/* ? 0x82u */ +/* ? 0x83u */ +/* ? 0x84u */ +/* ? 0x85u */ +/* ? 0x86u */ +/* ? 0x87u */ +/* ? 0x88u */ +/* ? 0x89u */ +/* ? 0x8au */ +/* ? 0x8bu */ +/* ? 0x8cu */ +/* ? 0x8du */ +/* ? 0x8eu */ +/* ? 0x8fu */ +#define TV_PRE_DAC_MUX_CNTL 0x90u +/* ? 0x91u */ +/* ? 0x92u */ +/* ? 0x93u */ +/* ? 0x94u */ +/* ? 0x95u */ +/* ? 0x96u */ +/* ? 0x97u */ +/* ? 0x98u */ +/* ? 0x99u */ +/* ? 0x9au */ +/* ? 0x9bu */ +/* ? 0x9cu */ +/* ? 0x9du */ +/* ? 0x9eu */ +/* ? 0x9fu */ +#define TV_DAC_CNTL 0xa0u +/* ? 0xa1u */ +/* ? 0xa2u */ +/* ? 0xa3u */ +/* ? 0xa4u */ +/* ? 0xa5u */ +/* ? 0xa6u */ +/* ? 0xa7u */ +/* ? 0xa8u */ +/* ? 0xa9u */ +/* ? 0xaau */ +/* ? 0xabu */ +/* ? 0xacu */ +/* ? 0xadu */ +/* ? 0xaeu */ +/* ? 0xafu */ +#define TV_CRC_CNTL 0xb0u +#define TV_VIDEO_PORT_SIG 0xb1u +/* ? 0xb2u */ +/* ? 0xb3u */ +/* ? 0xb4u */ +/* ? 0xb5u */ +/* ? 0xb6u */ +/* ? 0xb7u */ +#define TV_VBI_CC_CNTL 0xb8u +#define TV_VBI_EDS_CNTL 0xb9u +#define TV_VBI_20BIT_CNTL 0xbau +/* ? 0xbbu */ +/* ? 0xbcu */ +#define TV_VBI_DTO_CNTL 0xbdu +#define TV_VBI_LEVEL_CNTL 0xbeu +/* ? 0xbfu */ +#define TV_UV_ADR 0xc0u +#define TV_FIFO_TEST_CNTL 0xc1u +/* ? 0xc2u */ +/* ? 0xc3u */ +/* ? 0xc4u */ +/* ? 0xc5u */ +/* ? 0xc6u */ +/* ? 0xc7u */ +/* ? 0xc8u */ +/* ? 0xc9u */ +/* ? 0xcau */ +/* ? 0xcbu */ +/* ? 0xccu */ +/* ? 0xcdu */ +/* ? 0xceu */ +/* ? 0xcfu */ +/* ? 0xd0u */ +/* ? 0xd1u */ +/* ? 0xd2u */ +/* ? 0xd3u */ +/* ? 0xd4u */ +/* ? 0xd5u */ +/* ? 0xd6u */ +/* ? 0xd7u */ +/* ? 0xd8u */ +/* ? 0xd9u */ +/* ? 0xdau */ +/* ? 0xdbu */ +/* ? 0xdcu */ +/* ? 0xddu */ +/* ? 0xdeu */ +/* ? 0xdfu */ +/* ? 0xe0u */ +/* ? 0xe1u */ +/* ? 0xe2u */ +/* ? 0xe3u */ +/* ? 0xe4u */ +/* ? 0xe5u */ +/* ? 0xe6u */ +/* ? 0xe7u */ +/* ? 0xe8u */ +/* ? 0xe9u */ +/* ? 0xeau */ +/* ? 0xebu */ +/* ? 0xecu */ +/* ? 0xedu */ +/* ? 0xeeu */ +/* ? 0xefu */ +/* ? 0xf0u */ +/* ? 0xf1u */ +/* ? 0xf2u */ +/* ? 0xf3u */ +/* ? 0xf4u */ +/* ? 0xf5u */ +/* ? 0xf6u */ +/* ? 0xf7u */ +/* ? 0xf8u */ +/* ? 0xf9u */ +/* ? 0xfau */ +/* ? 0xfbu */ +/* ? 0xfcu */ +/* ? 0xfdu */ +/* ? 0xfeu */ +/* ? 0xffu */ + +/* Miscellaneous */ + +/* Current X, Y & Dest X, Y mask */ +#define COORD_MASK 0x07ffu + +/* Pixel widths */ +#define PIX_WIDTH_1BPP 0x00u +#define PIX_WIDTH_4BPP 0x01u /* CRTC2: 8bpp */ +#define PIX_WIDTH_8BPP 0x02u /* CRTC2: Undefined */ +#define PIX_WIDTH_15BPP 0x03u +#define PIX_WIDTH_16BPP 0x04u +#define PIX_WIDTH_24BPP 0x05u +#define PIX_WIDTH_32BPP 0x06u +#define PIX_WIDTH_YUV422 0x07u /* CRTC2 only */ + +/* Source definitions */ +#define SRC_BKGD 0x00u +#define SRC_FRGD 0x01u +#define SRC_HOST 0x02u +#define SRC_BLIT 0x03u +#define SRC_PATTERN 0x04u +#define SRC_SCALER_3D 0x05u +/* ? 0x06u */ +/* ? 0x07u */ + +/* The Mixes */ +#define MIX_MASK 0x001fu + +#define MIX_NOT_DST 0x0000u +#define MIX_0 0x0001u +#define MIX_1 0x0002u +#define MIX_DST 0x0003u +#define MIX_NOT_SRC 0x0004u +#define MIX_XOR 0x0005u +#define MIX_XNOR 0x0006u +#define MIX_SRC 0x0007u +#define MIX_NAND 0x0008u +#define MIX_NOT_SRC_OR_DST 0x0009u +#define MIX_SRC_OR_NOT_DST 0x000au +#define MIX_OR 0x000bu +#define MIX_AND 0x000cu +#define MIX_SRC_AND_NOT_DST 0x000du +#define MIX_NOT_SRC_AND_DST 0x000eu +#define MIX_NOR 0x000fu + +#define MIX_MIN 0x0010u +#define MIX_DST_MINUS_SRC 0x0011u +#define MIX_SRC_MINUS_DST 0x0012u +#define MIX_PLUS 0x0013u +#define MIX_MAX 0x0014u +#define MIX_HALF__DST_MINUS_SRC 0x0015u +#define MIX_HALF__SRC_MINUS_DST 0x0016u +#define MIX_AVERAGE 0x0017u +#define MIX_DST_MINUS_SRC_SAT 0x0018u +#define MIX_SRC_MINUS_DST_SAT 0x001au +#define MIX_HALF__DST_MINUS_SRC_SAT 0x001cu +#define MIX_HALF__SRC_MINUS_DST_SAT 0x001eu +#define MIX_AVERAGE_SAT 0x001fu +#define MIX_FN_PAINT MIX_SRC + + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/vidix/mach64_vid.c Sun Apr 01 00:02:43 2007 +0000 @@ -0,0 +1,1066 @@ +/* + mach64_vid - VIDIX based video driver for Mach64 and 3DRage chips + Copyrights 2002 Nick Kurshev. This file is based on sources from + GATOS (gatos.sf.net) and X11 (www.xfree86.org) + Licence: GPL + WARNING: THIS DRIVER IS IN BETTA STAGE +*/ +#include <errno.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <math.h> +#include <inttypes.h> +#include <fcntl.h> + +#include "../config.h" +#include "../libavutil/common.h" +#include "../mpbswap.h" +#include "vidix.h" +#include "fourcc.h" +#include "../libdha/libdha.h" +#include "../libdha/pci_ids.h" +#include "../libdha/pci_names.h" + +#include "mach64.h" +#include "../version.h" + +#define UNUSED(x) ((void)(x)) /**< Removes warning about unused arguments */ + +static void *mach64_mmio_base = 0; +static void *mach64_mem_base = 0; +static int32_t mach64_overlay_offset = 0; +static uint32_t mach64_ram_size = 0; +static uint32_t mach64_buffer_base[10][3]; +static int num_mach64_buffers=-1; +static int supports_planar=0; +static int supports_lcd_v_stretch=0; + +pciinfo_t pci_info; +static int probed = 0; +static int __verbose = 0; + +#define VERBOSE_LEVEL 1 + +typedef struct bes_registers_s +{ + /* base address of yuv framebuffer */ + uint32_t yuv_base; + uint32_t fourcc; + /* YUV BES registers */ + uint32_t reg_load_cntl; + uint32_t scale_inc; + uint32_t y_x_start; + uint32_t y_x_end; + uint32_t vid_buf_pitch; + uint32_t height_width; + + uint32_t scale_cntl; + uint32_t exclusive_horz; + uint32_t auto_flip_cntl; + uint32_t filter_cntl; + uint32_t key_cntl; + uint32_t test; + /* Configurable stuff */ + + int brightness; + int saturation; + + int ckey_on; + uint32_t graphics_key_clr; + uint32_t graphics_key_msk; + + int deinterlace_on; + uint32_t deinterlace_pattern; + +} bes_registers_t; + +static bes_registers_t besr; + +typedef struct video_registers_s +{ + const char * sname; + uint32_t name; + uint32_t value; +}video_registers_t; + +static bes_registers_t besr; + +/* Graphic keys */ +static vidix_grkey_t mach64_grkey; + +#define DECLARE_VREG(name) { #name, name, 0 } +static video_registers_t vregs[] = +{ + DECLARE_VREG(OVERLAY_SCALE_INC), + DECLARE_VREG(OVERLAY_Y_X_START), + DECLARE_VREG(OVERLAY_Y_X_END), + DECLARE_VREG(OVERLAY_SCALE_CNTL), + DECLARE_VREG(OVERLAY_EXCLUSIVE_HORZ), + DECLARE_VREG(OVERLAY_EXCLUSIVE_VERT), + DECLARE_VREG(OVERLAY_TEST), + DECLARE_VREG(SCALER_BUF_PITCH), + DECLARE_VREG(SCALER_HEIGHT_WIDTH), + DECLARE_VREG(SCALER_BUF0_OFFSET), + DECLARE_VREG(SCALER_BUF0_OFFSET_U), + DECLARE_VREG(SCALER_BUF0_OFFSET_V), + DECLARE_VREG(SCALER_BUF1_OFFSET), + DECLARE_VREG(SCALER_BUF1_OFFSET_U), + DECLARE_VREG(SCALER_BUF1_OFFSET_V), + DECLARE_VREG(SCALER_H_COEFF0), + DECLARE_VREG(SCALER_H_COEFF1), + DECLARE_VREG(SCALER_H_COEFF2), + DECLARE_VREG(SCALER_H_COEFF3), + DECLARE_VREG(SCALER_H_COEFF4), + DECLARE_VREG(SCALER_COLOUR_CNTL), + DECLARE_VREG(SCALER_THRESHOLD), + DECLARE_VREG(VIDEO_FORMAT), + DECLARE_VREG(VIDEO_CONFIG), + DECLARE_VREG(VIDEO_SYNC_TEST), + DECLARE_VREG(VIDEO_SYNC_TEST_B) +}; + +/* have to restore it on exit */ +static uint32_t SAVED_OVERLAY_GRAPHICS_KEY_CLR; + +/* VIDIX exports */ + +/* MMIO space*/ +#define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ)))) +#define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL + +#define INREG8(addr) GETREG(uint8_t,(uint8_t *)mach64_mmio_base,((addr)^0x100)<<2) +#define OUTREG8(addr,val) SETREG(uint8_t,(uint8_t *)mach64_mmio_base,((addr)^0x100)<<2,val) + +static inline uint32_t INREG (uint32_t addr) { + uint32_t tmp = GETREG(uint32_t,(uint8_t *)mach64_mmio_base,((addr)^0x100)<<2); + return le2me_32(tmp); +} +#define OUTREG(addr,val) SETREG(uint32_t,(uint8_t *)mach64_mmio_base,((addr)^0x100)<<2,le2me_32(val)) + +#define OUTREGP(addr,val,mask) \ + do { \ + unsigned int _tmp = INREG(addr); \ + _tmp &= (mask); \ + _tmp |= (val); \ + OUTREG(addr, _tmp); \ + } while (0) + +static __inline__ int ATIGetMach64LCDReg(int _Index) +{ + OUTREG8(LCD_INDEX, _Index); + return INREG(LCD_DATA); +} + +static __inline__ uint32_t INPLL(uint32_t addr) +{ + uint32_t res; + uint32_t in; + + in= INREG(CLOCK_CNTL); + in &= ~((PLL_WR_EN | PLL_ADDR)); //clean some stuff + OUTREG(CLOCK_CNTL, in | (addr<<10)); + + /* read the register value */ + res = (INREG(CLOCK_CNTL)>>16)&0xFF; + return res; +} + +static __inline__ void OUTPLL(uint32_t addr,uint32_t val) +{ +//FIXME buggy but its not used + /* write addr byte */ + OUTREG8(CLOCK_CNTL + 1, (addr << 2) | PLL_WR_EN); + /* write the register value */ + OUTREG(CLOCK_CNTL + 2, val); + OUTREG8(CLOCK_CNTL + 1, (addr << 2) & ~PLL_WR_EN); +} + +#define OUTPLLP(addr,val,mask) \ + do { \ + unsigned int _tmp = INPLL(addr); \ + _tmp &= (mask); \ + _tmp |= (val); \ + OUTPLL(addr, _tmp); \ + } while (0) + +static void mach64_fifo_wait(unsigned n) +{ + while ((INREG(FIFO_STAT) & 0xffff) > ((uint32_t)(0x8000 >> n))); +} + +static void mach64_wait_for_idle( void ) +{ + mach64_fifo_wait(16); + while ((INREG(GUI_STAT) & 1)!= 0); +} + +static void mach64_wait_vsync( void ) +{ + int i; + + for(i=0; i<2000000; i++) + if( (INREG(CRTC_INT_CNTL)&CRTC_VBLANK)==0 ) break; + for(i=0; i<2000000; i++) + if( (INREG(CRTC_INT_CNTL)&CRTC_VBLANK) ) break; + +} + +static vidix_capability_t mach64_cap = +{ + "BES driver for Mach64/3DRage cards", + "Nick Kurshev and Michael Niedermayer", + TYPE_OUTPUT, + { 0, 0, 0, 0 }, + 2048, + 2048, + 4, + 4, + -1, + FLAG_UPSCALER|FLAG_DOWNSCALER, + VENDOR_ATI, + -1, + { 0, 0, 0, 0 } +}; + +static uint32_t mach64_vid_get_dbpp( void ) +{ + uint32_t dbpp,retval; + dbpp = (INREG(CRTC_GEN_CNTL)>>8)& 0x7; + switch(dbpp) + { + case 1: retval = 4; break; + case 2: retval = 8; break; + case 3: retval = 15; break; + case 4: retval = 16; break; + case 5: retval = 24; break; + default: retval=32; break; + } + return retval; +} + +static int mach64_is_dbl_scan( void ) +{ + return INREG(CRTC_GEN_CNTL) & CRTC_DBL_SCAN_EN; +} + +static int mach64_is_interlace( void ) +{ + return INREG(CRTC_GEN_CNTL) & CRTC_INTERLACE_EN; +} + +static uint32_t mach64_get_xres( void ) +{ + /* FIXME: currently we extract that from CRTC!!!*/ + uint32_t xres,h_total; + h_total = INREG(CRTC_H_TOTAL_DISP); + xres = (h_total >> 16) & 0xffff; + return (xres + 1)*8; +} + +static uint32_t mach64_get_yres( void ) +{ + /* FIXME: currently we extract that from CRTC!!!*/ + uint32_t yres,v_total; + v_total = INREG(CRTC_V_TOTAL_DISP); + yres = (v_total >> 16) & 0xffff; + return yres + 1; +} + +// returns the verical stretch factor in 16.16 +static int mach64_get_vert_stretch(void) +{ + int lcd_index; + int vert_stretching; + int ext_vert_stretch; + int ret; + int yres= mach64_get_yres(); + + if(!supports_lcd_v_stretch){ + if(__verbose>0) printf("[mach64] vertical stretching not supported\n"); + return 1<<16; + } + + lcd_index= INREG(LCD_INDEX); + + vert_stretching= ATIGetMach64LCDReg(LCD_VERT_STRETCHING); + if(!(vert_stretching&VERT_STRETCH_EN)) ret= 1<<16; + else + { + int panel_size; + + ext_vert_stretch= ATIGetMach64LCDReg(LCD_EXT_VERT_STRETCH); + panel_size= (ext_vert_stretch&VERT_PANEL_SIZE)>>11; + panel_size++; + + ret= ((yres<<16) + (panel_size>>1))/panel_size; + } + +// lcd_gen_ctrl = ATIGetMach64LCDReg(LCD_GEN_CNTL); + + OUTREG(LCD_INDEX, lcd_index); + + if(__verbose>0) printf("[mach64] vertical stretching factor= %d\n", ret); + + return ret; +} + +static void mach64_vid_make_default(void) +{ + mach64_fifo_wait(5); + OUTREG(SCALER_COLOUR_CNTL,0x00101000); + + besr.ckey_on=0; + besr.graphics_key_msk=0; + besr.graphics_key_clr=0; + + OUTREG(OVERLAY_GRAPHICS_KEY_MSK, besr.graphics_key_msk); + OUTREG(OVERLAY_GRAPHICS_KEY_CLR, besr.graphics_key_clr); + OUTREG(OVERLAY_KEY_CNTL,VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_EQ|CMP_MIX_AND); + +} + +static void mach64_vid_dump_regs( void ) +{ + size_t i; + printf("[mach64] *** Begin of DRIVER variables dump ***\n"); + printf("[mach64] mach64_mmio_base=%p\n",mach64_mmio_base); + printf("[mach64] mach64_mem_base=%p\n",mach64_mem_base); + printf("[mach64] mach64_overlay_off=%08X\n",mach64_overlay_offset); + printf("[mach64] mach64_ram_size=%08X\n",mach64_ram_size); + printf("[mach64] video mode: %ux%u@%u\n",mach64_get_xres(),mach64_get_yres(),mach64_vid_get_dbpp()); + printf("[mach64] *** Begin of OV0 registers dump ***\n"); + for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) + { + mach64_wait_for_idle(); + printf("[mach64] %s = %08X\n",vregs[i].sname,INREG(vregs[i].name)); + } + printf("[mach64] *** End of OV0 registers dump ***\n"); +} + + +unsigned int vixGetVersion(void) +{ + return(VIDIX_VERSION); +} + +static unsigned short ati_card_ids[] = +{ + DEVICE_ATI_215CT_MACH64_CT, + DEVICE_ATI_210888CX_MACH64_CX, + DEVICE_ATI_210888ET_MACH64_ET, + DEVICE_ATI_MACH64_VT, + DEVICE_ATI_210888GX_MACH64_GX, + DEVICE_ATI_264LT_MACH64_LT, + DEVICE_ATI_264VT_MACH64_VT, + DEVICE_ATI_264VT3_MACH64_VT3, + DEVICE_ATI_264VT4_MACH64_VT4, + /**/ + DEVICE_ATI_3D_RAGE_PRO, + DEVICE_ATI_3D_RAGE_PRO2, + DEVICE_ATI_3D_RAGE_PRO3, + DEVICE_ATI_3D_RAGE_PRO4, + DEVICE_ATI_RAGE_XC, + DEVICE_ATI_RAGE_XL_AGP, + DEVICE_ATI_RAGE_XC_AGP, + DEVICE_ATI_RAGE_XL, + DEVICE_ATI_3D_RAGE_PRO5, + DEVICE_ATI_3D_RAGE_PRO6, + DEVICE_ATI_RAGE_XL2, + DEVICE_ATI_RAGE_XC2, + DEVICE_ATI_3D_RAGE_I_II, + DEVICE_ATI_3D_RAGE_II, + DEVICE_ATI_3D_RAGE_IIC, + DEVICE_ATI_3D_RAGE_IIC2, + DEVICE_ATI_3D_RAGE_IIC3, + DEVICE_ATI_3D_RAGE_IIC4, + DEVICE_ATI_3D_RAGE_LT, + DEVICE_ATI_3D_RAGE_LT2, + DEVICE_ATI_3D_RAGE_LT_G, + DEVICE_ATI_3D_RAGE_LT3, + DEVICE_ATI_RAGE_MOBILITY_P_M, + DEVICE_ATI_RAGE_MOBILITY_L, + DEVICE_ATI_3D_RAGE_LT4, + DEVICE_ATI_3D_RAGE_LT5, + DEVICE_ATI_RAGE_MOBILITY_P_M2, + DEVICE_ATI_RAGE_MOBILITY_L2 +}; + +static int find_chip(unsigned chip_id) +{ + unsigned i; + for(i = 0;i < sizeof(ati_card_ids)/sizeof(unsigned short);i++) + { + if(chip_id == ati_card_ids[i]) return i; + } + return -1; +} + +int vixProbe(int verbose,int force) +{ + pciinfo_t lst[MAX_PCI_DEVICES]; + unsigned i,num_pci; + int err; + __verbose = verbose; + err = pci_scan(lst,&num_pci); + if(err) + { + printf("[mach64] Error occurred during pci scan: %s\n",strerror(err)); + return err; + } + else + { + err = ENXIO; + for(i=0;i<num_pci;i++) + { + if(lst[i].vendor == VENDOR_ATI) + { + int idx; + const char *dname; + idx = find_chip(lst[i].device); + if(idx == -1 && force == PROBE_NORMAL) continue; + dname = pci_device_name(VENDOR_ATI,lst[i].device); + dname = dname ? dname : "Unknown chip"; + printf("[mach64] Found chip: %s\n",dname); + if ((lst[i].command & PCI_COMMAND_IO) == 0) + { + printf("[mach64] Device is disabled, ignoring\n"); + continue; + } + if(force > PROBE_NORMAL) + { + printf("[mach64] Driver was forced. Was found %sknown chip\n",idx == -1 ? "un" : ""); + if(idx == -1) + printf("[mach64] Assuming it as Mach64\n"); + } + mach64_cap.device_id = lst[i].device; + err = 0; + memcpy(&pci_info,&lst[i],sizeof(pciinfo_t)); + probed=1; + break; + } + } + } + if(err && verbose) printf("[mach64] Can't find chip\n"); + return err; +} + +static void reset_regs( void ) +{ + size_t i; + for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) + { + mach64_fifo_wait(2); + OUTREG(vregs[i].name,0); + } +} + + +int vixInit(void) +{ + int err; + if(!probed) + { + printf("[mach64] Driver was not probed but is being initializing\n"); + return EINTR; + } + if(__verbose>0) printf("[mach64] version %s\n", VERSION); + + if((mach64_mmio_base = map_phys_mem(pci_info.base2,0x1000))==(void *)-1) return ENOMEM; + mach64_wait_for_idle(); + mach64_ram_size = INREG(MEM_CNTL) & CTL_MEM_SIZEB; + if (mach64_ram_size < 8) mach64_ram_size = (mach64_ram_size + 1) * 512; + else if (mach64_ram_size < 12) mach64_ram_size = (mach64_ram_size - 3) * 1024; + else mach64_ram_size = (mach64_ram_size - 7) * 2048; + mach64_ram_size *= 0x400; /* KB -> bytes */ + if((mach64_mem_base = map_phys_mem(pci_info.base0,mach64_ram_size))==(void *)-1) return ENOMEM; + memset(&besr,0,sizeof(bes_registers_t)); + printf("[mach64] Video memory = %uMb\n",mach64_ram_size/0x100000); + err = mtrr_set_type(pci_info.base0,mach64_ram_size,MTRR_TYPE_WRCOMB); + if(!err) printf("[mach64] Set write-combining type of video memory\n"); + + /* save this */ + mach64_wait_for_idle(); + SAVED_OVERLAY_GRAPHICS_KEY_CLR = INREG(OVERLAY_GRAPHICS_KEY_CLR); + + /* check if planar formats are supported */ + supports_planar=0; + mach64_wait_for_idle(); + mach64_fifo_wait(2); + if(INREG(SCALER_BUF0_OFFSET_U)) supports_planar=1; + else + { + OUTREG(SCALER_BUF0_OFFSET_U, -1); + + mach64_wait_vsync(); + mach64_wait_for_idle(); + mach64_fifo_wait(2); + + if(INREG(SCALER_BUF0_OFFSET_U)) supports_planar=1; + } + if(supports_planar) printf("[mach64] Planar YUV formats are supported :)\n"); + else printf("[mach64] Planar YUV formats are not supported :(\n"); + + if( mach64_cap.device_id==DEVICE_ATI_RAGE_MOBILITY_P_M + || mach64_cap.device_id==DEVICE_ATI_RAGE_MOBILITY_P_M2 + || mach64_cap.device_id==DEVICE_ATI_RAGE_MOBILITY_L + || mach64_cap.device_id==DEVICE_ATI_RAGE_MOBILITY_L2) + supports_lcd_v_stretch=1; + else + supports_lcd_v_stretch=0; + + reset_regs(); + mach64_vid_make_default(); + + if(__verbose > VERBOSE_LEVEL) mach64_vid_dump_regs(); + return 0; +} + +void vixDestroy(void) +{ + /*restore this*/ + mach64_wait_for_idle(); + OUTREG(OVERLAY_GRAPHICS_KEY_CLR,SAVED_OVERLAY_GRAPHICS_KEY_CLR); + + unmap_phys_mem(mach64_mem_base,mach64_ram_size); + unmap_phys_mem(mach64_mmio_base,0x1000); +} + +int vixGetCapability(vidix_capability_t *to) +{ + memcpy(to, &mach64_cap, sizeof(vidix_capability_t)); + return 0; +} + +static unsigned mach64_query_pitch(unsigned fourcc,const vidix_yuv_t *spitch) +{ + unsigned pitch,spy,spv,spu; + spy = spv = spu = 0; + switch(spitch->y) + { + case 16: + case 32: + case 64: + case 128: + case 256: spy = spitch->y; break; + default: break; + } + switch(spitch->u) + { + case 16: + case 32: + case 64: + case 128: + case 256: spu = spitch->u; break; + default: break; + } + switch(spitch->v) + { + case 16: + case 32: + case 64: + case 128: + case 256: spv = spitch->v; break; + default: break; + } + switch(fourcc) + { + /* 4:2:0 */ + case IMGFMT_IYUV: + case IMGFMT_YV12: + case IMGFMT_I420: + if(spy > 16 && spu == spy/2 && spv == spy/2) pitch = spy; + else pitch = 32; + break; + case IMGFMT_YVU9: + if(spy > 32 && spu == spy/4 && spv == spy/4) pitch = spy; + else pitch = 64; + break; + default: + if(spy >= 16) pitch = spy; + else pitch = 16; + break; + } + return pitch; +} + +static void mach64_compute_framesize(vidix_playback_t *info) +{ + unsigned pitch,awidth; + pitch = mach64_query_pitch(info->fourcc,&info->src.pitch); + switch(info->fourcc) + { + case IMGFMT_I420: + case IMGFMT_YV12: + case IMGFMT_IYUV: + awidth = (info->src.w + (pitch-1)) & ~(pitch-1); + info->frame_size = awidth*(info->src.h+info->src.h/2); + break; + case IMGFMT_YVU9: + awidth = (info->src.w + (pitch-1)) & ~(pitch-1); + info->frame_size = awidth*(info->src.h+info->src.h/8); + break; +// case IMGFMT_RGB32: + case IMGFMT_BGR32: + awidth = (info->src.w*4 + (pitch-1)) & ~(pitch-1); + info->frame_size = (awidth*info->src.h); + break; + /* YUY2 YVYU, RGB15, RGB16 */ + default: + awidth = (info->src.w*2 + (pitch-1)) & ~(pitch-1); + info->frame_size = (awidth*info->src.h); + break; + } + info->frame_size+=256; // so we have some space for alignment & such + info->frame_size&=~16; +} + +static void mach64_vid_stop_video( void ) +{ + mach64_fifo_wait(14); + OUTREG(OVERLAY_SCALE_CNTL, 0x80000000); + OUTREG(OVERLAY_EXCLUSIVE_HORZ, 0); + OUTREG(OVERLAY_EXCLUSIVE_VERT, 0); + OUTREG(SCALER_H_COEFF0, 0x00002000); + OUTREG(SCALER_H_COEFF1, 0x0D06200D); + OUTREG(SCALER_H_COEFF2, 0x0D0A1C0D); + OUTREG(SCALER_H_COEFF3, 0x0C0E1A0C); + OUTREG(SCALER_H_COEFF4, 0x0C14140C); + OUTREG(VIDEO_FORMAT, 0xB000B); + OUTREG(OVERLAY_TEST, 0x0); +} + +static void mach64_vid_display_video( void ) +{ + uint32_t vf; + mach64_fifo_wait(14); + + OUTREG(OVERLAY_Y_X_START, besr.y_x_start); + OUTREG(OVERLAY_Y_X_END, besr.y_x_end); + OUTREG(OVERLAY_SCALE_INC, besr.scale_inc); + OUTREG(SCALER_BUF_PITCH, besr.vid_buf_pitch); + OUTREG(SCALER_HEIGHT_WIDTH, besr.height_width); + OUTREG(SCALER_BUF0_OFFSET, mach64_buffer_base[0][0]); + OUTREG(SCALER_BUF0_OFFSET_U, mach64_buffer_base[0][1]); + OUTREG(SCALER_BUF0_OFFSET_V, mach64_buffer_base[0][2]); + OUTREG(SCALER_BUF1_OFFSET, mach64_buffer_base[0][0]); + OUTREG(SCALER_BUF1_OFFSET_U, mach64_buffer_base[0][1]); + OUTREG(SCALER_BUF1_OFFSET_V, mach64_buffer_base[0][2]); + mach64_wait_vsync(); + + mach64_fifo_wait(4); + OUTREG(OVERLAY_SCALE_CNTL, 0xC4000003); +// OVERLAY_SCALE_CNTL bits & what they seem to affect +// bit 0 no effect +// bit 1 yuv2rgb coeff related +// bit 2 horizontal interpolation if 0 +// bit 3 vertical interpolation if 0 +// bit 4 chroma encoding (0-> 128=neutral / 1-> 0->neutral) +// bit 5-6 gamma correction +// bit 7 nothing visible if set +// bit 8-27 no effect +// bit 28-31 nothing interresting just crashed my system when i played with them :( + + mach64_wait_for_idle(); + vf = INREG(VIDEO_FORMAT); + +// Bits 16-19 seem to select the format +// 0x0 dunno behaves strange +// 0x1 dunno behaves strange +// 0x2 dunno behaves strange +// 0x3 BGR15 +// 0x4 BGR16 +// 0x5 BGR16 (hmm, that need investigation, 2 BGR16 formats, i guess 1 will have only 5bits for green) +// 0x6 BGR32 +// 0x7 BGR32 with somehow mixed even / odd pixels ? +// 0x8 YYYYUVUV +// 0x9 YVU9 +// 0xA YV12 +// 0xB YUY2 +// 0xC UYVY +// 0xD UYVY (no difference is visible if i switch between C/D for every even/odd frame) +// 0xE dunno behaves strange +// 0xF dunno behaves strange +// Bit 28 all values are assumed to be 7 bit with chroma=64 for black (tested with YV12 & YUY2) +// the remaining bits seem to have no effect + + + switch(besr.fourcc) + { + /* BGR formats */ + case IMGFMT_BGR15: OUTREG(VIDEO_FORMAT, 0x00030000); break; + case IMGFMT_BGR16: OUTREG(VIDEO_FORMAT, 0x00040000); break; + case IMGFMT_BGR32: OUTREG(VIDEO_FORMAT, 0x00060000); break; + /* 4:2:0 */ + case IMGFMT_IYUV: + case IMGFMT_I420: + case IMGFMT_YV12: OUTREG(VIDEO_FORMAT, 0x000A0000); break; + + case IMGFMT_YVU9: OUTREG(VIDEO_FORMAT, 0x00090000); break; + /* 4:2:2 */ + case IMGFMT_YVYU: + case IMGFMT_UYVY: OUTREG(VIDEO_FORMAT, 0x000C0000); break; + case IMGFMT_YUY2: + default: OUTREG(VIDEO_FORMAT, 0x000B0000); break; + } + if(__verbose > VERBOSE_LEVEL) mach64_vid_dump_regs(); +} + +static int mach64_vid_init_video( vidix_playback_t *config ) +{ + uint32_t src_w,src_h,dest_w,dest_h,pitch,h_inc,v_inc,left,leftUV,top,ecp,y_pos; + int is_420,best_pitch,mpitch; + int src_offset_y, src_offset_u, src_offset_v; + unsigned int i; + + mach64_vid_stop_video(); +/* warning, if left or top are != 0 this will fail, as the framesize is too small then */ + left = config->src.x; + top = config->src.y; + src_h = config->src.h; + src_w = config->src.w; + is_420 = 0; + if(config->fourcc == IMGFMT_YV12 || + config->fourcc == IMGFMT_I420 || + config->fourcc == IMGFMT_IYUV) is_420 = 1; + best_pitch = mach64_query_pitch(config->fourcc,&config->src.pitch); + mpitch = best_pitch-1; + switch(config->fourcc) + { + case IMGFMT_YVU9: + /* 4:2:0 */ + case IMGFMT_IYUV: + case IMGFMT_YV12: + case IMGFMT_I420: pitch = (src_w + mpitch) & ~mpitch; + config->dest.pitch.y = + config->dest.pitch.u = + config->dest.pitch.v = best_pitch; + besr.vid_buf_pitch= pitch; + break; + /* RGB 4:4:4:4 */ + case IMGFMT_RGB32: + case IMGFMT_BGR32: pitch = (src_w*4 + mpitch) & ~mpitch; + config->dest.pitch.y = + config->dest.pitch.u = + config->dest.pitch.v = best_pitch; + besr.vid_buf_pitch= pitch>>2; + break; + /* 4:2:2 */ + default: /* RGB15, RGB16, YVYU, UYVY, YUY2 */ + pitch = ((src_w*2) + mpitch) & ~mpitch; + config->dest.pitch.y = + config->dest.pitch.u = + config->dest.pitch.v = best_pitch; + besr.vid_buf_pitch= pitch>>1; + break; + } + dest_w = config->dest.w; + dest_h = config->dest.h; + besr.fourcc = config->fourcc; + ecp = (INPLL(PLL_VCLK_CNTL) & PLL_ECP_DIV) >> 4; +#if 0 +{ +int i; +for(i=0; i<32; i++){ + printf("%X ", INPLL(i)); +} +} +#endif + if(__verbose>0) printf("[mach64] ecp: %d\n", ecp); + v_inc = src_h * mach64_get_vert_stretch(); + + if(mach64_is_interlace()) v_inc<<=1; + if(mach64_is_dbl_scan() ) v_inc>>=1; + v_inc>>=4; // convert 16.16 -> 20.12 + v_inc/= dest_h; + + h_inc = (src_w << (12+ecp)) / dest_w; + /* keep everything in 16.16 */ + config->offsets[0] = 0; + for(i=1; i<config->num_frames; i++) + config->offsets[i] = config->offsets[i-1] + config->frame_size; + + /*FIXME the left / top stuff is broken (= zoom a src rectangle from a larger one) + 1. the framesize isn't known as the outer src rectangle dimensions aren't known + 2. the mach64 needs aligned addresses so it can't work anyway + -> so we could shift the outer buffer to compensate that but that would mean + alignment problems for the code which writes into it + */ + + if(is_420) + { + config->offset.y= 0; + config->offset.u= (pitch*src_h + 15)&~15; + config->offset.v= (config->offset.u + (pitch*src_h>>2) + 15)&~15; + + if(besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV) + { + uint32_t tmp; + tmp = config->offset.u; + config->offset.u = config->offset.v; + config->offset.v = tmp; + } + + src_offset_y= config->offset.y + top*pitch + left; + src_offset_u= config->offset.u + (top*pitch>>2) + (left>>1); + src_offset_v= config->offset.v + (top*pitch>>2) + (left>>1); + } + else if(besr.fourcc == IMGFMT_YVU9) + { + config->offset.y= 0; + config->offset.u= (pitch*src_h + 15)&~15; + config->offset.v= (config->offset.u + (pitch*src_h>>4) + 15)&~15; + + src_offset_y= config->offset.y + top*pitch + left; + src_offset_u= config->offset.u + (top*pitch>>4) + (left>>1); + src_offset_v= config->offset.v + (top*pitch>>4) + (left>>1); + } + else if(besr.fourcc == IMGFMT_BGR32) + { + config->offset.y = config->offset.u = config->offset.v = 0; + src_offset_y= src_offset_u= src_offset_v= top*pitch + (left << 2); + } + else + { + config->offset.y = config->offset.u = config->offset.v = 0; + src_offset_y= src_offset_u= src_offset_v= top*pitch + (left << 1); + } + + num_mach64_buffers= config->num_frames; + for(i=0; i<config->num_frames; i++) + { + mach64_buffer_base[i][0]= (mach64_overlay_offset + config->offsets[i] + src_offset_y)&~15; + mach64_buffer_base[i][1]= (mach64_overlay_offset + config->offsets[i] + src_offset_u)&~15; + mach64_buffer_base[i][2]= (mach64_overlay_offset + config->offsets[i] + src_offset_v)&~15; + } + + leftUV = (left >> 17) & 15; + left = (left >> 16) & 15; + besr.scale_inc = ( h_inc << 16 ) | v_inc; + y_pos = config->dest.y; + if(mach64_is_dbl_scan()) y_pos*=2; + else + if(mach64_is_interlace()) y_pos/=2; + besr.y_x_start = y_pos | (config->dest.x << 16); + y_pos =config->dest.y + dest_h; + if(mach64_is_dbl_scan()) y_pos*=2; + else + if(mach64_is_interlace()) y_pos/=2; + besr.y_x_end = y_pos | ((config->dest.x + dest_w) << 16); + besr.height_width = ((src_w - left)<<16) | (src_h - top); + + return 0; +} + +static int is_supported_fourcc(uint32_t fourcc) +{ + switch(fourcc) + { + case IMGFMT_YV12: + case IMGFMT_I420: + case IMGFMT_YVU9: + case IMGFMT_IYUV: + return supports_planar; + case IMGFMT_YUY2: + case IMGFMT_UYVY: + case IMGFMT_BGR15: + case IMGFMT_BGR16: + case IMGFMT_BGR32: + return 1; + default: + return 0; + } +} + +int vixQueryFourcc(vidix_fourcc_t *to) +{ + if(is_supported_fourcc(to->fourcc)) + { + to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | + VID_DEPTH_4BPP | VID_DEPTH_8BPP | + VID_DEPTH_12BPP| VID_DEPTH_15BPP| + VID_DEPTH_16BPP| VID_DEPTH_24BPP| + VID_DEPTH_32BPP; + to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; + return 0; + } + else to->depth = to->flags = 0; + return ENOSYS; +} + +int vixConfigPlayback(vidix_playback_t *info) +{ + if(!is_supported_fourcc(info->fourcc)) return ENOSYS; + + mach64_compute_framesize(info); + + if(info->num_frames>4) info->num_frames=4; + for(;info->num_frames>0; info->num_frames--) + { + mach64_overlay_offset = mach64_ram_size - info->frame_size*info->num_frames; + mach64_overlay_offset &= 0xffff0000; + if(mach64_overlay_offset>0) break; + } + if(info->num_frames <= 0) return EINVAL; + + info->dga_addr = (char *)mach64_mem_base + mach64_overlay_offset; + mach64_vid_init_video(info); + return 0; +} + +int vixPlaybackOn(void) +{ + mach64_vid_display_video(); + return 0; +} + +int vixPlaybackOff(void) +{ + mach64_vid_stop_video(); + return 0; +} + +int vixPlaybackFrameSelect(unsigned int frame) +{ + uint32_t off[6]; + int i; + int last_frame= (frame-1+num_mach64_buffers) % num_mach64_buffers; +//printf("Selecting frame %d\n", frame); + /* + buf3-5 always should point onto second buffer for better + deinterlacing and TV-in + */ + if(num_mach64_buffers==1) return 0; + + for(i=0; i<3; i++) + { + off[i] = mach64_buffer_base[frame][i]; + off[i+3]= mach64_buffer_base[last_frame][i]; + } + +#if 0 // delay routine so the individual frames can be ssen better +{ +volatile int i=0; +for(i=0; i<10000000; i++); +} +#endif + + mach64_wait_for_idle(); + mach64_fifo_wait(7); + + OUTREG(SCALER_BUF0_OFFSET, off[0]); + OUTREG(SCALER_BUF0_OFFSET_U, off[1]); + OUTREG(SCALER_BUF0_OFFSET_V, off[2]); + OUTREG(SCALER_BUF1_OFFSET, off[3]); + OUTREG(SCALER_BUF1_OFFSET_U, off[4]); + OUTREG(SCALER_BUF1_OFFSET_V, off[5]); + if(num_mach64_buffers==2) mach64_wait_vsync(); //only wait for vsync if we do double buffering + + if(__verbose > VERBOSE_LEVEL) mach64_vid_dump_regs(); + return 0; +} + +vidix_video_eq_t equal = +{ + VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION + , + 0, 0, 0, 0, 0, 0, 0, 0 }; + +int vixPlaybackGetEq( vidix_video_eq_t * eq) +{ + memcpy(eq,&equal,sizeof(vidix_video_eq_t)); + return 0; +} + +int vixPlaybackSetEq( const vidix_video_eq_t * eq) +{ + int br,sat; + if(eq->cap & VEQ_CAP_BRIGHTNESS) equal.brightness = eq->brightness; + if(eq->cap & VEQ_CAP_CONTRAST) equal.contrast = eq->contrast; + if(eq->cap & VEQ_CAP_SATURATION) equal.saturation = eq->saturation; + if(eq->cap & VEQ_CAP_HUE) equal.hue = eq->hue; + if(eq->cap & VEQ_CAP_RGB_INTENSITY) + { + equal.red_intensity = eq->red_intensity; + equal.green_intensity = eq->green_intensity; + equal.blue_intensity = eq->blue_intensity; + } + equal.flags = eq->flags; + br = equal.brightness * 64 / 1000; + if(br < -64) br = -64; if(br > 63) br = 63; + sat = (equal.saturation + 1000) * 16 / 1000; + if(sat < 0) sat = 0; if(sat > 31) sat = 31; + OUTREG(SCALER_COLOUR_CNTL, (br & 0x7f) | (sat << 8) | (sat << 16)); + return 0; +} + +int vixGetGrKeys(vidix_grkey_t *grkey) +{ + memcpy(grkey, &mach64_grkey, sizeof(vidix_grkey_t)); + return(0); +} + +int vixSetGrKeys(const vidix_grkey_t *grkey) +{ + memcpy(&mach64_grkey, grkey, sizeof(vidix_grkey_t)); + + if(mach64_grkey.ckey.op == CKEY_TRUE) + { + besr.ckey_on=1; + + switch(mach64_vid_get_dbpp()) + { + case 15: + besr.graphics_key_msk=0x7FFF; + besr.graphics_key_clr= + ((mach64_grkey.ckey.blue &0xF8)>>3) + | ((mach64_grkey.ckey.green&0xF8)<<2) + | ((mach64_grkey.ckey.red &0xF8)<<7); + break; + case 16: + besr.graphics_key_msk=0xFFFF; + besr.graphics_key_clr= + ((mach64_grkey.ckey.blue &0xF8)>>3) + | ((mach64_grkey.ckey.green&0xFC)<<3) + | ((mach64_grkey.ckey.red &0xF8)<<8); + //besr.graphics_key_clr=le2me_32(besr.graphics_key_clr); + break; + case 24: + besr.graphics_key_msk=0xFFFFFF; + besr.graphics_key_clr= + ((mach64_grkey.ckey.blue &0xFF)) + | ((mach64_grkey.ckey.green&0xFF)<<8) + | ((mach64_grkey.ckey.red &0xFF)<<16); + break; + case 32: + besr.graphics_key_msk=0xFFFFFF; + besr.graphics_key_clr= + ((mach64_grkey.ckey.blue &0xFF)) + | ((mach64_grkey.ckey.green&0xFF)<<8) + | ((mach64_grkey.ckey.red &0xFF)<<16); + break; + default: + besr.ckey_on=0; + besr.graphics_key_msk=0; + besr.graphics_key_clr=0; + } + } + else + { + besr.ckey_on=0; + besr.graphics_key_msk=0; + besr.graphics_key_clr=0; + } + + mach64_fifo_wait(4); + OUTREG(OVERLAY_GRAPHICS_KEY_MSK, besr.graphics_key_msk); + OUTREG(OVERLAY_GRAPHICS_KEY_CLR, besr.graphics_key_clr); +// OUTREG(OVERLAY_VIDEO_KEY_MSK, 0); +// OUTREG(OVERLAY_VIDEO_KEY_CLR, 0); + if(besr.ckey_on) + OUTREG(OVERLAY_KEY_CNTL,VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_EQ|CMP_MIX_AND); + else + OUTREG(OVERLAY_KEY_CNTL,VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_TRUE|CMP_MIX_AND); + + return(0); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/vidix/mga_vid.c Sun Apr 01 00:02:43 2007 +0000 @@ -0,0 +1,1508 @@ +/* + Matrox MGA driver + + ported to VIDIX by Alex Beregszaszi + + YUY2 support (see config.format) added by A'rpi/ESP-team + double buffering added by A'rpi/ESP-team + + Brightness/contrast support by Nick Kurshev/Dariush Pietrzak (eyck) and me + + TODO: + * fix memory size detection (current reading pci userconfig isn't + working as requested - returns the max avail. ram on arch?) + * translate all non-english comments to english +*/ + +/* + * Original copyright: + * + * mga_vid.c + * + * Copyright (C) 1999 Aaron Holtzman + * + * Module skeleton based on gutted agpgart module by Jeff Hartmann + * <slicer@ionet.net> + * + * Matrox MGA G200/G400 YUV Video Interface module Version 0.1.0 + * + * BES == Back End Scaler + * + * This software has been released under the terms of the GNU Public + * license. See http://www.gnu.org/copyleft/gpl.html for details. + */ + +//#define CRTC2 + +// Set this value, if autodetection fails! (video ram size in megabytes) +//#define MGA_MEMORY_SIZE 16 + +/* No irq support in userspace implemented yet, do not enable this! */ +/* disable irq */ +#undef MGA_ALLOW_IRQ + +#define MGA_VSYNC_POS 2 + +#undef MGA_PCICONFIG_MEMDETECT + +#define MGA_DEFAULT_FRAMES 4 + +#include <errno.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <math.h> +#include <inttypes.h> + +#include "vidix.h" +#include "fourcc.h" +#include "../libdha/libdha.h" +#include "../libdha/pci_ids.h" +#include "../libdha/pci_names.h" + +#ifdef __MINGW32__ +#define ENOTSUP 134 +#endif + +#if !defined(ENOTSUP) && defined(EOPNOTSUPP) +#define ENOTSUP EOPNOTSUPP +#endif + +/* from radeon_vid */ +#define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ)))) +#define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL + +#define readb(addr) GETREG(uint8_t,(uint32_t)(addr),0) +#define writeb(val,addr) SETREG(uint8_t,(uint32_t)(addr),0,val) +#define readl(addr) GETREG(uint32_t,(uint32_t)(addr),0) +#define writel(val,addr) SETREG(uint32_t,(uint32_t)(addr),0,val) + +static int mga_verbose = 0; + +/* for device detection */ +static int probed = 0; +static pciinfo_t pci_info; + +/* internal booleans */ +static int mga_vid_in_use = 0; +static int is_g400 = 0; +static int vid_src_ready = 0; +static int vid_overlay_on = 0; + +/* mapped physical addresses */ +static uint8_t *mga_mmio_base = 0; +static uint8_t *mga_mem_base = 0; + +static int mga_src_base = 0; /* YUV buffer position in video memory */ + +static uint32_t mga_ram_size = 0; /* how much megabytes videoram we have */ + +/* Graphic keys */ +static vidix_grkey_t mga_grkey; + +static int colkey_saved = 0; +static int colkey_on = 0; +static unsigned char colkey_color[4]; +static unsigned char colkey_mask[4]; + +/* for IRQ */ +static int mga_irq = -1; + +static int mga_next_frame = 0; + +static vidix_capability_t mga_cap = +{ + "Matrox MGA G200/G4x0/G5x0 YUV Video", + "Aaron Holtzman, Arpad Gereoffy, Alex Beregszaszi, Nick Kurshev", + TYPE_OUTPUT, + { 0, 0, 0, 0 }, + 2048, + 2048, + 4, + 4, + -1, + FLAG_UPSCALER | FLAG_DOWNSCALER | FLAG_EQUALIZER, + VENDOR_MATROX, + -1, /* will be set in vixProbe */ + { 0, 0, 0, 0} +}; + +/* MATROX BES registers */ +typedef struct bes_registers_s +{ + //BES Control + uint32_t besctl; + //BES Global control + uint32_t besglobctl; + //Luma control (brightness and contrast) + uint32_t beslumactl; + //Line pitch + uint32_t bespitch; + + //Buffer A-1 Chroma 3 plane org + uint32_t besa1c3org; + //Buffer A-1 Chroma org + uint32_t besa1corg; + //Buffer A-1 Luma org + uint32_t besa1org; + + //Buffer A-2 Chroma 3 plane org + uint32_t besa2c3org; + //Buffer A-2 Chroma org + uint32_t besa2corg; + //Buffer A-2 Luma org + uint32_t besa2org; + + //Buffer B-1 Chroma 3 plane org + uint32_t besb1c3org; + //Buffer B-1 Chroma org + uint32_t besb1corg; + //Buffer B-1 Luma org + uint32_t besb1org; + + //Buffer B-2 Chroma 3 plane org + uint32_t besb2c3org; + //Buffer B-2 Chroma org + uint32_t besb2corg; + //Buffer B-2 Luma org + uint32_t besb2org; + + //BES Horizontal coord + uint32_t beshcoord; + //BES Horizontal inverse scaling [5.14] + uint32_t beshiscal; + //BES Horizontal source start [10.14] (for scaling) + uint32_t beshsrcst; + //BES Horizontal source ending [10.14] (for scaling) + uint32_t beshsrcend; + //BES Horizontal source last + uint32_t beshsrclst; + + + //BES Vertical coord + uint32_t besvcoord; + //BES Vertical inverse scaling [5.14] + uint32_t besviscal; + //BES Field 1 vertical source last position + uint32_t besv1srclst; + //BES Field 1 weight start + uint32_t besv1wght; + //BES Field 2 vertical source last position + uint32_t besv2srclst; + //BES Field 2 weight start + uint32_t besv2wght; + +} bes_registers_t; +static bes_registers_t regs; + +#ifdef CRTC2 +typedef struct crtc2_registers_s +{ + uint32_t c2ctl; + uint32_t c2datactl; + uint32_t c2misc; + uint32_t c2hparam; + uint32_t c2hsync; + uint32_t c2offset; + uint32_t c2pl2startadd0; + uint32_t c2pl2startadd1; + uint32_t c2pl3startadd0; + uint32_t c2pl3startadd1; + uint32_t c2preload; + uint32_t c2spicstartadd0; + uint32_t c2spicstartadd1; + uint32_t c2startadd0; + uint32_t c2startadd1; + uint32_t c2subpiclut; + uint32_t c2vcount; + uint32_t c2vparam; + uint32_t c2vsync; +} crtc2_registers_t; +static crtc2_registers_t cregs; +#endif + +//All register offsets are converted to word aligned offsets (32 bit) +//because we want all our register accesses to be 32 bits +#define VCOUNT 0x1e20 + +#define PALWTADD 0x3c00 // Index register for X_DATAREG port +#define X_DATAREG 0x3c0a + +#define XMULCTRL 0x19 +#define BPP_8 0x00 +#define BPP_15 0x01 +#define BPP_16 0x02 +#define BPP_24 0x03 +#define BPP_32_DIR 0x04 +#define BPP_32_PAL 0x07 + +#define XCOLMSK 0x40 +#define X_COLKEY 0x42 +#define XKEYOPMODE 0x51 +#define XCOLMSK0RED 0x52 +#define XCOLMSK0GREEN 0x53 +#define XCOLMSK0BLUE 0x54 +#define XCOLKEY0RED 0x55 +#define XCOLKEY0GREEN 0x56 +#define XCOLKEY0BLUE 0x57 + +#ifdef CRTC2 +/*CRTC2 registers*/ +#define XMISCCTRL 0x1e +#define C2CTL 0x3c10 +#define C2DATACTL 0x3c4c +#define C2MISC 0x3c44 +#define C2HPARAM 0x3c14 +#define C2HSYNC 0x3c18 +#define C2OFFSET 0x3c40 +#define C2PL2STARTADD0 0x3c30 // like BESA1CORG +#define C2PL2STARTADD1 0x3c34 // like BESA2CORG +#define C2PL3STARTADD0 0x3c38 // like BESA1C3ORG +#define C2PL3STARTADD1 0x3c3c // like BESA2C3ORG +#define C2PRELOAD 0x3c24 +#define C2SPICSTARTADD0 0x3c54 +#define C2SPICSTARTADD1 0x3c58 +#define C2STARTADD0 0x3c28 // like BESA1ORG +#define C2STARTADD1 0x3c2c // like BESA2ORG +#define C2SUBPICLUT 0x3c50 +#define C2VCOUNT 0x3c48 +#define C2VPARAM 0x3c1c +#define C2VSYNC 0x3c20 +#endif /* CRTC2 */ + +// Backend Scaler registers +#define BESCTL 0x3d20 +#define BESGLOBCTL 0x3dc0 +#define BESLUMACTL 0x3d40 +#define BESPITCH 0x3d24 + +#define BESA1C3ORG 0x3d60 +#define BESA1CORG 0x3d10 +#define BESA1ORG 0x3d00 + +#define BESA2C3ORG 0x3d64 +#define BESA2CORG 0x3d14 +#define BESA2ORG 0x3d04 + +#define BESB1C3ORG 0x3d68 +#define BESB1CORG 0x3d18 +#define BESB1ORG 0x3d08 + +#define BESB2C3ORG 0x3d6C +#define BESB2CORG 0x3d1C +#define BESB2ORG 0x3d0C + +#define BESHCOORD 0x3d28 +#define BESHISCAL 0x3d30 +#define BESHSRCEND 0x3d3C +#define BESHSRCLST 0x3d50 +#define BESHSRCST 0x3d38 +#define BESV1WGHT 0x3d48 +#define BESV2WGHT 0x3d4c +#define BESV1SRCLST 0x3d54 +#define BESV2SRCLST 0x3d58 +#define BESVISCAL 0x3d34 +#define BESVCOORD 0x3d2c +#define BESSTATUS 0x3dc4 + +#define CRTCX 0x1fd4 +#define CRTCD 0x1fd5 +#define IEN 0x1e1c +#define ICLEAR 0x1e18 +#define STATUS 0x1e14 + + +#ifdef CRTC2 +static void crtc2_frame_sel(int frame) +{ +switch(frame) { +case 0: + cregs.c2pl2startadd0=regs.besa1corg; + cregs.c2pl3startadd0=regs.besa1c3org; + cregs.c2startadd0=regs.besa1org; + break; +case 1: + cregs.c2pl2startadd0=regs.besa2corg; + cregs.c2pl3startadd0=regs.besa2c3org; + cregs.c2startadd0=regs.besa2org; + break; +case 2: + cregs.c2pl2startadd0=regs.besb1corg; + cregs.c2pl3startadd0=regs.besb1c3org; + cregs.c2startadd0=regs.besb1org; + break; +case 3: + cregs.c2pl2startadd0=regs.besb2corg; + cregs.c2pl3startadd0=regs.besb2c3org; + cregs.c2startadd0=regs.besb2org; + break; +} + writel(cregs.c2startadd0, mga_mmio_base + C2STARTADD0); + writel(cregs.c2pl2startadd0, mga_mmio_base + C2PL2STARTADD0); + writel(cregs.c2pl3startadd0, mga_mmio_base + C2PL3STARTADD0); +} +#endif + +int vixPlaybackFrameSelect(unsigned int frame) +{ + mga_next_frame = frame; + if (mga_verbose>1) printf("[mga] frameselect: %d\n", mga_next_frame); +#if MGA_ALLOW_IRQ + if (mga_irq == -1) +#endif + { + //we don't need the vcount protection as we're only hitting + //one register (and it doesn't seem to be double buffered) + regs.besctl = (regs.besctl & ~0x07000000) + (mga_next_frame << 25); + writel( regs.besctl, mga_mmio_base + BESCTL ); + +// writel( regs.besglobctl + ((readl(mga_mmio_base + VCOUNT)+2)<<16), + writel( regs.besglobctl + (MGA_VSYNC_POS<<16), + mga_mmio_base + BESGLOBCTL); +#ifdef CRTC2 + crtc2_frame_sel(mga_next_frame); +#endif + } + + return(0); +} + + +static void mga_vid_write_regs(int restore) +{ + //Make sure internal registers don't get updated until we're done + writel( (readl(mga_mmio_base + VCOUNT)-1)<<16, + mga_mmio_base + BESGLOBCTL); + + // color or coordinate keying + + if(restore && colkey_saved){ + // restore it + colkey_saved=0; + +// printf("[mga] Restoring colorkey (ON: %d %02X:%02X:%02X)\n", +// colkey_on,colkey_color[0],colkey_color[1],colkey_color[2]); + + // Set color key registers: + writeb( XKEYOPMODE, mga_mmio_base + PALWTADD); + writeb( colkey_on, mga_mmio_base + X_DATAREG); + + writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD); + writeb( colkey_color[0], mga_mmio_base + X_DATAREG); + writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD); + writeb( colkey_color[1], mga_mmio_base + X_DATAREG); + writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD); + writeb( colkey_color[2], mga_mmio_base + X_DATAREG); + writeb( X_COLKEY, mga_mmio_base + PALWTADD); + writeb( colkey_color[3], mga_mmio_base + X_DATAREG); + + writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD); + writeb( colkey_mask[0], mga_mmio_base + X_DATAREG); + writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD); + writeb( colkey_mask[1], mga_mmio_base + X_DATAREG); + writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD); + writeb( colkey_mask[2], mga_mmio_base + X_DATAREG); + writeb( XCOLMSK, mga_mmio_base + PALWTADD); + writeb( colkey_mask[3], mga_mmio_base + X_DATAREG); + + } else if(!colkey_saved){ + // save it + colkey_saved=1; + // Get color key registers: + writeb( XKEYOPMODE, mga_mmio_base + PALWTADD); + colkey_on=(unsigned char)readb(mga_mmio_base + X_DATAREG) & 1; + + writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD); + colkey_color[0]=(unsigned char)readb(mga_mmio_base + X_DATAREG); + writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD); + colkey_color[1]=(unsigned char)readb(mga_mmio_base + X_DATAREG); + writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD); + colkey_color[2]=(unsigned char)readb(mga_mmio_base + X_DATAREG); + writeb( X_COLKEY, mga_mmio_base + PALWTADD); + colkey_color[3]=(unsigned char)readb(mga_mmio_base + X_DATAREG); + + writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD); + colkey_mask[0]=(unsigned char)readb(mga_mmio_base + X_DATAREG); + writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD); + colkey_mask[1]=(unsigned char)readb(mga_mmio_base + X_DATAREG); + writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD); + colkey_mask[2]=(unsigned char)readb(mga_mmio_base + X_DATAREG); + writeb( XCOLMSK, mga_mmio_base + PALWTADD); + colkey_mask[3]=(unsigned char)readb(mga_mmio_base + X_DATAREG); + +// printf("[mga] Saved colorkey (ON: %d %02X:%02X:%02X)\n", +// colkey_on,colkey_color[0],colkey_color[1],colkey_color[2]); + + } + +if(!restore){ + writeb( XKEYOPMODE, mga_mmio_base + PALWTADD); + writeb( mga_grkey.ckey.op == CKEY_TRUE, mga_mmio_base + X_DATAREG); + if ( mga_grkey.ckey.op == CKEY_TRUE ) + { + uint32_t r=0, g=0, b=0; + + writeb( XMULCTRL, mga_mmio_base + PALWTADD); + switch (readb (mga_mmio_base + X_DATAREG)) + { + case BPP_8: + /* Need to look up the color index, just using + color 0 for now. */ + break; + + case BPP_15: + r = mga_grkey.ckey.red >> 3; + g = mga_grkey.ckey.green >> 3; + b = mga_grkey.ckey.blue >> 3; + break; + + case BPP_16: + r = mga_grkey.ckey.red >> 3; + g = mga_grkey.ckey.green >> 2; + b = mga_grkey.ckey.blue >> 3; + break; + + case BPP_24: + case BPP_32_DIR: + case BPP_32_PAL: + r = mga_grkey.ckey.red; + g = mga_grkey.ckey.green; + b = mga_grkey.ckey.blue; + break; + } + + // Enable colorkeying + writeb( XKEYOPMODE, mga_mmio_base + PALWTADD); + writeb( 1, mga_mmio_base + X_DATAREG); + + // Disable color keying on alpha channel + writeb( XCOLMSK, mga_mmio_base + PALWTADD); + writeb( 0x00, mga_mmio_base + X_DATAREG); + writeb( X_COLKEY, mga_mmio_base + PALWTADD); + writeb( 0x00, mga_mmio_base + X_DATAREG); + + + // Set up color key registers + writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD); + writeb( r, mga_mmio_base + X_DATAREG); + writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD); + writeb( g, mga_mmio_base + X_DATAREG); + writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD); + writeb( b, mga_mmio_base + X_DATAREG); + + // Set up color key mask registers + writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD); + writeb( 0xff, mga_mmio_base + X_DATAREG); + writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD); + writeb( 0xff, mga_mmio_base + X_DATAREG); + writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD); + writeb( 0xff, mga_mmio_base + X_DATAREG); + } + else + { + // Disable colorkeying + writeb( XKEYOPMODE, mga_mmio_base + PALWTADD); + writeb( 0, mga_mmio_base + X_DATAREG); + } +} + + // Backend Scaler + writel( regs.besctl, mga_mmio_base + BESCTL); + if(is_g400) + writel( regs.beslumactl, mga_mmio_base + BESLUMACTL); + writel( regs.bespitch, mga_mmio_base + BESPITCH); + + writel( regs.besa1org, mga_mmio_base + BESA1ORG); + writel( regs.besa1corg, mga_mmio_base + BESA1CORG); + writel( regs.besa2org, mga_mmio_base + BESA2ORG); + writel( regs.besa2corg, mga_mmio_base + BESA2CORG); + writel( regs.besb1org, mga_mmio_base + BESB1ORG); + writel( regs.besb1corg, mga_mmio_base + BESB1CORG); + writel( regs.besb2org, mga_mmio_base + BESB2ORG); + writel( regs.besb2corg, mga_mmio_base + BESB2CORG); + if(is_g400) + { + writel( regs.besa1c3org, mga_mmio_base + BESA1C3ORG); + writel( regs.besa2c3org, mga_mmio_base + BESA2C3ORG); + writel( regs.besb1c3org, mga_mmio_base + BESB1C3ORG); + writel( regs.besb2c3org, mga_mmio_base + BESB2C3ORG); + } + + writel( regs.beshcoord, mga_mmio_base + BESHCOORD); + writel( regs.beshiscal, mga_mmio_base + BESHISCAL); + writel( regs.beshsrcst, mga_mmio_base + BESHSRCST); + writel( regs.beshsrcend, mga_mmio_base + BESHSRCEND); + writel( regs.beshsrclst, mga_mmio_base + BESHSRCLST); + + writel( regs.besvcoord, mga_mmio_base + BESVCOORD); + writel( regs.besviscal, mga_mmio_base + BESVISCAL); + + writel( regs.besv1srclst, mga_mmio_base + BESV1SRCLST); + writel( regs.besv1wght, mga_mmio_base + BESV1WGHT); + writel( regs.besv2srclst, mga_mmio_base + BESV2SRCLST); + writel( regs.besv2wght, mga_mmio_base + BESV2WGHT); + + //update the registers somewhere between 1 and 2 frames from now. + writel( regs.besglobctl + ((readl(mga_mmio_base + VCOUNT)+2)<<16), + mga_mmio_base + BESGLOBCTL); + + if (mga_verbose > 1) + { + printf("[mga] wrote BES registers\n"); + printf("[mga] BESCTL = 0x%08x\n", + readl(mga_mmio_base + BESCTL)); + printf("[mga] BESGLOBCTL = 0x%08x\n", + readl(mga_mmio_base + BESGLOBCTL)); + printf("[mga] BESSTATUS= 0x%08x\n", + readl(mga_mmio_base + BESSTATUS)); + } +#ifdef CRTC2 +// printf("c2ctl:0x%08x c2datactl:0x%08x\n",readl(mga_mmio_base + C2CTL),readl(mga_mmio_base + C2DATACTL)); +// printf("c2misc:0x%08x\n",readl(mga_mmio_base + C2MISC)); +// printf("c2ctl:0x%08x c2datactl:0x%08x\n",cregs.c2ctl,cregs.c2datactl); + +// writel(cregs.c2ctl, mga_mmio_base + C2CTL); + + writel(((readl(mga_mmio_base + C2CTL) & ~0x03e00000) + (cregs.c2ctl & 0x03e00000)), mga_mmio_base + C2CTL); + writel(((readl(mga_mmio_base + C2DATACTL) & ~0x000000ff) + (cregs.c2datactl & 0x000000ff)), mga_mmio_base + C2DATACTL); + // ctrc2 + // disable CRTC2 acording to specs +// writel(cregs.c2ctl & 0xfffffff0, mga_mmio_base + C2CTL); + // je to treba ??? +// writeb((readb(mga_mmio_base + XMISCCTRL) & 0x19) | 0xa2, mga_mmio_base + XMISCCTRL); // MAFC - mfcsel & vdoutsel +// writeb((readb(mga_mmio_base + XMISCCTRL) & 0x19) | 0x92, mga_mmio_base + XMISCCTRL); +// writeb((readb(mga_mmio_base + XMISCCTRL) & ~0xe9) + 0xa2, mga_mmio_base + XMISCCTRL); +// writel(cregs.c2datactl, mga_mmio_base + C2DATACTL); +// writel(cregs.c2hparam, mga_mmio_base + C2HPARAM); +// writel(cregs.c2hsync, mga_mmio_base + C2HSYNC); +// writel(cregs.c2vparam, mga_mmio_base + C2VPARAM); +// writel(cregs.c2vsync, mga_mmio_base + C2VSYNC); + writel(cregs.c2misc, mga_mmio_base + C2MISC); + + if (mga_verbose > 1) printf("[mga] c2offset = %d\n",cregs.c2offset); + + writel(cregs.c2offset, mga_mmio_base + C2OFFSET); + writel(cregs.c2startadd0, mga_mmio_base + C2STARTADD0); +// writel(cregs.c2startadd1, mga_mmio_base + C2STARTADD1); + writel(cregs.c2pl2startadd0, mga_mmio_base + C2PL2STARTADD0); +// writel(cregs.c2pl2startadd1, mga_mmio_base + C2PL2STARTADD1); + writel(cregs.c2pl3startadd0, mga_mmio_base + C2PL3STARTADD0); +// writel(cregs.c2pl3startadd1, mga_mmio_base + C2PL3STARTADD1); + writel(cregs.c2spicstartadd0, mga_mmio_base + C2SPICSTARTADD0); +// writel(cregs.c2spicstartadd1, mga_mmio_base + C2SPICSTARTADD1); +// writel(cregs.c2subpiclut, mga_mmio_base + C2SUBPICLUT); +// writel(cregs.c2preload, mga_mmio_base + C2PRELOAD); + // finaly enable everything +// writel(cregs.c2ctl, mga_mmio_base + C2CTL); +// printf("c2ctl:0x%08x c2datactl:0x%08x\n",readl(mga_mmio_base + C2CTL),readl(mga_mmio_base + C2DATACTL)); +// printf("c2misc:0x%08x\n", readl(mga_mmio_base + C2MISC)); +#endif +} + +#ifdef MGA_ALLOW_IRQ +static void enable_irq(){ + long int cc; + + cc = readl(mga_mmio_base + IEN); +// printf("*** !!! IRQREG = %d\n", (int)(cc&0xff)); + + writeb( 0x11, mga_mmio_base + CRTCX); + + writeb(0x20, mga_mmio_base + CRTCD ); /* clear 0, enable off */ + writeb(0x00, mga_mmio_base + CRTCD ); /* enable on */ + writeb(0x10, mga_mmio_base + CRTCD ); /* clear = 1 */ + + writel( regs.besglobctl , mga_mmio_base + BESGLOBCTL); + + return; +} + +static void disable_irq() +{ + writeb( 0x11, mga_mmio_base + CRTCX); + writeb(0x20, mga_mmio_base + CRTCD ); /* clear 0, enable off */ + + return; +} + +void mga_handle_irq(int irq, void *dev_id/*, struct pt_regs *pregs*/) { +// static int frame=0; +// static int counter=0; + long int cc; +// if ( ! mga_enabled_flag ) return; + +// printf("vcount = %d\n",readl(mga_mmio_base + VCOUNT)); + + //printf("mga_interrupt #%d\n", irq); + + if ( irq != -1 ) { + + cc = readl(mga_mmio_base + STATUS); + if ( ! (cc & 0x10) ) return; /* vsyncpen */ +// debug_irqcnt++; + } + +// if ( debug_irqignore ) { +// debug_irqignore = 0; + + +/* + if ( mga_conf_deinterlace ) { + if ( mga_first_field ) { + // printf("mga_interrupt first field\n"); + if ( syncfb_interrupt() ) + mga_first_field = 0; + } else { + // printf("mga_interrupt second field\n"); + mga_select_buffer( mga_current_field | 2 ); + mga_first_field = 1; + } + } else { + syncfb_interrupt(); + } +*/ + +// frame=(frame+1)&1; + regs.besctl = (regs.besctl & ~0x07000000) + (mga_next_frame << 25); + writel( regs.besctl, mga_mmio_base + BESCTL ); + +#ifdef CRTC2 +// sem pridat vyber obrazku !!!! + crtc2_frame_sel(mga_next_frame); +#endif + +#if 0 + ++counter; + if(!(counter&63)){ + printf("mga irq counter = %d\n",counter); + } +#endif + +// } else { +// debug_irqignore = 1; +// } + + if ( irq != -1 ) { + writeb( 0x11, mga_mmio_base + CRTCX); + writeb( 0, mga_mmio_base + CRTCD ); + writeb( 0x10, mga_mmio_base + CRTCD ); + } + +// writel( regs.besglobctl, mga_mmio_base + BESGLOBCTL); + + + return; + +} +#endif /* MGA_ALLOW_IRQ */ + +int vixConfigPlayback(vidix_playback_t *config) +{ + unsigned int i; + int x, y, sw, sh, dw, dh; + int besleft, bestop, ifactor, ofsleft, ofstop, baseadrofs, weight, weights; +#ifdef CRTC2 +#define right_margin 0 +#define left_margin 18 +#define hsync_len 46 +#define lower_margin 10 +#define vsync_len 4 +#define upper_margin 39 + + unsigned int hdispend = (config->src.w + 31) & ~31; + unsigned int hsyncstart = hdispend + (right_margin & ~7); + unsigned int hsyncend = hsyncstart + (hsync_len & ~7); + unsigned int htotal = hsyncend + (left_margin & ~7); + unsigned int vdispend = config->src.h; + unsigned int vsyncstart = vdispend + lower_margin; + unsigned int vsyncend = vsyncstart + vsync_len; + unsigned int vtotal = vsyncend + upper_margin; +#endif + + if ((config->num_frames < 1) || (config->num_frames > 4)) + { + printf("[mga] illegal num_frames: %d, setting to %d\n", + config->num_frames, MGA_DEFAULT_FRAMES); + config->num_frames = MGA_DEFAULT_FRAMES; + } + + x = config->dest.x; + y = config->dest.y; + sw = config->src.w; + sh = config->src.h; + dw = config->dest.w; + dh = config->dest.h; + + config->dest.pitch.y=32; + config->dest.pitch.u=config->dest.pitch.v=32; + + if (mga_verbose) printf("[mga] Setting up a %dx%d-%dx%d video window (src %dx%d) format %X\n", + dw, dh, x, y, sw, sh, config->fourcc); + + if ((sw < 4) || (sh < 4) || (dw < 4) || (dh < 4)) + { + printf("[mga] Invalid src/dest dimensions\n"); + return(EINVAL); + } + + //FIXME check that window is valid and inside desktop + +// printf("[mga] vcount = %d\n", readl(mga_mmio_base + VCOUNT)); + + sw+=sw&1; + switch(config->fourcc) + { + case IMGFMT_I420: + case IMGFMT_IYUV: + case IMGFMT_YV12: + sh+=sh&1; + config->frame_size = ((sw + 31) & ~31) * sh + (((sw + 31) & ~31) * sh) / 2; + break; + case IMGFMT_YUY2: + case IMGFMT_UYVY: + config->frame_size = ((sw + 31) & ~31) * sh * 2; + break; + default: + printf("[mga] Unsupported pixel format: %x\n", config->fourcc); + return(ENOTSUP); + } + + config->offsets[0] = 0; +// config->offsets[1] = config->frame_size; +// config->offsets[2] = 2*config->frame_size; +// config->offsets[3] = 3*config->frame_size; + for (i = 1; i < config->num_frames+1; i++) + config->offsets[i] = i*config->frame_size; + + config->offset.y=0; + if(config->fourcc == IMGFMT_I420 || config->fourcc == IMGFMT_IYUV) + { + config->offset.u=((sw + 31) & ~31) * sh; + config->offset.v=config->offset.u+((sw + 31) & ~31) * sh /4; + } + else { + config->offset.v=((sw + 31) & ~31) * sh; + config->offset.u=config->offset.v+((sw + 31) & ~31) * sh /4; + } + + //FIXME figure out a better way to allocate memory on card + //allocate 2 megs + //mga_src_base = mga_mem_base + (MGA_VIDMEM_SIZE-2) * 0x100000; + //mga_src_base = (MGA_VIDMEM_SIZE-3) * 0x100000; + + mga_src_base = (mga_ram_size*0x100000-config->num_frames*config->frame_size); + if (mga_src_base < 0) + { + printf("[mga] not enough memory for frames!\n"); + return(EFAULT); + } + mga_src_base &= (~0xFFFF); /* 64k boundary */ + if (mga_verbose > 1) printf("[mga] YUV buffer base: %#x\n", mga_src_base); + + config->dga_addr = mga_mem_base + mga_src_base; + + /* for G200 set Interleaved UV planes */ + if (!is_g400) + config->flags = VID_PLAY_INTERLEAVED_UV | INTERLEAVING_UV; + + //Setup the BES registers for a three plane 4:2:0 video source + + regs.besglobctl = 0; + + switch(config->fourcc) + { + case IMGFMT_YV12: + case IMGFMT_I420: + case IMGFMT_IYUV: + regs.besctl = 1 // BES enabled + + (0<<6) // even start polarity + + (1<<10) // x filtering enabled + + (1<<11) // y filtering enabled + + (1<<16) // chroma upsampling + + (1<<17) // 4:2:0 mode + + (1<<18); // dither enabled +#if 0 + if(is_g400) + { + //zoom disabled, zoom filter disabled, 420 3 plane format, proc amp + //disabled, rgb mode disabled + regs.besglobctl = (1<<5); + } + else + { + //zoom disabled, zoom filter disabled, Cb samples in 0246, Cr + //in 1357, BES register update on besvcnt + regs.besglobctl = 0; + } +#endif + break; + + case IMGFMT_YUY2: + regs.besctl = 1 // BES enabled + + (0<<6) // even start polarity + + (1<<10) // x filtering enabled + + (1<<11) // y filtering enabled + + (1<<16) // chroma upsampling + + (0<<17) // 4:2:2 mode + + (1<<18); // dither enabled + + regs.besglobctl = 0; // YUY2 format selected + break; + + case IMGFMT_UYVY: + regs.besctl = 1 // BES enabled + + (0<<6) // even start polarity + + (1<<10) // x filtering enabled + + (1<<11) // y filtering enabled + + (1<<16) // chroma upsampling + + (0<<17) // 4:2:2 mode + + (1<<18); // dither enabled + + regs.besglobctl = 1<<6; // UYVY format selected + break; + + } + + //Disable contrast and brightness control + regs.besglobctl |= (1<<5) + (1<<7); + regs.beslumactl = (0x7f << 16) + (0x80<<0); + regs.beslumactl = 0x80<<0; + + //Setup destination window boundaries + besleft = x > 0 ? x : 0; + bestop = y > 0 ? y : 0; + regs.beshcoord = (besleft<<16) + (x + dw-1); + regs.besvcoord = (bestop<<16) + (y + dh-1); + + //Setup source dimensions + regs.beshsrclst = (sw - 1) << 16; + regs.bespitch = (sw + 31) & ~31 ; + + //Setup horizontal scaling + ifactor = ((sw-1)<<14)/(dw-1); + ofsleft = besleft - x; + + regs.beshiscal = ifactor<<2; + regs.beshsrcst = (ofsleft*ifactor)<<2; + regs.beshsrcend = regs.beshsrcst + (((dw - ofsleft - 1) * ifactor) << 2); + + //Setup vertical scaling + ifactor = ((sh-1)<<14)/(dh-1); + ofstop = bestop - y; + + regs.besviscal = ifactor<<2; + + baseadrofs = ((ofstop*regs.besviscal)>>16)*regs.bespitch; + //frame_size = ((sw + 31) & ~31) * sh + (((sw + 31) & ~31) * sh) / 2; + regs.besa1org = (uint32_t) mga_src_base + baseadrofs; + regs.besa2org = (uint32_t) mga_src_base + baseadrofs + 1*config->frame_size; + regs.besb1org = (uint32_t) mga_src_base + baseadrofs + 2*config->frame_size; + regs.besb2org = (uint32_t) mga_src_base + baseadrofs + 3*config->frame_size; + +if(config->fourcc==IMGFMT_YV12 + ||config->fourcc==IMGFMT_IYUV + ||config->fourcc==IMGFMT_I420 + ){ + // planar YUV frames: + if (is_g400) + baseadrofs = (((ofstop*regs.besviscal)/4)>>16)*regs.bespitch; + else + baseadrofs = (((ofstop*regs.besviscal)/2)>>16)*regs.bespitch; + + if(config->fourcc==IMGFMT_YV12){ + regs.besa1corg = (uint32_t) mga_src_base + baseadrofs + regs.bespitch * sh ; + regs.besa2corg = (uint32_t) mga_src_base + baseadrofs + 1*config->frame_size + regs.bespitch * sh; + regs.besb1corg = (uint32_t) mga_src_base + baseadrofs + 2*config->frame_size + regs.bespitch * sh; + regs.besb2corg = (uint32_t) mga_src_base + baseadrofs + 3*config->frame_size + regs.bespitch * sh; + regs.besa1c3org = regs.besa1corg + ((regs.bespitch * sh) / 4); + regs.besa2c3org = regs.besa2corg + ((regs.bespitch * sh) / 4); + regs.besb1c3org = regs.besb1corg + ((regs.bespitch * sh) / 4); + regs.besb2c3org = regs.besb2corg + ((regs.bespitch * sh) / 4); + } else { + regs.besa1c3org = (uint32_t) mga_src_base + baseadrofs + regs.bespitch * sh ; + regs.besa2c3org = (uint32_t) mga_src_base + baseadrofs + 1*config->frame_size + regs.bespitch * sh; + regs.besb1c3org = (uint32_t) mga_src_base + baseadrofs + 2*config->frame_size + regs.bespitch * sh; + regs.besb2c3org = (uint32_t) mga_src_base + baseadrofs + 3*config->frame_size + regs.bespitch * sh; + regs.besa1corg = regs.besa1c3org + ((regs.bespitch * sh) / 4); + regs.besa2corg = regs.besa2c3org + ((regs.bespitch * sh) / 4); + regs.besb1corg = regs.besb1c3org + ((regs.bespitch * sh) / 4); + regs.besb2corg = regs.besb2c3org + ((regs.bespitch * sh) / 4); + } + +} + + weight = ofstop * (regs.besviscal >> 2); + weights = weight < 0 ? 1 : 0; + regs.besv2wght = regs.besv1wght = (weights << 16) + ((weight & 0x3FFF) << 2); + regs.besv2srclst = regs.besv1srclst = sh - 1 - (((ofstop * regs.besviscal) >> 16) & 0x03FF); + +#ifdef CRTC2 + // pridat hlavni registry - tj. casovani ... + + +switch(config->fourcc){ + case IMGFMT_YV12: + case IMGFMT_I420: + case IMGFMT_IYUV: + cregs.c2ctl = 1 // CRTC2 enabled + + (1<<1) // external clock + + (0<<2) // external clock + + (1<<3) // pixel clock enable - not needed ??? + + (0<<4) // high prioryty req + + (1<<5) // high prioryty req + + (0<<6) // high prioryty req + + (1<<8) // high prioryty req max + + (0<<9) // high prioryty req max + + (0<<10) // high prioryty req max + + (0<<20) // CRTC1 to DAC + + (1<<21) // 420 mode + + (1<<22) // 420 mode + + (1<<23) // 420 mode + + (0<<24) // single chroma line for 420 mode - need to be corrected + + (0<<25) /*/ interlace mode - need to be corrected*/ + + (0<<26) // field legth polariry + + (0<<27) // field identification polariry + + (1<<28) // VIDRST detection mode + + (0<<29) // VIDRST detection mode + + (1<<30) // Horizontal counter preload + + (1<<31) // Vertical counter preload + ; + cregs.c2datactl = 1 // disable dither - propably not needed, we are already in YUV mode + + (1<<1) // Y filter enable + + (1<<2) // CbCr filter enable + + (0<<3) // subpicture enable (disabled) + + (0<<4) // NTSC enable (disabled - PAL) + + (0<<5) // C2 static subpicture enable (disabled) + + (0<<6) // C2 subpicture offset division (disabled) + + (0<<7) // 422 subformat selection ! +/* + (0<<8) // 15 bpp high alpha + + (0<<9) // 15 bpp high alpha + + (0<<10) // 15 bpp high alpha + + (0<<11) // 15 bpp high alpha + + (0<<12) // 15 bpp high alpha + + (0<<13) // 15 bpp high alpha + + (0<<14) // 15 bpp high alpha + + (0<<15) // 15 bpp high alpha + + (0<<16) // 15 bpp low alpha + + (0<<17) // 15 bpp low alpha + + (0<<18) // 15 bpp low alpha + + (0<<19) // 15 bpp low alpha + + (0<<20) // 15 bpp low alpha + + (0<<21) // 15 bpp low alpha + + (0<<22) // 15 bpp low alpha + + (0<<23) // 15 bpp low alpha + + (0<<24) // static subpicture key + + (0<<25) // static subpicture key + + (0<<26) // static subpicture key + + (0<<27) // static subpicture key + + (0<<28) // static subpicture key +*/ ; + break; + + case IMGFMT_YUY2: + cregs.c2ctl = 1 // CRTC2 enabled + + (1<<1) // external clock + + (0<<2) // external clock + + (1<<3) // pixel clock enable - not needed ??? + + (0<<4) // high prioryty req - acc to spec + + (1<<5) // high prioryty req + + (0<<6) // high prioryty req + // 7 reserved + + (1<<8) // high prioryty req max + + (0<<9) // high prioryty req max + + (0<<10) // high prioryty req max + // 11-19 reserved + + (0<<20) // CRTC1 to DAC + + (1<<21) // 422 mode + + (0<<22) // 422 mode + + (1<<23) // 422 mode + + (0<<24) // single chroma line for 420 mode - need to be corrected + + (0<<25) /*/ interlace mode - need to be corrected*/ + + (0<<26) // field legth polariry + + (0<<27) // field identification polariry + + (1<<28) // VIDRST detection mode + + (0<<29) // VIDRST detection mode + + (1<<30) // Horizontal counter preload + + (1<<31) // Vertical counter preload + ; + cregs.c2datactl = 1 // disable dither - propably not needed, we are already in YUV mode + + (1<<1) // Y filter enable + + (1<<2) // CbCr filter enable + + (0<<3) // subpicture enable (disabled) + + (0<<4) // NTSC enable (disabled - PAL) + + (0<<5) // C2 static subpicture enable (disabled) + + (0<<6) // C2 subpicture offset division (disabled) + + (0<<7) // 422 subformat selection ! +/* + (0<<8) // 15 bpp high alpha + + (0<<9) // 15 bpp high alpha + + (0<<10) // 15 bpp high alpha + + (0<<11) // 15 bpp high alpha + + (0<<12) // 15 bpp high alpha + + (0<<13) // 15 bpp high alpha + + (0<<14) // 15 bpp high alpha + + (0<<15) // 15 bpp high alpha + + (0<<16) // 15 bpp low alpha + + (0<<17) // 15 bpp low alpha + + (0<<18) // 15 bpp low alpha + + (0<<19) // 15 bpp low alpha + + (0<<20) // 15 bpp low alpha + + (0<<21) // 15 bpp low alpha + + (0<<22) // 15 bpp low alpha + + (0<<23) // 15 bpp low alpha + + (0<<24) // static subpicture key + + (0<<25) // static subpicture key + + (0<<26) // static subpicture key + + (0<<27) // static subpicture key + + (0<<28) // static subpicture key +*/ ; + break; + + case IMGFMT_UYVY: + cregs.c2ctl = 1 // CRTC2 enabled + + (1<<1) // external clock + + (0<<2) // external clock + + (1<<3) // pixel clock enable - not needed ??? + + (0<<4) // high prioryty req + + (1<<5) // high prioryty req + + (0<<6) // high prioryty req + + (1<<8) // high prioryty req max + + (0<<9) // high prioryty req max + + (0<<10) // high prioryty req max + + (0<<20) // CRTC1 to DAC + + (1<<21) // 422 mode + + (0<<22) // 422 mode + + (1<<23) // 422 mode + + (1<<24) // single chroma line for 420 mode - need to be corrected + + (1<<25) /*/ interlace mode - need to be corrected*/ + + (0<<26) // field legth polariry + + (0<<27) // field identification polariry + + (1<<28) // VIDRST detection mode + + (0<<29) // VIDRST detection mode + + (1<<30) // Horizontal counter preload + + (1<<31) // Vertical counter preload + ; + cregs.c2datactl = 0 // enable dither - propably not needed, we are already in YUV mode + + (1<<1) // Y filter enable + + (1<<2) // CbCr filter enable + + (0<<3) // subpicture enable (disabled) + + (0<<4) // NTSC enable (disabled - PAL) + + (0<<5) // C2 static subpicture enable (disabled) + + (0<<6) // C2 subpicture offset division (disabled) + + (1<<7) // 422 subformat selection ! +/* + (0<<8) // 15 bpp high alpha + + (0<<9) // 15 bpp high alpha + + (0<<10) // 15 bpp high alpha + + (0<<11) // 15 bpp high alpha + + (0<<12) // 15 bpp high alpha + + (0<<13) // 15 bpp high alpha + + (0<<14) // 15 bpp high alpha + + (0<<15) // 15 bpp high alpha + + (0<<16) // 15 bpp low alpha + + (0<<17) // 15 bpp low alpha + + (0<<18) // 15 bpp low alpha + + (0<<19) // 15 bpp low alpha + + (0<<20) // 15 bpp low alpha + + (0<<21) // 15 bpp low alpha + + (0<<22) // 15 bpp low alpha + + (0<<23) // 15 bpp low alpha + + (0<<24) // static subpicture key + + (0<<25) // static subpicture key + + (0<<26) // static subpicture key + + (0<<27) // static subpicture key + + (0<<28) // static subpicture key +*/ ; + break; + } + + cregs.c2hparam=((hdispend - 8) << 16) | (htotal - 8); + cregs.c2hsync=((hsyncend - 8) << 16) | (hsyncstart - 8); + + cregs.c2misc=0 // CRTCV2 656 togg f0 + +(0<<1) // CRTCV2 656 togg f0 + +(0<<2) // CRTCV2 656 togg f0 + +(0<<4) // CRTCV2 656 togg f1 + +(0<<5) // CRTCV2 656 togg f1 + +(0<<6) // CRTCV2 656 togg f1 + +(0<<8) // Hsync active high + +(0<<9) // Vsync active high + // 16-27 c2vlinecomp - nevim co tam dat + ; + cregs.c2offset=(regs.bespitch << 1); + + cregs.c2pl2startadd0=regs.besa1corg; +// cregs.c2pl2startadd1=regs.besa2corg; + cregs.c2pl3startadd0=regs.besa1c3org; +// cregs.c2pl3startadd1=regs.besa2c3org; + + cregs.c2preload=(vsyncstart << 16) | (hsyncstart); // from + + cregs.c2spicstartadd0=0; // not used +// cregs.c2spicstartadd1=0; // not used + + cregs.c2startadd0=regs.besa1org; +// cregs.c2startadd1=regs.besa2org; + + cregs.c2subpiclut=0; //not used + + cregs.c2vparam=((vdispend - 1) << 16) | (vtotal - 1); + cregs.c2vsync=((vsyncend - 1) << 16) | (vsyncstart - 1); +#endif /* CRTC2 */ + + mga_vid_write_regs(0); + return(0); +} + +int vixPlaybackOn(void) +{ + if (mga_verbose) printf("[mga] playback on\n"); + + vid_src_ready = 1; + if(vid_overlay_on) + { + regs.besctl |= 1; + mga_vid_write_regs(0); + } +#ifdef MGA_ALLOW_IRQ + if (mga_irq != -1) + enable_irq(); +#endif + mga_next_frame=0; + + return(0); +} + +int vixPlaybackOff(void) +{ + if (mga_verbose) printf("[mga] playback off\n"); + + vid_src_ready = 0; +#ifdef MGA_ALLOW_IRQ + if (mga_irq != -1) + disable_irq(); +#endif + regs.besctl &= ~1; + regs.besglobctl &= ~(1<<6); /* UYVY format selected */ + mga_vid_write_regs(0); + + return(0); +} + +int vixProbe(int verbose,int force) +{ + pciinfo_t lst[MAX_PCI_DEVICES]; + unsigned int i, num_pci; + int err; + + if (verbose) printf("[mga] probe\n"); + + mga_verbose = verbose; + + is_g400 = -1; + + err = pci_scan(lst, &num_pci); + if (err) + { + printf("[mga] Error occurred during pci scan: %s\n", strerror(err)); + return(err); + } + + if (mga_verbose) + printf("[mga] found %d pci devices\n", num_pci); + + for (i = 0; i < num_pci; i++) + { + if (mga_verbose > 1) + printf("[mga] pci[%d] vendor: %d device: %d\n", + i, lst[i].vendor, lst[i].device); + if (lst[i].vendor == VENDOR_MATROX) + { + if ((lst[i].command & PCI_COMMAND_IO) == 0) + { + printf("[mga] Device is disabled, ignoring\n"); + continue; + } + switch(lst[i].device) + { + case DEVICE_MATROX_MGA_G550_AGP: + printf("[mga] Found MGA G550\n"); + is_g400 = 1; + goto card_found; + case DEVICE_MATROX_MGA_G400_AGP: + printf("[mga] Found MGA G400/G450\n"); + is_g400 = 1; + goto card_found; + case DEVICE_MATROX_MGA_G200_AGP: + printf("[mga] Found MGA G200 AGP\n"); + is_g400 = 0; + goto card_found; + case DEVICE_MATROX_MGA_G200: + printf("[mga] Found MGA G200 PCI\n"); + is_g400 = 0; + goto card_found; + } + } + } + + if (is_g400 == -1) + { + if (verbose) printf("[mga] Can't find chip\n"); + return(ENXIO); + } + +card_found: + probed = 1; + memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); + + mga_cap.device_id = pci_info.device; /* set device id in capabilites */ + + return(0); +} + +int vixInit(void) +{ + unsigned int card_option = 0; + int err; + + if (mga_verbose) printf("[mga] init\n"); + + mga_vid_in_use = 0; + + printf("Matrox MGA G200/G400/G450 YUV Video interface v2.01 (c) Aaron Holtzman & A'rpi\n"); +#ifdef CRCT2 + printf("Driver compiled with TV-out (second-head) support\n"); +#endif + + if (!probed) + { + printf("[mga] driver was not probed but is being initializing\n"); + return(EINTR); + } + +#ifdef MGA_PCICONFIG_MEMDETECT + pci_config_read(pci_info.bus, pci_info.card, pci_info.func, + 0x40, 4, &card_option); + if (mga_verbose > 1) printf("[mga] OPTION word: 0x%08X mem: 0x%02X %s\n", card_option, + (card_option>>10)&0x17, ((card_option>>14)&1)?"SGRAM":"SDRAM"); +#endif + + if (mga_ram_size) + { + printf("[mga] RAMSIZE forced to %d MB\n", mga_ram_size); + } + else + { +#ifdef MGA_MEMORY_SIZE + mga_ram_size = MGA_MEMORY_SIZE; + printf("[mga] hard-coded RAMSIZE is %d MB\n", (unsigned int) mga_ram_size); +#else + if (is_g400) + { + switch((card_option>>10)&0x17) + { + // SDRAM: + case 0x00: + case 0x04: mga_ram_size = 16; break; + case 0x03: mga_ram_size = 32; break; + // SGRAM: + case 0x10: + case 0x14: mga_ram_size = 32; break; + case 0x11: + case 0x12: mga_ram_size = 16; break; + default: + mga_ram_size = 16; + printf("[mga] Couldn't detect RAMSIZE, assuming 16MB!\n"); + } + } + else + { + switch((card_option>>10)&0x17) + { +// case 0x10: +// case 0x13: mga_ram_size = 8; break; + default: mga_ram_size = 8; + } + } + +#if 0 +// printf("List resources -----------\n"); + for(temp=0;temp<DEVICE_COUNT_RESOURCE;temp++){ + struct resource *res=&pci_dev->resource[temp]; + if(res->flags){ + int size=(1+res->end-res->start)>>20; + printf("res %d: start: 0x%X end: 0x%X (%d MB) flags=0x%X\n",temp,res->start,res->end,size,res->flags); + if(res->flags&(IORESOURCE_MEM|IORESOURCE_PREFETCH)){ + if(size>mga_ram_size && size<=64) mga_ram_size=size; + } + } + } +#endif + + printf("[mga] detected RAMSIZE is %d MB\n", (unsigned int) mga_ram_size); +#endif + } + + if (mga_ram_size) + { + if ((mga_ram_size < 4) || (mga_ram_size > 64)) + { + printf("[mga] invalid RAMSIZE: %d MB\n", mga_ram_size); + return(EINVAL); + } + } + + if (mga_verbose > 1) printf("[mga] hardware addresses: mmio: %#x, framebuffer: %#x\n", + pci_info.base1, pci_info.base0); + + mga_mmio_base = map_phys_mem(pci_info.base1,0x4000); + mga_mem_base = map_phys_mem(pci_info.base0,mga_ram_size*1024*1024); + + if (mga_verbose > 1) printf("[mga] MMIO at %p, IRQ: %d, framebuffer: %p\n", + mga_mmio_base, mga_irq, mga_mem_base); + err = mtrr_set_type(pci_info.base0,mga_ram_size*1024*1024,MTRR_TYPE_WRCOMB); + if(!err) printf("[mga] Set write-combining type of video memory\n"); +#ifdef MGA_ALLOW_IRQ + if (mga_irq != -1) + { + int tmp = request_irq(mga_irq, mga_handle_irq, SA_INTERRUPT | SA_SHIRQ, "Syncfb Time Base", &mga_irq); + if (tmp) + { + printf("syncfb (mga): cannot register irq %d (Err: %d)\n", mga_irq, tmp); + mga_irq=-1; + } + else + { + printf("syncfb (mga): registered irq %d\n", mga_irq); + } + } + else + { + printf("syncfb (mga): No valid irq was found\n"); + mga_irq=-1; + } +#else + printf("syncfb (mga): IRQ disabled in mga_vid.c\n"); + mga_irq=-1; +#endif + + return(0); +} + +void vixDestroy(void) +{ + if (mga_verbose) printf("[mga] destroy\n"); + + /* FIXME turn off BES */ + vid_src_ready = 0; + regs.besctl &= ~1; + regs.besglobctl &= ~(1<<6); // UYVY format selected +// mga_config.colkey_on=0; //!!! + mga_vid_write_regs(1); + mga_vid_in_use = 0; + +#ifdef MGA_ALLOW_IRQ + if (mga_irq != -1) + free_irq(mga_irq, &mga_irq); +#endif + + if (mga_mmio_base) + unmap_phys_mem(mga_mmio_base, 0x4000); + if (mga_mem_base) + unmap_phys_mem(mga_mem_base, mga_ram_size); + return; +} + +int vixQueryFourcc(vidix_fourcc_t *to) +{ + if (mga_verbose) printf("[mga] query fourcc (%x)\n", to->fourcc); + + switch(to->fourcc) + { + case IMGFMT_YV12: + case IMGFMT_IYUV: + case IMGFMT_I420: + case IMGFMT_YUY2: + case IMGFMT_UYVY: + break; + default: + to->depth = to->flags = 0; + return(ENOTSUP); + } + + to->depth = VID_DEPTH_12BPP | + VID_DEPTH_15BPP | VID_DEPTH_16BPP | + VID_DEPTH_24BPP | VID_DEPTH_32BPP; + to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; + return(0); +} + +unsigned int vixGetVersion(void) +{ + return(VIDIX_VERSION); +} + +int vixGetCapability(vidix_capability_t *to) +{ + memcpy(to, &mga_cap, sizeof(vidix_capability_t)); + return(0); +} + +int vixGetGrKeys(vidix_grkey_t *grkey) +{ + memcpy(grkey, &mga_grkey, sizeof(vidix_grkey_t)); + return(0); +} + +int vixSetGrKeys(const vidix_grkey_t *grkey) +{ + memcpy(&mga_grkey, grkey, sizeof(vidix_grkey_t)); + mga_vid_write_regs(0); + return(0); +} + +int vixPlaybackSetEq( const vidix_video_eq_t * eq) +{ + /* contrast and brightness control isn't supported on G200 - alex */ + if (!is_g400) + { + if (mga_verbose) printf("[mga] equalizer isn't supported with G200\n"); + return(ENOTSUP); + } + + // only brightness&contrast are supported: + if(!(eq->cap & (VEQ_CAP_BRIGHTNESS|VEQ_CAP_CONTRAST))) + return(ENOTSUP); + + //regs.beslumactl = readl(mga_mmio_base + BESLUMACTL); +// printf("LUMA = %08X \n",regs.beslumactl); + if (eq->cap & VEQ_CAP_BRIGHTNESS) { + regs.beslumactl &= 0xFFFF; + regs.beslumactl |= (eq->brightness*255/2000)<<16; + } + if (eq->cap & VEQ_CAP_CONTRAST) { + regs.beslumactl &= 0xFFFF0000; + regs.beslumactl |= (128+eq->contrast*255/2000)&0xFFFF; + } + writel(regs.beslumactl,mga_mmio_base + BESLUMACTL); + + return(0); +} + +int vixPlaybackGetEq( vidix_video_eq_t * eq) +{ + /* contrast and brightness control isn't supported on G200 - alex */ + if (!is_g400) + { + if (mga_verbose) printf("[mga] equalizer isn't supported with G200\n"); + return(ENOTSUP); + } + +// regs.beslumactl = readl(mga_mmio_base + BESLUMACTL); + + eq->brightness = (signed short int)(regs.beslumactl >> 16) * 1000 / 128; + eq->contrast = (signed short int)(regs.beslumactl & 0xFFFF) * 1000 / 128 - 1000; + eq->cap = VEQ_CAP_BRIGHTNESS | VEQ_CAP_CONTRAST; + + printf("MGA GET_EQ: br=%d c=%d \n",eq->brightness,eq->contrast); + + return(0); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/vidix/nvidia_vid.c Sun Apr 01 00:02:43 2007 +0000 @@ -0,0 +1,935 @@ +/* + nvidia_vid - VIDIX based video driver for NVIDIA chips + Copyrights 2003 - 2004 Sascha Sommer. This file is based on sources from + RIVATV (rivatv.sf.net) + Licence: GPL + WARNING: THIS DRIVER IS IN BETA STAGE + + multi buffer support and TNT2 fixes by Dmitry Baryshkov +*/ + + +#include <errno.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <math.h> +#include <inttypes.h> +#include <unistd.h> + + +#include "vidix.h" +#include "fourcc.h" +#include "../libdha/libdha.h" +#include "../libdha/pci_ids.h" +#include "../libdha/pci_names.h" +#include "../config.h" +#include "../libavutil/common.h" +#include "../mpbswap.h" + + +pciinfo_t pci_info; + + +#define MAX_FRAMES 3 +#define NV04_BES_SIZE 1024*2000*4 + + +static vidix_capability_t nvidia_cap = { + "NVIDIA RIVA OVERLAY DRIVER", + "Sascha Sommer <saschasommer@freenet.de>", + TYPE_OUTPUT, + { 0, 0, 0, 0 }, + 2046, + 2046, + 4, + 4, + -1, + FLAG_UPSCALER|FLAG_DOWNSCALER, + VENDOR_NVIDIA2, + -1, + { 0, 0, 0, 0 } +}; + + +unsigned int vixGetVersion(void){ + return(VIDIX_VERSION); +} + + +#define NV_ARCH_03 0x03 +#define NV_ARCH_04 0x04 +#define NV_ARCH_10 0x10 +#define NV_ARCH_20 0x20 +#define NV_ARCH_30 0x30 + +// since no useful information whatsoever is passed +// to the equalizer functions we need this +static struct { + uint32_t lum; // luminance (brightness + contrast) + uint32_t chrom; // chrominance (saturation + hue) + uint8_t red_off; // for NV03/NV04 + uint8_t green_off; + uint8_t blue_off; + vidix_video_eq_t vals; +} eq; + +struct nvidia_cards { + unsigned short chip_id; + unsigned short arch; +}; + + +static struct nvidia_cards nvidia_card_ids[] = { + /*NV03*/ + {DEVICE_NVIDIA2_RIVA128, NV_ARCH_03}, + {DEVICE_NVIDIA2_RIVA128ZX,NV_ARCH_03}, + /*NV04*/ + {DEVICE_NVIDIA_NV4_RIVA_TNT,NV_ARCH_04}, + {DEVICE_NVIDIA_NV5_RIVA_TNT2,NV_ARCH_04}, + {DEVICE_NVIDIA_NV5_RIVA_TNT22,NV_ARCH_04}, + {DEVICE_NVIDIA_NV5_RIVA_TNT23,NV_ARCH_04}, + {DEVICE_NVIDIA_NV5_RIVA_TNT24,NV_ARCH_04}, + {DEVICE_NVIDIA_NV6_VANTA,NV_ARCH_04}, + {DEVICE_NVIDIA_RIVA_TNT2_MODEL,NV_ARCH_04}, + {DEVICE_NVIDIA_NV6_VANTA2,NV_ARCH_04}, + {DEVICE_NVIDIA_NV6_VANTA3,NV_ARCH_04}, + {DEVICE_NVIDIA_NV5_RIVA_TNT25,NV_ARCH_04}, + {DEVICE_NVIDIA2_TNT,NV_ARCH_04}, + {DEVICE_NVIDIA2_TNT2,NV_ARCH_04}, + {DEVICE_NVIDIA2_VTNT2,NV_ARCH_04}, + {DEVICE_NVIDIA2_UTNT2 ,NV_ARCH_04}, + {DEVICE_NVIDIA2_ITNT2,NV_ARCH_04}, + /*NV10*/ + {DEVICE_NVIDIA_NV10_GEFORCE_256,NV_ARCH_10}, + {DEVICE_NVIDIA_NV10_GEFORCE_2562,NV_ARCH_10}, + {DEVICE_NVIDIA_NV11_GEFORCE2_MX,NV_ARCH_10}, + {DEVICE_NVIDIA_NV11_GEFORCE2_MX2,NV_ARCH_10}, + {DEVICE_NVIDIA_NV11_GEFORCE2_GO,NV_ARCH_10}, + {DEVICE_NVIDIA_NV11_GEFORCE2_MXR ,NV_ARCH_10}, + {DEVICE_NVIDIA_NV15_GEFORCE2_GTS,NV_ARCH_10}, + {DEVICE_NVIDIA_NV15_GEFORCE2_TI,NV_ARCH_10}, + {DEVICE_NVIDIA_NV15_GEFORCE2_ULTRA,NV_ARCH_10}, + {DEVICE_NVIDIA_NV17_GEFORCE4_MX460,NV_ARCH_10}, + {DEVICE_NVIDIA_NV17_GEFORCE4_MX440,NV_ARCH_10}, + {DEVICE_NVIDIA_NV17_GEFORCE4_MX420,NV_ARCH_10}, + {DEVICE_NVIDIA_NV17_GEFORCE4_440,NV_ARCH_10}, + {DEVICE_NVIDIA_NV17_GEFORCE4_420,NV_ARCH_10}, + {DEVICE_NVIDIA_NV17_GEFORCE4_4202,NV_ARCH_10}, + {DEVICE_NVIDIA_NV17_GEFORCE4_4402,NV_ARCH_10}, + {DEVICE_NVIDIA_NV18_GEFORCE4_MX440,NV_ARCH_10}, + {DEVICE_NVIDIA_NV15_GEFORCE2,NV_ARCH_10}, + /*NV20*/ + {DEVICE_NVIDIA_NV20_GEFORCE3,NV_ARCH_20}, + {DEVICE_NVIDIA_NV20_GEFORCE3_TI200,NV_ARCH_20}, + {DEVICE_NVIDIA_NV20_GEFORCE3_TI500,NV_ARCH_20}, + {DEVICE_NVIDIA_NV25_GEFORCE4_TI4600,NV_ARCH_20}, + {DEVICE_NVIDIA_NV25_GEFORCE4_TI4400,NV_ARCH_20}, + {DEVICE_NVIDIA_NV25_GEFORCE4_TI4200,NV_ARCH_20}, + {DEVICE_NVIDIA_QUADRO4_900XGL,NV_ARCH_20}, + {DEVICE_NVIDIA_QUADRO4_750XGL,NV_ARCH_20}, + {DEVICE_NVIDIA_QUADRO4_700XGL,NV_ARCH_20}, + {DEVICE_NVIDIA_NV28_GEFORCE4_TI,NV_ARCH_20}, + {DEVICE_NVIDIA_NV28_GEFORCE4_TI2,NV_ARCH_20}, + {DEVICE_NVIDIA_NV28_GEFORCE4_TI3,NV_ARCH_20}, + {DEVICE_NVIDIA_NV28_GEFORCE4_TI4,NV_ARCH_20}, + {DEVICE_NVIDIA_NV28GL_QUADRO4_980,NV_ARCH_20}, + {DEVICE_NVIDIA_NV28GL_QUADRO4_780,NV_ARCH_20}, + /*NV30*/ + {DEVICE_NVIDIA_NV30_GEFORCE_FX,NV_ARCH_30}, + {DEVICE_NVIDIA_NV30_GEFORCE_FX2,NV_ARCH_30}, + {DEVICE_NVIDIA_NV30_GEFORCE_FX3,NV_ARCH_30}, + {DEVICE_NVIDIA_NV30GL_QUADRO_FX,NV_ARCH_30}, + {DEVICE_NVIDIA_NV30GL_QUADRO_FX2,NV_ARCH_30}, + {DEVICE_NVIDIA_NV31_GEFORCE_FX,NV_ARCH_30}, + {DEVICE_NVIDIA_NV31_GEFORCE_FX2,NV_ARCH_30}, + {DEVICE_NVIDIA_NV34_GEFORCE_FX,NV_ARCH_30}, + {DEVICE_NVIDIA_NV34_GEFORCE_FX2,NV_ARCH_30}, + {DEVICE_NVIDIA_NV34_GEFORCE_FX3,NV_ARCH_30}, + {DEVICE_NVIDIA_NV34M_GEFORCE_FX,NV_ARCH_30}, + {DEVICE_NVIDIA_NV34GL_QUADRO_FX,NV_ARCH_30}, + {DEVICE_NVIDIA_NV35_GEFORCE_FX,NV_ARCH_30}, + {DEVICE_NVIDIA_NV35_GEFORCE_FX2,NV_ARCH_30}, + {DEVICE_NVIDIA_NV35GL_QUADRO_FX,NV_ARCH_30}, + {DEVICE_NVIDIA_NV36_GEFORCE_FX,NV_ARCH_30}, +}; + + +static int find_chip(unsigned chip_id){ + unsigned i; + for(i = 0;i < sizeof(nvidia_card_ids)/sizeof(struct nvidia_cards);i++) + { + if(chip_id == nvidia_card_ids[i].chip_id)return i; + } + return -1; +} + +int vixProbe(int verbose, int force){ + pciinfo_t lst[MAX_PCI_DEVICES]; + unsigned i,num_pci; + int err; + + if (force) + printf("[nvidia_vid]: warning: forcing not supported yet!\n"); + err = pci_scan(lst,&num_pci); + if(err){ + printf("[nvidia_vid] Error occurred during pci scan: %s\n",strerror(err)); + return err; + } + else { + err = ENXIO; + for(i=0; i < num_pci; i++){ + if(lst[i].vendor == VENDOR_NVIDIA2 || lst[i].vendor == VENDOR_NVIDIA){ + int idx; + const char *dname; + idx = find_chip(lst[i].device); + if(idx == -1) + continue; + dname = pci_device_name(lst[i].vendor, lst[i].device); + dname = dname ? dname : "Unknown chip"; + printf("[nvidia_vid] Found chip: %s\n", dname); + if ((lst[i].command & PCI_COMMAND_IO) == 0){ + printf("[nvidia_vid] Device is disabled, ignoring\n"); + continue; + } + nvidia_cap.device_id = lst[i].device; + err = 0; + memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); + break; + } + } + } + if(err && verbose) printf("[nvidia_vid] Can't find chip\n"); + return err; +} + + + + +/* + * PCI-Memory IO access macros. + */ + +#define MEM_BARRIER() __asm__ __volatile__ ("" : : : "memory") + +#undef VID_WR08 +#define VID_WR08(p,i,val) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]=(val); }) +#undef VID_RD08 +#define VID_RD08(p,i) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]; }) + +#undef VID_WR32 +#define VID_WR32(p,i,val) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]=val; }) +#undef VID_RD32 +#define VID_RD32(p,i) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]; }) + +#define VID_AND32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)&(val)) +#define VID_OR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)|(val)) +#define VID_XOR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)^(val)) + + + + + + +struct rivatv_chip { + volatile uint32_t *PMC; /* general control */ + volatile uint32_t *PME; /* multimedia port */ + volatile uint32_t *PFB; /* framebuffer control */ + volatile uint32_t *PVIDEO; /* overlay control */ + volatile uint8_t *PCIO; /* SVGA (CRTC, ATTR) registers */ + volatile uint8_t *PVIO; /* SVGA (MISC, GRAPH, SEQ) registers */ + volatile uint32_t *PRAMIN; /* instance memory */ + volatile uint32_t *PRAMHT; /* hash table */ + volatile uint32_t *PRAMFC; /* fifo context table */ + volatile uint32_t *PRAMRO; /* fifo runout table */ + volatile uint32_t *PFIFO; /* fifo control region */ + volatile uint32_t *FIFO; /* fifo channels (USER) */ + volatile uint32_t *PGRAPH; /* graphics engine */ + + unsigned long fbsize; /* framebuffer size */ + int arch; /* compatible NV_ARCH_XX define */ + int realarch; /* real architecture */ + void (* lock) (struct rivatv_chip *, int); +}; +typedef struct rivatv_chip rivatv_chip; + + +struct rivatv_info { + unsigned int use_colorkey; + unsigned int colorkey; /* saved xv colorkey*/ + unsigned int vidixcolorkey; /*currently used colorkey*/ + unsigned int depth; + unsigned int format; + unsigned int pitch; + unsigned int width,height; + unsigned int d_width,d_height; /*scaled width && height*/ + unsigned int wx,wy; /*window x && y*/ + unsigned int screen_x; /*screen width*/ + unsigned int screen_y; /*screen height*/ + unsigned long buffer_size; /* size of the image buffer */ + struct rivatv_chip chip; /* NV architecture structure */ + void* video_base; /* virtual address of control region */ + void* control_base; /* virtual address of fb region */ + void* picture_base; /* direct pointer to video picture */ + unsigned long picture_offset; /* offset of video picture in frame buffer */ +// struct rivatv_dma dma; /* DMA structure */ + unsigned int cur_frame; + unsigned int num_frames; /* number of buffers */ + int bps; /* bytes per line */ +}; +typedef struct rivatv_info rivatv_info; + +//framebuffer size funcs +static unsigned long rivatv_fbsize_nv03 (struct rivatv_chip *chip){ + if (VID_RD32 (chip->PFB, 0) & 0x00000020) { + if (((VID_RD32 (chip->PMC, 0) & 0xF0) == 0x20) + && ((VID_RD32 (chip->PMC, 0) & 0x0F) >= 0x02)) { + /* SDRAM 128 ZX. */ + return ((1 << (VID_RD32 (chip->PFB, 0) & 0x03)) * 1024 * 1024); + } + else { + return 1024 * 1024 * 8; + } + } + else { + /* SGRAM 128. */ + switch (VID_RD32(chip->PFB, 0) & 0x00000003) { + case 0: + return 1024 * 1024 * 8; + break; + case 2: + return 1024 * 1024 * 4; + break; + default: + return 1024 * 1024 * 2; + break; + } + } +} +static unsigned long rivatv_fbsize_nv04 (struct rivatv_chip *chip){ + if (VID_RD32 (chip->PFB, 0) & 0x00000100) { + return ((VID_RD32 (chip->PFB, 0) >> 12) & 0x0F) * 1024 * 1024 * 2 + + 1024 * 1024 * 2; + } else { + switch (VID_RD32 (chip->PFB, 0) & 0x00000003) { + case 0: + return 1024 * 1024 * 32; + break; + case 1: + return 1024 * 1024 * 4; + break; + case 2: + return 1024 * 1024 * 8; + break; + case 3: + default: + return 1024 * 1024 * 16; + break; + } + } +} + +static unsigned long rivatv_fbsize_nv10 (struct rivatv_chip *chip){ + return VID_RD32 (chip->PFB, 0x20C) & 0xFFF00000; +} + +//lock funcs +static void rivatv_lock_nv03 (struct rivatv_chip *chip, int LockUnlock){ + VID_WR08 (chip->PVIO, 0x3C4, 0x06); + VID_WR08 (chip->PVIO, 0x3C5, LockUnlock ? 0x99 : 0x57); +} + +static void rivatv_lock_nv04 (struct rivatv_chip *chip, int LockUnlock){ + VID_WR08 (chip->PCIO, 0x3C4, 0x06); + VID_WR08 (chip->PCIO, 0x3C5, LockUnlock ? 0x99 : 0x57); + VID_WR08 (chip->PCIO, 0x3D4, 0x1F); + VID_WR08 (chip->PCIO, 0x3D5, LockUnlock ? 0x99 : 0x57); +} + + + + +/* Enable PFB (Framebuffer), PVIDEO (Overlay unit) and PME (Mediaport) if neccessary. */ +static void rivatv_enable_PMEDIA (struct rivatv_info *info){ + uint32_t reg; + + /* switch off interrupts once for a while */ +// VID_WR32 (info->chip.PME, 0x200140, 0x00); +// VID_WR32 (info->chip.PMC, 0x000140, 0x00); + + reg = VID_RD32 (info->chip.PMC, 0x000200); + + /* NV3 (0x10100010): NV03_PMC_ENABLE_PMEDIA, NV03_PMC_ENABLE_PFB, NV03_PMC_ENABLE_PVIDEO */ + + if ((reg & 0x10100010) != 0x10100010) { + printf("PVIDEO and PFB disabled, enabling...\n"); + VID_OR32 (info->chip.PMC, 0x000200, 0x10100010); + } + + /* save the current colorkey */ + switch (info->chip.arch ) { + case NV_ARCH_10: + case NV_ARCH_20: + case NV_ARCH_30: + /* NV_PVIDEO_COLOR_KEY */ + info->colorkey = VID_RD32 (info->chip.PVIDEO, 0xB00); + break; + case NV_ARCH_03: + case NV_ARCH_04: + /* NV_PVIDEO_KEY */ + info->colorkey = VID_RD32 (info->chip.PVIDEO, 0x240); + break; + } + + + /* re-enable interrupts again */ +// VID_WR32 (info->chip.PMC, 0x000140, 0x01); +// VID_WR32 (info->chip.PME, 0x200140, 0x01); +} + +/* Stop overlay video. */ +static void rivatv_overlay_stop (struct rivatv_info *info) { + switch (info->chip.arch ) { + case NV_ARCH_10: + case NV_ARCH_20: + case NV_ARCH_30: + /* NV_PVIDEO_COLOR_KEY */ + /* Xv-Extension-Hack: Restore previously saved value. */ + VID_WR32 (info->chip.PVIDEO, 0xB00, info->colorkey); + /* NV_PVIDEO_STOP */ + VID_OR32 (info->chip.PVIDEO, 0x704, 0x11); + /* NV_PVIDEO_BUFFER */ + VID_AND32 (info->chip.PVIDEO, 0x700, ~0x11); + /* NV_PVIDEO_INTR_EN_BUFFER */ +// VID_AND32 (info->chip.PVIDEO, 0x140, ~0x11); + break; + case NV_ARCH_03: + case NV_ARCH_04: + /* NV_PVIDEO_KEY */ + VID_WR32 (info->chip.PVIDEO, 0x240, info->colorkey); + /* NV_PVIDEO_OVERLAY_VIDEO_OFF */ + VID_AND32 (info->chip.PVIDEO, 0x244, ~0x01); + /* NV_PVIDEO_INTR_EN_0_NOTIFY */ +// VID_AND32 (info->chip.PVIDEO, 0x140, ~0x01); + /* NV_PVIDEO_OE_STATE */ + VID_WR32 (info->chip.PVIDEO, 0x224, 0); + /* NV_PVIDEO_SU_STATE */ + VID_WR32 (info->chip.PVIDEO, 0x228, 0); + /* NV_PVIDEO_RM_STATE */ + VID_WR32 (info->chip.PVIDEO, 0x22C, 0); + break; + } +} + +/* Get pan offset of the physical screen. */ +static uint32_t rivatv_overlay_pan (struct rivatv_info *info){ + uint32_t pan; + info->chip.lock (&info->chip, 0); + VID_WR08 (info->chip.PCIO, 0x3D4, 0x0D); + pan = VID_RD08 (info->chip.PCIO, 0x3D5); + VID_WR08 (info->chip.PCIO, 0x3D4, 0x0C); + pan |= VID_RD08 (info->chip.PCIO, 0x3D5) << 8; + VID_WR08 (info->chip.PCIO, 0x3D4, 0x19); + pan |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0x1F) << 16; + VID_WR08 (info->chip.PCIO, 0x3D4, 0x2D); + pan |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0x60) << 16; + return pan << 2; +} + +/* Compute and set colorkey depending on the colour depth. */ +static void rivatv_overlay_colorkey (rivatv_info* info, unsigned int chromakey){ + uint32_t r, g, b, key = 0; + + r = (chromakey & 0x00FF0000) >> 16; + g = (chromakey & 0x0000FF00) >> 8; + b = chromakey & 0x000000FF; + switch (info->depth) { + case 15: + key = ((r >> 3) << 10) | ((g >> 3) << 5) | ((b >> 3)); +#ifndef WIN32 + key = key | 0x00008000; +#endif + break; + case 16: // XXX unchecked + key = ((r >> 3) << 11) | ((g >> 2) << 5) | ((b >> 3)); +#ifndef WIN32 + key = key | 0x00008000; +#endif + break; + case 24: // XXX unchecked, maybe swap order of masking - FIXME Can the card be in 24 bit mode anyway? + key = (chromakey & 0x00FFFFFF) | 0x00800000; + break; + case 32: + key = chromakey; +#ifndef WIN32 + key = key | 0x80000000; +#endif + break; + } + //printf("[nvidia_vid] depth=%d %08X \n", info->depth, chromakey); + switch (info->chip.arch) { + case NV_ARCH_10: + case NV_ARCH_20: + case NV_ARCH_30: + VID_WR32 (info->chip.PVIDEO, 0xB00, key); + break; + case NV_ARCH_03: + case NV_ARCH_04: + VID_WR32 (info->chip.PVIDEO, 0x240, key); + break; + } +} + +static void nv_getscreenproperties(struct rivatv_info *info){ + uint32_t bpp=0,x; + info->chip.lock(&info->chip, 0); + /*get screen depth*/ + VID_WR08(info->chip.PCIO, 0x03D4,0x28); + bpp = VID_RD08(info->chip.PCIO,0x03D5)&0x3; + if((bpp == 2) && (VID_RD32(info->chip.PVIDEO,0x600) & 0x00001000) == 0x0)info->depth=15; + else info->depth = 0x04 << bpp; + /*get screen width*/ + VID_WR08(info->chip.PCIO, 0x03D4, 0x1); + info->screen_x = (1 + VID_RD08(info->chip.PCIO, 0x3D5)) * 8; + /*get screen height*/ + /* get first 8 bits in VT_DISPLAY_END*/ + VID_WR08(info->chip.PCIO, 0x03D4, 0x12); + info->screen_y = VID_RD08(info->chip.PCIO,0x03D5); + VID_WR08(info->chip.PCIO,0x03D4,0x07); + /* get 9th bit in CRTC_OVERFLOW*/ + info->screen_y |= (VID_RD08(info->chip.PCIO,0x03D5) &0x02)<<7; + /* and the 10th in CRTC_OVERFLOW*/ + info->screen_y |=(VID_RD08(info->chip.PCIO,0x03D5) &0x40)<<3; + ++info->screen_y; + + /* NV_PCRTC_OFFSET */ + VID_WR08 (info->chip.PCIO, 0x3D4, 0x13); + x = VID_RD08 (info->chip.PCIO, 0x3D5); + /* NV_PCRTC_REPAINT0_OFFSET_10_8 */ + VID_WR08 (info->chip.PCIO, 0x3D4, 0x19); + x |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0xE0) << 3; + /* NV_PCRTC_EXTRA_OFFSET_11 */ + VID_WR08 (info->chip.PCIO, 0x3D4, 0x25); + x |= (VID_RD08 (info->chip.PCIO, 0x3D5) & 0x20) << 6; x <<= 3; + info->bps = x * bpp; +} + + + + +/* Start overlay video. */ +static void rivatv_overlay_start (struct rivatv_info *info,int bufno){ + uint32_t base, size, offset, xscale, yscale, pan; + uint32_t value; + int x=info->wx, y=info->wy; + int lwidth=info->d_width, lheight=info->d_height; + + size = info->buffer_size; + base = info->picture_offset; + offset = bufno*size; + /*update depth & dimensions here because it may change with vo vesa or vo fbdev*/ + nv_getscreenproperties(info); + + if(info->depth){ + /* get pan offset of the physical screen */ + pan = rivatv_overlay_pan (info); + /* adjust window position depending on the pan offset */ + if (info->bps != 0) + { + x = info->wx - (pan % info->bps) * 8 / info->depth; + y = info->wy - (pan / info->bps); + } + } else { + // we can't adjust the window position correctly in textmode + // setting y to 8 seems to work ok, though + if(info->chip.arch < NV_ARCH_10 && y < 8) y = 8; + } + + /* adjust negative output window variables */ + if (x < 0) { + lwidth = info->d_width + x; + offset += (-x * info->width / info->d_width) << 1; +// offset += (-window->x * port->vld_width / window->width) << 1; + x = 0; + } + if (y < 0) { + lheight = info->d_height + y; + offset += (-y * info->height / info->d_height * info->width) << 1; +// offset += (-window->y * port->vld_height / window->height * port->org_width) << 1; + y = 0; + } + + switch (info->chip.arch) { + case NV_ARCH_10: + case NV_ARCH_20: + case NV_ARCH_30: + + /* NV_PVIDEO_BASE */ + VID_WR32 (info->chip.PVIDEO, 0x900 + 0, base + offset); + //VID_WR32 (info->chip.PVIDEO, 0x900 + 4, base); + /* NV_PVIDEO_LIMIT */ + VID_WR32 (info->chip.PVIDEO, 0x908 + 0, base + offset + size - 1); + //VID_WR32 (info->chip.PVIDEO, 0x908 + 4, base + size - 1); + + /* extra code for NV20 && NV30 architectures */ + if (info->chip.arch == NV_ARCH_20 || info->chip.arch == NV_ARCH_30) { + VID_WR32 (info->chip.PVIDEO, 0x800 + 0, base + offset); + //VID_WR32 (info->chip.PVIDEO, 0x800 + 4, base); + VID_WR32 (info->chip.PVIDEO, 0x808 + 0, base + offset + size - 1); + //VID_WR32 (info->chip.PVIDEO, 0x808 + 4, base + size - 1); + } + + /* NV_PVIDEO_LUMINANCE */ + VID_WR32 (info->chip.PVIDEO, 0x910 + 0, eq.lum); + //VID_WR32 (info->chip.PVIDEO, 0x910 + 4, 0x00001000); + /* NV_PVIDEO_CHROMINANCE */ + VID_WR32 (info->chip.PVIDEO, 0x918 + 0, eq.chrom); + //VID_WR32 (info->chip.PVIDEO, 0x918 + 4, 0x00001000); + + /* NV_PVIDEO_OFFSET */ + VID_WR32 (info->chip.PVIDEO, 0x920 + 0, 0x0); + //VID_WR32 (info->chip.PVIDEO, 0x920 + 4, offset + pitch); + /* NV_PVIDEO_SIZE_IN */ + VID_WR32 (info->chip.PVIDEO, 0x928 + 0, ((info->height) << 16) | info->width); + //VID_WR32 (info->chip.PVIDEO, 0x928 + 4, ((port->org_height/2) << 16) | port->org_width); + /* NV_PVIDEO_POINT_IN */ + VID_WR32 (info->chip.PVIDEO, 0x930 + 0, 0x00000000); + //VID_WR32 (info->chip.PVIDEO, 0x930 + 4, 0x00000000); + /* NV_PVIDEO_DS_DX_RATIO */ + VID_WR32 (info->chip.PVIDEO, 0x938 + 0, (info->width << 20) / info->d_width); + //VID_WR32 (info->chip.PVIDEO, 0x938 + 4, (port->org_width << 20) / window->width); + /* NV_PVIDEO_DT_DY_RATIO */ + VID_WR32 (info->chip.PVIDEO, 0x940 + 0, ((info->height) << 20) / info->d_height); + //VID_WR32 (info->chip.PVIDEO, 0x940 + 4, ((port->org_height/2) << 20) / window->height); + + /* NV_PVIDEO_POINT_OUT */ + VID_WR32 (info->chip.PVIDEO, 0x948 + 0, ((y + 0) << 16) | x); + //VID_WR32 (info->chip.PVIDEO, 0x948 + 4, ((y + 0) << 16) | x); + /* NV_PVIDEO_SIZE_OUT */ + VID_WR32 (info->chip.PVIDEO, 0x950 + 0, (lheight << 16) | lwidth); + //VID_WR32 (info->chip.PVIDEO, 0x950 + 4, (height << 16) | width); + + /* NV_PVIDEO_FORMAT */ + value = info->pitch; + if(info->use_colorkey)value |= 1 << 20; + if(info->format == IMGFMT_YUY2)value |= 1 << 16; + VID_WR32 (info->chip.PVIDEO, 0x958 + 0, value); + //VID_WR32 (info->chip.PVIDEO, 0x958 + 4, (pitch << 1) | 0x00100000); + + /* NV_PVIDEO_INTR_EN_BUFFER */ +// VID_OR32 (info->chip.PVIDEO, 0x140, 0x01/*0x11*/); + /* NV_PVIDEO_STOP */ + VID_WR32 (info->chip.PVIDEO, 0x704,0x0); + /* NV_PVIDEO_BUFFER */ + VID_WR32 (info->chip.PVIDEO, 0x700, 0x01/*0x11*/); + break; + + case NV_ARCH_03: + case NV_ARCH_04: + + + /* NV_PVIDEO_OE_STATE */ + VID_WR32 (info->chip.PVIDEO, 0x224, 0); + /* NV_PVIDEO_SU_STATE */ + VID_WR32 (info->chip.PVIDEO, 0x228, 0); + /* NV_PVIDEO_RM_STATE */ + VID_WR32 (info->chip.PVIDEO, 0x22C, 0); + + /* NV_PVIDEO_BUFF0_START_ADDRESS */ + VID_WR32 (info->chip.PVIDEO, 0x20C + 0, base + offset + 0); + VID_WR32 (info->chip.PVIDEO, 0x20C + 4, base + offset + 0); + /* NV_PVIDEO_BUFF0_PITCH_LENGTH */ + VID_WR32 (info->chip.PVIDEO, 0x214 + 0, info->pitch); + VID_WR32 (info->chip.PVIDEO, 0x214 + 4, info->pitch); + + /* NV_PVIDEO_WINDOW_START */ + VID_WR32 (info->chip.PVIDEO, 0x230, (y << 16) | x); + /* NV_PVIDEO_WINDOW_SIZE */ + VID_WR32 (info->chip.PVIDEO, 0x234, (lheight << 16) | lwidth); + /* NV_PVIDEO_STEP_SIZE */ + yscale = ((info->height - 1) << 11) / (info->d_height - 1); + xscale = ((info->width - 1) << 11) / (info->d_width - 1); + VID_WR32 (info->chip.PVIDEO, 0x200, (yscale << 16) | xscale); + + /* NV_PVIDEO_RED_CSC_OFFSET */ + VID_WR32 (info->chip.PVIDEO, 0x280, eq.red_off); + /* NV_PVIDEO_GREEN_CSC_OFFSET */ + VID_WR32 (info->chip.PVIDEO, 0x284, eq.green_off); + /* NV_PVIDEO_BLUE_CSC_OFFSET */ + VID_WR32 (info->chip.PVIDEO, 0x288, eq.blue_off); + /* NV_PVIDEO_CSC_ADJUST */ + VID_WR32 (info->chip.PVIDEO, 0x28C, 0x00000); /* No colour correction! */ + + /* NV_PVIDEO_CONTROL_Y (BLUR_ON, LINE_HALF) */ + VID_WR32 (info->chip.PVIDEO, 0x204, 0x001); + /* NV_PVIDEO_CONTROL_X (WEIGHT_HEAVY, SHARPENING_ON, SMOOTHING_ON) */ + VID_WR32 (info->chip.PVIDEO, 0x208, 0x111); /*directx overlay 0x110 */ + + /* NV_PVIDEO_FIFO_BURST_LENGTH */ + VID_WR32 (info->chip.PVIDEO, 0x23C, 0x03); + /* NV_PVIDEO_FIFO_THRES_SIZE */ + VID_WR32 (info->chip.PVIDEO, 0x238, 0x38); /*windows uses 0x40*/ + + /* NV_PVIDEO_BUFF0_OFFSET */ + VID_WR32 (info->chip.PVIDEO, 0x21C + 0, 0); + VID_WR32 (info->chip.PVIDEO, 0x21C + 4, 0); + + /* NV_PVIDEO_INTR_EN_0_NOTIFY_ENABLED */ +// VID_OR32 (info->chip.PVIDEO, 0x140, 0x01); + + /* NV_PVIDEO_OVERLAY (KEY_ON, VIDEO_ON, FORMAT_CCIR) */ + value = 0x1; /*video on*/ + if(info->format==IMGFMT_YUY2)value |= 0x100; + if(info->use_colorkey)value |=0x10; + VID_WR32 (info->chip.PVIDEO, 0x244, value); + + /* NV_PVIDEO_SU_STATE */ + VID_XOR32 (info->chip.PVIDEO, 0x228, 1 << 16); + break; + } + /*set colorkey*/ + rivatv_overlay_colorkey(info,info->vidixcolorkey); + +} + + + + + + + +static rivatv_info* info; + + + + +int vixInit(void){ + int mtrr; + info = calloc(1,sizeof(rivatv_info)); + info->control_base = map_phys_mem(pci_info.base0, 0x00C00000 + 0x00008000); + info->chip.arch = nvidia_card_ids[find_chip(pci_info.device)].arch; + printf("[nvidia_vid] arch %x register base %p\n",info->chip.arch,info->control_base); + info->chip.PFIFO = (uint32_t *) (info->control_base + 0x00002000); + info->chip.FIFO = (uint32_t *) (info->control_base + 0x00800000); + info->chip.PMC = (uint32_t *) (info->control_base + 0x00000000); + info->chip.PFB = (uint32_t *) (info->control_base + 0x00100000); + info->chip.PME = (uint32_t *) (info->control_base + 0x00000000); + info->chip.PCIO = (uint8_t *) (info->control_base + 0x00601000); + info->chip.PVIO = (uint8_t *) (info->control_base + 0x000C0000); + info->chip.PGRAPH = (uint32_t *) (info->control_base + 0x00400000); + /* setup chip specific functions */ + switch (info->chip.arch) { + case NV_ARCH_03: + info->chip.lock = rivatv_lock_nv03; + info->chip.fbsize = rivatv_fbsize_nv03 (&info->chip); + info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00680000); + break; + case NV_ARCH_04: + info->chip.lock = rivatv_lock_nv04; + info->chip.fbsize = rivatv_fbsize_nv04 (&info->chip); + info->chip.PRAMIN = (uint32_t *) (info->control_base + 0x00700000); + info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00680000); + break; + case NV_ARCH_10: + case NV_ARCH_20: + case NV_ARCH_30: + info->chip.lock = rivatv_lock_nv04; + info->chip.fbsize = rivatv_fbsize_nv10 (&info->chip); + info->chip.PRAMIN = (uint32_t *) (info->control_base + 0x00700000); + info->chip.PVIDEO = (uint32_t *) (info->control_base + 0x00008000); + break; + } + switch (info->chip.arch) { + case NV_ARCH_03: + { + /* This maps framebuffer @6MB, thus 2MB are left for video. */ + info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize); + /* This may trash your screen for resolutions greater than 1024x768, sorry. */ + info->picture_offset = 1024*768* 4 * ((info->chip.fbsize > 4194304)?2:1); + info->picture_base = info->video_base + info->picture_offset; + info->chip.PRAMIN = (uint32_t *) (info->video_base + 0x00C00000); + break; + } + case NV_ARCH_04: + case NV_ARCH_10: + case NV_ARCH_20: + case NV_ARCH_30: + { + info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize); + info->picture_offset = info->chip.fbsize - NV04_BES_SIZE; + if(info->chip.fbsize > 16*1024*1024) + info->picture_offset -= NV04_BES_SIZE; +// info->picture_base = (unsigned long)map_phys_mem(pci_info.base1+info->picture_offset,NV04_BES_SIZE); + info->picture_base = info->video_base + info->picture_offset; + break; + } + } + + printf("[nvidia_vid] detected memory size %u MB\n",(uint32_t)(info->chip.fbsize /1024/1024)); + + if ((mtrr = mtrr_set_type(pci_info.base1, info->chip.fbsize, MTRR_TYPE_WRCOMB))!= 0) + printf("[nvidia_vid] unable to setup MTRR: %s\n", strerror(mtrr)); + else + printf("[nvidia_vid] MTRR set up\n"); + + nv_getscreenproperties(info); + if(!info->depth)printf("[nvidia_vid] text mode: %ux%u\n",info->screen_x,info->screen_y); + else printf("[nvidia_vid] video mode: %ux%u@%u\n",info->screen_x,info->screen_y, info->depth); + + + rivatv_enable_PMEDIA(info); + info->cur_frame = 0; + info->use_colorkey = 0; + + eq.lum = 0x00001000; + eq.chrom = 0x00001000; + memset(&eq.vals, 0, sizeof(vidix_video_eq_t)); + eq.vals.cap = VEQ_CAP_BRIGHTNESS; + if (info->chip.arch > NV_ARCH_04) + eq.vals.cap |= VEQ_CAP_CONTRAST | VEQ_CAP_SATURATION | VEQ_CAP_HUE; + eq.red_off = 0x69; + eq.green_off = 0x3e; + eq.blue_off = 0x89; + return 0; +} + +void vixDestroy(void){ + unmap_phys_mem(info->control_base ,0x00C00000 + 0x00008000); + unmap_phys_mem(info->video_base, info->chip.fbsize); + free(info); +} + +int vixGetCapability(vidix_capability_t *to){ + memcpy(to, &nvidia_cap, sizeof(vidix_capability_t)); + return 0; +} + +inline static int is_supported_fourcc(uint32_t fourcc) +{ + if (fourcc == IMGFMT_UYVY || fourcc == IMGFMT_YUY2) + return 1; + else + return 0; +} + +int vixQueryFourcc(vidix_fourcc_t *to){ + if(is_supported_fourcc(to->fourcc)){ + to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | + VID_DEPTH_4BPP | VID_DEPTH_8BPP | + VID_DEPTH_12BPP| VID_DEPTH_15BPP| + VID_DEPTH_16BPP| VID_DEPTH_24BPP| + VID_DEPTH_32BPP; + to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; + return 0; + } + else to->depth = to->flags = 0; + return ENOSYS; +} + +int vixConfigPlayback(vidix_playback_t *vinfo){ + uint32_t i; + printf("called %s\n", __FUNCTION__); + if (! is_supported_fourcc(vinfo->fourcc)) + return ENOSYS; + + info->width = vinfo->src.w; + info->height = vinfo->src.h; + + info->d_width = vinfo->dest.w; + info->d_height = vinfo->dest.h; + info->wx = vinfo->dest.x; + info->wy = vinfo->dest.y; + info->format = vinfo->fourcc; + + printf("[nvidia_vid] setting up a %dx%d-%dx%d video window (src %dx%d), format 0x%X\n", + info->d_width, info->d_height, info->wx, info->wy, info->width, info->height, vinfo->fourcc); + + + vinfo->dga_addr=info->picture_base; + + switch (vinfo->fourcc) + { + case IMGFMT_YUY2: + case IMGFMT_UYVY: + + vinfo->dest.pitch.y = 64; + vinfo->dest.pitch.u = 0; + vinfo->dest.pitch.v = 0; + + vinfo->offset.y = 0; + vinfo->offset.v = 0; + vinfo->offset.u = 0; + info->pitch = ((info->width << 1) + (vinfo->dest.pitch.y-1)) & ~(vinfo->dest.pitch.y-1); + vinfo->frame_size = info->pitch * info->height; + break; + } + info->buffer_size = vinfo->frame_size; + info->num_frames = vinfo->num_frames= (info->chip.fbsize - info->picture_offset)/vinfo->frame_size; + if(vinfo->num_frames > MAX_FRAMES)vinfo->num_frames = MAX_FRAMES; +// vinfo->num_frames = 1; +// printf("[nvidia_vid] Number of frames %i\n",vinfo->num_frames); + for(i=0;i <vinfo->num_frames;i++)vinfo->offsets[i] = vinfo->frame_size*i; + return 0; +} + +int vixPlaybackOn(void){ + rivatv_overlay_start(info,info->cur_frame); + return 0; +} + +int vixPlaybackOff(void){ + rivatv_overlay_stop(info); + return 0; +} + +int vixSetGrKeys( const vidix_grkey_t * grkey){ + if (grkey->ckey.op == CKEY_FALSE) + { + info->use_colorkey = 0; + printf("[nvidia_vid] colorkeying disabled\n"); + } + else { + info->use_colorkey = 1; + info->vidixcolorkey = ((grkey->ckey.red<<16)|(grkey->ckey.green<<8)|grkey->ckey.blue); + printf("[nvidia_vid] set colorkey 0x%x\n",info->vidixcolorkey); + } + if(info->d_width && info->d_height)rivatv_overlay_start(info,0); + return 0; +} + +int vixPlaybackFrameSelect(unsigned int frame){ +// printf("selecting buffer %d\n", frame); + rivatv_overlay_start(info, frame); + if (info->num_frames >= 1) + info->cur_frame = frame/*(frame+1)%info->num_frames*/; + return 0; +} + +int vixPlaybackSetEq(const vidix_video_eq_t *eq_parm) { + double angle; + int16_t chrom_cos, chrom_sin; + if (eq_parm->cap & VEQ_CAP_BRIGHTNESS) + eq.vals.brightness = eq_parm->brightness; + if (eq_parm->cap & VEQ_CAP_CONTRAST) + eq.vals.contrast = eq_parm->contrast; + if (eq_parm->cap & VEQ_CAP_SATURATION) + eq.vals.saturation = eq_parm->saturation; + if (eq_parm->cap & VEQ_CAP_HUE) + eq.vals.hue = eq_parm->hue; + eq.lum = (((eq.vals.brightness * 512 + 500) / 1000) << 16) | + ((((eq.vals.contrast + 1000) * 8191 + 1000) / 2000) & 0xffff); + angle = (double)eq.vals.hue / 1000.0 * 3.1415927; + chrom_cos = ((eq.vals.saturation + 1000) * 8191 * cos(angle) + 1000) / 2000; + chrom_sin = ((eq.vals.saturation + 1000) * 8191 * sin(angle) + 1000) / 2000; + eq.chrom = chrom_sin << 16 | chrom_cos; + eq.red_off = 0x69 - eq.vals.brightness * 62 / 1000; + eq.green_off = 0x3e + eq.vals.brightness * 62 / 1000; + eq.blue_off = 0x89 - eq.vals.brightness * 62 / 1000; + return 0; +} + +int vixPlaybackGetEq(vidix_video_eq_t *eq_parm) { + memcpy(eq_parm, &eq.vals, sizeof(vidix_video_eq_t)); + return 0; +} +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/vidix/pm3_regs.h Sun Apr 01 00:02:43 2007 +0000 @@ -0,0 +1,1113 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/glint/pm3_regs.h,v 1.9 2001/11/20 00:09:15 alanh Exp $ */ + +/* + * glint register file + * + * Copyright by Sven Luther + * Authors: Sven Luther, <luther@dpt-info.u-strasbg.fr> + * Thomas Witzel, <twitzel@nmr.mgh.harvard.edu> + * + * this work is sponsored by Appian Graphics. + * + */ + +#ifndef _PM3_REG_H_ +#define _PM3_REG_H_ + +/********************************************** +* GLINT Permedia3 Control Status registers * +***********************************************/ +/* Control Status Registers */ +#define PM3ResetStatus 0x0000 +#define PM3IntEnable 0x0008 +#define PM3IntFlags 0x0010 +#define PM3InFIFOSpace 0x0018 +#define PM3OutFIFOWords 0x0020 +#define PM3DMAAddress 0x0028 +#define PM3DMACount 0x0030 +#define PM3ErrorFlags 0x0038 +#define PM3VClkCtl 0x0040 +#define PM3TestRegister 0x0048 +#define PM3Aperture0 0x0050 +#define PM3Aperture1 0x0058 +#define PM3DMAControl 0x0060 +#define PM3FIFODis 0x0068 +#define PM3ChipConfig 0x0070 +#define PM3AGPControl 0x0078 + +#define PM3GPOutDMAAddress 0x0080 +#define PM3PCIFeedbackCount 0x0088 +#define PM3PCIAbortStatus 0x0090 +#define PM3PCIAbortAddress 0x0098 + +#define PM3PCIPLLStatus 0x00f0 + +#define PM3HostTextureAddress 0x0100 +#define PM3TextureDownloadControl 0x0108 +#define PM3TextureOperation 0x0110 +#define PM3LogicalTexturePage 0x0118 +#define PM3TexDMAAddress 0x0120 +#define PM3TexFIFOSpace 0x0128 + +/********************************************** +* GLINT Permedia3 Region 0 Bypass Controls * +***********************************************/ +#define PM3ByAperture1Mode 0x0300 + #define PM3ByApertureMode_BYTESWAP_ABCD (0<<0) + #define PM3ByApertureMode_BYTESWAP_BADC (1<<0) + #define PM3ByApertureMode_BYTESWAP_CDAB (2<<0) + #define PM3ByApertureMode_BYTESWAP_DCBA (3<<0) + #define PM3ByApertureMode_PATCH_DISABLE (0<<2) + #define PM3ByApertureMode_PATCH_ENABLE (1<<2) + #define PM3ByApertureMode_FORMAT_RAW (0<<3) + #define PM3ByApertureMode_FORMAT_YUYV (1<<3) + #define PM3ByApertureMode_FORMAT_UYVY (2<<3) + #define PM3ByApertureMode_PIXELSIZE_8BIT (0<<5) + #define PM3ByApertureMode_PIXELSIZE_16BIT (1<<5) + #define PM3ByApertureMode_PIXELSIZE_32BIT (2<<5) + #define PM3ByApertureMode_EFFECTIVE_STRIDE_1024 (0<<7) + #define PM3ByApertureMode_EFFECTIVE_STRIDE_2048 (1<<7) + #define PM3ByApertureMode_EFFECTIVE_STRIDE_4096 (2<<7) + #define PM3ByApertureMode_EFFECTIVE_STRIDE_8192 (3<<7) + #define PM3ByApertureMode_PATCH_OFFSET_X(off) (((off)&7f)<<9) + #define PM3ByApertureMode_PATCH_OFFSET_Y(off) (((off)&7f)<<16) + #define PM3ByApertureMode_FRAMEBUFFER (0<<21) + #define PM3ByApertureMode_LOCALBUFFER (1<<21) + #define PM3ByApertureMode_DOUBLE_WRITE_OFF (0<<22) + #define PM3ByApertureMode_DOUBLE_WRITE_1MB (1<<22) + #define PM3ByApertureMode_DOUBLE_WRITE_2MB (2<<22) + #define PM3ByApertureMode_DOUBLE_WRITE_4MB (3<<22) + #define PM3ByApertureMode_DOUBLE_WRITE_8MB (4<<22) + #define PM3ByApertureMode_DOUBLE_WRITE_16MB (5<<22) + #define PM3ByApertureMode_DOUBLE_WRITE_32MB (6<<22) + +#define PM3ByAperture2Mode 0x0328 + +/********************************************** +* GLINT Permedia3 Memory Control (0x1000) * +***********************************************/ +#define PM3MemCounter 0x1000 +#define PM3MemBypassWriteMask 0x1008 +#define PM3MemScratch 0x1010 +#define PM3LocalMemCaps 0x1018 + #define PM3LocalMemCaps_NoWriteMask (1<<28) +#define PM3LocalMemTimings 0x1020 +#define PM3LocalMemControl 0x1028 +#define PM3LocalMemRefresh 0x1030 +#define PM3LocalMemPowerDown 0x1038 +#define PM3RemoteMemControl 0x1100 + +/********************************************** +* GLINT Permedia3 Video Control (0x3000) * +***********************************************/ + +#define PM3ScreenBase 0x3000 +#define PM3ScreenStride 0x3008 +#define PM3HTotal 0x3010 +#define PM3HgEnd 0x3018 +#define PM3HbEnd 0x3020 +#define PM3HsStart 0x3028 +#define PM3HsEnd 0x3030 +#define PM3VTotal 0x3038 +#define PM3VbEnd 0x3040 +#define PM3VsStart 0x3048 +#define PM3VsEnd 0x3050 +#define PM3VideoControl 0x3058 + #define PM3VideoControl_DISABLE (0<<0) + #define PM3VideoControl_ENABLE (1<<0) + #define PM3VideoControl_BLANK_ACTIVE_HIGH (0<<1) + #define PM3VideoControl_BLANK_ACTIVE_LOW (1<<1) + #define PM3VideoControl_LINE_DOUBLE_OFF (0<<2) + #define PM3VideoControl_LINE_DOUBLE_ON (1<<2) + #define PM3VideoControl_HSYNC_FORCE_HIGH (0<<3) + #define PM3VideoControl_HSYNC_ACTIVE_HIGH (1<<3) + #define PM3VideoControl_HSYNC_FORCE_LOW (2<<3) + #define PM3VideoControl_HSYNC_ACTIVE_LOW (3<<3) + #define PM3VideoControl_VSYNC_FORCE_HIGH (0<<5) + #define PM3VideoControl_VSYNC_ACTIVE_HIGH (1<<5) + #define PM3VideoControl_VSYNC_FORCE_LOW (2<<5) + #define PM3VideoControl_VSYNC_ACTIVE_LOW (3<<5) + #define PM3VideoControl_BYTE_DOUBLE_OFF (0<<7) + #define PM3VideoControl_BYTE_DOUBLE_ON (1<<7) + #define PM3VideoControl_BUFFER_SWAP_SYNCON_FRAMEBLANK (0<<9) + #define PM3VideoControl_BUFFER_SWAP_FREE_RUNNING (1<<9) + #define PM3VideoControl_BUFFER_SWAP_LIMITETO_FRAMERATE (2<<9) + #define PM3VideoControl_STEREO_DISABLE (0<<11) + #define PM3VideoControl_STEREO_ENABLE (1<<11) + #define PM3VideoControl_RIGHT_EYE_ACTIVE_HIGH (0<<12) + #define PM3VideoControl_RIGHT_EYE_ACTIVE_LOW (1<<12) + #define PM3VideoControl_VIDEO_EXT_LOW (0<<14) + #define PM3VideoControl_VIDEO_EXT_HIGH (1<<14) + #define PM3VideoControl_SYNC_MODE_INDEPENDENT (0<<16) + #define PM3VideoControl_SYNC_MODE_SYNCTO_VSA (1<<16) + #define PM3VideoControl_SYNC_MODE_SYNCTO_VSB (2<<16) + #define PM3VideoControl_PATCH_DISABLE (0<<18) + #define PM3VideoControl_PATCH_ENABLE (1<<18) + #define PM3VideoControl_PIXELSIZE_8BIT (0<<19) + #define PM3VideoControl_PIXELSIZE_16BIT (1<<19) + #define PM3VideoControl_PIXELSIZE_32BIT (2<<19) + #define PM3VideoControl_DISPLAY_DISABLE (0<<21) + #define PM3VideoControl_DISPLAY_ENABLE (1<<21) + #define PM3VideoControl_PATCH_OFFSET_X(off) (((off)&0x3f)<<22) + #define PM3VideoControl_PATCH_OFFSET_Y(off) (((off)&0x3f)<<28) +#define PM3InterruptLine 0x3060 +#define PM3DisplayData 0x3068 +#define PM3VerticalLineCount 0x3070 +#define PM3FifoControl 0x3078 +#define PM3ScreenBaseRight 0x3080 +#define PM3MiscControl 0x3088 + +#define PM3VideoOverlayUpdate 0x3100 + #define PM3VideoOverlayUpdate_DISABLE (0<<0) + #define PM3VideoOverlayUpdate_ENABLE (1<<0) +#define PM3VideoOverlayMode 0x3108 + #define PM3VideoOverlayMode_DISABLE (0<<0) + #define PM3VideoOverlayMode_ENABLE (1<<0) + #define PM3VideoOverlayMode_BUFFERSYNC_MANUAL (0<<1) + #define PM3VideoOverlayMode_BUFFERSYNC_VIDEOSTREAMA (1<<1) + #define PM3VideoOverlayMode_BUFFERSYNC_VIDEOSTREAMB (2<<1) + #define PM3VideoOverlayMode_FIELDPOLARITY_NORMAL (0<<4) + #define PM3VideoOverlayMode_FIELDPOLARITY_INVERT (1<<4) + #define PM3VideoOverlayMode_PIXELSIZE_8BIT (0<<5) + #define PM3VideoOverlayMode_PIXELSIZE_16BIT (1<<5) + #define PM3VideoOverlayMode_PIXELSIZE_32BIT (2<<5) + #define PM3VideoOverlayMode_COLORFORMAT_RGB8888 ((0<<7)|(1<<12)|(2<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_RGB4444 ((1<<7)|(1<<12)|(1<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_RGB5551 ((2<<7)|(1<<12)|(1<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_RGB565 ((3<<7)|(1<<12)|(1<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_RGB332 ((4<<7)|(1<<12)|(0<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_BGR8888 ((0<<7)|(2<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_BGR4444 ((1<<7)|(1<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_BGR5551 ((2<<7)|(1<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_BGR565 ((3<<7)|(1<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_BGR332 ((4<<7)|(0<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_CI8 ((5<<7)|(1<<12)|(0<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_VUY444 ((2<<10)|(1<<12)|(2<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_YUV444 ((2<<10)|(2<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_VUY422 ((1<<10)|(1<<12)|(1<<5)) + #define PM3VideoOverlayMode_COLORFORMAT_YUV422 ((1<<10)|(1<<5)) + #define PM3VideoOverlayMode_COLORORDER_BGR (0<<12) + #define PM3VideoOverlayMode_COLORORDER_RGB (1<<12) + #define PM3VideoOverlayMode_LINEARCOLOREXT_OFF (0<<13) + #define PM3VideoOverlayMode_LINEARCOLOREXT_ON (1<<13) + #define PM3VideoOverlayMode_FILTER_MASK (3<<14) + #define PM3VideoOverlayMode_FILTER_OFF (0<<14) + #define PM3VideoOverlayMode_FILTER_FULL (1<<14) + #define PM3VideoOverlayMode_FILTER_PARTIAL (2<<14) + #define PM3VideoOverlayMode_DEINTERLACE_OFF (0<<16) + #define PM3VideoOverlayMode_DEINTERLACE_BOB (1<<16) + #define PM3VideoOverlayMode_PATCHMODE_OFF (0<<18) + #define PM3VideoOverlayMode_PATCHMODE_ON (1<<18) + #define PM3VideoOverlayMode_FLIP_VIDEO (0<<20) + #define PM3VideoOverlayMode_FLIP_VIDEOSTREAMA (1<<20) + #define PM3VideoOverlayMode_FLIP_VIDEOSTREAMB (2<<20) + #define PM3VideoOverlayMode_MIRROR_MASK (3<<23) + #define PM3VideoOverlayMode_MIRRORX_OFF (0<<23) + #define PM3VideoOverlayMode_MIRRORX_ON (1<<23) + #define PM3VideoOverlayMode_MIRRORY_OFF (0<<24) + #define PM3VideoOverlayMode_MIRRORY_ON (1<<24) +#define PM3VideoOverlayFifoControl 0x3110 +#define PM3VideoOverlayIndex 0x3118 +#define PM3VideoOverlayBase 0x3120 +#define PM3VideoOverlayBase0 0x3120 +#define PM3VideoOverlayBase1 0x3128 +#define PM3VideoOverlayBase2 0x3130 +#define PM3VideoOverlayStride 0x3138 + #define PM3VideoOverlayStride_STRIDE(s) (((s)&0xfff)<<0) +#define PM3VideoOverlayWidth 0x3140 + #define PM3VideoOverlayWidth_WIDTH(w) (((w)&0xfff)<<0) +#define PM3VideoOverlayHeight 0x3148 + #define PM3VideoOverlayHeight_HEIGHT(h) (((h)&0xfff)<<0) +#define PM3VideoOverlayOrigin 0x3150 + #define PM3VideoOverlayOrigin_XORIGIN(x) (((x)&0xfff)<<0) + #define PM3VideoOverlayOrigin_YORIGIN(y) (((y)&0xfff)<<16) +#define PM3VideoOverlayShrinkXDelta 0x3158 + #define PM3VideoOverlayShrinkXDelta_NONE (1<<16) + #define PM3VideoOverlayShrinkXDelta_DELTA(s,d) \ + ((((s)<<16)/(d))&0x0ffffff0) +#define PM3VideoOverlayZoomXDelta 0x3160 + #define PM3VideoOverlayZoomXDelta_NONE (1<<16) + #define PM3VideoOverlayZoomXDelta_DELTA(s,d) \ + ((((s)<<16)/(d))&0x0001fff0) +#define PM3VideoOverlayYDelta 0x3168 + #define PM3VideoOverlayYDelta_NONE (1<<16) + #define PM3VideoOverlayYDelta_DELTA(s,d) \ + ((((s)<<16)/(d))&0x0ffffff0) +#define PM3VideoOverlayFieldOffset 0x3170 +#define PM3VideoOverlayStatus 0x3178 + +/********************************************** +* GLINT Permedia3 RAMDAC Registers (0x4000) * +***********************************************/ +/* Direct Registers */ +#define PM3RD_PaletteWriteAddress 0x4000 +#define PM3RD_PaletteData 0x4008 +#define PM3RD_PixelMask 0x4010 +#define PM3RD_PaletteReadAddress 0x4018 + +#define PM3RD_IndexLow 0x4020 +#define PM3RD_IndexHigh 0x4028 +#define PM3RD_IndexedData 0x4030 +#define PM3RD_IndexControl 0x4038 + #define PM3RD_IndexControl_AUTOINCREMENT_ENABLE (1<<0) + #define PM3RD_IndexControl_AUTOINCREMENT_DISABLE (0<<0) + +/* Indirect Registers */ +#define PM3RD_MiscControl 0x000 + #define PM3RD_MiscControl_HIGHCOLOR_RES_DISABLE (0<<0) + #define PM3RD_MiscControl_HIGHCOLOR_RES_ENABLE (1<<0) + #define PM3RD_MiscControl_PIXELDOUBLE_DISABLE (0<<1) + #define PM3RD_MiscControl_PIXELDOUBLE_ENABLE (1<<1) + #define PM3RD_MiscControl_LASTREAD_ADDR_DISABLE (0<<2) + #define PM3RD_MiscControl_LASTREAD_ADDR_ENABLE (1<<2) + #define PM3RD_MiscControl_DIRECTCOLOR_DISABLE (0<<3) + #define PM3RD_MiscControl_DIRECTCOLOR_ENABLE (1<<3) + #define PM3RD_MiscControl_OVERLAY_DISABLE (0<<4) + #define PM3RD_MiscControl_OVERLAY_ENABLE (1<<4) + #define PM3RD_MiscControl_PIXELDOUBLE_BUFFER_DISABLE (0<<5) + #define PM3RD_MiscControl_PIXELDOUBLE_BUFFER_ENABLE (1<<5) + #define PM3RD_MiscControl_VSB_OUTPUT_DISABLE (0<<6) + #define PM3RD_MiscControl_VSB_OUTPUT_ENABLE (1<<6) + #define PM3RD_MiscControl_STEREODOUBLE_BUFFER_DISABLE (0<<7) + #define PM3RD_MiscControl_STEREODOUBLE_BUFFER_ENABLE (1<<7) +#define PM3RD_SyncControl 0x001 + #define PM3RD_SyncControl_HSYNC_ACTIVE_LOW (0<<0) + #define PM3RD_SyncControl_HSYNC_ACTIVE_HIGH (1<<0) + #define PM3RD_SyncControl_HSYNC_FORCE_ACTIVE (3<<0) + #define PM3RD_SyncControl_HSYNC_FORCE_INACTIVE (4<<0) + #define PM3RD_SyncControl_HSYNC_TRI_STATE (2<<0) + #define PM3RD_SyncControl_VSYNC_ACTIVE_LOW (0<<3) + #define PM3RD_SyncControl_VSYNC_ACTIVE_HIGH (1<<3) + #define PM3RD_SyncControl_VSYNC_TRI_STATE (2<<3) + #define PM3RD_SyncControl_VSYNC_FORCE_ACTIVE (3<<3) + #define PM3RD_SyncControl_VSYNC_FORCE_INACTIVE (4<<3) + #define PM3RD_SyncControl_HSYNC_OVERRIDE_SETBY_HSYNC (0<<6) + #define PM3RD_SyncControl_HSYNC_OVERRIDE_FORCE_HIGH (1<<6) + #define PM3RD_SyncControl_VSYNC_OVERRIDE_SETBY_VSYNC (0<<7) + #define PM3RD_SyncControl_VSYNC_OVERRIDE_FORCE_HIGH (1<<7) +#define PM3RD_DACControl 0x002 + #define PM3RD_DACControl_DAC_POWER_ON (0<<0) + #define PM3RD_DACControl_DAC_POWER_OFF (1<<0) + #define PM3RD_DACControl_SYNC_ON_GREEN_DISABLE (0<<3) + #define PM3RD_DACControl_SYNC_ON_GREEN_ENABLE (1<<3) + #define PM3RD_DACControl_BLANK_RED_DAC_DISABLE (0<<4) + #define PM3RD_DACControl_BLANK_RED_DAC_ENABLE (1<<4) + #define PM3RD_DACControl_BLANK_GREEN_DAC_DISABLE (0<<5) + #define PM3RD_DACControl_BLANK_GREEN_DAC_ENABLE (1<<5) + #define PM3RD_DACControl_BLANK_BLUE_DAC_DISABLE (0<<6) + #define PM3RD_DACControl_BLANK_BLUE_DAC_ENABLE (1<<6) + #define PM3RD_DACControl_BLANK_PEDESTAL_DISABLE (0<<7) + #define PM3RD_DACControl_BLANK_PEDESTAL_ENABLE (1<<7) +#define PM3RD_PixelSize 0x003 + #define PM3RD_PixelSize_24_BIT_PIXELS (4<<0) + #define PM3RD_PixelSize_32_BIT_PIXELS (2<<0) + #define PM3RD_PixelSize_16_BIT_PIXELS (1<<0) + #define PM3RD_PixelSize_8_BIT_PIXELS (0<<0) +#define PM3RD_ColorFormat 0x004 + #define PM3RD_ColorFormat_LINEAR_COLOR_EXT_ENABLE (1<<6) + #define PM3RD_ColorFormat_LINEAR_COLOR_EXT_DISABLE (0<<6) + #define PM3RD_ColorFormat_COLOR_ORDER_BLUE_LOW (1<<5) + #define PM3RD_ColorFormat_COLOR_ORDER_RED_LOW (0<<5) + #define PM3RD_ColorFormat_COLOR_FORMAT_MASK (0x1f<<0) + #define PM3RD_ColorFormat_8888_COLOR (0<<0) + #define PM3RD_ColorFormat_5551_FRONT_COLOR (1<<0) + #define PM3RD_ColorFormat_4444_COLOR (2<<0) + #define PM3RD_ColorFormat_332_FRONT_COLOR (5<<0) + #define PM3RD_ColorFormat_332_BACK_COLOR (6<<0) + #define PM3RD_ColorFormat_2321_FRONT_COLOR (9<<0) + #define PM3RD_ColorFormat_2321_BACK_COLOR (10<<0) + #define PM3RD_ColorFormat_232_FRONTOFF_COLOR (11<<0) + #define PM3RD_ColorFormat_232_BACKOFF_COLOR (12<<0) + #define PM3RD_ColorFormat_5551_BACK_COLOR (13<<0) + #define PM3RD_ColorFormat_CI8_COLOR (14<<0) + #define PM3RD_ColorFormat_565_FRONT_COLOR (16<<0) + #define PM3RD_ColorFormat_565_BACK_COLOR (17<<0) +#define PM3RD_CursorMode 0x005 + #define PM3RD_CursorMode_CURSOR_DISABLE (0<<0) + #define PM3RD_CursorMode_CURSOR_ENABLE (1<<0) + #define PM3RD_CursorMode_FORMAT_64x64_2BPE_P0123 (0<<2) + #define PM3RD_CursorMode_FORMAT_32x32_2BPE_P0 (1<<2) + #define PM3RD_CursorMode_FORMAT_32x32_2BPE_P1 (2<<2) + #define PM3RD_CursorMode_FORMAT_32x32_2BPE_P2 (3<<2) + #define PM3RD_CursorMode_FORMAT_32x32_2BPE_P3 (4<<2) + #define PM3RD_CursorMode_FORMAT_32x32_4BPE_P01 (5<<2) + #define PM3RD_CursorMode_FORMAT_32x32_4BPE_P23 (6<<2) + #define PM3RD_CursorMode_TYPE_MS (0<<4) + #define PM3RD_CursorMode_TYPE_X (1<<4) + #define PM3RD_CursorMode_REVERSE_PIXEL_ORDER_DISABLE (0<<6) + #define PM3RD_CursorMode_REVERSE_PIXEL_ORDER_ENABLE (1<<6) + #define PM3RD_CursorMode_REVERSE_PIXEL_ORDER_3_COLOR (2<<6) + #define PM3RD_CursorMode_REVERSE_PIXEL_ORDER_15_COLOR (3<<6) +#define PM3RD_CursorControl 0x006 + #define PM3RD_CursorControl_DOUBLE_X_DISABLED (0<<0) + #define PM3RD_CursorControl_DOUBLE_X_ENABLED (1<<0) + #define PM3RD_CursorControl_DOUBLE_Y_DISABLED (0<<1) + #define PM3RD_CursorControl_DOUBLE_Y_ENABLED (1<<1) + #define PM3RD_CursorControl_READBACK_POS_DISABLED (0<<2) + #define PM3RD_CursorControl_READBACK_POS_ENABLED (1<<2) + +#define PM3RD_CursorXLow 0x007 +#define PM3RD_CursorXHigh 0x008 +#define PM3RD_CursorYLow 0x009 +#define PM3RD_CursorYHigh 0x00a +#define PM3RD_CursorHotSpotX 0x00b +#define PM3RD_CursorHotSpotY 0x00c +#define PM3RD_OverlayKey 0x00d +#define PM3RD_Pan 0x00e + #define PM3RD_Pan_DISABLE (0<<0) + #define PM3RD_Pan_ENABLE (1<<0) + #define PM3RD_Pan_GATE_DISABLE (0<<1) + #define PM3RD_Pan_GATE_ENABLE (1<<1) +#define PM3RD_Sense 0x00f + +#define PM3RD_CheckControl 0x018 + #define PM3RD_CheckControl_PIXEL_DISABLED (0<<0) + #define PM3RD_CheckControl_PIXEL_ENABLED (1<<0) + #define PM3RD_CheckControl_LUT_DISABLED (0<<1) + #define PM3RD_CheckControl_LUT_ENABLED (1<<1) +#define PM3RD_CheckPixelRed 0x019 +#define PM3RD_CheckPixelGreen 0x01a +#define PM3RD_CheckPixelBlue 0x01b +#define PM3RD_CheckLUTRed 0x01c +#define PM3RD_CheckLUTGreen 0x01d +#define PM3RD_CheckLUTBlue 0x01e +#define PM3RD_Scratch 0x01f + +#define PM3RD_VideoOverlayControl 0x020 + #define PM3RD_VideoOverlayControl_DISABLE (0<<0) + #define PM3RD_VideoOverlayControl_ENABLE (1<<0) + #define PM3RD_VideoOverlayControl_MODE_MASK (3<<1) + #define PM3RD_VideoOverlayControl_MODE_MAINKEY (0<<1) + #define PM3RD_VideoOverlayControl_MODE_OVERLAYKEY (1<<1) + #define PM3RD_VideoOverlayControl_MODE_ALWAYS (2<<1) + #define PM3RD_VideoOverlayControl_MODE_BLEND (3<<1) + #define PM3RD_VideoOverlayControl_DIRECTCOLOR_DISABLED (0<<3) + #define PM3RD_VideoOverlayControl_DIRECTCOLOR_ENABLED (1<<3) + #define PM3RD_VideoOverlayControl_BLENDSRC_MAIN (0<<4) + #define PM3RD_VideoOverlayControl_BLENDSRC_REGISTER (1<<4) + #define PM3RD_VideoOverlayControl_KEY_COLOR (0<<5) + #define PM3RD_VideoOverlayControl_KEY_ALPHA (1<<5) +#define PM3RD_VideoOverlayXStartLow 0x021 +#define PM3RD_VideoOverlayXStartHigh 0x022 +#define PM3RD_VideoOverlayYStartLow 0x023 +#define PM3RD_VideoOverlayYStartHigh 0x024 +#define PM3RD_VideoOverlayXEndLow 0x025 +#define PM3RD_VideoOverlayXEndHigh 0x026 +#define PM3RD_VideoOverlayYEndLow 0x027 +#define PM3RD_VideoOverlayYEndHigh 0x028 +#define PM3RD_VideoOverlayKeyR 0x029 +#define PM3RD_VideoOverlayKeyG 0x02a +#define PM3RD_VideoOverlayKeyB 0x02b +#define PM3RD_VideoOverlayBlend 0x02c + #define PM3RD_VideoOverlayBlend_FACTOR_0_PERCENT (0<<6) + #define PM3RD_VideoOverlayBlend_FACTOR_25_PERCENT (1<<6) + #define PM3RD_VideoOverlayBlend_FACTOR_75_PERCENT (2<<6) + #define PM3RD_VideoOverlayBlend_FACTOR_100_PERCENT (3<<6) + +#define PM3RD_DClkSetup1 0x1f0 +#define PM3RD_DClkSetup2 0x1f1 +#define PM3RD_KClkSetup1 0x1f2 +#define PM3RD_KClkSetup2 0x1f3 + +#define PM3RD_DClkControl 0x200 + #define PM3RD_DClkControl_SOURCE_PLL (0<<4) + #define PM3RD_DClkControl_SOURCE_VSA (1<<4) + #define PM3RD_DClkControl_SOURCE_VSB (2<<4) + #define PM3RD_DClkControl_SOURCE_EXT (3<<4) + #define PM3RD_DClkControl_STATE_RUN (2<<2) + #define PM3RD_DClkControl_STATE_HIGH (1<<2) + #define PM3RD_DClkControl_STATE_LOW (0<<2) + #define PM3RD_DClkControl_LOCKED (1<<1) + #define PM3RD_DClkControl_NOT_LOCKED (0<<1) + #define PM3RD_DClkControl_ENABLE (1<<0) + #define PM3RD_DClkControl_DISABLE (0<<0) +#define PM3RD_DClk0PreScale 0x201 +#define PM3RD_DClk0FeedbackScale 0x202 +#define PM3RD_DClk0PostScale 0x203 +#define PM3RD_DClk1PreScale 0x204 +#define PM3RD_DClk1FeedbackScale 0x205 +#define PM3RD_DClk1PostScale 0x206 +#define PM3RD_DClk2PreScale 0x207 +#define PM3RD_DClk2FeedbackScale 0x208 +#define PM3RD_DClk2PostScale 0x209 +#define PM3RD_DClk3PreScale 0x20a +#define PM3RD_DClk3FeedbackScale 0x20b +#define PM3RD_DClk3PostScale 0x20c +#define PM3RD_KClkControl 0x20d + #define PM3RD_KClkControl_DISABLE (0<<0) + #define PM3RD_KClkControl_ENABLE (1<<0) + #define PM3RD_KClkControl_NOT_LOCKED (0<<1) + #define PM3RD_KClkControl_LOCKED (1<<1) + #define PM3RD_KClkControl_STATE_LOW (0<<2) + #define PM3RD_KClkControl_STATE_HIGH (1<<2) + #define PM3RD_KClkControl_STATE_RUN (2<<2) + #define PM3RD_KClkControl_STATE_LOW_POWER (3<<2) + #define PM3RD_KClkControl_SOURCE_PCLK (0<<4) + #define PM3RD_KClkControl_SOURCE_HALF_PCLK (1<<4) + #define PM3RD_KClkControl_SOURCE_PLL (2<<4) +#define PM3RD_KClkPreScale 0x20e +#define PM3RD_KClkFeedbackScale 0x20f +#define PM3RD_KClkPostScale 0x210 +#define PM3RD_MClkControl 0x211 + #define PM3RD_MClkControl_DISABLE (0<<0) + #define PM3RD_MClkControl_ENABLE (1<<0) + #define PM3RD_MClkControl_NOT_LOCKED (0<<1) + #define PM3RD_MClkControl_LOCKED (1<<1) + #define PM3RD_MClkControl_STATE_LOW (0<<2) + #define PM3RD_MClkControl_STATE_HIGH (1<<2) + #define PM3RD_MClkControl_STATE_RUN (2<<2) + #define PM3RD_MClkControl_STATE_LOW_POWER (3<<2) + #define PM3RD_MClkControl_SOURCE_PCLK (0<<4) + #define PM3RD_MClkControl_SOURCE_HALF_PCLK (1<<4) + #define PM3RD_MClkControl_SOURCE_HALF_EXT (3<<4) + #define PM3RD_MClkControl_SOURCE_EXT (4<<4) + #define PM3RD_MClkControl_SOURCE_HALF_KCLK (5<<4) + #define PM3RD_MClkControl_SOURCE_KCLK (6<<4) +#define PM3RD_MClkPreScale 0x212 +#define PM3RD_MClkFeedbackScale 0x213 +#define PM3RD_MClkPostScale 0x214 +#define PM3RD_SClkControl 0x215 + #define PM3RD_SClkControl_DISABLE (0<<0) + #define PM3RD_SClkControl_ENABLE (1<<0) + #define PM3RD_SClkControl_NOT_LOCKED (0<<1) + #define PM3RD_SClkControl_LOCKED (1<<1) + #define PM3RD_SClkControl_STATE_LOW (0<<2) + #define PM3RD_SClkControl_STATE_HIGH (1<<2) + #define PM3RD_SClkControl_STATE_RUN (2<<2) + #define PM3RD_SClkControl_STATE_LOW_POWER (3<<2) + #define PM3RD_SClkControl_SOURCE_PCLK (0<<4) + #define PM3RD_SClkControl_SOURCE_HALF_PCLK (1<<4) + #define PM3RD_SClkControl_SOURCE_HALF_EXT (3<<4) + #define PM3RD_SClkControl_SOURCE_EXT (4<<4) + #define PM3RD_SClkControl_SOURCE_HALF_KCLK (5<<4) + #define PM3RD_SClkControl_SOURCE_KCLK (6<<4) +#define PM3RD_SClkPreScale 0x216 +#define PM3RD_SClkFeedbackScale 0x217 +#define PM3RD_SClkPostScale 0x218 + +#define PM3RD_CursorPalette(p) (0x303+(p)) +#define PM3RD_CursorPattern(p) (0x400+(p)) +/****************************************************** +* GLINT Permedia3 Video Streaming Registers (0x5000) * +*******************************************************/ + +#define PM3VSConfiguration 0x5800 + +/********************************************** +* GLINT Permedia3 Core Registers (0x8000+) * +***********************************************/ +#define PM3AALineWidth 0x94c0 +#define PM3AAPointsize 0x94a0 +#define PM3AlphaBlendAlphaMode 0xafa8 +#define PM3AlphaBlendAlphaModeAnd 0xad30 +#define PM3AlphaBlendAlphaModeOr 0xad38 +#define PM3AlphaBlendColorMode 0xafa0 +#define PM3AlphaBlendColorModeAnd 0xacb0 +#define PM3AlphaBlendColorModeOr 0xacb8 +#define PM3AlphaDestColor 0xaf88 +#define PM3AlphaSourceColor 0xaf80 +#define PM3AlphaTestMode 0x8800 +#define PM3AlphaTestModeAnd 0xabf0 +#define PM3AlphaTestModeOr 0xabf8 +#define PM3AntialiasMode 0x8808 +#define PM3AntialiasModeAnd 0xac00 +#define PM3AntialiasModeOr 0xac08 +/* ... */ +#define PM3BackgroundColor 0xb0c8 +/* ... */ +#define PM3ColorDDAMode 0x87e0 +#define PM3ColorDDAModeAnd 0xabe0 +#define PM3ColorDDAModeOr 0xabe8 +#define PM3CommandInterrupt 0xa990 +#define PM3ConstantColorDDA 0xafb0 + #define PM3ConstantColorDDA_R(r) ((r)&0xff) + #define PM3ConstantColorDDA_G(g) (((g)&0xff)<<8) + #define PM3ConstantColorDDA_B(b) (((b)&0xff)<<16) + #define PM3ConstantColorDDA_A(a) (((a)&0xff)<<24) +#define PM3ContextData 0x8dd0 +#define PM3ContextDump 0x8dc0 +#define PM3ContextRestore 0x8dc8 +#define PM3Continue 0x8058 +#define PM3ContinueNewDom 0x8048 +#define PM3ContinueNewLine 0x8040 +#define PM3ContinueNewSub 0x8050 +#define PM3Count 0x8030 +/* ... */ +#define PM3DeltaControl 0x9350 +#define PM3DeltaControlAnd 0xab20 +#define PM3DeltaControlOr 0xab28 +#define PM3DeltaMode 0x9300 +#define PM3DeltaModeAnd 0xaad0 +#define PM3DeltaModeOr 0xaad8 +/* ... */ +#define PM3DitherMode 0x8818 +#define PM3DitherModeAnd 0xacd0 +#define PM3DitherModeOr 0xacd8 +/* ... */ +#define PM3dXDom 0x8008 +#define PM3dXSub 0x8018 +#define PM3dY 0x8028 +/* ... */ +#define PM3FBBlockColor 0x8ac8 +#define PM3FBBlockColor0 0xb060 +#define PM3FBBlockColor1 0xb068 +#define PM3FBBlockColor2 0xb070 +#define PM3FBBlockColor3 0xb078 +#define PM3FBBlockColorBack 0xb0a0 +#define PM3FBBlockColorBack0 0xb080 +#define PM3FBBlockColorBack1 0xb088 +#define PM3FBBlockColorBack2 0xb090 +#define PM3FBBlockColorBack3 0xb098 +#define PM3FBColor 0x8a98 +#define PM3FBDestReadBufferAddr0 0xae80 +#define PM3FBDestReadBufferAddr1 0xae88 +#define PM3FBDestReadBufferAddr2 0xae90 +#define PM3FBDestReadBufferAddr3 0xae98 +#define PM3FBDestReadBufferOffset0 0xaea0 +#define PM3FBDestReadBufferOffset1 0xaea8 +#define PM3FBDestReadBufferOffset2 0xaeb0 +#define PM3FBDestReadBufferOffset3 0xaeb8 + #define PM3FBDestReadBufferOffset_XOffset(x) ((x)&0xffff) + #define PM3FBDestReadBufferOffset_YOffset(y) (((y)&0xffff)<<16) +#define PM3FBDestReadBufferWidth0 0xaec0 +#define PM3FBDestReadBufferWidth1 0xaec8 +#define PM3FBDestReadBufferWidth2 0xaed0 +#define PM3FBDestReadBufferWidth3 0xaed8 + #define PM3FBDestReadBufferWidth_Width(w) ((w)&0x0fff) + +#define PM3FBDestReadEnables 0xaee8 +#define PM3FBDestReadEnablesAnd 0xad20 +#define PM3FBDestReadEnablesOr 0xad28 + #define PM3FBDestReadEnables_E(e) ((e)&0xff) + #define PM3FBDestReadEnables_E0 1<<0 + #define PM3FBDestReadEnables_E1 1<<1 + #define PM3FBDestReadEnables_E2 1<<2 + #define PM3FBDestReadEnables_E3 1<<3 + #define PM3FBDestReadEnables_E4 1<<4 + #define PM3FBDestReadEnables_E5 1<<5 + #define PM3FBDestReadEnables_E6 1<<6 + #define PM3FBDestReadEnables_E7 1<<7 + #define PM3FBDestReadEnables_R(r) (((r)&0xff)<<8) + #define PM3FBDestReadEnables_R0 1<<8 + #define PM3FBDestReadEnables_R1 1<<9 + #define PM3FBDestReadEnables_R2 1<<10 + #define PM3FBDestReadEnables_R3 1<<11 + #define PM3FBDestReadEnables_R4 1<<12 + #define PM3FBDestReadEnables_R5 1<<13 + #define PM3FBDestReadEnables_R6 1<<14 + #define PM3FBDestReadEnables_R7 1<<15 + #define PM3FBDestReadEnables_ReferenceAlpha(a) (((a)&0xff)<<24) + +#define PM3FBDestReadMode 0xaee0 +#define PM3FBDestReadModeAnd 0xac90 +#define PM3FBDestReadModeOr 0xac98 + #define PM3FBDestReadMode_ReadDisable 0<<0 + #define PM3FBDestReadMode_ReadEnable 1<<0 + #define PM3FBDestReadMode_StripePitch(sp) (((sp)&0x7)<<2) + #define PM3FBDestReadMode_StripeHeight(sh) (((sh)&0x7)<<7) + #define PM3FBDestReadMode_Enable0 1<<8 + #define PM3FBDestReadMode_Enable1 1<<9 + #define PM3FBDestReadMode_Enable2 1<<10 + #define PM3FBDestReadMode_Enable3 1<<11 + #define PM3FBDestReadMode_Layout0(l) (((l)&0x3)<<12) + #define PM3FBDestReadMode_Layout1(l) (((l)&0x3)<<14) + #define PM3FBDestReadMode_Layout2(l) (((l)&0x3)<<16) + #define PM3FBDestReadMode_Layout3(l) (((l)&0x3)<<18) + #define PM3FBDestReadMode_Origin0 1<<20 + #define PM3FBDestReadMode_Origin1 1<<21 + #define PM3FBDestReadMode_Origin2 1<<22 + #define PM3FBDestReadMode_Origin3 1<<23 + #define PM3FBDestReadMode_Blocking 1<<24 + #define PM3FBDestReadMode_UseReadEnabled 1<<26 + #define PM3FBDestReadMode_AlphaFiltering 1<<27 + +#define PM3FBHardwareWriteMask 0x8ac0 +#define PM3FBSoftwareWriteMask 0x8820 +#define PM3FBData 0x8aa0 +#define PM3FBSourceData 0x8aa8 +#define PM3FBSourceReadBufferAddr 0xaf08 +#define PM3FBSourceReadBufferOffset 0xaf10 + #define PM3FBSourceReadBufferOffset_XOffset(x) ((x)&0xffff) + #define PM3FBSourceReadBufferOffset_YOffset(y) (((y)&0xffff)<<16) +#define PM3FBSourceReadBufferWidth 0xaf18 + #define PM3FBSourceReadBufferWidth_Width(w) ((w)&0x0fff) +#define PM3FBSourceReadMode 0xaf00 +#define PM3FBSourceReadModeAnd 0xaca0 +#define PM3FBSourceReadModeOr 0xaca8 + #define PM3FBSourceReadMode_ReadDisable (0<<0) + #define PM3FBSourceReadMode_ReadEnable (1<<0) + #define PM3FBSourceReadMode_StripePitch(sp) (((sp)&0x7)<<2) + #define PM3FBSourceReadMode_StripeHeight(sh) (((sh)&0x7)<<7) + #define PM3FBSourceReadMode_Layout(l) (((l)&0x3)<<8) + #define PM3FBSourceReadMode_Origin 1<<10 + #define PM3FBSourceReadMode_Blocking 1<<11 + #define PM3FBSourceReadMode_UserTexelCoord 1<<13 + #define PM3FBSourceReadMode_WrapXEnable 1<<14 + #define PM3FBSourceReadMode_WrapYEnable 1<<15 + #define PM3FBSourceReadMode_WrapX(w) (((w)&0xf)<<16) + #define PM3FBSourceReadMode_WrapY(w) (((w)&0xf)<<20) + #define PM3FBSourceReadMode_ExternalSourceData 1<<24 +#define PM3FBWriteBufferAddr0 0xb000 +#define PM3FBWriteBufferAddr1 0xb008 +#define PM3FBWriteBufferAddr2 0xb010 +#define PM3FBWriteBufferAddr3 0xb018 + +#define PM3FBWriteBufferOffset0 0xb020 +#define PM3FBWriteBufferOffset1 0xb028 +#define PM3FBWriteBufferOffset2 0xb030 +#define PM3FBWriteBufferOffset3 0xb038 + #define PM3FBWriteBufferOffset_XOffset(x) ((x)&0xffff) + #define PM3FBWriteBufferOffset_YOffset(y) (((y)&0xffff)<<16) + +#define PM3FBWriteBufferWidth0 0xb040 +#define PM3FBWriteBufferWidth1 0xb048 +#define PM3FBWriteBufferWidth2 0xb050 +#define PM3FBWriteBufferWidth3 0xb058 + #define PM3FBWriteBufferWidth_Width(w) ((w)&0x0fff) + +#define PM3FBWriteMode 0x8ab8 +#define PM3FBWriteModeAnd 0xacf0 +#define PM3FBWriteModeOr 0xacf8 + #define PM3FBWriteMode_WriteDisable 0<<0 + #define PM3FBWriteMode_WriteEnable 1<<0 + #define PM3FBWriteMode_Replicate 1<<4 + #define PM3FBWriteMode_OpaqueSpan 1<<5 + #define PM3FBWriteMode_StripePitch(p) (((p)&0x7)<<6) + #define PM3FBWriteMode_StripeHeight(h) (((h)&0x7)<<9) + #define PM3FBWriteMode_Enable0 1<<12 + #define PM3FBWriteMode_Enable1 1<<13 + #define PM3FBWriteMode_Enable2 1<<14 + #define PM3FBWriteMode_Enable3 1<<15 + #define PM3FBWriteMode_Layout0(l) (((l)&0x3)<<16) + #define PM3FBWriteMode_Layout1(l) (((l)&0x3)<<18) + #define PM3FBWriteMode_Layout2(l) (((l)&0x3)<<20) + #define PM3FBWriteMode_Layout3(l) (((l)&0x3)<<22) + #define PM3FBWriteMode_Origin0 1<<24 + #define PM3FBWriteMode_Origin1 1<<25 + #define PM3FBWriteMode_Origin2 1<<26 + #define PM3FBWriteMode_Origin3 1<<27 +#define PM3ForegroundColor 0xb0c0 +/* ... */ +#define PM3GIDMode 0xb538 +#define PM3GIDModeAnd 0xb5b0 +#define PM3GIDModeOr 0xb5b8 +/* ... */ +#define PM3LBDestReadBufferAddr 0xb510 +#define PM3LBDestReadBufferOffset 0xb518 +#define PM3LBDestReadEnables 0xb508 +#define PM3LBDestReadEnablesAnd 0xb590 +#define PM3LBDestReadEnablesOr 0xb598 +#define PM3LBDestReadMode 0xb500 +#define PM3LBDestReadModeAnd 0xb580 +#define PM3LBDestReadModeOr 0xb588 + #define PM3LBDestReadMode_Disable 0<<0 + #define PM3LBDestReadMode_Enable 1<<0 + #define PM3LBDestReadMode_StripePitch(p) (((p)&0x7)<<2) + #define PM3LBDestReadMode_StripeHeight(h) (((h)&0x7)<<5) + #define PM3LBDestReadMode_Layout 1<<8 + #define PM3LBDestReadMode_Origin 1<<9 + #define PM3LBDestReadMode_UserReadEnables 1<<10 + #define PM3LBDestReadMode_Packed16 1<<11 + #define PM3LBDestReadMode_Width(w) (((w)&0xfff)<<12) +#define PM3LBReadFormat 0x8888 + #define PM3LBReadFormat_DepthWidth(w) (((w)&0x3)<<0) + #define PM3LBReadFormat_StencilWidth(w) (((w)&0xf)<<2) + #define PM3LBReadFormat_StencilPosition(p) (((p)&0x1f)<<6) + #define PM3LBReadFormat_FCPWidth(w) (((w)&0xf)<<11) + #define PM3LBReadFormat_FCPPosition(p) (((p)&0x1f)<<15) + #define PM3LBReadFormat_GIDWidth(w) (((w)&0x7)<<20) + #define PM3LBReadFormat_GIDPosition(p) (((p)&0x1f)<<23) +#define PM3LBSourceReadBufferAddr 0xb528 +#define PM3LBSourceReadBufferOffset 0xb530 +#define PM3LBSourceReadMode 0xb520 +#define PM3LBSourceReadModeAnd 0xb5a0 +#define PM3LBSourceReadModeOr 0xb5a8 + #define PM3LBSourceReadMode_Enable 1<<0 + #define PM3LBSourceReadMode_StripePitch(p) (((p)&0x7)<<2) + #define PM3LBSourceReadMode_StripeHeight(h) (((h)&0x7)<<5) + #define PM3LBSourceReadMode_Layout 1<<8 + #define PM3LBSourceReadMode_Origin 1<<9 + #define PM3LBSourceReadMode_Packed16 1<<10 + #define PM3LBSourceReadMode_Width(w) (((w)&0xfff)<<11) +#define PM3LBStencil 0x88a8 +#define PM3LBWriteBufferAddr 0xb540 +#define PM3LBWriteBufferOffset 0xb548 +#define PM3LBWriteFormat 0x88c8 + #define PM3LBWriteFormat_DepthWidth(w) (((w)&0x3)<<0) + #define PM3LBWriteFormat_StencilWidth(w) (((w)&0xf)<<2) + #define PM3LBWriteFormat_StencilPosition(p) (((p)&0x1f)<<6) + #define PM3LBWriteFormat_GIDWidth(w) (((w)&0x7)<<20) + #define PM3LBWriteFormat_GIDPosition(p) (((p)&0x1f)<<23) +#define PM3LBWriteMode 0x88c0 +#define PM3LBWriteModeAnd 0xac80 +#define PM3LBWriteModeOr 0xac88 + #define PM3LBWriteMode_WriteDisable 0<<0 + #define PM3LBWriteMode_WriteEnable 1<<0 + #define PM3LBWriteMode_StripePitch(p) (((p)&0x7)<<3) + #define PM3LBWriteMode_StripeHeight(h) (((h)&0x7)<<6) + #define PM3LBWriteMode_Layout 1<<9 + #define PM3LBWriteMode_Origin 1<<10 + #define PM3LBWriteMode_Packed16 1<<11 + #define PM3LBWriteMode_Width(w) (((w)&0xfff)<<12) +/* ... */ +#define PM3LineStippleMode 0x81a8 +#define PM3LineStippleModeAnd 0xabc0 +#define PM3LineStippleModeOr 0xabc8 +#define PM3LoadLineStippleCounters 0x81b0 +/* ... */ +#define PM3LogicalOpMode 0x8828 +#define PM3LogicalOpModeAnd 0xace0 +#define PM3LogicalOpModeOr 0xace8 + #define PM3LogicalOpMode_Disable (0<<0) + #define PM3LogicalOpMode_Enable (1<<0) + #define PM3LogicalOpMode_LogicOp(op) (((op)&0xf)<<1) + #define PM3LogicalOpMode_UseConstantWriteData_Disable (0<<5) + #define PM3LogicalOpMode_UseConstantWriteData_Enable (1<<5) + #define PM3LogicalOpMode_Background_Disable (0<<6) + #define PM3LogicalOpMode_Background_Enable (1<<6) + #define PM3LogicalOpMode_Background_LogicOp(op) (((op)&0xf)<<7) + #define PM3LogicalOpMode_UseConstantSource_Disable (0<<11) + #define PM3LogicalOpMode_UseConstantSource_Enable (1<<11) + +/* ... */ +#define PM3LUT 0x8e80 +/* ... */ +#define PM3LUT 0x8e80 +#define PM3LUTAddress 0x84d0 +#define PM3LUTData 0x84c8 +#define PM3LUTIndex 0x84c0 +#define PM3LUTMode 0xb378 +#define PM3LUTModeAnd 0xad70 +#define PM3LUTModeOr 0xad78 +#define PM3LUTTransfer 0x84d8 +/* ... */ +#define PM3PixelSize 0x80c0 + #define PM3PixelSize_GLOBAL_32BIT (0<<0) + #define PM3PixelSize_GLOBAL_16BIT (1<<0) + #define PM3PixelSize_GLOBAL_8BIT (2<<0) + #define PM3PixelSize_RASTERIZER_32BIT (0<<2) + #define PM3PixelSize_RASTERIZER_16BIT (1<<2) + #define PM3PixelSize_RASTERIZER_8BIT (2<<2) + #define PM3PixelSize_SCISSOR_AND_STIPPLE_32BIT (0<<4) + #define PM3PixelSize_SCISSOR_AND_STIPPLE_16BIT (1<<4) + #define PM3PixelSize_SCISSOR_AND_STIPPLE_8BIT (2<<4) + #define PM3PixelSize_TEXTURE_32BIT (0<<6) + #define PM3PixelSize_TEXTURE_16BIT (1<<6) + #define PM3PixelSize_TEXTURE_8BIT (2<<6) + #define PM3PixelSize_LUT_32BIT (0<<8) + #define PM3PixelSize_LUT_16BIT (1<<8) + #define PM3PixelSize_LUT_8BIT (2<<8) + #define PM3PixelSize_FRAMEBUFFER_32BIT (0<<10) + #define PM3PixelSize_FRAMEBUFFER_16BIT (1<<10) + #define PM3PixelSize_FRAMEBUFFER_8BIT (2<<10) + #define PM3PixelSize_LOGICAL_OP_32BIT (0<<12) + #define PM3PixelSize_LOGICAL_OP_16BIT (1<<12) + #define PM3PixelSize_LOGICAL_OP_8BIT (2<<12) + #define PM3PixelSize_LOCALBUFFER_32BIT (0<<14) + #define PM3PixelSize_LOCALBUFFER_16BIT (1<<14) + #define PM3PixelSize_LOCALBUFFER_8BIT (2<<14) + #define PM3PixelSize_SETUP_32BIT (0<<16) + #define PM3PixelSize_SETUP_16BIT (1<<16) + #define PM3PixelSize_SETUP_8BIT (2<<16) + #define PM3PixelSize_GLOBAL (0<<31) + #define PM3PixelSize_INDIVIDUAL (1<<31) +/* ... */ +#define PM3Render 0x8038 + #define PM3Render_AreaStipple_Disable (0<<0) + #define PM3Render_AreaStipple_Enable (1<<0) + #define PM3Render_LineStipple_Disable (0<<1) + #define PM3Render_LineStipple_Enable (1<<1) + #define PM3Render_ResetLine_Disable (0<<2) + #define PM3Render_ResetLine_Enable (1<<2) + #define PM3Render_FastFill_Disable (0<<3) + #define PM3Render_FastFill_Enable (1<<3) + #define PM3Render_Primitive_Line (0<<6) + #define PM3Render_Primitive_Trapezoid (1<<6) + #define PM3Render_Primitive_Point (2<<6) + #define PM3Render_Antialias_Disable (0<<8) + #define PM3Render_Antialias_Enable (1<<8) + #define PM3Render_Antialias_SubPixelRes_4x4 (0<<9) + #define PM3Render_Antialias_SubPixelRes_8x8 (1<<9) + #define PM3Render_UsePointTable_Disable (0<<10) + #define PM3Render_UsePointTable_Enable (1<<10) + #define PM3Render_SyncOnbitMask_Disable (0<<11) + #define PM3Render_SyncOnBitMask_Enable (1<<11) + #define PM3Render_SyncOnHostData_Disable (0<<12) + #define PM3Render_SyncOnHostData_Enable (1<<12) + #define PM3Render_Texture_Disable (0<<13) + #define PM3Render_Texture_Enable (1<<13) + #define PM3Render_Fog_Disable (0<<14) + #define PM3Render_Fog_Enable (1<<14) + #define PM3Render_Coverage_Disable (0<<15) + #define PM3Render_Coverage_Enable (1<<15) + #define PM3Render_SubPixelCorrection_Disable (0<<16) + #define PM3Render_SubPixelCorrection_Enable (1<<16) + #define PM3Render_SpanOperation_Disable (0<<18) + #define PM3Render_SpanOperation_Enable (1<<18) + #define PM3Render_FBSourceRead_Disable (0<<27) + #define PM3Render_FBSourceRead_Enable (1<<27) +#define PM3RasterizerMode 0x80a0 +#define PM3RasterizerModeAnd 0xaba0 +#define PM3RasterizerModeOr 0xabb8 +#define PM3RectangleHeight 0x94e0 +#define PM3Render 0x8038 +#define PM3RepeatLine 0x9328 +#define PM3ResetPickResult 0x8c20 +#define PM3RLEMask 0x8c48 +#define PM3RouterMode 0x8840 +#define PM3RStart 0x8780 +#define PM3S1Start 0x8400 +#define PM3aveLineStippleCounters 0x81c0 +#define PM3ScissorMaxXY 0x8190 +#define PM3ScissorMinXY 0x8188 +#define PM3ScissorMode 0x8180 +#define PM3ScissorModeAnd 0xabb0 +#define PM3ScissorModeOr 0xabb8 +#define PM3ScreenSize 0x8198 +#define PM3Security 0x8908 +#define PM3SetLogicalTexturePage 0xb360 +#define PM3SizeOfFramebuffer 0xb0a8 +#define PM3SStart 0x8388 +#define PM3StartXDom 0x8000 +#define PM3StartXSub 0x8010 +#define PM3StartY 0x8020 +/* ... */ +#define PM3SpanColorMask 0x8168 +/* ... */ +#define PM3TextureApplicationMode 0x8680 +#define PM3TextureApplicationModeAnd 0xac50 +#define PM3TextureApplicationModeOr 0xac58 +#define PM3TextureBaseAddr 0x8500 +#define PM3TextureCacheControl 0x8490 +#define PM3TextureChromaLower0 0x84f0 +#define PM3TextureChromaLower1 0x8608 +#define PM3TextureChromaUpper0 0x84e8 +#define PM3TextureChromaUpper1 0x8600 +#define PM3TextureCompositeAlphaMode0 0xb310 +#define PM3TextureCompositeAlphaMode0And 0xb390 +#define PM3TextureCompositeAlphaMode0Or 0xb398 +#define PM3TextureCompositeAlphaMode1 0xb320 +#define PM3TextureCompositeAlphaMode1And 0xb3b0 +#define PM3TextureCompositeAlphaMode1Or 0xb3b8 +#define PM3TextureCompositeColorMode0 0xb308 +#define PM3TextureCompositeColorMode0And 0xb380 +#define PM3TextureCompositeColorMode0Or 0xb388 +#define PM3TextureCompositeColorMode1 0xb318 +#define PM3TextureCompositeColorMode1And 0xb3a0 +#define PM3TextureCompositeColorMode1Or 0xb3a8 +#define PM3TextureCompositeFactor0 0xb328 +#define PM3TextureCompositeFactor1 0xb330 +#define PM3TextureCompositeMode 0xb300 +#define PM3TextureCoordMode 0x8380 +#define PM3TextureCoordModeAnd 0xac20 +#define PM3TextureCoordModeOr 0xac28 +#define PM3TextureData 0x88e8 +/* +#define PM3TextureDownloadControl 0x0108 +*/ +#define PM3TextureDownloadOffset 0x88f0 +#define PM3TextureEnvColor 0x8688 +#define PM3TextureFilterMode 0x84e0 +#define PM3TextureFilterModeAnd 0xad50 +#define PM3TextureFilterModeOr 0xad58 +#define PM3TextureIndexMode0 0xb338 +#define PM3TextureIndexMode0And 0xb3c0 +#define PM3TextureIndexMode0Or 0xb3c8 +#define PM3TextureIndexMode1 0xb340 +#define PM3TextureIndexMode1And 0xb3d0 +#define PM3TextureIndexMode1Or 0xb3d8 +#define PM3TextureLODBiasS 0x8450 +#define PM3TextureLODBiasT 0x8458 +/* ... */ +#define PM3TextureMapSize 0xb428 +#define PM3TextureMapWidth0 0x8580 +#define PM3TextureMapWidth1 0x8588 + #define PM3TextureMapWidth_Width(w) ((w&0xfff)<<0) + #define PM3TextureMapWidth_BorderLayout (1<<12) + #define PM3TextureMapWidth_Layout_Linear (0<<13) + #define PM3TextureMapWidth_Layout_Patch64 (1<<13) + #define PM3TextureMapWidth_Layout_Patch32_2 (2<<13) + #define PM3TextureMapWidth_Layout_Patch2 (3<<13) + #define PM3TextureMapWidth_HostTexture (1<<15) +#define PM3TextureReadMode0 0xb400 +#define PM3TextureReadMode0And 0xac30 +#define PM3TextureReadMode0Or 0xac38 +#define PM3TextureReadMode1 0xb408 +#define PM3TextureReadMode1And 0xad40 +#define PM3TextureReadMode1Or 0xad48 +/* ... */ +#define PM3WaitForCompletion 0x80b8 +#define PM3Window 0x8980 + #define PM3Window_ForceLBUpdate 1<<3 + #define PM3Window_LBUpdateSource 1<<4 + #define PM3Window_FrameCount(c) (((c)&0xff)<<9) + #define PM3Window_StencilFCP 1<<17 + #define PM3Window_DepthFCP 1<<18 + #define PM3Window_OverrideWriteFiltering 1<<19 +#define PM3WindowAnd 0xab80 +#define PM3WindowOr 0xab88 +#define PM3WindowOrigin 0x81c8 +#define PM3XBias 0x9480 +#define PM3YBias 0x9488 +#define PM3YLimits 0x80a8 +#define PM3UVMode 0x8f00 +#define PM3ZFogBias 0x86b8 +#define PM3ZStart 0xadd8 +#define PM3ZStartL 0x89b8 +#define PM3ZStartU 0x89b0 + + +/********************************************** +* GLINT Permedia3 2D setup Unit * +***********************************************/ +#define PM3Config2D 0xb618 + #define PM3Config2D_OpaqueSpan 1<<0 + #define PM3Config2D_MultiRXBlit 1<<1 + #define PM3Config2D_UserScissorEnable 1<<2 + #define PM3Config2D_FBDestReadEnable 1<<3 + #define PM3Config2D_AlphaBlendEnable 1<<4 + #define PM3Config2D_DitherEnable 1<<5 + #define PM3Config2D_ForegroundROPEnable 1<<6 + #define PM3Config2D_ForegroundROP(rop) (((rop)&0xf)<<7) + #define PM3Config2D_BackgroundROPEnable 1<<11 + #define PM3Config2D_BackgroundROP(rop) (((rop)&0xf)<<12) + #define PM3Config2D_UseConstantSource 1<<16 + #define PM3Config2D_FBWriteEnable 1<<17 + #define PM3Config2D_Blocking 1<<18 + #define PM3Config2D_ExternalSourceData 1<<19 + #define PM3Config2D_LUTModeEnable 1<<20 +#define PM3DownloadGlyphwidth 0xb658 + #define PM3DownloadGlyphwidth_GlyphWidth(gw) ((gw)&0xffff) +#define PM3DownloadTarget 0xb650 + #define PM3DownloadTarget_TagName(tag) ((tag)&0x1fff) +#define PM3GlyphData 0xb660 +#define PM3GlyphPosition 0xb608 + #define PM3GlyphPosition_XOffset(x) ((x)&0xffff) + #define PM3GlyphPosition_YOffset(y) (((y)&0xffff)<<16) +#define PM3Packed4Pixels 0xb668 +#define PM3Packed8Pixels 0xb630 +#define PM3Packed16Pixels 0xb638 +#define PM3RectanglePosition 0xb600 + #define PM3RectanglePosition_XOffset(x) ((x)&0xffff) + #define PM3RectanglePosition_YOffset(y) (((y)&0xffff)<<16) +#define PM3Render2D 0xb640 + #define PM3Render2D_Width(w) ((w)&0x0fff) + #define PM3Render2D_Operation_Normal 0<<12 + #define PM3Render2D_Operation_SyncOnHostData 1<<12 + #define PM3Render2D_Operation_SyncOnBitMask 2<<12 + #define PM3Render2D_Operation_PatchOrderRendering 3<<12 + #define PM3Render2D_FBSourceReadEnable 1<<14 + #define PM3Render2D_SpanOperation 1<<15 + #define PM3Render2D_Height(h) (((h)&0x0fff)<<16) + #define PM3Render2D_XPositive 1<<28 + #define PM3Render2D_YPositive 1<<29 + #define PM3Render2D_AreaStippleEnable 1<<30 + #define PM3Render2D_TextureEnable 1<<31 +#define PM3Render2DGlyph 0xb648 + #define PM3Render2DGlyph_Width(w) ((w)&0x7f) + #define PM3Render2DGlyph_Height(h) (((h)&0x7f)<<7) + #define PM3Render2DGlyph_XOffset(x) (((x)&0x1ff)<<14) + #define PM3Render2DGlyph_YOffset(y) (((y)&0x1ff)<<23) +#define PM3RenderPatchOffset 0xb610 + #define PM3RenderPatchOffset_XOffset(x) ((x)&0xffff) + #define PM3RenderPatchOffset_YOffset(y) (((y)&0xffff)<<16) +#define PM3RLCount 0xb678 + #define PM3RLCount_Count(c) ((c)&0x0fff) +#define PM3RLData 0xb670 + +/********************************************** +* GLINT Permedia3 Alias Register * +***********************************************/ +#define PM3FillBackgroundColor 0x8330 +#define PM3FillConfig2D0 0x8338 +#define PM3FillConfig2D1 0x8360 + #define PM3FillConfig2D_OpaqueSpan 1<<0 + #define PM3FillConfig2D_MultiRXBlit 1<<1 + #define PM3FillConfig2D_UserScissorEnable 1<<2 + #define PM3FillConfig2D_FBDestReadEnable 1<<3 + #define PM3FillConfig2D_AlphaBlendEnable 1<<4 + #define PM3FillConfig2D_DitherEnable 1<<5 + #define PM3FillConfig2D_ForegroundROPEnable 1<<6 + #define PM3FillConfig2D_ForegroundROP(rop) (((rop)&0xf)<<7) + #define PM3FillConfig2D_BackgroundROPEnable 1<<11 + #define PM3FillConfig2D_BackgroundROP(rop) (((rop)&0xf)<<12) + #define PM3FillConfig2D_UseConstantSource 1<<16 + #define PM3FillConfig2D_FBWriteEnable 1<<17 + #define PM3FillConfig2D_Blocking 1<<18 + #define PM3FillConfig2D_ExternalSourceData 1<<19 + #define PM3FillConfig2D_LUTModeEnable 1<<20 +#define PM3FillFBDestReadBufferAddr 0x8310 +#define PM3FillFBSourceReadBufferAddr 0x8308 +#define PM3FillFBSourceReadBufferOffset 0x8340 + #define PM3FillFBSourceReadBufferOffset_XOffset(x) ((x)&0xffff) + #define PM3FillFBSourceReadBufferOffset_YOffset(y) (((y)&0xffff)<<16) +#define PM3FillFBWriteBufferAddr 0x8300 +#define PM3FillForegroundColor0 0x8328 +#define PM3FillForegroundColor1 0x8358 +#define PM3FillGlyphPosition 0x8368 + #define PM3FillGlyphPosition_XOffset(x) ((x)&0xffff) + #define PM3FillGlyphPosition_YOffset(y) (((y)&0xffff)<<16) +#define PM3FillRectanglePosition 0x8348 + #define PM3FillRectanglePosition_XOffset(x) ((x)&0xffff) + #define PM3FillRectanglePosition_YOffset(y) (((y)&0xffff)<<16) + +#if 1 + +/********************************************** +* GLINT Permedia3 Macros * +***********************************************/ + +extern void *pm3_reg_base; + +#define WRITE_REG(offset,val) \ + *(volatile unsigned long *)(((unsigned char *)(pm3_reg_base)) + (offset)) = (val) + +#define READ_REG(offset) \ + *(volatile unsigned long *)(((unsigned char *)(pm3_reg_base)) + (offset)) + +#define UPDATE_SET_REG(offset,val) \ + { \ + unsigned long temp; \ + temp = READ_REG(offset); \ + WRITE_REG(offset,temp|(val)); \ + } + +#define UPDATE_CLEAR_REG(offset,val) \ + { \ + unsigned long temp; \ + temp = READ_REG(offset); \ + WRITE_REG(offset,temp&(~(val))); \ + } + +#define RAMDAC_DELAY(x) do { \ + int delay = x; \ + unsigned char tmp; \ + while(delay--){tmp = READ_REG(PM3InFIFOSpace);}; \ +} while(0) + +#define SLOW_WRITE_REG(v,r) \ +do{ \ + RAMDAC_DELAY(5); \ + WRITE_REG(v,r); \ + RAMDAC_DELAY(5); \ +}while(0) + +#define RAMDAC_SET_INDEX(index) \ +{ \ + SLOW_WRITE_REG (PM3RD_IndexHigh,((index)>>8)&0xff); \ + SLOW_WRITE_REG (PM3RD_IndexLow,(index)&0xff); \ +} + +#define RAMDAC_SET_REG(index, data) \ +{ \ + RAMDAC_SET_INDEX(index); \ + SLOW_WRITE_REG(PM3RD_IndexedData, data); \ +} + +#define RAMDAC_GET_REG(index, temp) \ +{ \ + RAMDAC_SET_INDEX(index); \ + temp = READ_REG(PM3RD_IndexedData); \ +} +#endif +#endif /* _PM3_REG_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/vidix/pm3_vid.c Sun Apr 01 00:02:43 2007 +0000 @@ -0,0 +1,375 @@ +/** + Driver for 3DLabs GLINT R3 and Permedia3 chips. + + Copyright (C) 2002 Måns Rullgård + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +**/ + +#include <errno.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <inttypes.h> +#include <unistd.h> + +#include "vidix.h" +#include "fourcc.h" +#include "../libdha/libdha.h" +#include "../libdha/pci_ids.h" +#include "../libdha/pci_names.h" +#include "../config.h" + +#include "pm3_regs.h" + +#if 0 +#define TRACE_ENTER() fprintf(stderr, "%s: enter\n", __FUNCTION__) +#define TRACE_EXIT() fprintf(stderr, "%s: exit\n", __FUNCTION__) +#else +#define TRACE_ENTER() +#define TRACE_EXIT() +#endif + +pciinfo_t pci_info; + +void *pm3_reg_base; +void *pm3_mem; + +static vidix_capability_t pm3_cap = +{ + "3DLabs GLINT R3/Permedia3 driver", + "Måns Rullgård <mru@users.sf.net>", + TYPE_OUTPUT, + { 0, 0, 0, 0 }, + 2048, + 2048, + 4, + 4, + -1, + FLAG_UPSCALER|FLAG_DOWNSCALER, + VENDOR_3DLABS, + -1, + { 0, 0, 0, 0 } +}; + + +unsigned int vixGetVersion(void) +{ + return(VIDIX_VERSION); +} + +static unsigned short pm3_card_ids[] = +{ + DEVICE_3DLABS_GLINT_R3 +}; + +static int find_chip(unsigned chip_id) +{ + unsigned i; + for(i = 0;i < sizeof(pm3_card_ids)/sizeof(unsigned short);i++) + { + if(chip_id == pm3_card_ids[i]) return i; + } + return -1; +} + +int vixProbe(int verbose, int force) +{ + pciinfo_t lst[MAX_PCI_DEVICES]; + unsigned i,num_pci; + int err; + + err = pci_scan(lst,&num_pci); + if(err) + { + printf("[pm3] Error occurred during pci scan: %s\n",strerror(err)); + return err; + } + else + { + err = ENXIO; + for(i=0; i < num_pci; i++) + { + if(lst[i].vendor == VENDOR_3DLABS) + { + int idx; + const char *dname; + idx = find_chip(lst[i].device); + if(idx == -1) + continue; + dname = pci_device_name(VENDOR_3DLABS, lst[i].device); + dname = dname ? dname : "Unknown chip"; + printf("[pm3] Found chip: %s\n", dname); + if ((lst[i].command & PCI_COMMAND_IO) == 0) + { + printf("[pm3] Device is disabled, ignoring\n"); + continue; + } + pm3_cap.device_id = lst[i].device; + err = 0; + memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); + break; + } + } + } + if(err && verbose) printf("[pm3] Can't find chip\n"); + return err; +} + +#define PRINT_REG(reg) \ +{ \ + long _foo = READ_REG(reg); \ + printf("[pm3] " #reg " (%x) = %#lx (%li)\n", reg, _foo, _foo); \ +} + +int vixInit(void) +{ + pm3_reg_base = map_phys_mem(pci_info.base0, 0x20000); + pm3_mem = map_phys_mem(pci_info.base2, 0x2000000); + return 0; +} + +void vixDestroy(void) +{ + unmap_phys_mem(pm3_reg_base, 0x20000); + unmap_phys_mem(pm3_mem, 0x2000000); +} + +int vixGetCapability(vidix_capability_t *to) +{ + memcpy(to, &pm3_cap, sizeof(vidix_capability_t)); + return 0; +} + +static int is_supported_fourcc(uint32_t fourcc) +{ + switch(fourcc){ + case IMGFMT_YUY2: + case IMGFMT_UYVY: + return 1; + default: + return 0; + } +} + +int vixQueryFourcc(vidix_fourcc_t *to) +{ + if(is_supported_fourcc(to->fourcc)) + { + to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | + VID_DEPTH_4BPP | VID_DEPTH_8BPP | + VID_DEPTH_12BPP| VID_DEPTH_15BPP| + VID_DEPTH_16BPP| VID_DEPTH_24BPP| + VID_DEPTH_32BPP; + to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; + return 0; + } + else to->depth = to->flags = 0; + return ENOSYS; +} + +#define FORMAT_RGB8888 PM3VideoOverlayMode_COLORFORMAT_RGB8888 +#define FORMAT_RGB4444 PM3VideoOverlayMode_COLORFORMAT_RGB4444 +#define FORMAT_RGB5551 PM3VideoOverlayMode_COLORFORMAT_RGB5551 +#define FORMAT_RGB565 PM3VideoOverlayMode_COLORFORMAT_RGB565 +#define FORMAT_RGB332 PM3VideoOverlayMode_COLORFORMAT_RGB332 +#define FORMAT_BGR8888 PM3VideoOverlayMode_COLORFORMAT_BGR8888 +#define FORMAT_BGR4444 PM3VideoOverlayMode_COLORFORMAT_BGR4444 +#define FORMAT_BGR5551 PM3VideoOverlayMode_COLORFORMAT_BGR5551 +#define FORMAT_BGR565 PM3VideoOverlayMode_COLORFORMAT_BGR565 +#define FORMAT_BGR332 PM3VideoOverlayMode_COLORFORMAT_BGR332 +#define FORMAT_CI8 PM3VideoOverlayMode_COLORFORMAT_CI8 +#define FORMAT_VUY444 PM3VideoOverlayMode_COLORFORMAT_VUY444 +#define FORMAT_YUV444 PM3VideoOverlayMode_COLORFORMAT_YUV444 +#define FORMAT_VUY422 PM3VideoOverlayMode_COLORFORMAT_VUY422 +#define FORMAT_YUV422 PM3VideoOverlayMode_COLORFORMAT_YUV422 + +/* Notice, have to check that we don't overflow the deltas here ... */ +static void +compute_scale_factor( + short* src_w, short* dst_w, + unsigned int* shrink_delta, unsigned int* zoom_delta) +{ + /* NOTE: If we don't return reasonable values here then the video + * unit can potential shut off and won't display an image until re-enabled. + * Seems as though the zoom_delta is o.k, and I've not had the problem. + * The 'shrink_delta' is prone to this the most - FIXME ! */ + + if (*src_w >= *dst_w) { + *src_w &= ~0x3; + *dst_w &= ~0x3; + *shrink_delta = (((*src_w << 16) / *dst_w) + 0x0f) & 0x0ffffff0; + *zoom_delta = 1<<16; + if ( ((*shrink_delta * *dst_w) >> 16) & 0x03 ) + *shrink_delta += 0x10; + } else { + *src_w &= ~0x3; + *dst_w &= ~0x3; + *zoom_delta = (((*src_w << 16) / *dst_w) + 0x0f) & 0x0001fff0; + *shrink_delta = 1<<16; + if ( ((*zoom_delta * *dst_w) >> 16) & 0x03 ) + *zoom_delta += 0x10; + } +} + +static int frames[VID_PLAY_MAXFRAMES]; + +static long overlay_mode, overlay_control; + +int vixConfigPlayback(vidix_playback_t *info) +{ + int shrink, zoom; + short src_w, drw_w; + short src_h, drw_h; + long base0; + int pitch; + int format; + unsigned int i; + + TRACE_ENTER(); + + if(!is_supported_fourcc(info->fourcc)) + return -1; + + switch(info->fourcc){ + case IMGFMT_YUY2: + format = FORMAT_YUV422; + break; + case IMGFMT_UYVY: + format = FORMAT_VUY422; + break; + default: + return -1; + } + + src_w = info->src.w; + src_h = info->src.h; + + drw_w = info->dest.w; + drw_h = info->dest.h; + + pitch = src_w; + + /* Assume we have 16 MB to play with */ + info->num_frames = 0x1000000 / (pitch * src_h * 2); + if(info->num_frames > VID_PLAY_MAXFRAMES) + info->num_frames = VID_PLAY_MAXFRAMES; + + /* Start at 16 MB. Let's hope it's not in use. */ + base0 = 0x1000000; + info->dga_addr = pm3_mem + base0; + + info->dest.pitch.y = 2; + info->dest.pitch.u = 0; + info->dest.pitch.v = 0; + info->offset.y = 0; + info->offset.v = 0; + info->offset.u = 0; + info->frame_size = pitch * src_h * 2; + for(i = 0; i < info->num_frames; i++){ + info->offsets[i] = info->frame_size * i; + frames[i] = (base0 + info->offsets[i]) >> 1; + } + + compute_scale_factor(&src_w, &drw_w, &shrink, &zoom); + + WRITE_REG(PM3VideoOverlayBase0, base0 >> 1); + WRITE_REG(PM3VideoOverlayStride, PM3VideoOverlayStride_STRIDE(pitch)); + WRITE_REG(PM3VideoOverlayWidth, PM3VideoOverlayWidth_WIDTH(src_w)); + WRITE_REG(PM3VideoOverlayHeight, PM3VideoOverlayHeight_HEIGHT(src_h)); + WRITE_REG(PM3VideoOverlayOrigin, 0); + + /* Scale the source to the destinationsize */ + if (src_h == drw_h) { + WRITE_REG(PM3VideoOverlayYDelta, PM3VideoOverlayYDelta_NONE); + } else { + WRITE_REG(PM3VideoOverlayYDelta, + PM3VideoOverlayYDelta_DELTA(src_h, drw_h)); + } + if (src_w == drw_w) { + WRITE_REG(PM3VideoOverlayShrinkXDelta, 1<<16); + WRITE_REG(PM3VideoOverlayZoomXDelta, 1<<16); + } else { + WRITE_REG(PM3VideoOverlayShrinkXDelta, shrink); + WRITE_REG(PM3VideoOverlayZoomXDelta, zoom); + } + WRITE_REG(PM3VideoOverlayIndex, 0); + + /* Now set the ramdac video overlay region and mode */ + RAMDAC_SET_REG(PM3RD_VideoOverlayXStartLow, (info->dest.x & 0xff)); + RAMDAC_SET_REG(PM3RD_VideoOverlayXStartHigh, (info->dest.x & 0xf00)>>8); + RAMDAC_SET_REG(PM3RD_VideoOverlayXEndLow, (info->dest.x+drw_w) & 0xff); + RAMDAC_SET_REG(PM3RD_VideoOverlayXEndHigh, + ((info->dest.x+drw_w) & 0xf00)>>8); + RAMDAC_SET_REG(PM3RD_VideoOverlayYStartLow, (info->dest.y & 0xff)); + RAMDAC_SET_REG(PM3RD_VideoOverlayYStartHigh, (info->dest.y & 0xf00)>>8); + RAMDAC_SET_REG(PM3RD_VideoOverlayYEndLow, (info->dest.y+drw_h) & 0xff); + RAMDAC_SET_REG(PM3RD_VideoOverlayYEndHigh, + ((info->dest.y+drw_h) & 0xf00)>>8); + + RAMDAC_SET_REG(PM3RD_VideoOverlayKeyR, 0xff); + RAMDAC_SET_REG(PM3RD_VideoOverlayKeyG, 0x00); + RAMDAC_SET_REG(PM3RD_VideoOverlayKeyB, 0xff); + + overlay_mode = + 1 << 5 | + format | + PM3VideoOverlayMode_FILTER_FULL | + PM3VideoOverlayMode_BUFFERSYNC_MANUAL | + PM3VideoOverlayMode_FLIP_VIDEO; + + overlay_control = + PM3RD_VideoOverlayControl_KEY_COLOR | + PM3RD_VideoOverlayControl_MODE_MAINKEY | + PM3RD_VideoOverlayControl_DIRECTCOLOR_ENABLED; + + TRACE_EXIT(); + return 0; +} + +int vixPlaybackOn(void) +{ + TRACE_ENTER(); + + WRITE_REG(PM3VideoOverlayMode, + overlay_mode | PM3VideoOverlayMode_ENABLE); + RAMDAC_SET_REG(PM3RD_VideoOverlayControl, + overlay_control | PM3RD_VideoOverlayControl_ENABLE); + WRITE_REG(PM3VideoOverlayUpdate, + PM3VideoOverlayUpdate_ENABLE); + + TRACE_EXIT(); + return 0; +} + +int vixPlaybackOff(void) +{ + RAMDAC_SET_REG(PM3RD_VideoOverlayControl, + PM3RD_VideoOverlayControl_DISABLE); + WRITE_REG(PM3VideoOverlayMode, + PM3VideoOverlayMode_DISABLE); + + RAMDAC_SET_REG(PM3RD_VideoOverlayKeyR, 0x01); + RAMDAC_SET_REG(PM3RD_VideoOverlayKeyG, 0x01); + RAMDAC_SET_REG(PM3RD_VideoOverlayKeyB, 0xfe); + + return 0; +} + +int vixPlaybackFrameSelect(unsigned int frame) +{ + WRITE_REG(PM3VideoOverlayBase0, frames[frame]); + return 0; +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/vidix/radeon.h Sun Apr 01 00:02:43 2007 +0000 @@ -0,0 +1,2156 @@ +/* + * radeon.h + * This software has been released under the terms of the GNU Public + * license. See http://www.gnu.org/copyleft/gpl.html for details. + * + * This collection of definition was written by Nick Kurshev + * It's based on radeonfb, X11, GATOS sources + * and partly compatible with Rage128 set (in OV0, CAP0, CAP1 parts) +*/ + +#ifndef _RADEON_H +#define _RADEON_H + +#define RADEON_REGSIZE 0x4000 +#define MM_INDEX 0x0000 +/* MM_INDEX bit constants */ +# define MM_APER 0x80000000 +#define MM_DATA 0x0004 +#define BUS_CNTL 0x0030 +/* BUS_CNTL bit constants */ +# define BUS_DBL_RESYNC 0x00000001 +# define BUS_MSTR_RESET 0x00000002 +# define BUS_FLUSH_BUF 0x00000004 +# define BUS_STOP_REQ_DIS 0x00000008 +# define BUS_ROTATION_DIS 0x00000010 +# define BUS_MASTER_DIS 0x00000040 +# define BUS_ROM_WRT_EN 0x00000080 +# define BUS_DIS_ROM 0x00001000 +# define BUS_PCI_READ_RETRY_EN 0x00002000 +# define BUS_AGP_AD_STEPPING_EN 0x00004000 +# define BUS_PCI_WRT_RETRY_EN 0x00008000 +# define BUS_MSTR_RD_MULT 0x00100000 +# define BUS_MSTR_RD_LINE 0x00200000 +# define BUS_SUSPEND 0x00400000 +# define LAT_16X 0x00800000 +# define BUS_RD_DISCARD_EN 0x01000000 +# define BUS_RD_ABORT_EN 0x02000000 +# define BUS_MSTR_WS 0x04000000 +# define BUS_PARKING_DIS 0x08000000 +# define BUS_MSTR_DISCONNECT_EN 0x10000000 +# define BUS_WRT_BURST 0x20000000 +# define BUS_READ_BURST 0x40000000 +# define BUS_RDY_READ_DLY 0x80000000 +#define HI_STAT 0x004C +#define BUS_CNTL1 0x0034 +# define BUS_WAIT_ON_LOCK_EN (1 << 4) +#define I2C_CNTL_0 0x0090 +# define I2C_DONE (1<<0) +# define I2C_NACK (1<<1) +# define I2C_HALT (1<<2) +# define I2C_SOFT_RST (1<<5) +# define I2C_DRIVE_EN (1<<6) +# define I2C_DRIVE_SEL (1<<7) +# define I2C_START (1<<8) +# define I2C_STOP (1<<9) +# define I2C_RECEIVE (1<<10) +# define I2C_ABORT (1<<11) +# define I2C_GO (1<<12) +# define I2C_SEL (1<<16) +# define I2C_EN (1<<17) +#define I2C_CNTL_1 0x0094 +#define I2C_DATA 0x0098 +#define CONFIG_CNTL 0x00E0 +/* CONFIG_CNTL bit constants */ +# define CFG_VGA_RAM_EN 0x00000100 +#ifdef RAGE128 +#define GEN_RESET_CNTL 0x00f0 +# define SOFT_RESET_GUI 0x00000001 +# define SOFT_RESET_VCLK 0x00000100 +# define SOFT_RESET_PCLK 0x00000200 +# define SOFT_RESET_ECP 0x00000400 +# define SOFT_RESET_DISPENG_XCLK 0x00000800 +# define SOFT_RESET_MEMCTLR_XCLK 0x00001000 +#endif +#define CONFIG_MEMSIZE 0x00F8 +#define CONFIG_APER_0_BASE 0x0100 +#define CONFIG_APER_1_BASE 0x0104 +#define CONFIG_APER_SIZE 0x0108 +#define CONFIG_REG_1_BASE 0x010C +#define CONFIG_REG_APER_SIZE 0x0110 +#define PAD_AGPINPUT_DELAY 0x0164 +#define PAD_CTLR_STRENGTH 0x0168 +#define PAD_CTLR_UPDATE 0x016C +#define AGP_CNTL 0x0174 +# define AGP_APER_SIZE_256MB (0x00 << 0) +# define AGP_APER_SIZE_128MB (0x20 << 0) +# define AGP_APER_SIZE_64MB (0x30 << 0) +# define AGP_APER_SIZE_32MB (0x38 << 0) +# define AGP_APER_SIZE_16MB (0x3c << 0) +# define AGP_APER_SIZE_8MB (0x3e << 0) +# define AGP_APER_SIZE_4MB (0x3f << 0) +# define AGP_APER_SIZE_MASK (0x3f << 0) +#define AMCGPIO_A_REG 0x01a0 +#define AMCGPIO_EN_REG 0x01a8 +#define AMCGPIO_MASK 0x0194 +#define AMCGPIO_Y_REG 0x01a4 +/*#define BM_STATUS 0x0160*/ +#define MPP_TB_CONFIG 0x01c0 /* ? */ +#define MPP_GP_CONFIG 0x01c8 /* ? */ +#define VENDOR_ID 0x0F00 +#define DEVICE_ID 0x0F02 +#define COMMAND 0x0F04 +#define STATUS 0x0F06 +#define REVISION_ID 0x0F08 +#define REGPROG_INF 0x0F09 +#define SUB_CLASS 0x0F0A +#define CACHE_LINE 0x0F0C +#define LATENCY 0x0F0D +#define HEADER 0x0F0E +#define BIST 0x0F0F +#define REG_MEM_BASE 0x0F10 +#define REG_IO_BASE 0x0F14 +#define REG_REG_BASE 0x0F18 +#define ADAPTER_ID 0x0F2C +#define BIOS_ROM 0x0F30 +#define CAPABILITIES_PTR 0x0F34 +#define INTERRUPT_LINE 0x0F3C +#define INTERRUPT_PIN 0x0F3D +#define MIN_GRANT 0x0F3E +#define MAX_LATENCY 0x0F3F +#define ADAPTER_ID_W 0x0F4C +#define PMI_CAP_ID 0x0F50 +#define PMI_NXT_CAP_PTR 0x0F51 +#define PMI_PMC_REG 0x0F52 +#define PM_STATUS 0x0F54 +#define PMI_DATA 0x0F57 +#define AGP_CAP_ID 0x0F58 +#define AGP_STATUS 0x0F5C +# define AGP_1X_MODE 0x01 +# define AGP_2X_MODE 0x02 +# define AGP_4X_MODE 0x04 +# define AGP_MODE_MASK 0x07 +#define AGP_COMMAND 0x0F60 + +/* Video muxer unit */ +#define VIDEOMUX_CNTL 0x0190 +#define VIPPAD_MASK 0x0198 +#define VIPPAD1_A 0x01AC +#define VIPPAD1_EN 0x01B0 +#define VIPPAD1_Y 0x01B4 + +#define AIC_CTRL 0x01D0 +#define AIC_STAT 0x01D4 +#define AIC_PT_BASE 0x01D8 +#define AIC_LO_ADDR 0x01DC +#define AIC_HI_ADDR 0x01E0 +#define AIC_TLB_ADDR 0x01E4 +#define AIC_TLB_DATA 0x01E8 +#define DAC_CNTL 0x0058 +/* DAC_CNTL bit constants */ +# define DAC_8BIT_EN 0x00000100 +# define DAC_4BPP_PIX_ORDER 0x00000200 +# define DAC_CRC_EN 0x00080000 +# define DAC_MASK_ALL (0xff << 24) +# define DAC_VGA_ADR_EN (1 << 13) +# define DAC_RANGE_CNTL (3 << 0) +# define DAC_BLANKING (1 << 2) +#define DAC_CNTL2 0x007c +/* DAC_CNTL2 bit constants */ +# define DAC2_DAC_CLK_SEL (1 << 0) +# define DAC2_DAC2_CLK_SEL (1 << 1) +# define DAC2_PALETTE_ACC_CTL (1 << 5) +#define TV_DAC_CNTL 0x088c +/* TV_DAC_CNTL bit constants */ +# define TV_DAC_STD_MASK 0x0300 +# define TV_DAC_RDACPD (1 << 24) +# define TV_DAC_GDACPD (1 << 25) +# define TV_DAC_BDACPD (1 << 26) +#define CRTC_GEN_CNTL 0x0050 +/* CRTC_GEN_CNTL bit constants */ +# define CRTC_DBL_SCAN_EN 0x00000001 +# define CRTC_INTERLACE_EN (1 << 1) +# define CRTC_CSYNC_EN (1 << 4) +# define CRTC_CUR_EN 0x00010000 +# define CRTC_CUR_MODE_MASK (7 << 17) +# define CRTC_ICON_EN (1 << 20) +# define CRTC_EXT_DISP_EN (1 << 24) +# define CRTC_EN (1 << 25) +# define CRTC_DISP_REQ_EN_B (1 << 26) +#define CRTC2_GEN_CNTL 0x03f8 +/* CRTC2_GEN_CNTL bit constants */ +# define CRTC2_DBL_SCAN_EN (1 << 0) +# define CRTC2_INTERLACE_EN (1 << 1) +# define CRTC2_SYNC_TRISTAT (1 << 4) +# define CRTC2_HSYNC_TRISTAT (1 << 5) +# define CRTC2_VSYNC_TRISTAT (1 << 6) +# define CRTC2_CRT2_ON (1 << 7) +# define CRTC2_ICON_EN (1 << 15) +# define CRTC2_CUR_EN (1 << 16) +# define CRTC2_CUR_MODE_MASK (7 << 20) +# define CRTC2_DISP_DIS (1 << 23) +# define CRTC2_EN (1 << 25) +# define CRTC2_DISP_REQ_EN_B (1 << 26) +# define CRTC2_HSYNC_DIS (1 << 28) +# define CRTC2_VSYNC_DIS (1 << 29) +#define MEM_CNTL 0x0140 +/* MEM_CNTL bit constants */ +# define MEM_CTLR_STATUS_IDLE 0x00000000 +# define MEM_CTLR_STATUS_BUSY 0x00100000 +# define MEM_SEQNCR_STATUS_IDLE 0x00000000 +# define MEM_SEQNCR_STATUS_BUSY 0x00200000 +# define MEM_ARBITER_STATUS_IDLE 0x00000000 +# define MEM_ARBITER_STATUS_BUSY 0x00400000 +# define MEM_REQ_UNLOCK 0x00000000 +# define MEM_REQ_LOCK 0x00800000 +#define EXT_MEM_CNTL 0x0144 +#define MC_AGP_LOCATION 0x014C +#define MEM_IO_CNTL_A0 0x0178 +#define MEM_INIT_LATENCY_TIMER 0x0154 +#define MEM_SDRAM_MODE_REG 0x0158 +#define AGP_BASE 0x0170 +#ifdef RAGE128 +#define PCI_GART_PAGE 0x017c +#define PC_NGUI_MODE 0x0180 +#define PC_NGUI_CTLSTAT 0x0184 +# define PC_FLUSH_GUI (3 << 0) +# define PC_RI_GUI (1 << 2) +# define PC_FLUSH_ALL 0x00ff +# define PC_BUSY (1 << 31) +#define PC_MISC_CNTL 0x0188 +#else +#define MEM_IO_CNTL_A1 0x017C +#define MEM_IO_CNTL_B0 0x0180 +#define MEM_IO_CNTL_B1 0x0184 +#define MC_DEBUG 0x0188 +#endif +#define MC_STATUS 0x0150 +#define MEM_IO_OE_CNTL 0x018C +#define MC_FB_LOCATION 0x0148 +#define HOST_PATH_CNTL 0x0130 +#define MEM_VGA_WP_SEL 0x0038 +#define MEM_VGA_RP_SEL 0x003C +#define HDP_DEBUG 0x0138 +#define SW_SEMAPHORE 0x013C +#define SURFACE_CNTL 0x0B00 +/* SURFACE_CNTL bit constants */ +# define SURF_TRANSLATION_DIS (1 << 8) +# define NONSURF_AP0_SWP_16BPP (1 << 20) +# define NONSURF_AP0_SWP_32BPP (2 << 20) +#define SURFACE0_LOWER_BOUND 0x0B04 +#define SURFACE1_LOWER_BOUND 0x0B14 +#define SURFACE2_LOWER_BOUND 0x0B24 +#define SURFACE3_LOWER_BOUND 0x0B34 +#define SURFACE4_LOWER_BOUND 0x0B44 +#define SURFACE5_LOWER_BOUND 0x0B54 +#define SURFACE6_LOWER_BOUND 0x0B64 +#define SURFACE7_LOWER_BOUND 0x0B74 +#define SURFACE0_UPPER_BOUND 0x0B08 +#define SURFACE1_UPPER_BOUND 0x0B18 +#define SURFACE2_UPPER_BOUND 0x0B28 +#define SURFACE3_UPPER_BOUND 0x0B38 +#define SURFACE4_UPPER_BOUND 0x0B48 +#define SURFACE5_UPPER_BOUND 0x0B58 +#define SURFACE6_UPPER_BOUND 0x0B68 +#define SURFACE7_UPPER_BOUND 0x0B78 +#define SURFACE0_INFO 0x0B0C +#define SURFACE1_INFO 0x0B1C +#define SURFACE2_INFO 0x0B2C +#define SURFACE3_INFO 0x0B3C +#define SURFACE4_INFO 0x0B4C +#define SURFACE5_INFO 0x0B5C +#define SURFACE6_INFO 0x0B6C +#define SURFACE7_INFO 0x0B7C +#define SURFACE_ACCESS_FLAGS 0x0BF8 +#define SURFACE_ACCESS_CLR 0x0BFC +#define GEN_INT_CNTL 0x0040 +#define GEN_INT_STATUS 0x0044 +# define VSYNC_INT_AK (1 << 2) +# define VSYNC_INT (1 << 2) +#define CRTC_EXT_CNTL 0x0054 +/* CRTC_EXT_CNTL bit constants */ +# define CRTC_VGA_XOVERSCAN (1 << 0) +# define VGA_ATI_LINEAR 0x00000008 +# define VGA_128KAP_PAGING 0x00000010 +# define XCRT_CNT_EN (1 << 6) +# define CRTC_HSYNC_DIS (1 << 8) +# define CRTC_VSYNC_DIS (1 << 9) +# define CRTC_DISPLAY_DIS (1 << 10) +# define CRTC_SYNC_TRISTAT (1 << 11) +# define CRTC_CRT_ON (1 << 15) +#define CRTC_EXT_CNTL_DPMS_BYTE 0x0055 +# define CRTC_HSYNC_DIS_BYTE (1 << 0) +# define CRTC_VSYNC_DIS_BYTE (1 << 1) +# define CRTC_DISPLAY_DIS_BYTE (1 << 2) +#define RB3D_CNTL 0x1C3C +#define WAIT_UNTIL 0x1720 +#define ISYNC_CNTL 0x1724 +#define RBBM_GUICNTL 0x172C +#define RBBM_STATUS 0x0E40 +# define RBBM_FIFOCNT_MASK 0x007f +# define RBBM_ACTIVE (1 << 31) +#define RBBM_STATUS_alt_1 0x1740 +#define RBBM_CNTL 0x00EC +#define RBBM_CNTL_alt_1 0x0E44 +#define RBBM_SOFT_RESET 0x00F0 +/* RBBM_SOFT_RESET bit constants */ +# define SOFT_RESET_CP (1 << 0) +# define SOFT_RESET_HI (1 << 1) +# define SOFT_RESET_SE (1 << 2) +# define SOFT_RESET_RE (1 << 3) +# define SOFT_RESET_PP (1 << 4) +# define SOFT_RESET_E2 (1 << 5) +# define SOFT_RESET_RB (1 << 6) +# define SOFT_RESET_HDP (1 << 7) +#define RBBM_SOFT_RESET_alt_1 0x0E48 +#define NQWAIT_UNTIL 0x0E50 +#define RBBM_DEBUG 0x0E6C +#define RBBM_CMDFIFO_ADDR 0x0E70 +#define RBBM_CMDFIFO_DATAL 0x0E74 +#define RBBM_CMDFIFO_DATAH 0x0E78 +#define RBBM_CMDFIFO_STAT 0x0E7C +#define CRTC_STATUS 0x005C +/* CRTC_STATUS bit constants */ +# define CRTC_VBLANK 0x00000001 +# define CRTC_VBLANK_SAVE ( 1 << 1) +#define GPIO_VGA_DDC 0x0060 +#define GPIO_DVI_DDC 0x0064 +#define GPIO_MONID 0x0068 +#define PALETTE_INDEX 0x00B0 +#define PALETTE_DATA 0x00B4 +#define PALETTE_30_DATA 0x00B8 +#define CRTC_H_TOTAL_DISP 0x0200 +# define CRTC_H_TOTAL (0x03ff << 0) +# define CRTC_H_TOTAL_SHIFT 0 +# define CRTC_H_DISP (0x01ff << 16) +# define CRTC_H_DISP_SHIFT 16 +#define CRTC2_H_TOTAL_DISP 0x0300 +# define CRTC2_H_TOTAL (0x03ff << 0) +# define CRTC2_H_TOTAL_SHIFT 0 +# define CRTC2_H_DISP (0x01ff << 16) +# define CRTC2_H_DISP_SHIFT 16 +#define CRTC_H_SYNC_STRT_WID 0x0204 +# define CRTC_H_SYNC_STRT_PIX (0x07 << 0) +# define CRTC_H_SYNC_STRT_CHAR (0x3ff << 3) +# define CRTC_H_SYNC_STRT_CHAR_SHIFT 3 +# define CRTC_H_SYNC_WID (0x3f << 16) +# define CRTC_H_SYNC_WID_SHIFT 16 +# define CRTC_H_SYNC_POL (1 << 23) +#define CRTC2_H_SYNC_STRT_WID 0x0304 +# define CRTC2_H_SYNC_STRT_PIX (0x07 << 0) +# define CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3) +# define CRTC2_H_SYNC_STRT_CHAR_SHIFT 3 +# define CRTC2_H_SYNC_WID (0x3f << 16) +# define CRTC2_H_SYNC_WID_SHIFT 16 +# define CRTC2_H_SYNC_POL (1 << 23) +#define CRTC_V_TOTAL_DISP 0x0208 +# define CRTC_V_TOTAL (0x07ff << 0) +# define CRTC_V_TOTAL_SHIFT 0 +# define CRTC_V_DISP (0x07ff << 16) +# define CRTC_V_DISP_SHIFT 16 +#define CRTC2_V_TOTAL_DISP 0x0308 +# define CRTC2_V_TOTAL (0x07ff << 0) +# define CRTC2_V_TOTAL_SHIFT 0 +# define CRTC2_V_DISP (0x07ff << 16) +# define CRTC2_V_DISP_SHIFT 16 +#define CRTC_V_SYNC_STRT_WID 0x020C +# define CRTC_V_SYNC_STRT (0x7ff << 0) +# define CRTC_V_SYNC_STRT_SHIFT 0 +# define CRTC_V_SYNC_WID (0x1f << 16) +# define CRTC_V_SYNC_WID_SHIFT 16 +# define CRTC_V_SYNC_POL (1 << 23) +#define CRTC2_V_SYNC_STRT_WID 0x030C +# define CRTC2_V_SYNC_STRT (0x7ff << 0) +# define CRTC2_V_SYNC_STRT_SHIFT 0 +# define CRTC2_V_SYNC_WID (0x1f << 16) +# define CRTC2_V_SYNC_WID_SHIFT 16 +# define CRTC2_V_SYNC_POL (1 << 23) +#define CRTC_VLINE_CRNT_VLINE 0x0210 +# define CRTC_CRNT_VLINE_MASK (0x7ff << 16) +#define CRTC2_VLINE_CRNT_VLINE 0x0310 +#define CRTC_CRNT_FRAME 0x0214 +#define CRTC2_CRNT_FRAME 0x0314 +#define CRTC_GUI_TRIG_VLINE 0x0218 +#define CRTC2_GUI_TRIG_VLINE 0x0318 +#define CRTC_DEBUG 0x021C +#define CRTC2_DEBUG 0x031C +#define CRTC_OFFSET_RIGHT 0x0220 +#define CRTC_OFFSET 0x0224 +#define CRTC2_OFFSET 0x0324 +#define CRTC_OFFSET_CNTL 0x0228 +# define CRTC_TILE_EN (1 << 15) +#define CRTC2_OFFSET_CNTL 0x0328 +# define CRTC2_TILE_EN (1 << 15) +#define CRTC_PITCH 0x022C +#define CRTC2_PITCH 0x032C +#define TMDS_CRC 0x02a0 +#define OVR_CLR 0x0230 +#define OVR_WID_LEFT_RIGHT 0x0234 +#define OVR_WID_TOP_BOTTOM 0x0238 +#define DISPLAY_BASE_ADDR 0x023C +#define SNAPSHOT_VH_COUNTS 0x0240 +#define SNAPSHOT_F_COUNT 0x0244 +#define N_VIF_COUNT 0x0248 +#define SNAPSHOT_VIF_COUNT 0x024C +#define FP_CRTC_H_TOTAL_DISP 0x0250 +#define FP_CRTC2_H_TOTAL_DISP 0x0350 +#define FP_CRTC_V_TOTAL_DISP 0x0254 +#define FP_CRTC2_V_TOTAL_DISP 0x0354 +# define FP_CRTC_H_TOTAL_MASK 0x000003ff +# define FP_CRTC_H_DISP_MASK 0x01ff0000 +# define FP_CRTC_V_TOTAL_MASK 0x00000fff +# define FP_CRTC_V_DISP_MASK 0x0fff0000 +# define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 +# define FP_H_SYNC_WID_MASK 0x003f0000 +# define FP_V_SYNC_STRT_MASK 0x00000fff +# define FP_V_SYNC_WID_MASK 0x001f0000 +# define FP_CRTC_H_TOTAL_SHIFT 0x00000000 +# define FP_CRTC_H_DISP_SHIFT 0x00000010 +# define FP_CRTC_V_TOTAL_SHIFT 0x00000000 +# define FP_CRTC_V_DISP_SHIFT 0x00000010 +# define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 +# define FP_H_SYNC_WID_SHIFT 0x00000010 +# define FP_V_SYNC_STRT_SHIFT 0x00000000 +# define FP_V_SYNC_WID_SHIFT 0x00000010 +#define CRT_CRTC_H_SYNC_STRT_WID 0x0258 +#define CRT_CRTC_V_SYNC_STRT_WID 0x025C +#define CUR_OFFSET 0x0260 +#define CUR_HORZ_VERT_POSN 0x0264 +#define CUR_HORZ_VERT_OFF 0x0268 +/* CUR_OFFSET, CUR_HORZ_VERT_POSN, CUR_HORZ_VERT_OFF bit constants */ +# define CUR_LOCK 0x80000000 +#define CUR_CLR0 0x026C +#define CUR_CLR1 0x0270 +#define CUR2_OFFSET 0x0360 +#define CUR2_HORZ_VERT_POSN 0x0364 +#define CUR2_HORZ_VERT_OFF 0x0368 +# define CUR2_LOCK (1 << 31) +#define CUR2_CLR0 0x036c +#define CUR2_CLR1 0x0370 +#define FP_HORZ_VERT_ACTIVE 0x0278 +#define CRTC_MORE_CNTL 0x027C +#define DAC_EXT_CNTL 0x0280 +#define FP_GEN_CNTL 0x0284 +/* FP_GEN_CNTL bit constants */ +# define FP_FPON (1 << 0) +# define FP_TMDS_EN (1 << 2) +# define FP_EN_TMDS (1 << 7) +# define FP_DETECT_SENSE (1 << 8) +# define FP_SEL_CRTC2 (1 << 13) +# define FP_CRTC_DONT_SHADOW_HPAR (1 << 15) +# define FP_CRTC_DONT_SHADOW_VPAR (1 << 16) +# define FP_CRTC_DONT_SHADOW_HEND (1 << 17) +# define FP_CRTC_USE_SHADOW_VEND (1 << 18) +# define FP_RMX_HVSYNC_CONTROL_EN (1 << 20) +# define FP_DFP_SYNC_SEL (1 << 21) +# define FP_CRTC_LOCK_8DOT (1 << 22) +# define FP_CRT_SYNC_SEL (1 << 23) +# define FP_USE_SHADOW_EN (1 << 24) +# define FP_CRT_SYNC_ALT (1 << 26) +#define FP2_GEN_CNTL 0x0288 +/* FP2_GEN_CNTL bit constants */ +# define FP2_FPON (1 << 0) +# define FP2_TMDS_EN (1 << 2) +# define FP2_EN_TMDS (1 << 7) +# define FP2_DETECT_SENSE (1 << 8) +# define FP2_SEL_CRTC2 (1 << 13) +# define FP2_FP_POL (1 << 16) +# define FP2_LP_POL (1 << 17) +# define FP2_SCK_POL (1 << 18) +# define FP2_LCD_CNTL_MASK (7 << 19) +# define FP2_PAD_FLOP_EN (1 << 22) +# define FP2_CRC_EN (1 << 23) +# define FP2_CRC_READ_EN (1 << 24) +#define FP_HORZ_STRETCH 0x028C +#define FP_HORZ2_STRETCH 0x038C +# define HORZ_STRETCH_RATIO_MASK 0xffff +# define HORZ_STRETCH_RATIO_MAX 4096 +# define HORZ_PANEL_SIZE (0x1ff << 16) +# define HORZ_PANEL_SHIFT 16 +# define HORZ_STRETCH_PIXREP (0 << 25) +# define HORZ_STRETCH_BLEND (1 << 26) +# define HORZ_STRETCH_ENABLE (1 << 25) +# define HORZ_AUTO_RATIO (1 << 27) +# define HORZ_FP_LOOP_STRETCH (0x7 << 28) +# define HORZ_AUTO_RATIO_INC (1 << 31) +#define FP_VERT_STRETCH 0x0290 +#define FP_VERT2_STRETCH 0x0390 +# define VERT_PANEL_SIZE (0xfff << 12) +# define VERT_PANEL_SHIFT 12 +# define VERT_STRETCH_RATIO_MASK 0xfff +# define VERT_STRETCH_RATIO_SHIFT 0 +# define VERT_STRETCH_RATIO_MAX 4096 +# define VERT_STRETCH_ENABLE (1 << 25) +# define VERT_STRETCH_LINEREP (0 << 26) +# define VERT_STRETCH_BLEND (1 << 26) +# define VERT_AUTO_RATIO_EN (1 << 27) +# define VERT_STRETCH_RESERVED 0xf1000000 +#define FP_H_SYNC_STRT_WID 0x02C4 +#define FP_H2_SYNC_STRT_WID 0x03C4 +#define FP_V_SYNC_STRT_WID 0x02C8 +#define FP_V2_SYNC_STRT_WID 0x03C8 +#define LVDS_GEN_CNTL 0x02d0 +# define LVDS_ON (1 << 0) +# define LVDS_DISPLAY_DIS (1 << 1) +# define LVDS_PANEL_TYPE (1 << 2) +# define LVDS_PANEL_FORMAT (1 << 3) +# define LVDS_EN (1 << 7) +# define LVDS_DIGON (1 << 18) +# define LVDS_BLON (1 << 19) +# define LVDS_SEL_CRTC2 (1 << 23) +#define LVDS_PLL_CNTL 0x02d4 +# define HSYNC_DELAY_SHIFT 28 +# define HSYNC_DELAY_MASK (0xf << 28) +#define AUX_WINDOW_HORZ_CNTL 0x02D8 +#define AUX_WINDOW_VERT_CNTL 0x02DC +#define DDA_CONFIG 0x02e0 +#define DDA_ON_OFF 0x02e4 + +#define GRPH_BUFFER_CNTL 0x02F0 +#define VGA_BUFFER_CNTL 0x02F4 + +/* first overlay unit (there is only one) */ + +#define OV0_Y_X_START 0x0400 +#define OV0_Y_X_END 0x0404 +#define OV0_PIPELINE_CNTL 0x0408 +#define OV0_EXCLUSIVE_HORZ 0x0408 +# define EXCL_HORZ_START_MASK 0x000000ff +# define EXCL_HORZ_END_MASK 0x0000ff00 +# define EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000 +# define EXCL_HORZ_EXCLUSIVE_EN 0x80000000 +#define OV0_EXCLUSIVE_VERT 0x040C +# define EXCL_VERT_START_MASK 0x000003ff +# define EXCL_VERT_END_MASK 0x03ff0000 +#define OV0_REG_LOAD_CNTL 0x0410 +# define REG_LD_CTL_LOCK 0x00000001L +# define REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002L +# define REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004L +# define REG_LD_CTL_LOCK_READBACK 0x00000008L +#define OV0_SCALE_CNTL 0x0420 +# define SCALER_PIX_EXPAND 0x00000001L +# define SCALER_Y2R_TEMP 0x00000002L +#ifdef RAGE128 +# define SCALER_HORZ_PICK_NEAREST 0x00000003L +# define SCALER_VERT_PICK_NEAREST 0x00000004L +#else +# define SCALER_HORZ_PICK_NEAREST 0x00000004L +# define SCALER_VERT_PICK_NEAREST 0x00000008L +#endif +# define SCALER_SIGNED_UV 0x00000010L +# define SCALER_GAMMA_SEL_MASK 0x00000060L +# define SCALER_GAMMA_SEL_BRIGHT 0x00000000L +# define SCALER_GAMMA_SEL_G22 0x00000020L +# define SCALER_GAMMA_SEL_G18 0x00000040L +# define SCALER_GAMMA_SEL_G14 0x00000060L +# define SCALER_COMCORE_SHIFT_UP_ONE 0x00000080L +# define SCALER_SURFAC_FORMAT 0x00000f00L +# define SCALER_SOURCE_UNK0 0x00000000L /* 2 bpp ??? */ +# define SCALER_SOURCE_UNK1 0x00000100L /* 4 bpp ??? */ +# define SCALER_SOURCE_UNK2 0x00000200L /* 8 bpp ??? */ +# define SCALER_SOURCE_15BPP 0x00000300L +# define SCALER_SOURCE_16BPP 0x00000400L +/*# define SCALER_SOURCE_24BPP 0x00000500L*/ +# define SCALER_SOURCE_32BPP 0x00000600L +# define SCALER_SOURCE_UNK3 0x00000700L /* 8BPP_RGB332 ??? */ +# define SCALER_SOURCE_UNK4 0x00000800L /* 8BPP_Y8 ??? */ +# define SCALER_SOURCE_YUV9 0x00000900L /* 8BPP_RGB8 */ +# define SCALER_SOURCE_YUV12 0x00000A00L +# define SCALER_SOURCE_VYUY422 0x00000B00L +# define SCALER_SOURCE_YVYU422 0x00000C00L +# define SCALER_SOURCE_UNK5 0x00000D00L /* ??? */ +# define SCALER_SOURCE_UNK6 0x00000E00L /* 32BPP_AYUV444 */ +# define SCALER_SOURCE_UNK7 0x00000F00L /* 16BPP_ARGB4444 */ +# define SCALER_ADAPTIVE_DEINT 0x00001000L +# define R200_SCALER_TEMPORAL_DEINT 0x00002000L +# define SCALER_UNKNOWN_FLAG1 0x00004000L /* ??? */ +# define SCALER_SMART_SWITCH 0x00008000L +#ifdef RAGE128 +# define SCALER_BURST_PER_PLANE 0x00ff0000L +#else +# define SCALER_BURST_PER_PLANE 0x007f0000L +#endif +# define SCALER_DOUBLE_BUFFER 0x01000000L +# define SCALER_UNKNOWN_FLAG3 0x02000000L /* ??? */ +# define SCALER_UNKNOWN_FLAG4 0x04000000L /* ??? */ +# define SCALER_DIS_LIMIT 0x08000000L +#ifdef RAGE128 +# define SCALER_PRG_LOAD_START 0x10000000L +#endif +# define SCALER_INT_EMU 0x20000000L +# define SCALER_ENABLE 0x40000000L +# define SCALER_SOFT_RESET 0x80000000L +#define OV0_V_INC 0x0424 +#define OV0_P1_V_ACCUM_INIT 0x0428 +# define OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003L +# define OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000L +#define OV0_P23_V_ACCUM_INIT 0x042C +# define OV0_P23_MAX_LN_IN_PER_LN_OUT 0x00000003L +# define OV0_P23_V_ACCUM_INIT_MASK 0x01ff8000L +#define OV0_P1_BLANK_LINES_AT_TOP 0x0430 +# define P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fffL +# define P1_ACTIVE_LINES_M1 0x0fff0000L +#define OV0_P23_BLANK_LINES_AT_TOP 0x0434 +# define P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ffL +# define P23_ACTIVE_LINES_M1 0x07ff0000L +#ifndef RAGE128 +#define OV0_BASE_ADDR 0x043C +#endif +#define OV0_VID_BUF0_BASE_ADRS 0x0440 +# define VIF_BUF0_PITCH_SEL 0x00000001L +# define VIF_BUF0_TILE_ADRS 0x00000002L +# define VIF_BUF0_BASE_ADRS_MASK 0x03fffff0L +# define VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF1_BASE_ADRS 0x0444 +# define VIF_BUF1_PITCH_SEL 0x00000001L +# define VIF_BUF1_TILE_ADRS 0x00000002L +# define VIF_BUF1_BASE_ADRS_MASK 0x03fffff0L +# define VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF2_BASE_ADRS 0x0448 +# define VIF_BUF2_PITCH_SEL 0x00000001L +# define VIF_BUF2_TILE_ADRS 0x00000002L +# define VIF_BUF2_BASE_ADRS_MASK 0x03fffff0L +# define VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF3_BASE_ADRS 0x044C +# define VIF_BUF3_PITCH_SEL 0x00000001L +# define VIF_BUF3_TILE_ADRS 0x00000002L +# define VIF_BUF3_BASE_ADRS_MASK 0x03fffff0L +# define VIF_BUF3_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF4_BASE_ADRS 0x0450 +# define VIF_BUF4_PITCH_SEL 0x00000001L +# define VIF_BUF4_TILE_ADRS 0x00000002L +# define VIF_BUF4_BASE_ADRS_MASK 0x03fffff0L +# define VIF_BUF4_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF5_BASE_ADRS 0x0454 +# define VIF_BUF5_PITCH_SEL 0x00000001L +# define VIF_BUF5_TILE_ADRS 0x00000002L +# define VIF_BUF5_BASE_ADRS_MASK 0x03fffff0L +# define VIF_BUF5_1ST_LINE_LSBS_MASK 0x48000000L +#define OV0_VID_BUF_PITCH0_VALUE 0x0460 +#define OV0_VID_BUF_PITCH1_VALUE 0x0464 +#define OV0_AUTO_FLIP_CNTL 0x0470 +# define OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x00000007 +# define OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x00000008 +# define OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x00000010 +# define OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020 +# define OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x00000040 +# define OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x00000300 +# define OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x00010000 +# define OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x00040000 +# define OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x00080000 +# define OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x00800000 +#define OV0_DEINTERLACE_PATTERN 0x0474 +#define OV0_SUBMIT_HISTORY 0x0478 +#define OV0_H_INC 0x0480 +#define OV0_STEP_BY 0x0484 +#define OV0_P1_H_ACCUM_INIT 0x0488 +#define OV0_P23_H_ACCUM_INIT 0x048C +#define OV0_P1_X_START_END 0x0494 +#define OV0_P2_X_START_END 0x0498 +#define OV0_P3_X_START_END 0x049C +#define OV0_FILTER_CNTL 0x04A0 +# define FILTER_PROGRAMMABLE_COEF 0x00000000 +# define FILTER_HARD_SCALE_HORZ_Y 0x00000001 +# define FILTER_HARD_SCALE_HORZ_UV 0x00000002 +# define FILTER_HARD_SCALE_VERT_Y 0x00000004 +# define FILTER_HARD_SCALE_VERT_UV 0x00000008 +# define FILTER_HARDCODED_COEF 0x0000000F +# define FILTER_COEF_MASK 0x0000000F +/* When bit is set hard coded coefficients are used. */ + +/* + Top quality 4x4-tap filtered vertical and horizontal scaler. + It allows up to 64:1 upscaling and downscaling without + performance or quality degradation. +*/ +#define OV0_FOUR_TAP_COEF_0 0x04B0 +# define OV0_FOUR_TAP_PHASE_0_TAP_0 0x0000000F +# define OV0_FOUR_TAP_PHASE_0_TAP_1 0x00007F00 +# define OV0_FOUR_TAP_PHASE_0_TAP_2 0x007F0000 +# define OV0_FOUR_TAP_PHASE_0_TAP_3 0x0F000000 +#define OV0_FOUR_TAP_COEF_1 0x04B4 +# define OV0_FOUR_TAP_PHASE_1_5_TAP_0 0x0000000F +# define OV0_FOUR_TAP_PHASE_1_5_TAP_1 0x00007F00 +# define OV0_FOUR_TAP_PHASE_1_5_TAP_2 0x007F0000 +# define OV0_FOUR_TAP_PHASE_1_5_TAP_3 0x0F000000 +#define OV0_FOUR_TAP_COEF_2 0x04B8 +# define OV0_FOUR_TAP_PHASE_2_6_TAP_0 0x0000000F +# define OV0_FOUR_TAP_PHASE_2_6_TAP_1 0x00007F00 +# define OV0_FOUR_TAP_PHASE_2_6_TAP_2 0x007F0000 +# define OV0_FOUR_TAP_PHASE_2_6_TAP_3 0x0F000000 +#define OV0_FOUR_TAP_COEF_3 0x04BC +# define OV0_FOUR_TAP_PHASE_3_7_TAP_0 0x0000000F +# define OV0_FOUR_TAP_PHASE_3_7_TAP_1 0x00007F00 +# define OV0_FOUR_TAP_PHASE_3_7_TAP_2 0x007F0000 +# define OV0_FOUR_TAP_PHASE_3_7_TAP_3 0x0F000000 +#define OV0_FOUR_TAP_COEF_4 0x04C0 +# define OV0_FOUR_TAP_PHASE_4_TAP_0 0x0000000F +# define OV0_FOUR_TAP_PHASE_4_TAP_1 0x00007F00 +# define OV0_FOUR_TAP_PHASE_4_TAP_2 0x007F0000 +# define OV0_FOUR_TAP_PHASE_4_TAP_3 0x0F000000 +/* 0th_tap means that the left most of top most pixel in a set of four will + be multiplied by this coefficient. */ + +#define OV0_FLAG_CNTL 0x04DC +#ifdef RAGE128 +#define OV0_COLOUR_CNTL 0x04E0 +# define COLOUR_CNTL_BRIGHTNESS 0x0000007F +# define COLOUR_CNTL_SATURATION 0x001F1F00 +#else +/* NB: radeons have no COLOUR_CNTL register */ +#define OV0_SLICE_CNTL 0x04E0 +# define SLICE_CNTL_DISABLE 0x40000000 +#endif +/* Video and graphics keys allow alpha blending, color correction + and many other video effects */ +#define OV0_VID_KEY_CLR 0x04E4 +#define OV0_VID_KEY_MSK 0x04E8 +#define OV0_GRAPHICS_KEY_CLR 0x04EC +#define OV0_GRAPHICS_KEY_MSK 0x04F0 +#define OV0_KEY_CNTL 0x04F4 +#ifdef RAGE128 +# define VIDEO_KEY_FN_MASK 0x00000007L +# define VIDEO_KEY_FN_FALSE 0x00000000L +# define VIDEO_KEY_FN_TRUE 0x00000001L +# define VIDEO_KEY_FN_EQ 0x00000004L +# define VIDEO_KEY_FN_NE 0x00000005L +# define GRAPHIC_KEY_FN_MASK 0x00000070L +# define GRAPHIC_KEY_FN_FALSE 0x00000000L +# define GRAPHIC_KEY_FN_TRUE 0x00000010L +# define GRAPHIC_KEY_FN_EQ 0x00000040L +# define GRAPHIC_KEY_FN_NE 0x00000050L +#else +# define VIDEO_KEY_FN_MASK 0x00000003L +# define VIDEO_KEY_FN_FALSE 0x00000000L +# define VIDEO_KEY_FN_TRUE 0x00000001L +# define VIDEO_KEY_FN_EQ 0x00000002L +# define VIDEO_KEY_FN_NE 0x00000003L +# define GRAPHIC_KEY_FN_MASK 0x00000030L +# define GRAPHIC_KEY_FN_FALSE 0x00000000L +# define GRAPHIC_KEY_FN_TRUE 0x00000010L +# define GRAPHIC_KEY_FN_EQ 0x00000020L +# define GRAPHIC_KEY_FN_NE 0x00000030L +#endif +# define CMP_MIX_MASK 0x00000100L +# define CMP_MIX_OR 0x00000000L +# define CMP_MIX_AND 0x00000100L +#define OV0_TEST 0x04F8 +#define OV0_LIN_TRANS_A 0x0D20 +#define OV0_LIN_TRANS_B 0x0D24 +#define OV0_LIN_TRANS_C 0x0D28 +#define OV0_LIN_TRANS_D 0x0D2C +#define OV0_LIN_TRANS_E 0x0D30 +#define OV0_LIN_TRANS_F 0x0D34 +#define OV0_GAMMA_0_F 0x0D40 +#define OV0_GAMMA_10_1F 0x0D44 +#define OV0_GAMMA_20_3F 0x0D48 +#define OV0_GAMMA_40_7F 0x0D4C +/* These registers exist on R200 only */ +#define OV0_GAMMA_80_BF 0x0E00 +#define OV0_GAMMA_C0_FF 0x0E04 +#define OV0_GAMMA_100_13F 0x0E08 +#define OV0_GAMMA_140_17F 0x0E0C +#define OV0_GAMMA_180_1BF 0x0E10 +#define OV0_GAMMA_1C0_1FF 0x0E14 +#define OV0_GAMMA_200_23F 0x0E18 +#define OV0_GAMMA_240_27F 0x0E1C +#define OV0_GAMMA_280_2BF 0x0E20 +#define OV0_GAMMA_2C0_2FF 0x0E24 +#define OV0_GAMMA_300_33F 0x0E28 +#define OV0_GAMMA_340_37F 0x0E2C +/* End of R200 specific definitions */ +#define OV0_GAMMA_380_3BF 0x0D50 +#define OV0_GAMMA_3C0_3FF 0x0D54 + +/* + IDCT ENGINE: + It's MPEG-2 hardware decoder which incorporates run-level decode, de-zigzag + and IDCT into an IDCT engine to complement the motion compensation engine. +*/ +#define IDCT_RUNS 0x1F80 +#define IDCT_LEVELS 0x1F84 +#define IDCT_AUTH_CONTROL 0x1F88 +#define IDCT_AUTH 0x1F8C +#define IDCT_CONTROL 0x1FBC + +#define SE_MC_SRC2_CNTL 0x19D4 +#define SE_MC_SRC1_CNTL 0x19D8 +#define SE_MC_DST_CNTL 0x19DC +#define SE_MC_CNTL_START 0x19E0 +#ifndef RAGE128 +#define SE_MC_BUF_BASE 0x19E4 +#define PP_MC_CONTEXT 0x19E8 +#define PP_MISC 0x1C14 +#endif +/* + SUBPICTURE UNIT: + Decompressing, scaling and alpha blending the compressed bitmap on the fly. + Provide optimal DVD subpicture qualtity. +*/ +#define SUBPIC_CNTL 0x0540 +#define SUBPIC_DEFCOLCON 0x0544 +#define SUBPIC_Y_X_START 0x054C +#define SUBPIC_Y_X_END 0x0550 +#define SUBPIC_V_INC 0x0554 +#define SUBPIC_H_INC 0x0558 +#define SUBPIC_BUF0_OFFSET 0x055C +#define SUBPIC_BUF1_OFFSET 0x0560 +#define SUBPIC_LC0_OFFSET 0x0564 +#define SUBPIC_LC1_OFFSET 0x0568 +#define SUBPIC_PITCH 0x056C +#define SUBPIC_BTN_HLI_COLCON 0x0570 +#define SUBPIC_BTN_HLI_Y_X_START 0x0574 +#define SUBPIC_BTN_HLI_Y_X_END 0x0578 +#define SUBPIC_PALETTE_INDEX 0x057C +#define SUBPIC_PALETTE_DATA 0x0580 +#define SUBPIC_H_ACCUM_INIT 0x0584 +#define SUBPIC_V_ACCUM_INIT 0x0588 + +#define CP_RB_BASE 0x0700 +#define CP_RB_CNTL 0x0704 +#define CP_RB_RPTR_ADDR 0x070C +#define CP_RB_RPTR 0x0710 +#define CP_RB_WPTR 0x0714 +#define CP_RB_WPTR_DELAY 0x0718 +#define CP_IB_BASE 0x0738 +#define CP_IB_BUFSZ 0x073C +#define CP_CSQ_CNTL 0x0740 +#define SCRATCH_UMSK 0x0770 +#define SCRATCH_ADDR 0x0774 +#define DMA_GUI_TABLE_ADDR 0x0780 +# define DMA_GUI_COMMAND__BYTE_COUNT_MASK 0x001fffff +# define DMA_GUI_COMMAND__INTDIS 0x40000000 +# define DMA_GUI_COMMAND__EOL 0x80000000 +#define DMA_GUI_SRC_ADDR 0x0784 +#define DMA_GUI_DST_ADDR 0x0788 +#define DMA_GUI_COMMAND 0x078C +#define DMA_GUI_STATUS 0x0790 +#define DMA_GUI_ACT_DSCRPTR 0x0794 +#define DMA_VID_TABLE_ADDR 0x07A0 +#define DMA_VID_SRC_ADDR 0x07A4 +#define DMA_VID_DST_ADDR 0x07A8 +#define DMA_VID_COMMAND 0x07AC +#define DMA_VID_STATUS 0x07B0 +#define DMA_VID_ACT_DSCRPTR 0x07B4 +#define CP_ME_CNTL 0x07D0 +#define CP_ME_RAM_ADDR 0x07D4 +#define CP_ME_RAM_RADDR 0x07D8 +#define CP_ME_RAM_DATAH 0x07DC +#define CP_ME_RAM_DATAL 0x07E0 +#define CP_CSQ_ADDR 0x07F0 +#define CP_CSQ_DATA 0x07F4 +#define CP_CSQ_STAT 0x07F8 + +#define DISP_MISC_CNTL 0x0D00 +# define SOFT_RESET_GRPH_PP (1 << 0) +#define DAC_MACRO_CNTL 0x0D04 +#define DISP_PWR_MAN 0x0D08 +#define DISP_TEST_DEBUG_CNTL 0x0D10 +#define DISP_HW_DEBUG 0x0D14 +#define DAC_CRC_SIG1 0x0D18 +#define DAC_CRC_SIG2 0x0D1C + +/* first capture unit */ + +#define VID_BUFFER_CONTROL 0x0900 +#define CAP_INT_CNTL 0x0908 +#define CAP_INT_STATUS 0x090C +#define FCP_CNTL 0x0910 +# define FCP_CNTL__PCICLK 0 +# define FCP_CNTL__PCLK 1 +# define FCP_CNTL__PCLKb 2 +# define FCP_CNTL__HREF 3 +# define FCP_CNTL__GND 4 +# define FCP_CNTL__HREFb 5 + +#define CAP0_BUF0_OFFSET 0x0920 +#define CAP0_BUF1_OFFSET 0x0924 +#define CAP0_BUF0_EVEN_OFFSET 0x0928 +#define CAP0_BUF1_EVEN_OFFSET 0x092C +#define CAP0_BUF_PITCH 0x0930 +#define CAP0_V_WINDOW 0x0934 +#define CAP0_H_WINDOW 0x0938 +#define CAP0_VBI0_OFFSET 0x093C +#define CAP0_VBI1_OFFSET 0x0940 +#define CAP0_VBI_V_WINDOW 0x0944 +#define CAP0_VBI_H_WINDOW 0x0948 +#define CAP0_PORT_MODE_CNTL 0x094C +#define CAP0_TRIG_CNTL 0x0950 +#define CAP0_DEBUG 0x0954 +#define CAP0_CONFIG 0x0958 +# define CAP0_CONFIG_CONTINUOS 0x00000001 +# define CAP0_CONFIG_START_FIELD_EVEN 0x00000002 +# define CAP0_CONFIG_START_BUF_GET 0x00000004 +# define CAP0_CONFIG_START_BUF_SET 0x00000008 +# define CAP0_CONFIG_BUF_TYPE_ALT 0x00000010 +# define CAP0_CONFIG_BUF_TYPE_FRAME 0x00000020 +# define CAP0_CONFIG_ONESHOT_MODE_FRAME 0x00000040 +# define CAP0_CONFIG_BUF_MODE_DOUBLE 0x00000080 +# define CAP0_CONFIG_BUF_MODE_TRIPLE 0x00000100 +# define CAP0_CONFIG_MIRROR_EN 0x00000200 +# define CAP0_CONFIG_ONESHOT_MIRROR_EN 0x00000400 +# define CAP0_CONFIG_VIDEO_SIGNED_UV 0x00000800 +# define CAP0_CONFIG_ANC_DECODE_EN 0x00001000 +# define CAP0_CONFIG_VBI_EN 0x00002000 +# define CAP0_CONFIG_SOFT_PULL_DOWN_EN 0x00004000 +# define CAP0_CONFIG_VIP_EXTEND_FLAG_EN 0x00008000 +# define CAP0_CONFIG_FAKE_FIELD_EN 0x00010000 +# define CAP0_CONFIG_ODD_ONE_MORE_LINE 0x00020000 +# define CAP0_CONFIG_EVEN_ONE_MORE_LINE 0x00040000 +# define CAP0_CONFIG_HORZ_DIVIDE_2 0x00080000 +# define CAP0_CONFIG_HORZ_DIVIDE_4 0x00100000 +# define CAP0_CONFIG_VERT_DIVIDE_2 0x00200000 +# define CAP0_CONFIG_VERT_DIVIDE_4 0x00400000 +# define CAP0_CONFIG_FORMAT_BROOKTREE 0x00000000 +# define CAP0_CONFIG_FORMAT_CCIR656 0x00800000 +# define CAP0_CONFIG_FORMAT_ZV 0x01000000 +# define CAP0_CONFIG_FORMAT_VIP 0x01800000 +# define CAP0_CONFIG_FORMAT_TRANSPORT 0x02000000 +# define CAP0_CONFIG_HORZ_DECIMATOR 0x04000000 +# define CAP0_CONFIG_VIDEO_IN_YVYU422 0x00000000 +# define CAP0_CONFIG_VIDEO_IN_VYUY422 0x20000000 +# define CAP0_CONFIG_VBI_DIVIDE_2 0x40000000 +# define CAP0_CONFIG_VBI_DIVIDE_4 0x80000000 +#define CAP0_ANC_ODD_OFFSET 0x095C +#define CAP0_ANC_EVEN_OFFSET 0x0960 +#define CAP0_ANC_H_WINDOW 0x0964 +#define CAP0_VIDEO_SYNC_TEST 0x0968 +#define CAP0_ONESHOT_BUF_OFFSET 0x096C +#define CAP0_BUF_STATUS 0x0970 +#ifdef RAGE128 +#define CAP0_DWNSC_XRATIO 0x0978 +#define CAP0_XSHARPNESS 0x097C +#else +/* #define CAP0_DWNSC_XRATIO 0x0978 */ +/* #define CAP0_XSHARPNESS 0x097C */ +#endif +#define CAP0_VBI2_OFFSET 0x0980 +#define CAP0_VBI3_OFFSET 0x0984 +#define CAP0_ANC2_OFFSET 0x0988 +#define CAP0_ANC3_OFFSET 0x098C + +/* second capture unit */ + +#define CAP1_BUF0_OFFSET 0x0990 +#define CAP1_BUF1_OFFSET 0x0994 +#define CAP1_BUF0_EVEN_OFFSET 0x0998 +#define CAP1_BUF1_EVEN_OFFSET 0x099C + +#define CAP1_BUF_PITCH 0x09A0 +#define CAP1_V_WINDOW 0x09A4 +#define CAP1_H_WINDOW 0x09A8 +#define CAP1_VBI_ODD_OFFSET 0x09AC +#define CAP1_VBI_EVEN_OFFSET 0x09B0 +#define CAP1_VBI_V_WINDOW 0x09B4 +#define CAP1_VBI_H_WINDOW 0x09B8 +#define CAP1_PORT_MODE_CNTL 0x09BC +#define CAP1_TRIG_CNTL 0x09C0 +#define CAP1_DEBUG 0x09C4 +#define CAP1_CONFIG 0x09C8 +#define CAP1_ANC_ODD_OFFSET 0x09CC +#define CAP1_ANC_EVEN_OFFSET 0x09D0 +#define CAP1_ANC_H_WINDOW 0x09D4 +#define CAP1_VIDEO_SYNC_TEST 0x09D8 +#define CAP1_ONESHOT_BUF_OFFSET 0x09DC +#define CAP1_BUF_STATUS 0x09E0 +#define CAP1_DWNSC_XRATIO 0x09E8 +#define CAP1_XSHARPNESS 0x09EC + +#define DISP_MERGE_CNTL 0x0D60 +#define DISP_OUTPUT_CNTL 0x0D64 +# define DISP_DAC_SOURCE_MASK 0x03 +# define DISP_DAC_SOURCE_CRTC2 0x01 +#define DISP_LIN_TRANS_GRPH_A 0x0D80 +#define DISP_LIN_TRANS_GRPH_B 0x0D84 +#define DISP_LIN_TRANS_GRPH_C 0x0D88 +#define DISP_LIN_TRANS_GRPH_D 0x0D8C +#define DISP_LIN_TRANS_GRPH_E 0x0D90 +#define DISP_LIN_TRANS_GRPH_F 0x0D94 +#define DISP_LIN_TRANS_VID_A 0x0D98 +#define DISP_LIN_TRANS_VID_B 0x0D9C +#define DISP_LIN_TRANS_VID_C 0x0DA0 +#define DISP_LIN_TRANS_VID_D 0x0DA4 +#define DISP_LIN_TRANS_VID_E 0x0DA8 +#define DISP_LIN_TRANS_VID_F 0x0DAC +#define RMX_HORZ_FILTER_0TAP_COEF 0x0DB0 +#define RMX_HORZ_FILTER_1TAP_COEF 0x0DB4 +#define RMX_HORZ_FILTER_2TAP_COEF 0x0DB8 +#define RMX_HORZ_PHASE 0x0DBC +#define DAC_EMBEDDED_SYNC_CNTL 0x0DC0 +#define DAC_BROAD_PULSE 0x0DC4 +#define DAC_SKEW_CLKS 0x0DC8 +#define DAC_INCR 0x0DCC +#define DAC_NEG_SYNC_LEVEL 0x0DD0 +#define DAC_POS_SYNC_LEVEL 0x0DD4 +#define DAC_BLANK_LEVEL 0x0DD8 +#define CLOCK_CNTL_INDEX 0x0008 +/* CLOCK_CNTL_INDEX bit constants */ +# define PLL_WR_EN 0x00000080 +# define PLL_DIV_SEL (3 << 8) +# define PLL2_DIV_SEL_MASK ~(3 << 8) +#define CLOCK_CNTL_DATA 0x000C +#define CP_RB_CNTL 0x0704 +#define CP_RB_BASE 0x0700 +#define CP_RB_RPTR_ADDR 0x070C +#define CP_RB_RPTR 0x0710 +#define CP_RB_WPTR 0x0714 +#define CP_RB_WPTR_DELAY 0x0718 +#define CP_IB_BASE 0x0738 +#define CP_IB_BUFSZ 0x073C +#define SCRATCH_REG0 0x15E0 +#define GUI_SCRATCH_REG0 0x15E0 +#define SCRATCH_REG1 0x15E4 +#define GUI_SCRATCH_REG1 0x15E4 +#define SCRATCH_REG2 0x15E8 +#define GUI_SCRATCH_REG2 0x15E8 +#define SCRATCH_REG3 0x15EC +#define GUI_SCRATCH_REG3 0x15EC +#define SCRATCH_REG4 0x15F0 +#define GUI_SCRATCH_REG4 0x15F0 +#define SCRATCH_REG5 0x15F4 +#define GUI_SCRATCH_REG5 0x15F4 +#define SCRATCH_UMSK 0x0770 +#define SCRATCH_ADDR 0x0774 +#define DP_BRUSH_FRGD_CLR 0x147C +#define DP_BRUSH_BKGD_CLR 0x1478 +#define DST_LINE_START 0x1600 +#define DST_LINE_END 0x1604 +#define SRC_OFFSET 0x15AC +#define SRC_PITCH 0x15B0 +#define SRC_TILE 0x1704 +#define SRC_PITCH_OFFSET 0x1428 +#define SRC_X 0x1414 +#define SRC_Y 0x1418 +#define DST_WIDTH_X 0x1588 +#define DST_HEIGHT_WIDTH_8 0x158C +#define SRC_X_Y 0x1590 +#define SRC_Y_X 0x1434 +#define DST_Y_X 0x1438 +#define DST_WIDTH_HEIGHT 0x1598 +#define DST_HEIGHT_WIDTH 0x143c +#ifdef RAGE128 +#define GUI_STAT 0x1740 +# define GUI_FIFOCNT_MASK 0x0fff +# define GUI_ACTIVE (1 << 31) +#endif +#define SRC_CLUT_ADDRESS 0x1780 +#define SRC_CLUT_DATA 0x1784 +#define SRC_CLUT_DATA_RD 0x1788 +#define HOST_DATA0 0x17C0 +#define HOST_DATA1 0x17C4 +#define HOST_DATA2 0x17C8 +#define HOST_DATA3 0x17CC +#define HOST_DATA4 0x17D0 +#define HOST_DATA5 0x17D4 +#define HOST_DATA6 0x17D8 +#define HOST_DATA7 0x17DC +#define HOST_DATA_LAST 0x17E0 +#define DP_SRC_ENDIAN 0x15D4 +#define DP_SRC_FRGD_CLR 0x15D8 +#define DP_SRC_BKGD_CLR 0x15DC +#define DP_WRITE_MASK 0x16cc +#define SC_LEFT 0x1640 +#define SC_RIGHT 0x1644 +#define SC_TOP 0x1648 +#define SC_BOTTOM 0x164C +#define SRC_SC_RIGHT 0x1654 +#define SRC_SC_BOTTOM 0x165C +#define DP_CNTL 0x16C0 +/* DP_CNTL bit constants */ +# define DST_X_RIGHT_TO_LEFT 0x00000000 +# define DST_X_LEFT_TO_RIGHT 0x00000001 +# define DST_Y_BOTTOM_TO_TOP 0x00000000 +# define DST_Y_TOP_TO_BOTTOM 0x00000002 +# define DST_X_MAJOR 0x00000000 +# define DST_Y_MAJOR 0x00000004 +# define DST_X_TILE 0x00000008 +# define DST_Y_TILE 0x00000010 +# define DST_LAST_PEL 0x00000020 +# define DST_TRAIL_X_RIGHT_TO_LEFT 0x00000000 +# define DST_TRAIL_X_LEFT_TO_RIGHT 0x00000040 +# define DST_TRAP_FILL_RIGHT_TO_LEFT 0x00000000 +# define DST_TRAP_FILL_LEFT_TO_RIGHT 0x00000080 +# define DST_BRES_SIGN 0x00000100 +# define DST_HOST_BIG_ENDIAN_EN 0x00000200 +# define DST_POLYLINE_NONLAST 0x00008000 +# define DST_RASTER_STALL 0x00010000 +# define DST_POLY_EDGE 0x00040000 +#define DP_CNTL_XDIR_YDIR_YMAJOR 0x16D0 +/* DP_CNTL_XDIR_YDIR_YMAJOR bit constants (short version of DP_CNTL) */ +# define DST_X_MAJOR_S 0x00000000 +# define DST_Y_MAJOR_S 0x00000001 +# define DST_Y_BOTTOM_TO_TOP_S 0x00000000 +# define DST_Y_TOP_TO_BOTTOM_S 0x00008000 +# define DST_X_RIGHT_TO_LEFT_S 0x00000000 +# define DST_X_LEFT_TO_RIGHT_S 0x80000000 +#define DP_DATATYPE 0x16C4 +/* DP_DATATYPE bit constants */ +# define DST_8BPP 0x00000002 +# define DST_15BPP 0x00000003 +# define DST_16BPP 0x00000004 +# define DST_24BPP 0x00000005 +# define DST_32BPP 0x00000006 +# define DST_8BPP_RGB332 0x00000007 +# define DST_8BPP_Y8 0x00000008 +# define DST_8BPP_RGB8 0x00000009 +# define DST_16BPP_VYUY422 0x0000000b +# define DST_16BPP_YVYU422 0x0000000c +# define DST_32BPP_AYUV444 0x0000000e +# define DST_16BPP_ARGB4444 0x0000000f +# define BRUSH_SOLIDCOLOR 0x00000d00 +# define SRC_MONO 0x00000000 +# define SRC_MONO_LBKGD 0x00010000 +# define SRC_DSTCOLOR 0x00030000 +# define BYTE_ORDER_MSB_TO_LSB 0x00000000 +# define BYTE_ORDER_LSB_TO_MSB 0x40000000 +# define DP_CONVERSION_TEMP 0x80000000 +# define HOST_BIG_ENDIAN_EN (1 << 29) +#define DP_MIX 0x16C8 +/* DP_MIX bit constants */ +# define DP_SRC_RECT 0x00000200 +# define DP_SRC_HOST 0x00000300 +# define DP_SRC_HOST_BYTEALIGN 0x00000400 +#define DP_WRITE_MSK 0x16CC +#define DP_XOP 0x17F8 +#define CLR_CMP_CLR_SRC 0x15C4 +#define CLR_CMP_CLR_DST 0x15C8 +#define CLR_CMP_CNTL 0x15C0 +/* CLR_CMP_CNTL bit constants */ +# define COMPARE_SRC_FALSE 0x00000000 +# define COMPARE_SRC_TRUE 0x00000001 +# define COMPARE_SRC_NOT_EQUAL 0x00000004 +# define COMPARE_SRC_EQUAL 0x00000005 +# define COMPARE_SRC_EQUAL_FLIP 0x00000007 +# define COMPARE_DST_FALSE 0x00000000 +# define COMPARE_DST_TRUE 0x00000100 +# define COMPARE_DST_NOT_EQUAL 0x00000400 +# define COMPARE_DST_EQUAL 0x00000500 +# define COMPARE_DESTINATION 0x00000000 +# define COMPARE_SOURCE 0x01000000 +# define COMPARE_SRC_AND_DST 0x02000000 +#define CLR_CMP_MSK 0x15CC +#define DSTCACHE_MODE 0x1710 +#define DSTCACHE_CTLSTAT 0x1714 +/* DSTCACHE_CTLSTAT bit constants */ +# define RB2D_DC_FLUSH (3 << 0) +# define RB2D_DC_FLUSH_ALL 0xf +# define RB2D_DC_BUSY (1 << 31) +#define DEFAULT_OFFSET 0x16e0 +#define DEFAULT_PITCH_OFFSET 0x16E0 +#define DEFAULT_SC_BOTTOM_RIGHT 0x16E8 +/* DEFAULT_SC_BOTTOM_RIGHT bit constants */ +# define DEFAULT_SC_RIGHT_MAX (0x1fff << 0) +# define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) +#define DP_GUI_MASTER_CNTL 0x146C +/* DP_GUI_MASTER_CNTL bit constants */ +# define GMC_SRC_PITCH_OFFSET_DEFAULT 0x00000000 +# define GMC_SRC_PITCH_OFFSET_LEAVE 0x00000001 +# define GMC_DST_PITCH_OFFSET_DEFAULT 0x00000000 +# define GMC_DST_PITCH_OFFSET_LEAVE 0x00000002 +# define GMC_SRC_CLIP_DEFAULT 0x00000000 +# define GMC_SRC_CLIP_LEAVE 0x00000004 +# define GMC_DST_CLIP_DEFAULT 0x00000000 +# define GMC_DST_CLIP_LEAVE 0x00000008 +# define GMC_BRUSH_8x8MONO 0x00000000 +# define GMC_BRUSH_8x8MONO_LBKGD 0x00000010 +# define GMC_BRUSH_8x1MONO 0x00000020 +# define GMC_BRUSH_8x1MONO_LBKGD 0x00000030 +# define GMC_BRUSH_1x8MONO 0x00000040 +# define GMC_BRUSH_1x8MONO_LBKGD 0x00000050 +# define GMC_BRUSH_32x1MONO 0x00000060 +# define GMC_BRUSH_32x1MONO_LBKGD 0x00000070 +# define GMC_BRUSH_32x32MONO 0x00000080 +# define GMC_BRUSH_32x32MONO_LBKGD 0x00000090 +# define GMC_BRUSH_8x8COLOR 0x000000a0 +# define GMC_BRUSH_8x1COLOR 0x000000b0 +# define GMC_BRUSH_1x8COLOR 0x000000c0 +# define GMC_BRUSH_SOLID_COLOR 0x000000d0 +# define GMC_DST_8BPP 0x00000200 +# define GMC_DST_15BPP 0x00000300 +# define GMC_DST_16BPP 0x00000400 +# define GMC_DST_24BPP 0x00000500 +# define GMC_DST_32BPP 0x00000600 +# define GMC_DST_8BPP_RGB332 0x00000700 +# define GMC_DST_8BPP_Y8 0x00000800 +# define GMC_DST_8BPP_RGB8 0x00000900 +# define GMC_DST_16BPP_VYUY422 0x00000b00 +# define GMC_DST_16BPP_YVYU422 0x00000c00 +# define GMC_DST_32BPP_AYUV444 0x00000e00 +# define GMC_DST_16BPP_ARGB4444 0x00000f00 +# define GMC_SRC_MONO 0x00000000 +# define GMC_SRC_MONO_LBKGD 0x00001000 +# define GMC_SRC_DSTCOLOR 0x00003000 +# define GMC_BYTE_ORDER_MSB_TO_LSB 0x00000000 +# define GMC_BYTE_ORDER_LSB_TO_MSB 0x00004000 +# define GMC_DP_CONVERSION_TEMP_9300 0x00008000 +# define GMC_DP_CONVERSION_TEMP_6500 0x00000000 +# define GMC_DP_SRC_RECT 0x02000000 +# define GMC_DP_SRC_HOST 0x03000000 +# define GMC_DP_SRC_HOST_BYTEALIGN 0x04000000 +# define GMC_3D_FCN_EN_CLR 0x00000000 +# define GMC_3D_FCN_EN_SET 0x08000000 +# define GMC_DST_CLR_CMP_FCN_LEAVE 0x00000000 +# define GMC_DST_CLR_CMP_FCN_CLEAR 0x10000000 +# define GMC_AUX_CLIP_LEAVE 0x00000000 +# define GMC_AUX_CLIP_CLEAR 0x20000000 +# define GMC_WRITE_MASK_LEAVE 0x00000000 +# define GMC_WRITE_MASK_SET 0x40000000 +# define GMC_CLR_CMP_CNTL_DIS (1 << 28) +# define GMC_SRC_DATATYPE_COLOR (3 << 12) +# define ROP3_S 0x00cc0000 +# define ROP3_SRCCOPY 0x00cc0000 +# define ROP3_P 0x00f00000 +# define ROP3_PATCOPY 0x00f00000 +# define DP_SRC_SOURCE_MASK (7 << 24) +# define GMC_BRUSH_NONE (15 << 4) +# define DP_SRC_SOURCE_MEMORY (2 << 24) +# define GMC_BRUSH_SOLIDCOLOR 0x000000d0 +#define SC_TOP_LEFT 0x16EC +#define SC_BOTTOM_RIGHT 0x16F0 +#define SRC_SC_BOTTOM_RIGHT 0x16F4 +#define RB2D_DSTCACHE_CTLSTAT 0x342C +#define RB2D_DSTCACHE_MODE 0x3428 + +#define BASE_CODE 0x0f0b +#define RADEON_BIOS_0_SCRATCH 0x0010 +#define RADEON_BIOS_1_SCRATCH 0x0014 +#define RADEON_BIOS_2_SCRATCH 0x0018 +#define RADEON_BIOS_3_SCRATCH 0x001c +#define RADEON_BIOS_4_SCRATCH 0x0020 +#define RADEON_BIOS_5_SCRATCH 0x0024 +#define RADEON_BIOS_6_SCRATCH 0x0028 +#define RADEON_BIOS_7_SCRATCH 0x002c + + +#define CLK_PIN_CNTL 0x0001 +#define PPLL_CNTL 0x0002 +# define PPLL_RESET (1 << 0) +# define PPLL_SLEEP (1 << 1) +# define PPLL_ATOMIC_UPDATE_EN (1 << 16) +# define PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17) +# define PPLL_ATOMIC_UPDATE_VSYNC (1 << 18) +#define PPLL_REF_DIV 0x0003 +# define PPLL_REF_DIV_MASK 0x03ff +# define PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ +# define PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ +#define PPLL_DIV_0 0x0004 +#define PPLL_DIV_1 0x0005 +#define PPLL_DIV_2 0x0006 +#define PPLL_DIV_3 0x0007 +#define VCLK_ECP_CNTL 0x0008 +# define VCLK_SRC_SEL_MASK 0x03 +# define VCLK_SRC_SEL_CPUCLK 0x00 +# define VCLK_SRC_SEL_PSCANCLK 0x01 +# define VCLK_SRC_SEL_BYTECLK 0x02 +# define VCLK_SRC_SEL_PPLLCLK 0x03 +#define HTOTAL_CNTL 0x0009 +#define HTOTAL2_CNTL 0x002e /* PLL */ +#define M_SPLL_REF_FB_DIV 0x000a +#define AGP_PLL_CNTL 0x000b +#define SPLL_CNTL 0x000c +#define SCLK_CNTL 0x000d +# define DYN_STOP_LAT_MASK 0x00007ff8 +# define CP_MAX_DYN_STOP_LAT 0x0008 +# define SCLK_FORCEON_MASK 0xffff8000 +#define SCLK_MORE_CNTL 0x0035 /* PLL */ +# define SCLK_MORE_FORCEON 0x0700 +#define MPLL_CNTL 0x000e +#ifdef RAGE128 +#define MCLK_CNTL 0x000f /* PLL */ +# define FORCE_GCP (1 << 16) +# define FORCE_PIPE3D_CP (1 << 17) +# define FORCE_RCP (1 << 18) +#else +#define MCLK_CNTL 0x0012 +/* MCLK_CNTL bit constants */ +# define FORCEON_MCLKA (1 << 16) +# define FORCEON_MCLKB (1 << 17) +# define FORCEON_YCLKA (1 << 18) +# define FORCEON_YCLKB (1 << 19) +# define FORCEON_MC (1 << 20) +# define FORCEON_AIC (1 << 21) +#endif +#define PLL_TEST_CNTL 0x0013 +#define P2PLL_CNTL 0x002a /* P2PLL */ +# define P2PLL_RESET (1 << 0) +# define P2PLL_SLEEP (1 << 1) +# define P2PLL_ATOMIC_UPDATE_EN (1 << 16) +# define P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17) +# define P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18) +#define P2PLL_DIV_0 0x002c +# define P2PLL_FB0_DIV_MASK 0x07ff +# define P2PLL_POST0_DIV_MASK 0x00070000 +#define P2PLL_REF_DIV 0x002B /* PLL */ +# define P2PLL_REF_DIV_MASK 0x03ff +# define P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ +# define P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ +#define PIXCLKS_CNTL 0x002d +# define PIX2CLK_SRC_SEL_MASK 0x03 +# define PIX2CLK_SRC_SEL_CPUCLK 0x00 +# define PIX2CLK_SRC_SEL_PSCANCLK 0x01 +# define PIX2CLK_SRC_SEL_BYTECLK 0x02 +# define PIX2CLK_SRC_SEL_P2PLLCLK 0x03 + +/* masks */ + +#define CONFIG_MEMSIZE_MASK 0x1f000000 +#define MEM_CFG_TYPE 0x40000000 +#define DST_OFFSET_MASK 0x003fffff +#define DST_PITCH_MASK 0x3fc00000 +#define DEFAULT_TILE_MASK 0xc0000000 +#define PPLL_DIV_SEL_MASK 0x00000300 +#define PPLL_FB3_DIV_MASK 0x000007ff +#define PPLL_POST3_DIV_MASK 0x00070000 + +/* BUS MASTERING */ +#define BM_FRAME_BUF_OFFSET 0xA00 +#define BM_SYSTEM_MEM_ADDR 0xA04 +#define BM_COMMAND 0xA08 +# define BM_INTERRUPT_DIS 0x08000000 +# define BM_TRANSFER_DEST_REG 0x10000000 +# define BM_FORCE_TO_PCI 0x20000000 +# define BM_FRAME_OFFSET_HOLD 0x40000000 +# define BM_END_OF_LIST 0x80000000 +#define BM_STATUS 0xA0c +#define BM_QUEUE_STATUS 0xA10 +#define BM_QUEUE_FREE_STATUS 0xA14 +#define BM_CHUNK_0_VAL 0xA18 +# define BM_PTR_FORCE_TO_PCI 0x00200000 +# define BM_PM4_RD_FORCE_TO_PCI 0x00400000 +# define BM_GLOBAL_FORCE_TO_PCI 0x00800000 +# define BM_VIP3_NOCHUNK 0x10000000 +# define BM_VIP2_NOCHUNK 0x20000000 +# define BM_VIP1_NOCHUNK 0x40000000 +# define BM_VIP0_NOCHUNK 0x80000000 +#define BM_CHUNK_1_VAL 0xA1C +#define BM_VIP0_BUF 0xA20 +# define SYSTEM_TRIGGER_SYSTEM_TO_VIDEO 0x0 +# define SYSTEM_TRIGGER_VIDEO_TO_SYSTEM 0x1 +#define BM_VIP0_ACTIVE 0xA24 +#define BM_VIP1_BUF 0xA30 +#define BM_VIP1_ACTIVE 0xA34 +#define BM_VIP2_BUF 0xA40 +#define BM_VIP2_ACTIVE 0xA44 +#define BM_VIP3_BUF 0xA50 +#define BM_VIP3_ACTIVE 0xA54 +#define BM_VIDCAP_BUF0 0xA60 +#define BM_VIDCAP_BUF1 0xA64 +#define BM_VIDCAP_BUF2 0xA68 +#define BM_VIDCAP_ACTIVE 0xA6c +#define BM_GUI 0xA80 + +/* RAGE THEATER REGISTERS */ + +#define DMA_VIPH0_COMMAND 0x0A00 +#define DMA_VIPH1_COMMAND 0x0A04 +#define DMA_VIPH2_COMMAND 0x0A08 +#define DMA_VIPH3_COMMAND 0x0A0C +#define DMA_VIPH_STATUS 0x0A10 +#define DMA_VIPH_CHUNK_0 0x0A18 +#define DMA_VIPH_CHUNK_1_VAL 0x0A1C +#define DMA_VIP0_TABLE_ADDR 0x0A20 +#define DMA_VIPH0_ACTIVE 0x0A24 +#define DMA_VIP1_TABLE_ADDR 0x0A30 +#define DMA_VIPH1_ACTIVE 0x0A34 +#define DMA_VIP2_TABLE_ADDR 0x0A40 +#define DMA_VIPH2_ACTIVE 0x0A44 +#define DMA_VIP3_TABLE_ADDR 0x0A50 +#define DMA_VIPH3_ACTIVE 0x0A54 +#define DMA_VIPH_ABORT 0x0A88 + +#define VIPH_CH0_DATA 0x0c00 +#define VIPH_CH1_DATA 0x0c04 +#define VIPH_CH2_DATA 0x0c08 +#define VIPH_CH3_DATA 0x0c0c +#define VIPH_CH0_ADDR 0x0c10 +#define VIPH_CH1_ADDR 0x0c14 +#define VIPH_CH2_ADDR 0x0c18 +#define VIPH_CH3_ADDR 0x0c1c +#define VIPH_CH0_SBCNT 0x0c20 +#define VIPH_CH1_SBCNT 0x0c24 +#define VIPH_CH2_SBCNT 0x0c28 +#define VIPH_CH3_SBCNT 0x0c2c +#define VIPH_CH0_ABCNT 0x0c30 +#define VIPH_CH1_ABCNT 0x0c34 +#define VIPH_CH2_ABCNT 0x0c38 +#define VIPH_CH3_ABCNT 0x0c3c +#define VIPH_CONTROL 0x0c40 +#define VIPH_DV_LAT 0x0c44 +#define VIPH_BM_CHUNK 0x0c48 +#define VIPH_DV_INT 0x0c4c +#define VIPH_TIMEOUT_STAT 0x0c50 + +#define VIPH_REG_DATA 0x0084 +#define VIPH_REG_ADDR 0x0080 + +/* Address Space Rage Theatre Registers (VIP Access) */ +#define VIP_VIP_VENDOR_DEVICE_ID 0x0000 +#define VIP_VIP_SUB_VENDOR_DEVICE_ID 0x0004 +#define VIP_VIP_COMMAND_STATUS 0x0008 +#define VIP_VIP_REVISION_ID 0x000c +#define VIP_HW_DEBUG 0x0010 +#define VIP_SW_SCRATCH 0x0014 +#define VIP_I2C_CNTL_0 0x0020 +#define VIP_I2C_CNTL_1 0x0024 +#define VIP_I2C_DATA 0x0028 +#define VIP_INT_CNTL 0x002c +#define VIP_GPIO_INOUT 0x0030 +#define VIP_GPIO_CNTL 0x0034 +#define VIP_CLKOUT_GPIO_CNTL 0x0038 +#define VIP_RIPINTF_PORT_CNTL 0x003c +#define VIP_ADC_CNTL 0x0400 +#define VIP_ADC_DEBUG 0x0404 +#define VIP_STANDARD_SELECT 0x0408 +#define VIP_THERMO2BIN_STATUS 0x040c +#define VIP_COMB_CNTL0 0x0440 +#define VIP_COMB_CNTL1 0x0444 +#define VIP_COMB_CNTL2 0x0448 +#define VIP_COMB_LINE_LENGTH 0x044c +#define VIP_NOISE_CNTL0 0x0450 +#define VIP_HS_PLINE 0x0480 +#define VIP_HS_DTOINC 0x0484 +#define VIP_HS_PLLGAIN 0x0488 +#define VIP_HS_MINMAXWIDTH 0x048c +#define VIP_HS_GENLOCKDELAY 0x0490 +#define VIP_HS_WINDOW_LIMIT 0x0494 +#define VIP_HS_WINDOW_OC_SPEED 0x0498 +#define VIP_HS_PULSE_WIDTH 0x049c +#define VIP_HS_PLL_ERROR 0x04a0 +#define VIP_HS_PLL_FS_PATH 0x04a4 +#define VIP_SG_BLACK_GATE 0x04c0 +#define VIP_SG_SYNCTIP_GATE 0x04c4 +#define VIP_SG_UVGATE_GATE 0x04c8 +#define VIP_LP_AGC_CLAMP_CNTL0 0x0500 +#define VIP_LP_AGC_CLAMP_CNTL1 0x0504 +#define VIP_LP_BRIGHTNESS 0x0508 +#define VIP_LP_CONTRAST 0x050c +#define VIP_LP_SLICE_LIMIT 0x0510 +#define VIP_LP_WPA_CNTL0 0x0514 +#define VIP_LP_WPA_CNTL1 0x0518 +#define VIP_LP_BLACK_LEVEL 0x051c +#define VIP_LP_SLICE_LEVEL 0x0520 +#define VIP_LP_SYNCTIP_LEVEL 0x0524 +#define VIP_LP_VERT_LOCKOUT 0x0528 +#define VIP_VS_DETECTOR_CNTL 0x0540 +#define VIP_VS_BLANKING_CNTL 0x0544 +#define VIP_VS_FIELD_ID_CNTL 0x0548 +#define VIP_VS_COUNTER_CNTL 0x054c +#define VIP_VS_FRAME_TOTAL 0x0550 +#define VIP_VS_LINE_COUNT 0x0554 +#define VIP_CP_PLL_CNTL0 0x0580 +#define VIP_CP_PLL_CNTL1 0x0584 +#define VIP_CP_HUE_CNTL 0x0588 +#define VIP_CP_BURST_GAIN 0x058c +#define VIP_CP_AGC_CNTL 0x0590 +#define VIP_CP_ACTIVE_GAIN 0x0594 +#define VIP_CP_PLL_STATUS0 0x0598 +#define VIP_CP_PLL_STATUS1 0x059c +#define VIP_CP_PLL_STATUS2 0x05a0 +#define VIP_CP_PLL_STATUS3 0x05a4 +#define VIP_CP_PLL_STATUS4 0x05a8 +#define VIP_CP_PLL_STATUS5 0x05ac +#define VIP_CP_PLL_STATUS6 0x05b0 +#define VIP_CP_PLL_STATUS7 0x05b4 +#define VIP_CP_DEBUG_FORCE 0x05b8 +#define VIP_CP_VERT_LOCKOUT 0x05bc +#define VIP_H_ACTIVE_WINDOW 0x05c0 +#define VIP_V_ACTIVE_WINDOW 0x05c4 +#define VIP_H_VBI_WINDOW 0x05c8 +#define VIP_V_VBI_WINDOW 0x05cc +#define VIP_VBI_CONTROL 0x05d0 +#define VIP_DECODER_DEBUG_CNTL 0x05d4 +#define VIP_SINGLE_STEP_DATA 0x05d8 +#define VIP_MASTER_CNTL 0x0040 +#define VIP_RGB_CNTL 0x0048 +#define VIP_CLKOUT_CNTL 0x004c +#define VIP_SYNC_CNTL 0x0050 +#define VIP_I2C_CNTL 0x0054 +#define VIP_HTOTAL 0x0080 +#define VIP_HDISP 0x0084 +#define VIP_HSIZE 0x0088 +#define VIP_HSTART 0x008c +#define VIP_HCOUNT 0x0090 +#define VIP_VTOTAL 0x0094 +#define VIP_VDISP 0x0098 +#define VIP_VCOUNT 0x009c +#define VIP_VFTOTAL 0x00a0 +#define VIP_DFCOUNT 0x00a4 +#define VIP_DFRESTART 0x00a8 +#define VIP_DHRESTART 0x00ac +#define VIP_DVRESTART 0x00b0 +#define VIP_SYNC_SIZE 0x00b4 +#define VIP_TV_PLL_FINE_CNTL 0x00b8 +#define VIP_CRT_PLL_FINE_CNTL 0x00bc +#define VIP_TV_PLL_CNTL 0x00c0 +#define VIP_CRT_PLL_CNTL 0x00c4 +#define VIP_PLL_CNTL0 0x00c8 +#define VIP_PLL_TEST_CNTL 0x00cc +#define VIP_CLOCK_SEL_CNTL 0x00d0 +#define VIP_VIN_PLL_CNTL 0x00d4 +#define VIP_VIN_PLL_FINE_CNTL 0x00d8 +#define VIP_AUD_PLL_CNTL 0x00e0 +#define VIP_AUD_PLL_FINE_CNTL 0x00e4 +#define VIP_AUD_CLK_DIVIDERS 0x00e8 +#define VIP_AUD_DTO_INCREMENTS 0x00ec +#define VIP_L54_PLL_CNTL 0x00f0 +#define VIP_L54_PLL_FINE_CNTL 0x00f4 +#define VIP_L54_DTO_INCREMENTS 0x00f8 +#define VIP_PLL_CNTL1 0x00fc +#define VIP_FRAME_LOCK_CNTL 0x0100 +#define VIP_SYNC_LOCK_CNTL 0x0104 +#define VIP_TVO_SYNC_PAT_ACCUM 0x0108 +#define VIP_TVO_SYNC_THRESHOLD 0x010c +#define VIP_TVO_SYNC_PAT_EXPECT 0x0110 +#define VIP_DELAY_ONE_MAP_A 0x0114 +#define VIP_DELAY_ONE_MAP_B 0x0118 +#define VIP_DELAY_ZERO_MAP_A 0x011c +#define VIP_DELAY_ZERO_MAP_B 0x0120 +#define VIP_TVO_DATA_DELAY_A 0x0140 +#define VIP_TVO_DATA_DELAY_B 0x0144 +#define VIP_HOST_READ_DATA 0x0180 +#define VIP_HOST_WRITE_DATA 0x0184 +#define VIP_HOST_RD_WT_CNTL 0x0188 +#define VIP_VSCALER_CNTL1 0x01c0 +#define VIP_TIMING_CNTL 0x01c4 +#define VIP_VSCALER_CNTL2 0x01c8 +#define VIP_Y_FALL_CNTL 0x01cc +#define VIP_Y_RISE_CNTL 0x01d0 +#define VIP_Y_SAW_TOOTH_CNTL 0x01d4 +#define VIP_UPSAMP_AND_GAIN_CNTL 0x01e0 +#define VIP_GAIN_LIMIT_SETTINGS 0x01e4 +#define VIP_LINEAR_GAIN_SETTINGS 0x01e8 +#define VIP_MODULATOR_CNTL1 0x0200 +#define VIP_MODULATOR_CNTL2 0x0204 +#define VIP_MV_MODE_CNTL 0x0208 +#define VIP_MV_STRIPE_CNTL 0x020c +#define VIP_MV_LEVEL_CNTL1 0x0210 +#define VIP_MV_LEVEL_CNTL2 0x0214 +#define VIP_PRE_DAC_MUX_CNTL 0x0240 +#define VIP_TV_DAC_CNTL 0x0280 +#define VIP_CRC_CNTL 0x02c0 +#define VIP_VIDEO_PORT_SIG 0x02c4 +#define VIP_VBI_CC_CNTL 0x02c8 +#define VIP_VBI_EDS_CNTL 0x02cc +#define VIP_VBI_20BIT_CNTL 0x02d0 +#define VIP_VBI_DTO_CNTL 0x02d4 +#define VIP_VBI_LEVEL_CNTL 0x02d8 +#define VIP_UV_ADR 0x0300 +#define VIP_MV_STATUS 0x0330 +#define VIP_UPSAMP_COEFF0_0 0x0340 +#define VIP_UPSAMP_COEFF0_1 0x0344 +#define VIP_UPSAMP_COEFF0_2 0x0348 +#define VIP_UPSAMP_COEFF1_0 0x034c +#define VIP_UPSAMP_COEFF1_1 0x0350 +#define VIP_UPSAMP_COEFF1_2 0x0354 +#define VIP_UPSAMP_COEFF2_0 0x0358 +#define VIP_UPSAMP_COEFF2_1 0x035c +#define VIP_UPSAMP_COEFF2_2 0x0360 +#define VIP_UPSAMP_COEFF3_0 0x0364 +#define VIP_UPSAMP_COEFF3_1 0x0368 +#define VIP_UPSAMP_COEFF3_2 0x036c +#define VIP_UPSAMP_COEFF4_0 0x0370 +#define VIP_UPSAMP_COEFF4_1 0x0374 +#define VIP_UPSAMP_COEFF4_2 0x0378 +#define VIP_TV_DTO_INCREMENTS 0x0390 +#define VIP_CRT_DTO_INCREMENTS 0x0394 +#define VIP_VSYNC_DIFF_CNTL 0x03a0 +#define VIP_VSYNC_DIFF_LIMITS 0x03a4 +#define VIP_VSYNC_DIFF_RD_DATA 0x03a8 +#define VIP_SCALER_IN_WINDOW 0x0618 +#define VIP_SCALER_OUT_WINDOW 0x061c +#define VIP_H_SCALER_CONTROL 0x0600 +#define VIP_V_SCALER_CONTROL 0x0604 +#define VIP_V_DEINTERLACE_CONTROL 0x0608 +#define VIP_VBI_SCALER_CONTROL 0x060c +#define VIP_DVS_PORT_CTRL 0x0610 +#define VIP_DVS_PORT_READBACK 0x0614 +#define VIP_FIFOA_CONFIG 0x0800 +#define VIP_FIFOB_CONFIG 0x0804 +#define VIP_FIFOC_CONFIG 0x0808 +#define VIP_SPDIF_PORT_CNTL 0x080c +#define VIP_SPDIF_CHANNEL_STAT 0x0810 +#define VIP_SPDIF_AC3_PREAMBLE 0x0814 +#define VIP_I2S_TRANSMIT_CNTL 0x0818 +#define VIP_I2S_RECEIVE_CNTL 0x081c +#define VIP_SPDIF_TX_CNT_REG 0x0820 +#define VIP_IIS_TX_CNT_REG 0x0824 + +/* Status defines */ +#define VIP_BUSY 0 +#define VIP_IDLE 1 +#define VIP_RESET 2 + +#define VIPH_TIMEOUT_STAT__VIPH_REG_STAT 0x00000010 +#define VIPH_TIMEOUT_STAT__VIPH_REG_AK 0x00000010 +#define VIPH_TIMEOUT_STAT__VIPH_REGR_DIS 0x01000000 +#define TEST_DEBUG_CNTL__TEST_DEBUG_OUT_EN 0x00000001 + +#define RT_ATI_ID 0x4D541002 + +/* Register/Field values: */ +#define RT_COMP0 0x0 +#define RT_COMP1 0x1 +#define RT_COMP2 0x2 +#define RT_YF_COMP3 0x3 +#define RT_YR_COMP3 0x4 +#define RT_YCF_COMP4 0x5 +#define RT_YCR_COMP4 0x6 + +/* Video standard defines */ +#define RT_NTSC 0x0 +#define RT_PAL 0x1 +#define RT_SECAM 0x2 +#define extNONE 0x0000 +#define extNTSC 0x0100 +#define extRsvd 0x0200 +#define extPAL 0x0300 +#define extPAL_M 0x0400 +#define extPAL_N 0x0500 +#define extSECAM 0x0600 +#define extPAL_NCOMB 0x0700 +#define extNTSC_J 0x0800 +#define extNTSC_443 0x0900 +#define extPAL_BGHI 0x0A00 +#define extPAL_60 0x0B00 + /* these are used in MSP3430 */ +#define extPAL_DK1 0x0C00 +#define extPAL_AUTO 0x0D00 + +#define RT_FREF_2700 6 +#define RT_FREF_2950 5 + +#define RT_COMPOSITE 0x0 +#define RT_SVIDEO 0x1 + +#define RT_NORM_SHARPNESS 0x03 +#define RT_HIGH_SHARPNESS 0x0F + +#define RT_HUE_PAL_DEF 0x00 + +#define RT_DECINTERLACED 0x1 +#define RT_DECNONINTERLACED 0x0 + +#define NTSC_LINES 525 +#define PAL_SECAM_LINES 625 + +#define RT_ASYNC_ENABLE 0x0 +#define RT_ASYNC_DISABLE 0x1 +#define RT_ASYNC_RESET 0x1 + +#define RT_VINRST_ACTIVE 0x0 +#define RT_VINRST_RESET 0x1 +#define RT_L54RST_RESET 0x1 + +#define RT_REF_CLK 0x0 +#define RT_PLL_VIN_CLK 0x1 + +#define RT_VIN_ASYNC_RST 0x20 +#define RT_DVS_ASYNC_RST 0x80 + +#define RT_ADC_ENABLE 0x0 +#define RT_ADC_DISABLE 0x1 + +#define RT_DVSDIR_IN 0x0 +#define RT_DVSDIR_OUT 0x1 + +#define RT_DVSCLK_HIGH 0x0 +#define RT_DVSCLK_LOW 0x1 + +#define RT_DVSCLK_SEL_8FS 0x0 +#define RT_DVSCLK_SEL_27MHZ 0x1 + +#define RT_DVS_CONTSTREAM 0x1 +#define RT_DVS_NONCONTSTREAM 0x0 + +#define RT_DVSDAT_HIGH 0x0 +#define RT_DVSDAT_LOW 0x1 + +#define RT_ADC_CNTL_DEFAULT 0x03252338 + +/* COMB_CNTL0 FILTER SETTINGS FOR DIFFERENT STANDARDS: */ +#define RT_NTSCM_COMB_CNTL0_COMPOSITE 0x09438090 +#define RT_NTSCM_COMB_CNTL0_SVIDEO 0x48540000 + +#define RT_PAL_COMB_CNTL0_COMPOSITE 0x09438090 +#define RT_PAL_COMB_CNTL0_SVIDEO 0x40348090 + +#define RT_SECAM_COMB_CNTL0_COMPOSITE 0xD0108090 /* instead of orig 0xD0088090 - eric*/ +#define RT_SECAM_COMB_CNTL0_SVIDEO 0x50148090 + +#define RT_PALN_COMB_CNTL0_COMPOSITE 0x09438090 +#define RT_PALN_COMB_CNTL0_SVIDEO 0x40348090 + +#define RT_PALM_COMB_CNTL0_COMPOSITE 0x09438090 +#define RT_PALM_COMB_CNTL0_SVIDEO 0x40348090 +/* End of filter settings. */ + +/* COMB_CNTL1 FILTER SETTINGS FOR DIFFERENT STANDARDS: */ +#define RT_NTSCM_COMB_CNTL1_COMPOSITE 0x00000010 +#define RT_NTSCM_COMB_CNTL1_SVIDEO 0x00000081 + +#define RT_PAL_COMB_CNTL1_COMPOSITE 0x00000010 +#define RT_PAL_COMB_CNTL1_SVIDEO 0x000000A1 + +#define RT_SECAM_COMB_CNTL1_COMPOSITE 0x00000091 +#define RT_SECAM_COMB_CNTL1_SVIDEO 0x00000081 + +#define RT_PALN_COMB_CNTL1_COMPOSITE 0x00000010 +#define RT_PALN_COMB_CNTL1_SVIDEO 0x000000A1 + +#define RT_PALM_COMB_CNTL1_COMPOSITE 0x00000010 +#define RT_PALM_COMB_CNTL1_SVIDEO 0x000000A1 +/* End of filter settings. */ + +/* COMB_CNTL2 FILTER SETTINGS FOR DIFFERENT STANDARDS: */ +#define RT_NTSCM_COMB_CNTL2_COMPOSITE 0x16161010 +#define RT_NTSCM_COMB_CNTL2_SVIDEO 0xFFFFFFFF + +#define RT_PAL_COMB_CNTL2_COMPOSITE 0x06080102 /* instead of 0x16161010 - Ivo */ +#define RT_PAL_COMB_CNTL2_SVIDEO 0x06080102 + +#define RT_SECAM_COMB_CNTL2_COMPOSITE 0xffffffff /* instead of 0x06080102 - eric */ +#define RT_SECAM_COMB_CNTL2_SVIDEO 0x06080102 + +#define RT_PALN_COMB_CNTL2_COMPOSITE 0x06080102 +#define RT_PALN_COMB_CNTL2_SVIDEO 0x06080102 + +#define RT_PALM_COMB_CNTL2_COMPOSITE 0x06080102 +#define RT_PALM_COMB_CNTL2_SVIDEO 0x06080102 +/* End of filter settings. */ + +/* COMB_LINE_LENGTH FILTER SETTINGS FOR DIFFERENT STANDARDS: */ +#define RT_NTSCM_COMB_LENGTH_COMPOSITE 0x0718038A +#define RT_NTSCM_COMB_LENGTH_SVIDEO 0x0718038A + +#define RT_PAL_COMB_LENGTH_COMPOSITE 0x08DA046B +#define RT_PAL_COMB_LENGTH_SVIDEO 0x08DA046B + +#define RT_SECAM_COMB_LENGTH_COMPOSITE 0x08DA046A +#define RT_SECAM_COMB_LENGTH_SVIDEO 0x08DA046A + +#define RT_PALN_COMB_LENGTH_COMPOSITE 0x07260391 +#define RT_PALN_COMB_LENGTH_SVIDEO 0x07260391 + +#define RT_PALM_COMB_LENGTH_COMPOSITE 0x07160389 +#define RT_PALM_COMB_LENGTH_SVIDEO 0x07160389 +/* End of filter settings. */ + +/* LP_AGC_CLAMP_CNTL0 */ +#define RT_NTSCM_SYNCTIP_REF0 0x00000037 +#define RT_NTSCM_SYNCTIP_REF1 0x00000029 +#define RT_NTSCM_CLAMP_REF 0x0000003B +#define RT_NTSCM_PEAKWHITE 0x000000FF +#define RT_NTSCM_VBI_PEAKWHITE 0x000000C2 + +#define RT_NTSCM_WPA_THRESHOLD 0x00000406 +#define RT_NTSCM_WPA_TRIGGER_LO 0x000000B3 + +#define RT_NTSCM_WPA_TRIGGER_HIGH 0x0000021B + +#define RT_NTSCM_LP_LOCKOUT_START 0x00000206 +#define RT_NTSCM_LP_LOCKOUT_END 0x00000021 +#define RT_NTSCM_CH_DTO_INC 0x00400000 +#define RT_NTSCM_CH_PLL_SGAIN 0x00000001 +#define RT_NTSCM_CH_PLL_FGAIN 0x00000002 + +#define RT_NTSCM_CR_BURST_GAIN 0x0000007A +#define RT_NTSCM_CB_BURST_GAIN 0x000000AC + +#define RT_NTSCM_CH_HEIGHT 0x000000CD +#define RT_NTSCM_CH_KILL_LEVEL 0x000000C0 +#define RT_NTSCM_CH_AGC_ERROR_LIM 0x00000002 +#define RT_NTSCM_CH_AGC_FILTER_EN 0x00000000 +#define RT_NTSCM_CH_AGC_LOOP_SPEED 0x00000000 + +#define RT_NTSCM_CRDR_ACTIVE_GAIN 0x0000007A +#define RT_NTSCM_CBDB_ACTIVE_GAIN 0x000000AC + +#define RT_NTSCM_VERT_LOCKOUT_START 0x00000207 +#define RT_NTSCM_VERT_LOCKOUT_END 0x0000000E + +#define RT_NTSCJ_SYNCTIP_REF0 0x00000004 +#define RT_NTSCJ_SYNCTIP_REF1 0x00000012 +#define RT_NTSCJ_CLAMP_REF 0x0000003B +#define RT_NTSCJ_PEAKWHITE 0x000000CB +#define RT_NTSCJ_VBI_PEAKWHITE 0x000000C2 +#define RT_NTSCJ_WPA_THRESHOLD 0x000004B0 +#define RT_NTSCJ_WPA_TRIGGER_LO 0x000000B4 +#define RT_NTSCJ_WPA_TRIGGER_HIGH 0x0000021C +#define RT_NTSCJ_LP_LOCKOUT_START 0x00000206 +#define RT_NTSCJ_LP_LOCKOUT_END 0x00000021 + +#define RT_NTSCJ_CR_BURST_GAIN 0x00000071 +#define RT_NTSCJ_CB_BURST_GAIN 0x0000009F +#define RT_NTSCJ_CH_HEIGHT 0x000000CD +#define RT_NTSCJ_CH_KILL_LEVEL 0x000000C0 +#define RT_NTSCJ_CH_AGC_ERROR_LIM 0x00000002 +#define RT_NTSCJ_CH_AGC_FILTER_EN 0x00000000 +#define RT_NTSCJ_CH_AGC_LOOP_SPEED 0x00000000 + +#define RT_NTSCJ_CRDR_ACTIVE_GAIN 0x00000071 +#define RT_NTSCJ_CBDB_ACTIVE_GAIN 0x0000009F +#define RT_NTSCJ_VERT_LOCKOUT_START 0x00000207 +#define RT_NTSCJ_VERT_LOCKOUT_END 0x0000000E + +#define RT_PAL_SYNCTIP_REF0 0x37 /* instead of 0x00000004 - Ivo */ +#define RT_PAL_SYNCTIP_REF1 0x26 /* instead of 0x0000000F - Ivo */ +#define RT_PAL_CLAMP_REF 0x0000003B +#define RT_PAL_PEAKWHITE 0xFF /* instead of 0x000000C1 - Ivo */ +#define RT_PAL_VBI_PEAKWHITE 0xC6 /* instead of 0x000000C7 - Ivo */ +#define RT_PAL_WPA_THRESHOLD 0x59C /* instead of 0x000006A4 - Ivo */ + +#define RT_PAL_WPA_TRIGGER_LO 0x00000096 +#define RT_PAL_WPA_TRIGGER_HIGH 0x000001C2 +#define RT_PAL_LP_LOCKOUT_START 0x00000263 +#define RT_PAL_LP_LOCKOUT_END 0x0000002C + +#define RT_PAL_CH_DTO_INC 0x00400000 +#define RT_PAL_CH_PLL_SGAIN 1 /* instead of 0x00000002 - Ivo */ +#define RT_PAL_CH_PLL_FGAIN 2 /* instead of 0x00000001 - Ivo */ +#define RT_PAL_CR_BURST_GAIN 0x0000007A +#define RT_PAL_CB_BURST_GAIN 0x000000AB +#define RT_PAL_CH_HEIGHT 0x0000009C +#define RT_PAL_CH_KILL_LEVEL 4 /* instead of 0x00000090 - Ivo */ +#define RT_PAL_CH_AGC_ERROR_LIM 1 /* instead of 0x00000002 - Ivo */ +#define RT_PAL_CH_AGC_FILTER_EN 1 /* instead of 0x00000000 - Ivo */ +#define RT_PAL_CH_AGC_LOOP_SPEED 0x00000000 + +#define RT_PAL_CRDR_ACTIVE_GAIN 0x9E /* instead of 0x0000007A - Ivo */ +#define RT_PAL_CBDB_ACTIVE_GAIN 0xDF /* instead of 0x000000AB - Ivo */ +#define RT_PAL_VERT_LOCKOUT_START 0x00000269 +#define RT_PAL_VERT_LOCKOUT_END 0x00000012 + +#define RT_SECAM_SYNCTIP_REF0 0x37 /* instead of 0x00000004 - Ivo */ +#define RT_SECAM_SYNCTIP_REF1 0x26 /* instead of 0x0000000F - Ivo */ +#define RT_SECAM_CLAMP_REF 0x0000003B +#define RT_SECAM_PEAKWHITE 0xFF /* instead of 0x000000C1 - Ivo */ +#define RT_SECAM_VBI_PEAKWHITE 0xC6 /* instead of 0x000000C7 - Ivo */ +#define RT_SECAM_WPA_THRESHOLD 0x57A /* instead of 0x6A4, instead of 0x0000059C is Ivo's value , -eric*/ + +#define RT_SECAM_WPA_TRIGGER_LO 0x96 /* instead of 0x0000026B - eric */ +#define RT_SECAM_WPA_TRIGGER_HIGH 0x000001C2 +#define RT_SECAM_LP_LOCKOUT_START 0x263 /* instead of 0x0000026B - eric */ +#define RT_SECAM_LP_LOCKOUT_END 0x2b /* instead of 0x0000002C -eric */ + +#define RT_SECAM_CH_DTO_INC 0x003E7A28 +#define RT_SECAM_CH_PLL_SGAIN 0x4 /* instead of 0x00000006 -Volodya */ +#define RT_SECAM_CH_PLL_FGAIN 0x7 /* instead of 0x00000006 -Volodya */ + +#define RT_SECAM_CR_BURST_GAIN 0x1FF /* instead of 0x00000200 -Volodya */ +#define RT_SECAM_CB_BURST_GAIN 0x1FF /* instead of 0x00000200 -Volodya */ +#define RT_SECAM_CH_HEIGHT 0x00000066 +#define RT_SECAM_CH_KILL_LEVEL 0x00000060 +#define RT_SECAM_CH_AGC_ERROR_LIM 0x00000003 +#define RT_SECAM_CH_AGC_FILTER_EN 0x00000000 +#define RT_SECAM_CH_AGC_LOOP_SPEED 0x00000000 + +#define RT_SECAM_CRDR_ACTIVE_GAIN 0x11B /* instead of 0x00000200 - eric */ +#define RT_SECAM_CBDB_ACTIVE_GAIN 0x15A /* instead of 0x00000200 - eric */ +#define RT_SECAM_VERT_LOCKOUT_START 0x00000269 +#define RT_SECAM_VERT_LOCKOUT_END 0x00000012 + +#define RT_PAL_VS_FIELD_BLANK_END 0x2A /* instead of 0x0000002C - Ivo*/ +#define RT_NTSCM_VS_FIELD_BLANK_END 0x0000000A + +#define RT_NTSCM_FIELD_IDLOCATION 0x00000105 +#define RT_PAL_FIELD_IDLOCATION 0x00000137 + +#define RT_NTSCM_H_ACTIVE_START 0x00000070 +#define RT_NTSCM_H_ACTIVE_END 0x00000363 + +#define RT_PAL_H_ACTIVE_START 0x0000009A +#define RT_PAL_H_ACTIVE_END 0x00000439 + +#define RT_NTSCM_V_ACTIVE_START ((22-4)*2+1) +#define RT_NTSCM_V_ACTIVE_END ((22+240-4)*2+1) + +#define RT_PAL_V_ACTIVE_START 0x2E /* instead of 0x00000023 (Same as SECAM) - Ivo */ +#define RT_PAL_V_ACTIVE_END 0x269 /* instead of 0x00000262 - Ivo */ + +/* VBI */ +#define RT_NTSCM_H_VBI_WIND_START 0x00000049 +#define RT_NTSCM_H_VBI_WIND_END 0x00000366 + +#define RT_PAL_H_VBI_WIND_START 0x00000084 +#define RT_PAL_H_VBI_WIND_END 0x0000041F + +#define RT_NTSCM_V_VBI_WIND_START fld_V_VBI_WIND_START_def +#define RT_NTSCM_V_VBI_WIND_END fld_V_VBI_WIND_END_def + +#define RT_PAL_V_VBI_WIND_START 0x8 /* instead of 0x0000000B - Ivo */ +#define RT_PAL_V_VBI_WIND_END 0x2D /* instead of 0x00000022 - Ivo */ + +#define RT_VBI_CAPTURE_EN 0x00000001 /* Enable */ +#define RT_VBI_CAPTURE_DIS 0x00000000 /* Disable */ +#define RT_RAW_CAPTURE 0x00000002 /* Use raw Video Capture. */ + +#define RT_NTSCM_VSYNC_INT_TRIGGER 0x2AA +#define RT_PALSEM_VSYNC_INT_TRIGGER 0x353 + +#define RT_NTSCM_VSYNC_INT_HOLD 0x17 +#define RT_PALSEM_VSYNC_INT_HOLD 0x1C + +#define RT_NTSCM_VS_FIELD_BLANK_START 0x206 +#define RT_PALSEM_VS_FIELD_BLANK_START 0x26D /* instead of 0x26C - Ivo */ + +#define RT_FIELD_FLIP_EN 0x4 +#define RT_V_FIELD_FLIP_INVERTED 0x2000 + +#define RT_NTSCM_H_IN_START 0x70 +#define RT_PAL_H_IN_START 154 /* instead of 144 - Ivo */ +#define RT_SECAM_H_IN_START 0x91 /* instead of 0x9A, Ivo value is 154, instead of 144 - Volodya, - eric */ +#define RT_NTSC_H_ACTIVE_SIZE 744 +#define RT_PAL_H_ACTIVE_SIZE 928 /* instead of 927 - Ivo */ +#define RT_SECAM_H_ACTIVE_SIZE 932 /* instead of 928, instead of 927 - Ivo, - eric */ +#define RT_NTSCM_V_IN_START (0x23) +#define RT_PAL_V_IN_START 44 /* instead of (45-6) - Ivo */ +#define RT_SECAM_V_IN_START 0x2C /* instead of (45-6) - Volodya */ +#define RT_NTSCM_V_ACTIVE_SIZE 480 +#define RT_PAL_V_ACTIVE_SIZE 572 /* instead of 575 - Ivo */ +#define RT_SECAM_V_ACTIVE_SIZE 570 /* instead of 572, instead of 575 - Ivo, - eric */ + +#define RT_NTSCM_WIN_CLOSE_LIMIT 0x4D +#define RT_NTSCJ_WIN_CLOSE_LIMIT 0x4D +#define RT_NTSC443_WIN_CLOSE_LIMIT 0x5F +#define RT_PALM_WIN_CLOSE_LIMIT 0x4D +#define RT_PALN_WIN_CLOSE_LIMIT 0x5F +#define RT_SECAM_WIN_CLOSE_LIMIT 0xC7 /* instead of 0x5F - eric */ + +#define RT_NTSCM_VS_FIELD_BLANK_START 0x206 + +#define RT_NTSCM_HS_PLL_SGAIN 0x5 +#define RT_NTSCM_HS_PLL_FGAIN 0x7 + +#define RT_NTSCM_H_OUT_WIND_WIDTH 0x2F4 +#define RT_NTSCM_V_OUT_WIND_HEIGHT 0xF0 + +#define TV 0x1 +#define LINEIN 0x2 +#define MUTE 0x3 + +#define DEC_COMPOSITE 0 +#define DEC_SVIDEO 1 +#define DEC_TUNER 2 + +#define DEC_NTSC 0 +#define DEC_PAL 1 +#define DEC_SECAM 2 +#define DEC_NTSC_J 8 + +#define DEC_SMOOTH 0 +#define DEC_SHARP 1 + +/* RT Register Field Defaults: */ +#define fld_tmpReg1_def 0x00000000 +#define fld_tmpReg2_def 0x00000001 +#define fld_tmpReg3_def 0x00000002 + +#define fld_LP_CONTRAST_def 0x0000006e +#define fld_LP_BRIGHTNESS_def 0x00003ff0 +#define fld_CP_HUE_CNTL_def 0x00000000 +#define fld_LUMA_FILTER_def 0x00000001 +#define fld_H_SCALE_RATIO_def 0x00010000 +#define fld_H_SHARPNESS_def 0x00000000 + +#define fld_V_SCALE_RATIO_def 0x00000800 +#define fld_V_DEINTERLACE_ON_def 0x00000001 +#define fld_V_BYPSS_def 0x00000000 +#define fld_V_DITHER_ON_def 0x00000001 +#define fld_EVENF_OFFSET_def 0x00000000 +#define fld_ODDF_OFFSET_def 0x00000000 + +#define fld_INTERLACE_DETECTED_def 0x00000000 + +#define fld_VS_LINE_COUNT_def 0x00000000 +#define fld_VS_DETECTED_LINES_def 0x00000000 +#define fld_VS_ITU656_VB_def 0x00000000 + +#define fld_VBI_CC_DATA_def 0x00000000 +#define fld_VBI_CC_WT_def 0x00000000 +#define fld_VBI_CC_WT_ACK_def 0x00000000 +#define fld_VBI_CC_HOLD_def 0x00000000 +#define fld_VBI_DECODE_EN_def 0x00000000 + +#define fld_VBI_CC_DTO_P_def 0x00001802 +#define fld_VBI_20BIT_DTO_P_def 0x0000155c + +#define fld_VBI_CC_LEVEL_def 0x0000003f +#define fld_VBI_20BIT_LEVEL_def 0x00000059 +#define fld_VBI_CLK_RUNIN_GAIN_def 0x0000010f + +#define fld_H_VBI_WIND_START_def 0x00000041 +#define fld_H_VBI_WIND_END_def 0x00000366 + +#define fld_V_VBI_WIND_START_def 0x0D +#define fld_V_VBI_WIND_END_def 0x24 + +#define fld_VBI_20BIT_DATA0_def 0x00000000 +#define fld_VBI_20BIT_DATA1_def 0x00000000 +#define fld_VBI_20BIT_WT_def 0x00000000 +#define fld_VBI_20BIT_WT_ACK_def 0x00000000 +#define fld_VBI_20BIT_HOLD_def 0x00000000 + +#define fld_VBI_CAPTURE_ENABLE_def 0x00000000 + +#define fld_VBI_EDS_DATA_def 0x00000000 +#define fld_VBI_EDS_WT_def 0x00000000 +#define fld_VBI_EDS_WT_ACK_def 0x00000000 +#define fld_VBI_EDS_HOLD_def 0x00000000 + +#define fld_VBI_SCALING_RATIO_def 0x00010000 +#define fld_VBI_ALIGNER_ENABLE_def 0x00000000 + +#define fld_H_ACTIVE_START_def 0x00000070 +#define fld_H_ACTIVE_END_def 0x000002f0 + +#define fld_V_ACTIVE_START_def ((22-4)*2+1) +#define fld_V_ACTIVE_END_def ((22+240-4)*2+2) + +#define fld_CH_HEIGHT_def 0x000000CD +#define fld_CH_KILL_LEVEL_def 0x000000C0 +#define fld_CH_AGC_ERROR_LIM_def 0x00000002 +#define fld_CH_AGC_FILTER_EN_def 0x00000000 +#define fld_CH_AGC_LOOP_SPEED_def 0x00000000 + +#define fld_HUE_ADJ_def 0x00000000 + +#define fld_STANDARD_SEL_def 0x00000000 +#define fld_STANDARD_YC_def 0x00000000 + +#define fld_ADC_PDWN_def 0x00000001 +#define fld_INPUT_SELECT_def 0x00000000 + +#define fld_ADC_PREFLO_def 0x00000003 +#define fld_H_SYNC_PULSE_WIDTH_def 0x00000000 +#define fld_HS_GENLOCKED_def 0x00000000 +#define fld_HS_SYNC_IN_WIN_def 0x00000000 + +#define fld_VIN_ASYNC_RST_def 0x00000001 +#define fld_DVS_ASYNC_RST_def 0x00000001 + +/* Vendor IDs: */ +#define fld_VIP_VENDOR_ID_def 0x00001002 +#define fld_VIP_DEVICE_ID_def 0x00004d54 +#define fld_VIP_REVISION_ID_def 0x00000001 + +/* AGC Delay Register */ +#define fld_BLACK_INT_START_def 0x00000031 +#define fld_BLACK_INT_LENGTH_def 0x0000000f + +#define fld_UV_INT_START_def 0x0000003b +#define fld_U_INT_LENGTH_def 0x0000000f +#define fld_V_INT_LENGTH_def 0x0000000f +#define fld_CRDR_ACTIVE_GAIN_def 0x0000007a +#define fld_CBDB_ACTIVE_GAIN_def 0x000000ac + +#define fld_DVS_DIRECTION_def 0x00000000 +#define fld_DVS_VBI_CARD8_SWAP_def 0x00000000 +#define fld_DVS_CLK_SELECT_def 0x00000000 +#define fld_CONTINUOUS_STREAM_def 0x00000000 +#define fld_DVSOUT_CLK_DRV_def 0x00000001 +#define fld_DVSOUT_DATA_DRV_def 0x00000001 + +#define fld_COMB_CNTL0_def 0x09438090 +#define fld_COMB_CNTL1_def 0x00000010 + +#define fld_COMB_CNTL2_def 0x16161010 +#define fld_COMB_LENGTH_def 0x0718038A + +#define fld_SYNCTIP_REF0_def 0x00000037 +#define fld_SYNCTIP_REF1_def 0x00000029 +#define fld_CLAMP_REF_def 0x0000003B +#define fld_AGC_PEAKWHITE_def 0x000000FF +#define fld_VBI_PEAKWHITE_def 0x000000D2 + +#define fld_WPA_THRESHOLD_def 0x000003B0 + +#define fld_WPA_TRIGGER_LO_def 0x000000B4 +#define fld_WPA_TRIGGER_HIGH_def 0x0000021C + +#define fld_LOCKOUT_START_def 0x00000206 +#define fld_LOCKOUT_END_def 0x00000021 + +#define fld_CH_DTO_INC_def 0x00400000 +#define fld_PLL_SGAIN_def 0x00000001 +#define fld_PLL_FGAIN_def 0x00000002 + +#define fld_CR_BURST_GAIN_def 0x0000007a +#define fld_CB_BURST_GAIN_def 0x000000ac + +#define fld_VERT_LOCKOUT_START_def 0x00000207 +#define fld_VERT_LOCKOUT_END_def 0x0000000E + +#define fld_H_IN_WIND_START_def 0x00000070 +#define fld_V_IN_WIND_START_def 0x00000027 + +#define fld_H_OUT_WIND_WIDTH_def 0x000002f4 + +#define fld_V_OUT_WIND_WIDTH_def 0x000000f0 + +#define fld_HS_LINE_TOTAL_def 0x0000038E + +#define fld_MIN_PULSE_WIDTH_def 0x0000002F +#define fld_MAX_PULSE_WIDTH_def 0x00000046 + +#define fld_WIN_CLOSE_LIMIT_def 0x0000004D +#define fld_WIN_OPEN_LIMIT_def 0x000001B7 + +#define fld_VSYNC_INT_TRIGGER_def 0x000002AA + +#define fld_VSYNC_INT_HOLD_def 0x0000001D + +#define fld_VIN_M0_def 0x00000039 +#define fld_VIN_N0_def 0x0000014c +#define fld_MNFLIP_EN_def 0x00000000 +#define fld_VIN_P_def 0x00000006 +#define fld_REG_CLK_SEL_def 0x00000000 + +#define fld_VIN_M1_def 0x00000000 +#define fld_VIN_N1_def 0x00000000 +#define fld_VIN_DRIVER_SEL_def 0x00000000 +#define fld_VIN_MNFLIP_REQ_def 0x00000000 +#define fld_VIN_MNFLIP_DONE_def 0x00000000 +#define fld_TV_LOCK_TO_VIN_def 0x00000000 +#define fld_TV_P_FOR_WINCLK_def 0x00000004 + +#define fld_VINRST_def 0x00000001 +#define fld_VIN_CLK_SEL_def 0x00000000 + +#define fld_VS_FIELD_BLANK_START_def 0x00000206 + +#define fld_VS_FIELD_BLANK_END_def 0x0000000A + +/*#define fld_VS_FIELD_IDLOCATION_def 0x00000105 */ +#define fld_VS_FIELD_IDLOCATION_def 0x00000001 +#define fld_VS_FRAME_TOTAL_def 0x00000217 + +#define fld_SYNC_TIP_START_def 0x00000372 +#define fld_SYNC_TIP_LENGTH_def 0x0000000F + +#define fld_GAIN_FORCE_DATA_def 0x00000000 +#define fld_GAIN_FORCE_EN_def 0x00000000 +#define fld_I_CLAMP_SEL_def 0x00000003 +#define fld_I_AGC_SEL_def 0x00000001 +#define fld_EXT_CLAMP_CAP_def 0x00000001 +#define fld_EXT_AGC_CAP_def 0x00000001 +#define fld_DECI_DITHER_EN_def 0x00000001 +#define fld_ADC_PREFHI_def 0x00000000 +#define fld_ADC_CH_GAIN_SEL_def 0x00000001 + +#define fld_HS_PLL_SGAIN_def 0x00000003 + +#define fld_NREn_def 0x00000000 +#define fld_NRGainCntl_def 0x00000000 +#define fld_NRBWTresh_def 0x00000000 +#define fld_NRGCTresh_def 0x00000000 +#define fld_NRCoefDespeclMode_def 0x00000000 + +#define fld_GPIO_5_OE_def 0x00000000 +#define fld_GPIO_6_OE_def 0x00000000 + +#define fld_GPIO_5_OUT_def 0x00000000 +#define fld_GPIO_6_OUT_def 0x00000000 + +/* End of field default values. */ + +#endif /* RADEON_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/vidix/radeon_vid.c Sun Apr 01 00:02:43 2007 +0000 @@ -0,0 +1,2101 @@ +/* + radeon_vid - VIDIX based video driver for Radeon and Rage128 chips + Copyrights 2002 Nick Kurshev. This file is based on sources from + GATOS (gatos.sf.net) and X11 (www.xfree86.org) + Licence: GPL + + 31.12.2002 added support for fglrx drivers by Marcel Naziri (zwobbl@zwobbl.de) + 6.04.2004 fixes to allow compiling vidix without X11 (broken in original patch) + PPC support by Alex Beregszaszi +*/ + +#include <errno.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <math.h> +#include <inttypes.h> + +#include "../config.h" +#include "../libavutil/common.h" +#include "../mpbswap.h" +#include "../libdha/pci_ids.h" +#include "../libdha/pci_names.h" +#include "vidix.h" +#include "fourcc.h" +#include "../libdha/libdha.h" +#include "radeon.h" + +#ifdef HAVE_X11 +#include <X11/Xlib.h> +#endif + +#ifdef RAGE128 +#define RADEON_MSG "[rage128]" +#define X_ADJUST 0 +#else +#define RADEON_MSG "[radeon]" +#define X_ADJUST (is_shift_required ? 8 : 0) +#ifndef RADEON +#define RADEON +#endif +#endif + +static int __verbose = 0; +#ifdef RADEON +static int is_shift_required = 0; +#endif + +typedef struct bes_registers_s +{ + /* base address of yuv framebuffer */ + uint32_t yuv_base; + uint32_t fourcc; + uint32_t dest_bpp; + /* YUV BES registers */ + uint32_t reg_load_cntl; + uint32_t h_inc; + uint32_t step_by; + uint32_t y_x_start; + uint32_t y_x_end; + uint32_t v_inc; + uint32_t p1_blank_lines_at_top; + uint32_t p23_blank_lines_at_top; + uint32_t vid_buf_pitch0_value; + uint32_t vid_buf_pitch1_value; + uint32_t p1_x_start_end; + uint32_t p2_x_start_end; + uint32_t p3_x_start_end; + uint32_t base_addr; + uint32_t vid_buf_base_adrs_y[VID_PLAY_MAXFRAMES]; + uint32_t vid_buf_base_adrs_u[VID_PLAY_MAXFRAMES]; + uint32_t vid_buf_base_adrs_v[VID_PLAY_MAXFRAMES]; + uint32_t vid_nbufs; + + uint32_t p1_v_accum_init; + uint32_t p1_h_accum_init; + uint32_t p23_v_accum_init; + uint32_t p23_h_accum_init; + uint32_t scale_cntl; + uint32_t exclusive_horz; + uint32_t auto_flip_cntl; + uint32_t filter_cntl; + uint32_t key_cntl; + uint32_t test; + /* Configurable stuff */ + int double_buff; + + int brightness; + int saturation; + + int ckey_on; + uint32_t graphics_key_clr; + uint32_t graphics_key_msk; + uint32_t ckey_cntl; + + int deinterlace_on; + uint32_t deinterlace_pattern; + +} bes_registers_t; + +typedef struct video_registers_s +{ + const char * sname; + uint32_t name; + uint32_t value; +}video_registers_t; + +static bes_registers_t besr; +#ifndef RAGE128 +static int RadeonFamily=100; +#endif +#define DECLARE_VREG(name) { #name, name, 0 } +static video_registers_t vregs[] = +{ + DECLARE_VREG(VIDEOMUX_CNTL), + DECLARE_VREG(VIPPAD_MASK), + DECLARE_VREG(VIPPAD1_A), + DECLARE_VREG(VIPPAD1_EN), + DECLARE_VREG(VIPPAD1_Y), + DECLARE_VREG(OV0_Y_X_START), + DECLARE_VREG(OV0_Y_X_END), + DECLARE_VREG(OV0_PIPELINE_CNTL), + DECLARE_VREG(OV0_EXCLUSIVE_HORZ), + DECLARE_VREG(OV0_EXCLUSIVE_VERT), + DECLARE_VREG(OV0_REG_LOAD_CNTL), + DECLARE_VREG(OV0_SCALE_CNTL), + DECLARE_VREG(OV0_V_INC), + DECLARE_VREG(OV0_P1_V_ACCUM_INIT), + DECLARE_VREG(OV0_P23_V_ACCUM_INIT), + DECLARE_VREG(OV0_P1_BLANK_LINES_AT_TOP), + DECLARE_VREG(OV0_P23_BLANK_LINES_AT_TOP), +#ifdef RADEON + DECLARE_VREG(OV0_BASE_ADDR), +#endif + DECLARE_VREG(OV0_VID_BUF0_BASE_ADRS), + DECLARE_VREG(OV0_VID_BUF1_BASE_ADRS), + DECLARE_VREG(OV0_VID_BUF2_BASE_ADRS), + DECLARE_VREG(OV0_VID_BUF3_BASE_ADRS), + DECLARE_VREG(OV0_VID_BUF4_BASE_ADRS), + DECLARE_VREG(OV0_VID_BUF5_BASE_ADRS), + DECLARE_VREG(OV0_VID_BUF_PITCH0_VALUE), + DECLARE_VREG(OV0_VID_BUF_PITCH1_VALUE), + DECLARE_VREG(OV0_AUTO_FLIP_CNTL), + DECLARE_VREG(OV0_DEINTERLACE_PATTERN), + DECLARE_VREG(OV0_SUBMIT_HISTORY), + DECLARE_VREG(OV0_H_INC), + DECLARE_VREG(OV0_STEP_BY), + DECLARE_VREG(OV0_P1_H_ACCUM_INIT), + DECLARE_VREG(OV0_P23_H_ACCUM_INIT), + DECLARE_VREG(OV0_P1_X_START_END), + DECLARE_VREG(OV0_P2_X_START_END), + DECLARE_VREG(OV0_P3_X_START_END), + DECLARE_VREG(OV0_FILTER_CNTL), + DECLARE_VREG(OV0_FOUR_TAP_COEF_0), + DECLARE_VREG(OV0_FOUR_TAP_COEF_1), + DECLARE_VREG(OV0_FOUR_TAP_COEF_2), + DECLARE_VREG(OV0_FOUR_TAP_COEF_3), + DECLARE_VREG(OV0_FOUR_TAP_COEF_4), + DECLARE_VREG(OV0_FLAG_CNTL), +#ifdef RAGE128 + DECLARE_VREG(OV0_COLOUR_CNTL), +#else + DECLARE_VREG(OV0_SLICE_CNTL), +#endif + DECLARE_VREG(OV0_VID_KEY_CLR), + DECLARE_VREG(OV0_VID_KEY_MSK), + DECLARE_VREG(OV0_GRAPHICS_KEY_CLR), + DECLARE_VREG(OV0_GRAPHICS_KEY_MSK), + DECLARE_VREG(OV0_KEY_CNTL), + DECLARE_VREG(OV0_TEST), + DECLARE_VREG(OV0_LIN_TRANS_A), + DECLARE_VREG(OV0_LIN_TRANS_B), + DECLARE_VREG(OV0_LIN_TRANS_C), + DECLARE_VREG(OV0_LIN_TRANS_D), + DECLARE_VREG(OV0_LIN_TRANS_E), + DECLARE_VREG(OV0_LIN_TRANS_F), + DECLARE_VREG(OV0_GAMMA_0_F), + DECLARE_VREG(OV0_GAMMA_10_1F), + DECLARE_VREG(OV0_GAMMA_20_3F), + DECLARE_VREG(OV0_GAMMA_40_7F), + DECLARE_VREG(OV0_GAMMA_380_3BF), + DECLARE_VREG(OV0_GAMMA_3C0_3FF), + DECLARE_VREG(SUBPIC_CNTL), + DECLARE_VREG(SUBPIC_DEFCOLCON), + DECLARE_VREG(SUBPIC_Y_X_START), + DECLARE_VREG(SUBPIC_Y_X_END), + DECLARE_VREG(SUBPIC_V_INC), + DECLARE_VREG(SUBPIC_H_INC), + DECLARE_VREG(SUBPIC_BUF0_OFFSET), + DECLARE_VREG(SUBPIC_BUF1_OFFSET), + DECLARE_VREG(SUBPIC_LC0_OFFSET), + DECLARE_VREG(SUBPIC_LC1_OFFSET), + DECLARE_VREG(SUBPIC_PITCH), + DECLARE_VREG(SUBPIC_BTN_HLI_COLCON), + DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_START), + DECLARE_VREG(SUBPIC_BTN_HLI_Y_X_END), + DECLARE_VREG(SUBPIC_PALETTE_INDEX), + DECLARE_VREG(SUBPIC_PALETTE_DATA), + DECLARE_VREG(SUBPIC_H_ACCUM_INIT), + DECLARE_VREG(SUBPIC_V_ACCUM_INIT), + DECLARE_VREG(IDCT_RUNS), + DECLARE_VREG(IDCT_LEVELS), + DECLARE_VREG(IDCT_AUTH_CONTROL), + DECLARE_VREG(IDCT_AUTH), + DECLARE_VREG(IDCT_CONTROL), + DECLARE_VREG(CONFIG_CNTL) +}; + +#ifdef HAVE_X11 +static uint32_t firegl_shift = 0; +#endif +static void * radeon_mmio_base = 0; +static void * radeon_mem_base = 0; +static int32_t radeon_overlay_off = 0; +static uint32_t radeon_ram_size = 0; +/* Restore on exit */ +static uint32_t SAVED_OV0_GRAPHICS_KEY_CLR = 0; +static uint32_t SAVED_OV0_GRAPHICS_KEY_MSK = 0; +static uint32_t SAVED_OV0_VID_KEY_CLR = 0; +static uint32_t SAVED_OV0_VID_KEY_MSK = 0; +static uint32_t SAVED_OV0_KEY_CNTL = 0; +#ifdef WORDS_BIGENDIAN +static uint32_t SAVED_CONFIG_CNTL = 0; +#if defined(RAGE128) +#define APER_0_BIG_ENDIAN_16BPP_SWAP (1<<0) +#define APER_0_BIG_ENDIAN_32BPP_SWAP (2<<0) +#else +#define RADEON_SURFACE_CNTL 0x0b00 +#define RADEON_NONSURF_AP0_SWP_16BPP (1 << 20) +#define RADEON_NONSURF_AP0_SWP_32BPP (1 << 21) +#endif +#endif + +#define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ)))) +#define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL + +#define INREG8(addr) GETREG(uint8_t,(uint8_t*)(radeon_mmio_base),addr) +#define OUTREG8(addr,val) SETREG(uint8_t,(uint8_t*)(radeon_mmio_base),addr,val) + +static inline uint32_t INREG (uint32_t addr) { + uint32_t tmp = GETREG(uint32_t,(uint8_t*)(radeon_mmio_base),addr); + return le2me_32(tmp); +} +//#define OUTREG(addr,val) SETREG(uint32_t,(uint8_t*)(radeon_mmio_base),addr,val) +#define OUTREG(addr,val) SETREG(uint32_t,(uint8_t*)(radeon_mmio_base),addr,le2me_32(val)) +#define OUTREGP(addr,val,mask) \ + do { \ + unsigned int _tmp = INREG(addr); \ + _tmp &= (mask); \ + _tmp |= (val); \ + OUTREG(addr, _tmp); \ + } while (0) + +static __inline__ uint32_t INPLL(uint32_t addr) +{ + OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000001f); + return (INREG(CLOCK_CNTL_DATA)); +} + +#define OUTPLL(addr,val) OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000001f) | 0x00000080); \ + OUTREG(CLOCK_CNTL_DATA, val) +#define OUTPLLP(addr,val,mask) \ + do { \ + unsigned int _tmp = INPLL(addr); \ + _tmp &= (mask); \ + _tmp |= (val); \ + OUTPLL(addr, _tmp); \ + } while (0) + +static uint32_t radeon_vid_get_dbpp( void ) +{ + uint32_t dbpp,retval; + dbpp = (INREG(CRTC_GEN_CNTL)>>8)& 0xF; + switch(dbpp) + { + case DST_8BPP: retval = 8; break; + case DST_15BPP: retval = 15; break; + case DST_16BPP: retval = 16; break; + case DST_24BPP: retval = 24; break; + default: retval=32; break; + } + return retval; +} + +static int radeon_is_dbl_scan( void ) +{ + return (INREG(CRTC_GEN_CNTL))&CRTC_DBL_SCAN_EN; +} + +static int radeon_is_interlace( void ) +{ + return (INREG(CRTC_GEN_CNTL))&CRTC_INTERLACE_EN; +} + +static uint32_t radeon_get_xres( void ) +{ + /* FIXME: currently we extract that from CRTC!!!*/ + uint32_t xres,h_total; + h_total = INREG(CRTC_H_TOTAL_DISP); + xres = (h_total >> 16) & 0xffff; + return (xres + 1)*8; +} + +static uint32_t radeon_get_yres( void ) +{ + /* FIXME: currently we extract that from CRTC!!!*/ + uint32_t yres,v_total; + v_total = INREG(CRTC_V_TOTAL_DISP); + yres = (v_total >> 16) & 0xffff; + return yres + 1; +} + +/* get flat panel x resolution*/ +static uint32_t radeon_get_fp_xres( void ){ + uint32_t xres=(INREG(FP_HORZ_STRETCH)&0x00fff000)>>16; + xres=(xres+1)*8; + return xres; +} + +/* get flat panel y resolution*/ +static uint32_t radeon_get_fp_yres( void ){ + uint32_t yres=(INREG(FP_VERT_STRETCH)&0x00fff000)>>12; + return yres+1; +} + +static void radeon_wait_vsync(void) +{ + int i; + + OUTREG(GEN_INT_STATUS, VSYNC_INT_AK); + for (i = 0; i < 2000000; i++) + { + if (INREG(GEN_INT_STATUS) & VSYNC_INT) break; + } +} + +#ifdef RAGE128 +static void _radeon_engine_idle(void); +static void _radeon_fifo_wait(unsigned); +#define radeon_engine_idle() _radeon_engine_idle() +#define radeon_fifo_wait(entries) _radeon_fifo_wait(entries) +/* Flush all dirty data in the Pixel Cache to memory. */ +static __inline__ void radeon_engine_flush ( void ) +{ + unsigned i; + + OUTREGP(PC_NGUI_CTLSTAT, PC_FLUSH_ALL, ~PC_FLUSH_ALL); + for (i = 0; i < 2000000; i++) { + if (!(INREG(PC_NGUI_CTLSTAT) & PC_BUSY)) break; + } +} + +/* Reset graphics card to known state. */ +static void radeon_engine_reset( void ) +{ + uint32_t clock_cntl_index; + uint32_t mclk_cntl; + uint32_t gen_reset_cntl; + + radeon_engine_flush(); + + clock_cntl_index = INREG(CLOCK_CNTL_INDEX); + mclk_cntl = INPLL(MCLK_CNTL); + + OUTPLL(MCLK_CNTL, mclk_cntl | FORCE_GCP | FORCE_PIPE3D_CP); + + gen_reset_cntl = INREG(GEN_RESET_CNTL); + + OUTREG(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI); + INREG(GEN_RESET_CNTL); + OUTREG(GEN_RESET_CNTL, + gen_reset_cntl & (uint32_t)(~SOFT_RESET_GUI)); + INREG(GEN_RESET_CNTL); + + OUTPLL(MCLK_CNTL, mclk_cntl); + OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index); + OUTREG(GEN_RESET_CNTL, gen_reset_cntl); +} +#else + +static __inline__ void radeon_engine_flush ( void ) +{ + int i; + + /* initiate flush */ + OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL, + ~RB2D_DC_FLUSH_ALL); + + for (i=0; i < 2000000; i++) { + if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY)) + break; + } +} + +static void _radeon_engine_idle(void); +static void _radeon_fifo_wait(unsigned); +#define radeon_engine_idle() _radeon_engine_idle() +#define radeon_fifo_wait(entries) _radeon_fifo_wait(entries) + +static void radeon_engine_reset( void ) +{ + uint32_t clock_cntl_index, mclk_cntl, rbbm_soft_reset; + + radeon_engine_flush (); + + clock_cntl_index = INREG(CLOCK_CNTL_INDEX); + mclk_cntl = INPLL(MCLK_CNTL); + + OUTPLL(MCLK_CNTL, (mclk_cntl | + FORCEON_MCLKA | + FORCEON_MCLKB | + FORCEON_YCLKA | + FORCEON_YCLKB | + FORCEON_MC | + FORCEON_AIC)); + rbbm_soft_reset = INREG(RBBM_SOFT_RESET); + + OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset | + SOFT_RESET_CP | + SOFT_RESET_HI | + SOFT_RESET_SE | + SOFT_RESET_RE | + SOFT_RESET_PP | + SOFT_RESET_E2 | + SOFT_RESET_RB | + SOFT_RESET_HDP); + INREG(RBBM_SOFT_RESET); + OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (uint32_t) + ~(SOFT_RESET_CP | + SOFT_RESET_HI | + SOFT_RESET_SE | + SOFT_RESET_RE | + SOFT_RESET_PP | + SOFT_RESET_E2 | + SOFT_RESET_RB | + SOFT_RESET_HDP)); + INREG(RBBM_SOFT_RESET); + + OUTPLL(MCLK_CNTL, mclk_cntl); + OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index); + OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset); + + return; +} +#endif +static void radeon_engine_restore( void ) +{ +#ifndef RAGE128 + int pitch64; + uint32_t xres,yres,bpp; + radeon_fifo_wait(1); + xres = radeon_get_xres(); + yres = radeon_get_yres(); + bpp = radeon_vid_get_dbpp(); + /* turn of all automatic flushing - we'll do it all */ + OUTREG(RB2D_DSTCACHE_MODE, 0); + + pitch64 = ((xres * (bpp / 8) + 0x3f)) >> 6; + + radeon_fifo_wait(1); + OUTREG(DEFAULT_OFFSET, (INREG(DEFAULT_OFFSET) & 0xC0000000) | + (pitch64 << 22)); + + radeon_fifo_wait(1); +#if defined(WORDS_BIGENDIAN) +#ifdef RADEON + OUTREGP(DP_DATATYPE, HOST_BIG_ENDIAN_EN, ~HOST_BIG_ENDIAN_EN); +#endif +#else + OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN); +#endif + + radeon_fifo_wait(1); + OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX + | DEFAULT_SC_BOTTOM_MAX)); + radeon_fifo_wait(1); + OUTREG(DP_GUI_MASTER_CNTL, (INREG(DP_GUI_MASTER_CNTL) + | GMC_BRUSH_SOLID_COLOR + | GMC_SRC_DATATYPE_COLOR)); + + radeon_fifo_wait(7); + OUTREG(DST_LINE_START, 0); + OUTREG(DST_LINE_END, 0); + OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff); + OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000); + OUTREG(DP_SRC_FRGD_CLR, 0xffffffff); + OUTREG(DP_SRC_BKGD_CLR, 0x00000000); + OUTREG(DP_WRITE_MASK, 0xffffffff); + + radeon_engine_idle(); +#endif +} +#ifdef RAGE128 +static void _radeon_fifo_wait (unsigned entries) +{ + unsigned i; + + for(;;) + { + for (i=0; i<2000000; i++) + if ((INREG(GUI_STAT) & GUI_FIFOCNT_MASK) >= entries) + return; + radeon_engine_reset(); + radeon_engine_restore(); + } +} + +static void _radeon_engine_idle ( void ) +{ + unsigned i; + + /* ensure FIFO is empty before waiting for idle */ + radeon_fifo_wait (64); + for(;;) + { + for (i=0; i<2000000; i++) { + if ((INREG(GUI_STAT) & GUI_ACTIVE) == 0) { + radeon_engine_flush (); + return; + } + } + radeon_engine_reset(); + radeon_engine_restore(); + } +} +#else +static void _radeon_fifo_wait (unsigned entries) +{ + unsigned i; + + for(;;) + { + for (i=0; i<2000000; i++) + if ((INREG(RBBM_STATUS) & RBBM_FIFOCNT_MASK) >= entries) + return; + radeon_engine_reset(); + radeon_engine_restore(); + } +} +static void _radeon_engine_idle ( void ) +{ + int i; + + /* ensure FIFO is empty before waiting for idle */ + radeon_fifo_wait (64); + for(;;) + { + for (i=0; i<2000000; i++) { + if (((INREG(RBBM_STATUS) & RBBM_ACTIVE)) == 0) { + radeon_engine_flush (); + return; + } + } + radeon_engine_reset(); + radeon_engine_restore(); + } +} +#endif + +#ifndef RAGE128 +/* Reference color space transform data */ +typedef struct tagREF_TRANSFORM +{ + float RefLuma; + float RefRCb; + float RefRCr; + float RefGCb; + float RefGCr; + float RefBCb; + float RefBCr; +} REF_TRANSFORM; + +/* Parameters for ITU-R BT.601 and ITU-R BT.709 colour spaces */ +REF_TRANSFORM trans[2] = +{ + {1.1678, 0.0, 1.6007, -0.3929, -0.8154, 2.0232, 0.0}, /* BT.601 */ + {1.1678, 0.0, 1.7980, -0.2139, -0.5345, 2.1186, 0.0} /* BT.709 */ +}; +/**************************************************************************** + * SetTransform * + * Function: Calculates and sets color space transform from supplied * + * reference transform, gamma, brightness, contrast, hue and * + * saturation. * + * Inputs: bright - brightness * + * cont - contrast * + * sat - saturation * + * hue - hue * + * red_intensity - intense of red component * + * green_intensity - intense of green component * + * blue_intensity - intense of blue component * + * ref - index to the table of refernce transforms * + * Outputs: NONE * + ****************************************************************************/ + +static void radeon_set_transform(float bright, float cont, float sat, + float hue, float red_intensity, + float green_intensity,float blue_intensity, + unsigned ref) +{ + float OvHueSin, OvHueCos; + float CAdjLuma, CAdjOff; + float RedAdj,GreenAdj,BlueAdj; + float CAdjRCb, CAdjRCr; + float CAdjGCb, CAdjGCr; + float CAdjBCb, CAdjBCr; + float OvLuma, OvROff, OvGOff, OvBOff; + float OvRCb, OvRCr; + float OvGCb, OvGCr; + float OvBCb, OvBCr; + float Loff = 64.0; + float Coff = 512.0f; + + uint32_t dwOvLuma, dwOvROff, dwOvGOff, dwOvBOff; + uint32_t dwOvRCb, dwOvRCr; + uint32_t dwOvGCb, dwOvGCr; + uint32_t dwOvBCb, dwOvBCr; + + if (ref >= 2) return; + + OvHueSin = sin((double)hue); + OvHueCos = cos((double)hue); + + CAdjLuma = cont * trans[ref].RefLuma; + CAdjOff = cont * trans[ref].RefLuma * bright * 1023.0; + RedAdj = cont * trans[ref].RefLuma * red_intensity * 1023.0; + GreenAdj = cont * trans[ref].RefLuma * green_intensity * 1023.0; + BlueAdj = cont * trans[ref].RefLuma * blue_intensity * 1023.0; + + CAdjRCb = sat * -OvHueSin * trans[ref].RefRCr; + CAdjRCr = sat * OvHueCos * trans[ref].RefRCr; + CAdjGCb = sat * (OvHueCos * trans[ref].RefGCb - OvHueSin * trans[ref].RefGCr); + CAdjGCr = sat * (OvHueSin * trans[ref].RefGCb + OvHueCos * trans[ref].RefGCr); + CAdjBCb = sat * OvHueCos * trans[ref].RefBCb; + CAdjBCr = sat * OvHueSin * trans[ref].RefBCb; + +#if 0 /* default constants */ + CAdjLuma = 1.16455078125; + + CAdjRCb = 0.0; + CAdjRCr = 1.59619140625; + CAdjGCb = -0.39111328125; + CAdjGCr = -0.8125; + CAdjBCb = 2.01708984375; + CAdjBCr = 0; +#endif + OvLuma = CAdjLuma; + OvRCb = CAdjRCb; + OvRCr = CAdjRCr; + OvGCb = CAdjGCb; + OvGCr = CAdjGCr; + OvBCb = CAdjBCb; + OvBCr = CAdjBCr; + OvROff = RedAdj + CAdjOff - + OvLuma * Loff - (OvRCb + OvRCr) * Coff; + OvGOff = GreenAdj + CAdjOff - + OvLuma * Loff - (OvGCb + OvGCr) * Coff; + OvBOff = BlueAdj + CAdjOff - + OvLuma * Loff - (OvBCb + OvBCr) * Coff; +#if 0 /* default constants */ + OvROff = -888.5; + OvGOff = 545; + OvBOff = -1104; +#endif + + dwOvROff = ((int)(OvROff * 2.0)) & 0x1fff; + dwOvGOff = (int)(OvGOff * 2.0) & 0x1fff; + dwOvBOff = (int)(OvBOff * 2.0) & 0x1fff; + /* Whatever docs say about R200 having 3.8 format instead of 3.11 + as in Radeon is a lie */ +#if 0 + if(RadeonFamily == 100) + { +#endif + dwOvLuma =(((int)(OvLuma * 2048.0))&0x7fff)<<17; + dwOvRCb = (((int)(OvRCb * 2048.0))&0x7fff)<<1; + dwOvRCr = (((int)(OvRCr * 2048.0))&0x7fff)<<17; + dwOvGCb = (((int)(OvGCb * 2048.0))&0x7fff)<<1; + dwOvGCr = (((int)(OvGCr * 2048.0))&0x7fff)<<17; + dwOvBCb = (((int)(OvBCb * 2048.0))&0x7fff)<<1; + dwOvBCr = (((int)(OvBCr * 2048.0))&0x7fff)<<17; +#if 0 + } + else + { + dwOvLuma = (((int)(OvLuma * 256.0))&0x7ff)<<20; + dwOvRCb = (((int)(OvRCb * 256.0))&0x7ff)<<4; + dwOvRCr = (((int)(OvRCr * 256.0))&0x7ff)<<20; + dwOvGCb = (((int)(OvGCb * 256.0))&0x7ff)<<4; + dwOvGCr = (((int)(OvGCr * 256.0))&0x7ff)<<20; + dwOvBCb = (((int)(OvBCb * 256.0))&0x7ff)<<4; + dwOvBCr = (((int)(OvBCr * 256.0))&0x7ff)<<20; + } +#endif + OUTREG(OV0_LIN_TRANS_A, dwOvRCb | dwOvLuma); + OUTREG(OV0_LIN_TRANS_B, dwOvROff | dwOvRCr); + OUTREG(OV0_LIN_TRANS_C, dwOvGCb | dwOvLuma); + OUTREG(OV0_LIN_TRANS_D, dwOvGOff | dwOvGCr); + OUTREG(OV0_LIN_TRANS_E, dwOvBCb | dwOvLuma); + OUTREG(OV0_LIN_TRANS_F, dwOvBOff | dwOvBCr); +} + +/* Gamma curve definition */ +typedef struct +{ + unsigned int gammaReg; + unsigned int gammaSlope; + unsigned int gammaOffset; +}GAMMA_SETTINGS; + +/* Recommended gamma curve parameters */ +GAMMA_SETTINGS r200_def_gamma[18] = +{ + {OV0_GAMMA_0_F, 0x100, 0x0000}, + {OV0_GAMMA_10_1F, 0x100, 0x0020}, + {OV0_GAMMA_20_3F, 0x100, 0x0040}, + {OV0_GAMMA_40_7F, 0x100, 0x0080}, + {OV0_GAMMA_80_BF, 0x100, 0x0100}, + {OV0_GAMMA_C0_FF, 0x100, 0x0100}, + {OV0_GAMMA_100_13F, 0x100, 0x0200}, + {OV0_GAMMA_140_17F, 0x100, 0x0200}, + {OV0_GAMMA_180_1BF, 0x100, 0x0300}, + {OV0_GAMMA_1C0_1FF, 0x100, 0x0300}, + {OV0_GAMMA_200_23F, 0x100, 0x0400}, + {OV0_GAMMA_240_27F, 0x100, 0x0400}, + {OV0_GAMMA_280_2BF, 0x100, 0x0500}, + {OV0_GAMMA_2C0_2FF, 0x100, 0x0500}, + {OV0_GAMMA_300_33F, 0x100, 0x0600}, + {OV0_GAMMA_340_37F, 0x100, 0x0600}, + {OV0_GAMMA_380_3BF, 0x100, 0x0700}, + {OV0_GAMMA_3C0_3FF, 0x100, 0x0700} +}; + +GAMMA_SETTINGS r100_def_gamma[6] = +{ + {OV0_GAMMA_0_F, 0x100, 0x0000}, + {OV0_GAMMA_10_1F, 0x100, 0x0020}, + {OV0_GAMMA_20_3F, 0x100, 0x0040}, + {OV0_GAMMA_40_7F, 0x100, 0x0080}, + {OV0_GAMMA_380_3BF, 0x100, 0x0100}, + {OV0_GAMMA_3C0_3FF, 0x100, 0x0100} +}; + +static void make_default_gamma_correction( void ) +{ + size_t i; + if(RadeonFamily == 100) { + OUTREG(OV0_LIN_TRANS_A, 0x12A00000); + OUTREG(OV0_LIN_TRANS_B, 0x199018FE); + OUTREG(OV0_LIN_TRANS_C, 0x12A0F9B0); + OUTREG(OV0_LIN_TRANS_D, 0xF2F0043B); + OUTREG(OV0_LIN_TRANS_E, 0x12A02050); + OUTREG(OV0_LIN_TRANS_F, 0x0000174E); + for(i=0; i<6; i++){ + OUTREG(r100_def_gamma[i].gammaReg, + (r100_def_gamma[i].gammaSlope<<16) | + r100_def_gamma[i].gammaOffset); + } + } + else{ + OUTREG(OV0_LIN_TRANS_A, 0x12a00000); + OUTREG(OV0_LIN_TRANS_B, 0x1990190e); + OUTREG(OV0_LIN_TRANS_C, 0x12a0f9c0); + OUTREG(OV0_LIN_TRANS_D, 0xf3000442); + OUTREG(OV0_LIN_TRANS_E, 0x12a02040); + OUTREG(OV0_LIN_TRANS_F, 0x175f); + + /* Default Gamma, + Of 18 segments for gamma cure, all segments in R200 are programmable, + while only lower 4 and upper 2 segments are programmable in Radeon*/ + for(i=0; i<18; i++){ + OUTREG(r200_def_gamma[i].gammaReg, + (r200_def_gamma[i].gammaSlope<<16) | + r200_def_gamma[i].gammaOffset); + } + } +} +#endif + +static void radeon_vid_make_default(void) +{ +#ifdef RAGE128 + OUTREG(OV0_COLOUR_CNTL,0x00101000UL); /* Default brightness and saturation for Rage128 */ +#else + make_default_gamma_correction(); +#endif + besr.deinterlace_pattern = 0x900AAAAA; + OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); + besr.deinterlace_on=1; + besr.double_buff=1; + besr.ckey_on=0; + besr.graphics_key_msk=0; + besr.graphics_key_clr=0; + besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_TRUE|CMP_MIX_AND; +} + + +unsigned vixGetVersion( void ) { return VIDIX_VERSION; } + +static unsigned short ati_card_ids[] = +{ +#ifdef RAGE128 + /* + This driver should be compatible with Rage128 (pro) chips. + (include adaptive deinterlacing!!!). + Moreover: the same logic can be used with Mach64 chips. + (I mean: mach64xx, 3d rage, 3d rage IIc, 3D rage pro, 3d rage mobility). + but they are incompatible by i/o ports. So if enthusiasts will want + then they can redefine OUTREG and INREG macros and redefine OV0_* + constants. Also it seems that mach64 chips supports only: YUY2, YV12, UYVY + fourccs (422 and 420 formats only). + */ +/* Rage128 Pro GL */ + DEVICE_ATI_RAGE_128_PA_PRO, + DEVICE_ATI_RAGE_128_PB_PRO, + DEVICE_ATI_RAGE_128_PC_PRO, + DEVICE_ATI_RAGE_128_PD_PRO, + DEVICE_ATI_RAGE_128_PE_PRO, + DEVICE_ATI_RAGE_128_PF_PRO, +/* Rage128 Pro VR */ + DEVICE_ATI_RAGE_128_PG_PRO, + DEVICE_ATI_RAGE_128_PH_PRO, + DEVICE_ATI_RAGE_128_PI_PRO, + DEVICE_ATI_RAGE_128_PJ_PRO, + DEVICE_ATI_RAGE_128_PK_PRO, + DEVICE_ATI_RAGE_128_PL_PRO, + DEVICE_ATI_RAGE_128_PM_PRO, + DEVICE_ATI_RAGE_128_PN_PRO, + DEVICE_ATI_RAGE_128_PO_PRO, + DEVICE_ATI_RAGE_128_PP_PRO, + DEVICE_ATI_RAGE_128_PQ_PRO, + DEVICE_ATI_RAGE_128_PR_PRO, + DEVICE_ATI_RAGE_128_PS_PRO, + DEVICE_ATI_RAGE_128_PT_PRO, + DEVICE_ATI_RAGE_128_PU_PRO, + DEVICE_ATI_RAGE_128_PV_PRO, + DEVICE_ATI_RAGE_128_PW_PRO, + DEVICE_ATI_RAGE_128_PX_PRO, +/* Rage128 GL */ + DEVICE_ATI_RAGE_128_RE_SG, + DEVICE_ATI_RAGE_128_RF_SG, + DEVICE_ATI_RAGE_128_RG, + DEVICE_ATI_RAGE_128_RK_VR, + DEVICE_ATI_RAGE_128_RL_VR, + DEVICE_ATI_RAGE_128_SE_4X, + DEVICE_ATI_RAGE_128_SF_4X, + DEVICE_ATI_RAGE_128_SG_4X, + DEVICE_ATI_RAGE_128_SH, + DEVICE_ATI_RAGE_128_SK_4X, + DEVICE_ATI_RAGE_128_SL_4X, + DEVICE_ATI_RAGE_128_SM_4X, + DEVICE_ATI_RAGE_128_4X, + DEVICE_ATI_RAGE_128_PRO, + DEVICE_ATI_RAGE_128_PRO2, + DEVICE_ATI_RAGE_128_PRO3, +/* these seem to be based on rage 128 instead of mach64 */ + DEVICE_ATI_RAGE_MOBILITY_M3, + DEVICE_ATI_RAGE_MOBILITY_M32 +#else +/* Radeons (indeed: Rage 256 Pro ;) */ + DEVICE_ATI_RADEON_R100_QD, + DEVICE_ATI_RADEON_R100_QE, + DEVICE_ATI_RADEON_R100_QF, + DEVICE_ATI_RADEON_R100_QG, + DEVICE_ATI_RADEON_VE_QY, + DEVICE_ATI_RADEON_VE_QZ, + DEVICE_ATI_RADEON_MOBILITY_M7, + DEVICE_ATI_RADEON_MOBILITY_M72, + DEVICE_ATI_RADEON_MOBILITY_M6, + DEVICE_ATI_RADEON_MOBILITY_M62, + DEVICE_ATI_RADEON_MOBILITY_U1, + DEVICE_ATI_RADEON_R200_BB, + DEVICE_ATI_RADEON_R200_QH, + DEVICE_ATI_RADEON_R200_QI, + DEVICE_ATI_RADEON_R200_QJ, + DEVICE_ATI_RADEON_R200_QK, + DEVICE_ATI_RADEON_R200_QL, + DEVICE_ATI_RADEON_R200_QM, + DEVICE_ATI_RADEON_R200_QH2, + DEVICE_ATI_RADEON_R200_QI2, + DEVICE_ATI_RADEON_R200_QJ2, + DEVICE_ATI_RADEON_R200_QK2, + DEVICE_ATI_RADEON_RV200_QW, + DEVICE_ATI_RADEON_RV200_QX, + DEVICE_ATI_RADEON_R250_ID, + DEVICE_ATI_RADEON_R250_IE, + DEVICE_ATI_RADEON_R250_IF, + DEVICE_ATI_RADEON_R250_IG, + DEVICE_ATI_RADEON_R250_LD, + DEVICE_ATI_RADEON_R250_LE, + DEVICE_ATI_RADEON_R250_LF, + DEVICE_ATI_RADEON_R250_LG, + DEVICE_ATI_RV370_5B60_RADEON, + DEVICE_ATI_RV250_5C61_RADEON, + DEVICE_ATI_RV250_5C63_RADEON, + DEVICE_ATI_RV280_RADEON_9200, + DEVICE_ATI_RV280_RADEON_92002, + DEVICE_ATI_RV280_RADEON_92003, + DEVICE_ATI_RV280_RADEON_92004, + DEVICE_ATI_RV280_RADEON_92005, + DEVICE_ATI_RV280_RADEON_92006, + DEVICE_ATI_RADEON_R300_ND, + DEVICE_ATI_RADEON_R300_NE, + DEVICE_ATI_RADEON_R300_NF, + DEVICE_ATI_RADEON_R300_NG, + DEVICE_ATI_RADEON_R300_AE, + DEVICE_ATI_RADEON_R300_AF, + DEVICE_ATI_RADEON_RV350_AP, + DEVICE_ATI_RADEON_RV350_AQ, + DEVICE_ATI_RADEON_RV350_AR, + DEVICE_ATI_RADEON_RV350_BK, + DEVICE_ATI_RADEON_R350_AH, + DEVICE_ATI_RADEON_R350_AI, + DEVICE_ATI_RADEON_R350_NH, + DEVICE_ATI_RADEON_R360_NJ, + DEVICE_ATI_RV350_MOBILITY_RADEON, + DEVICE_ATI_RV350_MOBILITY_RADEON2 +#endif +}; + +static int find_chip(unsigned chip_id) +{ + unsigned i; + for(i = 0;i < sizeof(ati_card_ids)/sizeof(unsigned short);i++) + { + if(chip_id == ati_card_ids[i]) return i; + } + return -1; +} + +static pciinfo_t pci_info; +static int probed=0; + +vidix_capability_t def_cap = +{ +#ifdef RAGE128 + "BES driver for Rage128 cards", +#else + "BES driver for Radeon cards", +#endif + "Nick Kurshev", + TYPE_OUTPUT | TYPE_FX, + { 0, 0, 0, 0 }, + 2048, + 2048, + 4, + 4, + -1, + FLAG_UPSCALER | FLAG_DOWNSCALER | FLAG_EQUALIZER, + VENDOR_ATI, + 0, + { 0, 0, 0, 0} +}; + +#ifdef HAVE_X11 +static void probe_fireGL_driver(void) { + Display *dp = XOpenDisplay ((void*)0); + int n = 0; + char **extlist; + if (dp==NULL) { + return; + } + extlist = XListExtensions (dp, &n); + XCloseDisplay (dp); + if (extlist) { + int i; + int ext_fgl = 0, ext_fglrx = 0; + for (i = 0; i < n; i++) { + if (!strcmp(extlist[i], "ATIFGLEXTENSION")) ext_fgl = 1; + if (!strcmp(extlist[i], "ATIFGLRXDRI")) ext_fglrx = 1; + } + if (ext_fgl) { + printf(RADEON_MSG" ATI FireGl driver detected"); + firegl_shift = 0x500000; + if (!ext_fglrx) { + printf(", but DRI seems not to be activated\n"); + printf(RADEON_MSG" Output may not work correctly, check your DRI configuration!"); + } + printf("\n"); + } + } +} +#endif + +int vixProbe( int verbose,int force ) +{ + pciinfo_t lst[MAX_PCI_DEVICES]; + unsigned i,num_pci; + int err; + __verbose = verbose; + err = pci_scan(lst,&num_pci); + if(err) + { + printf(RADEON_MSG" Error occurred during pci scan: %s\n",strerror(err)); + return err; + } + else + { + err = ENXIO; + for(i=0;i<num_pci;i++) + { + if(lst[i].vendor == VENDOR_ATI) + { + int idx; + const char *dname; + idx = find_chip(lst[i].device); + if(idx == -1 && force == PROBE_NORMAL) continue; + dname = pci_device_name(VENDOR_ATI,lst[i].device); + dname = dname ? dname : "Unknown chip"; + printf(RADEON_MSG" Found chip: %s\n",dname); +#if 0 + if ((lst[i].command & PCI_COMMAND_IO) == 0) + { + printf("[radeon] Device is disabled, ignoring\n"); + continue; + } +#endif +#ifndef RAGE128 + if(idx != -1) +#ifdef HAVE_X11 + probe_fireGL_driver(); +#endif + { + switch(ati_card_ids[idx]) { + /* Original radeon */ + case DEVICE_ATI_RADEON_R100_QD: + case DEVICE_ATI_RADEON_R100_QE: + case DEVICE_ATI_RADEON_R100_QF: + case DEVICE_ATI_RADEON_R100_QG: + RadeonFamily = 100; + break; + + /* Radeon VE / Radeon Mobility */ + case DEVICE_ATI_RADEON_VE_QY: + case DEVICE_ATI_RADEON_VE_QZ: + case DEVICE_ATI_RADEON_MOBILITY_M6: + case DEVICE_ATI_RADEON_MOBILITY_M62: + case DEVICE_ATI_RADEON_MOBILITY_U1: + RadeonFamily = 120; + break; + + /* Radeon 7500 / Radeon Mobility 7500 */ + case DEVICE_ATI_RADEON_RV200_QW: + case DEVICE_ATI_RADEON_RV200_QX: + case DEVICE_ATI_RADEON_MOBILITY_M7: + case DEVICE_ATI_RADEON_MOBILITY_M72: + RadeonFamily = 150; + break; + + /* Radeon 8500 */ + case DEVICE_ATI_RADEON_R200_BB: + case DEVICE_ATI_RADEON_R200_QH: + case DEVICE_ATI_RADEON_R200_QI: + case DEVICE_ATI_RADEON_R200_QJ: + case DEVICE_ATI_RADEON_R200_QK: + case DEVICE_ATI_RADEON_R200_QL: + case DEVICE_ATI_RADEON_R200_QM: + case DEVICE_ATI_RADEON_R200_QH2: + case DEVICE_ATI_RADEON_R200_QI2: + case DEVICE_ATI_RADEON_R200_QJ2: + case DEVICE_ATI_RADEON_R200_QK2: + RadeonFamily = 200; + break; + + /* Radeon 9000 */ + case DEVICE_ATI_RADEON_R250_ID: + case DEVICE_ATI_RADEON_R250_IE: + case DEVICE_ATI_RADEON_R250_IF: + case DEVICE_ATI_RADEON_R250_IG: + case DEVICE_ATI_RADEON_R250_LD: + case DEVICE_ATI_RADEON_R250_LE: + case DEVICE_ATI_RADEON_R250_LF: + case DEVICE_ATI_RADEON_R250_LG: + case DEVICE_ATI_RV250_5C61_RADEON: + case DEVICE_ATI_RV250_5C63_RADEON: + RadeonFamily = 250; + break; + + /* Radeon 9200 */ + case DEVICE_ATI_RV280_RADEON_9200: + case DEVICE_ATI_RV280_RADEON_92002: + case DEVICE_ATI_RV280_RADEON_92003: + case DEVICE_ATI_RV280_RADEON_92004: + case DEVICE_ATI_RV280_RADEON_92005: + case DEVICE_ATI_RV280_RADEON_92006: + RadeonFamily = 280; + break; + + /* Radeon 9700 */ + case DEVICE_ATI_RADEON_R300_ND: + case DEVICE_ATI_RADEON_R300_NE: + case DEVICE_ATI_RADEON_R300_NF: + case DEVICE_ATI_RADEON_R300_NG: + case DEVICE_ATI_RADEON_R300_AE: + case DEVICE_ATI_RADEON_R300_AF: + RadeonFamily = 300; + break; + + /* Radeon 9600/9800 */ + case DEVICE_ATI_RV370_5B60_RADEON: + case DEVICE_ATI_RADEON_RV350_AP: + case DEVICE_ATI_RADEON_RV350_AQ: + case DEVICE_ATI_RADEON_RV350_AR: + case DEVICE_ATI_RADEON_RV350_BK: + case DEVICE_ATI_RADEON_R350_NH: + case DEVICE_ATI_RADEON_R350_AH: + case DEVICE_ATI_RADEON_R350_AI: + case DEVICE_ATI_RADEON_R360_NJ: + case DEVICE_ATI_RV350_MOBILITY_RADEON: + case DEVICE_ATI_RV350_MOBILITY_RADEON2: + RadeonFamily = 350; + break; + + default: + break; + } + } +#endif + if(force > PROBE_NORMAL) + { + printf(RADEON_MSG" Driver was forced. Was found %sknown chip\n",idx == -1 ? "un" : ""); + if(idx == -1) +#ifdef RAGE128 + printf(RADEON_MSG" Assuming it as Rage128\n"); +#else + printf(RADEON_MSG" Assuming it as Radeon1\n"); +#endif + } + def_cap.device_id = lst[i].device; + err = 0; + memcpy(&pci_info,&lst[i],sizeof(pciinfo_t)); + probed=1; + break; + } + } + } + if(err && verbose) printf(RADEON_MSG" Can't find chip\n"); + return err; +} + +static void radeon_vid_dump_regs( void ); /* forward declaration */ + +int vixInit( void ) +{ + int err; + if(!probed) + { + printf(RADEON_MSG" Driver was not probed but is being initializing\n"); + return EINTR; + } + if((radeon_mmio_base = map_phys_mem(pci_info.base2,0xFFFF))==(void *)-1) return ENOMEM; + radeon_ram_size = INREG(CONFIG_MEMSIZE); + /* mem size is bits [28:0], mask off the rest. Range: from 1Mb up to 512 Mb */ + radeon_ram_size &= CONFIG_MEMSIZE_MASK; +#ifdef RADEON + /* according to XFree86 4.2.0, some production M6's return 0 for 8MB */ + if (radeon_ram_size == 0 && + (def_cap.device_id == DEVICE_ATI_RADEON_MOBILITY_M6 || + def_cap.device_id == DEVICE_ATI_RADEON_MOBILITY_M62)) + { + printf(RADEON_MSG" Workarounding buggy Radeon Mobility M6 (0 vs. 8MB ram)\n"); + radeon_ram_size = 8192*1024; + } +#else + /* Rage Mobility (rage128) also has memsize bug */ + if (radeon_ram_size == 0 && + (def_cap.device_id == DEVICE_ATI_RAGE_MOBILITY_M3 || + def_cap.device_id == DEVICE_ATI_RAGE_128_RL_VR || + def_cap.device_id == DEVICE_ATI_RAGE_MOBILITY_M32)) + { + printf(RADEON_MSG" Workarounding buggy Rage Mobility M3 (0 vs. 8MB ram)\n"); + radeon_ram_size = 8192*1024; + } +#endif + printf(RADEON_MSG" Video memory = %uMb\n",radeon_ram_size/0x100000); +#ifdef WIN32 + //mapping large areas of video ram will fail on windows + if(radeon_ram_size > 16*1024*1024)radeon_ram_size=16*1024*1024; +#endif + if((radeon_mem_base = map_phys_mem(pci_info.base0,radeon_ram_size))==(void *)-1) return ENOMEM; + memset(&besr,0,sizeof(bes_registers_t)); + radeon_vid_make_default(); + err = mtrr_set_type(pci_info.base0,radeon_ram_size,MTRR_TYPE_WRCOMB); + if(!err) printf(RADEON_MSG" Set write-combining type of video memory\n"); + + radeon_fifo_wait(3); + SAVED_OV0_GRAPHICS_KEY_CLR = INREG(OV0_GRAPHICS_KEY_CLR); + SAVED_OV0_GRAPHICS_KEY_MSK = INREG(OV0_GRAPHICS_KEY_MSK); + SAVED_OV0_VID_KEY_CLR = INREG(OV0_VID_KEY_CLR); + SAVED_OV0_VID_KEY_MSK = INREG(OV0_VID_KEY_MSK); + SAVED_OV0_KEY_CNTL = INREG(OV0_KEY_CNTL); + printf(RADEON_MSG" Saved overlay colorkey settings\n"); + +#ifdef RADEON + switch(RadeonFamily) + { + case 100: + case 120: + case 150: + case 250: + case 280: + is_shift_required=1; + break; + default: + break; + } +#endif + +/* XXX: hack, but it works for me (tm) */ +#ifdef WORDS_BIGENDIAN +#if defined(RAGE128) + /* code from gatos */ + { + SAVED_CONFIG_CNTL = INREG(CONFIG_CNTL); + OUTREG(CONFIG_CNTL, SAVED_CONFIG_CNTL & + ~(APER_0_BIG_ENDIAN_16BPP_SWAP|APER_0_BIG_ENDIAN_32BPP_SWAP)); + +// printf("saved: %x, current: %x\n", SAVED_CONFIG_CNTL, +// INREG(CONFIG_CNTL)); + } +#else + /*code from radeon_video.c*/ + { + SAVED_CONFIG_CNTL = INREG(RADEON_SURFACE_CNTL); +/* OUTREG(RADEON_SURFACE_CNTL, (SAVED_CONFIG_CNTL | + RADEON_NONSURF_AP0_SWP_32BPP) & ~RADEON_NONSURF_AP0_SWP_16BPP); +*/ + OUTREG(RADEON_SURFACE_CNTL, SAVED_CONFIG_CNTL & ~(RADEON_NONSURF_AP0_SWP_32BPP + | RADEON_NONSURF_AP0_SWP_16BPP)); + +/* + OUTREG(RADEON_SURFACE_CNTL, (SAVED_CONFIG_CNTL | RADEON_NONSURF_AP0_SWP_32BPP) + & ~RADEON_NONSURF_AP0_SWP_16BPP); +*/ + } +#endif +#endif + + if(__verbose > 1) radeon_vid_dump_regs(); + return 0; +} + +void vixDestroy( void ) +{ + /* remove colorkeying */ + radeon_fifo_wait(3); + OUTREG(OV0_GRAPHICS_KEY_CLR, SAVED_OV0_GRAPHICS_KEY_CLR); + OUTREG(OV0_GRAPHICS_KEY_MSK, SAVED_OV0_GRAPHICS_KEY_MSK); + OUTREG(OV0_VID_KEY_CLR, SAVED_OV0_VID_KEY_CLR); + OUTREG(OV0_VID_KEY_MSK, SAVED_OV0_VID_KEY_MSK); + OUTREG(OV0_KEY_CNTL, SAVED_OV0_KEY_CNTL); + printf(RADEON_MSG" Restored overlay colorkey settings\n"); + +#ifdef WORDS_BIGENDIAN +#if defined(RAGE128) + OUTREG(CONFIG_CNTL, SAVED_CONFIG_CNTL); +// printf("saved: %x, restored: %x\n", SAVED_CONFIG_CNTL, +// INREG(CONFIG_CNTL)); +#else + OUTREG(RADEON_SURFACE_CNTL, SAVED_CONFIG_CNTL); +#endif +#endif + + unmap_phys_mem(radeon_mem_base,radeon_ram_size); + unmap_phys_mem(radeon_mmio_base,0xFFFF); +} + +int vixGetCapability(vidix_capability_t *to) +{ + memcpy(to,&def_cap,sizeof(vidix_capability_t)); + return 0; +} + +/* + Full list of fourcc which are supported by Win2K redeon driver: + YUY2, UYVY, DDES, OGLT, OGL2, OGLS, OGLB, OGNT, OGNZ, OGNS, + IF09, YVU9, IMC4, M2IA, IYUV, VBID, DXT1, DXT2, DXT3, DXT4, DXT5 +*/ +uint32_t supported_fourcc[] = +{ + IMGFMT_Y800, IMGFMT_Y8, IMGFMT_YVU9, IMGFMT_IF09, + IMGFMT_YV12, IMGFMT_I420, IMGFMT_IYUV, + IMGFMT_UYVY, IMGFMT_YUY2, IMGFMT_YVYU, + IMGFMT_RGB15, IMGFMT_BGR15, + IMGFMT_RGB16, IMGFMT_BGR16, + IMGFMT_RGB32, IMGFMT_BGR32 +}; + +inline static int is_supported_fourcc(uint32_t fourcc) +{ + unsigned int i; + for(i=0;i<sizeof(supported_fourcc)/sizeof(uint32_t);i++) + { + if(fourcc==supported_fourcc[i]) return 1; + } + return 0; +} + +int vixQueryFourcc(vidix_fourcc_t *to) +{ + if(is_supported_fourcc(to->fourcc)) + { + to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | + VID_DEPTH_4BPP | VID_DEPTH_8BPP | + VID_DEPTH_12BPP| VID_DEPTH_15BPP| + VID_DEPTH_16BPP| VID_DEPTH_24BPP| + VID_DEPTH_32BPP; + to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; + return 0; + } + else to->depth = to->flags = 0; + return ENOSYS; +} + +static void radeon_vid_dump_regs( void ) +{ + size_t i; + printf(RADEON_MSG"*** Begin of DRIVER variables dump ***\n"); + printf(RADEON_MSG"radeon_mmio_base=%p\n",radeon_mmio_base); + printf(RADEON_MSG"radeon_mem_base=%p\n",radeon_mem_base); + printf(RADEON_MSG"radeon_overlay_off=%08X\n",radeon_overlay_off); + printf(RADEON_MSG"radeon_ram_size=%08X\n",radeon_ram_size); + printf(RADEON_MSG"video mode: %ux%u@%u\n",radeon_get_xres(),radeon_get_yres(),radeon_vid_get_dbpp()); + printf(RADEON_MSG"flatpanel size: %ux%u\n",radeon_get_fp_xres(),radeon_get_fp_yres()); + printf(RADEON_MSG"*** Begin of OV0 registers dump ***\n"); + for(i=0;i<sizeof(vregs)/sizeof(video_registers_t);i++) + printf(RADEON_MSG"%s = %08X\n",vregs[i].sname,INREG(vregs[i].name)); + printf(RADEON_MSG"*** End of OV0 registers dump ***\n"); +} + +static void radeon_vid_stop_video( void ) +{ + radeon_engine_idle(); + OUTREG(OV0_SCALE_CNTL, SCALER_SOFT_RESET); + OUTREG(OV0_EXCLUSIVE_HORZ, 0); + OUTREG(OV0_AUTO_FLIP_CNTL, 0); /* maybe */ + OUTREG(OV0_FILTER_CNTL, FILTER_HARDCODED_COEF); +#ifdef RADEON + OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_EQ); +#else + OUTREG(OV0_KEY_CNTL, GRAPHIC_KEY_FN_NE); +#endif + OUTREG(OV0_TEST, 0); +} + +static void radeon_vid_display_video( void ) +{ + int bes_flags; + /** workaround for Xorg-6.8 not saving the surface registers on bigendian architectures */ +#ifdef WORDS_BIGENDIAN +#if defined(RAGE128) + /* code from gatos */ + { + SAVED_CONFIG_CNTL = INREG(CONFIG_CNTL); + OUTREG(CONFIG_CNTL, SAVED_CONFIG_CNTL & + ~(APER_0_BIG_ENDIAN_16BPP_SWAP|APER_0_BIG_ENDIAN_32BPP_SWAP)); + +// printf("saved: %x, current: %x\n", SAVED_CONFIG_CNTL, +// INREG(CONFIG_CNTL)); + } +#else + /*code from radeon_video.c*/ + { + SAVED_CONFIG_CNTL = INREG(RADEON_SURFACE_CNTL); +/* OUTREG(RADEON_SURFACE_CNTL, (SAVED_CONFIG_CNTL | + RADEON_NONSURF_AP0_SWP_32BPP) & ~RADEON_NONSURF_AP0_SWP_16BPP); +*/ + OUTREG(RADEON_SURFACE_CNTL, SAVED_CONFIG_CNTL & ~(RADEON_NONSURF_AP0_SWP_32BPP + | RADEON_NONSURF_AP0_SWP_16BPP)); + +/* + OUTREG(RADEON_SURFACE_CNTL, (SAVED_CONFIG_CNTL | RADEON_NONSURF_AP0_SWP_32BPP) + & ~RADEON_NONSURF_AP0_SWP_16BPP); +*/ + } +#endif +#endif + + + + radeon_fifo_wait(2); + OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); + radeon_engine_idle(); + while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); + radeon_fifo_wait(15); + + /* Shutdown capturing */ + OUTREG(FCP_CNTL, FCP_CNTL__GND); + OUTREG(CAP0_TRIG_CNTL, 0); + + OUTREG(VID_BUFFER_CONTROL, (1<<16) | 0x01); + OUTREG(DISP_TEST_DEBUG_CNTL, 0); + + OUTREG(OV0_AUTO_FLIP_CNTL,OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD); + + if(besr.deinterlace_on) OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); +#ifdef RAGE128 + OUTREG(OV0_COLOUR_CNTL, (((besr.brightness*64)/1000) & 0x7f) | + (((besr.saturation*31+31000)/2000) << 8) | + (((besr.saturation*31+31000)/2000) << 16)); +#endif + radeon_fifo_wait(2); + OUTREG(OV0_GRAPHICS_KEY_MSK, besr.graphics_key_msk); + OUTREG(OV0_GRAPHICS_KEY_CLR, besr.graphics_key_clr); + OUTREG(OV0_KEY_CNTL,besr.ckey_cntl); + + OUTREG(OV0_H_INC, besr.h_inc); + OUTREG(OV0_STEP_BY, besr.step_by); + OUTREG(OV0_Y_X_START, besr.y_x_start); + OUTREG(OV0_Y_X_END, besr.y_x_end); + OUTREG(OV0_V_INC, besr.v_inc); + OUTREG(OV0_P1_BLANK_LINES_AT_TOP, besr.p1_blank_lines_at_top); + OUTREG(OV0_P23_BLANK_LINES_AT_TOP, besr.p23_blank_lines_at_top); + OUTREG(OV0_VID_BUF_PITCH0_VALUE, besr.vid_buf_pitch0_value); + OUTREG(OV0_VID_BUF_PITCH1_VALUE, besr.vid_buf_pitch1_value); + OUTREG(OV0_P1_X_START_END, besr.p1_x_start_end); + OUTREG(OV0_P2_X_START_END, besr.p2_x_start_end); + OUTREG(OV0_P3_X_START_END, besr.p3_x_start_end); +#ifdef RADEON + OUTREG(OV0_BASE_ADDR, besr.base_addr); +#endif + OUTREG(OV0_VID_BUF0_BASE_ADRS, besr.vid_buf_base_adrs_y[0]); + OUTREG(OV0_VID_BUF1_BASE_ADRS, besr.vid_buf_base_adrs_v[0]); + OUTREG(OV0_VID_BUF2_BASE_ADRS, besr.vid_buf_base_adrs_u[0]); + radeon_fifo_wait(9); + OUTREG(OV0_VID_BUF3_BASE_ADRS, besr.vid_buf_base_adrs_y[0]); + OUTREG(OV0_VID_BUF4_BASE_ADRS, besr.vid_buf_base_adrs_v[0]); + OUTREG(OV0_VID_BUF5_BASE_ADRS, besr.vid_buf_base_adrs_u[0]); + OUTREG(OV0_P1_V_ACCUM_INIT, besr.p1_v_accum_init); + OUTREG(OV0_P1_H_ACCUM_INIT, besr.p1_h_accum_init); + OUTREG(OV0_P23_H_ACCUM_INIT, besr.p23_h_accum_init); + OUTREG(OV0_P23_V_ACCUM_INIT, besr.p23_v_accum_init); + +#ifdef RADEON + bes_flags = SCALER_ENABLE | + SCALER_SMART_SWITCH; +// SCALER_HORZ_PICK_NEAREST | +// SCALER_VERT_PICK_NEAREST | +#endif + bes_flags = SCALER_ENABLE | + SCALER_SMART_SWITCH | + SCALER_Y2R_TEMP | + SCALER_PIX_EXPAND; + if(besr.double_buff) bes_flags |= SCALER_DOUBLE_BUFFER; + if(besr.deinterlace_on) bes_flags |= SCALER_ADAPTIVE_DEINT; +#ifdef RAGE128 + bes_flags |= SCALER_BURST_PER_PLANE; +#endif + switch(besr.fourcc) + { + case IMGFMT_RGB15: + case IMGFMT_BGR15: bes_flags |= SCALER_SOURCE_15BPP; break; + case IMGFMT_RGB16: + case IMGFMT_BGR16: bes_flags |= SCALER_SOURCE_16BPP; break; +/* + case IMGFMT_RGB24: + case IMGFMT_BGR24: bes_flags |= SCALER_SOURCE_24BPP; break; +*/ + case IMGFMT_RGB32: + case IMGFMT_BGR32: bes_flags |= SCALER_SOURCE_32BPP; break; + /* 4:1:0 */ + case IMGFMT_IF09: + case IMGFMT_YVU9: bes_flags |= SCALER_SOURCE_YUV9; break; + /* 4:0:0 */ + case IMGFMT_Y800: + case IMGFMT_Y8: + /* 4:2:0 */ + case IMGFMT_IYUV: + case IMGFMT_I420: + case IMGFMT_YV12: bes_flags |= SCALER_SOURCE_YUV12; break; + /* 4:2:2 */ + case IMGFMT_YVYU: + case IMGFMT_UYVY: bes_flags |= SCALER_SOURCE_YVYU422; break; + case IMGFMT_YUY2: + default: bes_flags |= SCALER_SOURCE_VYUY422; break; + } + OUTREG(OV0_SCALE_CNTL, bes_flags); + OUTREG(OV0_REG_LOAD_CNTL, 0); + if(__verbose > 1) printf(RADEON_MSG"we wanted: scaler=%08X\n",bes_flags); + if(__verbose > 1) radeon_vid_dump_regs(); +} + +static unsigned radeon_query_pitch(unsigned fourcc,const vidix_yuv_t *spitch) +{ + unsigned pitch,spy,spv,spu; + spy = spv = spu = 0; + switch(spitch->y) + { + case 16: + case 32: + case 64: + case 128: + case 256: spy = spitch->y; break; + default: break; + } + switch(spitch->u) + { + case 16: + case 32: + case 64: + case 128: + case 256: spu = spitch->u; break; + default: break; + } + switch(spitch->v) + { + case 16: + case 32: + case 64: + case 128: + case 256: spv = spitch->v; break; + default: break; + } + switch(fourcc) + { + /* 4:2:0 */ + case IMGFMT_IYUV: + case IMGFMT_YV12: + case IMGFMT_I420: + if(spy > 16 && spu == spy/2 && spv == spy/2) pitch = spy; + else pitch = 32; + break; + /* 4:1:0 */ + case IMGFMT_IF09: + case IMGFMT_YVU9: + if(spy > 32 && spu == spy/4 && spv == spy/4) pitch = spy; + else pitch = 64; + break; + default: + if(spy >= 16) pitch = spy; + else pitch = 16; + break; + } + return pitch; +} + +static int radeon_vid_init_video( vidix_playback_t *config ) +{ + uint32_t i,tmp,src_w,src_h,dest_w,dest_h,pitch,h_inc,step_by,left,leftUV,top; + int is_400,is_410,is_420,is_rgb32,is_rgb,best_pitch,mpitch; + radeon_vid_stop_video(); + left = config->src.x << 16; + top = config->src.y << 16; + src_h = config->src.h; + src_w = config->src.w; + is_400 = is_410 = is_420 = is_rgb32 = is_rgb = 0; + if(config->fourcc == IMGFMT_YV12 || + config->fourcc == IMGFMT_I420 || + config->fourcc == IMGFMT_IYUV) is_420 = 1; + if(config->fourcc == IMGFMT_YVU9 || + config->fourcc == IMGFMT_IF09) is_410 = 1; + if(config->fourcc == IMGFMT_Y800 || + config->fourcc == IMGFMT_Y8) is_400 = 1; + if(config->fourcc == IMGFMT_RGB32 || + config->fourcc == IMGFMT_BGR32) is_rgb32 = 1; + if(config->fourcc == IMGFMT_RGB32 || + config->fourcc == IMGFMT_BGR32 || + config->fourcc == IMGFMT_RGB24 || + config->fourcc == IMGFMT_BGR24 || + config->fourcc == IMGFMT_RGB16 || + config->fourcc == IMGFMT_BGR16 || + config->fourcc == IMGFMT_RGB15 || + config->fourcc == IMGFMT_BGR15) is_rgb = 1; + best_pitch = radeon_query_pitch(config->fourcc,&config->src.pitch); + mpitch = best_pitch-1; + switch(config->fourcc) + { + /* 4:0:0 */ + case IMGFMT_Y800: + case IMGFMT_Y8: + /* 4:1:0 */ + case IMGFMT_YVU9: + case IMGFMT_IF09: + /* 4:2:0 */ + case IMGFMT_IYUV: + case IMGFMT_YV12: + case IMGFMT_I420: pitch = (src_w + mpitch) & ~mpitch; + config->dest.pitch.y = + config->dest.pitch.u = + config->dest.pitch.v = best_pitch; + break; + /* RGB 4:4:4:4 */ + case IMGFMT_RGB32: + case IMGFMT_BGR32: pitch = (src_w*4 + mpitch) & ~mpitch; + config->dest.pitch.y = + config->dest.pitch.u = + config->dest.pitch.v = best_pitch; + break; + /* 4:2:2 */ + default: /* RGB15, RGB16, YVYU, UYVY, YUY2 */ + pitch = ((src_w*2) + mpitch) & ~mpitch; + config->dest.pitch.y = + config->dest.pitch.u = + config->dest.pitch.v = best_pitch; + break; + } + dest_w = config->dest.w; + dest_h = config->dest.h; + if(radeon_is_dbl_scan()) dest_h *= 2; + besr.dest_bpp = radeon_vid_get_dbpp(); + besr.fourcc = config->fourcc; + + /* flat panel */ + if(INREG(FP_VERT_STRETCH)&VERT_STRETCH_ENABLE){ + besr.v_inc = (src_h * radeon_get_yres() / radeon_get_fp_yres() << 20) / dest_h; + } + else besr.v_inc = (src_h << 20) / dest_h; + if(radeon_is_interlace()) besr.v_inc *= 2; + h_inc = (src_w << 12) / dest_w; + + { + unsigned int ecp_div; + ecp_div = (INPLL(VCLK_ECP_CNTL) >> 8) & 3; + h_inc <<= ecp_div; + } + + + step_by = 1; + while(h_inc >= (2 << 12)) { + step_by++; + h_inc >>= 1; + } + + /* keep everything in 16.16 */ + besr.base_addr = INREG(DISPLAY_BASE_ADDR); + config->offsets[0] = 0; + for(i=1;i<besr.vid_nbufs;i++) + config->offsets[i] = config->offsets[i-1]+config->frame_size; + if(is_420 || is_410 || is_400) + { + uint32_t d1line,d2line,d3line; + d1line = top*pitch; + if(is_420) + { + d2line = src_h*pitch+(d1line>>2); + d3line = d2line+((src_h*pitch)>>2); + } + else + if(is_410) + { + d2line = src_h*pitch+(d1line>>4); + d3line = d2line+((src_h*pitch)>>4); + } + else + { + d2line = 0; + d3line = 0; + } + d1line += (left >> 16) & ~15; + if(is_420) + { + d2line += (left >> 17) & ~15; + d3line += (left >> 17) & ~15; + } + else + if(is_410) + { + d2line += (left >> 18) & ~15; + d3line += (left >> 18) & ~15; + } + config->offset.y = d1line & VIF_BUF0_BASE_ADRS_MASK; + if(is_400) + { + config->offset.v = 0; + config->offset.u = 0; + } + else + { + config->offset.v = d2line & VIF_BUF1_BASE_ADRS_MASK; + config->offset.u = d3line & VIF_BUF2_BASE_ADRS_MASK; + } + for(i=0;i<besr.vid_nbufs;i++) + { + besr.vid_buf_base_adrs_y[i]=((radeon_overlay_off+config->offsets[i]+config->offset.y)&VIF_BUF0_BASE_ADRS_MASK); + if(is_400) + { + besr.vid_buf_base_adrs_v[i]=0; + besr.vid_buf_base_adrs_u[i]=0; + } + else + { + if (besr.fourcc == IMGFMT_I420 || besr.fourcc == IMGFMT_IYUV) + { + besr.vid_buf_base_adrs_u[i]=((radeon_overlay_off+config->offsets[i]+config->offset.v)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL; + besr.vid_buf_base_adrs_v[i]=((radeon_overlay_off+config->offsets[i]+config->offset.u)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL; + } + else + { + besr.vid_buf_base_adrs_v[i]=((radeon_overlay_off+config->offsets[i]+config->offset.v)&VIF_BUF1_BASE_ADRS_MASK)|VIF_BUF1_PITCH_SEL; + besr.vid_buf_base_adrs_u[i]=((radeon_overlay_off+config->offsets[i]+config->offset.u)&VIF_BUF2_BASE_ADRS_MASK)|VIF_BUF2_PITCH_SEL; + } + } + } + config->offset.y = ((besr.vid_buf_base_adrs_y[0])&VIF_BUF0_BASE_ADRS_MASK) - radeon_overlay_off; + if(is_400) + { + config->offset.v = 0; + config->offset.u = 0; + } + else + { + config->offset.v = ((besr.vid_buf_base_adrs_v[0])&VIF_BUF1_BASE_ADRS_MASK) - radeon_overlay_off; + config->offset.u = ((besr.vid_buf_base_adrs_u[0])&VIF_BUF2_BASE_ADRS_MASK) - radeon_overlay_off; + } + } + else + { + config->offset.y = config->offset.u = config->offset.v = ((left & ~7) << 1)&VIF_BUF0_BASE_ADRS_MASK; + for(i=0;i<besr.vid_nbufs;i++) + { + besr.vid_buf_base_adrs_y[i] = + besr.vid_buf_base_adrs_u[i] = + besr.vid_buf_base_adrs_v[i] = radeon_overlay_off + config->offsets[i] + config->offset.y; + } + } + + tmp = (left & 0x0003ffff) + 0x00028000 + (h_inc << 3); + besr.p1_h_accum_init = ((tmp << 4) & 0x000f8000) | + ((tmp << 12) & 0xf0000000); + + tmp = ((left >> 1) & 0x0001ffff) + 0x00028000 + (h_inc << 2); + besr.p23_h_accum_init = ((tmp << 4) & 0x000f8000) | + ((tmp << 12) & 0x70000000); + tmp = (top & 0x0000ffff) + 0x00018000; + besr.p1_v_accum_init = ((tmp << 4) & OV0_P1_V_ACCUM_INIT_MASK) + |(OV0_P1_MAX_LN_IN_PER_LN_OUT & 1); + + tmp = ((top >> 1) & 0x0000ffff) + 0x00018000; + besr.p23_v_accum_init = (is_420||is_410) ? + ((tmp << 4) & OV0_P23_V_ACCUM_INIT_MASK) + |(OV0_P23_MAX_LN_IN_PER_LN_OUT & 1) : 0; + + leftUV = (left >> (is_410?18:17)) & 15; + left = (left >> 16) & 15; + if(is_rgb && !is_rgb32) h_inc<<=1; + if(is_rgb32) + besr.h_inc = (h_inc >> 1) | ((h_inc >> 1) << 16); + else + if(is_410) + besr.h_inc = h_inc | ((h_inc >> 2) << 16); + else + besr.h_inc = h_inc | ((h_inc >> 1) << 16); + besr.step_by = step_by | (step_by << 8); + besr.y_x_start = (config->dest.x+X_ADJUST) | (config->dest.y << 16); + besr.y_x_end = (config->dest.x + dest_w+X_ADJUST) | ((config->dest.y + dest_h) << 16); + besr.p1_blank_lines_at_top = P1_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); + if(is_420 || is_410) + { + src_h = (src_h + 1) >> (is_410?2:1); + besr.p23_blank_lines_at_top = P23_BLNK_LN_AT_TOP_M1_MASK|((src_h-1)<<16); + } + else besr.p23_blank_lines_at_top = 0; + besr.vid_buf_pitch0_value = pitch; + besr.vid_buf_pitch1_value = is_410 ? pitch>>2 : is_420 ? pitch>>1 : pitch; + besr.p1_x_start_end = (src_w+left-1)|(left<<16); + if (is_410||is_420) src_w>>=is_410?2:1; + if(is_400) + { + besr.p2_x_start_end = 0; + besr.p3_x_start_end = 0; + } + else + { + besr.p2_x_start_end = (src_w+left-1)|(leftUV<<16); + besr.p3_x_start_end = besr.p2_x_start_end; + } + + return 0; +} + +static void radeon_compute_framesize(vidix_playback_t *info) +{ + unsigned pitch,awidth,dbpp; + pitch = radeon_query_pitch(info->fourcc,&info->src.pitch); + dbpp = radeon_vid_get_dbpp(); + switch(info->fourcc) + { + case IMGFMT_I420: + case IMGFMT_YV12: + case IMGFMT_IYUV: + awidth = (info->src.w + (pitch-1)) & ~(pitch-1); + info->frame_size = awidth*(info->src.h+info->src.h/2); + break; + case IMGFMT_Y800: + case IMGFMT_Y8: + awidth = (info->src.w + (pitch-1)) & ~(pitch-1); + info->frame_size = awidth*info->src.h; + break; + case IMGFMT_IF09: + case IMGFMT_YVU9: + awidth = (info->src.w + (pitch-1)) & ~(pitch-1); + info->frame_size = awidth*(info->src.h+info->src.h/8); + break; + case IMGFMT_RGB32: + case IMGFMT_BGR32: + awidth = (info->src.w*4 + (pitch-1)) & ~(pitch-1); + info->frame_size = awidth*info->src.h; + break; + /* YUY2 YVYU, RGB15, RGB16 */ + default: + awidth = (info->src.w*2 + (pitch-1)) & ~(pitch-1); + info->frame_size = awidth*info->src.h; + break; + } +} + +int vixConfigPlayback(vidix_playback_t *info) +{ + unsigned rgb_size,nfr; + if(!is_supported_fourcc(info->fourcc)) return ENOSYS; + if(info->num_frames>VID_PLAY_MAXFRAMES) info->num_frames=VID_PLAY_MAXFRAMES; + if(info->num_frames==1) besr.double_buff=0; + else besr.double_buff=1; + radeon_compute_framesize(info); + + rgb_size = radeon_get_xres()*radeon_get_yres()*((radeon_vid_get_dbpp()+7)/8); + nfr = info->num_frames; + for(;nfr>0; nfr--) + { + radeon_overlay_off = radeon_ram_size - info->frame_size*nfr; +#ifdef HAVE_X11 + radeon_overlay_off -= firegl_shift; +#endif + radeon_overlay_off &= 0xffff0000; + if(radeon_overlay_off >= (int)rgb_size ) break; + } + if(nfr <= 3) + { + nfr = info->num_frames; + for(;nfr>0; nfr--) + { + radeon_overlay_off = radeon_ram_size - info->frame_size*nfr; +#ifdef HAVE_X11 + radeon_overlay_off -= firegl_shift; +#endif + radeon_overlay_off &= 0xffff0000; + if(radeon_overlay_off > 0) break; + } + } + if(nfr <= 0) return EINVAL; + info->num_frames = nfr; + besr.vid_nbufs = info->num_frames; + info->dga_addr = (char *)radeon_mem_base + radeon_overlay_off; + radeon_vid_init_video(info); + return 0; +} + +int vixPlaybackOn( void ) +{ + radeon_vid_display_video(); + return 0; +} + +int vixPlaybackOff( void ) +{ + radeon_vid_stop_video(); + return 0; +} + +int vixPlaybackFrameSelect(unsigned frame) +{ + uint32_t off[6]; + int prev_frame= (frame-1+besr.vid_nbufs) % besr.vid_nbufs; + /* + buf3-5 always should point onto second buffer for better + deinterlacing and TV-in + */ + if(!besr.double_buff) return 0; + if(frame > besr.vid_nbufs) frame = besr.vid_nbufs-1; + if(prev_frame > (int)besr.vid_nbufs) prev_frame = besr.vid_nbufs-1; + off[0] = besr.vid_buf_base_adrs_y[frame]; + off[1] = besr.vid_buf_base_adrs_v[frame]; + off[2] = besr.vid_buf_base_adrs_u[frame]; + off[3] = besr.vid_buf_base_adrs_y[prev_frame]; + off[4] = besr.vid_buf_base_adrs_v[prev_frame]; + off[5] = besr.vid_buf_base_adrs_u[prev_frame]; + radeon_fifo_wait(8); + OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); + radeon_engine_idle(); + while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); + OUTREG(OV0_VID_BUF0_BASE_ADRS, off[0]); + OUTREG(OV0_VID_BUF1_BASE_ADRS, off[1]); + OUTREG(OV0_VID_BUF2_BASE_ADRS, off[2]); + OUTREG(OV0_VID_BUF3_BASE_ADRS, off[3]); + OUTREG(OV0_VID_BUF4_BASE_ADRS, off[4]); + OUTREG(OV0_VID_BUF5_BASE_ADRS, off[5]); + OUTREG(OV0_REG_LOAD_CNTL, 0); + if(besr.vid_nbufs == 2) radeon_wait_vsync(); + if(__verbose > 1) radeon_vid_dump_regs(); + return 0; +} + +vidix_video_eq_t equal = +{ + VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION +#ifndef RAGE128 + | VEQ_CAP_CONTRAST | VEQ_CAP_HUE | VEQ_CAP_RGB_INTENSITY +#endif + , + 0, 0, 0, 0, 0, 0, 0, 0 }; + +int vixPlaybackGetEq( vidix_video_eq_t * eq) +{ + memcpy(eq,&equal,sizeof(vidix_video_eq_t)); + return 0; +} + +#ifndef RAGE128 +#define RTFSaturation(a) (1.0 + ((a)*1.0)/1000.0) +#define RTFBrightness(a) (((a)*1.0)/2000.0) +#define RTFIntensity(a) (((a)*1.0)/2000.0) +#define RTFContrast(a) (1.0 + ((a)*1.0)/1000.0) +#define RTFHue(a) (((a)*3.1416)/1000.0) +#define RTFCheckParam(a) {if((a)<-1000) (a)=-1000; if((a)>1000) (a)=1000;} +#endif + +int vixPlaybackSetEq( const vidix_video_eq_t * eq) +{ +#ifdef RAGE128 + int br,sat; +#else + int itu_space; +#endif + if(eq->cap & VEQ_CAP_BRIGHTNESS) equal.brightness = eq->brightness; + if(eq->cap & VEQ_CAP_CONTRAST) equal.contrast = eq->contrast; + if(eq->cap & VEQ_CAP_SATURATION) equal.saturation = eq->saturation; + if(eq->cap & VEQ_CAP_HUE) equal.hue = eq->hue; + if(eq->cap & VEQ_CAP_RGB_INTENSITY) + { + equal.red_intensity = eq->red_intensity; + equal.green_intensity = eq->green_intensity; + equal.blue_intensity = eq->blue_intensity; + } + equal.flags = eq->flags; +#ifdef RAGE128 + br = equal.brightness * 64 / 1000; + if(br < -64) br = -64; if(br > 63) br = 63; + sat = (equal.saturation + 1000) * 16 / 1000; + if(sat < 0) sat = 0; if(sat > 31) sat = 31; + OUTREG(OV0_COLOUR_CNTL, (br & 0x7f) | (sat << 8) | (sat << 16)); +#else + itu_space = equal.flags == VEQ_FLG_ITU_R_BT_709 ? 1 : 0; + RTFCheckParam(equal.brightness); + RTFCheckParam(equal.saturation); + RTFCheckParam(equal.contrast); + RTFCheckParam(equal.hue); + RTFCheckParam(equal.red_intensity); + RTFCheckParam(equal.green_intensity); + RTFCheckParam(equal.blue_intensity); + radeon_set_transform(RTFBrightness(equal.brightness), + RTFContrast(equal.contrast), + RTFSaturation(equal.saturation), + RTFHue(equal.hue), + RTFIntensity(equal.red_intensity), + RTFIntensity(equal.green_intensity), + RTFIntensity(equal.blue_intensity), + itu_space); +#endif + return 0; +} + +int vixPlaybackSetDeint( const vidix_deinterlace_t * info) +{ + unsigned sflg; + switch(info->flags) + { + default: + case CFG_NON_INTERLACED: + besr.deinterlace_on = 0; + break; + case CFG_EVEN_ODD_INTERLACING: + case CFG_INTERLACED: + besr.deinterlace_on = 1; + besr.deinterlace_pattern = 0x900AAAAA; + break; + case CFG_ODD_EVEN_INTERLACING: + besr.deinterlace_on = 1; + besr.deinterlace_pattern = 0x00055555; + break; + case CFG_UNIQUE_INTERLACING: + besr.deinterlace_on = 1; + besr.deinterlace_pattern = info->deinterlace_pattern; + break; + } + OUTREG(OV0_REG_LOAD_CNTL, REG_LD_CTL_LOCK); + radeon_engine_idle(); + while(!(INREG(OV0_REG_LOAD_CNTL)®_LD_CTL_LOCK_READBACK)); + radeon_fifo_wait(15); + sflg = INREG(OV0_SCALE_CNTL); + if(besr.deinterlace_on) + { + OUTREG(OV0_SCALE_CNTL,sflg | SCALER_ADAPTIVE_DEINT); + OUTREG(OV0_DEINTERLACE_PATTERN,besr.deinterlace_pattern); + } + else OUTREG(OV0_SCALE_CNTL,sflg & (~SCALER_ADAPTIVE_DEINT)); + OUTREG(OV0_REG_LOAD_CNTL, 0); + return 0; +} + +int vixPlaybackGetDeint( vidix_deinterlace_t * info) +{ + if(!besr.deinterlace_on) info->flags = CFG_NON_INTERLACED; + else + { + info->flags = CFG_UNIQUE_INTERLACING; + info->deinterlace_pattern = besr.deinterlace_pattern; + } + return 0; +} + + +/* Graphic keys */ +static vidix_grkey_t radeon_grkey; + +static void set_gr_key( void ) +{ + if(radeon_grkey.ckey.op == CKEY_TRUE) + { + int dbpp=radeon_vid_get_dbpp(); + besr.ckey_on=1; + + switch(dbpp) + { + case 15: +#ifdef RADEON + if(RadeonFamily > 100) + besr.graphics_key_clr= + ((radeon_grkey.ckey.blue &0xF8)) + | ((radeon_grkey.ckey.green&0xF8)<<8) + | ((radeon_grkey.ckey.red &0xF8)<<16); + else +#endif + besr.graphics_key_clr= + ((radeon_grkey.ckey.blue &0xF8)>>3) + | ((radeon_grkey.ckey.green&0xF8)<<2) + | ((radeon_grkey.ckey.red &0xF8)<<7); + break; + case 16: +#ifdef RADEON + /* This test may be too general/specific */ + if(RadeonFamily > 100) + besr.graphics_key_clr= + ((radeon_grkey.ckey.blue &0xF8)) + | ((radeon_grkey.ckey.green&0xFC)<<8) + | ((radeon_grkey.ckey.red &0xF8)<<16); + else +#endif + besr.graphics_key_clr= + ((radeon_grkey.ckey.blue &0xF8)>>3) + | ((radeon_grkey.ckey.green&0xFC)<<3) + | ((radeon_grkey.ckey.red &0xF8)<<8); + break; + case 24: + besr.graphics_key_clr= + ((radeon_grkey.ckey.blue &0xFF)) + | ((radeon_grkey.ckey.green&0xFF)<<8) + | ((radeon_grkey.ckey.red &0xFF)<<16); + break; + case 32: + besr.graphics_key_clr= + ((radeon_grkey.ckey.blue &0xFF)) + | ((radeon_grkey.ckey.green&0xFF)<<8) + | ((radeon_grkey.ckey.red &0xFF)<<16); + break; + default: + besr.ckey_on=0; + besr.graphics_key_msk=0; + besr.graphics_key_clr=0; + } +#ifdef RAGE128 + besr.graphics_key_msk=(1<<dbpp)-1; + besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_NE|CMP_MIX_AND; +#else + besr.graphics_key_msk=besr.graphics_key_clr; + besr.ckey_cntl = VIDEO_KEY_FN_TRUE|CMP_MIX_AND|GRAPHIC_KEY_FN_EQ; +#endif + } + else + { + besr.ckey_on=0; + besr.graphics_key_msk=0; + besr.graphics_key_clr=0; + besr.ckey_cntl = VIDEO_KEY_FN_TRUE|GRAPHIC_KEY_FN_TRUE|CMP_MIX_AND; + } + radeon_fifo_wait(3); + OUTREG(OV0_GRAPHICS_KEY_MSK, besr.graphics_key_msk); + OUTREG(OV0_GRAPHICS_KEY_CLR, besr.graphics_key_clr); + OUTREG(OV0_KEY_CNTL,besr.ckey_cntl); +} + +int vixGetGrKeys(vidix_grkey_t *grkey) +{ + memcpy(grkey, &radeon_grkey, sizeof(vidix_grkey_t)); + return(0); +} + +int vixSetGrKeys(const vidix_grkey_t *grkey) +{ + memcpy(&radeon_grkey, grkey, sizeof(vidix_grkey_t)); + set_gr_key(); + return(0); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/vidix/savage_regs.h Sun Apr 01 00:02:43 2007 +0000 @@ -0,0 +1,303 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/savage/savage_regs.h,v 1.10 2001/11/04 22:17:48 alanh Exp $ */ + +#ifndef _SAVAGE_REGS_H +#define _SAVAGE_REGS_H + +/* These are here until xf86PciInfo.h is updated. */ + +#ifndef PCI_CHIP_S3TWISTER_P +#define PCI_CHIP_S3TWISTER_P 0x8d01 +#endif +#ifndef PCI_CHIP_S3TWISTER_K +#define PCI_CHIP_S3TWISTER_K 0x8d02 +#endif +#ifndef PCI_CHIP_SUPSAV_MX128 +#define PCI_CHIP_SUPSAV_MX128 0x8c22 +#define PCI_CHIP_SUPSAV_MX64 0x8c24 +#define PCI_CHIP_SUPSAV_MX64C 0x8c26 +#define PCI_CHIP_SUPSAV_IX128SDR 0x8c2a +#define PCI_CHIP_SUPSAV_IX128DDR 0x8c2b +#define PCI_CHIP_SUPSAV_IX64SDR 0x8c2c +#define PCI_CHIP_SUPSAV_IX64DDR 0x8c2d +#define PCI_CHIP_SUPSAV_IXCSDR 0x8c2e +#define PCI_CHIP_SUPSAV_IXCDDR 0x8c2f +#endif +#ifndef PCI_CHIP_PROSAVAGE_DDR +#define PCI_CHIP_PROSAVAGE_DDR 0x8d03 +#define PCI_CHIP_PROSAVAGE_DDRK 0x8d04 +#endif + +#define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX)) + +#define S3_SAVAGE4_SERIES(chip) ((chip==S3_SAVAGE4) || (chip==S3_PROSAVAGE)) + +#define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE)) + +#define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000)) + + +/* Chip tags. These are used to group the adapters into + * related families. + */ + + +enum S3CHIPTAGS { + S3_UNKNOWN = 0, + S3_SAVAGE3D, + S3_SAVAGE_MX, + S3_SAVAGE4, + S3_PROSAVAGE, + S3_SUPERSAVAGE, + S3_SAVAGE2000, + S3_LAST +}; + +typedef struct { + unsigned int mode, refresh; + unsigned char SR08, SR0E, SR0F; + unsigned char SR10, SR11, SR12, SR13, SR15, SR18, SR1B, SR29, SR30; + unsigned char SR54[8]; + unsigned char Clock; + unsigned char CR31, CR32, CR33, CR34, CR36, CR3A, CR3B, CR3C; + unsigned char CR40, CR41, CR42, CR43, CR45; + unsigned char CR50, CR51, CR53, CR55, CR58, CR5B, CR5D, CR5E; + unsigned char CR60, CR63, CR65, CR66, CR67, CR68, CR69, CR6D, CR6F; + unsigned char CR86, CR88; + unsigned char CR90, CR91, CRB0; + unsigned int STREAMS[22]; /* yuck, streams regs */ + unsigned int MMPR0, MMPR1, MMPR2, MMPR3; +} SavageRegRec, *SavageRegPtr; + + + +#define BIOS_BSIZE 1024 +#define BIOS_BASE 0xc0000 + +#define SAVAGE_NEWMMIO_REGBASE_S3 0x1000000 /* 16MB */ +#define SAVAGE_NEWMMIO_REGBASE_S4 0x0000000 +#define SAVAGE_NEWMMIO_REGSIZE 0x0080000 /* 512kb */ +#define SAVAGE_NEWMMIO_VGABASE 0x8000 + +#define BASE_FREQ 14.31818 + +#define FIFO_CONTROL_REG 0x8200 +#define MIU_CONTROL_REG 0x8204 +#define STREAMS_TIMEOUT_REG 0x8208 +#define MISC_TIMEOUT_REG 0x820c + +/* Stream Processor 1 */ + +/* Primary Stream 1 Frame Buffer Address 0 */ +#define PRI_STREAM_FBUF_ADDR0 0x81c0 +/* Primary Stream 1 Frame Buffer Address 0 */ +#define PRI_STREAM_FBUF_ADDR1 0x81c4 +/* Primary Stream 1 Stride */ +#define PRI_STREAM_STRIDE 0x81c8 +/* Primary Stream 1 Frame Buffer Size */ +#define PRI_STREAM_BUFFERSIZE 0x8214 + +/* Secondary stream 1 Color/Chroma Key Control */ +#define SEC_STREAM_CKEY_LOW 0x8184 +/* Secondary stream 1 Chroma Key Upper Bound */ +#define SEC_STREAM_CKEY_UPPER 0x8194 +/* Blend Control of Secondary Stream 1 & 2 */ +#define BLEND_CONTROL 0x8190 +/* Secondary Stream 1 Color conversion/Adjustment 1 */ +#define SEC_STREAM_COLOR_CONVERT1 0x8198 +/* Secondary Stream 1 Color conversion/Adjustment 2 */ +#define SEC_STREAM_COLOR_CONVERT2 0x819c +/* Secondary Stream 1 Color conversion/Adjustment 3 */ +#define SEC_STREAM_COLOR_CONVERT3 0x81e4 +/* Secondary Stream 1 Horizontal Scaling */ +#define SEC_STREAM_HSCALING 0x81a0 +/* Secondary Stream 1 Frame Buffer Size */ +#define SEC_STREAM_BUFFERSIZE 0x81a8 +/* Secondary Stream 1 Horizontal Scaling Normalization (2K only) */ +#define SEC_STREAM_HSCALE_NORMALIZE 0x81ac +/* Secondary Stream 1 Horizontal Scaling */ +#define SEC_STREAM_VSCALING 0x81e8 +/* Secondary Stream 1 Frame Buffer Address 0 */ +#define SEC_STREAM_FBUF_ADDR0 0x81d0 +/* Secondary Stream 1 Frame Buffer Address 1 */ +#define SEC_STREAM_FBUF_ADDR1 0x81d4 +/* Secondary Stream 1 Frame Buffer Address 2 */ +#define SEC_STREAM_FBUF_ADDR2 0x81ec +/* Secondary Stream 1 Stride */ +#define SEC_STREAM_STRIDE 0x81d8 +/* Secondary Stream 1 Window Start Coordinates */ +#define SEC_STREAM_WINDOW_START 0x81f8 +/* Secondary Stream 1 Window Size */ +#define SEC_STREAM_WINDOW_SZ 0x81fc +/* Secondary Streams Tile Offset */ +#define SEC_STREAM_TILE_OFF 0x821c +/* Secondary Stream 1 Opaque Overlay Control */ +#define SEC_STREAM_OPAQUE_OVERLAY 0x81dc + + +/* Stream Processor 2 */ + +/* Primary Stream 2 Frame Buffer Address 0 */ +#define PRI_STREAM2_FBUF_ADDR0 0x81b0 +/* Primary Stream 2 Frame Buffer Address 1 */ +#define PRI_STREAM2_FBUF_ADDR1 0x81b4 +/* Primary Stream 2 Stride */ +#define PRI_STREAM2_STRIDE 0x81b8 +/* Primary Stream 2 Frame Buffer Size */ +#define PRI_STREAM2_BUFFERSIZE 0x8218 + +/* Secondary Stream 2 Color/Chroma Key Control */ +#define SEC_STREAM2_CKEY_LOW 0x8188 +/* Secondary Stream 2 Chroma Key Upper Bound */ +#define SEC_STREAM2_CKEY_UPPER 0x818c +/* Secondary Stream 2 Horizontal Scaling */ +#define SEC_STREAM2_HSCALING 0x81a4 +/* Secondary Stream 2 Horizontal Scaling */ +#define SEC_STREAM2_VSCALING 0x8204 +/* Secondary Stream 2 Frame Buffer Size */ +#define SEC_STREAM2_BUFFERSIZE 0x81ac +/* Secondary Stream 2 Frame Buffer Address 0 */ +#define SEC_STREAM2_FBUF_ADDR0 0x81bc +/* Secondary Stream 2 Frame Buffer Address 1 */ +#define SEC_STREAM2_FBUF_ADDR1 0x81e0 +/* Secondary Stream 2 Frame Buffer Address 2 */ +#define SEC_STREAM2_FBUF_ADDR2 0x8208 +/* Multiple Buffer/LPB and Secondary Stream 2 Stride */ +#define SEC_STREAM2_STRIDE_LPB 0x81cc +/* Secondary Stream 2 Color conversion/Adjustment 1 */ +#define SEC_STREAM2_COLOR_CONVERT1 0x81f0 +/* Secondary Stream 2 Color conversion/Adjustment 2 */ +#define SEC_STREAM2_COLOR_CONVERT2 0x81f4 +/* Secondary Stream 2 Color conversion/Adjustment 3 */ +#define SEC_STREAM2_COLOR_CONVERT3 0x8200 +/* Secondary Stream 2 Window Start Coordinates */ +#define SEC_STREAM2_WINDOW_START 0x820c +/* Secondary Stream 2 Window Size */ +#define SEC_STREAM2_WINDOW_SZ 0x8210 +/* Secondary Stream 2 Opaque Overlay Control */ +#define SEC_STREAM2_OPAQUE_OVERLAY 0x8180 + + +/* savage 2000 */ +#define SEC_STREAM_COLOR_CONVERT0_2000 0x8198 +#define SEC_STREAM_COLOR_CONVERT1_2000 0x819c +#define SEC_STREAM_COLOR_CONVERT2_2000 0x81e0 +#define SEC_STREAM_COLOR_CONVERT3_2000 0x81e4 + +#define SUBSYS_STAT_REG 0x8504 + +#define SRC_BASE 0xa4d4 +#define DEST_BASE 0xa4d8 +#define CLIP_L_R 0xa4dc +#define CLIP_T_B 0xa4e0 +#define DEST_SRC_STR 0xa4e4 +#define MONO_PAT_0 0xa4e8 +#define MONO_PAT_1 0xa4ec + +/* Constants for CR69. */ + +#define CRT_ACTIVE 0x01 +#define LCD_ACTIVE 0x02 +#define TV_ACTIVE 0x04 +#define CRT_ATTACHED 0x10 +#define LCD_ATTACHED 0x20 +#define TV_ATTACHED 0x40 + + +/* + * reads from SUBSYS_STAT + */ +#define STATUS_WORD0 (INREG(0x48C00)) +#define ALT_STATUS_WORD0 (INREG(0x48C60)) +#define MAXLOOP 0xffffff +#define IN_SUBSYS_STAT() (INREG(SUBSYS_STAT_REG)) + +#define MAXFIFO 0x7f00 + +/* + * NOTE: don't remove 'VGAIN8(vgaCRIndex);'. + * If not present it will cause lockups on Savage4. + * Ask S3, why. + */ +/*#define VerticalRetraceWait() \ +{ \ + VGAIN8(0x3d0+4); \ + VGAOUT8(0x3d0+4, 0x17); \ + if (VGAIN8(0x3d0+5) & 0x80) { \ + while ((VGAIN8(0x3d0 + 0x0a) & 0x08) == 0x08) ; \ + while ((VGAIN8(0x3d0 + 0x0a) & 0x08) == 0x00) ; \ + } \ +} +*/ + +#define VerticalRetraceWait() \ +do { \ + VGAIN8(0x3d4); \ + VGAOUT8(0x3d4, 0x17); \ + if (VGAIN8(0x3d5) & 0x80) { \ + int i = 0x10000; \ + while ((VGAIN8(0x3da) & 0x08) == 0x08 && i--) ; \ + i = 0x10000; \ + while ((VGAIN8(0x3da) & 0x08) == 0x00 && i--) ; \ + } \ +} while (0) + + +#define I2C_REG 0xa0 +#define InI2CREG(a) \ +{ \ + VGAOUT8(0x3d0 + 4, I2C_REG); \ + a = VGAIN8(0x3d0 + 5); \ +} + +#define OutI2CREG(a) \ +{ \ + VGAOUT8(0x3d0 + 4, I2C_REG); \ + VGAOUT8(0x3d0 + 5, a); \ +} + +#define HZEXP_COMP_1 0x54 +#define HZEXP_BORDER 0x58 +#define HZEXP_FACTOR_IGA1 0x59 + +#define VTEXP_COMP_1 0x56 +#define VTEXP_BORDER 0x5a +#define VTEXP_FACTOR_IGA1 0x5b + +#define EC1_CENTER_ON 0x10 +#define EC1_EXPAND_ON 0x0c + +#define MODE_24 24 + +#if (MODE_24 == 32) +# define BYTES_PP24 4 +#else +# define BYTES_PP24 3 +#endif + +#define OVERLAY_DEPTH 16 + +#define STREAMS_MODE32 0x7 +#define STREAMS_MODE24 0x6 +#define STREAMS_MODE16 0x5 /* @@@ */ + + +#define DEPTH_BPP(depth) (depth == 24 ? (BYTES_PP24 << 3) : (depth + 7) & ~0x7) +#define DEPTH_2ND(depth) (depth > 8 ? depth\ + : OVERLAY_DEPTH) +#define SSTREAMS_MODE(bpp) (bpp > 16 ? (bpp > 24 ? STREAMS_MODE32 :\ + STREAMS_MODE24) : STREAMS_MODE16) + +#define HSCALING_Shift 0 +#define HSCALING_Mask (((1L << 16)-1) << HSCALING_Shift) +#define HSCALING(w0,w1) ((((unsigned int)(((double)w0/(double)w1) * (1 << 15))) \ + << HSCALING_Shift) \ + & HSCALING_Mask) + +#define VSCALING_Shift 0 +#define VSCALING_Mask (((1L << 20)-1) << VSCALING_Shift) +#define VSCALING(h0,h1) ((((unsigned int) (((double)h0/(double)h1) * (1 << 15))) \ + << VSCALING_Shift) \ + & VSCALING_Mask) + + +#endif /* _SAVAGE_REGS_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/vidix/savage_vid.c Sun Apr 01 00:02:43 2007 +0000 @@ -0,0 +1,1475 @@ +/* + Driver for S3 Savage Series + + Copyright (C) 2004 by Reza Jelveh + + Based on the X11 driver and nvidia vid + + Thanks to Alex Deucher for Support + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Changes: + 2004-11-09 + Initial version + + To Do: + +*/ + + +#include <errno.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <inttypes.h> +#include <unistd.h> +#include <math.h> + +#include "vidix.h" +#include "fourcc.h" +#include "../libdha/libdha.h" +#include "../libdha/pci_ids.h" +#include "../libdha/pci_names.h" +#include "../config.h" + +#include "savage_regs.h" + + +#define VF_STREAMS_ON 0x0001 +#define BASE_PAD 0xf +#define FRAMEBUFFER_SIZE 1024*2000*4 +/************************************** + S3 streams processor +**************************************/ + +#define EXT_MISC_CTRL2 0x67 + +/* New streams */ + +/* CR67[2] = 1 : enable stream 1 */ +#define ENABLE_STREAM1 0x04 +/* CR67[1] = 1 : enable stream 2 */ +#define ENABLE_STREAM2 0x02 +/* mask to clear CR67[2,1] */ +#define NO_STREAMS 0xF9 +/* CR67[3] = 1 : Mem-mapped regs */ +#define USE_MM_FOR_PRI_STREAM 0x08 + +#define HDM_SHIFT 16 +#define HDSCALE_4 (2 << HDM_SHIFT) +#define HDSCALE_8 (3 << HDM_SHIFT) +#define HDSCALE_16 (4 << HDM_SHIFT) +#define HDSCALE_32 (5 << HDM_SHIFT) +#define HDSCALE_64 (6 << HDM_SHIFT) + +/* Old Streams */ + +#define ENABLE_STREAMS_OLD 0x0c +#define NO_STREAMS_OLD 0xf3 +/* CR69[0] = 1 : Mem-mapped regs */ +#define USE_MM_FOR_PRI_STREAM_OLD 0x01 + +void SavageStreamsOn(void); + +/* + * There are two different streams engines used in the Savage line. + * The old engine is in the 3D, 4, Pro, and Twister. + * The new engine is in the 2000, MX, IX, and Super. + */ + + +/* streams registers for old engine */ +#define PSTREAM_CONTROL_REG 0x8180 +#define COL_CHROMA_KEY_CONTROL_REG 0x8184 +#define SSTREAM_CONTROL_REG 0x8190 +#define CHROMA_KEY_UPPER_BOUND_REG 0x8194 +#define SSTREAM_STRETCH_REG 0x8198 +#define COLOR_ADJUSTMENT_REG 0x819C +#define BLEND_CONTROL_REG 0x81A0 +#define PSTREAM_FBADDR0_REG 0x81C0 +#define PSTREAM_FBADDR1_REG 0x81C4 +#define PSTREAM_STRIDE_REG 0x81C8 +#define DOUBLE_BUFFER_REG 0x81CC +#define SSTREAM_FBADDR0_REG 0x81D0 +#define SSTREAM_FBADDR1_REG 0x81D4 +#define SSTREAM_STRIDE_REG 0x81D8 +#define SSTREAM_VSCALE_REG 0x81E0 +#define SSTREAM_VINITIAL_REG 0x81E4 +#define SSTREAM_LINES_REG 0x81E8 +#define STREAMS_FIFO_REG 0x81EC +#define PSTREAM_WINDOW_START_REG 0x81F0 +#define PSTREAM_WINDOW_SIZE_REG 0x81F4 +#define SSTREAM_WINDOW_START_REG 0x81F8 +#define SSTREAM_WINDOW_SIZE_REG 0x81FC +#define FIFO_CONTROL 0x8200 +#define PSTREAM_FBSIZE_REG 0x8300 +#define SSTREAM_FBSIZE_REG 0x8304 +#define SSTREAM_FBADDR2_REG 0x8308 + +#define OS_XY(x,y) (((x+1)<<16)|(y+1)) +#define OS_WH(x,y) (((x-1)<<16)|(y)) + +#define PCI_COMMAND_MEM 0x2 +#define MAX_FRAMES 3 +/** + * @brief Information on PCI device. + */ +pciinfo_t pci_info; + +/** + * @brief Unichrome driver colorkey settings. + */ +static vidix_grkey_t savage_grkey; + +static int frames[VID_PLAY_MAXFRAMES]; +uint8_t *vio; +uint8_t mclk_save[3]; + +#define outb(reg,val) OUTPORT8(reg,val) +#define inb(reg) INPORT8(reg) +#define outw(reg,val) OUTPORT16(reg,val) +#define inw(reg) INPORT16(reg) +#define outl(reg,val) OUTPORT32(reg,val) +#define inl(reg) INPORT32(reg) + + +/* + * PCI-Memory IO access macros. + */ +#define VID_WR08(p,i,val) (((uint8_t *)(p))[(i)]=(val)) +#define VID_RD08(p,i) (((uint8_t *)(p))[(i)]) + +#define VID_WR32(p,i,val) (((uint32_t *)(p))[(i)/4]=(val)) +#define VID_RD32(p,i) (((uint32_t *)(p))[(i)/4]) + +#ifndef USE_RMW_CYCLES +/* + * Can be used to inhibit READ-MODIFY-WRITE cycles. On by default. + */ + +#define MEM_BARRIER() __asm__ __volatile__ ("" : : : "memory") + +#undef VID_WR08 +#define VID_WR08(p,i,val) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]=(val); }) +#undef VID_RD08 +#define VID_RD08(p,i) ({ MEM_BARRIER(); ((uint8_t *)(p))[(i)]; }) + +#undef VID_WR16 +#define VID_WR16(p,i,val) ({ MEM_BARRIER(); ((uint16_t *)(p))[(i)/2]=(val); }) +#undef VID_RD16 +#define VID_RD16(p,i) ({ MEM_BARRIER(); ((uint16_t *)(p))[(i)/2]; }) + +#undef VID_WR32 +#define VID_WR32(p,i,val) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]=(val); }) +#undef VID_RD32 +#define VID_RD32(p,i) ({ MEM_BARRIER(); ((uint32_t *)(p))[(i)/4]; }) +#endif /* USE_RMW_CYCLES */ + +#define VID_AND32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)&(val)) +#define VID_OR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)|(val)) +#define VID_XOR32(p,i,val) VID_WR32(p,i,VID_RD32(p,i)^(val)) + + +/* from x driver */ + +#define VGAIN8(addr) VID_RD08(info->control_base+0x8000, addr) +#define VGAIN16(addr) VID_RD16(info->control_base+0x8000, addr) +#define VGAIN(addr) VID_RD32(info->control_base+0x8000, addr) + +#define VGAOUT8(addr,val) VID_WR08(info->control_base+0x8000, addr, val) +#define VGAOUT16(addr,val) VID_WR16(info->control_base+0x8000, addr, val) +#define VGAOUT(addr,val) VID_WR32(info->control_base+0x8000, addr, val) + +#define INREG(addr) VID_RD32(info->control_base, addr) +#define OUTREG(addr,val) VID_WR32(info->control_base, addr, val) +#define INREG8(addr) VID_RD08(info->control_base, addr) +#define OUTREG8(addr,val) VID_WR08(info->control_base, addr, val) +#define INREG16(addr) VID_RD16(info->control_base, addr) +#define OUTREG16(addr,val) VID_WR16(info->control_base, addr, val) + +#define ALIGN_TO(v, n) (((v) + (n-1)) & ~(n-1)) + + +void debugout(unsigned int addr, unsigned int val); + + +struct savage_chip { + volatile uint32_t *PMC; /* general control */ + volatile uint32_t *PME; /* multimedia port */ + volatile uint32_t *PFB; /* framebuffer control */ + volatile uint32_t *PVIDEO; /* overlay control */ + volatile uint8_t *PCIO; /* SVGA (CRTC, ATTR) registers */ + volatile uint8_t *PVIO; /* SVGA (MISC, GRAPH, SEQ) registers */ + volatile uint32_t *PRAMIN; /* instance memory */ + volatile uint32_t *PRAMHT; /* hash table */ + volatile uint32_t *PRAMFC; /* fifo context table */ + volatile uint32_t *PRAMRO; /* fifo runout table */ + volatile uint32_t *PFIFO; /* fifo control region */ + volatile uint32_t *FIFO; /* fifo channels (USER) */ + volatile uint32_t *PGRAPH; /* graphics engine */ + + int arch; /* compatible NV_ARCH_XX define */ + unsigned long fbsize; /* framebuffer size */ + void (* lock) (struct savage_chip *, int); +}; +typedef struct savage_chip savage_chip; + + +struct savage_info { + unsigned int use_colorkey; + unsigned int colorkey; /* saved xv colorkey*/ + unsigned int vidixcolorkey; /*currently used colorkey*/ + unsigned int depth; + unsigned int bpp; + unsigned int videoFlags; + unsigned int format; + unsigned int pitch; + unsigned int blendBase; + unsigned int lastKnownPitch; + unsigned int displayWidth, displayHeight; + unsigned int brightness,hue,saturation,contrast; + unsigned int src_w,src_h; + unsigned int drw_w,drw_h; /*scaled width && height*/ + unsigned int wx,wy; /*window x && y*/ + unsigned int screen_x; /*screen width*/ + unsigned int screen_y; /*screen height*/ + unsigned long buffer_size; /* size of the image buffer */ + struct savage_chip chip; /* NV architecture structure */ + void* video_base; /* virtual address of control region */ + void* control_base; /* virtual address of fb region */ + unsigned long picture_base; /* direct pointer to video picture */ + unsigned long picture_offset; /* offset of video picture in frame buffer */ +// struct savage_dma dma; /* DMA structure */ + unsigned int cur_frame; + unsigned int num_frames; /* number of buffers */ + int bps; /* bytes per line */ + void (*SavageWaitIdle) (); + void (*SavageWaitFifo) (int space); +}; +typedef struct savage_info savage_info; + + +static savage_info* info; + + +/** + * @brief Unichrome driver vidix capabilities. + */ +static vidix_capability_t savage_cap = { + "Savage/ProSavage/Twister vidix", + "Reza Jelveh <reza.jelveh@tuhh.de>", + TYPE_OUTPUT, + {0, 0, 0, 0}, + 4096, + 4096, + 4, + 4, + -1, + FLAG_UPSCALER | FLAG_DOWNSCALER, + VENDOR_S3_INC, + -1, + {0, 0, 0, 0} +}; + +struct savage_cards { + unsigned short chip_id; + unsigned short arch; +}; + + +static +unsigned int GetBlendForFourCC( int id ) +{ + switch( id ) { + case IMGFMT_YUY2: + case IMGFMT_YV12: + case IMGFMT_I420: + return 1; + case IMGFMT_Y211: + return 4; + case IMGFMT_RGB15: + return 3; + case IMGFMT_RGB16: + return 5; + default: + return 0; + } +} + +/** + * @brief list of card IDs compliant with the Unichrome driver . + */ +static struct savage_cards savage_card_ids[] = { + /*[ProSavage PN133] AGP4X VGA Controller (Twister)*/ + { PCI_CHIP_S3TWISTER_P, S3_PROSAVAGE }, + /*[ProSavage KN133] AGP4X VGA Controller (TwisterK)*/ + { PCI_CHIP_S3TWISTER_K, S3_PROSAVAGE }, + /*ProSavage DDR*/ + { PCI_CHIP_PROSAVAGE_DDR , S3_PROSAVAGE }, + /*[ProSavageDDR P4M266 K] */ + { PCI_CHIP_PROSAVAGE_DDRK , S3_PROSAVAGE }, +}; + +static void SavageSetColorOld(void) +{ + + + if( + (info->format == IMGFMT_RGB15) || + (info->format == IMGFMT_RGB16) + ) + { + OUTREG( COLOR_ADJUSTMENT_REG, 0 ); + } + else + { + /* Change 0..255 into 0..15 */ + long sat = info->saturation * 16 / 256; + double hue = info->hue * 0.017453292; + unsigned long hs1 = ((long)(sat * cos(hue))) & 0x1f; + unsigned long hs2 = ((long)(sat * sin(hue))) & 0x1f; + + OUTREG( COLOR_ADJUSTMENT_REG, + 0x80008000 | + (info->brightness + 128) | + ((info->contrast & 0xf8) << (12-7)) | + (hs1 << 16) | + (hs2 << 24) + ); + debugout( COLOR_ADJUSTMENT_REG, + 0x80008000 | + (info->brightness + 128) | + ((info->contrast & 0xf8) << (12-7)) | + (hs1 << 16) | + (hs2 << 24) + ); + + } +} + +static void SavageSetColorKeyOld(void) +{ + int red, green, blue; + + /* Here, we reset the colorkey and all the controls. */ + + red = (info->vidixcolorkey & 0x00FF0000) >> 16; + green = (info->vidixcolorkey & 0x0000FF00) >> 8; + blue = info->vidixcolorkey & 0x000000FF; + + if( !info->vidixcolorkey ) { + printf("SavageSetColorKey disabling colorkey\n"); + OUTREG( COL_CHROMA_KEY_CONTROL_REG, 0 ); + OUTREG( CHROMA_KEY_UPPER_BOUND_REG, 0 ); + OUTREG( BLEND_CONTROL_REG, 0 ); + } + else { + switch (info->depth) { + // FIXME: isnt fixed yet + case 8: + OUTREG( COL_CHROMA_KEY_CONTROL_REG, + 0x37000000 | (info->vidixcolorkey & 0xFF) ); + OUTREG( CHROMA_KEY_UPPER_BOUND_REG, + 0x00000000 | (info->vidixcolorkey & 0xFF) ); + break; + case 15: + /* 15 bpp 555 */ + red&=0x1f; + green&=0x1f; + blue&=0x1f; + OUTREG( COL_CHROMA_KEY_CONTROL_REG, + 0x05000000 | (red<<19) | (green<<11) | (blue<<3) ); + OUTREG( CHROMA_KEY_UPPER_BOUND_REG, + 0x00000000 | (red<<19) | (green<<11) | (blue<<3) ); + break; + case 16: + /* 16 bpp 565 */ + red&=0x1f; + green&=0x3f; + blue&=0x1f; + OUTREG( COL_CHROMA_KEY_CONTROL_REG, + 0x16000000 | (red<<19) | (green<<10) | (blue<<3) ); + OUTREG( CHROMA_KEY_UPPER_BOUND_REG, + 0x00020002 | (red<<19) | (green<<10) | (blue<<3) ); + break; + case 24: + /* 24 bpp 888 */ + OUTREG( COL_CHROMA_KEY_CONTROL_REG, + 0x17000000 | (red<<16) | (green<<8) | (blue) ); + OUTREG( CHROMA_KEY_UPPER_BOUND_REG, + 0x00000000 | (red<<16) | (green<<8) | (blue) ); + break; + } + + /* We use destination colorkey */ + OUTREG( BLEND_CONTROL_REG, 0x05000000 ); + } +} + + +static void +SavageDisplayVideoOld(void) +{ + int vgaCRIndex, vgaCRReg, vgaIOBase; + unsigned int ssControl; + int cr92; + + + vgaIOBase = 0x3d0; + vgaCRIndex = vgaIOBase + 4; + vgaCRReg = vgaIOBase + 5; + +// if( psav->videoFourCC != id ) +// SavageStreamsOff(pScrn); + + if( !info->videoFlags & VF_STREAMS_ON ) + { + SavageStreamsOn(); + // SavageResetVideo(); + SavageSetColorOld(); + SavageSetColorKeyOld(); + } + + + + + /* Set surface format. */ + + OUTREG(SSTREAM_CONTROL_REG,GetBlendForFourCC(info->format) << 24 | info->src_w); + + debugout(SSTREAM_CONTROL_REG,GetBlendForFourCC(info->format) << 24 | info->src_w); + + /* Calculate horizontal scale factor. */ + + //FIXME: enable scaling + OUTREG(SSTREAM_STRETCH_REG, (info->src_w << 15) / info->drw_w ); +// debugout(SSTREAM_STRETCH_REG, 1 << 15); + + OUTREG(SSTREAM_LINES_REG, info->src_h ); + debugout(SSTREAM_LINES_REG, info->src_h ); + + + OUTREG(SSTREAM_VINITIAL_REG, 0 ); + debugout(SSTREAM_VINITIAL_REG, 0 ); + /* Calculate vertical scale factor. */ + +// OUTREG(SSTREAM_VSCALE_REG, 1 << 15); + OUTREG(SSTREAM_VSCALE_REG, VSCALING(info->src_h,info->drw_h) ); + debugout(SSTREAM_VSCALE_REG, VSCALING(info->src_h,info->drw_h) ); +// OUTREG(SSTREAM_VSCALE_REG, (info->src_h << 15) / info->drw_h ); + + /* Set surface location and stride. */ + + OUTREG(SSTREAM_FBADDR0_REG, info->picture_offset ); + debugout(SSTREAM_FBADDR0_REG, info->picture_offset ); + + OUTREG(SSTREAM_FBADDR1_REG, 0 ); + debugout(SSTREAM_FBADDR1_REG, 0 ); + + OUTREG(SSTREAM_STRIDE_REG, info->pitch ); + debugout(SSTREAM_STRIDE_REG, info->pitch ); + + OUTREG(SSTREAM_WINDOW_START_REG, OS_XY(info->wx, info->wy) ); + debugout(SSTREAM_WINDOW_START_REG, OS_XY(info->wx, info->wy) ); + OUTREG(SSTREAM_WINDOW_SIZE_REG, OS_WH(info->drw_w, info->drw_h) ); + debugout(SSTREAM_WINDOW_SIZE_REG, OS_WH(info->drw_w, info->drw_h) ); + + + + ssControl = 0; + + if( info->src_w > (info->drw_w << 1) ) + { + /* BUGBUG shouldn't this be >=? */ + if( info->src_w <= (info->drw_w << 2) ) + ssControl |= HDSCALE_4; + else if( info->src_w > (info->drw_w << 3) ) + ssControl |= HDSCALE_8; + else if( info->src_w > (info->drw_w << 4) ) + ssControl |= HDSCALE_16; + else if( info->src_w > (info->drw_w << 5) ) + ssControl |= HDSCALE_32; + else if( info->src_w > (info->drw_w << 6) ) + ssControl |= HDSCALE_64; + } + + ssControl |= info->src_w; + ssControl |= (1 << 24); + + //FIXME: enable scaling + OUTREG(SSTREAM_CONTROL_REG, ssControl); + debugout(SSTREAM_CONTROL_REG, ssControl); + + // FIXME: this should actually be enabled + + info->pitch = (info->pitch + 7) / 8; + VGAOUT8(vgaCRIndex, 0x92); + cr92 = VGAIN8(vgaCRReg); + VGAOUT8(vgaCRReg, (cr92 & 0x40) | (info->pitch >> 8) | 0x80); + VGAOUT8(vgaCRIndex, 0x93); + VGAOUT8(vgaCRReg, info->pitch); + OUTREG(STREAMS_FIFO_REG, 2 | 25 << 5 | 32 << 11); + + + + +} + +static void SavageInitStreamsOld(void) +{ + /*unsigned long jDelta;*/ + unsigned long format = 0; + + /* + * For the OLD streams engine, several of these registers + * cannot be touched unless streams are on. Seems backwards to me; + * I'd want to set 'em up, then cut 'em loose. + */ + + + /*jDelta = pScrn->displayWidth * (pScrn->bitsPerPixel + 7) / 8;*/ + switch( info->depth ) { + case 8: format = 0 << 24; break; + case 15: format = 3 << 24; break; + case 16: format = 5 << 24; break; + case 24: format = 7 << 24; break; + } +#warning enable this again + OUTREG(PSTREAM_FBSIZE_REG, + info->screen_y * info->screen_x * (info->bpp >> 3)); + + OUTREG( PSTREAM_WINDOW_START_REG, OS_XY(0,0) ); + OUTREG( PSTREAM_WINDOW_SIZE_REG, OS_WH(info->screen_x, info->screen_y) ); + OUTREG( PSTREAM_FBADDR1_REG, 0 ); + /*OUTREG( PSTREAM_STRIDE_REG, jDelta );*/ + OUTREG( PSTREAM_CONTROL_REG, format ); + OUTREG( PSTREAM_FBADDR0_REG, 0 ); + + /*OUTREG( PSTREAM_FBSIZE_REG, jDelta * pScrn->virtualY >> 3 );*/ + + OUTREG( COL_CHROMA_KEY_CONTROL_REG, 0 ); + OUTREG( SSTREAM_CONTROL_REG, 0 ); + OUTREG( CHROMA_KEY_UPPER_BOUND_REG, 0 ); + OUTREG( SSTREAM_STRETCH_REG, 0 ); + OUTREG( COLOR_ADJUSTMENT_REG, 0 ); + OUTREG( BLEND_CONTROL_REG, 1 << 24 ); + OUTREG( DOUBLE_BUFFER_REG, 0 ); + OUTREG( SSTREAM_FBADDR0_REG, 0 ); + OUTREG( SSTREAM_FBADDR1_REG, 0 ); + OUTREG( SSTREAM_FBADDR2_REG, 0 ); + OUTREG( SSTREAM_FBSIZE_REG, 0 ); + OUTREG( SSTREAM_STRIDE_REG, 0 ); + OUTREG( SSTREAM_VSCALE_REG, 0 ); + OUTREG( SSTREAM_LINES_REG, 0 ); + OUTREG( SSTREAM_VINITIAL_REG, 0 ); +#warning is this needed? + OUTREG( SSTREAM_WINDOW_START_REG, OS_XY(0xfffe, 0xfffe) ); + OUTREG( SSTREAM_WINDOW_SIZE_REG, OS_WH(10,2) ); + +} + +void +SavageStreamsOn(void) +{ + unsigned char jStreamsControl; + unsigned short vgaCRIndex = 0x3d0 + 4; + unsigned short vgaCRReg = 0x3d0 + 5; + +// xf86ErrorFVerb(STREAMS_TRACE, "SavageStreamsOn\n" ); + + /* Sequence stolen from streams.c in M7 NT driver */ + + + enable_app_io (); + + /* Unlock extended registers. */ + + /* FIXME: it looks like mmaped io is broken with vgaout16 */ + VGAOUT16(vgaCRIndex, 0x4838 ); + VGAOUT16(vgaCRIndex, 0xa039); + VGAOUT16(0x3c4, 0x0608); + + + + VGAOUT8( vgaCRIndex, EXT_MISC_CTRL2 ); + + if( S3_SAVAGE_MOBILE_SERIES(info->chip.arch) ) + { +// SavageInitStreamsNew( pScrn ); + + jStreamsControl = VGAIN8( vgaCRReg ) | ENABLE_STREAM1; + + /* Wait for VBLANK. */ + VerticalRetraceWait(); + /* Fire up streams! */ + VGAOUT16( vgaCRIndex, (jStreamsControl << 8) | EXT_MISC_CTRL2 ); + /* These values specify brightness, contrast, saturation and hue. */ + OUTREG( SEC_STREAM_COLOR_CONVERT1, 0x0000C892 ); + OUTREG( SEC_STREAM_COLOR_CONVERT2, 0x00039F9A ); + OUTREG( SEC_STREAM_COLOR_CONVERT3, 0x01F1547E ); + } + else if (info->chip.arch == S3_SAVAGE2000) + { +// SavageInitStreams2000( pScrn ); + + jStreamsControl = VGAIN8( vgaCRReg ) | ENABLE_STREAM1; + + /* Wait for VBLANK. */ + VerticalRetraceWait(); + /* Fire up streams! */ + VGAOUT16( vgaCRIndex, (jStreamsControl << 8) | EXT_MISC_CTRL2 ); + /* These values specify brightness, contrast, saturation and hue. */ + OUTREG( SEC_STREAM_COLOR_CONVERT0_2000, 0x0000C892 ); + OUTREG( SEC_STREAM_COLOR_CONVERT1_2000, 0x00033400 ); + OUTREG( SEC_STREAM_COLOR_CONVERT2_2000, 0x000001CF ); + OUTREG( SEC_STREAM_COLOR_CONVERT3_2000, 0x01F1547E ); + } + else + { + jStreamsControl = VGAIN8( vgaCRReg ) | ENABLE_STREAMS_OLD; + + /* Wait for VBLANK. */ + + VerticalRetraceWait(); + + /* Fire up streams! */ + + VGAOUT16( vgaCRIndex, (jStreamsControl << 8) | EXT_MISC_CTRL2 ); + + SavageInitStreamsOld( ); + } + + /* Wait for VBLANK. */ + + VerticalRetraceWait(); + + /* Turn on secondary stream TV flicker filter, once we support TV. */ + + /* SR70 |= 0x10 */ + + info->videoFlags |= VF_STREAMS_ON; + +} + + + + +static void savage_getscreenproperties(struct savage_info *info){ + unsigned char bpp=0; + uint32_t width=0; + + uint32_t vgaIOBase, vgaCRIndex, vgaCRReg; + + vgaIOBase = 0x3d0; + vgaCRIndex = vgaIOBase + 4; + vgaCRReg = vgaIOBase + 5; + + + /* a little reversed from x driver source code */ + VGAOUT8(vgaCRIndex, 0x67); + bpp = VGAIN8(vgaCRReg); + + + switch (bpp&0xf0) { + case 0x00: + case 0x10: + info->depth=8; + info->bpp=8; + break; + case 0x20: + case 0x30: + info->depth=15; + info->bpp=16; + break; + case 0x40: + case 0x50: + info->depth=16; + info->bpp=16; + break; + case 0x70: + case 0xd0: + info->depth=24; + info->bpp=32; + break; + + + } + + + VGAOUT8(vgaCRIndex, 0x1); + info->screen_x = (1 + VGAIN8(vgaCRReg)) <<3; + /*get screen height*/ + /* get first 8 bits in VT_DISPLAY_END*/ + VGAOUT8(0x03D4, 0x12); + info->screen_y = VGAIN8(0x03D5); + VGAOUT8(0x03D4,0x07); + /* get 9th bit in CRTC_OVERFLOW*/ + info->screen_y |= (VGAIN8(0x03D5) &0x02)<<7; + /* and the 10th in CRTC_OVERFLOW*/ + info->screen_y |=(VGAIN8(0x03D5) &0x40)<<3; + ++info->screen_y; + + printf("screen_x = %d, screen_y = %d, bpp = %d\n",info->screen_x,info->screen_y,info->bpp); +} + + +static void SavageStreamsOff(void) +{ + unsigned char jStreamsControl; + unsigned short vgaCRIndex = 0x3d0 + 4; + unsigned short vgaCRReg = 0x3d0 + 5; + + + /* Unlock extended registers. */ + + VGAOUT16(vgaCRIndex, 0x4838); + VGAOUT16(vgaCRIndex, 0xa039); + VGAOUT16(0x3c4, 0x0608); + + VGAOUT8( vgaCRIndex, EXT_MISC_CTRL2 ); + if( S3_SAVAGE_MOBILE_SERIES(info->chip.arch) || + (info->chip.arch == S3_SUPERSAVAGE) || + (info->chip.arch == S3_SAVAGE2000) ) + jStreamsControl = VGAIN8( vgaCRReg ) & NO_STREAMS; + else + jStreamsControl = VGAIN8( vgaCRReg ) & NO_STREAMS_OLD; + + /* Wait for VBLANK. */ + + VerticalRetraceWait(); + + /* Kill streams. */ + + VGAOUT16(vgaCRIndex, (jStreamsControl << 8) | EXT_MISC_CTRL2 ); + + VGAOUT16(vgaCRIndex, 0x0093 ); + VGAOUT8( vgaCRIndex, 0x92 ); + VGAOUT8( vgaCRReg, VGAIN8(vgaCRReg) & 0x40 ); + + info->videoFlags &= ~VF_STREAMS_ON; +} + + +/** + * @brief Check age of driver. + * + * @return vidix version number. + */ +unsigned int +vixGetVersion (void) +{ + return (VIDIX_VERSION); +} + +/** + * @brief Find chip index in Unichrome compliant devices list. + * + * @param chip_id PCI device ID. + * + * @returns index position in savage_card_ids if successful. + * -1 if chip_id is not a compliant chipset ID. + */ + +static int find_chip(unsigned chip_id){ + unsigned i; + for(i = 0;i < sizeof(savage_card_ids)/sizeof(struct savage_cards);i++) + { + if(chip_id == savage_card_ids[i].chip_id)return i; + } + return -1; +} + +/** + * @brief Probe hardware to find some useable chipset. + * + * @param verbose specifies verbose level. + * @param force specifies force mode : driver should ignore + * device_id (danger but useful for new devices) + * + * @returns 0 if it can handle something in PC. + * a negative error code otherwise. + */ + +int vixProbe(int verbose, int force){ + pciinfo_t lst[MAX_PCI_DEVICES]; + unsigned i,num_pci; + int err; + + if (force) + printf("[savage_vid]: warning: forcing not supported yet!\n"); + err = pci_scan(lst,&num_pci); + if(err){ + printf("[savage_vid] Error occurred during pci scan: %s\n",strerror(err)); + return err; + } + else { + err = ENXIO; + for(i=0; i < num_pci; i++){ + if(lst[i].vendor == VENDOR_S3_INC) { + int idx; + const char *dname; + idx = find_chip(lst[i].device); + if(idx == -1) + continue; + dname = pci_device_name(lst[i].vendor, lst[i].device); + dname = dname ? dname : "Unknown chip"; + printf("[savage_vid] Found chip: %s\n", dname); + // FIXME: whats wrong here? + if ((lst[i].command & PCI_COMMAND_IO ) == 0){ + printf("[savage_vid] Device is disabled, ignoring\n"); + continue; + } + savage_cap.device_id = lst[i].device; + err = 0; + memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); + break; + } + } + } + if(err && verbose) printf("[savage_vid] Can't find chip\n"); + return err; +} + +/** + * @brief Initializes driver. + * + * @returns 0 if ok. + * a negative error code otherwise. + */ +int +vixInit (void) +{ + int mtrr; + unsigned char config1, m, n, n1, n2, sr8, cr3f, cr66 = 0, tmp; + + static unsigned char RamSavage3D[] = { 8, 4, 4, 2 }; + static unsigned char RamSavage4[] = { 2, 4, 8, 12, 16, 32, 64, 32 }; + static unsigned char RamSavageMX[] = { 2, 8, 4, 16, 8, 16, 4, 16 }; + static unsigned char RamSavageNB[] = { 0, 2, 4, 8, 16, 32, 16, 2 }; + + int videoRam, videoRambytes; + + uint32_t vgaIOBase, vgaCRIndex, vgaCRReg ; + + unsigned char val; + + vgaIOBase = 0x3d0; + vgaCRIndex = vgaIOBase + 4; + vgaCRReg = vgaIOBase + 5; + + fprintf(stderr, "vixInit enter \n"); +// //getc(stdin); + + info = calloc(1,sizeof(savage_info)); + + + /* need this if we want direct outb and inb access? */ + enable_app_io (); + + /* 12mb + 32kb ? */ + /* allocate some space for control registers */ + info->chip.arch = savage_card_ids[find_chip(pci_info.device)].arch; + + if (info->chip.arch == S3_SAVAGE3D) { + info->control_base = map_phys_mem(pci_info.base0+SAVAGE_NEWMMIO_REGBASE_S3, SAVAGE_NEWMMIO_REGSIZE); + } + else { + info->control_base = map_phys_mem(pci_info.base0+SAVAGE_NEWMMIO_REGBASE_S4, SAVAGE_NEWMMIO_REGSIZE); + } + +// info->chip.PCIO = (uint8_t *) (info->control_base + SAVAGE_NEWMMIO_VGABASE); + + // FIXME: enable mmio? + val = VGAIN8 (0x3c3); + VGAOUT8 (0x3c3, val | 0x01); + val = VGAIN8 (0x3cc); + VGAOUT8 (0x3c2, val | 0x01); + + if (info->chip.arch >= S3_SAVAGE4) + { + VGAOUT8 (0x3d4, 0x40); + val = VGAIN8 (0x3d5); + VGAOUT8 (0x3d5, val | 1); + } + + + + /* unprotect CRTC[0-7] */ + VGAOUT8(vgaCRIndex, 0x11); + tmp = VGAIN8(vgaCRReg); +// printf("$########## tmp = %d\n",tmp); + VGAOUT8(vgaCRReg, tmp & 0x7f); + + + /* unlock extended regs */ + VGAOUT16(vgaCRIndex, 0x4838); + VGAOUT16(vgaCRIndex, 0xa039); + VGAOUT16(0x3c4, 0x0608); + + VGAOUT8(vgaCRIndex, 0x40); + tmp = VGAIN8(vgaCRReg); + VGAOUT8(vgaCRReg, tmp & ~0x01); + + /* unlock sys regs */ + VGAOUT8(vgaCRIndex, 0x38); + VGAOUT8(vgaCRReg, 0x48); + + /* Unlock system registers. */ + VGAOUT16(vgaCRIndex, 0x4838); + + /* Next go on to detect amount of installed ram */ + + VGAOUT8(vgaCRIndex, 0x36); /* for register CR36 (CONFG_REG1), */ + config1 = VGAIN8(vgaCRReg); /* get amount of vram installed */ + + + switch( info->chip.arch ) { + case S3_SAVAGE3D: + videoRam = RamSavage3D[ (config1 & 0xC0) >> 6 ] * 1024; + break; + + case S3_SAVAGE4: + /* + * The Savage4 has one ugly special case to consider. On + * systems with 4 banks of 2Mx32 SDRAM, the BIOS says 4MB + * when it really means 8MB. Why do it the same when you + * can do it different... + */ + VGAOUT8(0x3d4, 0x68); /* memory control 1 */ + if( (VGAIN8(0x3d5) & 0xC0) == (0x01 << 6) ) + RamSavage4[1] = 8; + + /*FALLTHROUGH*/ + + case S3_SAVAGE2000: + videoRam = RamSavage4[ (config1 & 0xE0) >> 5 ] * 1024; + break; + + case S3_SAVAGE_MX: + videoRam = RamSavageMX[ (config1 & 0x0E) >> 1 ] * 1024; + break; + + case S3_PROSAVAGE: + videoRam = RamSavageNB[ (config1 & 0xE0) >> 5 ] * 1024; + break; + + default: + /* How did we get here? */ + videoRam = 0; + break; + } + + + printf("###### videoRam = %d\n",videoRam); + info->chip.fbsize = videoRam * 1024; + + + /* reset graphics engine to avoid memory corruption */ +/* VGAOUT8 (0x3d4, 0x66); + cr66 = VGAIN8 (0x3d5); + VGAOUT8 (0x3d5, cr66 | 0x02); + udelay (10000); + + VGAOUT8 (0x3d4, 0x66); + VGAOUT8 (0x3d5, cr66 & ~0x02); /* clear reset flag */ + /* udelay (10000); */ + + /* This maps framebuffer @6MB, thus 2MB are left for video. */ + if (info->chip.arch == S3_SAVAGE3D) { + info->video_base = map_phys_mem(pci_info.base0, info->chip.fbsize); + info->picture_offset = 1024*768* 4 * ((info->chip.fbsize > 4194304)?2:1); + } + else { + info->video_base = map_phys_mem(pci_info.base1, info->chip.fbsize); + info->picture_offset = info->chip.fbsize - FRAMEBUFFER_SIZE; +// info->picture_offset = 1024*1024* 4 * 2; + } + if ( info->video_base < 0 ){ + printf("errno = %s\n", strerror(errno)); + return -1; + } + + + info->picture_base = (uint32_t) info->video_base + info->picture_offset; + + if ( info->chip.arch == S3_SAVAGE3D ){ + mtrr = mtrr_set_type(pci_info.base0, info->chip.fbsize, MTRR_TYPE_WRCOMB); + } + else{ + mtrr = mtrr_set_type(pci_info.base1, info->chip.fbsize, MTRR_TYPE_WRCOMB); + } + + if (mtrr!= 0) + printf("[savage_vid] unable to setup MTRR: %s\n", strerror(mtrr)); + else + printf("[savage_vid] MTRR set up\n"); + + /* This may trash your screen for resolutions greater than 1024x768, sorry. */ + + + savage_getscreenproperties(info); +// return -1; + info->videoFlags = 0; + + SavageStreamsOn(); + //getc(stdin); + //FIXME ADD + return 0; +} + +/** + * @brief Destroys driver. + */ +void +vixDestroy (void) +{ + unmap_phys_mem(info->video_base, info->chip.fbsize); + unmap_phys_mem(info->control_base, SAVAGE_NEWMMIO_REGSIZE); + //FIXME ADD +} + +/** + * @brief Get chipset's hardware capabilities. + * + * @param to Pointer to the vidix_capability_t structure to be filled. + * + * @returns 0. + */ +int +vixGetCapability (vidix_capability_t * to) +{ + memcpy (to, &savage_cap, sizeof (vidix_capability_t)); + return 0; +} + +/** + * @brief Report if the video FourCC is supported by hardware. + * + * @param fourcc input image format. + * + * @returns 1 if the fourcc is supported. + * 0 otherwise. + */ +static int +is_supported_fourcc (uint32_t fourcc) +{ + switch (fourcc) + { +//FIXME: YV12 isnt working properly yet +// case IMGFMT_YV12: +// case IMGFMT_I420: + case IMGFMT_UYVY: + case IMGFMT_YVYU: + case IMGFMT_YUY2: + case IMGFMT_RGB15: + case IMGFMT_RGB16: +// case IMGFMT_BGR32: + return 1; + default: + return 0; + } +} + +/** + * @brief Try to configure video memory for given fourcc. + * + * @param to Pointer to the vidix_fourcc_t structure to be filled. + * + * @returns 0 if ok. + * errno otherwise. + */ +int +vixQueryFourcc (vidix_fourcc_t * to) +{ + if (is_supported_fourcc (to->fourcc)) + { + to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | + VID_DEPTH_4BPP | VID_DEPTH_8BPP | + VID_DEPTH_12BPP | VID_DEPTH_15BPP | + VID_DEPTH_16BPP | VID_DEPTH_24BPP | VID_DEPTH_32BPP; + to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; + return 0; + } + else + to->depth = to->flags = 0; + + return ENOSYS; +} + +/** + * @brief Get the GrKeys + * + * @param grkey Pointer to the vidix_grkey_t structure to be filled by driver. + * + * @return 0. + */ +/*int +vixGetGrKeys (vidix_grkey_t * grkey) +{ + +// if(info->d_width && info->d_height)savage_overlay_start(info,0); + + return (0); +} + * */ + +/** + * @brief Set the GrKeys + * + * @param grkey Colorkey to be set. + * + * @return 0. + */ +int +vixSetGrKeys (const vidix_grkey_t * grkey) +{ + if (grkey->ckey.op == CKEY_FALSE) + { + info->use_colorkey = 0; + info->vidixcolorkey=0; + printf("[savage_vid] colorkeying disabled\n"); + } + else { + info->use_colorkey = 1; + info->vidixcolorkey = ((grkey->ckey.red<<16)|(grkey->ckey.green<<8)|grkey->ckey.blue); + + printf("[savage_vid] set colorkey 0x%x\n",info->vidixcolorkey); + } + //FIXME: freezes if streams arent enabled + SavageSetColorKeyOld(); + return (0); +} + +/** + * @brief Unichrome driver equalizer capabilities. + */ +vidix_video_eq_t equal = { + VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION | VEQ_CAP_HUE, + 300, 100, 0, 0, 0, 0, 0, 0 +}; + + +/** + * @brief Get the equalizer capabilities. + * + * @param eq Pointer to the vidix_video_eq_t structure to be filled by driver. + * + * @return 0. + */ +int +vixPlaybackGetEq (vidix_video_eq_t * eq) +{ + memcpy (eq, &equal, sizeof (vidix_video_eq_t)); + return 0; +} + +/** + * @brief Set the equalizer capabilities for color correction + * + * @param eq equalizer capabilities to be set. + * + * @return 0. + */ +int +vixPlaybackSetEq (const vidix_video_eq_t * eq) +{ + return 0; +} + +/** + * @brief Y, U, V offsets. + */ +static int YOffs, UOffs, VOffs; + +/** + * @brief Configure driver for playback. Driver should prepare BES. + * + * @param info configuration description for playback. + * + * @returns 0 in case of success. + * -1 otherwise. + */ +int +vixConfigPlayback (vidix_playback_t * vinfo) +{ + int uv_size, swap_uv; + unsigned int i; + int extfifo_on; + int srcPitch,srcPitch2; + + /* Overlay register settings */ + uint32_t win_start, win_end; + uint32_t zoom, mini; + uint32_t dcount, falign, qwfetch; + uint32_t y_start, u_start, v_start; + uint32_t v_ctrl, fifo_ctrl; + + if (!is_supported_fourcc (vinfo->fourcc)) + return -1; + + + + info->src_w = vinfo->src.w; + info->src_h = vinfo->src.h; + + info->drw_w = vinfo->dest.w; + info->drw_h = vinfo->dest.h; + + info->wx = vinfo->dest.x; + info->wy = vinfo->dest.y; + info->format = vinfo->fourcc; + + info->lastKnownPitch = 0; + info->brightness = 0; + info->contrast = 128; + info->saturation = 128; + info->hue = 0; + + + vinfo->dga_addr=(void*)(info->picture_base); + + + vinfo->offset.y = 0; + vinfo->offset.v = 0; + vinfo->offset.u = 0; + + vinfo->dest.pitch.y = 32; + vinfo->dest.pitch.u = 32; + vinfo->dest.pitch.v = 32; + // vinfo->dest.pitch.u = 0; + // vinfo->dest.pitch.v = 0; + + + info->pitch = ((info->src_w << 1) + 15) & ~15; + + swap_uv = 0; + switch (vinfo->fourcc) + { + case IMGFMT_YUY2: + case IMGFMT_UYVY: + + info->pitch = ((info->src_w << 1) + (vinfo->dest.pitch.y-1)) & ~(vinfo->dest.pitch.y-1); + + info->pitch = info->src_w << 1; + info->pitch = ALIGN_TO (info->src_w << 1, 32); + uv_size = 0; + break; + case IMGFMT_YV12: + swap_uv = 1; + + + + /* + srcPitch = (info->src_w + 3) & ~3; + vinfo->offset.u = srcPitch * info->src_h; + srcPitch2 = ((info->src_w >> 1) + 3) & ~3; + vinfo->offset.v = (srcPitch2 * (info->src_h >> 1)) + vinfo->offset.v; + + vinfo->dest.pitch.y=srcPitch ; + vinfo->dest.pitch.v=srcPitch2 ; + vinfo->dest.pitch.u=srcPitch2 ; + */ + + + info->pitch = ALIGN_TO (info->src_w, 32); + uv_size = (info->pitch >> 1) * (info->src_h >> 1); + + vinfo->offset.y = 0; + vinfo->offset.v = vinfo->offset.y + info->pitch * info->src_h; + vinfo->offset.u = vinfo->offset.v + uv_size; + vinfo->frame_size = vinfo->offset.u + uv_size; +/* YOffs = info->offset.y; + UOffs = (swap_uv ? vinfo->offset.v : vinfo->offset.u); + VOffs = (swap_uv ? vinfo->offset.u : vinfo->offset.v); + */ +// vinfo->offset.y = info->src_w; +// vinfo->offset.v = vinfo->offset.y + info->src_w /2 * info->src_h; +// vinfo->offset.u = vinfo->offset.v + (info->src_w >> 1) * (info->src_h >> 1) ; + + break; + } + info->pitch |= ((info->pitch >> 1) << 16); + + vinfo->frame_size = info->pitch * info->src_h; + + printf("$#### destination pitch = %u\n", info->pitch&0xffff); + + + + + info->buffer_size = vinfo->frame_size; + info->num_frames = vinfo->num_frames= (info->chip.fbsize - info->picture_offset)/vinfo->frame_size; + if(vinfo->num_frames > MAX_FRAMES)vinfo->num_frames = MAX_FRAMES; +// vinfo->num_frames = 1; +// printf("[nvidia_vid] Number of frames %i\n",vinfo->num_frames); + for(i=0;i <vinfo->num_frames;i++)vinfo->offsets[i] = vinfo->frame_size*i; + + return 0; +} + +/** + * @brief Set playback on : driver should activate BES on this call. + * + * @return 0. + */ +int +vixPlaybackOn (void) +{ + // FIXME: enable + SavageDisplayVideoOld(); +//FIXME ADD + return 0; +} + +/** + * @brief Set playback off : driver should deactivate BES on this call. + * + * @return 0. + */ +int +vixPlaybackOff (void) +{ + // otherwise we wont disable streams properly in new xorg + // FIXME: shouldnt this be enabled? +// SavageStreamsOn(); + SavageStreamsOff(); +// info->vidixcolorkey=0x0; + +// OUTREG( SSTREAM_WINDOW_START_REG, OS_XY(0xfffe, 0xfffe) ); +// SavageSetColorKeyOld(); +//FIXME ADD + return 0; +} + +/** + * @brief Driver should prepare and activate corresponded frame. + * + * @param frame the frame index. + * + * @return 0. + * + * @note This function is used only for double and triple buffering + * and never used for single buffering playback. + */ +#if 0 +int +vixPlaybackFrameSelect (unsigned int frame) +{ +////FIXME ADD +// savage_overlay_start(info, frame); + //if (info->num_frames >= 1) +// info->cur_frame = frame//(frame+1)%info->num_frames; +// +// savage4_waitidle(info); + + printf("vixPlaybackFrameSelect Leave\n" ); + // FIXME: does this work to avoid tearing? +// VerticalRetraceWait(); + + return 0; +} + +#endif + + + +void debugout(unsigned int addr, unsigned int val){ + return ; + switch ( addr ){ + case PSTREAM_CONTROL_REG: + fprintf(stderr,"PSTREAM_CONTROL_REG"); + break; + case COL_CHROMA_KEY_CONTROL_REG: + fprintf(stderr,"COL_CHROMA_KEY_CONTROL_REG"); + break; + case SSTREAM_CONTROL_REG: + fprintf(stderr,"SSTREAM_CONTROL_REG"); + break; + case CHROMA_KEY_UPPER_BOUND_REG: + fprintf(stderr,"CHROMA_KEY_UPPER_BOUND_REG"); + break; + case SSTREAM_STRETCH_REG: + fprintf(stderr,"SSTREAM_STRETCH_REG"); + break; + case COLOR_ADJUSTMENT_REG: + fprintf(stderr,"COLOR_ADJUSTMENT_REG"); + break; + case BLEND_CONTROL_REG: + fprintf(stderr,"BLEND_CONTROL_REG"); + break; + case PSTREAM_FBADDR0_REG: + fprintf(stderr,"PSTREAM_FBADDR0_REG"); + break; + case PSTREAM_FBADDR1_REG: + fprintf(stderr,"PSTREAM_FBADDR1_REG"); + break; + case PSTREAM_STRIDE_REG: + fprintf(stderr,"PSTREAM_STRIDE_REG"); + break; + case DOUBLE_BUFFER_REG: + fprintf(stderr,"DOUBLE_BUFFER_REG"); + break; + case SSTREAM_FBADDR0_REG: + fprintf(stderr,"SSTREAM_FBADDR0_REG"); + break; + case SSTREAM_FBADDR1_REG: + fprintf(stderr,"SSTREAM_FBADDR1_REG"); + break; + case SSTREAM_STRIDE_REG: + fprintf(stderr,"SSTREAM_STRIDE_REG"); + break; + case SSTREAM_VSCALE_REG: + fprintf(stderr,"SSTREAM_VSCALE_REG"); + break; + case SSTREAM_VINITIAL_REG: + fprintf(stderr,"SSTREAM_VINITIAL_REG"); + break; + case SSTREAM_LINES_REG: + fprintf(stderr,"SSTREAM_LINES_REG"); + break; + case STREAMS_FIFO_REG: + fprintf(stderr,"STREAMS_FIFO_REG"); + break; + case PSTREAM_WINDOW_START_REG: + fprintf(stderr,"PSTREAM_WINDOW_START_REG"); + break; + case PSTREAM_WINDOW_SIZE_REG: + fprintf(stderr,"PSTREAM_WINDOW_SIZE_REG"); + break; + case SSTREAM_WINDOW_START_REG: + fprintf(stderr,"SSTREAM_WINDOW_START_REG"); + break; + case SSTREAM_WINDOW_SIZE_REG: + fprintf(stderr,"SSTREAM_WINDOW_SIZE_REG"); + break; + case FIFO_CONTROL: + fprintf(stderr,"FIFO_CONTROL"); + break; + case PSTREAM_FBSIZE_REG: + fprintf(stderr,"PSTREAM_FBSIZE_REG"); + break; + case SSTREAM_FBSIZE_REG: + fprintf(stderr,"SSTREAM_FBSIZE_REG"); + break; + case SSTREAM_FBADDR2_REG: + fprintf(stderr,"SSTREAM_FBADDR2_REG"); + break; + + } + fprintf(stderr,":\t\t 0x%08X = %u\n",val,val); +} + +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/vidix/sis_bridge.c Sun Apr 01 00:02:43 2007 +0000 @@ -0,0 +1,827 @@ +/** + Video bridge detection for SiS 300 and 310/325 series chips. + + Copyright 2003 Jake Page, Sugar Media. + + Based on SiS Xv driver: + Copyright 2002-2003 by Thomas Winischhofer, Vienna, Austria. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + +**/ + +#include <stdio.h> +#include <stdlib.h> +#include <unistd.h> + +#include "../libdha/libdha.h" +#include "sis_regs.h" +#include "sis_defs.h" + + +static void sis_ddc2_delay(unsigned short delaytime) +{ + unsigned short i; + int temp; + + for (i = 0; i < delaytime; i++) { + inSISIDXREG(SISSR, 0x05, temp); + } +} + + +static int sis_do_sense(int tempbl, int tempbh, int tempcl, int tempch) +{ + int temp; + + outSISIDXREG(SISPART4, 0x11, tempbl); + temp = tempbh | tempcl; + setSISIDXREG(SISPART4, 0x10, 0xe0, temp); + //usleep(200000); + sis_ddc2_delay(0x1000); + tempch &= 0x7f; + inSISIDXREG(SISPART4, 0x03, temp); + temp ^= 0x0e; + temp &= tempch; + return (temp == tempch); +} + + +/* sense connected devices on 30x bridge */ +static void sis_sense_30x(void) +{ + unsigned char backupP4_0d, backupP2_00, biosflag; + unsigned char testsvhs_tempbl, testsvhs_tempbh; + unsigned char testsvhs_tempcl, testsvhs_tempch; + unsigned char testcvbs_tempbl, testcvbs_tempbh; + unsigned char testcvbs_tempcl, testcvbs_tempch; + unsigned char testvga2_tempbl, testvga2_tempbh; + unsigned char testvga2_tempcl, testvga2_tempch; + int myflag, result = 0, i, j, haveresult; + unsigned short temp; + + inSISIDXREG(SISPART4, 0x0d, backupP4_0d); + outSISIDXREG(SISPART4, 0x0d, (backupP4_0d | 0x04)); + + inSISIDXREG(SISPART2, 0x00, backupP2_00); + outSISIDXREG(SISPART2, 0x00, (backupP2_00 | 0x1c)); + + sis_do_sense(0, 0, 0, 0); + + if ((sis_vga_engine == SIS_315_VGA) || + (sis_device_id == DEVICE_SIS_300)) { +#if 0 + if (0 /*pSiS->sishw_ext.UseROM */ ) { + if (sis_vga_engine == SIS_300_VGA) + temp = 0xfe; + else { + temp = 0xf3; + if (sis_device_id == DEVICE_SIS_330) + temp = 0x11b; + } + if (pSiS->BIOS[temp] & 0x08) { + if (sis_verbose > 1) { + printf + ("[SiS] SiS30x: Video bridge has DVI-I TMDS/VGA combo connector\n"); + } + orSISIDXREG(SISCR, 0x32, 0x80); + } else { + andSISIDXREG(SISCR, 0x32, 0x7f); + } + } +#endif + } + + if (sis_vga_engine == SIS_300_VGA) { + if (0 /*pSiS->sishw_ext.UseROM */ ) { +#if 0 + testvga2_tempbh = pSiS->BIOS[0xf9]; + testvga2_tempbl = pSiS->BIOS[0xf8]; + testsvhs_tempbh = pSiS->BIOS[0xfb]; + testsvhs_tempbl = pSiS->BIOS[0xfa]; + testcvbs_tempbh = pSiS->BIOS[0xfd]; + testcvbs_tempbl = pSiS->BIOS[0xfc]; + biosflag = pSiS->BIOS[0xfe]; +#endif + } else { + testvga2_tempbh = 0x00; + testvga2_tempbl = 0xd1; + testsvhs_tempbh = 0x00; + testsvhs_tempbl = 0xb9; + testcvbs_tempbh = 0x00; + testcvbs_tempbl = 0xb3; + biosflag = 0; + } + if (sis_vbflags & (VB_301B | VB_302B | VB_301LV | VB_302LV)) { + testvga2_tempbh = 0x01; + testvga2_tempbl = 0x90; + testsvhs_tempbh = 0x01; + testsvhs_tempbl = 0x6b; + testcvbs_tempbh = 0x01; + testcvbs_tempbl = 0x74; + } + inSISIDXREG(SISPART4, 0x01, myflag); + if (myflag & 0x04) { + testvga2_tempbh = 0x00; + testvga2_tempbl = 0xfd; + testsvhs_tempbh = 0x00; + testsvhs_tempbl = 0xdd; + testcvbs_tempbh = 0x00; + testcvbs_tempbl = 0xee; + } + testvga2_tempch = 0x0e; + testvga2_tempcl = 0x08; + testsvhs_tempch = 0x06; + testsvhs_tempcl = 0x04; + testcvbs_tempch = 0x08; + testcvbs_tempcl = 0x04; + + if (sis_device_id == DEVICE_SIS_300) { + inSISIDXREG(SISSR, 0x3b, myflag); + if (!(myflag & 0x01)) { + testvga2_tempbh = 0x00; + testvga2_tempbl = 0x00; + testvga2_tempch = 0x00; + testvga2_tempcl = 0x00; + } + } + } else { + if (0 /*pSiS->sishw_ext.UseROM */ ) { +#if 0 + if (sis_device_id == DEVICE_SIS_330) { + testvga2_tempbh = pSiS->BIOS[0xe6]; + testvga2_tempbl = pSiS->BIOS[0xe5]; + testsvhs_tempbh = pSiS->BIOS[0xe8]; + testsvhs_tempbl = pSiS->BIOS[0xe7]; + testcvbs_tempbh = pSiS->BIOS[0xea]; + testcvbs_tempbl = pSiS->BIOS[0xe9]; + biosflag = pSiS->BIOS[0x11b]; + } else { + testvga2_tempbh = pSiS->BIOS[0xbe]; + testvga2_tempbl = pSiS->BIOS[0xbd]; + testsvhs_tempbh = pSiS->BIOS[0xc0]; + testsvhs_tempbl = pSiS->BIOS[0xbf]; + testcvbs_tempbh = pSiS->BIOS[0xc2]; + testcvbs_tempbl = pSiS->BIOS[0xc1]; + biosflag = pSiS->BIOS[0xf3]; + } +#endif + } else { + testvga2_tempbh = 0x00; + testvga2_tempbl = 0xd1; + testsvhs_tempbh = 0x00; + testsvhs_tempbl = 0xb9; + testcvbs_tempbh = 0x00; + testcvbs_tempbl = 0xb3; + biosflag = 0; + } + + if (sis_vbflags & (VB_301B | VB_302B | VB_301LV | VB_302LV)) { + if (0 /*pSiS->sishw_ext.UseROM */ ) { +#if 0 + if (sis_device_id == DEVICE_SIS_330) { + testvga2_tempbh = pSiS->BIOS[0xec]; + testvga2_tempbl = pSiS->BIOS[0xeb]; + testsvhs_tempbh = pSiS->BIOS[0xee]; + testsvhs_tempbl = pSiS->BIOS[0xed]; + testcvbs_tempbh = pSiS->BIOS[0xf0]; + testcvbs_tempbl = pSiS->BIOS[0xef]; + } else { + testvga2_tempbh = pSiS->BIOS[0xc4]; + testvga2_tempbl = pSiS->BIOS[0xc3]; + testsvhs_tempbh = pSiS->BIOS[0xc6]; + testsvhs_tempbl = pSiS->BIOS[0xc5]; + testcvbs_tempbh = pSiS->BIOS[0xc8]; + testcvbs_tempbl = pSiS->BIOS[0xc7]; + } +#endif + } else { + if (sis_vbflags & (VB_301B | VB_302B)) { + testvga2_tempbh = 0x01; + testvga2_tempbl = 0x90; + testsvhs_tempbh = 0x01; + testsvhs_tempbl = 0x6b; + testcvbs_tempbh = 0x01; + testcvbs_tempbl = 0x74; + } else { + testvga2_tempbh = 0x00; + testvga2_tempbl = 0x00; + testsvhs_tempbh = 0x02; + testsvhs_tempbl = 0x00; + testcvbs_tempbh = 0x01; + testcvbs_tempbl = 0x00; + } + } + } + if (sis_vbflags & (VB_301 | VB_301B | VB_302B)) { + inSISIDXREG(SISPART4, 0x01, myflag); + if (myflag & 0x04) { + testvga2_tempbh = 0x00; + testvga2_tempbl = 0xfd; + testsvhs_tempbh = 0x00; + testsvhs_tempbl = 0xdd; + testcvbs_tempbh = 0x00; + testcvbs_tempbl = 0xee; + } + } + if (sis_vbflags & (VB_301LV | VB_302LV)) { + /* TW: No VGA2 or SCART on LV bridges */ + testvga2_tempbh = 0x00; + testvga2_tempbl = 0x00; + testvga2_tempch = 0x00; + testvga2_tempcl = 0x00; + testsvhs_tempch = 0x04; + testsvhs_tempcl = 0x08; + testcvbs_tempch = 0x08; + testcvbs_tempcl = 0x08; + } else { + testvga2_tempch = 0x0e; + testvga2_tempcl = 0x08; + testsvhs_tempch = 0x06; + testsvhs_tempcl = 0x04; + testcvbs_tempch = 0x08; + testcvbs_tempcl = 0x04; + } + } + + /* XXX: ?? andSISIDXREG(SISCR, 0x32, ~0x14); */ + /* pSiS->postVBCR32 &= ~0x14; */ + + /* scan for VGA2/SCART */ + if (testvga2_tempch || testvga2_tempcl || + testvga2_tempbh || testvga2_tempbl) { + + haveresult = 0; + for (j = 0; j < 10; j++) { + result = 0; + for (i = 0; i < 3; i++) { + if (sis_do_sense(testvga2_tempbl, testvga2_tempbh, + testvga2_tempcl, testvga2_tempch)) + result++; + } + if ((result == 0) || (result >= 2)) + break; + } + if (result) { + if (biosflag & 0x01) { + if (sis_verbose > 1) { + printf + ("[SiS] SiS30x: Detected TV connected to SCART output\n"); + } + sis_vbflags |= TV_SCART; + orSISIDXREG(SISCR, 0x32, 0x04); + /*pSiS->postVBCR32 |= 0x04; */ + } else { + if (sis_verbose > 1) { + printf + ("[SiS] SiS30x: Detected secondary VGA connection\n"); + } + sis_vbflags |= VGA2_CONNECTED; + orSISIDXREG(SISCR, 0x32, 0x10); + /*pSiS->postVBCR32 |= 0x10; */ + } + } + } + + /* scanning for TV */ + + /* XXX: ?? andSISIDXREG(SISCR, 0x32, ~0x03); */ + /* pSiS->postVBCR32 &= ~0x03; */ + + result = sis_do_sense(testsvhs_tempbl, testsvhs_tempbh, + testsvhs_tempcl, testsvhs_tempch); + + + haveresult = 0; + for (j = 0; j < 10; j++) { + result = 0; + for (i = 0; i < 3; i++) { + if (sis_do_sense(testsvhs_tempbl, testsvhs_tempbh, + testsvhs_tempcl, testsvhs_tempch)) + result++; + } + if ((result == 0) || (result >= 2)) + break; + } + if (result) { + if (sis_verbose > 1) { + printf + ("[SiS] SiS30x: Detected TV connected to SVIDEO output\n"); + } + /* TW: So we can be sure that there IS a SVIDEO output */ + sis_vbflags |= TV_SVIDEO; + orSISIDXREG(SISCR, 0x32, 0x02); + //pSiS->postVBCR32 |= 0x02; + } + + if ((biosflag & 0x02) || (!(result))) { + haveresult = 0; + for (j = 0; j < 10; j++) { + result = 0; + for (i = 0; i < 3; i++) { + if (sis_do_sense(testcvbs_tempbl, testcvbs_tempbh, + testcvbs_tempcl, testcvbs_tempch)) + result++; + } + if ((result == 0) || (result >= 2)) + break; + } + if (result) { + if (sis_verbose > 1) { + printf + ("[SiS] SiS30x: Detected TV connected to COMPOSITE output\n"); + } + sis_vbflags |= TV_AVIDEO; + orSISIDXREG(SISCR, 0x32, 0x01); + //pSiS->postVBCR32 |= 0x01; + } + } + + sis_do_sense(0, 0, 0, 0); + + outSISIDXREG(SISPART2, 0x00, backupP2_00); + outSISIDXREG(SISPART4, 0x0d, backupP4_0d); +} + + +static void sis_detect_crt1(void) +{ + unsigned char CR32; + unsigned char CRT1Detected = 0; + unsigned char OtherDevices = 0; + + if (!(sis_vbflags & VB_VIDEOBRIDGE)) { + sis_crt1_off = 0; + return; + } + + inSISIDXREG(SISCR, 0x32, CR32); + + if (CR32 & 0x20) + CRT1Detected = 1; + if (CR32 & 0x5F) + OtherDevices = 1; + + if (sis_crt1_off == -1) { + if (!CRT1Detected) { + /* BIOS detected no CRT1. */ + /* If other devices exist, switch it off */ + if (OtherDevices) + sis_crt1_off = 1; + else + sis_crt1_off = 0; + } else { + /* BIOS detected CRT1, leave/switch it on */ + sis_crt1_off = 0; + } + } + if (sis_verbose > 0) { + printf("[SiS] %sCRT1 connection detected\n", + sis_crt1_off ? "No " : ""); + } +} + + +static void sis_detect_lcd(void) +{ + unsigned char CR32, CR36, CR37; + + if (!(sis_vbflags & VB_VIDEOBRIDGE)) { + return; + } + + inSISIDXREG(SISCR, 0x32, CR32); + + if (CR32 & 0x08) + sis_vbflags |= CRT2_LCD; + + /* DDC detection of LCD - not supported yet */ + + /* Get other misc info about LCD - not supported */ +} + + +static void sis_detect_tv(void) +{ + unsigned char SR16, SR38, CR32, CR38 = 0, CR79; + int temp = 0; + + if (!(sis_vbflags & VB_VIDEOBRIDGE)) + return; + + inSISIDXREG(SISCR, 0x32, CR32); + inSISIDXREG(SISSR, 0x16, SR16); + inSISIDXREG(SISSR, 0x38, SR38); + switch (sis_vga_engine) { + case SIS_300_VGA: + if (sis_device_id == DEVICE_SIS_630_VGA) + temp = 0x35; + break; + case SIS_315_VGA: + temp = 0x38; + break; + } + if (temp) { + inSISIDXREG(SISCR, temp, CR38); + } + + if (CR32 & 0x47) + sis_vbflags |= CRT2_TV; + + if (CR32 & 0x04) + sis_vbflags |= TV_SCART; + else if (CR32 & 0x02) + sis_vbflags |= TV_SVIDEO; + else if (CR32 & 0x01) + sis_vbflags |= TV_AVIDEO; + else if (CR32 & 0x40) + sis_vbflags |= (TV_SVIDEO | TV_HIVISION); + else if ((CR38 & 0x04) && (sis_vbflags & (VB_301LV | VB_302LV))) + sis_vbflags |= TV_HIVISION_LV; + else if ((CR38 & 0x04) && (sis_vbflags & VB_CHRONTEL)) + sis_vbflags |= (TV_CHSCART | TV_PAL); + else if ((CR38 & 0x08) && (sis_vbflags & VB_CHRONTEL)) + sis_vbflags |= (TV_CHHDTV | TV_NTSC); + + if (sis_vbflags & (TV_SCART | TV_SVIDEO | TV_AVIDEO | TV_HIVISION)) { + if (sis_vga_engine == SIS_300_VGA) { + /* TW: Should be SR38 here as well, but this + * does not work. Looks like a BIOS bug (2.04.5c). + */ + if (SR16 & 0x20) + sis_vbflags |= TV_PAL; + else + sis_vbflags |= TV_NTSC; + } else if ((sis_device_id == DEVICE_SIS_550_VGA)) { + inSISIDXREG(SISCR, 0x79, CR79); + if (CR79 & 0x08) { + inSISIDXREG(SISCR, 0x79, CR79); + CR79 >>= 5; + } + if (CR79 & 0x01) { + sis_vbflags |= TV_PAL; + if (CR38 & 0x40) + sis_vbflags |= TV_PALM; + else if (CR38 & 0x80) + sis_vbflags |= TV_PALN; + } else + sis_vbflags |= TV_NTSC; + } else if ((sis_device_id == DEVICE_SIS_650_VGA)) { + inSISIDXREG(SISCR, 0x79, CR79); + if (CR79 & 0x20) { + sis_vbflags |= TV_PAL; + if (CR38 & 0x40) + sis_vbflags |= TV_PALM; + else if (CR38 & 0x80) + sis_vbflags |= TV_PALN; + } else + sis_vbflags |= TV_NTSC; + } else { /* 315, 330 */ + if (SR38 & 0x01) { + sis_vbflags |= TV_PAL; + if (CR38 & 0x40) + sis_vbflags |= TV_PALM; + else if (CR38 & 0x80) + sis_vbflags |= TV_PALN; + } else + sis_vbflags |= TV_NTSC; + } + } + + if (sis_vbflags & + (TV_SCART | TV_SVIDEO | TV_AVIDEO | TV_HIVISION | TV_CHSCART | + TV_CHHDTV)) { + if (sis_verbose > 0) { + printf("[SiS] %sTV standard %s\n", + (sis_vbflags & (TV_CHSCART | TV_CHHDTV)) ? "Using " : + "Detected default ", + (sis_vbflags & TV_NTSC) ? ((sis_vbflags & TV_CHHDTV) ? + "480i HDTV" : "NTSC") + : ((sis_vbflags & TV_PALM) ? "PALM" + : ((sis_vbflags & TV_PALN) ? "PALN" : "PAL"))); + } + } + +} + + +static void sis_detect_crt2(void) +{ + unsigned char CR32; + + if (!(sis_vbflags & VB_VIDEOBRIDGE)) + return; + + /* CRT2-VGA not supported on LVDS and 30xLV */ + if (sis_vbflags & (VB_LVDS | VB_301LV | VB_302LV)) + return; + + inSISIDXREG(SISCR, 0x32, CR32); + + if (CR32 & 0x10) + sis_vbflags |= CRT2_VGA; + +#if 0 + if (!(pSiS->nocrt2ddcdetection)) { + if (sis_vbflags & (VB_301B | VB_302B)) { + if (!(sis_vbflags & (CRT2_VGA | CRT2_LCD))) { + printf + ("[SiS] BIOS detected no secondary VGA, sensing via DDC\n"); + if (SiS_SenseVGA2DDC(pSiS->SiS_Pr, pSiS)) { + printf + ("[SiS] DDC error during secondary VGA detection\n"); + } else { + inSISIDXREG(SISCR, 0x32, CR32); + if (CR32 & 0x10) { + sis_vbflags |= CRT2_VGA; + /*pSiS->postVBCR32 |= 0x10; */ + printf + ("[SiS] Detected secondary VGA connection\n"); + } else { + printf + ("[SiS] No secondary VGA connection detected\n"); + } + } + } + } + } +#endif + +} + + +/* Preinit: detect video bridge and sense connected devs */ +static void sis_detect_video_bridge(void) +{ + int temp, temp1, temp2; + + + sis_vbflags = 0; + + if (sis_vga_engine != SIS_300_VGA && sis_vga_engine != SIS_315_VGA) + return; + + inSISIDXREG(SISPART4, 0x00, temp); + temp &= 0x0F; + if (temp == 1) { + inSISIDXREG(SISPART4, 0x01, temp1); + temp1 &= 0xff; + if (temp1 >= 0xE0) { + sis_vbflags |= VB_302LV; + //pSiS->sishw_ext.ujVBChipID = VB_CHIP_302LV; + if (sis_verbose > 1) { + printf + ("[SiS] Detected SiS302LV video bridge (ID 1; Revision 0x%x)\n", + temp1); + } + + } else if (temp1 >= 0xD0) { + sis_vbflags |= VB_301LV; + //pSiS->sishw_ext.ujVBChipID = VB_CHIP_301LV; + if (sis_verbose > 1) { + printf + ("[SiS] Detected SiS301LV video bridge (ID 1; Revision 0x%x)\n", + temp1); + } + } else if (temp1 >= 0xB0) { + sis_vbflags |= VB_301B; + //pSiS->sishw_ext.ujVBChipID = VB_CHIP_301B; + inSISIDXREG(SISPART4, 0x23, temp2); + if (!(temp2 & 0x02)) + sis_vbflags |= VB_30xBDH; + if (sis_verbose > 1) { + printf + ("[SiS] Detected SiS301B%s video bridge (Revision 0x%x)\n", + (temp2 & 0x02) ? "" : " (DH)", temp1); + } + } else { + sis_vbflags |= VB_301; + //pSiS->sishw_ext.ujVBChipID = VB_CHIP_301; + if (sis_verbose > 1) { + printf + ("[SiS] Detected SiS301 video bridge (Revision 0x%x)\n", + temp1); + } + } + + sis_sense_30x(); + + } else if (temp == 2) { + + inSISIDXREG(SISPART4, 0x01, temp1); + temp1 &= 0xff; + if (temp1 >= 0xE0) { + sis_vbflags |= VB_302LV; + //pSiS->sishw_ext.ujVBChipID = VB_CHIP_302LV; + if (sis_verbose > 1) { + printf + ("[SiS] Detected SiS302LV video bridge (ID 2; Revision 0x%x)\n", + temp1); + } + } else if (temp1 >= 0xD0) { + sis_vbflags |= VB_301LV; + //pSiS->sishw_ext.ujVBChipID = VB_CHIP_301LV; + if (sis_verbose > 1) { + printf + ("[SiS] Detected SiS301LV video bridge (ID 2; Revision 0x%x)\n", + temp1); + } + } else { + sis_vbflags |= VB_302B; + //pSiS->sishw_ext.ujVBChipID = VB_CHIP_302B; + inSISIDXREG(SISPART4, 0x23, temp2); + if (!(temp & 0x02)) + sis_vbflags |= VB_30xBDH; + if (sis_verbose > 1) { + printf + ("[SiS] Detected SiS302B%s video bridge (Revision 0x%x)\n", + (temp2 & 0x02) ? "" : " (DH)", temp1); + } + } + + sis_sense_30x(); + + } else if (temp == 3) { + if (sis_verbose > 1) { + printf("[SiS] Detected SiS303 video bridge - not supported\n"); + } + } else { + /* big scary mess of code to handle unknown or Chrontel LVDS */ + /* skipping it for now */ + if (sis_verbose > 1) { + printf + ("[SiS] Detected Chrontel video bridge - not supported\n"); + } + } + + /* this is probably not relevant to video overlay driver... */ + /* detects if brdige uses LCDA for low res text modes */ + if (sis_vga_engine == SIS_315_VGA) { + if (sis_vbflags & (VB_302B | VB_301LV | VB_302LV)) { +#if 0 + if (pSiS->sisfblcda != 0xff) { + if ((pSiS->sisfblcda & 0x03) == 0x03) { + //pSiS->SiS_Pr->SiS_UseLCDA = TRUE; + sis_vbflags |= VB_USELCDA; + } + } else +#endif + { + inSISIDXREG(SISCR, 0x34, temp); + if (temp <= 0x13) { + inSISIDXREG(SISCR, 0x38, temp); + if ((temp & 0x03) == 0x03) { + //pSiS->SiS_Pr->SiS_UseLCDA = TRUE; + sis_vbflags |= VB_USELCDA; + } else { + inSISIDXREG(SISCR, 0x30, temp); + if (temp & 0x20) { + inSISIDXREG(SISPART1, 0x13, temp); + if (temp & 0x40) { + //pSiS->SiS_Pr->SiS_UseLCDA = TRUE; + sis_vbflags |= VB_USELCDA; + } + } + } + } + } + if (sis_vbflags & VB_USELCDA) { + /* printf("Bridge uses LCDA for low resolution and text modes\n"); */ + } + } + } + + +} + + +/* detect video bridge type and sense connected devices */ +void sis_init_video_bridge(void) +{ + + sis_detect_video_bridge(); + + sis_detect_crt1(); + //sis_detect_lcd(); + sis_detect_tv(); + sis_detect_crt2(); + + sis_detected_crt2_devices = + sis_vbflags & (CRT2_LCD | CRT2_TV | CRT2_VGA); + + // force crt2 type + if (sis_force_crt2_type == CRT2_DEFAULT) { + if (sis_vbflags & CRT2_VGA) + sis_force_crt2_type = CRT2_VGA; + else if (sis_vbflags & CRT2_LCD) + sis_force_crt2_type = CRT2_LCD; + else if (sis_vbflags & CRT2_TV) + sis_force_crt2_type = CRT2_TV; + } + + switch (sis_force_crt2_type) { + case CRT2_TV: + sis_vbflags = sis_vbflags & ~(CRT2_LCD | CRT2_VGA); + if (sis_vbflags & VB_VIDEOBRIDGE) + sis_vbflags = sis_vbflags | CRT2_TV; + else + sis_vbflags = sis_vbflags & ~(CRT2_TV); + break; + case CRT2_LCD: + sis_vbflags = sis_vbflags & ~(CRT2_TV | CRT2_VGA); + if ((sis_vbflags & VB_VIDEOBRIDGE) /* XXX: && (pSiS->VBLCDFlags) */ + ) + sis_vbflags = sis_vbflags | CRT2_LCD; + else { + sis_vbflags = sis_vbflags & ~(CRT2_LCD); + if (sis_verbose > 0) { + printf + ("[SiS] Can't force CRT2 to LCD, no panel detected\n"); + } + } + break; + case CRT2_VGA: + if (sis_vbflags & VB_LVDS) { + if (sis_verbose > 0) { + printf("[SiS] LVDS does not support secondary VGA\n"); + } + break; + } + if (sis_vbflags & (VB_301LV | VB_302LV)) { + if (sis_verbose > 0) { + printf + ("[SiS] SiS30xLV bridge does not support secondary VGA\n"); + } + break; + } + sis_vbflags = sis_vbflags & ~(CRT2_TV | CRT2_LCD); + if (sis_vbflags & VB_VIDEOBRIDGE) + sis_vbflags = sis_vbflags | CRT2_VGA; + else + sis_vbflags = sis_vbflags & ~(CRT2_VGA); + break; + default: + sis_vbflags &= ~(CRT2_TV | CRT2_LCD | CRT2_VGA); + } + + /* CRT2 gamma correction?? */ + + /* other force modes: */ + /* have a 'force tv type' (svideo, composite, scart) option? */ + /* have a 'force crt1 type' (to turn it off, etc??) */ + + /* TW: Check if CRT1 used (or needed; this eg. if no CRT2 detected) */ + if (sis_vbflags & VB_VIDEOBRIDGE) { + + /* TW: No CRT2 output? Then we NEED CRT1! + * We also need CRT1 if depth = 8 and bridge=LVDS|630+301B + */ + if ((!(sis_vbflags & (CRT2_VGA | CRT2_LCD | CRT2_TV))) || ( /*(pScrn->bitsPerPixel == 8) && */ + ((sis_vbflags & (VB_LVDS | VB_CHRONTEL)) || ((sis_vga_engine == SIS_300_VGA) && (sis_vbflags & VB_301B))))) { + sis_crt1_off = 0; + } + /* TW: No CRT2 output? Then we can't use hw overlay on CRT2 */ + if (!(sis_vbflags & (CRT2_VGA | CRT2_LCD | CRT2_TV))) + sis_overlay_on_crt1 = 1; + + } else { /* TW: no video bridge? */ + + /* Then we NEED CRT1... */ + sis_crt1_off = 0; + /* ... and can't use CRT2 for overlay output */ + sis_overlay_on_crt1 = 1; + } + + /* tvstandard options ? */ + + // determine using CRT1 or CRT2? + /* -> NO dualhead right now... */ + if (sis_vbflags & DISPTYPE_DISP2) { + if (sis_crt1_off) { + sis_vbflags |= VB_DISPMODE_SINGLE; + /* TW: No CRT1? Then we use the video overlay on CRT2 */ + sis_overlay_on_crt1 = 0; + } else /* TW: CRT1 and CRT2 - mirror or dual head ----- */ + sis_vbflags |= (VB_DISPMODE_MIRROR | DISPTYPE_CRT1); + } else { /* TW: CRT1 only ------------------------------- */ + sis_vbflags |= (VB_DISPMODE_SINGLE | DISPTYPE_CRT1); + } + + if (sis_verbose > 0) { + printf("[SiS] Using hardware overlay on CRT%d\n", + sis_overlay_on_crt1 ? 1 : 2); + } + +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/vidix/sis_defs.h Sun Apr 01 00:02:43 2007 +0000 @@ -0,0 +1,106 @@ +/** + SiS graphics misc definitions. + + Taken from SiS Xv driver: + Copyright 2002-2003 by Thomas Winischhofer, Vienna, Austria. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + +**/ + +#ifndef VIDIX_SIS_DEFS_H +#define VIDIX_SIS_DEFS_H + +/** PCI IDs **/ +#define VENDOR_SIS 0x1039 + +#define DEVICE_SIS_300 0x0300 +#define DEVICE_SIS_315H 0x0310 +#define DEVICE_SIS_315 0x0315 +#define DEVICE_SIS_315PRO 0x0325 +#define DEVICE_SIS_330 0x0330 +#define DEVICE_SIS_540 0x0540 +#define DEVICE_SIS_540_VGA 0x5300 +#define DEVICE_SIS_550 0x0550 +#define DEVICE_SIS_550_VGA 0x5315 +#define DEVICE_SIS_630 0x0630 +#define DEVICE_SIS_630_VGA 0x6300 +#define DEVICE_SIS_650 0x0650 +#define DEVICE_SIS_650_VGA 0x6325 +#define DEVICE_SIS_730 0x0730 + + +/* TW: VBFlags */ +#define CRT2_DEFAULT 0x00000001 +#define CRT2_LCD 0x00000002 /* TW: Never change the order of the CRT2_XXX entries */ +#define CRT2_TV 0x00000004 /* (see SISCycleCRT2Type()) */ +#define CRT2_VGA 0x00000008 +#define CRT2_ENABLE (CRT2_LCD | CRT2_TV | CRT2_VGA) +#define DISPTYPE_DISP2 CRT2_ENABLE +#define TV_NTSC 0x00000010 +#define TV_PAL 0x00000020 +#define TV_HIVISION 0x00000040 +#define TV_HIVISION_LV 0x00000080 +#define TV_TYPE (TV_NTSC | TV_PAL | TV_HIVISION | TV_HIVISION_LV) +#define TV_AVIDEO 0x00000100 +#define TV_SVIDEO 0x00000200 +#define TV_SCART 0x00000400 +#define TV_INTERFACE (TV_AVIDEO | TV_SVIDEO | TV_SCART | TV_CHSCART | TV_CHHDTV) +#define VB_USELCDA 0x00000800 +#define TV_PALM 0x00001000 +#define TV_PALN 0x00002000 +#define TV_CHSCART 0x00008000 +#define TV_CHHDTV 0x00010000 +#define VGA2_CONNECTED 0x00040000 +#define DISPTYPE_CRT1 0x00080000 /* TW: CRT1 connected and used */ +#define DISPTYPE_DISP1 DISPTYPE_CRT1 +#define VB_301 0x00100000 /* Video bridge type */ +#define VB_301B 0x00200000 +#define VB_302B 0x00400000 +#define VB_30xBDH 0x00800000 /* 30xB DH version (w/o LCD support) */ +#define VB_LVDS 0x01000000 +#define VB_CHRONTEL 0x02000000 +#define VB_301LV 0x04000000 +#define VB_302LV 0x08000000 +#define VB_30xLV VB_301LV +#define VB_30xLVX VB_302LV +#define VB_TRUMPION 0x10000000 +#define VB_VIDEOBRIDGE (VB_301|VB_301B|VB_302B|VB_301LV|VB_302LV| \ + VB_LVDS|VB_CHRONTEL|VB_TRUMPION) /* TW */ +#define VB_SISBRIDGE (VB_301|VB_301B|VB_302B|VB_301LV|VB_302LV) +#define SINGLE_MODE 0x20000000 /* TW: CRT1 or CRT2; determined by DISPTYPE_CRTx */ +#define VB_DISPMODE_SINGLE SINGLE_MODE /* TW: alias */ +#define MIRROR_MODE 0x40000000 /* TW: CRT1 + CRT2 identical (mirror mode) */ +#define VB_DISPMODE_MIRROR MIRROR_MODE /* TW: alias */ +#define DUALVIEW_MODE 0x80000000 /* TW: CRT1 + CRT2 independent (dual head mode) */ +#define VB_DISPMODE_DUAL DUALVIEW_MODE /* TW: alias */ +#define DISPLAY_MODE (SINGLE_MODE | MIRROR_MODE | DUALVIEW_MODE) /* TW */ + +/* SiS vga engine type */ +#define UNKNOWN_VGA 0 +#define SIS_300_VGA 1 +#define SIS_315_VGA 2 + +extern unsigned int sis_verbose; +extern unsigned short sis_iobase; +extern unsigned int sis_vga_engine; +extern unsigned int sis_vbflags; +extern unsigned int sis_overlay_on_crt1; +extern unsigned int sis_crt1_off; +extern unsigned int sis_detected_crt2_devices; +extern unsigned int sis_force_crt2_type; +extern unsigned int sis_device_id; + +#endif /* VIDIX_SIS_DEFS_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/vidix/sis_regs.h Sun Apr 01 00:02:43 2007 +0000 @@ -0,0 +1,412 @@ +/** + SiS register definitions and access macros. + From SiS X11 driver. + + Copyright 2001-2003 by Thomas Winischhofer, Vienna, Austria. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + +**/ + +#ifndef VIDIX_SIS_REGS_H +#define VIDIX_SIS_REGS_H + +#define inSISREG(base) INPORT8(base) +#define outSISREG(base,val) OUTPORT8(base, val) +#define orSISREG(base,val) do { \ + unsigned char __Temp = INPORT8(base); \ + outSISREG(base, __Temp | (val)); \ + } while (0) +#define andSISREG(base,val) do { \ + unsigned char __Temp = INPORT8(base); \ + outSISREG(base, __Temp & (val)); \ + } while (0) + +#define inSISIDXREG(base,idx,var) do { \ + OUTPORT8(base, idx); var=INPORT8((base)+1); \ + } while (0) +#define outSISIDXREG(base,idx,val) do { \ + OUTPORT8(base, idx); OUTPORT8((base)+1, val); \ + } while (0) +#define orSISIDXREG(base,idx,val) do { \ + unsigned char __Temp; \ + OUTPORT8(base, idx); \ + __Temp = INPORT8((base)+1)|(val); \ + outSISIDXREG(base,idx,__Temp); \ + } while (0) +#define andSISIDXREG(base,idx,and) do { \ + unsigned char __Temp; \ + OUTPORT8(base, idx); \ + __Temp = INPORT8((base)+1)&(and); \ + outSISIDXREG(base,idx,__Temp); \ + } while (0) +#define setSISIDXREG(base,idx,and,or) do { \ + unsigned char __Temp; \ + OUTPORT8(base, idx); \ + __Temp = (INPORT8((base)+1)&(and))|(or); \ + outSISIDXREG(base,idx,__Temp); \ + } while (0) + +#define BITMASK(h,l) (((unsigned)(1U << ((h)-(l)+1))-1)<<(l)) +#define GENMASK(mask) BITMASK(1?mask,0?mask) + +#define GETBITS(var,mask) (((var) & GENMASK(mask)) >> (0?mask)) +#define SETBITS(val,mask) ((val) << (0?mask)) +#define SETBIT(n) (1<<(n)) + +#define GETBITSTR(val,from,to) ((GETBITS(val,from)) << (0?to)) +#define SETVARBITS(var,val,from,to) (((var)&(~(GENMASK(to)))) | \ + GETBITSTR(val,from,to)) +#define GETVAR8(var) ((var)&0xFF) +#define SETVAR8(var,val) (var) = GETVAR8(val) + +/* #define VGA_RELIO_BASE 0x380 */ + +#define AROFFSET 0x40 /* VGA_ATTR_INDEX - VGA_RELIO_BASE */ +#define ARROFFSET 0x41 /* VGA_ATTR_DATA_R - VGA_RELIO_BASE */ +#define GROFFSET 0x4e /* VGA_GRAPH_INDEX - VGA_RELIO_BASE */ +#define SROFFSET 0x44 /* VGA_SEQ_INDEX - VGA_RELIO_BASE */ +#define CROFFSET 0x54 /* VGA_CRTC_INDEX_OFFSET + VGA_IOBASE_COLOR - VGA_RELIO_BASE */ +#define MISCROFFSET 0x4c /* VGA_MISC_OUT_R - VGA_RELIO_BASE */ +#define MISCWOFFSET 0x42 /* VGA_MISC_OUT_W - VGA_RELIO_BASE */ +#define INPUTSTATOFFSET 0x5A +#define PART1OFFSET 0x04 +#define PART2OFFSET 0x10 +#define PART3OFFSET 0x12 +#define PART4OFFSET 0x14 +#define PART5OFFSET 0x16 +#define VIDEOOFFSET 0x02 +#define COLREGOFFSET 0x48 + +#define SIS_IOBASE sis_iobase /* var defined in sis_vid.c */ +#define SISAR SIS_IOBASE + AROFFSET +#define SISARR SIS_IOBASE + ARROFFSET +#define SISGR SIS_IOBASE + GROFFSET +#define SISSR SIS_IOBASE + SROFFSET +#define SISCR SIS_IOBASE + CROFFSET +#define SISMISCR SIS_IOBASE + MISCROFFSET +#define SISMISCW SIS_IOBASE + MISCWOFFSET +#define SISINPSTAT SIS_IOBASE + INPUTSTATOFFSET +#define SISPART1 SIS_IOBASE + PART1OFFSET +#define SISPART2 SIS_IOBASE + PART2OFFSET +#define SISPART3 SIS_IOBASE + PART3OFFSET +#define SISPART4 SIS_IOBASE + PART4OFFSET +#define SISPART5 SIS_IOBASE + PART5OFFSET +#define SISVID SIS_IOBASE + VIDEOOFFSET +#define SISCOLIDX SIS_IOBASE + COLREGOFFSET +#define SISCOLDATA SIS_IOBASE + COLREGOFFSET + 1 +#define SISCOL2IDX SISPART5 +#define SISCOL2DATA SISPART5 + 1 + + +#define vc_index_offset 0x00 /* Video capture - unused */ +#define vc_data_offset 0x01 +#define vi_index_offset VIDEOOFFSET +#define vi_data_offset (VIDEOOFFSET + 1) +#define crt2_index_offset PART1OFFSET +#define crt2_port_offset (PART1OFFSET + 1) +#define sr_index_offset SROFFSET +#define sr_data_offset (SROFFSET + 1) +#define cr_index_offset CROFFSET +#define cr_data_offset (CROFFSET + 1) +#define input_stat INPUTSTATOFFSET + +/* For old chipsets (5597/5598, 6326, 530/620) ------------ */ +/* SR (3C4) */ +#define BankReg 0x06 +#define ClockReg 0x07 +#define CPUThreshold 0x08 +#define CRTThreshold 0x09 +#define CRTCOff 0x0A +#define DualBanks 0x0B +#define MMIOEnable 0x0B +#define RAMSize 0x0C +#define Mode64 0x0C +#define ExtConfStatus1 0x0E +#define ClockBase 0x13 +#define LinearAdd0 0x20 +#define LinearAdd1 0x21 +#define GraphEng 0x27 +#define MemClock0 0x28 +#define MemClock1 0x29 +#define XR2A 0x2A +#define XR2B 0x2B +#define TurboQueueBase 0x2C +#define FBSize 0x2F +#define ExtMiscCont5 0x34 +#define ExtMiscCont9 0x3C + +/* 3x4 */ +#define Offset 0x13 + +/* SiS Registers for 300, 540, 630, 730, 315, 550, 650, 740 */ + +/* VGA standard register */ +#define Index_SR_Graphic_Mode 0x06 +#define Index_SR_RAMDAC_Ctrl 0x07 +#define Index_SR_Threshold_Ctrl1 0x08 +#define Index_SR_Threshold_Ctrl2 0x09 +#define Index_SR_Misc_Ctrl 0x0F +#define Index_SR_DDC 0x11 +#define Index_SR_Feature_Connector_Ctrl 0x12 +#define Index_SR_DRAM_Sizing 0x14 +#define Index_SR_DRAM_State_Machine_Ctrl 0x15 +#define Index_SR_AGP_PCI_State_Machine 0x21 +#define Index_SR_Internal_MCLK0 0x28 +#define Index_SR_Internal_MCLK1 0x29 +#define Index_SR_Internal_DCLK1 0x2B +#define Index_SR_Internal_DCLK2 0x2C +#define Index_SR_Internal_DCLK3 0x2D +#define Index_SR_Ext_Clock_Sel 0x32 +#define Index_SR_Int_Status 0x34 +#define Index_SR_Int_Enable 0x35 +#define Index_SR_Int_Reset 0x36 +#define Index_SR_Power_On_Trap 0x38 +#define Index_SR_Power_On_Trap2 0x39 +#define Index_SR_Power_On_Trap3 0x3A + +/* video registers (300/630/730/315/550/650/740 only) */ +#define Index_VI_Passwd 0x00 + +/* Video overlay horizontal start/end, unit=screen pixels */ +#define Index_VI_Win_Hor_Disp_Start_Low 0x01 +#define Index_VI_Win_Hor_Disp_End_Low 0x02 +#define Index_VI_Win_Hor_Over 0x03 /* Overflow */ + +/* Video overlay vertical start/end, unit=screen pixels */ +#define Index_VI_Win_Ver_Disp_Start_Low 0x04 +#define Index_VI_Win_Ver_Disp_End_Low 0x05 +#define Index_VI_Win_Ver_Over 0x06 /* Overflow */ + +/* Y Plane (4:2:0) or YUV (4:2:2) buffer start address, unit=word */ +#define Index_VI_Disp_Y_Buf_Start_Low 0x07 +#define Index_VI_Disp_Y_Buf_Start_Middle 0x08 +#define Index_VI_Disp_Y_Buf_Start_High 0x09 + +/* U Plane (4:2:0) buffer start address, unit=word */ +#define Index_VI_U_Buf_Start_Low 0x0A +#define Index_VI_U_Buf_Start_Middle 0x0B +#define Index_VI_U_Buf_Start_High 0x0C + +/* V Plane (4:2:0) buffer start address, unit=word */ +#define Index_VI_V_Buf_Start_Low 0x0D +#define Index_VI_V_Buf_Start_Middle 0x0E +#define Index_VI_V_Buf_Start_High 0x0F + +/* Pitch for Y, UV Planes, unit=word */ +#define Index_VI_Disp_Y_Buf_Pitch_Low 0x10 +#define Index_VI_Disp_UV_Buf_Pitch_Low 0x11 +#define Index_VI_Disp_Y_UV_Buf_Pitch_Middle 0x12 + +/* What is this ? */ +#define Index_VI_Disp_Y_Buf_Preset_Low 0x13 +#define Index_VI_Disp_Y_Buf_Preset_Middle 0x14 + +#define Index_VI_UV_Buf_Preset_Low 0x15 +#define Index_VI_UV_Buf_Preset_Middle 0x16 +#define Index_VI_Disp_Y_UV_Buf_Preset_High 0x17 + +/* Scaling control registers */ +#define Index_VI_Hor_Post_Up_Scale_Low 0x18 +#define Index_VI_Hor_Post_Up_Scale_High 0x19 +#define Index_VI_Ver_Up_Scale_Low 0x1A +#define Index_VI_Ver_Up_Scale_High 0x1B +#define Index_VI_Scale_Control 0x1C + +/* Playback line buffer control */ +#define Index_VI_Play_Threshold_Low 0x1D +#define Index_VI_Play_Threshold_High 0x1E +#define Index_VI_Line_Buffer_Size 0x1F + +/* Destination color key */ +#define Index_VI_Overlay_ColorKey_Red_Min 0x20 +#define Index_VI_Overlay_ColorKey_Green_Min 0x21 +#define Index_VI_Overlay_ColorKey_Blue_Min 0x22 +#define Index_VI_Overlay_ColorKey_Red_Max 0x23 +#define Index_VI_Overlay_ColorKey_Green_Max 0x24 +#define Index_VI_Overlay_ColorKey_Blue_Max 0x25 + +/* Source color key, YUV color space */ +#define Index_VI_Overlay_ChromaKey_Red_Y_Min 0x26 +#define Index_VI_Overlay_ChromaKey_Green_U_Min 0x27 +#define Index_VI_Overlay_ChromaKey_Blue_V_Min 0x28 +#define Index_VI_Overlay_ChromaKey_Red_Y_Max 0x29 +#define Index_VI_Overlay_ChromaKey_Green_U_Max 0x2A +#define Index_VI_Overlay_ChromaKey_Blue_V_Max 0x2B + +/* Contrast enhancement and brightness control */ +#define Index_VI_Contrast_Factor 0x2C /* obviously unused/undefined */ +#define Index_VI_Brightness 0x2D +#define Index_VI_Contrast_Enh_Ctrl 0x2E + +#define Index_VI_Key_Overlay_OP 0x2F + +#define Index_VI_Control_Misc0 0x30 +#define Index_VI_Control_Misc1 0x31 +#define Index_VI_Control_Misc2 0x32 + +/* TW: Subpicture registers */ +#define Index_VI_SubPict_Buf_Start_Low 0x33 +#define Index_VI_SubPict_Buf_Start_Middle 0x34 +#define Index_VI_SubPict_Buf_Start_High 0x35 + +/* TW: What is this ? */ +#define Index_VI_SubPict_Buf_Preset_Low 0x36 +#define Index_VI_SubPict_Buf_Preset_Middle 0x37 + +/* TW: Subpicture pitch, unit=16 bytes */ +#define Index_VI_SubPict_Buf_Pitch 0x38 + +/* TW: Subpicture scaling control */ +#define Index_VI_SubPict_Hor_Scale_Low 0x39 +#define Index_VI_SubPict_Hor_Scale_High 0x3A +#define Index_VI_SubPict_Vert_Scale_Low 0x3B +#define Index_VI_SubPict_Vert_Scale_High 0x3C + +#define Index_VI_SubPict_Scale_Control 0x3D +/* (0x40 = enable/disable subpicture) */ + +/* TW: Subpicture line buffer control */ +#define Index_VI_SubPict_Threshold 0x3E + +/* TW: What is this? */ +#define Index_VI_FIFO_Max 0x3F + +/* TW: Subpicture palette; 16 colors, total 32 bytes address space */ +#define Index_VI_SubPict_Pal_Base_Low 0x40 +#define Index_VI_SubPict_Pal_Base_High 0x41 + +/* I wish I knew how to use these ... */ +#define Index_MPEG_Read_Ctrl0 0x60 /* MPEG auto flip */ +#define Index_MPEG_Read_Ctrl1 0x61 /* MPEG auto flip */ +#define Index_MPEG_Read_Ctrl2 0x62 /* MPEG auto flip */ +#define Index_MPEG_Read_Ctrl3 0x63 /* MPEG auto flip */ + +/* TW: MPEG AutoFlip scale */ +#define Index_MPEG_Ver_Up_Scale_Low 0x64 +#define Index_MPEG_Ver_Up_Scale_High 0x65 + +#define Index_MPEG_Y_Buf_Preset_Low 0x66 +#define Index_MPEG_Y_Buf_Preset_Middle 0x67 +#define Index_MPEG_UV_Buf_Preset_Low 0x68 +#define Index_MPEG_UV_Buf_Preset_Middle 0x69 +#define Index_MPEG_Y_UV_Buf_Preset_High 0x6A + +/* TW: The following registers only exist on the 310/325 series */ + +/* TW: Bit 16:24 of Y_U_V buf start address (?) */ +#define Index_VI_Y_Buf_Start_Over 0x6B +#define Index_VI_U_Buf_Start_Over 0x6C +#define Index_VI_V_Buf_Start_Over 0x6D + +#define Index_VI_Disp_Y_Buf_Pitch_High 0x6E +#define Index_VI_Disp_UV_Buf_Pitch_High 0x6F + +/* Hue and saturation */ +#define Index_VI_Hue 0x70 +#define Index_VI_Saturation 0x71 + +#define Index_VI_SubPict_Start_Over 0x72 +#define Index_VI_SubPict_Buf_Pitch_High 0x73 + +#define Index_VI_Control_Misc3 0x74 + + +/* TW: Bits (and helpers) for Index_VI_Control_Misc0 */ +#define VI_Misc0_Enable_Overlay 0x02 +#define VI_Misc0_420_Plane_Enable 0x04 /* Select Plane or Packed mode */ +#define VI_Misc0_422_Enable 0x20 /* Select 422 or 411 mode */ +#define VI_Misc0_Fmt_YVU420P 0x0C /* YUV420 Planar (I420, YV12) */ +#define VI_Misc0_Fmt_YUYV 0x28 /* YUYV Packed (YUY2) */ +#define VI_Misc0_Fmt_UYVY 0x08 /* (UYVY) */ + +/* TW: Bits for Index_VI_Control_Misc1 */ +/* #define VI_Misc1_? 0x01 */ +#define VI_Misc1_BOB_Enable 0x02 +#define VI_Misc1_Line_Merge 0x04 +#define VI_Misc1_Field_Mode 0x08 +/* #define VI_Misc1_? 0x10 */ +#define VI_Misc1_Non_Interleave 0x20 /* 300 series only? */ +#define VI_Misc1_Buf_Addr_Lock 0x20 /* 310 series only? */ +/* #define VI_Misc1_? 0x40 */ +/* #define VI_Misc1_? 0x80 */ + +/* TW: Bits for Index_VI_Control_Misc2 */ +#define VI_Misc2_Select_Video2 0x01 +#define VI_Misc2_Video2_On_Top 0x02 +/* #define VI_Misc2_? 0x04 */ +#define VI_Misc2_Vertical_Interpol 0x08 +#define VI_Misc2_Dual_Line_Merge 0x10 +#define VI_Misc2_All_Line_Merge 0x20 /* 310 series only? */ +#define VI_Misc2_Auto_Flip_Enable 0x40 /* 300 series only? */ +#define VI_Misc2_Video_Reg_Write_Enable 0x80 /* 310 series only? */ + +/* TW: Bits for Index_VI_Control_Misc3 */ +#define VI_Misc3_Submit_Video_1 0x01 /* AKA "address ready" */ +#define VI_Misc3_Submit_Video_2 0x02 /* AKA "address ready" */ +#define VI_Misc3_Submit_SubPict 0x04 /* AKA "address ready" */ + +/* TW: Values for Index_VI_Key_Overlay_OP (0x2F) */ +#define VI_ROP_Never 0x00 +#define VI_ROP_DestKey 0x03 +#define VI_ROP_Always 0x0F + +/* + * CRT_2 function control register --------------------------------- + */ +#define Index_CRT2_FC_CONTROL 0x00 +#define Index_CRT2_FC_SCREEN_HIGH 0x04 +#define Index_CRT2_FC_SCREEN_MID 0x05 +#define Index_CRT2_FC_SCREEN_LOW 0x06 +#define Index_CRT2_FC_ENABLE_WRITE 0x24 +#define Index_CRT2_FC_VR 0x25 +#define Index_CRT2_FC_VCount 0x27 +#define Index_CRT2_FC_VCount1 0x28 + +#define Index_310_CRT2_FC_VR 0x30 /* d[1] = vertical retrace */ +#define Index_310_CRT2_FC_RT 0x33 /* d[7] = retrace in progress */ + +/* video attributes - these should probably be configurable on the fly + * so users with different desktop sizes can keep + * captured data off the desktop + */ +#define _VINWID 704 +#define _VINHGT _VINHGT_NTSC +#define _VINHGT_NTSC 240 +#define _VINHGT_PAL 290 +#define _VIN_WINDOW (704 * 291 * 2) +#define _VBI_WINDOW (704 * 64 * 2) + +#define _VIN_FIELD_EVEN 1 +#define _VIN_FIELD_ODD 2 +#define _VIN_FIELD_BOTH 4 + + +/* i2c registers (TW; not on 300/310/325 series) */ +#define X_INDEXREG 0x14 +#define X_PORTREG 0x15 +#define X_DATA 0x0f +#define I2C_SCL 0x00 +#define I2C_SDA 0x01 +#define I2C_DELAY 10 + +/* mmio registers for video */ +#define REG_PRIM_CRT_COUNTER 0x8514 + +/* TW: MPEG MMIO registers (630 and later) ----------------------------*/ + +/* Not public (yet?) */ + +#endif /* VIDIX_SIS_REGS_H */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/vidix/sis_vid.c Sun Apr 01 00:02:43 2007 +0000 @@ -0,0 +1,1560 @@ +/** + VIDIX driver for SiS 300 and 310/325 series chips. + + Copyright 2003 Jake Page, Sugar Media. + + Based on SiS Xv driver: + Copyright 2002-2003 by Thomas Winischhofer, Vienna, Austria. + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + 2003/10/08 integrated into mplayer/vidix architecture -- Alex Beregszaszi +**/ + +#include <errno.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <inttypes.h> +#include <unistd.h> + +#include "vidix.h" +#include "fourcc.h" +#include "../libdha/libdha.h" +#include "../libdha/pci_ids.h" +#include "../libdha/pci_names.h" +#include "../config.h" + +#include "sis_regs.h" +#include "sis_defs.h" + + +/** Random defines **/ + +#define WATCHDOG_DELAY 500000 /* Watchdog counter for retrace waiting */ +#define IMAGE_MIN_WIDTH 32 /* Min and max source image sizes */ +#define IMAGE_MIN_HEIGHT 24 +#define IMAGE_MAX_WIDTH 720 +#define IMAGE_MAX_HEIGHT 576 +#define IMAGE_MAX_WIDTH_M650 1920 +#define IMAGE_MAX_HEIGHT_M650 1080 + +#define OVERLAY_MIN_WIDTH 32 /* Minimum overlay sizes */ +#define OVERLAY_MIN_HEIGHT 24 + +#define DISPMODE_SINGLE1 0x1 /* TW: CRT1 only */ +#define DISPMODE_SINGLE2 0x2 /* TW: CRT2 only */ +#define DISPMODE_MIRROR 0x4 /* TW: CRT1 + CRT2 MIRROR */ + +#define VMODE_INTERLACED 0x1 +#define VMODE_DOUBLESCAN 0x2 + +typedef struct { + short x1, y1, x2, y2; +} BoxRec; + +typedef struct { + int pixelFormat; + + uint16_t pitch; + uint16_t origPitch; + + uint8_t keyOP; + uint16_t HUSF; + uint16_t VUSF; + uint8_t IntBit; + uint8_t wHPre; + + uint16_t srcW; + uint16_t srcH; + + BoxRec dstBox; + + uint32_t PSY; + uint32_t PSV; + uint32_t PSU; + uint8_t bobEnable; + + uint8_t contrastCtrl; + uint8_t contrastFactor; + + uint8_t lineBufSize; + + uint8_t(*VBlankActiveFunc) (); + + uint16_t SCREENheight; + +} SISOverlayRec, *SISOverlayPtr; + + +/** static variable definitions **/ +static int sis_probed = 0; +static pciinfo_t pci_info; +unsigned int sis_verbose = 0; + +static void *sis_mem_base; +/* static void *sis_reg_base; */ +unsigned short sis_iobase; + +unsigned int sis_vga_engine = UNKNOWN_VGA; +static unsigned int sis_displaymode = DISPMODE_SINGLE1; +static unsigned int sis_has_two_overlays = 0; +static unsigned int sis_bridge_is_slave = 0; +static unsigned int sis_shift_value = 1; +static unsigned int sis_vmode = 0; +unsigned int sis_vbflags = DISPTYPE_DISP1; +unsigned int sis_overlay_on_crt1 = 1; +unsigned int sis_crt1_off = -1; +unsigned int sis_detected_crt2_devices; +unsigned int sis_force_crt2_type = CRT2_DEFAULT; +unsigned int sis_device_id = -1; + +static int sis_format; +static int sis_Yoff = 0; +static int sis_Voff = 0; +static int sis_Uoff = 0; +static int sis_screen_width = 640; +static int sis_screen_height = 480; + +static int sis_frames[VID_PLAY_MAXFRAMES]; + +static vidix_grkey_t sis_grkey; + +static vidix_capability_t sis_cap = { + "SiS 300/310/325 Video Driver", + "Jake Page", + TYPE_OUTPUT, + {0, 0, 0, 0}, + 2048, + 2048, + 4, + 4, + -1, + FLAG_UPSCALER | FLAG_DOWNSCALER | FLAG_EQUALIZER, + VENDOR_SIS, + -1, + {0, 0, 0, 0} +}; + +vidix_video_eq_t sis_equal = { + VEQ_CAP_BRIGHTNESS | VEQ_CAP_CONTRAST, + 200, 0, 0, 0, 0, 0, 0, 0 +}; + +static unsigned short sis_card_ids[] = { + DEVICE_SIS_300, + DEVICE_SIS_315H, + DEVICE_SIS_315, + DEVICE_SIS_315PRO, + DEVICE_SIS_330, + DEVICE_SIS_540_VGA, + DEVICE_SIS_550_VGA, + DEVICE_SIS_630_VGA, + DEVICE_SIS_650_VGA +}; + +/** function declarations **/ + +extern void sis_init_video_bridge(void); + + +static void set_overlay(SISOverlayPtr pOverlay, int index); +static void close_overlay(void); +static void calc_scale_factor(SISOverlayPtr pOverlay, + int index, int iscrt2); +static void set_line_buf_size(SISOverlayPtr pOverlay); +static void merge_line_buf(int enable); +static void set_format(SISOverlayPtr pOverlay); +static void set_colorkey(void); + +static void set_brightness(uint8_t brightness); +static void set_contrast(uint8_t contrast); +static void set_saturation(char saturation); +static void set_hue(uint8_t hue); +#if 0 +static void set_alpha(uint8_t alpha); +#endif + +/* IO Port access functions */ +static uint8_t getvideoreg(uint8_t reg) +{ + uint8_t ret; + inSISIDXREG(SISVID, reg, ret); + return (ret); +} + +static void setvideoreg(uint8_t reg, uint8_t data) +{ + outSISIDXREG(SISVID, reg, data); +} + +static void setvideoregmask(uint8_t reg, uint8_t data, uint8_t mask) +{ + uint8_t old; + + inSISIDXREG(SISVID, reg, old); + data = (data & mask) | (old & (~mask)); + outSISIDXREG(SISVID, reg, data); +} + +static void setsrregmask(uint8_t reg, uint8_t data, uint8_t mask) +{ + uint8_t old; + + inSISIDXREG(SISSR, reg, old); + data = (data & mask) | (old & (~mask)); + outSISIDXREG(SISSR, reg, data); +} + +/* vblank checking*/ +static uint8_t vblank_active_CRT1(void) +{ + /* this may be too simplistic? */ + return (inSISREG(SISINPSTAT) & 0x08); +} + +static uint8_t vblank_active_CRT2(void) +{ + uint8_t ret; + if (sis_vga_engine == SIS_315_VGA) { + inSISIDXREG(SISPART1, Index_310_CRT2_FC_VR, ret); + } else { + inSISIDXREG(SISPART1, Index_CRT2_FC_VR, ret); + } + return ((ret & 0x02) ^ 0x02); +} + + +unsigned int vixGetVersion(void) +{ + return (VIDIX_VERSION); +} + +static int find_chip(unsigned chip_id) +{ + unsigned i; + for (i = 0; i < sizeof(sis_card_ids) / sizeof(unsigned short); i++) { + if (chip_id == sis_card_ids[i]) + return i; + } + return -1; +} + +int vixProbe(int verbose, int force) +{ + pciinfo_t lst[MAX_PCI_DEVICES]; + unsigned i, num_pci; + int err; + + sis_verbose = verbose; + force = force; + err = pci_scan(lst, &num_pci); + if (err) { + printf("[SiS] Error occurred during pci scan: %s\n", strerror(err)); + return err; + } else { + err = ENXIO; + for (i = 0; i < num_pci; i++) { + if (lst[i].vendor == VENDOR_SIS) { + int idx; + const char *dname; + idx = find_chip(lst[i].device); + if (idx == -1) + continue; + dname = pci_device_name(VENDOR_SIS, lst[i].device); + dname = dname ? dname : "Unknown chip"; + if (sis_verbose > 0) + printf("[SiS] Found chip: %s (0x%X)\n", + dname, lst[i].device); + sis_device_id = sis_cap.device_id = lst[i].device; + err = 0; + memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); + + sis_has_two_overlays = 0; + switch (sis_cap.device_id) { + case DEVICE_SIS_300: + case DEVICE_SIS_630_VGA: + sis_has_two_overlays = 1; + case DEVICE_SIS_540_VGA: + sis_vga_engine = SIS_300_VGA; + break; + case DEVICE_SIS_330: + case DEVICE_SIS_550_VGA: + sis_has_two_overlays = 1; + case DEVICE_SIS_315H: + case DEVICE_SIS_315: + case DEVICE_SIS_315PRO: + case DEVICE_SIS_650_VGA: + /* M650 & 651 have 2 overlays */ + /* JCP: I think this works, but not really tested yet */ + { + unsigned char CR5F; + unsigned char tempreg1, tempreg2; + + inSISIDXREG(SISCR, 0x5F, CR5F); + CR5F &= 0xf0; + andSISIDXREG(SISCR, 0x5c, 0x07); + inSISIDXREG(SISCR, 0x5c, tempreg1); + tempreg1 &= 0xf8; + setSISIDXREG(SISCR, 0x5c, 0x07, 0xf8); + inSISIDXREG(SISCR, 0x5c, tempreg2); + tempreg2 &= 0xf8; + if ((!tempreg1) || (tempreg2)) { + if (CR5F & 0x80) { + sis_has_two_overlays = 1; + } + } else { + sis_has_two_overlays = 1; /* ? */ + } + if (sis_has_two_overlays) { + if (sis_verbose > 0) + printf + ("[SiS] detected M650/651 with 2 overlays\n"); + } + } + sis_vga_engine = SIS_315_VGA; + break; + default: + /* should never get here */ + sis_vga_engine = UNKNOWN_VGA; + break; + } + } + } + } + if (err && sis_verbose) { + printf("[SiS] Can't find chip\n"); + } else { + sis_probed = 1; + } + + return err; +} + +int vixInit(void) +{ + uint8_t sr_data, cr_data, cr_data2; + char *env_overlay_crt; + + if (!sis_probed) { + printf("[SiS] driver was not probed but is being initialized\n"); + return (EINTR); + } + + /* JCP: this is WRONG. Need to coordinate w/ sisfb to use correct mem */ + /* map 16MB scary hack for now. */ + sis_mem_base = map_phys_mem(pci_info.base0, 0x1000000); + /* sis_reg_base = map_phys_mem(pci_info.base1, 0x20000); */ + sis_iobase = pci_info.base2 & 0xFFFC; + + /* would like to use fb ioctl - or some other method - here to get + current resolution. */ + inSISIDXREG(SISCR, 0x12, cr_data); + inSISIDXREG(SISCR, 0x07, cr_data2); + sis_screen_height = + ((cr_data & 0xff) | ((uint16_t) (cr_data2 & 0x02) << 7) | + ((uint16_t) (cr_data2 & 0x40) << 3) | ((uint16_t) (cr_data & 0x02) + << 9)) + 1; + + inSISIDXREG(SISSR, 0x0b, sr_data); + inSISIDXREG(SISCR, 0x01, cr_data); + sis_screen_width = (((cr_data & 0xff) | + ((uint16_t) (sr_data & 0x0C) << 6)) + 1) * 8; + + inSISIDXREG(SISSR, Index_SR_Graphic_Mode, sr_data); + if (sr_data & 0x20) /* interlaced mode */ + sis_vmode |= VMODE_INTERLACED; + +#if 0 /* getting back false data here... */ + /* CR9 bit 7 set = double scan active */ + inSISIDXREG(SISCR, 0x09, cr_data); + if (cr_data & 0x40) { + sis_vmode |= VMODE_DOUBLESCAN; + } +#endif + + /* JCP: eventually I'd like to replace this with a call to sisfb + SISFB_GET_INFO ioctl to get video bridge info. Not for now, + since it requires a very new and not widely distributed version. */ + sis_init_video_bridge(); + + env_overlay_crt = getenv("VIDIX_CRT"); + if (env_overlay_crt) { + int crt = atoi(env_overlay_crt); + if (crt == 1 || crt == 2) { + sis_overlay_on_crt1 = (crt == 1); + if (sis_verbose > 0) { + printf + ("[SiS] override: using overlay on CRT%d from VIDIX_CRT\n", + crt); + } + } + } + + return 0; +} + +void vixDestroy(void) +{ + /* unmap_phys_mem(sis_reg_base, 0x20000); */ + /* JCP: see above, hence also a hack. */ + unmap_phys_mem(sis_mem_base, 0x1000000); +} + +int vixGetCapability(vidix_capability_t * to) +{ + memcpy(to, &sis_cap, sizeof(vidix_capability_t)); + return 0; +} + +static int is_supported_fourcc(uint32_t fourcc) +{ + switch (fourcc) { + case IMGFMT_YV12: + case IMGFMT_I420: + case IMGFMT_UYVY: + case IMGFMT_YUY2: + case IMGFMT_RGB15: + case IMGFMT_RGB16: + return 1; + default: + return 0; + } +} + +int vixQueryFourcc(vidix_fourcc_t * to) +{ + if (is_supported_fourcc(to->fourcc)) { + to->depth = VID_DEPTH_8BPP | VID_DEPTH_16BPP | VID_DEPTH_32BPP; + to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; + return 0; + } else + to->depth = to->flags = 0; + return ENOSYS; +} + +static int bridge_in_slave_mode(void) +{ + unsigned char usScratchP1_00; + + if (!(sis_vbflags & VB_VIDEOBRIDGE)) + return 0; + + inSISIDXREG(SISPART1, 0x00, usScratchP1_00); + if (((sis_vga_engine == SIS_300_VGA) + && (usScratchP1_00 & 0xa0) == 0x20) + || ((sis_vga_engine == SIS_315_VGA) + && (usScratchP1_00 & 0x50) == 0x10)) { + return 1; + } else { + return 0; + } +} + +/* This does not handle X dual head mode, since 1) vidix doesn't support it + and 2) it doesn't make sense for other gfx drivers */ +static void set_dispmode(void) +{ + sis_bridge_is_slave = 0; + + if (bridge_in_slave_mode()) + sis_bridge_is_slave = 1; + + if ((sis_vbflags & VB_DISPMODE_MIRROR) || + (sis_bridge_is_slave && (sis_vbflags & DISPTYPE_DISP2))) { + if (sis_has_two_overlays) + sis_displaymode = DISPMODE_MIRROR; /* TW: CRT1+CRT2 (2 overlays) */ + else if (!sis_overlay_on_crt1) + sis_displaymode = DISPMODE_SINGLE2; + else + sis_displaymode = DISPMODE_SINGLE1; + } else { + if (sis_vbflags & DISPTYPE_DISP1) { + sis_displaymode = DISPMODE_SINGLE1; /* TW: CRT1 only */ + } else { + sis_displaymode = DISPMODE_SINGLE2; /* TW: CRT2 only */ + } + } +} + +static void set_disptype_regs(void) +{ + switch (sis_displaymode) { + case DISPMODE_SINGLE1: /* TW: CRT1 only */ + if (sis_verbose > 2) { + printf("[SiS] Setting up overlay on CRT1\n"); + } + if (sis_has_two_overlays) { + setsrregmask(0x06, 0x00, 0xc0); + setsrregmask(0x32, 0x00, 0xc0); + } else { + setsrregmask(0x06, 0x00, 0xc0); + setsrregmask(0x32, 0x00, 0xc0); + } + break; + case DISPMODE_SINGLE2: /* TW: CRT2 only */ + if (sis_verbose > 2) { + printf("[SiS] Setting up overlay on CRT2\n"); + } + if (sis_has_two_overlays) { + setsrregmask(0x06, 0x80, 0xc0); + setsrregmask(0x32, 0x80, 0xc0); + } else { + setsrregmask(0x06, 0x40, 0xc0); + setsrregmask(0x32, 0x40, 0xc0); + } + break; + case DISPMODE_MIRROR: /* TW: CRT1 + CRT2 */ + default: + if (sis_verbose > 2) { + printf("[SiS] Setting up overlay on CRT1 AND CRT2!\n"); + } + setsrregmask(0x06, 0x80, 0xc0); + setsrregmask(0x32, 0x80, 0xc0); + break; + } +} + +static void init_overlay(void) +{ + /* Initialize first overlay (CRT1) */ + + /* Write-enable video registers */ + setvideoregmask(Index_VI_Control_Misc2, 0x80, 0x81); + + /* Disable overlay */ + setvideoregmask(Index_VI_Control_Misc0, 0x00, 0x02); + + /* Disable bobEnable */ + setvideoregmask(Index_VI_Control_Misc1, 0x02, 0x02); + + /* Reset scale control and contrast */ + setvideoregmask(Index_VI_Scale_Control, 0x60, 0x60); + setvideoregmask(Index_VI_Contrast_Enh_Ctrl, 0x04, 0x1F); + + setvideoreg(Index_VI_Disp_Y_Buf_Preset_Low, 0x00); + setvideoreg(Index_VI_Disp_Y_Buf_Preset_Middle, 0x00); + setvideoreg(Index_VI_UV_Buf_Preset_Low, 0x00); + setvideoreg(Index_VI_UV_Buf_Preset_Middle, 0x00); + setvideoreg(Index_VI_Disp_Y_UV_Buf_Preset_High, 0x00); + setvideoreg(Index_VI_Play_Threshold_Low, 0x00); + setvideoreg(Index_VI_Play_Threshold_High, 0x00); + + /* may not want to init these here, could already be set to other + values by app? */ + setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x01); + setvideoregmask(Index_VI_Contrast_Enh_Ctrl, 0x04, 0x07); + setvideoreg(Index_VI_Brightness, 0x20); + if (sis_vga_engine == SIS_315_VGA) { + setvideoreg(Index_VI_Hue, 0x00); + setvideoreg(Index_VI_Saturation, 0x00); + } + + /* Initialize second overlay (CRT2) */ + if (sis_has_two_overlays) { + /* Write-enable video registers */ + setvideoregmask(Index_VI_Control_Misc2, 0x81, 0x81); + + /* Disable overlay */ + setvideoregmask(Index_VI_Control_Misc0, 0x00, 0x02); + + /* Disable bobEnable */ + setvideoregmask(Index_VI_Control_Misc1, 0x02, 0x02); + + /* Reset scale control and contrast */ + setvideoregmask(Index_VI_Scale_Control, 0x60, 0x60); + setvideoregmask(Index_VI_Contrast_Enh_Ctrl, 0x04, 0x1F); + + setvideoreg(Index_VI_Disp_Y_Buf_Preset_Low, 0x00); + setvideoreg(Index_VI_Disp_Y_Buf_Preset_Middle, 0x00); + setvideoreg(Index_VI_UV_Buf_Preset_Low, 0x00); + setvideoreg(Index_VI_UV_Buf_Preset_Middle, 0x00); + setvideoreg(Index_VI_Disp_Y_UV_Buf_Preset_High, 0x00); + setvideoreg(Index_VI_Play_Threshold_Low, 0x00); + setvideoreg(Index_VI_Play_Threshold_High, 0x00); + + setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x01); + setvideoregmask(Index_VI_Contrast_Enh_Ctrl, 0x04, 0x07); + setvideoreg(Index_VI_Brightness, 0x20); + if (sis_vga_engine == SIS_315_VGA) { + setvideoreg(Index_VI_Hue, 0x00); + setvideoreg(Index_VI_Saturation, 0x00); + } + } +} + +int vixConfigPlayback(vidix_playback_t * info) +{ + SISOverlayRec overlay; + int srcOffsetX = 0, srcOffsetY = 0; + int sx, sy; + int index = 0, iscrt2 = 0; + int total_size; + + short src_w, drw_w; + short src_h, drw_h; + short src_x, drw_x; + short src_y, drw_y; + long dga_offset; + int pitch; + unsigned int i; + + if (!is_supported_fourcc(info->fourcc)) + return -1; + + /* set chipset/engine.dependent config info */ + /* which CRT to use, etc.? */ + switch (sis_vga_engine) { + case SIS_315_VGA: + sis_shift_value = 1; + sis_equal.cap |= VEQ_CAP_SATURATION | VEQ_CAP_HUE; + break; + case SIS_300_VGA: + default: + sis_shift_value = 2; + break; + } + + sis_displaymode = DISPMODE_SINGLE1; /* xV driver code in set_dispmode() */ + set_dispmode(); + + set_disptype_regs(); + + init_overlay(); + + /* get basic dimension info */ + src_x = info->src.x; + src_y = info->src.y; + src_w = info->src.w; + src_h = info->src.h; + + drw_x = info->dest.x; + drw_y = info->dest.y; + drw_w = info->dest.w; + drw_h = info->dest.h; + + switch (info->fourcc) { + case IMGFMT_YV12: + case IMGFMT_I420: + pitch = (src_w + 7) & ~7; + total_size = (pitch * src_h * 3) >> 1; + break; + case IMGFMT_YUY2: + case IMGFMT_UYVY: + case IMGFMT_RGB15: + case IMGFMT_RGB16: + pitch = ((src_w << 1) + 3) & ~3; + total_size = pitch * src_h; + break; + default: + return -1; + } + + /* "allocate" memory for overlay! */ + /* start at 8MB = sisfb's "dri reserved space" - + really shouldn't hardcode though */ + /* XXX: JCP - this can use the sisfb FBIO_ALLOC ioctl to safely + allocate "video heap" memory... */ + dga_offset = 0x800000; + + /* use 7MB for now. need to calc/get real info from sisfb? */ + /* this can result in a LOT of frames - probably not necessary */ + info->num_frames = 0x700000 / (total_size * 2); + if (info->num_frames > VID_PLAY_MAXFRAMES) + info->num_frames = VID_PLAY_MAXFRAMES; + + info->dga_addr = sis_mem_base + dga_offset; + info->dest.pitch.y = 16; + info->dest.pitch.u = 16; + info->dest.pitch.v = 16; + info->offset.y = 0; + info->offset.u = 0; + info->offset.v = 0; + info->frame_size = (total_size * 2); /* why times 2 ? */ + for (i = 0; i < info->num_frames; i++) { + info->offsets[i] = info->frame_size * i; + /* save ptrs to mem buffers */ + sis_frames[i] = (dga_offset + info->offsets[i]); + } + + memset(&overlay, 0, sizeof(overlay)); + overlay.pixelFormat = sis_format = info->fourcc; + overlay.pitch = overlay.origPitch = pitch; + + + overlay.keyOP = (sis_grkey.ckey.op == CKEY_TRUE ? + VI_ROP_DestKey : VI_ROP_Always); + + overlay.bobEnable = 0x00; + + overlay.SCREENheight = sis_screen_height; + + /* probably will not support X virtual screen > phys very well? */ + overlay.dstBox.x1 = drw_x; /* - pScrn->frameX0; */ + overlay.dstBox.x2 = drw_x + drw_w; /* - pScrn->frameX0; ??? */ + overlay.dstBox.y1 = drw_y; /* - pScrn->frameY0; */ + overlay.dstBox.y2 = drw_y + drw_h; /* - pScrn->frameY0; ??? */ + + if ((overlay.dstBox.x1 > overlay.dstBox.x2) || + (overlay.dstBox.y1 > overlay.dstBox.y2)) + return -1; + + if ((overlay.dstBox.x2 < 0) || (overlay.dstBox.y2 < 0)) + return -1; + + if (overlay.dstBox.x1 < 0) { + srcOffsetX = src_w * (-overlay.dstBox.x1) / drw_w; + overlay.dstBox.x1 = 0; + } + if (overlay.dstBox.y1 < 0) { + srcOffsetY = src_h * (-overlay.dstBox.y1) / drw_h; + overlay.dstBox.y1 = 0; + } + + switch (info->fourcc) { + case IMGFMT_YV12: + info->dest.pitch.y = 16; + sx = (src_x + srcOffsetX) & ~7; + sy = (src_y + srcOffsetY) & ~1; + info->offset.y = sis_Yoff = sx + sy * pitch; + /* JCP: NOTE reversed u & v here! Not sure why this is needed. + maybe mplayer & sis define U & V differently?? */ + info->offset.u = sis_Voff = + src_h * pitch + ((sx + sy * pitch / 2) >> 1); + info->offset.v = sis_Uoff = + src_h * pitch * 5 / 4 + ((sx + sy * pitch / 2) >> 1); + + overlay.PSY = (sis_frames[0] + sis_Yoff) >> sis_shift_value; + overlay.PSV = (sis_frames[0] + sis_Voff) >> sis_shift_value; + overlay.PSU = (sis_frames[0] + sis_Uoff) >> sis_shift_value; + break; + case IMGFMT_I420: + sx = (src_x + srcOffsetX) & ~7; + sy = (src_y + srcOffsetY) & ~1; + info->offset.y = sis_Yoff = sx + sy * pitch; + /* JCP: see above... */ + info->offset.u = sis_Voff = + src_h * pitch * 5 / 4 + ((sx + sy * pitch / 2) >> 1); + info->offset.v = sis_Uoff = + src_h * pitch + ((sx + sy * pitch / 2) >> 1); + + overlay.PSY = (sis_frames[0] + sis_Yoff) >> sis_shift_value; + overlay.PSV = (sis_frames[0] + sis_Voff) >> sis_shift_value; + overlay.PSU = (sis_frames[0] + sis_Uoff) >> sis_shift_value; + break; + case IMGFMT_YUY2: + case IMGFMT_UYVY: + case IMGFMT_RGB16: + case IMGFMT_RGB15: + default: + sx = (src_x + srcOffsetX) & ~1; + sy = (src_y + srcOffsetY); + info->offset.y = sis_Yoff = sx * 2 + sy * pitch; + + overlay.PSY = (sis_frames[0] + sis_Yoff) >> sis_shift_value; + break; + } + + /* FIXME: is it possible that srcW < 0? */ + overlay.srcW = src_w - (sx - src_x); + overlay.srcH = src_h - (sy - src_y); + + /* JCP: what to do about this? */ +#if 0 + if ((pPriv->oldx1 != overlay.dstBox.x1) || + (pPriv->oldx2 != overlay.dstBox.x2) || + (pPriv->oldy1 != overlay.dstBox.y1) || + (pPriv->oldy2 != overlay.dstBox.y2)) { + pPriv->mustwait = 1; + pPriv->oldx1 = overlay.dstBox.x1; + pPriv->oldx2 = overlay.dstBox.x2; + pPriv->oldy1 = overlay.dstBox.y1; + pPriv->oldy2 = overlay.dstBox.y2; + } +#endif + + /* set merge line buffer */ + merge_line_buf(overlay.srcW > 384); + + /* calculate line buffer length */ + set_line_buf_size(&overlay); + + if (sis_displaymode == DISPMODE_SINGLE2) { + if (sis_has_two_overlays) { + /* TW: On chips with two overlays we use + * overlay 2 for CRT2 */ + index = 1; + iscrt2 = 1; + } else { + /* TW: On chips with only one overlay we + * use that only overlay for CRT2 */ + index = 0; + iscrt2 = 1; + } + overlay.VBlankActiveFunc = vblank_active_CRT2; + /* overlay.GetScanLineFunc = get_scanline_CRT2; */ + } else { + index = 0; + iscrt2 = 0; + overlay.VBlankActiveFunc = vblank_active_CRT1; + /* overlay.GetScanLineFunc = get_scanline_CRT1; */ + } + + /* calc scale factor (to use below) */ + calc_scale_factor(&overlay, index, iscrt2); + + /* Select video1 (used for CRT1) or video2 (used for CRT2) */ + setvideoregmask(Index_VI_Control_Misc2, index, 0x01); + + set_format(&overlay); + + set_colorkey(); + + vixPlaybackSetEq(&sis_equal); + + /* set up video overlay registers */ + set_overlay(&overlay, index); + + /* prevent badness if bits are not at default setting */ + setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x01); + setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x04); + + /* JCP: Xv driver implementation loops back over above code to + setup mirror CRT2 */ + + return 0; +} + +int vixPlaybackOn(void) +{ + setvideoregmask(Index_VI_Control_Misc0, 0x02, 0x02); + return 0; +} + +int vixPlaybackOff(void) +{ + unsigned char sridx, cridx; + sridx = inSISREG(SISSR); + cridx = inSISREG(SISCR); + close_overlay(); + outSISREG(SISSR, sridx); + outSISREG(SISCR, cridx); + + return 0; +} + +int vixPlaybackFrameSelect(unsigned int frame) +{ + uint8_t data; + int index = 0; + uint32_t PSY; + + if (sis_displaymode == DISPMODE_SINGLE2 && sis_has_two_overlays) { + index = 1; + } + + PSY = (sis_frames[frame] + sis_Yoff) >> sis_shift_value; + + /* Unlock address registers */ + data = getvideoreg(Index_VI_Control_Misc1); + setvideoreg(Index_VI_Control_Misc1, data | 0x20); + /* TEST: Is this required? */ + setvideoreg(Index_VI_Control_Misc1, data | 0x20); + /* TEST end */ + /* TEST: Is this required? */ + if (sis_vga_engine == SIS_315_VGA) + setvideoreg(Index_VI_Control_Misc3, 0x00); + /* TEST end */ + + /* set Y start address */ + setvideoreg(Index_VI_Disp_Y_Buf_Start_Low, (uint8_t) (PSY)); + setvideoreg(Index_VI_Disp_Y_Buf_Start_Middle, (uint8_t) ((PSY) >> 8)); + setvideoreg(Index_VI_Disp_Y_Buf_Start_High, (uint8_t) ((PSY) >> 16)); + /* set 310/325 series overflow bits for Y plane */ + if (sis_vga_engine == SIS_315_VGA) { + setvideoreg(Index_VI_Y_Buf_Start_Over, + ((uint8_t) ((PSY) >> 24) & 0x01)); + } + + /* Set U/V data if using plane formats */ + if ((sis_format == IMGFMT_YV12) || (sis_format == IMGFMT_I420)) { + + uint32_t PSU, PSV; + + PSU = (sis_frames[frame] + sis_Uoff) >> sis_shift_value; + PSV = (sis_frames[frame] + sis_Voff) >> sis_shift_value; + + /* set U/V start address */ + setvideoreg(Index_VI_U_Buf_Start_Low, (uint8_t) PSU); + setvideoreg(Index_VI_U_Buf_Start_Middle, (uint8_t) (PSU >> 8)); + setvideoreg(Index_VI_U_Buf_Start_High, (uint8_t) (PSU >> 16)); + + setvideoreg(Index_VI_V_Buf_Start_Low, (uint8_t) PSV); + setvideoreg(Index_VI_V_Buf_Start_Middle, (uint8_t) (PSV >> 8)); + setvideoreg(Index_VI_V_Buf_Start_High, (uint8_t) (PSV >> 16)); + + /* 310/325 series overflow bits */ + if (sis_vga_engine == SIS_315_VGA) { + setvideoreg(Index_VI_U_Buf_Start_Over, + ((uint8_t) (PSU >> 24) & 0x01)); + setvideoreg(Index_VI_V_Buf_Start_Over, + ((uint8_t) (PSV >> 24) & 0x01)); + } + } + + if (sis_vga_engine == SIS_315_VGA) { + /* Trigger register copy for 310 series */ + setvideoreg(Index_VI_Control_Misc3, 1 << index); + } + + /* Lock the address registers */ + setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x20); + + return 0; +} + +int vixGetGrKeys(vidix_grkey_t * grkey) +{ + memcpy(grkey, &sis_grkey, sizeof(vidix_grkey_t)); + return 0; +} + +int vixSetGrKeys(const vidix_grkey_t * grkey) +{ + memcpy(&sis_grkey, grkey, sizeof(vidix_grkey_t)); + set_colorkey(); + return 0; +} + +int vixPlaybackGetEq(vidix_video_eq_t * eq) +{ + memcpy(eq, &sis_equal, sizeof(vidix_video_eq_t)); + return 0; +} + +int vixPlaybackSetEq(const vidix_video_eq_t * eq) +{ + int br, sat, cr, hue; + if (eq->cap & VEQ_CAP_BRIGHTNESS) + sis_equal.brightness = eq->brightness; + if (eq->cap & VEQ_CAP_CONTRAST) + sis_equal.contrast = eq->contrast; + if (eq->cap & VEQ_CAP_SATURATION) + sis_equal.saturation = eq->saturation; + if (eq->cap & VEQ_CAP_HUE) + sis_equal.hue = eq->hue; + if (eq->cap & VEQ_CAP_RGB_INTENSITY) { + sis_equal.red_intensity = eq->red_intensity; + sis_equal.green_intensity = eq->green_intensity; + sis_equal.blue_intensity = eq->blue_intensity; + } + sis_equal.flags = eq->flags; + + cr = (sis_equal.contrast + 1000) * 7 / 2000; + if (cr < 0) + cr = 0; + if (cr > 7) + cr = 7; + + br = sis_equal.brightness * 127 / 1000; + if (br < -128) + br = -128; + if (br > 127) + br = 127; + + sat = (sis_equal.saturation * 7) / 1000; + if (sat < -7) + sat = -7; + if (sat > 7) + sat = 7; + + hue = sis_equal.hue * 7 / 1000; + if (hue < -8) + hue = -8; + if (hue > 7) + hue = 7; + + set_brightness(br); + set_contrast(cr); + if (sis_vga_engine == SIS_315_VGA) { + set_saturation(sat); + set_hue(hue); + } + + return 0; +} + +static void set_overlay(SISOverlayPtr pOverlay, int index) +{ + uint16_t pitch = 0; + uint8_t h_over = 0, v_over = 0; + uint16_t top, bottom, left, right; + uint16_t screenX = sis_screen_width; + uint16_t screenY = sis_screen_height; + uint8_t data; + uint32_t watchdog; + + top = pOverlay->dstBox.y1; + bottom = pOverlay->dstBox.y2; + if (bottom > screenY) { + bottom = screenY; + } + + left = pOverlay->dstBox.x1; + right = pOverlay->dstBox.x2; + if (right > screenX) { + right = screenX; + } + + /* JCP: these aren't really tested... */ + /* TW: DoubleScan modes require Y coordinates * 2 */ + if (sis_vmode & VMODE_DOUBLESCAN) { + top <<= 1; + bottom <<= 1; + } + /* TW: Interlace modes require Y coordinates / 2 */ + if (sis_vmode & VMODE_INTERLACED) { + top >>= 1; + bottom >>= 1; + } + + h_over = (((left >> 8) & 0x0f) | ((right >> 4) & 0xf0)); + v_over = (((top >> 8) & 0x0f) | ((bottom >> 4) & 0xf0)); + + pitch = pOverlay->pitch >> sis_shift_value; + + /* set line buffer size */ + setvideoreg(Index_VI_Line_Buffer_Size, pOverlay->lineBufSize); + + /* set color key mode */ + setvideoregmask(Index_VI_Key_Overlay_OP, pOverlay->keyOP, 0x0F); + + /* TW: We don't have to wait for vertical retrace in all cases */ + /* JCP: be safe for now. */ + if (1 /*pPriv->mustwait */ ) { + watchdog = WATCHDOG_DELAY; + while (pOverlay->VBlankActiveFunc() && --watchdog); + watchdog = WATCHDOG_DELAY; + while ((!pOverlay->VBlankActiveFunc()) && --watchdog); + if (!watchdog && sis_verbose > 0) { + printf("[SiS]: timed out waiting for vertical retrace\n"); + } + } + + /* Unlock address registers */ + data = getvideoreg(Index_VI_Control_Misc1); + setvideoreg(Index_VI_Control_Misc1, data | 0x20); + /* TEST: Is this required? */ + setvideoreg(Index_VI_Control_Misc1, data | 0x20); + /* TEST end */ + + /* TEST: Is this required? */ + if (sis_vga_engine == SIS_315_VGA) + setvideoreg(Index_VI_Control_Misc3, 0x00); + /* TEST end */ + + /* Set Y buf pitch */ + setvideoreg(Index_VI_Disp_Y_Buf_Pitch_Low, (uint8_t) (pitch)); + setvideoregmask(Index_VI_Disp_Y_UV_Buf_Pitch_Middle, + (uint8_t) (pitch >> 8), 0x0f); + + /* Set Y start address */ + setvideoreg(Index_VI_Disp_Y_Buf_Start_Low, (uint8_t) (pOverlay->PSY)); + setvideoreg(Index_VI_Disp_Y_Buf_Start_Middle, + (uint8_t) ((pOverlay->PSY) >> 8)); + setvideoreg(Index_VI_Disp_Y_Buf_Start_High, + (uint8_t) ((pOverlay->PSY) >> 16)); + + /* set 310/325 series overflow bits for Y plane */ + if (sis_vga_engine == SIS_315_VGA) { + setvideoreg(Index_VI_Disp_Y_Buf_Pitch_High, + (uint8_t) (pitch >> 12)); + setvideoreg(Index_VI_Y_Buf_Start_Over, + ((uint8_t) ((pOverlay->PSY) >> 24) & 0x01)); + } + + /* Set U/V data if using plane formats */ + if ((pOverlay->pixelFormat == IMGFMT_YV12) || + (pOverlay->pixelFormat == IMGFMT_I420)) { + + uint32_t PSU, PSV; + + PSU = pOverlay->PSU; + PSV = pOverlay->PSV; + + /* Set U/V pitch */ + setvideoreg(Index_VI_Disp_UV_Buf_Pitch_Low, + (uint8_t) (pitch >> 1)); + setvideoregmask(Index_VI_Disp_Y_UV_Buf_Pitch_Middle, + (uint8_t) (pitch >> 5), 0xf0); + + /* set U/V start address */ + setvideoreg(Index_VI_U_Buf_Start_Low, (uint8_t) PSU); + setvideoreg(Index_VI_U_Buf_Start_Middle, (uint8_t) (PSU >> 8)); + setvideoreg(Index_VI_U_Buf_Start_High, (uint8_t) (PSU >> 16)); + + setvideoreg(Index_VI_V_Buf_Start_Low, (uint8_t) PSV); + setvideoreg(Index_VI_V_Buf_Start_Middle, (uint8_t) (PSV >> 8)); + setvideoreg(Index_VI_V_Buf_Start_High, (uint8_t) (PSV >> 16)); + + /* 310/325 series overflow bits */ + if (sis_vga_engine == SIS_315_VGA) { + setvideoreg(Index_VI_Disp_UV_Buf_Pitch_High, + (uint8_t) (pitch >> 13)); + setvideoreg(Index_VI_U_Buf_Start_Over, + ((uint8_t) (PSU >> 24) & 0x01)); + setvideoreg(Index_VI_V_Buf_Start_Over, + ((uint8_t) (PSV >> 24) & 0x01)); + } + } + + if (sis_vga_engine == SIS_315_VGA) { + /* Trigger register copy for 310 series */ + setvideoreg(Index_VI_Control_Misc3, 1 << index); + } + + /* set scale factor */ + setvideoreg(Index_VI_Hor_Post_Up_Scale_Low, + (uint8_t) (pOverlay->HUSF)); + setvideoreg(Index_VI_Hor_Post_Up_Scale_High, + (uint8_t) ((pOverlay->HUSF) >> 8)); + setvideoreg(Index_VI_Ver_Up_Scale_Low, (uint8_t) (pOverlay->VUSF)); + setvideoreg(Index_VI_Ver_Up_Scale_High, + (uint8_t) ((pOverlay->VUSF) >> 8)); + + setvideoregmask(Index_VI_Scale_Control, (pOverlay->IntBit << 3) + | (pOverlay->wHPre), 0x7f); + + /* set destination window position */ + setvideoreg(Index_VI_Win_Hor_Disp_Start_Low, (uint8_t) left); + setvideoreg(Index_VI_Win_Hor_Disp_End_Low, (uint8_t) right); + setvideoreg(Index_VI_Win_Hor_Over, (uint8_t) h_over); + + setvideoreg(Index_VI_Win_Ver_Disp_Start_Low, (uint8_t) top); + setvideoreg(Index_VI_Win_Ver_Disp_End_Low, (uint8_t) bottom); + setvideoreg(Index_VI_Win_Ver_Over, (uint8_t) v_over); + + setvideoregmask(Index_VI_Control_Misc1, pOverlay->bobEnable, 0x1a); + + /* Lock the address registers */ + setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x20); +} + + +/* TW: Overlay MUST NOT be switched off while beam is over it */ +static void close_overlay(void) +{ + uint32_t watchdog; + + if ((sis_displaymode == DISPMODE_SINGLE2) || + (sis_displaymode == DISPMODE_MIRROR)) { + if (sis_has_two_overlays) { + setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x01); + watchdog = WATCHDOG_DELAY; + while (vblank_active_CRT2() && --watchdog); + watchdog = WATCHDOG_DELAY; + while ((!vblank_active_CRT2()) && --watchdog); + setvideoregmask(Index_VI_Control_Misc0, 0x00, 0x02); + watchdog = WATCHDOG_DELAY; + while (vblank_active_CRT2() && --watchdog); + watchdog = WATCHDOG_DELAY; + while ((!vblank_active_CRT2()) && --watchdog); + } else if (sis_displaymode == DISPMODE_SINGLE2) { + setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x01); + watchdog = WATCHDOG_DELAY; + while (vblank_active_CRT1() && --watchdog); + watchdog = WATCHDOG_DELAY; + while ((!vblank_active_CRT1()) && --watchdog); + setvideoregmask(Index_VI_Control_Misc0, 0x00, 0x02); + watchdog = WATCHDOG_DELAY; + while (vblank_active_CRT1() && --watchdog); + watchdog = WATCHDOG_DELAY; + while ((!vblank_active_CRT1()) && --watchdog); + } + } + if ((sis_displaymode == DISPMODE_SINGLE1) || + (sis_displaymode == DISPMODE_MIRROR)) { + setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x01); + watchdog = WATCHDOG_DELAY; + while (vblank_active_CRT1() && --watchdog); + watchdog = WATCHDOG_DELAY; + while ((!vblank_active_CRT1()) && --watchdog); + setvideoregmask(Index_VI_Control_Misc0, 0x00, 0x02); + watchdog = WATCHDOG_DELAY; + while (vblank_active_CRT1() && --watchdog); + watchdog = WATCHDOG_DELAY; + while ((!vblank_active_CRT1()) && --watchdog); + } +} + + +static void +calc_scale_factor(SISOverlayPtr pOverlay, int index, int iscrt2) +{ + uint32_t i = 0, mult = 0; + int flag = 0; + + int dstW = pOverlay->dstBox.x2 - pOverlay->dstBox.x1; + int dstH = pOverlay->dstBox.y2 - pOverlay->dstBox.y1; + int srcW = pOverlay->srcW; + int srcH = pOverlay->srcH; + /* uint16_t LCDheight = pSiS->LCDheight; */ + int srcPitch = pOverlay->origPitch; + int origdstH = dstH; + + /* get rid of warnings for now */ + index = index; + iscrt2 = iscrt2; + +#if 0 /* JCP: don't bother with this for now. */ + /* TW: Stretch image due to idiotic LCD "auto"-scaling on LVDS (and 630+301B) */ + if (pSiS->VBFlags & CRT2_LCD) { + if (sis_bridge_is_slave) { + if (pSiS->VBFlags & VB_LVDS) { + dstH = (dstH * LCDheight) / pOverlay->SCREENheight; + } else if ((sis_vga_engine == SIS_300_VGA) && + (pSiS-> + VBFlags & (VB_301B | VB_302B | VB_301LV | + VB_302LV))) { + dstH = (dstH * LCDheight) / pOverlay->SCREENheight; + } + } else if (iscrt2) { + if (pSiS->VBFlags & VB_LVDS) { + dstH = (dstH * LCDheight) / pOverlay->SCREENheight; + if (sis_displaymode == DISPMODE_MIRROR) + flag = 1; + } else if ((sis_vga_engine == SIS_300_VGA) && + (pSiS-> + VBFlags & (VB_301B | VB_302B | VB_301LV | + VB_302LV))) { + dstH = (dstH * LCDheight) / pOverlay->SCREENheight; + if (sis_displaymode == DISPMODE_MIRROR) + flag = 1; + } + } + } +#endif + + /* TW: For double scan modes, we need to double the height + * (Perhaps we also need to scale LVDS, but I'm not sure.) + * On 310/325 series, we need to double the width as well. + * Interlace mode vice versa. + */ + if (sis_vmode & VMODE_DOUBLESCAN) { + dstH = origdstH << 1; + flag = 0; + if (sis_vga_engine == SIS_315_VGA) { + dstW <<= 1; + } + } + if (sis_vmode & VMODE_INTERLACED) { + dstH = origdstH >> 1; + flag = 0; + } + + if (dstW < OVERLAY_MIN_WIDTH) + dstW = OVERLAY_MIN_WIDTH; + if (dstW == srcW) { + pOverlay->HUSF = 0x00; + pOverlay->IntBit = 0x05; + pOverlay->wHPre = 0; + } else if (dstW > srcW) { + dstW += 2; + pOverlay->HUSF = (srcW << 16) / dstW; + pOverlay->IntBit = 0x04; + pOverlay->wHPre = 0; + } else { + int tmpW = dstW; + + /* TW: It seems, the hardware can't scale below factor .125 (=1/8) if the + pitch isn't a multiple of 256. + TODO: Test this on the 310/325 series! + */ + if ((srcPitch % 256) || (srcPitch < 256)) { + if (((dstW * 1000) / srcW) < 125) + dstW = tmpW = ((srcW * 125) / 1000) + 1; + } + + i = 0; + pOverlay->IntBit = 0x01; + while (srcW >= tmpW) { + tmpW <<= 1; + i++; + } + pOverlay->wHPre = (uint8_t) (i - 1); + dstW <<= (i - 1); + if ((srcW % dstW)) + pOverlay->HUSF = ((srcW - dstW) << 16) / dstW; + else + pOverlay->HUSF = 0x00; + } + + if (dstH < OVERLAY_MIN_HEIGHT) + dstH = OVERLAY_MIN_HEIGHT; + if (dstH == srcH) { + pOverlay->VUSF = 0x00; + pOverlay->IntBit |= 0x0A; + } else if (dstH > srcH) { + dstH += 0x02; + pOverlay->VUSF = (srcH << 16) / dstH; + pOverlay->IntBit |= 0x08; + } else { + uint32_t realI; + + i = realI = srcH / dstH; + pOverlay->IntBit |= 0x02; + + if (i < 2) { + pOverlay->VUSF = ((srcH - dstH) << 16) / dstH; + /* TW: Needed for LCD-scaling modes */ + if ((flag) && (mult = (srcH / origdstH)) >= 2) + pOverlay->pitch /= mult; + } else { +#if 0 + if (((pOverlay->bobEnable & 0x08) == 0x00) && + (((srcPitch * i) >> 2) > 0xFFF)) { + pOverlay->bobEnable |= 0x08; + srcPitch >>= 1; + } +#endif + if (((srcPitch * i) >> 2) > 0xFFF) { + i = (0xFFF * 2 / srcPitch); + pOverlay->VUSF = 0xFFFF; + } else { + dstH = i * dstH; + if (srcH % dstH) + pOverlay->VUSF = ((srcH - dstH) << 16) / dstH; + else + pOverlay->VUSF = 0x00; + } + /* set video frame buffer offset */ + pOverlay->pitch = (uint16_t) (srcPitch * i); + } + } +} + +static void set_line_buf_size(SISOverlayPtr pOverlay) +{ + uint8_t preHIDF; + uint32_t i; + uint32_t line = pOverlay->srcW; + + if ((pOverlay->pixelFormat == IMGFMT_YV12) || + (pOverlay->pixelFormat == IMGFMT_I420)) { + preHIDF = pOverlay->wHPre & 0x07; + switch (preHIDF) { + case 3: + if ((line & 0xffffff00) == line) + i = (line >> 8); + else + i = (line >> 8) + 1; + pOverlay->lineBufSize = (uint8_t) (i * 32 - 1); + break; + case 4: + if ((line & 0xfffffe00) == line) + i = (line >> 9); + else + i = (line >> 9) + 1; + pOverlay->lineBufSize = (uint8_t) (i * 64 - 1); + break; + case 5: + if ((line & 0xfffffc00) == line) + i = (line >> 10); + else + i = (line >> 10) + 1; + pOverlay->lineBufSize = (uint8_t) (i * 128 - 1); + break; + case 6: + if ((line & 0xfffff800) == line) + i = (line >> 11); + else + i = (line >> 11) + 1; + pOverlay->lineBufSize = (uint8_t) (i * 256 - 1); + break; + default: + if ((line & 0xffffff80) == line) + i = (line >> 7); + else + i = (line >> 7) + 1; + pOverlay->lineBufSize = (uint8_t) (i * 16 - 1); + break; + } + } else { /* YUV2, UYVY */ + if ((line & 0xffffff8) == line) + i = (line >> 3); + else + i = (line >> 3) + 1; + pOverlay->lineBufSize = (uint8_t) (i - 1); + } +} + +static void merge_line_buf(int enable) +{ + if (enable) { + switch (sis_displaymode) { + case DISPMODE_SINGLE1: + if (sis_has_two_overlays) { + /* dual line merge */ + setvideoregmask(Index_VI_Control_Misc2, 0x10, 0x11); + setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04); + } else { + setvideoregmask(Index_VI_Control_Misc2, 0x10, 0x11); + setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04); + } + break; + case DISPMODE_SINGLE2: + if (sis_has_two_overlays) { + /* line merge */ + setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x11); + setvideoregmask(Index_VI_Control_Misc1, 0x04, 0x04); + } else { + setvideoregmask(Index_VI_Control_Misc2, 0x10, 0x11); + setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04); + } + break; + case DISPMODE_MIRROR: + default: + /* line merge */ + setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x11); + setvideoregmask(Index_VI_Control_Misc1, 0x04, 0x04); + if (sis_has_two_overlays) { + /* line merge */ + setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x11); + setvideoregmask(Index_VI_Control_Misc1, 0x04, 0x04); + } + break; + } + } else { + switch (sis_displaymode) { + case DISPMODE_SINGLE1: + setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x11); + setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04); + break; + case DISPMODE_SINGLE2: + if (sis_has_two_overlays) { + setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x11); + setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04); + } else { + setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x11); + setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04); + } + break; + case DISPMODE_MIRROR: + default: + setvideoregmask(Index_VI_Control_Misc2, 0x00, 0x11); + setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04); + if (sis_has_two_overlays) { + setvideoregmask(Index_VI_Control_Misc2, 0x01, 0x11); + setvideoregmask(Index_VI_Control_Misc1, 0x00, 0x04); + } + break; + } + } +} + + +static void set_format(SISOverlayPtr pOverlay) +{ + uint8_t fmt; + + switch (pOverlay->pixelFormat) { + case IMGFMT_YV12: + case IMGFMT_I420: + fmt = 0x0c; + break; + case IMGFMT_YUY2: + fmt = 0x28; + break; + case IMGFMT_UYVY: + fmt = 0x08; + break; + case IMGFMT_RGB15: /* D[5:4] : 00 RGB555, 01 RGB 565 */ + fmt = 0x00; + break; + case IMGFMT_RGB16: + fmt = 0x10; + break; + default: + fmt = 0x00; + break; + } + setvideoregmask(Index_VI_Control_Misc0, fmt, 0x7c); +} + +static void set_colorkey(void) +{ + uint8_t r, g, b; + + b = (uint8_t) sis_grkey.ckey.blue; + g = (uint8_t) sis_grkey.ckey.green; + r = (uint8_t) sis_grkey.ckey.red; + + /* set color key mode */ + setvideoregmask(Index_VI_Key_Overlay_OP, + sis_grkey.ckey.op == CKEY_TRUE ? + VI_ROP_DestKey : VI_ROP_Always, 0x0F); + + /* set colorkey values */ + setvideoreg(Index_VI_Overlay_ColorKey_Blue_Min, (uint8_t) b); + setvideoreg(Index_VI_Overlay_ColorKey_Green_Min, (uint8_t) g); + setvideoreg(Index_VI_Overlay_ColorKey_Red_Min, (uint8_t) r); + + setvideoreg(Index_VI_Overlay_ColorKey_Blue_Max, (uint8_t) b); + setvideoreg(Index_VI_Overlay_ColorKey_Green_Max, (uint8_t) g); + setvideoreg(Index_VI_Overlay_ColorKey_Red_Max, (uint8_t) r); +} + +static void set_brightness(uint8_t brightness) +{ + setvideoreg(Index_VI_Brightness, brightness); +} + +static void set_contrast(uint8_t contrast) +{ + setvideoregmask(Index_VI_Contrast_Enh_Ctrl, contrast, 0x07); +} + +/* Next 3 functions are 310/325 series only */ + +static void set_saturation(char saturation) +{ + uint8_t temp = 0; + + if (saturation < 0) { + temp |= 0x88; + saturation = -saturation; + } + temp |= (saturation & 0x07); + temp |= ((saturation & 0x07) << 4); + + setvideoreg(Index_VI_Saturation, temp); +} + +static void set_hue(uint8_t hue) +{ + setvideoreg(Index_VI_Hue, (hue & 0x08) ? (hue ^ 0x07) : hue); +} + +#if 0 +/* JCP: not used (I don't think it's correct anyway) */ +static void set_alpha(uint8_t alpha) +{ + uint8_t data; + + data = getvideoreg(Index_VI_Key_Overlay_OP); + data &= 0x0F; + setvideoreg(Index_VI_Key_Overlay_OP, data | (alpha << 4)); +} +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/vidix/unichrome_regs.h Sun Apr 01 00:02:43 2007 +0000 @@ -0,0 +1,635 @@ +/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/via/via.h,v 1.5 2004/01/05 00:34:17 dawes Exp $ */ +/* + * Copyright 1998-2003 VIA Technologies, Inc. All Rights Reserved. + * Copyright 2001-2003 S3 Graphics, Inc. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sub license, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL + * VIA, S3 GRAPHICS, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#ifndef _VIA_H_ +#define _VIA_H_ 1 + +/* Video status flag */ + +#define VIDEO_SHOW 0x80000000 /*Video on*/ +#define VIDEO_HIDE 0x00000000 /*Video off*/ +#define VIDEO_MPEG_INUSE 0x08000000 /*Video is used with MPEG */ +#define VIDEO_HQV_INUSE 0x04000000 /*Video is used with HQV*/ +#define VIDEO_CAPTURE0_INUSE 0x02000000 /*Video is used with CAPTURE 0*/ +#define VIDEO_CAPTURE1_INUSE 0x00000000 /*Video is used with CAPTURE 1*/ +#define VIDEO_1_INUSE 0x01000000 /*Video 1 is used with software flip*/ +#define VIDEO_3_INUSE 0x00000000 /*Video 3 is used with software flip*/ +#define MPEG_USE_V1 0x00010000 /*[16] : 1:MPEG use V1, 0:MPEG use V3*/ +#define MPEG_USE_V3 0x00000000 /*[16] : 1:MPEG use V1, 0:MPEG use V3*/ +#define MPEG_USE_HQV 0x00020000 /*[17] : 1:MPEG use HQV,0:MPEG not use HQV*/ +#define MPEG_USE_HW_FLIP 0x00040000 /*[18] : 1:MPEG use H/W flip,0:MPEG use S/W flip*/ +#define MPEG_USE_SW_FLIP 0x00000000 /*[18] : 1:MPEG use H/W flip,0:MPEG use S/W flip*/ +#define CAP0_USE_V1 0x00001000 /*[12] : 1:Capture 0 use V1, 0:Capture 0 use V3*/ +#define CAP0_USE_V3 0x00000000 /*[12] : 1:Capture 0 use V1, 0:Capture 0 use V3*/ +#define CAP0_USE_HQV 0x00002000 /*[13] : 1:Capture 0 use HQV,0:Capture 0 not use HQV*/ +#define CAP0_USE_HW_FLIP 0x00004000 /*[14] : 1:Capture 0 use H/W flip,0:Capture 0 use S/W flip*/ +#define CAP0_USE_CCIR656 0x00008000 /*[15] : 1:Capture 0 use CCIR656,0:Capture 0 CCIR601*/ +#define CAP1_USE_V1 0x00000100 /*[ 8] : 1:Capture 1 use V1, 0:Capture 1 use V3*/ +#define CAP1_USE_V3 0x00000000 /*[ 8] : 1:Capture 1 use V1, 0:Capture 1 use V3*/ +#define CAP1_USE_HQV 0x00000200 /*[ 9] : 1:Capture 1 use HQV,0:Capture 1 not use HQV*/ +#define CAP1_USE_HW_FLIP 0x00000400 /*[10] : 1:Capture 1 use H/W flip,0:Capture 1 use S/W flip */ +#define SW_USE_V1 0x00000010 /*[ 4] : 1:Capture 1 use V1, 0:Capture 1 use V3 */ +#define SW_USE_V3 0x00000000 /*[ 4] : 1:Capture 1 use V1, 0:Capture 1 use V3 */ +#define SW_USE_HQV 0x00000020 /*[ 5] : 1:Capture 1 use HQV,0:Capture 1 not use HQV */ + +/* +#define VIDEO1_INUSE 0x00000010 //[ 4] : 1:Video 1 is used with S/W flip +#define VIDEO1_USE_HQV 0x00000020 //[ 5] : 1:Video 1 use HQV with S/W flip +#define VIDEO3_INUSE 0x00000001 //[ 0] : 1:Video 3 is used with S/W flip +#define VIDEO3_USE_HQV 0x00000002 //[ 1] : 1:Video 3 use HQV with S/W flip +*/ + +/* H/W registers for Video Engine */ + +/* + * bus master + */ +#define PCI_MASTER_ENABLE 0x01 +#define PCI_MASTER_SCATTER 0x00 +#define PCI_MASTER_SINGLE 0x02 +#define PCI_MASTER_GUI 0x00 +#define PCI_MASTER_VIDEO 0x04 +#define PCI_MASTER_INPUT 0x00 +#define PCI_MASTER_OUTPUT 0x08 + +/* + * video registers + */ +#define V_FLAGS 0x00 +#define V_CAP_STATUS 0x04 +#define V_FLIP_STATUS 0x04 +#define V_ALPHA_WIN_START 0x08 +#define V_ALPHA_WIN_END 0x0C +#define V_ALPHA_CONTROL 0x10 +#define V_CRT_STARTADDR 0x14 +#define V_CRT_STARTADDR_2 0x18 +#define V_ALPHA_STRIDE 0x1C +#define V_COLOR_KEY 0x20 +#define V_ALPHA_STARTADDR 0x24 +#define V_CHROMAKEY_LOW 0x28 +#define V_CHROMAKEY_HIGH 0x2C +#define V1_CONTROL 0x30 +#define V12_QWORD_PER_LINE 0x34 +#define V1_STARTADDR_1 0x38 +#define V1_STARTADDR_Y1 V1_STARTADDR_1 +#define V1_STRIDE 0x3C +#define V1_WIN_START_Y 0x40 +#define V1_WIN_START_X 0x42 +#define V1_WIN_END_Y 0x44 +#define V1_WIN_END_X 0x46 +#define V1_STARTADDR_2 0x48 +#define V1_STARTADDR_Y2 V1_STARTADDR_2 +#define V1_ZOOM_CONTROL 0x4C +#define V1_MINI_CONTROL 0x50 +#define V1_STARTADDR_0 0x54 +#define V1_STARTADDR_Y0 V1_STARTADDR_0 +#define V_FIFO_CONTROL 0x58 +#define V1_STARTADDR_3 0x5C +#define V1_STARTADDR_Y3 V1_STARTADDR_3 +#define HI_CONTROL 0x60 +#define SND_COLOR_KEY 0x64 +#define ALPHA_V3_PREFIFO_CONTROL 0x68 +#define V1_SOURCE_HEIGHT 0x6C +#define HI_TRANSPARENT_COLOR 0x70 +#define V_DISPLAY_TEMP 0x74 /* No use */ +#define ALPHA_V3_FIFO_CONTROL 0x78 +#define V3_SOURCE_WIDTH 0x7C +#define V3_COLOR_KEY 0x80 +#define V1_ColorSpaceReg_1 0x84 +#define V1_ColorSpaceReg_2 0x88 +#define V1_STARTADDR_CB0 0x8C +#define V1_OPAQUE_CONTROL 0x90 /* To be deleted */ +#define V3_OPAQUE_CONTROL 0x94 /* To be deleted */ +#define V_COMPOSE_MODE 0x98 +#define V3_STARTADDR_2 0x9C +#define V3_CONTROL 0xA0 +#define V3_STARTADDR_0 0xA4 +#define V3_STARTADDR_1 0xA8 +#define V3_STRIDE 0xAC +#define V3_WIN_START_Y 0xB0 +#define V3_WIN_START_X 0xB2 +#define V3_WIN_END_Y 0xB4 +#define V3_WIN_END_X 0xB6 +#define V3_ALPHA_QWORD_PER_LINE 0xB8 +#define V3_ZOOM_CONTROL 0xBC +#define V3_MINI_CONTROL 0xC0 +#define V3_ColorSpaceReg_1 0xC4 +#define V3_ColorSpaceReg_2 0xC8 +#define V3_DISPLAY_TEMP 0xCC /* No use */ +#define V1_STARTADDR_CB1 0xE4 +#define V1_STARTADDR_CB2 0xE8 +#define V1_STARTADDR_CB3 0xEC +#define V1_STARTADDR_CR0 0xF0 +#define V1_STARTADDR_CR1 0xF4 +#define V1_STARTADDR_CR2 0xF8 +#define V1_STARTADDR_CR3 0xFC + +/* Video Capture Engine Registers + * Capture Port 1 + */ +#define CAP0_MASKS 0x100 +#define CAP1_MASKS 0x104 +#define CAP0_CONTROL 0x110 +#define CAP0_H_RANGE 0x114 +#define CAP0_V_RANGE 0x118 +#define CAP0_SCAL_CONTROL 0x11C +#define CAP0_VBI_H_RANGE 0x120 +#define CAP0_VBI_V_RANGE 0x124 +#define CAP0_VBI_STARTADDR 0x128 +#define CAP0_VBI_STRIDE 0x12C +#define CAP0_ANCIL_COUNT 0x130 +#define CAP0_MAXCOUNT 0x134 +#define CAP0_VBIMAX_COUNT 0x138 +#define CAP0_DATA_COUNT 0x13C +#define CAP0_FB_STARTADDR0 0x140 +#define CAP0_FB_STARTADDR1 0x144 +#define CAP0_FB_STARTADDR2 0x148 +#define CAP0_STRIDE 0x150 +/* Capture Port 2 */ +#define CAP1_CONTROL 0x154 +#define CAP1_SCAL_CONTROL 0x160 +#define CAP1_VBI_H_RANGE 0x164 /*To be deleted*/ +#define CAP1_VBI_V_RANGE 0x168 /*To be deleted*/ +#define CAP1_VBI_STARTADDR 0x16C /*To be deleted*/ +#define CAP1_VBI_STRIDE 0x170 /*To be deleted*/ +#define CAP1_ANCIL_COUNT 0x174 /*To be deleted*/ +#define CAP1_MAXCOUNT 0x178 +#define CAP1_VBIMAX_COUNT 0x17C /*To be deleted*/ +#define CAP1_DATA_COUNT 0x180 +#define CAP1_FB_STARTADDR0 0x184 +#define CAP1_FB_STARTADDR1 0x188 +#define CAP1_STRIDE 0x18C + +/* SUBPICTURE Registers */ +#define SUBP_CONTROL_STRIDE 0x1C0 +#define SUBP_STARTADDR 0x1C4 +#define RAM_TABLE_CONTROL 0x1C8 +#define RAM_TABLE_READ 0x1CC + +/* HQV Registers */ +#define HQV_CONTROL 0x1D0 +#define HQV_SRC_STARTADDR_Y 0x1D4 +#define HQV_SRC_STARTADDR_U 0x1D8 +#define HQV_SRC_STARTADDR_V 0x1DC +#define HQV_SRC_FETCH_LINE 0x1E0 +#define HQV_FILTER_CONTROL 0x1E4 +#define HQV_MINIFY_CONTROL 0x1E8 +#define HQV_DST_STARTADDR0 0x1EC +#define HQV_DST_STARTADDR1 0x1F0 +#define HQV_DST_STARTADDR2 0x1FC +#define HQV_DST_STRIDE 0x1F4 +#define HQV_SRC_STRIDE 0x1F8 + + +/* + * Video command definition + */ +/* #define V_ALPHA_CONTROL 0x210 */ +#define ALPHA_WIN_EXPIRENUMBER_4 0x00040000 +#define ALPHA_WIN_CONSTANT_FACTOR_4 0x00004000 +#define ALPHA_WIN_CONSTANT_FACTOR_12 0x0000c000 +#define ALPHA_WIN_BLENDING_CONSTANT 0x00000000 +#define ALPHA_WIN_BLENDING_ALPHA 0x00000001 +#define ALPHA_WIN_BLENDING_GRAPHIC 0x00000002 +#define ALPHA_WIN_PREFIFO_THRESHOLD_12 0x000c0000 +#define ALPHA_WIN_FIFO_THRESHOLD_8 0x000c0000 +#define ALPHA_WIN_FIFO_DEPTH_16 0x00100000 + +/* V_CHROMAKEY_LOW 0x228 */ +#define V_CHROMAKEY_V3 0x80000000 + +/* V1_CONTROL 0x230 */ +#define V1_ENABLE 0x00000001 +#define V1_FULL_SCREEN 0x00000002 +#define V1_YUV422 0x00000000 +#define V1_RGB32 0x00000004 +#define V1_RGB15 0x00000008 +#define V1_RGB16 0x0000000C +#define V1_YCbCr420 0x00000010 +#define V1_COLORSPACE_SIGN 0x00000080 +#define V1_SRC_IS_FIELD_PIC 0x00000200 +#define V1_SRC_IS_FRAME_PIC 0x00000000 +#define V1_BOB_ENABLE 0x00400000 +#define V1_FIELD_BASE 0x00000000 +#define V1_FRAME_BASE 0x01000000 +#define V1_SWAP_SW 0x00000000 +#define V1_SWAP_HW_HQV 0x02000000 +#define V1_SWAP_HW_CAPTURE 0x04000000 +#define V1_SWAP_HW_MC 0x06000000 +/* #define V1_DOUBLE_BUFFERS 0x00000000 */ +/* #define V1_QUADRUPLE_BUFFERS 0x18000000 */ +#define V1_EXPIRE_NUM 0x00050000 +#define V1_EXPIRE_NUM_A 0x000a0000 +#define V1_EXPIRE_NUM_F 0x000f0000 /* jason */ +#define V1_FIFO_EXTENDED 0x00200000 +#define V1_ON_CRT 0x00000000 +#define V1_ON_SND_DISPLAY 0x80000000 +#define V1_FIFO_32V1_32V2 0x00000000 +#define V1_FIFO_48V1_32V2 0x00200000 + +/* V12_QWORD_PER_LINE 0x234 */ +#define V1_FETCH_COUNT 0x3ff00000 +#define V1_FETCHCOUNT_ALIGNMENT 0x0000000f +#define V1_FETCHCOUNT_UNIT 0x00000004 /* Doubld QWORD */ + +/* V1_STRIDE */ +#define V1_STRIDE_YMASK 0x00001fff +#define V1_STRIDE_UVMASK 0x1ff00000 + +/* V1_ZOOM_CONTROL 0x24C */ +#define V1_X_ZOOM_ENABLE 0x80000000 +#define V1_Y_ZOOM_ENABLE 0x00008000 + +/* V1_MINI_CONTROL 0x250 */ +#define V1_X_INTERPOLY 0x00000002 /* X interpolation */ +#define V1_Y_INTERPOLY 0x00000001 /* Y interpolation */ +#define V1_YCBCR_INTERPOLY 0x00000004 /* Y, Cb, Cr all interpolation */ +#define V1_X_DIV_2 0x01000000 +#define V1_X_DIV_4 0x03000000 +#define V1_X_DIV_8 0x05000000 +#define V1_X_DIV_16 0x07000000 +#define V1_Y_DIV_2 0x00010000 +#define V1_Y_DIV_4 0x00030000 +#define V1_Y_DIV_8 0x00050000 +#define V1_Y_DIV_16 0x00070000 + +/* V1_STARTADDR0 0x254 */ +#define SW_FLIP_ODD 0x08000000 + +/* V_FIFO_CONTROL 0x258 + * IA2 has 32 level FIFO for packet mode video format + * 32 level FIFO for planar mode video YV12. with extension reg 230 bit 21 enable + * 16 level FIFO for planar mode video YV12. with extension reg 230 bit 21 disable + * BCos of 128 bits. 1 level in IA2 = 2 level in VT3122 + */ +#define V1_FIFO_DEPTH12 0x0000000B +#define V1_FIFO_DEPTH16 0x0000000F +#define V1_FIFO_DEPTH32 0x0000001F +#define V1_FIFO_DEPTH48 0x0000002F +#define V1_FIFO_DEPTH64 0x0000003F +#define V1_FIFO_THRESHOLD6 0x00000600 +#define V1_FIFO_THRESHOLD8 0x00000800 +#define V1_FIFO_THRESHOLD12 0x00000C00 +#define V1_FIFO_THRESHOLD16 0x00001000 +#define V1_FIFO_THRESHOLD24 0x00001800 +#define V1_FIFO_THRESHOLD32 0x00002000 +#define V1_FIFO_THRESHOLD40 0x00002800 +#define V1_FIFO_THRESHOLD48 0x00003000 +#define V1_FIFO_THRESHOLD56 0x00003800 +#define V1_FIFO_THRESHOLD61 0x00003D00 +#define V1_FIFO_PRETHRESHOLD10 0x0A000000 +#define V1_FIFO_PRETHRESHOLD12 0x0C000000 +#define V1_FIFO_PRETHRESHOLD29 0x1d000000 +#define V1_FIFO_PRETHRESHOLD40 0x28000000 +#define V1_FIFO_PRETHRESHOLD44 0x2c000000 +#define V1_FIFO_PRETHRESHOLD56 0x38000000 +#define V1_FIFO_PRETHRESHOLD61 0x3D000000 + +/* ALPHA_V3_FIFO_CONTROL 0x278 + * IA2 has 32 level FIFO for packet mode video format + * 32 level FIFO for planar mode video YV12. with extension reg 230 bit 21 enable + * 16 level FIFO for planar mode video YV12. with extension reg 230 bit 21 disable + * 8 level FIFO for ALPHA + * BCos of 128 bits. 1 level in IA2 = 2 level in VT3122 + */ +#define V3_FIFO_DEPTH16 0x0000000F +#define V3_FIFO_DEPTH24 0x00000017 +#define V3_FIFO_DEPTH32 0x0000001F +#define V3_FIFO_DEPTH48 0x0000002F +#define V3_FIFO_DEPTH64 0x0000003F +#define V3_FIFO_THRESHOLD8 0x00000800 +#define V3_FIFO_THRESHOLD12 0x00000C00 +#define V3_FIFO_THRESHOLD16 0x00001000 +#define V3_FIFO_THRESHOLD24 0x00001800 +#define V3_FIFO_THRESHOLD32 0x00002000 +#define V3_FIFO_THRESHOLD40 0x00002800 +#define V3_FIFO_THRESHOLD48 0x00003000 +#define V3_FIFO_THRESHOLD56 0x00003800 +#define V3_FIFO_THRESHOLD61 0x00003D00 +#define V3_FIFO_PRETHRESHOLD10 0x0000000A +#define V3_FIFO_PRETHRESHOLD12 0x0000000C +#define V3_FIFO_PRETHRESHOLD29 0x0000001d +#define V3_FIFO_PRETHRESHOLD40 0x00000028 +#define V3_FIFO_PRETHRESHOLD44 0x0000002c +#define V3_FIFO_PRETHRESHOLD56 0x00000038 +#define V3_FIFO_PRETHRESHOLD61 0x0000003D +#define V3_FIFO_MASK 0x0000007F +#define ALPHA_FIFO_DEPTH8 0x00070000 +#define ALPHA_FIFO_THRESHOLD4 0x04000000 +#define ALPHA_FIFO_MASK 0xffff0000 +#define ALPHA_FIFO_PRETHRESHOLD4 0x00040000 + +/* IA2 */ +#define ColorSpaceValue_1 0x140020f2 +#define ColorSpaceValue_2 0x0a0a2c00 + +#define ColorSpaceValue_1_3123C0 0x13000DED +#define ColorSpaceValue_2_3123C0 0x13171000 + +/* For TV setting */ +#define ColorSpaceValue_1TV 0x140020f2 +#define ColorSpaceValue_2TV 0x0a0a2c00 + +/* V_COMPOSE_MODE 0x298 */ +#define SELECT_VIDEO_IF_COLOR_KEY 0x00000001 /* select video if (color key),otherwise select graphics */ +#define SELECT_VIDEO3_IF_COLOR_KEY 0x00000020 /* For 3123C0, select video3 if (color key),otherwise select graphics */ +#define SELECT_VIDEO_IF_CHROMA_KEY 0x00000002 /* 0x0000000a //select video if (chroma key ),otherwise select graphics */ +#define ALWAYS_SELECT_VIDEO 0x00000000 /* always select video,Chroma key and Color key disable */ +#define COMPOSE_V1_V3 0x00000000 /* V1 on top of V3 */ +#define COMPOSE_V3_V1 0x00100000 /* V3 on top of V1 */ +#define COMPOSE_V1_TOP 0x00000000 +#define COMPOSE_V3_TOP 0x00100000 +#define V1_COMMAND_FIRE 0x80000000 /* V1 commands fire */ +#define V3_COMMAND_FIRE 0x40000000 /* V3 commands fire */ +#define V_COMMAND_LOAD 0x20000000 /* Video register always loaded */ +#define V_COMMAND_LOAD_VBI 0x10000000 /* Video register always loaded at vbi without waiting source flip */ +#define V3_COMMAND_LOAD 0x08000000 /* CLE_C0 Video3 register always loaded */ +#define V3_COMMAND_LOAD_VBI 0x00000100 /* CLE_C0 Video3 register always loaded at vbi without waiting source flip */ +#define SECOND_DISPLAY_COLOR_KEY_ENABLE 0x00010000 + +/* V3_ZOOM_CONTROL 0x2bc */ +#define V3_X_ZOOM_ENABLE 0x80000000 +#define V3_Y_ZOOM_ENABLE 0x00008000 + +/* V3_MINI_CONTROL 0x2c0 */ +#define V3_X_INTERPOLY 0x00000002 /* X interpolation */ +#define V3_Y_INTERPOLY 0x00000001 /* Y interpolation */ +#define V3_YCBCR_INTERPOLY 0x00000004 /* Y, Cb, Cr all interpolation */ +#define V3_X_DIV_2 0x01000000 +#define V3_X_DIV_4 0x03000000 +#define V3_X_DIV_8 0x05000000 +#define V3_X_DIV_16 0x07000000 +#define V3_Y_DIV_2 0x00010000 +#define V3_Y_DIV_4 0x00030000 +#define V3_Y_DIV_8 0x00050000 +#define V3_Y_DIV_16 0x00070000 + +/* SUBP_CONTROL_STRIDE 0x3c0 */ +#define SUBP_HQV_ENABLE 0x00010000 +#define SUBP_IA44 0x00020000 +#define SUBP_AI44 0x00000000 +#define SUBP_STRIDE_MASK 0x00001fff +#define SUBP_CONTROL_MASK 0x00070000 + +/* RAM_TABLE_CONTROL 0x3c8 */ +#define RAM_TABLE_RGB_ENABLE 0x00000007 + +/* CAPTURE0_CONTROL 0x310 */ +#define C0_ENABLE 0x00000001 +#define BUFFER_2_MODE 0x00000000 +#define BUFFER_3_MODE 0x00000004 +#define BUFFER_4_MODE 0x00000006 +#define SWAP_YUYV 0x00000000 +#define SWAP_UYVY 0x00000100 +#define SWAP_YVYU 0x00000200 +#define SWAP_VYUY 0x00000300 +#define IN_601_8 0x00000000 +#define IN_656_8 0x00000010 +#define IN_601_16 0x00000020 +#define IN_656_16 0x00000030 +#define DEINTER_ODD 0x00000000 +#define DEINTER_EVEN 0x00001000 +#define DEINTER_ODD_EVEN 0x00002000 +#define DEINTER_FRAME 0x00003000 +#define VIP_1 0x00000000 +#define VIP_2 0x00000400 +#define H_FILTER_2 0x00010000 +#define H_FILTER_4 0x00020000 +#define H_FILTER_8_1331 0x00030000 +#define H_FILTER_8_12221 0x00040000 +#define VIP_ENABLE 0x00000008 +#define EN_FIELD_SIG 0x00000800 +#define VREF_INVERT 0x00100000 +#define FIELD_INPUT_INVERSE 0x00400000 +#define FIELD_INVERSE 0x40000000 + +#define C1_H_MINI_EN 0x00000800 +#define C0_H_MINI_EN 0x00000800 +#define C1_V_MINI_EN 0x04000000 +#define C0_V_MINI_EN 0x04000000 +#define C1_H_MINI_2 0x00000400 + +/* CAPTURE1_CONTROL 0x354 */ +#define C1_ENABLE 0x00000001 + +/* V3_CONTROL 0x2A0 */ +#define V3_ENABLE 0x00000001 +#define V3_FULL_SCREEN 0x00000002 +#define V3_YUV422 0x00000000 +#define V3_RGB32 0x00000004 +#define V3_RGB15 0x00000008 +#define V3_RGB16 0x0000000C +#define V3_COLORSPACE_SIGN 0x00000080 +#define V3_EXPIRE_NUM 0x00040000 +#define V3_EXPIRE_NUM_F 0x000f0000 +#define V3_BOB_ENABLE 0x00400000 +#define V3_FIELD_BASE 0x00000000 +#define V3_FRAME_BASE 0x01000000 +#define V3_SWAP_SW 0x00000000 +#define V3_SWAP_HW_HQV 0x02000000 +#define V3_FLIP_HW_CAPTURE0 0x04000000 +#define V3_FLIP_HW_CAPTURE1 0x06000000 + +/* V3_ALPHA_FETCH_COUNT 0x2B8 */ +#define V3_FETCH_COUNT 0x3ff00000 +#define ALPHA_FETCH_COUNT 0x000003ff + +/* HQV_CONTROL 0x3D0 */ +#define HQV_RGB32 0x00000000 +#define HQV_RGB16 0x20000000 +#define HQV_RGB15 0x30000000 +#define HQV_YUV422 0x80000000 +#define HQV_YUV420 0xC0000000 +#define HQV_ENABLE 0x08000000 +#define HQV_SRC_SW 0x00000000 +#define HQV_SRC_MC 0x01000000 +#define HQV_SRC_CAPTURE0 0x02000000 +#define HQV_SRC_CAPTURE1 0x03000000 +#define HQV_FLIP_EVEN 0x00000000 +#define HQV_FLIP_ODD 0x00000020 +#define HQV_SW_FLIP 0x00000010 /* Write 1 to flip HQV buffer */ +#define HQV_DEINTERLACE 0x00010000 /* First line of odd field will be repeated 3 times */ +#define HQV_FIELD_2_FRAME 0x00020000 /* Src is field. Display each line 2 times */ +#define HQV_FRAME_2_FIELD 0x00040000 /* Src is field. Display field */ +#define HQV_FRAME_UV 0x00000000 /* Src is Non-interleaved */ +#define HQV_FIELD_UV 0x00100000 /* Src is interleaved */ +#define HQV_IDLE 0x00000008 +#define HQV_FLIP_STATUS 0x00000001 +#define HQV_DOUBLE_BUFF 0x00000000 +#define HQV_TRIPLE_BUFF 0x04000000 +#define HQV_SUBPIC_FLIP 0x00008000 +#define HQV_FIFO_STATUS 0x00001000 + +/* HQV_FILTER_CONTROL 0x3E4 */ +#define HQV_H_LOWPASS_2TAP 0x00000001 +#define HQV_H_LOWPASS_4TAP 0x00000002 +#define HQV_H_LOWPASS_8TAP1 0x00000003 /* To be deleted */ +#define HQV_H_LOWPASS_8TAP2 0x00000004 /* To be deleted */ +#define HQV_H_HIGH_PASS 0x00000008 +#define HQV_H_LOW_PASS 0x00000000 +#define HQV_V_LOWPASS_2TAP 0x00010000 +#define HQV_V_LOWPASS_4TAP 0x00020000 +#define HQV_V_LOWPASS_8TAP1 0x00030000 +#define HQV_V_LOWPASS_8TAP2 0x00040000 +#define HQV_V_HIGH_PASS 0x00080000 +#define HQV_V_LOW_PASS 0x00000000 +#define HQV_H_HIPASS_F1_DEFAULT 0x00000040 +#define HQV_H_HIPASS_F2_DEFAULT 0x00000000 +#define HQV_V_HIPASS_F1_DEFAULT 0x00400000 +#define HQV_V_HIPASS_F2_DEFAULT 0x00000000 +#define HQV_H_HIPASS_F1_2TAP 0x00000050 +#define HQV_H_HIPASS_F2_2TAP 0x00000100 +#define HQV_V_HIPASS_F1_2TAP 0x00500000 +#define HQV_V_HIPASS_F2_2TAP 0x01000000 +#define HQV_H_HIPASS_F1_4TAP 0x00000060 +#define HQV_H_HIPASS_F2_4TAP 0x00000200 +#define HQV_V_HIPASS_F1_4TAP 0x00600000 +#define HQV_V_HIPASS_F2_4TAP 0x02000000 +#define HQV_H_HIPASS_F1_8TAP 0x00000080 +#define HQV_H_HIPASS_F2_8TAP 0x00000400 +#define HQV_V_HIPASS_F1_8TAP 0x00800000 +#define HQV_V_HIPASS_F2_8TAP 0x04000000 +/* IA2 NEW */ +#define HQV_V_FILTER2 0x00080000 +#define HQV_H_FILTER2 0x00000008 +#define HQV_H_TAP2_11 0x00000041 +#define HQV_H_TAP4_121 0x00000042 +#define HQV_H_TAP4_1111 0x00000401 +#define HQV_H_TAP8_1331 0x00000221 +#define HQV_H_TAP8_12221 0x00000402 +#define HQV_H_TAP16_1991 0x00000159 +#define HQV_H_TAP16_141041 0x0000026A +#define HQV_H_TAP32 0x0000015A +#define HQV_V_TAP2_11 0x00410000 +#define HQV_V_TAP4_121 0x00420000 +#define HQV_V_TAP4_1111 0x04010000 +#define HQV_V_TAP8_1331 0x02210000 +#define HQV_V_TAP8_12221 0x04020000 +#define HQV_V_TAP16_1991 0x01590000 +#define HQV_V_TAP16_141041 0x026A0000 +#define HQV_V_TAP32 0x015A0000 +#define HQV_V_FILTER_DEFAULT 0x00420000 +#define HQV_H_FILTER_DEFAULT 0x00000040 + + + + +/* HQV_MINI_CONTROL 0x3E8 */ +#define HQV_H_MINIFY_ENABLE 0x00000800 +#define HQV_V_MINIFY_ENABLE 0x08000000 +#define HQV_VDEBLOCK_FILTER 0x80000000 +#define HQV_HDEBLOCK_FILTER 0x00008000 + + +#define CHROMA_KEY_LOW 0x00FFFFFF +#define CHROMA_KEY_HIGH 0x00FFFFFF + +/* V_CAP_STATUS */ +#define V_ST_UPDATE_NOT_YET 0x00000003 +#define V1_ST_UPDATE_NOT_YET 0x00000001 +#define V3_ST_UPDATE_NOT_YET 0x00000008 + +#define VBI_STATUS 0x00000002 + +/* + * Macros for Video MMIO + */ +#ifndef V4L2 +#define VIDInB(port) *((volatile CARD8 *)(pVia->VidMapBase + (port))) +#define VIDInW(port) *((volatile CARD16 *)(pVia->VidMapBase + (port))) +#define VIDInD(port) *((volatile CARD32 *)(pVia->VidMapBase + (port))) +#define VIDOutB(port, data) *((volatile CARD8 *)(pVia->VidMapBase + (port))) = (data) +#define VIDOutW(port, data) *((volatile CARD16 *)(pVia->VidMapBase + (port))) = (data) +#define VIDOutD(port, data) *((volatile CARD32 *)(pVia->VidMapBase + (port))) = (data) +#define MPGOutD(port, data) *((volatile CARD32 *)(lpMPEGMMIO +(port))) = (data) +#define MPGInD(port) *((volatile CARD32 *)(lpMPEGMMIO +(port))) +#endif + +/* + * Macros for GE MMIO + */ +#define GEInW(port) *((volatile CARD16 *)(lpGEMMIO + (port))) +#define GEInD(port) *((volatile CARD32 *)(lpGEMMIO + (port))) +#define GEOutW(port, data) *((volatile CARD16 *)(lpGEMMIO + (port))) = (data) +#define GEOutD(port, data) *((volatile CARD32 *)(lpGEMMIO + (port))) = (data) + +/* + * MPEG 1/2 Slice Engine (at 0xC00 relative to base) + */ + +#define MPG_CONTROL 0x00 +#define MPG_CONTROL_STRUCT 0x03 +#define MPG_CONTROL_STRUCT_TOP 0x01 +#define MPG_CONTROL_STRUCT_BOTTOM 0x02 +#define MPG_CONTROL_STRUCT_FRAME 0x03 + /* Use TOP if interlaced */ +#define MPG_CONTROL_TYPE 0x3C +#define MPG_CONTROL_TYPE_I (0x01 << 2) +#define MPG_CONTROL_TYPE_B (0x02 << 2) +#define MPG_CONTROL_TYPE_P (0x03 << 3) +#define MPG_CONTROL_ALTSCAN 0x40 +#define MPG_BLOCK 0x08 /* Unsure */ +#define MPG_COMMAND 0x0C +#define MPG_DATA1 0x10 +#define MPG_DATA2 0x14 +#define MPG_DATA3 0x18 +#define MPG_DATA4 0x1C + +#define MPG_YPHYSICAL(x) (0x20 + 12*(x)) +#define MPG_CbPHYSICAL(x) (0x24 + 12*(x)) +#define MPG_CrPHYSICAL(x) (0x28 + 12*(x)) + +#define MPG_PITCH 0x50 +#define MPG_STATUS 0x54 + +#define MPG_MATRIX_IDX 0x5C +#define MPG_MATRIX_IDX_INTRA 0x00 +#define MPG_MATRIX_IDX_NON 0x01 +#define MPG_MATRIX_DATA 0x60 + +#define MPG_SLICE_CTRL_1 0x90 +#define MPG_SLICE_MBAMAX 0x2FFF +#define MPG_SLICE_PREDICTIVE_DCT 0x4000 +#define MPG_SLICE_TOP_FIRST 0x8000 +#define MPG_SLICE_MACROBLOCK_WIDTH(x) ((x)<<18) /* in 64's */ +#define MPG_SLICE_CTRL_2 0x94 +#define MPG_SLICE_CONCEAL_MVEC 0x0000001 +#define MPG_SLICE_QSCALE_TYPE 0x0000002 +#define MPG_SLICE_DCPRECISION 0x000000C +#define MPG_SLICE_MACROBQUOT 0x0FFFFF0 +#define MPG_SLICE_INTRAVLC 0x1000000 +#define MPG_SLICE_CTRL_3 0x98 +#define MPG_SLICE_FHMVR 0x0000003 +#define MPG_SLICE_FVMVR 0x000000C +#define MPG_SLICE_BHMVR 0x0000030 +#define MPG_SLICE_BVMVR 0x00000C0 +#define MPG_SLICE_SECOND_FIELD 0x0100000 +#define MPG_SLICE_RESET 0x0400000 +#define MPG_SLICE_LENGTH 0x9C +#define MPG_SLICE_DATA 0xA0 + + + +#endif /* _VIA_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/vidix/unichrome_vid.c Sun Apr 01 00:02:43 2007 +0000 @@ -0,0 +1,976 @@ +/* + Driver for VIA CLE266 Unichrome - Version 0.1.0 + + Copyright (C) 2004 by Timothy Lee + + Based on Cyberblade/i driver by Alastair M. Robison. + + Thanks to Gilles Frattini for bugfixes + + This program is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 2 of the License, or + (at your option) any later version. + + This program is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program; if not, write to the Free Software + Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + + Changes: + 2004-03-10 + Initial version + 2004-10-09 + Added Doxygen documentation (Benjamin Zores <ben@geexbox.org>) + 2004-11-08 + Added h/w revision detection (Timothy Lee <timothy.lee@siriushk.com>) + + To Do: +*/ + +#include <errno.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> +#include <inttypes.h> +#include <unistd.h> + +#include "vidix.h" +#include "fourcc.h" +#include "../libdha/libdha.h" +#include "../libdha/pci_ids.h" +#include "../libdha/pci_names.h" +#include "../config.h" + +#include "unichrome_regs.h" + +/** + * @brief Information on PCI device. + */ +pciinfo_t pci_info; + +/** + * @brief Unichrome driver colorkey settings. + */ +static vidix_grkey_t uc_grkey; + +static int frames[VID_PLAY_MAXFRAMES]; +uint8_t *vio; +uint8_t *uc_mem; +uint8_t mclk_save[3]; +uint8_t hwrev; + +#define VIA_OUT(hwregs, reg, val) *(volatile uint32_t *)((hwregs) + (reg)) = (val) +#define VIA_IN(hwregs, reg) *(volatile uint32_t *)((hwregs) + (reg)) +#define VGA_OUT8(hwregs, reg, val) *(volatile uint8_t *)((hwregs) + (reg) + 0x8000) = (val) +#define VGA_IN8(hwregs, reg) *(volatile uint8_t *)((hwregs) + (reg) + 0x8000) +#define VIDEO_OUT(hwregs, reg, val) VIA_OUT((hwregs)+0x200, reg, val) +#define VIDEO_IN(hwregs, reg) VIA_IN((hwregs)+0x200, reg) + +#define outb(val,reg) OUTPORT8(reg,val) +#define inb(reg) INPORT8(reg) + +#define ALIGN_TO(v, n) (((v) + (n-1)) & ~(n-1)) +#define UC_MAP_V1_FIFO_CONTROL(depth, pre_thr, thr) \ + (((depth)-1) | ((thr) << 8) | ((pre_thr) << 24)) + +#define VIDEOMEMORY_SIZE (8 * 1024 * 1024) +#define FRAMEBUFFER_SIZE 0x200000 +#define FRAMEBUFFER_START (VIDEOMEMORY_SIZE - FRAMEBUFFER_SIZE) + +#ifdef DEBUG_LOGFILE +FILE *logfile = 0; +#define LOGWRITE(x) {if(logfile) fprintf(logfile,x);} +#else +#define LOGWRITE(x) +#endif + +/** + * @brief Unichrome driver vidix capabilities. + */ +static vidix_capability_t uc_cap = { + "VIA CLE266 Unichrome driver", + "Timothy Lee <timothy@siriushk.com>", + TYPE_OUTPUT, + {0, 0, 0, 0}, + 4096, + 4096, + 4, + 4, + -1, + FLAG_UPSCALER | FLAG_DOWNSCALER, + VENDOR_VIA2, + -1, + {0, 0, 0, 0} +}; + +/** + * @brief list of card IDs compliant with the Unichrome driver . + */ +static unsigned short uc_card_ids[] = { + DEVICE_VIA2_VT8623_CLE266_AGP +}; + +/** + * @brief Check age of driver. + * + * @return vidix version number. + */ +unsigned int +vixGetVersion (void) +{ + return (VIDIX_VERSION); +} + +/** + * @brief Find chip index in Unichrome compliant devices list. + * + * @param chip_id PCI device ID. + * + * @returns index position in uc_card_ids if successful. + * -1 if chip_id is not a compliant chipset ID. + */ +static int +find_chip (unsigned chip_id) +{ + unsigned i; + for (i = 0; i < sizeof (uc_card_ids) / sizeof (unsigned short); i++) + { + if (chip_id == uc_card_ids[i]) + return i; + } + return -1; +} + +/** + * @brief Map hardware settings for vertical scaling. + * + * @param sh source height. + * @param dh destination height. + * @param zoom will hold vertical setting of zoom register. + * @param mini will hold vertical setting of mini register. + * + * @returns 1 if successful. + * 0 if the zooming factor is too large or small. + * + * @note Derived from VIA's V4L driver. + * See ddover.c, DDOVER_HQVCalcZoomHeight() + */ +static int +uc_ovl_map_vzoom (int sh, int dh, uint32_t * zoom, uint32_t * mini) +{ + uint32_t sh1, tmp, d; + int zoom_ok = 1; + + if (sh == dh) /* No zoom */ + { + /* Do nothing */ + } + else if (sh < dh) /* Zoom in */ + { + tmp = (sh * 0x0400) / dh; + zoom_ok = !(tmp > 0x3ff); + + *zoom |= (tmp & 0x3ff) | V1_Y_ZOOM_ENABLE; + *mini |= V1_Y_INTERPOLY | V1_YCBCR_INTERPOLY; + } + else /* sw > dh - Zoom out */ + { + /* Find a suitable divider (1 << d) = {2, 4, 8 or 16} */ + sh1 = sh; + for (d = 1; d < 5; d++) + { + sh1 >>= 1; + if (sh1 <= dh) + break; + } + if (d == 5) /* too small */ + { + d = 4; + zoom_ok = 0; + } + + *mini |= ((d << 1) - 1) << 16; /* <= {1,3,5,7} << 16 */ + + /* Add scaling */ + if (sh1 < dh) + { + tmp = (sh1 * 0x400) / dh; + *zoom |= ((tmp & 0x3ff) | V1_Y_ZOOM_ENABLE); + *mini |= V1_Y_INTERPOLY | V1_YCBCR_INTERPOLY; + } + } + + return zoom_ok; +} + +/** + * @brief Map hardware settings for horizontal scaling. + * + * @param sw source width. + * @param dw destination width. + * @param zoom will hold horizontal setting of zoom register. + * @param mini will hold horizontal setting of mini register. + * @param falign will hold fetch aligment. + * @param dcount will hold display count. + * + * @returns 1 if successful. + * 0 if the zooming factor is too large or small. + * + * @note Derived from VIA's V4L driver. + * See ddover.c, DDOVER_HQVCalcZoomWidth() and DDOver_GetDisplayCount() + */ +static int +uc_ovl_map_hzoom (int sw, int dw, uint32_t * zoom, uint32_t * mini, + int *falign, int *dcount) +{ + uint32_t tmp, sw1, d; + int md; /* Minify-divider */ + int zoom_ok = 1; + + md = 1; + *falign = 0; + + if (sw == dw) /* no zoom */ + { + /* Do nothing */ + } + else if (sw < dw) /* zoom in */ + { + tmp = (sw * 0x0800) / dw; + zoom_ok = !(tmp > 0x7ff); + + *zoom |= ((tmp & 0x7ff) << 16) | V1_X_ZOOM_ENABLE; + *mini |= V1_X_INTERPOLY; + } + else /* sw > dw - Zoom out */ + { + /* Find a suitable divider (1 << d) = {2, 4, 8 or 16} */ + sw1 = sw; + for (d = 1; d < 5; d++) + { + sw1 >>= 1; + if (sw1 <= dw) + break; + } + if (d == 5) /* too small */ + { + d = 4; + zoom_ok = 0; + } + + md = 1 << d; /* <= {2,4,8,16} */ + *falign = ((md << 1) - 1) & 0xf; /* <= {3,7,15,15} */ + *mini |= V1_X_INTERPOLY; + *mini |= ((d << 1) - 1) << 24; /* <= {1,3,5,7} << 24 */ + + /* Add scaling */ + if (sw1 < dw) + { + /* CLE bug */ + /* tmp = sw1*0x0800 / dw; */ + tmp = (sw1 - 2) * 0x0800 / dw; + *zoom |= ((tmp & 0x7ff) << 16) | V1_X_ZOOM_ENABLE; + } + } + + *dcount = sw - md; + return zoom_ok; +} + +/** + * @brief qword fetch register setting. + * + * @param format overlay pixel format. + * @param sw source width. + * + * @return qword fetch register setting + * + * @note Derived from VIA's V4L driver. See ddover.c, DDOver_GetFetch() + * @note Only call after uc_ovl_map_hzoom() + */ +static uint32_t +uc_ovl_map_qwfetch (uint32_t format, int sw) +{ + uint32_t fetch = 0; + + switch (format) + { + case IMGFMT_YV12: + case IMGFMT_I420: + fetch = ALIGN_TO (sw, 32) >> 4; + break; + case IMGFMT_UYVY: + case IMGFMT_YVYU: + case IMGFMT_YUY2: + fetch = (ALIGN_TO (sw << 1, 16) >> 4) + 1; + break; + case IMGFMT_BGR15: + case IMGFMT_BGR16: + fetch = (ALIGN_TO (sw << 1, 16) >> 4) + 1; + break; + case IMGFMT_BGR32: + fetch = (ALIGN_TO (sw << 2, 16) >> 4) + 1; + break; + default: + printf ("[unichrome] Unexpected pixelformat!"); + break; + } + + if (fetch < 4) + fetch = 4; + + return fetch; +} + +/** + * @brief Map pixel format. + * + * @param format pixel format. + * + * @return the mapped pixel format. + * + * @note Derived from VIA's V4L driver. See ddover.c, DDOver_GetV1Format() + */ +static uint32_t +uc_ovl_map_format (uint32_t format) +{ + switch (format) + { + case IMGFMT_UYVY: + case IMGFMT_YVYU: + case IMGFMT_YUY2: + return V1_COLORSPACE_SIGN | V1_YUV422; + case IMGFMT_IYUV: + return V1_COLORSPACE_SIGN | V1_YCbCr420 | V1_SWAP_SW; + case IMGFMT_YV12: + case IMGFMT_I420: + return V1_COLORSPACE_SIGN | V1_YCbCr420; + case IMGFMT_BGR15: + return V1_RGB15; + case IMGFMT_BGR16: + return V1_RGB16; + case IMGFMT_BGR32: + return V1_RGB32; + default: + printf ("[unichrome] Unexpected pixelformat!"); + return V1_YUV422; + } +} + +/** + * @brief Calculate V1 control and fifo-control register values. + * + * @param format pixel format. + * @param sw source width. + * @param hwrev CLE266 hardware revision. + * @param extfifo_on set this 1 if the extended FIFO is enabled. + * @param control will hold value for V1_CONTROL. + * @param fifo will hold value for V1_FIFO_CONTROL. + */ +static void +uc_ovl_map_v1_control (uint32_t format, int sw, + int hwrev, int extfifo_on, + uint32_t * control, uint32_t * fifo) +{ + *control = V1_BOB_ENABLE | uc_ovl_map_format (format); + + if (hwrev == 0x10) + { + *control |= V1_EXPIRE_NUM_F; + } + else + { + if (extfifo_on) + { + *control |= V1_EXPIRE_NUM_A | V1_FIFO_EXTENDED; + } + else + { + *control |= V1_EXPIRE_NUM; + } + } + + if ((format == IMGFMT_YV12) || (format == IMGFMT_I420)) + { + /* Minified video will be skewed without this workaround. */ + if (sw <= 80) /* Fetch count <= 5 */ + { + *fifo = UC_MAP_V1_FIFO_CONTROL (16, 0, 0); + } + else + { + if (hwrev == 0x10) + *fifo = UC_MAP_V1_FIFO_CONTROL (64, 56, 56); + else + *fifo = UC_MAP_V1_FIFO_CONTROL (16, 12, 8); + } + } + else + { + if (hwrev == 0x10) + { + *fifo = UC_MAP_V1_FIFO_CONTROL (64, 56, 56); /* Default rev 0x10 */ + } + else + { + if (extfifo_on) + *fifo = UC_MAP_V1_FIFO_CONTROL (48, 40, 40); + else + *fifo = UC_MAP_V1_FIFO_CONTROL (32, 29, 16); /* Default */ + } + } +} + +/** + * @brief Setup extended FIFO. + * + * @param extfifo_on pointer determining if extended fifo is enable or not. + * @param dst_w destination width. + */ +static void +uc_ovl_setup_fifo (int *extfifo_on, int dst_w) +{ + if (dst_w <= 1024) /* Disable extended FIFO */ + { + outb (0x16, 0x3c4); + outb (mclk_save[0], 0x3c5); + outb (0x17, 0x3c4); + outb (mclk_save[1], 0x3c5); + outb (0x18, 0x3c4); + outb (mclk_save[2], 0x3c5); + *extfifo_on = 0; + } + else /* Enable extended FIFO */ + { + outb (0x17, 0x3c4); + outb (0x2f, 0x3c5); + outb (0x16, 0x3c4); + outb ((mclk_save[0] & 0xf0) | 0x14, 0x3c5); + outb (0x18, 0x3c4); + outb (0x56, 0x3c5); + *extfifo_on = 1; + } +} + +static void +uc_ovl_vcmd_wait (volatile uint8_t * vio) +{ + while ((VIDEO_IN (vio, V_COMPOSE_MODE) + & (V1_COMMAND_FIRE | V3_COMMAND_FIRE))); +} + +/** + * @brief Probe hardware to find some useable chipset. + * + * @param verbose specifies verbose level. + * @param force specifies force mode : driver should ignore + * device_id (danger but useful for new devices) + * + * @returns 0 if it can handle something in PC. + * a negative error code otherwise. + */ +int +vixProbe (int verbose, int force) +{ + pciinfo_t lst[MAX_PCI_DEVICES]; + unsigned i, num_pci; + int err; + err = pci_scan (lst, &num_pci); + if (err) + { + printf ("[unichrome] Error occurred during pci scan: %s\n", + strerror (err)); + return err; + } + else + { + err = ENXIO; + for (i = 0; i < num_pci; i++) + { + if (lst[i].vendor == VENDOR_VIA2) + { + int idx; + const char *dname; + idx = find_chip (lst[i].device); + if (idx == -1) + continue; + dname = pci_device_name (VENDOR_VIA2, lst[i].device); + dname = dname ? dname : "Unknown chip"; + printf ("[unichrome] Found chip: %s\n", dname); + if ((lst[i].command & PCI_COMMAND_IO) == 0) + { + printf ("[unichrome] Device is disabled, ignoring\n"); + continue; + } + uc_cap.device_id = lst[i].device; + err = 0; + memcpy (&pci_info, &lst[i], sizeof (pciinfo_t)); + break; + } + } + } + + if (err && verbose) + printf ("[unichrome] Can't find chip\n"); + return err; +} + +/** + * @brief Initializes driver. + * + * @returns 0 if ok. + * a negative error code otherwise. + */ +int +vixInit (void) +{ + long tmp; + uc_mem = map_phys_mem (pci_info.base0, VIDEOMEMORY_SIZE); + enable_app_io (); + + outb (0x2f, 0x3c4); + tmp = inb (0x3c5) << 0x18; + vio = map_phys_mem (tmp, 0x1000); + + outb (0x16, 0x3c4); + mclk_save[0] = inb (0x3c5); + outb (0x17, 0x3c4); + mclk_save[1] = inb (0x3c5); + outb (0x18, 0x3c4); + mclk_save[2] = inb (0x3c5); + + uc_grkey.ckey.blue = 0x00; + uc_grkey.ckey.green = 0x00; + uc_grkey.ckey.red = 0x00; + + /* Detect whether we have a CLE266Ax or CLE266Cx */ + outb (0x4f, 0x3d4); + tmp = inb (0x3d5); + outb (0x4f, 0x3d4); + outb (0x55, 0x3d5); + outb (0x4f, 0x3d4); + if (0x55 == inb (0x3d5)) + { + /* Only CLE266Cx supports CR4F */ + hwrev = 0x11; + } + else + { + /* Otherwise assume to be a CLE266Ax */ + hwrev = 0x00; + } + outb (0x4f, 0x3d4); + outb (tmp, 0x3d5); + +#ifdef DEBUG_LOGFILE + logfile = fopen ("/tmp/uc_vidix.log", "w"); +#endif + return 0; +} + +/** + * @brief Destroys driver. + */ +void +vixDestroy (void) +{ +#ifdef DEBUG_LOGFILE + if (logfile) + fclose (logfile); +#endif + outb (0x16, 0x3c4); + outb (mclk_save[0], 0x3c5); + outb (0x17, 0x3c4); + outb (mclk_save[1], 0x3c5); + outb (0x18, 0x3c4); + outb (mclk_save[2], 0x3c5); + + disable_app_io (); + unmap_phys_mem (uc_mem, VIDEOMEMORY_SIZE); + unmap_phys_mem (vio, 0x1000); +} + +/** + * @brief Get chipset's hardware capabilities. + * + * @param to Pointer to the vidix_capability_t structure to be filled. + * + * @returns 0. + */ +int +vixGetCapability (vidix_capability_t * to) +{ + memcpy (to, &uc_cap, sizeof (vidix_capability_t)); + return 0; +} + +/** + * @brief Report if the video FourCC is supported by hardware. + * + * @param fourcc input image format. + * + * @returns 1 if the fourcc is supported. + * 0 otherwise. + */ +static int +is_supported_fourcc (uint32_t fourcc) +{ + switch (fourcc) + { + case IMGFMT_YV12: + case IMGFMT_I420: + case IMGFMT_UYVY: + case IMGFMT_YVYU: + case IMGFMT_YUY2: + case IMGFMT_BGR15: + case IMGFMT_BGR16: + case IMGFMT_BGR32: + return 1; + default: + return 0; + } +} + +/** + * @brief Try to configure video memory for given fourcc. + * + * @param to Pointer to the vidix_fourcc_t structure to be filled. + * + * @returns 0 if ok. + * errno otherwise. + */ +int +vixQueryFourcc (vidix_fourcc_t * to) +{ + if (is_supported_fourcc (to->fourcc)) + { + to->depth = VID_DEPTH_1BPP | VID_DEPTH_2BPP | + VID_DEPTH_4BPP | VID_DEPTH_8BPP | + VID_DEPTH_12BPP | VID_DEPTH_15BPP | + VID_DEPTH_16BPP | VID_DEPTH_24BPP | VID_DEPTH_32BPP; + to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; + return 0; + } + else + to->depth = to->flags = 0; + return ENOSYS; +} + +/** + * @brief Get the GrKeys + * + * @param grkey Pointer to the vidix_grkey_t structure to be filled by driver. + * + * @return 0. + */ +int +vixGetGrKeys (vidix_grkey_t * grkey) +{ + memcpy (grkey, &uc_grkey, sizeof (vidix_grkey_t)); + return (0); +} + +/** + * @brief Set the GrKeys + * + * @param grkey Colorkey to be set. + * + * @return 0. + */ +int +vixSetGrKeys (const vidix_grkey_t * grkey) +{ + unsigned long dwCompose = VIDEO_IN (vio, V_COMPOSE_MODE) & ~0x0f; + memcpy (&uc_grkey, grkey, sizeof (vidix_grkey_t)); + if (uc_grkey.ckey.op != CKEY_FALSE) + { + /* Set colorkey (how do I detect BPP in hardware ??) */ + unsigned long ckey; + if (1) /* Assume 16-bit graphics */ + { + ckey = (grkey->ckey.blue & 0x1f) + | ((grkey->ckey.green & 0x3f) << 5) + | ((grkey->ckey.red & 0x1f) << 11); + } + else + { + ckey = (grkey->ckey.blue) + | (grkey->ckey.green << 8) | (grkey->ckey.red << 16); + } + VIDEO_OUT (vio, V_COLOR_KEY, ckey); + dwCompose |= SELECT_VIDEO_IF_COLOR_KEY; + } + + /* Execute the changes */ + VIDEO_OUT (vio, V_COMPOSE_MODE, dwCompose | V1_COMMAND_FIRE); + return (0); +} + +/** + * @brief Unichrome driver equalizer capabilities. + */ +vidix_video_eq_t equal = { + VEQ_CAP_BRIGHTNESS | VEQ_CAP_SATURATION | VEQ_CAP_HUE, + 300, 100, 0, 0, 0, 0, 0, 0 +}; + + +/** + * @brief Get the equalizer capabilities. + * + * @param eq Pointer to the vidix_video_eq_t structure to be filled by driver. + * + * @return 0. + */ +int +vixPlaybackGetEq (vidix_video_eq_t * eq) +{ + memcpy (eq, &equal, sizeof (vidix_video_eq_t)); + return 0; +} + +/** + * @brief Set the equalizer capabilities for color correction + * + * @param eq equalizer capabilities to be set. + * + * @return 0. + */ +int +vixPlaybackSetEq (const vidix_video_eq_t * eq) +{ + return 0; +} + +/** + * @brief Y, U, V offsets. + */ +static int YOffs, UOffs, VOffs; + +/** + * @brief Configure driver for playback. Driver should prepare BES. + * + * @param info configuration description for playback. + * + * @returns 0 in case of success. + * -1 otherwise. + */ +int +vixConfigPlayback (vidix_playback_t * info) +{ + int src_w, drw_w; + int src_h, drw_h; + long base0, pitch; + int uv_size, swap_uv; + unsigned int i; + int extfifo_on; + + /* Overlay register settings */ + uint32_t win_start, win_end; + uint32_t zoom, mini; + uint32_t dcount, falign, qwfetch; + uint32_t y_start, u_start, v_start; + uint32_t v_ctrl, fifo_ctrl; + + if (!is_supported_fourcc (info->fourcc)) + return -1; + + src_w = info->src.w; + src_h = info->src.h; + + drw_w = info->dest.w; + drw_h = info->dest.h; + + /* Setup FIFO */ + uc_ovl_setup_fifo (&extfifo_on, src_w); + + /* Get image format, FIFO size, etc. */ + uc_ovl_map_v1_control (info->fourcc, src_w, hwrev, extfifo_on, + &v_ctrl, &fifo_ctrl); + + /* Setup layer window */ + win_start = (info->dest.x << 16) | info->dest.y; + win_end = ((info->dest.x + drw_w - 1) << 16) | (info->dest.y + drw_h - 1); + + /* Get scaling and data-fetch parameters */ + zoom = 0; + mini = 0; + uc_ovl_map_vzoom (src_h, drw_h, &zoom, &mini); + uc_ovl_map_hzoom (src_w, drw_w, &zoom, &mini, &falign, &dcount); + qwfetch = uc_ovl_map_qwfetch (info->fourcc, src_w); + + /* Calculate buffer sizes */ + swap_uv = 0; + switch (info->fourcc) + { + case IMGFMT_YV12: + swap_uv = 1; + case IMGFMT_I420: + case IMGFMT_UYVY: + case IMGFMT_YVYU: + pitch = ALIGN_TO (src_w, 32); + uv_size = (pitch >> 1) * (src_h >> 1); + break; + + case IMGFMT_YUY2: + case IMGFMT_BGR15: + case IMGFMT_BGR16: + pitch = ALIGN_TO (src_w << 1, 32); + uv_size = 0; + break; + + case IMGFMT_BGR32: + pitch = ALIGN_TO (src_w << 2, 32); + uv_size = 0; + break; + } + if ((src_w > 4096) || (src_h > 4096) || + (src_w < 32) || (src_h < 1) || (pitch > 0x1fff)) + { + printf ("[unichrome] Layer size out of bounds\n"); + } + + /* Calculate offsets */ + info->offset.y = 0; + info->offset.v = info->offset.y + pitch * src_h; + info->offset.u = info->offset.v + uv_size; + info->frame_size = info->offset.u + uv_size; + YOffs = info->offset.y; + UOffs = (swap_uv ? info->offset.v : info->offset.u); + VOffs = (swap_uv ? info->offset.u : info->offset.v); + + /* Assume we have 2 MB to play with */ + info->num_frames = FRAMEBUFFER_SIZE / info->frame_size; + if (info->num_frames > VID_PLAY_MAXFRAMES) + info->num_frames = VID_PLAY_MAXFRAMES; + + /* Start at 6 MB. Let's hope it's not in use. */ + base0 = FRAMEBUFFER_START; + info->dga_addr = uc_mem + base0; + + info->dest.pitch.y = 32; + info->dest.pitch.u = 32; + info->dest.pitch.v = 32; + + for (i = 0; i < info->num_frames; i++) + { + info->offsets[i] = info->frame_size * i; + frames[i] = base0 + info->offsets[i]; + } + + /* Write to the hardware */ + uc_ovl_vcmd_wait (vio); + + /* Configure diy_pitchlay parameters now */ + if (v_ctrl & V1_COLORSPACE_SIGN) + { + if (hwrev >= 0x10) + { + VIDEO_OUT (vio, V1_ColorSpaceReg_2, ColorSpaceValue_2_3123C0); + VIDEO_OUT (vio, V1_ColorSpaceReg_1, ColorSpaceValue_1_3123C0); + } + else + { + VIDEO_OUT (vio, V1_ColorSpaceReg_2, ColorSpaceValue_2); + VIDEO_OUT (vio, V1_ColorSpaceReg_1, ColorSpaceValue_1); + } + } + + VIDEO_OUT (vio, V1_CONTROL, v_ctrl); + VIDEO_OUT (vio, V_FIFO_CONTROL, fifo_ctrl); + + VIDEO_OUT (vio, V1_WIN_START_Y, win_start); + VIDEO_OUT (vio, V1_WIN_END_Y, win_end); + + VIDEO_OUT (vio, V1_SOURCE_HEIGHT, (src_h << 16) | dcount); + + VIDEO_OUT (vio, V12_QWORD_PER_LINE, qwfetch << 20); + VIDEO_OUT (vio, V1_STRIDE, pitch | ((pitch >> 1) << 16)); + + VIDEO_OUT (vio, V1_MINI_CONTROL, mini); + VIDEO_OUT (vio, V1_ZOOM_CONTROL, zoom); + + /* Configure buffer address and execute the changes now! */ + vixPlaybackFrameSelect (0); + + return 0; +} + +/** + * @brief Set playback on : driver should activate BES on this call. + * + * @return 0. + */ +int +vixPlaybackOn (void) +{ + LOGWRITE ("Enable overlay\n"); + + /* Turn on overlay */ + VIDEO_OUT (vio, V1_CONTROL, VIDEO_IN (vio, V1_CONTROL) | V1_ENABLE); + + /* Execute the changes */ + VIDEO_OUT (vio, V_COMPOSE_MODE, + VIDEO_IN (vio, V_COMPOSE_MODE) | V1_COMMAND_FIRE); + + return 0; +} + +/** + * @brief Set playback off : driver should deactivate BES on this call. + * + * @return 0. + */ +int +vixPlaybackOff (void) +{ + LOGWRITE ("Disable overlay\n"); + + uc_ovl_vcmd_wait (vio); + + /* Restore FIFO */ + VIDEO_OUT (vio, V_FIFO_CONTROL, UC_MAP_V1_FIFO_CONTROL (16, 12, 8)); + + /* Turn off overlay */ + VIDEO_OUT (vio, V1_CONTROL, VIDEO_IN (vio, V1_CONTROL) & ~V1_ENABLE); + + /* Execute the changes */ + VIDEO_OUT (vio, V_COMPOSE_MODE, + VIDEO_IN (vio, V_COMPOSE_MODE) | V1_COMMAND_FIRE); + + return 0; +} + +/** + * @brief Driver should prepare and activate corresponded frame. + * + * @param frame the frame index. + * + * @return 0. + * + * @note This function is used only for double and triple buffering + * and never used for single buffering playback. + */ +int +vixPlaybackFrameSelect (unsigned int frame) +{ + LOGWRITE ("Frame select\n"); + + uc_ovl_vcmd_wait (vio); + + /* Configure buffer address */ + VIDEO_OUT (vio, V1_STARTADDR_Y0, frames[frame] + YOffs); + VIDEO_OUT (vio, V1_STARTADDR_CB0, frames[frame] + UOffs); + VIDEO_OUT (vio, V1_STARTADDR_CR0, frames[frame] + VOffs); + + /* Execute the changes */ + VIDEO_OUT (vio, V_COMPOSE_MODE, + VIDEO_IN (vio, V_COMPOSE_MODE) | V1_COMMAND_FIRE); + + return 0; +}