Mercurial > mplayer.hg
annotate vidix/mga_vid.c @ 27559:21590d0bb4e6
The yuv->rgb tables are too small for clipping to be avoidable,
thus revert the respective optimization. The table generator code
has to be rewritten anyway one day by some volunteer because it is
not LGPL, fixing the GPL table generator thus seems like wasted time.
author | michael |
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date | Fri, 12 Sep 2008 21:25:42 +0000 |
parents | df448e1248b2 |
children | 8df85ad26746 |
rev | line source |
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22850 | 1 /* |
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2 * VIDIX driver for Matrox chipsets. |
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3 * |
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4 * Copyright (C) 2002 Alex Beregszaszi |
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5 * Original sources from Aaron Holtzman (C) 1999. |
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6 * module skeleton based on gutted agpgart module by Jeff Hartmann |
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7 * <slicer@ionet.net> |
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8 * YUY2 support and double buffering added by A'rpi/ESP-team |
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9 * brightness/contrast support by Nick Kurshev/Dariush Pietrzak (eyck) |
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10 * |
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11 * This file is part of MPlayer. |
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12 * |
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13 * MPlayer is free software; you can redistribute it and/or modify |
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14 * it under the terms of the GNU General Public License as published by |
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15 * the Free Software Foundation; either version 2 of the License, or |
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16 * (at your option) any later version. |
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17 * |
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18 * MPlayer is distributed in the hope that it will be useful, |
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19 * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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21 * GNU General Public License for more details. |
22850 | 22 * |
26719 | 23 * You should have received a copy of the GNU General Public License along |
24 * with MPlayer; if not, write to the Free Software Foundation, Inc., | |
25 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. | |
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26 */ |
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27 |
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28 /* TODO: |
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29 * - fix memory size detection (current reading pci userconfig isn't |
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30 * working as requested - returns the max avail. ram on arch?) |
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31 * - translate all non-english comments to english |
22850 | 32 */ |
33 | |
34 //#define CRTC2 | |
35 | |
36 // Set this value, if autodetection fails! (video ram size in megabytes) | |
37 //#define MGA_MEMORY_SIZE 16 | |
38 | |
39 /* No irq support in userspace implemented yet, do not enable this! */ | |
40 /* disable irq */ | |
41 #undef MGA_ALLOW_IRQ | |
42 | |
43 #define MGA_VSYNC_POS 2 | |
44 | |
45 #undef MGA_PCICONFIG_MEMDETECT | |
46 | |
47 #define MGA_DEFAULT_FRAMES 4 | |
48 | |
49 #include <errno.h> | |
50 #include <stdio.h> | |
51 #include <stdlib.h> | |
52 #include <string.h> | |
53 #include <math.h> | |
54 #include <inttypes.h> | |
55 | |
56 #include "vidix.h" | |
57 #include "fourcc.h" | |
22901 | 58 #include "dha.h" |
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59 #include "pci_ids.h" |
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60 #include "pci_names.h" |
22850 | 61 |
62 #ifdef __MINGW32__ | |
63 #define ENOTSUP 134 | |
64 #endif | |
65 | |
66 #if !defined(ENOTSUP) && defined(EOPNOTSUPP) | |
67 #define ENOTSUP EOPNOTSUPP | |
68 #endif | |
69 | |
70 /* from radeon_vid */ | |
71 #define GETREG(TYPE,PTR,OFFZ) (*((volatile TYPE*)((PTR)+(OFFZ)))) | |
72 #define SETREG(TYPE,PTR,OFFZ,VAL) (*((volatile TYPE*)((PTR)+(OFFZ))))=VAL | |
73 | |
74 #define readb(addr) GETREG(uint8_t,(uint32_t)(addr),0) | |
75 #define writeb(val,addr) SETREG(uint8_t,(uint32_t)(addr),0,val) | |
76 #define readl(addr) GETREG(uint32_t,(uint32_t)(addr),0) | |
77 #define writel(val,addr) SETREG(uint32_t,(uint32_t)(addr),0,val) | |
78 | |
79 static int mga_verbose = 0; | |
80 | |
81 /* for device detection */ | |
82 static int probed = 0; | |
83 static pciinfo_t pci_info; | |
84 | |
85 /* internal booleans */ | |
86 static int mga_vid_in_use = 0; | |
87 static int is_g400 = 0; | |
88 static int vid_src_ready = 0; | |
89 static int vid_overlay_on = 0; | |
90 | |
91 /* mapped physical addresses */ | |
92 static uint8_t *mga_mmio_base = 0; | |
93 static uint8_t *mga_mem_base = 0; | |
94 | |
95 static int mga_src_base = 0; /* YUV buffer position in video memory */ | |
96 | |
97 static uint32_t mga_ram_size = 0; /* how much megabytes videoram we have */ | |
98 | |
99 /* Graphic keys */ | |
100 static vidix_grkey_t mga_grkey; | |
101 | |
102 static int colkey_saved = 0; | |
103 static int colkey_on = 0; | |
104 static unsigned char colkey_color[4]; | |
105 static unsigned char colkey_mask[4]; | |
106 | |
107 /* for IRQ */ | |
108 static int mga_irq = -1; | |
109 | |
110 static int mga_next_frame = 0; | |
111 | |
112 static vidix_capability_t mga_cap = | |
113 { | |
114 "Matrox MGA G200/G4x0/G5x0 YUV Video", | |
115 "Aaron Holtzman, Arpad Gereoffy, Alex Beregszaszi, Nick Kurshev", | |
116 TYPE_OUTPUT, | |
117 { 0, 0, 0, 0 }, | |
118 2048, | |
119 2048, | |
120 4, | |
121 4, | |
122 -1, | |
123 FLAG_UPSCALER | FLAG_DOWNSCALER | FLAG_EQUALIZER, | |
124 VENDOR_MATROX, | |
125 -1, /* will be set in vixProbe */ | |
126 { 0, 0, 0, 0} | |
127 }; | |
128 | |
129 /* MATROX BES registers */ | |
130 typedef struct bes_registers_s | |
131 { | |
132 //BES Control | |
133 uint32_t besctl; | |
134 //BES Global control | |
135 uint32_t besglobctl; | |
136 //Luma control (brightness and contrast) | |
137 uint32_t beslumactl; | |
138 //Line pitch | |
139 uint32_t bespitch; | |
140 | |
141 //Buffer A-1 Chroma 3 plane org | |
142 uint32_t besa1c3org; | |
143 //Buffer A-1 Chroma org | |
144 uint32_t besa1corg; | |
145 //Buffer A-1 Luma org | |
146 uint32_t besa1org; | |
147 | |
148 //Buffer A-2 Chroma 3 plane org | |
149 uint32_t besa2c3org; | |
150 //Buffer A-2 Chroma org | |
151 uint32_t besa2corg; | |
152 //Buffer A-2 Luma org | |
153 uint32_t besa2org; | |
154 | |
155 //Buffer B-1 Chroma 3 plane org | |
156 uint32_t besb1c3org; | |
157 //Buffer B-1 Chroma org | |
158 uint32_t besb1corg; | |
159 //Buffer B-1 Luma org | |
160 uint32_t besb1org; | |
161 | |
162 //Buffer B-2 Chroma 3 plane org | |
163 uint32_t besb2c3org; | |
164 //Buffer B-2 Chroma org | |
165 uint32_t besb2corg; | |
166 //Buffer B-2 Luma org | |
167 uint32_t besb2org; | |
168 | |
169 //BES Horizontal coord | |
170 uint32_t beshcoord; | |
171 //BES Horizontal inverse scaling [5.14] | |
172 uint32_t beshiscal; | |
173 //BES Horizontal source start [10.14] (for scaling) | |
174 uint32_t beshsrcst; | |
175 //BES Horizontal source ending [10.14] (for scaling) | |
176 uint32_t beshsrcend; | |
177 //BES Horizontal source last | |
178 uint32_t beshsrclst; | |
179 | |
180 | |
181 //BES Vertical coord | |
182 uint32_t besvcoord; | |
183 //BES Vertical inverse scaling [5.14] | |
184 uint32_t besviscal; | |
185 //BES Field 1 vertical source last position | |
186 uint32_t besv1srclst; | |
187 //BES Field 1 weight start | |
188 uint32_t besv1wght; | |
189 //BES Field 2 vertical source last position | |
190 uint32_t besv2srclst; | |
191 //BES Field 2 weight start | |
192 uint32_t besv2wght; | |
193 | |
194 } bes_registers_t; | |
195 static bes_registers_t regs; | |
196 | |
197 #ifdef CRTC2 | |
198 typedef struct crtc2_registers_s | |
199 { | |
200 uint32_t c2ctl; | |
201 uint32_t c2datactl; | |
202 uint32_t c2misc; | |
203 uint32_t c2hparam; | |
204 uint32_t c2hsync; | |
205 uint32_t c2offset; | |
206 uint32_t c2pl2startadd0; | |
207 uint32_t c2pl2startadd1; | |
208 uint32_t c2pl3startadd0; | |
209 uint32_t c2pl3startadd1; | |
210 uint32_t c2preload; | |
211 uint32_t c2spicstartadd0; | |
212 uint32_t c2spicstartadd1; | |
213 uint32_t c2startadd0; | |
214 uint32_t c2startadd1; | |
215 uint32_t c2subpiclut; | |
216 uint32_t c2vcount; | |
217 uint32_t c2vparam; | |
218 uint32_t c2vsync; | |
219 } crtc2_registers_t; | |
220 static crtc2_registers_t cregs; | |
221 #endif | |
222 | |
223 //All register offsets are converted to word aligned offsets (32 bit) | |
224 //because we want all our register accesses to be 32 bits | |
225 #define VCOUNT 0x1e20 | |
226 | |
227 #define PALWTADD 0x3c00 // Index register for X_DATAREG port | |
228 #define X_DATAREG 0x3c0a | |
229 | |
230 #define XMULCTRL 0x19 | |
231 #define BPP_8 0x00 | |
232 #define BPP_15 0x01 | |
233 #define BPP_16 0x02 | |
234 #define BPP_24 0x03 | |
235 #define BPP_32_DIR 0x04 | |
236 #define BPP_32_PAL 0x07 | |
237 | |
238 #define XCOLMSK 0x40 | |
239 #define X_COLKEY 0x42 | |
240 #define XKEYOPMODE 0x51 | |
241 #define XCOLMSK0RED 0x52 | |
242 #define XCOLMSK0GREEN 0x53 | |
243 #define XCOLMSK0BLUE 0x54 | |
244 #define XCOLKEY0RED 0x55 | |
245 #define XCOLKEY0GREEN 0x56 | |
246 #define XCOLKEY0BLUE 0x57 | |
247 | |
248 #ifdef CRTC2 | |
249 /*CRTC2 registers*/ | |
250 #define XMISCCTRL 0x1e | |
251 #define C2CTL 0x3c10 | |
252 #define C2DATACTL 0x3c4c | |
253 #define C2MISC 0x3c44 | |
254 #define C2HPARAM 0x3c14 | |
255 #define C2HSYNC 0x3c18 | |
256 #define C2OFFSET 0x3c40 | |
257 #define C2PL2STARTADD0 0x3c30 // like BESA1CORG | |
258 #define C2PL2STARTADD1 0x3c34 // like BESA2CORG | |
259 #define C2PL3STARTADD0 0x3c38 // like BESA1C3ORG | |
260 #define C2PL3STARTADD1 0x3c3c // like BESA2C3ORG | |
261 #define C2PRELOAD 0x3c24 | |
262 #define C2SPICSTARTADD0 0x3c54 | |
263 #define C2SPICSTARTADD1 0x3c58 | |
264 #define C2STARTADD0 0x3c28 // like BESA1ORG | |
265 #define C2STARTADD1 0x3c2c // like BESA2ORG | |
266 #define C2SUBPICLUT 0x3c50 | |
267 #define C2VCOUNT 0x3c48 | |
268 #define C2VPARAM 0x3c1c | |
269 #define C2VSYNC 0x3c20 | |
270 #endif /* CRTC2 */ | |
271 | |
272 // Backend Scaler registers | |
273 #define BESCTL 0x3d20 | |
274 #define BESGLOBCTL 0x3dc0 | |
275 #define BESLUMACTL 0x3d40 | |
276 #define BESPITCH 0x3d24 | |
277 | |
278 #define BESA1C3ORG 0x3d60 | |
279 #define BESA1CORG 0x3d10 | |
280 #define BESA1ORG 0x3d00 | |
281 | |
282 #define BESA2C3ORG 0x3d64 | |
283 #define BESA2CORG 0x3d14 | |
284 #define BESA2ORG 0x3d04 | |
285 | |
286 #define BESB1C3ORG 0x3d68 | |
287 #define BESB1CORG 0x3d18 | |
288 #define BESB1ORG 0x3d08 | |
289 | |
290 #define BESB2C3ORG 0x3d6C | |
291 #define BESB2CORG 0x3d1C | |
292 #define BESB2ORG 0x3d0C | |
293 | |
294 #define BESHCOORD 0x3d28 | |
295 #define BESHISCAL 0x3d30 | |
296 #define BESHSRCEND 0x3d3C | |
297 #define BESHSRCLST 0x3d50 | |
298 #define BESHSRCST 0x3d38 | |
299 #define BESV1WGHT 0x3d48 | |
300 #define BESV2WGHT 0x3d4c | |
301 #define BESV1SRCLST 0x3d54 | |
302 #define BESV2SRCLST 0x3d58 | |
303 #define BESVISCAL 0x3d34 | |
304 #define BESVCOORD 0x3d2c | |
305 #define BESSTATUS 0x3dc4 | |
306 | |
307 #define CRTCX 0x1fd4 | |
308 #define CRTCD 0x1fd5 | |
309 #define IEN 0x1e1c | |
310 #define ICLEAR 0x1e18 | |
311 #define STATUS 0x1e14 | |
312 | |
313 | |
314 #ifdef CRTC2 | |
315 static void crtc2_frame_sel(int frame) | |
316 { | |
317 switch(frame) { | |
318 case 0: | |
319 cregs.c2pl2startadd0=regs.besa1corg; | |
320 cregs.c2pl3startadd0=regs.besa1c3org; | |
321 cregs.c2startadd0=regs.besa1org; | |
322 break; | |
323 case 1: | |
324 cregs.c2pl2startadd0=regs.besa2corg; | |
325 cregs.c2pl3startadd0=regs.besa2c3org; | |
326 cregs.c2startadd0=regs.besa2org; | |
327 break; | |
328 case 2: | |
329 cregs.c2pl2startadd0=regs.besb1corg; | |
330 cregs.c2pl3startadd0=regs.besb1c3org; | |
331 cregs.c2startadd0=regs.besb1org; | |
332 break; | |
333 case 3: | |
334 cregs.c2pl2startadd0=regs.besb2corg; | |
335 cregs.c2pl3startadd0=regs.besb2c3org; | |
336 cregs.c2startadd0=regs.besb2org; | |
337 break; | |
338 } | |
339 writel(cregs.c2startadd0, mga_mmio_base + C2STARTADD0); | |
340 writel(cregs.c2pl2startadd0, mga_mmio_base + C2PL2STARTADD0); | |
341 writel(cregs.c2pl3startadd0, mga_mmio_base + C2PL3STARTADD0); | |
342 } | |
343 #endif | |
344 | |
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345 static int mga_frame_select(unsigned int frame) |
22850 | 346 { |
347 mga_next_frame = frame; | |
348 if (mga_verbose>1) printf("[mga] frameselect: %d\n", mga_next_frame); | |
349 #if MGA_ALLOW_IRQ | |
350 if (mga_irq == -1) | |
351 #endif | |
352 { | |
353 //we don't need the vcount protection as we're only hitting | |
354 //one register (and it doesn't seem to be double buffered) | |
355 regs.besctl = (regs.besctl & ~0x07000000) + (mga_next_frame << 25); | |
356 writel( regs.besctl, mga_mmio_base + BESCTL ); | |
357 | |
358 // writel( regs.besglobctl + ((readl(mga_mmio_base + VCOUNT)+2)<<16), | |
359 writel( regs.besglobctl + (MGA_VSYNC_POS<<16), | |
360 mga_mmio_base + BESGLOBCTL); | |
361 #ifdef CRTC2 | |
362 crtc2_frame_sel(mga_next_frame); | |
363 #endif | |
364 } | |
365 | |
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366 return 0; |
22850 | 367 } |
368 | |
369 | |
370 static void mga_vid_write_regs(int restore) | |
371 { | |
372 //Make sure internal registers don't get updated until we're done | |
373 writel( (readl(mga_mmio_base + VCOUNT)-1)<<16, | |
374 mga_mmio_base + BESGLOBCTL); | |
375 | |
376 // color or coordinate keying | |
377 | |
378 if(restore && colkey_saved){ | |
379 // restore it | |
380 colkey_saved=0; | |
381 | |
382 // Set color key registers: | |
383 writeb( XKEYOPMODE, mga_mmio_base + PALWTADD); | |
384 writeb( colkey_on, mga_mmio_base + X_DATAREG); | |
385 | |
386 writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD); | |
387 writeb( colkey_color[0], mga_mmio_base + X_DATAREG); | |
388 writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD); | |
389 writeb( colkey_color[1], mga_mmio_base + X_DATAREG); | |
390 writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD); | |
391 writeb( colkey_color[2], mga_mmio_base + X_DATAREG); | |
392 writeb( X_COLKEY, mga_mmio_base + PALWTADD); | |
393 writeb( colkey_color[3], mga_mmio_base + X_DATAREG); | |
394 | |
395 writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD); | |
396 writeb( colkey_mask[0], mga_mmio_base + X_DATAREG); | |
397 writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD); | |
398 writeb( colkey_mask[1], mga_mmio_base + X_DATAREG); | |
399 writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD); | |
400 writeb( colkey_mask[2], mga_mmio_base + X_DATAREG); | |
401 writeb( XCOLMSK, mga_mmio_base + PALWTADD); | |
402 writeb( colkey_mask[3], mga_mmio_base + X_DATAREG); | |
403 | |
404 } else if(!colkey_saved){ | |
405 // save it | |
406 colkey_saved=1; | |
407 // Get color key registers: | |
408 writeb( XKEYOPMODE, mga_mmio_base + PALWTADD); | |
409 colkey_on=(unsigned char)readb(mga_mmio_base + X_DATAREG) & 1; | |
410 | |
411 writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD); | |
412 colkey_color[0]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
413 writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD); | |
414 colkey_color[1]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
415 writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD); | |
416 colkey_color[2]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
417 writeb( X_COLKEY, mga_mmio_base + PALWTADD); | |
418 colkey_color[3]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
419 | |
420 writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD); | |
421 colkey_mask[0]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
422 writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD); | |
423 colkey_mask[1]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
424 writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD); | |
425 colkey_mask[2]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
426 writeb( XCOLMSK, mga_mmio_base + PALWTADD); | |
427 colkey_mask[3]=(unsigned char)readb(mga_mmio_base + X_DATAREG); | |
428 } | |
429 | |
430 if(!restore){ | |
431 writeb( XKEYOPMODE, mga_mmio_base + PALWTADD); | |
432 writeb( mga_grkey.ckey.op == CKEY_TRUE, mga_mmio_base + X_DATAREG); | |
433 if ( mga_grkey.ckey.op == CKEY_TRUE ) | |
434 { | |
435 uint32_t r=0, g=0, b=0; | |
436 | |
437 writeb( XMULCTRL, mga_mmio_base + PALWTADD); | |
438 switch (readb (mga_mmio_base + X_DATAREG)) | |
439 { | |
440 case BPP_8: | |
441 /* Need to look up the color index, just using | |
442 color 0 for now. */ | |
443 break; | |
444 | |
445 case BPP_15: | |
446 r = mga_grkey.ckey.red >> 3; | |
447 g = mga_grkey.ckey.green >> 3; | |
448 b = mga_grkey.ckey.blue >> 3; | |
449 break; | |
450 | |
451 case BPP_16: | |
452 r = mga_grkey.ckey.red >> 3; | |
453 g = mga_grkey.ckey.green >> 2; | |
454 b = mga_grkey.ckey.blue >> 3; | |
455 break; | |
456 | |
457 case BPP_24: | |
458 case BPP_32_DIR: | |
459 case BPP_32_PAL: | |
460 r = mga_grkey.ckey.red; | |
461 g = mga_grkey.ckey.green; | |
462 b = mga_grkey.ckey.blue; | |
463 break; | |
464 } | |
465 | |
466 // Enable colorkeying | |
467 writeb( XKEYOPMODE, mga_mmio_base + PALWTADD); | |
468 writeb( 1, mga_mmio_base + X_DATAREG); | |
469 | |
470 // Disable color keying on alpha channel | |
471 writeb( XCOLMSK, mga_mmio_base + PALWTADD); | |
472 writeb( 0x00, mga_mmio_base + X_DATAREG); | |
473 writeb( X_COLKEY, mga_mmio_base + PALWTADD); | |
474 writeb( 0x00, mga_mmio_base + X_DATAREG); | |
475 | |
476 | |
477 // Set up color key registers | |
478 writeb( XCOLKEY0RED, mga_mmio_base + PALWTADD); | |
479 writeb( r, mga_mmio_base + X_DATAREG); | |
480 writeb( XCOLKEY0GREEN, mga_mmio_base + PALWTADD); | |
481 writeb( g, mga_mmio_base + X_DATAREG); | |
482 writeb( XCOLKEY0BLUE, mga_mmio_base + PALWTADD); | |
483 writeb( b, mga_mmio_base + X_DATAREG); | |
484 | |
485 // Set up color key mask registers | |
486 writeb( XCOLMSK0RED, mga_mmio_base + PALWTADD); | |
487 writeb( 0xff, mga_mmio_base + X_DATAREG); | |
488 writeb( XCOLMSK0GREEN, mga_mmio_base + PALWTADD); | |
489 writeb( 0xff, mga_mmio_base + X_DATAREG); | |
490 writeb( XCOLMSK0BLUE, mga_mmio_base + PALWTADD); | |
491 writeb( 0xff, mga_mmio_base + X_DATAREG); | |
492 } | |
493 else | |
494 { | |
495 // Disable colorkeying | |
496 writeb( XKEYOPMODE, mga_mmio_base + PALWTADD); | |
497 writeb( 0, mga_mmio_base + X_DATAREG); | |
498 } | |
499 } | |
500 | |
501 // Backend Scaler | |
502 writel( regs.besctl, mga_mmio_base + BESCTL); | |
503 if(is_g400) | |
504 writel( regs.beslumactl, mga_mmio_base + BESLUMACTL); | |
505 writel( regs.bespitch, mga_mmio_base + BESPITCH); | |
506 | |
507 writel( regs.besa1org, mga_mmio_base + BESA1ORG); | |
508 writel( regs.besa1corg, mga_mmio_base + BESA1CORG); | |
509 writel( regs.besa2org, mga_mmio_base + BESA2ORG); | |
510 writel( regs.besa2corg, mga_mmio_base + BESA2CORG); | |
511 writel( regs.besb1org, mga_mmio_base + BESB1ORG); | |
512 writel( regs.besb1corg, mga_mmio_base + BESB1CORG); | |
513 writel( regs.besb2org, mga_mmio_base + BESB2ORG); | |
514 writel( regs.besb2corg, mga_mmio_base + BESB2CORG); | |
515 if(is_g400) | |
516 { | |
517 writel( regs.besa1c3org, mga_mmio_base + BESA1C3ORG); | |
518 writel( regs.besa2c3org, mga_mmio_base + BESA2C3ORG); | |
519 writel( regs.besb1c3org, mga_mmio_base + BESB1C3ORG); | |
520 writel( regs.besb2c3org, mga_mmio_base + BESB2C3ORG); | |
521 } | |
522 | |
523 writel( regs.beshcoord, mga_mmio_base + BESHCOORD); | |
524 writel( regs.beshiscal, mga_mmio_base + BESHISCAL); | |
525 writel( regs.beshsrcst, mga_mmio_base + BESHSRCST); | |
526 writel( regs.beshsrcend, mga_mmio_base + BESHSRCEND); | |
527 writel( regs.beshsrclst, mga_mmio_base + BESHSRCLST); | |
528 | |
529 writel( regs.besvcoord, mga_mmio_base + BESVCOORD); | |
530 writel( regs.besviscal, mga_mmio_base + BESVISCAL); | |
531 | |
532 writel( regs.besv1srclst, mga_mmio_base + BESV1SRCLST); | |
533 writel( regs.besv1wght, mga_mmio_base + BESV1WGHT); | |
534 writel( regs.besv2srclst, mga_mmio_base + BESV2SRCLST); | |
535 writel( regs.besv2wght, mga_mmio_base + BESV2WGHT); | |
536 | |
537 //update the registers somewhere between 1 and 2 frames from now. | |
538 writel( regs.besglobctl + ((readl(mga_mmio_base + VCOUNT)+2)<<16), | |
539 mga_mmio_base + BESGLOBCTL); | |
540 | |
541 if (mga_verbose > 1) | |
542 { | |
543 printf("[mga] wrote BES registers\n"); | |
544 printf("[mga] BESCTL = 0x%08x\n", | |
545 readl(mga_mmio_base + BESCTL)); | |
546 printf("[mga] BESGLOBCTL = 0x%08x\n", | |
547 readl(mga_mmio_base + BESGLOBCTL)); | |
548 printf("[mga] BESSTATUS= 0x%08x\n", | |
549 readl(mga_mmio_base + BESSTATUS)); | |
550 } | |
551 #ifdef CRTC2 | |
552 writel(((readl(mga_mmio_base + C2CTL) & ~0x03e00000) + (cregs.c2ctl & 0x03e00000)), mga_mmio_base + C2CTL); | |
553 writel(((readl(mga_mmio_base + C2DATACTL) & ~0x000000ff) + (cregs.c2datactl & 0x000000ff)), mga_mmio_base + C2DATACTL); | |
554 // ctrc2 | |
555 // disable CRTC2 acording to specs | |
556 writel(cregs.c2misc, mga_mmio_base + C2MISC); | |
557 | |
558 if (mga_verbose > 1) printf("[mga] c2offset = %d\n",cregs.c2offset); | |
559 | |
560 writel(cregs.c2offset, mga_mmio_base + C2OFFSET); | |
561 writel(cregs.c2startadd0, mga_mmio_base + C2STARTADD0); | |
562 writel(cregs.c2pl2startadd0, mga_mmio_base + C2PL2STARTADD0); | |
563 writel(cregs.c2pl3startadd0, mga_mmio_base + C2PL3STARTADD0); | |
564 writel(cregs.c2spicstartadd0, mga_mmio_base + C2SPICSTARTADD0); | |
565 #endif | |
566 } | |
567 | |
568 #ifdef MGA_ALLOW_IRQ | |
569 static void enable_irq(){ | |
570 long int cc; | |
571 | |
572 cc = readl(mga_mmio_base + IEN); | |
573 | |
574 writeb( 0x11, mga_mmio_base + CRTCX); | |
575 | |
576 writeb(0x20, mga_mmio_base + CRTCD ); /* clear 0, enable off */ | |
577 writeb(0x00, mga_mmio_base + CRTCD ); /* enable on */ | |
578 writeb(0x10, mga_mmio_base + CRTCD ); /* clear = 1 */ | |
579 | |
580 writel( regs.besglobctl , mga_mmio_base + BESGLOBCTL); | |
581 | |
582 return; | |
583 } | |
584 | |
585 static void disable_irq() | |
586 { | |
587 writeb( 0x11, mga_mmio_base + CRTCX); | |
588 writeb(0x20, mga_mmio_base + CRTCD ); /* clear 0, enable off */ | |
589 | |
590 return; | |
591 } | |
592 | |
593 void mga_handle_irq(int irq, void *dev_id/*, struct pt_regs *pregs*/) { | |
594 long int cc; | |
595 | |
596 if ( irq != -1 ) { | |
597 | |
598 cc = readl(mga_mmio_base + STATUS); | |
599 if ( ! (cc & 0x10) ) return; /* vsyncpen */ | |
600 } | |
601 | |
602 regs.besctl = (regs.besctl & ~0x07000000) + (mga_next_frame << 25); | |
603 writel( regs.besctl, mga_mmio_base + BESCTL ); | |
604 | |
605 #ifdef CRTC2 | |
606 // sem pridat vyber obrazku !!!! | |
607 crtc2_frame_sel(mga_next_frame); | |
608 #endif | |
609 | |
610 if ( irq != -1 ) { | |
611 writeb( 0x11, mga_mmio_base + CRTCX); | |
612 writeb( 0, mga_mmio_base + CRTCD ); | |
613 writeb( 0x10, mga_mmio_base + CRTCD ); | |
614 } | |
615 | |
616 return; | |
617 | |
618 } | |
619 #endif /* MGA_ALLOW_IRQ */ | |
620 | |
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621 static int mga_config_playback(vidix_playback_t *config) |
22850 | 622 { |
623 unsigned int i; | |
624 int x, y, sw, sh, dw, dh; | |
625 int besleft, bestop, ifactor, ofsleft, ofstop, baseadrofs, weight, weights; | |
626 #ifdef CRTC2 | |
627 #define right_margin 0 | |
628 #define left_margin 18 | |
629 #define hsync_len 46 | |
630 #define lower_margin 10 | |
631 #define vsync_len 4 | |
632 #define upper_margin 39 | |
633 | |
634 unsigned int hdispend = (config->src.w + 31) & ~31; | |
635 unsigned int hsyncstart = hdispend + (right_margin & ~7); | |
636 unsigned int hsyncend = hsyncstart + (hsync_len & ~7); | |
637 unsigned int htotal = hsyncend + (left_margin & ~7); | |
638 unsigned int vdispend = config->src.h; | |
639 unsigned int vsyncstart = vdispend + lower_margin; | |
640 unsigned int vsyncend = vsyncstart + vsync_len; | |
641 unsigned int vtotal = vsyncend + upper_margin; | |
642 #endif | |
643 | |
644 if ((config->num_frames < 1) || (config->num_frames > 4)) | |
645 { | |
646 printf("[mga] illegal num_frames: %d, setting to %d\n", | |
647 config->num_frames, MGA_DEFAULT_FRAMES); | |
648 config->num_frames = MGA_DEFAULT_FRAMES; | |
649 } | |
650 | |
651 x = config->dest.x; | |
652 y = config->dest.y; | |
653 sw = config->src.w; | |
654 sh = config->src.h; | |
655 dw = config->dest.w; | |
656 dh = config->dest.h; | |
657 | |
658 config->dest.pitch.y=32; | |
659 config->dest.pitch.u=config->dest.pitch.v=32; | |
660 | |
661 if (mga_verbose) printf("[mga] Setting up a %dx%d-%dx%d video window (src %dx%d) format %X\n", | |
662 dw, dh, x, y, sw, sh, config->fourcc); | |
663 | |
664 if ((sw < 4) || (sh < 4) || (dw < 4) || (dh < 4)) | |
665 { | |
666 printf("[mga] Invalid src/dest dimensions\n"); | |
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667 return EINVAL; |
22850 | 668 } |
669 | |
670 //FIXME check that window is valid and inside desktop | |
671 | |
672 sw+=sw&1; | |
673 switch(config->fourcc) | |
674 { | |
675 case IMGFMT_I420: | |
676 case IMGFMT_IYUV: | |
677 case IMGFMT_YV12: | |
678 sh+=sh&1; | |
679 config->frame_size = ((sw + 31) & ~31) * sh + (((sw + 31) & ~31) * sh) / 2; | |
680 break; | |
681 case IMGFMT_YUY2: | |
682 case IMGFMT_UYVY: | |
683 config->frame_size = ((sw + 31) & ~31) * sh * 2; | |
684 break; | |
685 default: | |
686 printf("[mga] Unsupported pixel format: %x\n", config->fourcc); | |
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687 return ENOTSUP; |
22850 | 688 } |
689 | |
690 config->offsets[0] = 0; | |
691 for (i = 1; i < config->num_frames+1; i++) | |
692 config->offsets[i] = i*config->frame_size; | |
693 | |
694 config->offset.y=0; | |
695 if(config->fourcc == IMGFMT_I420 || config->fourcc == IMGFMT_IYUV) | |
696 { | |
697 config->offset.u=((sw + 31) & ~31) * sh; | |
698 config->offset.v=config->offset.u+((sw + 31) & ~31) * sh /4; | |
699 } | |
700 else { | |
701 config->offset.v=((sw + 31) & ~31) * sh; | |
702 config->offset.u=config->offset.v+((sw + 31) & ~31) * sh /4; | |
703 } | |
704 | |
705 mga_src_base = (mga_ram_size*0x100000-config->num_frames*config->frame_size); | |
706 if (mga_src_base < 0) | |
707 { | |
708 printf("[mga] not enough memory for frames!\n"); | |
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709 return EFAULT; |
22850 | 710 } |
711 mga_src_base &= (~0xFFFF); /* 64k boundary */ | |
712 if (mga_verbose > 1) printf("[mga] YUV buffer base: %#x\n", mga_src_base); | |
713 | |
714 config->dga_addr = mga_mem_base + mga_src_base; | |
715 | |
716 /* for G200 set Interleaved UV planes */ | |
717 if (!is_g400) | |
718 config->flags = VID_PLAY_INTERLEAVED_UV | INTERLEAVING_UV; | |
719 | |
720 //Setup the BES registers for a three plane 4:2:0 video source | |
721 | |
722 regs.besglobctl = 0; | |
723 | |
724 switch(config->fourcc) | |
725 { | |
726 case IMGFMT_YV12: | |
727 case IMGFMT_I420: | |
728 case IMGFMT_IYUV: | |
729 regs.besctl = 1 // BES enabled | |
730 + (0<<6) // even start polarity | |
731 + (1<<10) // x filtering enabled | |
732 + (1<<11) // y filtering enabled | |
733 + (1<<16) // chroma upsampling | |
734 + (1<<17) // 4:2:0 mode | |
735 + (1<<18); // dither enabled | |
736 break; | |
737 | |
738 case IMGFMT_YUY2: | |
739 regs.besctl = 1 // BES enabled | |
740 + (0<<6) // even start polarity | |
741 + (1<<10) // x filtering enabled | |
742 + (1<<11) // y filtering enabled | |
743 + (1<<16) // chroma upsampling | |
744 + (0<<17) // 4:2:2 mode | |
745 + (1<<18); // dither enabled | |
746 | |
747 regs.besglobctl = 0; // YUY2 format selected | |
748 break; | |
749 | |
750 case IMGFMT_UYVY: | |
751 regs.besctl = 1 // BES enabled | |
752 + (0<<6) // even start polarity | |
753 + (1<<10) // x filtering enabled | |
754 + (1<<11) // y filtering enabled | |
755 + (1<<16) // chroma upsampling | |
756 + (0<<17) // 4:2:2 mode | |
757 + (1<<18); // dither enabled | |
758 | |
759 regs.besglobctl = 1<<6; // UYVY format selected | |
760 break; | |
761 | |
762 } | |
763 | |
764 //Disable contrast and brightness control | |
765 regs.besglobctl |= (1<<5) + (1<<7); | |
766 regs.beslumactl = (0x7f << 16) + (0x80<<0); | |
767 regs.beslumactl = 0x80<<0; | |
768 | |
769 //Setup destination window boundaries | |
770 besleft = x > 0 ? x : 0; | |
771 bestop = y > 0 ? y : 0; | |
772 regs.beshcoord = (besleft<<16) + (x + dw-1); | |
773 regs.besvcoord = (bestop<<16) + (y + dh-1); | |
774 | |
775 //Setup source dimensions | |
776 regs.beshsrclst = (sw - 1) << 16; | |
777 regs.bespitch = (sw + 31) & ~31 ; | |
778 | |
779 //Setup horizontal scaling | |
780 ifactor = ((sw-1)<<14)/(dw-1); | |
781 ofsleft = besleft - x; | |
782 | |
783 regs.beshiscal = ifactor<<2; | |
784 regs.beshsrcst = (ofsleft*ifactor)<<2; | |
785 regs.beshsrcend = regs.beshsrcst + (((dw - ofsleft - 1) * ifactor) << 2); | |
786 | |
787 //Setup vertical scaling | |
788 ifactor = ((sh-1)<<14)/(dh-1); | |
789 ofstop = bestop - y; | |
790 | |
791 regs.besviscal = ifactor<<2; | |
792 | |
793 baseadrofs = ((ofstop*regs.besviscal)>>16)*regs.bespitch; | |
794 regs.besa1org = (uint32_t) mga_src_base + baseadrofs; | |
795 regs.besa2org = (uint32_t) mga_src_base + baseadrofs + 1*config->frame_size; | |
796 regs.besb1org = (uint32_t) mga_src_base + baseadrofs + 2*config->frame_size; | |
797 regs.besb2org = (uint32_t) mga_src_base + baseadrofs + 3*config->frame_size; | |
798 | |
799 if(config->fourcc==IMGFMT_YV12 | |
800 ||config->fourcc==IMGFMT_IYUV | |
801 ||config->fourcc==IMGFMT_I420 | |
802 ){ | |
803 // planar YUV frames: | |
804 if (is_g400) | |
805 baseadrofs = (((ofstop*regs.besviscal)/4)>>16)*regs.bespitch; | |
806 else | |
807 baseadrofs = (((ofstop*regs.besviscal)/2)>>16)*regs.bespitch; | |
808 | |
809 if(config->fourcc==IMGFMT_YV12){ | |
810 regs.besa1corg = (uint32_t) mga_src_base + baseadrofs + regs.bespitch * sh ; | |
811 regs.besa2corg = (uint32_t) mga_src_base + baseadrofs + 1*config->frame_size + regs.bespitch * sh; | |
812 regs.besb1corg = (uint32_t) mga_src_base + baseadrofs + 2*config->frame_size + regs.bespitch * sh; | |
813 regs.besb2corg = (uint32_t) mga_src_base + baseadrofs + 3*config->frame_size + regs.bespitch * sh; | |
814 regs.besa1c3org = regs.besa1corg + ((regs.bespitch * sh) / 4); | |
815 regs.besa2c3org = regs.besa2corg + ((regs.bespitch * sh) / 4); | |
816 regs.besb1c3org = regs.besb1corg + ((regs.bespitch * sh) / 4); | |
817 regs.besb2c3org = regs.besb2corg + ((regs.bespitch * sh) / 4); | |
818 } else { | |
819 regs.besa1c3org = (uint32_t) mga_src_base + baseadrofs + regs.bespitch * sh ; | |
820 regs.besa2c3org = (uint32_t) mga_src_base + baseadrofs + 1*config->frame_size + regs.bespitch * sh; | |
821 regs.besb1c3org = (uint32_t) mga_src_base + baseadrofs + 2*config->frame_size + regs.bespitch * sh; | |
822 regs.besb2c3org = (uint32_t) mga_src_base + baseadrofs + 3*config->frame_size + regs.bespitch * sh; | |
823 regs.besa1corg = regs.besa1c3org + ((regs.bespitch * sh) / 4); | |
824 regs.besa2corg = regs.besa2c3org + ((regs.bespitch * sh) / 4); | |
825 regs.besb1corg = regs.besb1c3org + ((regs.bespitch * sh) / 4); | |
826 regs.besb2corg = regs.besb2c3org + ((regs.bespitch * sh) / 4); | |
827 } | |
828 | |
829 } | |
830 | |
831 weight = ofstop * (regs.besviscal >> 2); | |
832 weights = weight < 0 ? 1 : 0; | |
833 regs.besv2wght = regs.besv1wght = (weights << 16) + ((weight & 0x3FFF) << 2); | |
834 regs.besv2srclst = regs.besv1srclst = sh - 1 - (((ofstop * regs.besviscal) >> 16) & 0x03FF); | |
835 | |
836 #ifdef CRTC2 | |
837 // pridat hlavni registry - tj. casovani ... | |
838 | |
839 | |
840 switch(config->fourcc){ | |
841 case IMGFMT_YV12: | |
842 case IMGFMT_I420: | |
843 case IMGFMT_IYUV: | |
844 cregs.c2ctl = 1 // CRTC2 enabled | |
845 + (1<<1) // external clock | |
846 + (0<<2) // external clock | |
847 + (1<<3) // pixel clock enable - not needed ??? | |
848 + (0<<4) // high prioryty req | |
849 + (1<<5) // high prioryty req | |
850 + (0<<6) // high prioryty req | |
851 + (1<<8) // high prioryty req max | |
852 + (0<<9) // high prioryty req max | |
853 + (0<<10) // high prioryty req max | |
854 + (0<<20) // CRTC1 to DAC | |
855 + (1<<21) // 420 mode | |
856 + (1<<22) // 420 mode | |
857 + (1<<23) // 420 mode | |
858 + (0<<24) // single chroma line for 420 mode - need to be corrected | |
859 + (0<<25) /*/ interlace mode - need to be corrected*/ | |
860 + (0<<26) // field legth polariry | |
861 + (0<<27) // field identification polariry | |
862 + (1<<28) // VIDRST detection mode | |
863 + (0<<29) // VIDRST detection mode | |
864 + (1<<30) // Horizontal counter preload | |
865 + (1<<31) // Vertical counter preload | |
866 ; | |
867 cregs.c2datactl = 1 // disable dither - propably not needed, we are already in YUV mode | |
868 + (1<<1) // Y filter enable | |
869 + (1<<2) // CbCr filter enable | |
870 + (0<<3) // subpicture enable (disabled) | |
871 + (0<<4) // NTSC enable (disabled - PAL) | |
872 + (0<<5) // C2 static subpicture enable (disabled) | |
873 + (0<<6) // C2 subpicture offset division (disabled) | |
874 + (0<<7) // 422 subformat selection ! | |
875 /* + (0<<8) // 15 bpp high alpha | |
876 + (0<<9) // 15 bpp high alpha | |
877 + (0<<10) // 15 bpp high alpha | |
878 + (0<<11) // 15 bpp high alpha | |
879 + (0<<12) // 15 bpp high alpha | |
880 + (0<<13) // 15 bpp high alpha | |
881 + (0<<14) // 15 bpp high alpha | |
882 + (0<<15) // 15 bpp high alpha | |
883 + (0<<16) // 15 bpp low alpha | |
884 + (0<<17) // 15 bpp low alpha | |
885 + (0<<18) // 15 bpp low alpha | |
886 + (0<<19) // 15 bpp low alpha | |
887 + (0<<20) // 15 bpp low alpha | |
888 + (0<<21) // 15 bpp low alpha | |
889 + (0<<22) // 15 bpp low alpha | |
890 + (0<<23) // 15 bpp low alpha | |
891 + (0<<24) // static subpicture key | |
892 + (0<<25) // static subpicture key | |
893 + (0<<26) // static subpicture key | |
894 + (0<<27) // static subpicture key | |
895 + (0<<28) // static subpicture key | |
896 */ ; | |
897 break; | |
898 | |
899 case IMGFMT_YUY2: | |
900 cregs.c2ctl = 1 // CRTC2 enabled | |
901 + (1<<1) // external clock | |
902 + (0<<2) // external clock | |
903 + (1<<3) // pixel clock enable - not needed ??? | |
904 + (0<<4) // high prioryty req - acc to spec | |
905 + (1<<5) // high prioryty req | |
906 + (0<<6) // high prioryty req | |
907 // 7 reserved | |
908 + (1<<8) // high prioryty req max | |
909 + (0<<9) // high prioryty req max | |
910 + (0<<10) // high prioryty req max | |
911 // 11-19 reserved | |
912 + (0<<20) // CRTC1 to DAC | |
913 + (1<<21) // 422 mode | |
914 + (0<<22) // 422 mode | |
915 + (1<<23) // 422 mode | |
916 + (0<<24) // single chroma line for 420 mode - need to be corrected | |
917 + (0<<25) /*/ interlace mode - need to be corrected*/ | |
918 + (0<<26) // field legth polariry | |
919 + (0<<27) // field identification polariry | |
920 + (1<<28) // VIDRST detection mode | |
921 + (0<<29) // VIDRST detection mode | |
922 + (1<<30) // Horizontal counter preload | |
923 + (1<<31) // Vertical counter preload | |
924 ; | |
925 cregs.c2datactl = 1 // disable dither - propably not needed, we are already in YUV mode | |
926 + (1<<1) // Y filter enable | |
927 + (1<<2) // CbCr filter enable | |
928 + (0<<3) // subpicture enable (disabled) | |
929 + (0<<4) // NTSC enable (disabled - PAL) | |
930 + (0<<5) // C2 static subpicture enable (disabled) | |
931 + (0<<6) // C2 subpicture offset division (disabled) | |
932 + (0<<7) // 422 subformat selection ! | |
933 /* + (0<<8) // 15 bpp high alpha | |
934 + (0<<9) // 15 bpp high alpha | |
935 + (0<<10) // 15 bpp high alpha | |
936 + (0<<11) // 15 bpp high alpha | |
937 + (0<<12) // 15 bpp high alpha | |
938 + (0<<13) // 15 bpp high alpha | |
939 + (0<<14) // 15 bpp high alpha | |
940 + (0<<15) // 15 bpp high alpha | |
941 + (0<<16) // 15 bpp low alpha | |
942 + (0<<17) // 15 bpp low alpha | |
943 + (0<<18) // 15 bpp low alpha | |
944 + (0<<19) // 15 bpp low alpha | |
945 + (0<<20) // 15 bpp low alpha | |
946 + (0<<21) // 15 bpp low alpha | |
947 + (0<<22) // 15 bpp low alpha | |
948 + (0<<23) // 15 bpp low alpha | |
949 + (0<<24) // static subpicture key | |
950 + (0<<25) // static subpicture key | |
951 + (0<<26) // static subpicture key | |
952 + (0<<27) // static subpicture key | |
953 + (0<<28) // static subpicture key | |
954 */ ; | |
955 break; | |
956 | |
957 case IMGFMT_UYVY: | |
958 cregs.c2ctl = 1 // CRTC2 enabled | |
959 + (1<<1) // external clock | |
960 + (0<<2) // external clock | |
961 + (1<<3) // pixel clock enable - not needed ??? | |
962 + (0<<4) // high prioryty req | |
963 + (1<<5) // high prioryty req | |
964 + (0<<6) // high prioryty req | |
965 + (1<<8) // high prioryty req max | |
966 + (0<<9) // high prioryty req max | |
967 + (0<<10) // high prioryty req max | |
968 + (0<<20) // CRTC1 to DAC | |
969 + (1<<21) // 422 mode | |
970 + (0<<22) // 422 mode | |
971 + (1<<23) // 422 mode | |
972 + (1<<24) // single chroma line for 420 mode - need to be corrected | |
973 + (1<<25) /*/ interlace mode - need to be corrected*/ | |
974 + (0<<26) // field legth polariry | |
975 + (0<<27) // field identification polariry | |
976 + (1<<28) // VIDRST detection mode | |
977 + (0<<29) // VIDRST detection mode | |
978 + (1<<30) // Horizontal counter preload | |
979 + (1<<31) // Vertical counter preload | |
980 ; | |
981 cregs.c2datactl = 0 // enable dither - propably not needed, we are already in YUV mode | |
982 + (1<<1) // Y filter enable | |
983 + (1<<2) // CbCr filter enable | |
984 + (0<<3) // subpicture enable (disabled) | |
985 + (0<<4) // NTSC enable (disabled - PAL) | |
986 + (0<<5) // C2 static subpicture enable (disabled) | |
987 + (0<<6) // C2 subpicture offset division (disabled) | |
988 + (1<<7) // 422 subformat selection ! | |
989 /* + (0<<8) // 15 bpp high alpha | |
990 + (0<<9) // 15 bpp high alpha | |
991 + (0<<10) // 15 bpp high alpha | |
992 + (0<<11) // 15 bpp high alpha | |
993 + (0<<12) // 15 bpp high alpha | |
994 + (0<<13) // 15 bpp high alpha | |
995 + (0<<14) // 15 bpp high alpha | |
996 + (0<<15) // 15 bpp high alpha | |
997 + (0<<16) // 15 bpp low alpha | |
998 + (0<<17) // 15 bpp low alpha | |
999 + (0<<18) // 15 bpp low alpha | |
1000 + (0<<19) // 15 bpp low alpha | |
1001 + (0<<20) // 15 bpp low alpha | |
1002 + (0<<21) // 15 bpp low alpha | |
1003 + (0<<22) // 15 bpp low alpha | |
1004 + (0<<23) // 15 bpp low alpha | |
1005 + (0<<24) // static subpicture key | |
1006 + (0<<25) // static subpicture key | |
1007 + (0<<26) // static subpicture key | |
1008 + (0<<27) // static subpicture key | |
1009 + (0<<28) // static subpicture key | |
1010 */ ; | |
1011 break; | |
1012 } | |
1013 | |
1014 cregs.c2hparam=((hdispend - 8) << 16) | (htotal - 8); | |
1015 cregs.c2hsync=((hsyncend - 8) << 16) | (hsyncstart - 8); | |
1016 | |
1017 cregs.c2misc=0 // CRTCV2 656 togg f0 | |
1018 +(0<<1) // CRTCV2 656 togg f0 | |
1019 +(0<<2) // CRTCV2 656 togg f0 | |
1020 +(0<<4) // CRTCV2 656 togg f1 | |
1021 +(0<<5) // CRTCV2 656 togg f1 | |
1022 +(0<<6) // CRTCV2 656 togg f1 | |
1023 +(0<<8) // Hsync active high | |
1024 +(0<<9) // Vsync active high | |
1025 // 16-27 c2vlinecomp - nevim co tam dat | |
1026 ; | |
1027 cregs.c2offset=(regs.bespitch << 1); | |
1028 | |
1029 cregs.c2pl2startadd0=regs.besa1corg; | |
1030 cregs.c2pl3startadd0=regs.besa1c3org; | |
1031 | |
1032 cregs.c2preload=(vsyncstart << 16) | (hsyncstart); // from | |
1033 | |
1034 cregs.c2spicstartadd0=0; // not used | |
1035 | |
1036 cregs.c2startadd0=regs.besa1org; | |
1037 | |
1038 cregs.c2subpiclut=0; //not used | |
1039 | |
1040 cregs.c2vparam=((vdispend - 1) << 16) | (vtotal - 1); | |
1041 cregs.c2vsync=((vsyncend - 1) << 16) | (vsyncstart - 1); | |
1042 #endif /* CRTC2 */ | |
1043 | |
1044 mga_vid_write_regs(0); | |
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1045 return 0; |
22850 | 1046 } |
1047 | |
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1048 static int mga_playback_on(void) |
22850 | 1049 { |
1050 if (mga_verbose) printf("[mga] playback on\n"); | |
1051 | |
1052 vid_src_ready = 1; | |
1053 if(vid_overlay_on) | |
1054 { | |
1055 regs.besctl |= 1; | |
1056 mga_vid_write_regs(0); | |
1057 } | |
1058 #ifdef MGA_ALLOW_IRQ | |
1059 if (mga_irq != -1) | |
1060 enable_irq(); | |
1061 #endif | |
1062 mga_next_frame=0; | |
1063 | |
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1064 return 0; |
22850 | 1065 } |
1066 | |
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1067 static int mga_playback_off(void) |
22850 | 1068 { |
1069 if (mga_verbose) printf("[mga] playback off\n"); | |
1070 | |
1071 vid_src_ready = 0; | |
1072 #ifdef MGA_ALLOW_IRQ | |
1073 if (mga_irq != -1) | |
1074 disable_irq(); | |
1075 #endif | |
1076 regs.besctl &= ~1; | |
1077 regs.besglobctl &= ~(1<<6); /* UYVY format selected */ | |
1078 mga_vid_write_regs(0); | |
1079 | |
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1080 return 0; |
22850 | 1081 } |
1082 | |
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1083 static int mga_probe(int verbose,int force) |
22850 | 1084 { |
1085 pciinfo_t lst[MAX_PCI_DEVICES]; | |
1086 unsigned int i, num_pci; | |
1087 int err; | |
1088 | |
1089 if (verbose) printf("[mga] probe\n"); | |
1090 | |
1091 mga_verbose = verbose; | |
1092 | |
1093 is_g400 = -1; | |
1094 | |
1095 err = pci_scan(lst, &num_pci); | |
1096 if (err) | |
1097 { | |
1098 printf("[mga] Error occurred during pci scan: %s\n", strerror(err)); | |
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1099 return err; |
22850 | 1100 } |
1101 | |
1102 if (mga_verbose) | |
1103 printf("[mga] found %d pci devices\n", num_pci); | |
1104 | |
1105 for (i = 0; i < num_pci; i++) | |
1106 { | |
1107 if (mga_verbose > 1) | |
1108 printf("[mga] pci[%d] vendor: %d device: %d\n", | |
1109 i, lst[i].vendor, lst[i].device); | |
1110 if (lst[i].vendor == VENDOR_MATROX) | |
1111 { | |
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1112 #if 0 |
22850 | 1113 if ((lst[i].command & PCI_COMMAND_IO) == 0) |
1114 { | |
1115 printf("[mga] Device is disabled, ignoring\n"); | |
1116 continue; | |
1117 } | |
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1118 #endif |
22850 | 1119 switch(lst[i].device) |
1120 { | |
1121 case DEVICE_MATROX_MGA_G550_AGP: | |
1122 printf("[mga] Found MGA G550\n"); | |
1123 is_g400 = 1; | |
1124 goto card_found; | |
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1125 case DEVICE_MATROX_MGA_G400_G450: |
22850 | 1126 printf("[mga] Found MGA G400/G450\n"); |
1127 is_g400 = 1; | |
1128 goto card_found; | |
1129 case DEVICE_MATROX_MGA_G200_AGP: | |
1130 printf("[mga] Found MGA G200 AGP\n"); | |
1131 is_g400 = 0; | |
1132 goto card_found; | |
1133 case DEVICE_MATROX_MGA_G200: | |
1134 printf("[mga] Found MGA G200 PCI\n"); | |
1135 is_g400 = 0; | |
1136 goto card_found; | |
1137 } | |
1138 } | |
1139 } | |
1140 | |
1141 if (is_g400 == -1) | |
1142 { | |
1143 if (verbose) printf("[mga] Can't find chip\n"); | |
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1144 return ENXIO; |
22850 | 1145 } |
1146 | |
1147 card_found: | |
1148 probed = 1; | |
1149 memcpy(&pci_info, &lst[i], sizeof(pciinfo_t)); | |
1150 | |
1151 mga_cap.device_id = pci_info.device; /* set device id in capabilites */ | |
1152 | |
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1153 return 0; |
22850 | 1154 } |
1155 | |
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1156 static int mga_init(void) |
22850 | 1157 { |
1158 unsigned int card_option = 0; | |
1159 int err; | |
1160 | |
1161 if (mga_verbose) printf("[mga] init\n"); | |
1162 | |
1163 mga_vid_in_use = 0; | |
1164 | |
1165 printf("Matrox MGA G200/G400/G450 YUV Video interface v2.01 (c) Aaron Holtzman & A'rpi\n"); | |
25504 | 1166 #ifdef CRTC2 |
22850 | 1167 printf("Driver compiled with TV-out (second-head) support\n"); |
1168 #endif | |
1169 | |
1170 if (!probed) | |
1171 { | |
1172 printf("[mga] driver was not probed but is being initializing\n"); | |
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1173 return EINTR; |
22850 | 1174 } |
1175 | |
1176 #ifdef MGA_PCICONFIG_MEMDETECT | |
1177 pci_config_read(pci_info.bus, pci_info.card, pci_info.func, | |
1178 0x40, 4, &card_option); | |
1179 if (mga_verbose > 1) printf("[mga] OPTION word: 0x%08X mem: 0x%02X %s\n", card_option, | |
1180 (card_option>>10)&0x17, ((card_option>>14)&1)?"SGRAM":"SDRAM"); | |
1181 #endif | |
1182 | |
1183 if (mga_ram_size) | |
1184 { | |
1185 printf("[mga] RAMSIZE forced to %d MB\n", mga_ram_size); | |
1186 } | |
1187 else | |
1188 { | |
1189 #ifdef MGA_MEMORY_SIZE | |
1190 mga_ram_size = MGA_MEMORY_SIZE; | |
1191 printf("[mga] hard-coded RAMSIZE is %d MB\n", (unsigned int) mga_ram_size); | |
1192 #else | |
1193 if (is_g400) | |
1194 { | |
1195 switch((card_option>>10)&0x17) | |
1196 { | |
1197 // SDRAM: | |
1198 case 0x00: | |
1199 case 0x04: mga_ram_size = 16; break; | |
1200 case 0x03: mga_ram_size = 32; break; | |
1201 // SGRAM: | |
1202 case 0x10: | |
1203 case 0x14: mga_ram_size = 32; break; | |
1204 case 0x11: | |
1205 case 0x12: mga_ram_size = 16; break; | |
1206 default: | |
1207 mga_ram_size = 16; | |
1208 printf("[mga] Couldn't detect RAMSIZE, assuming 16MB!\n"); | |
1209 } | |
1210 } | |
1211 else | |
1212 { | |
1213 switch((card_option>>10)&0x17) | |
1214 { | |
1215 default: mga_ram_size = 8; | |
1216 } | |
1217 } | |
1218 | |
1219 printf("[mga] detected RAMSIZE is %d MB\n", (unsigned int) mga_ram_size); | |
1220 #endif | |
1221 } | |
1222 | |
1223 if (mga_ram_size) | |
1224 { | |
1225 if ((mga_ram_size < 4) || (mga_ram_size > 64)) | |
1226 { | |
1227 printf("[mga] invalid RAMSIZE: %d MB\n", mga_ram_size); | |
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1228 return EINVAL; |
22850 | 1229 } |
1230 } | |
1231 | |
1232 if (mga_verbose > 1) printf("[mga] hardware addresses: mmio: %#x, framebuffer: %#x\n", | |
1233 pci_info.base1, pci_info.base0); | |
1234 | |
1235 mga_mmio_base = map_phys_mem(pci_info.base1,0x4000); | |
1236 mga_mem_base = map_phys_mem(pci_info.base0,mga_ram_size*1024*1024); | |
1237 | |
1238 if (mga_verbose > 1) printf("[mga] MMIO at %p, IRQ: %d, framebuffer: %p\n", | |
1239 mga_mmio_base, mga_irq, mga_mem_base); | |
1240 err = mtrr_set_type(pci_info.base0,mga_ram_size*1024*1024,MTRR_TYPE_WRCOMB); | |
1241 if(!err) printf("[mga] Set write-combining type of video memory\n"); | |
1242 #ifdef MGA_ALLOW_IRQ | |
1243 if (mga_irq != -1) | |
1244 { | |
1245 int tmp = request_irq(mga_irq, mga_handle_irq, SA_INTERRUPT | SA_SHIRQ, "Syncfb Time Base", &mga_irq); | |
1246 if (tmp) | |
1247 { | |
1248 printf("syncfb (mga): cannot register irq %d (Err: %d)\n", mga_irq, tmp); | |
1249 mga_irq=-1; | |
1250 } | |
1251 else | |
1252 { | |
1253 printf("syncfb (mga): registered irq %d\n", mga_irq); | |
1254 } | |
1255 } | |
1256 else | |
1257 { | |
1258 printf("syncfb (mga): No valid irq was found\n"); | |
1259 mga_irq=-1; | |
1260 } | |
1261 #else | |
1262 printf("syncfb (mga): IRQ disabled in mga_vid.c\n"); | |
1263 mga_irq=-1; | |
1264 #endif | |
1265 | |
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1266 return 0; |
22850 | 1267 } |
1268 | |
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1269 static void mga_destroy(void) |
22850 | 1270 { |
1271 if (mga_verbose) printf("[mga] destroy\n"); | |
1272 | |
1273 /* FIXME turn off BES */ | |
1274 vid_src_ready = 0; | |
1275 regs.besctl &= ~1; | |
1276 regs.besglobctl &= ~(1<<6); // UYVY format selected | |
1277 mga_vid_write_regs(1); | |
1278 mga_vid_in_use = 0; | |
1279 | |
1280 #ifdef MGA_ALLOW_IRQ | |
1281 if (mga_irq != -1) | |
1282 free_irq(mga_irq, &mga_irq); | |
1283 #endif | |
1284 | |
1285 if (mga_mmio_base) | |
1286 unmap_phys_mem(mga_mmio_base, 0x4000); | |
1287 if (mga_mem_base) | |
1288 unmap_phys_mem(mga_mem_base, mga_ram_size); | |
1289 return; | |
1290 } | |
1291 | |
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1292 static int mga_query_fourcc(vidix_fourcc_t *to) |
22850 | 1293 { |
1294 if (mga_verbose) printf("[mga] query fourcc (%x)\n", to->fourcc); | |
1295 | |
1296 switch(to->fourcc) | |
1297 { | |
1298 case IMGFMT_YV12: | |
1299 case IMGFMT_IYUV: | |
1300 case IMGFMT_I420: | |
1301 case IMGFMT_YUY2: | |
1302 case IMGFMT_UYVY: | |
1303 break; | |
1304 default: | |
1305 to->depth = to->flags = 0; | |
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1306 return ENOTSUP; |
22850 | 1307 } |
1308 | |
1309 to->depth = VID_DEPTH_12BPP | | |
1310 VID_DEPTH_15BPP | VID_DEPTH_16BPP | | |
1311 VID_DEPTH_24BPP | VID_DEPTH_32BPP; | |
1312 to->flags = VID_CAP_EXPAND | VID_CAP_SHRINK | VID_CAP_COLORKEY; | |
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1313 return 0; |
22850 | 1314 } |
1315 | |
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1316 static int mga_get_caps(vidix_capability_t *to) |
22850 | 1317 { |
1318 memcpy(to, &mga_cap, sizeof(vidix_capability_t)); | |
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1319 return 0; |
22850 | 1320 } |
1321 | |
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1322 static int mga_get_gkeys(vidix_grkey_t *grkey) |
22850 | 1323 { |
1324 memcpy(grkey, &mga_grkey, sizeof(vidix_grkey_t)); | |
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1325 return 0; |
22850 | 1326 } |
1327 | |
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1328 static int mga_set_gkeys(const vidix_grkey_t *grkey) |
22850 | 1329 { |
1330 memcpy(&mga_grkey, grkey, sizeof(vidix_grkey_t)); | |
1331 mga_vid_write_regs(0); | |
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1332 return 0; |
22850 | 1333 } |
1334 | |
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1335 static int mga_set_eq( const vidix_video_eq_t * eq) |
22850 | 1336 { |
1337 /* contrast and brightness control isn't supported on G200 - alex */ | |
1338 if (!is_g400) | |
1339 { | |
1340 if (mga_verbose) printf("[mga] equalizer isn't supported with G200\n"); | |
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1341 return ENOTSUP; |
22850 | 1342 } |
1343 | |
1344 // only brightness&contrast are supported: | |
1345 if(!(eq->cap & (VEQ_CAP_BRIGHTNESS|VEQ_CAP_CONTRAST))) | |
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1346 return ENOTSUP; |
22850 | 1347 |
1348 //regs.beslumactl = readl(mga_mmio_base + BESLUMACTL); | |
1349 if (eq->cap & VEQ_CAP_BRIGHTNESS) { | |
1350 regs.beslumactl &= 0xFFFF; | |
1351 regs.beslumactl |= (eq->brightness*255/2000)<<16; | |
1352 } | |
1353 if (eq->cap & VEQ_CAP_CONTRAST) { | |
1354 regs.beslumactl &= 0xFFFF0000; | |
1355 regs.beslumactl |= (128+eq->contrast*255/2000)&0xFFFF; | |
1356 } | |
1357 writel(regs.beslumactl,mga_mmio_base + BESLUMACTL); | |
1358 | |
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1359 return 0; |
22850 | 1360 } |
1361 | |
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1362 static int mga_get_eq( vidix_video_eq_t * eq) |
22850 | 1363 { |
1364 /* contrast and brightness control isn't supported on G200 - alex */ | |
1365 if (!is_g400) | |
1366 { | |
1367 if (mga_verbose) printf("[mga] equalizer isn't supported with G200\n"); | |
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1368 return ENOTSUP; |
22850 | 1369 } |
1370 | |
1371 eq->brightness = (signed short int)(regs.beslumactl >> 16) * 1000 / 128; | |
1372 eq->contrast = (signed short int)(regs.beslumactl & 0xFFFF) * 1000 / 128 - 1000; | |
1373 eq->cap = VEQ_CAP_BRIGHTNESS | VEQ_CAP_CONTRAST; | |
1374 | |
1375 printf("MGA GET_EQ: br=%d c=%d \n",eq->brightness,eq->contrast); | |
1376 | |
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1377 return 0; |
22850 | 1378 } |
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1379 |
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1380 #ifndef CRTC2 |
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1381 VDXDriver mga_drv = { |
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1382 "mga", |
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1383 #else |
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1384 VDXDriver mga_crtc2_drv = { |
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1385 "mga_crtc2", |
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1386 #endif |
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1387 NULL, |
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1388 |
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1389 .probe = mga_probe, |
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1390 .get_caps = mga_get_caps, |
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1391 .query_fourcc = mga_query_fourcc, |
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1392 .init = mga_init, |
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1393 .destroy = mga_destroy, |
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1394 .config_playback = mga_config_playback, |
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1395 .playback_on = mga_playback_on, |
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1396 .playback_off = mga_playback_off, |
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1397 .frame_sel = mga_frame_select, |
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1398 .get_eq = mga_get_eq, |
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1399 .set_eq = mga_set_eq, |
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1400 .get_gkey = mga_get_gkeys, |
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1401 .set_gkey = mga_set_gkeys, |
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1402 }; |